drivers/gpu/drm/tilcdc/tilcdc_drv.c

   1 /*
   2  * Copyright (C) 2012 Texas Instruments
   3  * Author: Rob Clark <robdclark@gmail.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 as published by
   7  * the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program.  If not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18 /* LCDC DRM driver, based on da8xx-fb */
  19
  20 #include <linux/component.h>
  21 #include <linux/pinctrl/consumer.h>
  22 #include <linux/suspend.h>
  23 #include <drm/drm_atomic.h>
  24 #include <drm/drm_atomic_helper.h>
  25
  26 #include "tilcdc_drv.h"
  27 #include "tilcdc_regs.h"
  28 #include "tilcdc_tfp410.h"
  29 #include "tilcdc_panel.h"
  30 #include "tilcdc_external.h"
  31
  32 #include "drm_fb_helper.h"
  33
  34 static LIST_HEAD(module_list);
  35
  36 void tilcdc_module_init(struct tilcdc_module *mod, const char *name,
  37                 const struct tilcdc_module_ops *funcs)
  38 {
  39         mod->name = name;
  40         mod->funcs = funcs;
  41         INIT_LIST_HEAD(&mod->list);
  42         list_add(&mod->list, &module_list);
  43 }
  44
  45 void tilcdc_module_cleanup(struct tilcdc_module *mod)
  46 {
  47         list_del(&mod->list);
  48 }
  49
  50 static struct of_device_id tilcdc_of_match[];
  51
  52 static struct drm_framebuffer *tilcdc_fb_create(struct drm_device *dev,
  53                 struct drm_file *file_priv, const struct drm_mode_fb_cmd2 *mode_cmd)
  54 {
  55         return drm_fb_cma_create(dev, file_priv, mode_cmd);
  56 }
  57
  58 static void tilcdc_fb_output_poll_changed(struct drm_device *dev)
  59 {
  60         struct tilcdc_drm_private *priv = dev->dev_private;
  61         drm_fbdev_cma_hotplug_event(priv->fbdev);
  62 }
  63
  64 int tilcdc_atomic_check(struct drm_device *dev,
  65                         struct drm_atomic_state *state)
  66 {
  67         int ret;
  68
  69         ret = drm_atomic_helper_check_modeset(dev, state);
  70         if (ret)
  71                 return ret;
  72
  73         ret = drm_atomic_helper_check_planes(dev, state);
  74         if (ret)
  75                 return ret;
  76
  77         /*
  78          * tilcdc ->atomic_check can update ->mode_changed if pixel format
  79          * changes, hence will we check modeset changes again.
  80          */
  81         ret = drm_atomic_helper_check_modeset(dev, state);
  82         if (ret)
  83                 return ret;
  84
  85         return ret;
  86 }
  87
  88 static int tilcdc_commit(struct drm_device *dev,
  89                   struct drm_atomic_state *state,
  90                   bool async)
  91 {
  92         int ret;
  93
  94         ret = drm_atomic_helper_prepare_planes(dev, state);
  95         if (ret)
  96                 return ret;
  97
  98         drm_atomic_helper_swap_state(state, true);
  99
 100         /*
 101          * Everything below can be run asynchronously without the need to grab
 102          * any modeset locks at all under one condition: It must be guaranteed
 103          * that the asynchronous work has either been cancelled (if the driver
 104          * supports it, which at least requires that the framebuffers get
 105          * cleaned up with drm_atomic_helper_cleanup_planes()) or completed
 106          * before the new state gets committed on the software side with
 107          * drm_atomic_helper_swap_state().
 108          *
 109          * This scheme allows new atomic state updates to be prepared and
 110          * checked in parallel to the asynchronous completion of the previous
 111          * update. Which is important since compositors need to figure out the
 112          * composition of the next frame right after having submitted the
 113          * current layout.
 114          */
 115
 116         /* Keep HW on while we commit the state. */
 117         pm_runtime_get_sync(dev->dev);
 118
 119         drm_atomic_helper_commit_modeset_disables(dev, state);
 120
 121         drm_atomic_helper_commit_planes(dev, state, 0);
 122
 123         drm_atomic_helper_commit_modeset_enables(dev, state);
 124
 125         /* Now HW should remain on if need becase the crtc is enabled */
 126         pm_runtime_put_sync(dev->dev);
 127
 128         drm_atomic_helper_wait_for_vblanks(dev, state);
 129
 130         drm_atomic_helper_cleanup_planes(dev, state);
 131
 132         drm_atomic_state_free(state);
 133
 134         return 0;
 135 }
 136
 137 static const struct drm_mode_config_funcs mode_config_funcs = {
 138         .fb_create = tilcdc_fb_create,
 139         .output_poll_changed = tilcdc_fb_output_poll_changed,
 140         .atomic_check = tilcdc_atomic_check,
 141         .atomic_commit = tilcdc_commit,
 142 };
 143
 144 static int modeset_init(struct drm_device *dev)
 145 {
 146         struct tilcdc_drm_private *priv = dev->dev_private;
 147         struct tilcdc_module *mod;
 148
 149         drm_mode_config_init(dev);
 150
 151         priv->crtc = tilcdc_crtc_create(dev);
 152
 153         list_for_each_entry(mod, &module_list, list) {
 154                 DBG("loading module: %s", mod->name);
 155                 mod->funcs->modeset_init(mod, dev);
 156         }
 157
 158         dev->mode_config.min_width = 0;
 159         dev->mode_config.min_height = 0;
 160         dev->mode_config.max_width = tilcdc_crtc_max_width(priv->crtc);
 161         dev->mode_config.max_height = 2048;
 162         dev->mode_config.funcs = &mode_config_funcs;
 163
 164         return 0;
 165 }
 166
 167 #ifdef CONFIG_CPU_FREQ
 168 static int cpufreq_transition(struct notifier_block *nb,
 169                                      unsigned long val, void *data)
 170 {
 171         struct tilcdc_drm_private *priv = container_of(nb,
 172                         struct tilcdc_drm_private, freq_transition);
 173         if (val == CPUFREQ_POSTCHANGE) {
 174                 if (priv->lcd_fck_rate != clk_get_rate(priv->clk)) {
 175                         priv->lcd_fck_rate = clk_get_rate(priv->clk);
 176                         tilcdc_crtc_update_clk(priv->crtc);
 177                 }
 178         }
 179
 180         return 0;
 181 }
 182 #endif
 183
 184 /*
 185  * DRM operations:
 186  */
 187
 188 static int tilcdc_unload(struct drm_device *dev)
 189 {
 190         struct tilcdc_drm_private *priv = dev->dev_private;
 191
 192         tilcdc_crtc_disable(priv->crtc);
 193
 194         tilcdc_remove_external_encoders(dev);
 195
 196         drm_fbdev_cma_fini(priv->fbdev);
 197         drm_kms_helper_poll_fini(dev);
 198         drm_mode_config_cleanup(dev);
 199         drm_vblank_cleanup(dev);
 200
 201         drm_irq_uninstall(dev);
 202
 203 #ifdef CONFIG_CPU_FREQ
 204         cpufreq_unregister_notifier(&priv->freq_transition,
 205                         CPUFREQ_TRANSITION_NOTIFIER);
 206 #endif
 207
 208         if (priv->clk)
 209                 clk_put(priv->clk);
 210
 211         if (priv->mmio)
 212                 iounmap(priv->mmio);
 213
 214         flush_workqueue(priv->wq);
 215         destroy_workqueue(priv->wq);
 216
 217         dev->dev_private = NULL;
 218
 219         pm_runtime_disable(dev->dev);
 220
 221         return 0;
 222 }
 223
 224 static int tilcdc_load(struct drm_device *dev, unsigned long flags)
 225 {
 226         struct platform_device *pdev = dev->platformdev;
 227         struct device_node *node = pdev->dev.of_node;
 228         struct tilcdc_drm_private *priv;
 229         struct tilcdc_module *mod;
 230         struct resource *res;
 231         u32 bpp = 0;
 232         int ret;
 233
 234         priv = devm_kzalloc(dev->dev, sizeof(*priv), GFP_KERNEL);
 235         if (!priv) {
 236                 dev_err(dev->dev, "failed to allocate private data\n");
 237                 return -ENOMEM;
 238         }
 239
 240         dev->dev_private = priv;
 241
 242         priv->is_componentized =
 243                 tilcdc_get_external_components(dev->dev, NULL) > 0;
 244
 245         priv->wq = alloc_ordered_workqueue("tilcdc", 0);
 246         if (!priv->wq) {
 247                 ret = -ENOMEM;
 248                 goto fail_unset_priv;
 249         }
 250
 251         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 252         if (!res) {
 253                 dev_err(dev->dev, "failed to get memory resource\n");
 254                 ret = -EINVAL;
 255                 goto fail_free_wq;
 256         }
 257
 258         priv->mmio = ioremap_nocache(res->start, resource_size(res));
 259         if (!priv->mmio) {
 260                 dev_err(dev->dev, "failed to ioremap\n");
 261                 ret = -ENOMEM;
 262                 goto fail_free_wq;
 263         }
 264
 265         priv->clk = clk_get(dev->dev, "fck");
 266         if (IS_ERR(priv->clk)) {
 267                 dev_err(dev->dev, "failed to get functional clock\n");
 268                 ret = -ENODEV;
 269                 goto fail_iounmap;
 270         }
 271
 272 #ifdef CONFIG_CPU_FREQ
 273         priv->lcd_fck_rate = clk_get_rate(priv->clk);
 274         priv->freq_transition.notifier_call = cpufreq_transition;
 275         ret = cpufreq_register_notifier(&priv->freq_transition,
 276                         CPUFREQ_TRANSITION_NOTIFIER);
 277         if (ret) {
 278                 dev_err(dev->dev, "failed to register cpufreq notifier\n");
 279                 goto fail_put_clk;
 280         }
 281 #endif
 282
 283         if (of_property_read_u32(node, "max-bandwidth", &priv->max_bandwidth))
 284                 priv->max_bandwidth = TILCDC_DEFAULT_MAX_BANDWIDTH;
 285
 286         DBG("Maximum Bandwidth Value %d", priv->max_bandwidth);
 287
 288         if (of_property_read_u32(node, "ti,max-width", &priv->max_width))
 289                 priv->max_width = TILCDC_DEFAULT_MAX_WIDTH;
 290
 291         DBG("Maximum Horizontal Pixel Width Value %dpixels", priv->max_width);
 292
 293         if (of_property_read_u32(node, "ti,max-pixelclock",
 294                                         &priv->max_pixelclock))
 295                 priv->max_pixelclock = TILCDC_DEFAULT_MAX_PIXELCLOCK;
 296
 297         DBG("Maximum Pixel Clock Value %dKHz", priv->max_pixelclock);
 298
 299         pm_runtime_enable(dev->dev);
 300
 301         /* Determine LCD IP Version */
 302         pm_runtime_get_sync(dev->dev);
 303         switch (tilcdc_read(dev, LCDC_PID_REG)) {
 304         case 0x4c100102:
 305                 priv->rev = 1;
 306                 break;
 307         case 0x4f200800:
 308         case 0x4f201000:
 309                 priv->rev = 2;
 310                 break;
 311         default:
 312                 dev_warn(dev->dev, "Unknown PID Reg value 0x%08x, "
 313                                 "defaulting to LCD revision 1\n",
 314                                 tilcdc_read(dev, LCDC_PID_REG));
 315                 priv->rev = 1;
 316                 break;
 317         }
 318
 319         pm_runtime_put_sync(dev->dev);
 320
 321         ret = modeset_init(dev);
 322         if (ret < 0) {
 323                 dev_err(dev->dev, "failed to initialize mode setting\n");
 324                 goto fail_cpufreq_unregister;
 325         }
 326
 327         platform_set_drvdata(pdev, dev);
 328
 329         if (priv->is_componentized) {
 330                 ret = component_bind_all(dev->dev, dev);
 331                 if (ret < 0)
 332                         goto fail_mode_config_cleanup;
 333
 334                 ret = tilcdc_add_external_encoders(dev, &bpp);
 335                 if (ret < 0)
 336                         goto fail_component_cleanup;
 337         }
 338
 339         if ((priv->num_encoders == 0) || (priv->num_connectors == 0)) {
 340                 dev_err(dev->dev, "no encoders/connectors found\n");
 341                 ret = -ENXIO;
 342                 goto fail_external_cleanup;
 343         }
 344
 345         ret = drm_vblank_init(dev, 1);
 346         if (ret < 0) {
 347                 dev_err(dev->dev, "failed to initialize vblank\n");
 348                 goto fail_external_cleanup;
 349         }
 350
 351         ret = drm_irq_install(dev, platform_get_irq(dev->platformdev, 0));
 352         if (ret < 0) {
 353                 dev_err(dev->dev, "failed to install IRQ handler\n");
 354                 goto fail_vblank_cleanup;
 355         }
 356
 357         list_for_each_entry(mod, &module_list, list) {
 358                 DBG("%s: preferred_bpp: %d", mod->name, mod->preferred_bpp);
 359                 bpp = mod->preferred_bpp;
 360                 if (bpp > 0)
 361                         break;
 362         }
 363
 364         drm_mode_config_reset(dev);
 365
 366         priv->fbdev = drm_fbdev_cma_init(dev, bpp,
 367                         dev->mode_config.num_crtc,
 368                         dev->mode_config.num_connector);
 369         if (IS_ERR(priv->fbdev)) {
 370                 ret = PTR_ERR(priv->fbdev);
 371                 goto fail_irq_uninstall;
 372         }
 373
 374         drm_kms_helper_poll_init(dev);
 375
 376         return 0;
 377
 378 fail_irq_uninstall:
 379         drm_irq_uninstall(dev);
 380
 381 fail_vblank_cleanup:
 382         drm_vblank_cleanup(dev);
 383
 384 fail_mode_config_cleanup:
 385         drm_mode_config_cleanup(dev);
 386
 387 fail_component_cleanup:
 388         if (priv->is_componentized)
 389                 component_unbind_all(dev->dev, dev);
 390
 391 fail_external_cleanup:
 392         tilcdc_remove_external_encoders(dev);
 393
 394 fail_cpufreq_unregister:
 395         pm_runtime_disable(dev->dev);
 396 #ifdef CONFIG_CPU_FREQ
 397         cpufreq_unregister_notifier(&priv->freq_transition,
 398                         CPUFREQ_TRANSITION_NOTIFIER);
 399
 400 fail_put_clk:
 401 #endif
 402         clk_put(priv->clk);
 403
 404 fail_iounmap:
 405         iounmap(priv->mmio);
 406
 407 fail_free_wq:
 408         flush_workqueue(priv->wq);
 409         destroy_workqueue(priv->wq);
 410
 411 fail_unset_priv:
 412         dev->dev_private = NULL;
 413
 414         return ret;
 415 }
 416
 417 static void tilcdc_lastclose(struct drm_device *dev)
 418 {
 419         struct tilcdc_drm_private *priv = dev->dev_private;
 420         drm_fbdev_cma_restore_mode(priv->fbdev);
 421 }
 422
 423 static irqreturn_t tilcdc_irq(int irq, void *arg)
 424 {
 425         struct drm_device *dev = arg;
 426         struct tilcdc_drm_private *priv = dev->dev_private;
 427         return tilcdc_crtc_irq(priv->crtc);
 428 }
 429
 430 static int tilcdc_enable_vblank(struct drm_device *dev, unsigned int pipe)
 431 {
 432         return 0;
 433 }
 434
 435 static void tilcdc_disable_vblank(struct drm_device *dev, unsigned int pipe)
 436 {
 437         return;
 438 }
 439
 440 #if defined(CONFIG_DEBUG_FS)
 441 static const struct {
 442         const char *name;
 443         uint8_t  rev;
 444         uint8_t  save;
 445         uint32_t reg;
 446 } registers[] =         {
 447 #define REG(rev, save, reg) { #reg, rev, save, reg }
 448                 /* exists in revision 1: */
 449                 REG(1, false, LCDC_PID_REG),
 450                 REG(1, true,  LCDC_CTRL_REG),
 451                 REG(1, false, LCDC_STAT_REG),
 452                 REG(1, true,  LCDC_RASTER_CTRL_REG),
 453                 REG(1, true,  LCDC_RASTER_TIMING_0_REG),
 454                 REG(1, true,  LCDC_RASTER_TIMING_1_REG),
 455                 REG(1, true,  LCDC_RASTER_TIMING_2_REG),
 456                 REG(1, true,  LCDC_DMA_CTRL_REG),
 457                 REG(1, true,  LCDC_DMA_FB_BASE_ADDR_0_REG),
 458                 REG(1, true,  LCDC_DMA_FB_CEILING_ADDR_0_REG),
 459                 REG(1, true,  LCDC_DMA_FB_BASE_ADDR_1_REG),
 460                 REG(1, true,  LCDC_DMA_FB_CEILING_ADDR_1_REG),
 461                 /* new in revision 2: */
 462                 REG(2, false, LCDC_RAW_STAT_REG),
 463                 REG(2, false, LCDC_MASKED_STAT_REG),
 464                 REG(2, true, LCDC_INT_ENABLE_SET_REG),
 465                 REG(2, false, LCDC_INT_ENABLE_CLR_REG),
 466                 REG(2, false, LCDC_END_OF_INT_IND_REG),
 467                 REG(2, true,  LCDC_CLK_ENABLE_REG),
 468 #undef REG
 469 };
 470
 471 #endif
 472
 473 #ifdef CONFIG_DEBUG_FS
 474 static int tilcdc_regs_show(struct seq_file *m, void *arg)
 475 {
 476         struct drm_info_node *node = (struct drm_info_node *) m->private;
 477         struct drm_device *dev = node->minor->dev;
 478         struct tilcdc_drm_private *priv = dev->dev_private;
 479         unsigned i;
 480
 481         pm_runtime_get_sync(dev->dev);
 482
 483         seq_printf(m, "revision: %d\n", priv->rev);
 484
 485         for (i = 0; i < ARRAY_SIZE(registers); i++)
 486                 if (priv->rev >= registers[i].rev)
 487                         seq_printf(m, "%s:\t %08x\n", registers[i].name,
 488                                         tilcdc_read(dev, registers[i].reg));
 489
 490         pm_runtime_put_sync(dev->dev);
 491
 492         return 0;
 493 }
 494
 495 static int tilcdc_mm_show(struct seq_file *m, void *arg)
 496 {
 497         struct drm_info_node *node = (struct drm_info_node *) m->private;
 498         struct drm_device *dev = node->minor->dev;
 499         return drm_mm_dump_table(m, &dev->vma_offset_manager->vm_addr_space_mm);
 500 }
 501
 502 static struct drm_info_list tilcdc_debugfs_list[] = {
 503                 { "regs", tilcdc_regs_show, 0 },
 504                 { "mm",   tilcdc_mm_show,   0 },
 505                 { "fb",   drm_fb_cma_debugfs_show, 0 },
 506 };
 507
 508 static int tilcdc_debugfs_init(struct drm_minor *minor)
 509 {
 510         struct drm_device *dev = minor->dev;
 511         struct tilcdc_module *mod;
 512         int ret;
 513
 514         ret = drm_debugfs_create_files(tilcdc_debugfs_list,
 515                         ARRAY_SIZE(tilcdc_debugfs_list),
 516                         minor->debugfs_root, minor);
 517
 518         list_for_each_entry(mod, &module_list, list)
 519                 if (mod->funcs->debugfs_init)
 520                         mod->funcs->debugfs_init(mod, minor);
 521
 522         if (ret) {
 523                 dev_err(dev->dev, "could not install tilcdc_debugfs_list\n");
 524                 return ret;
 525         }
 526
 527         return ret;
 528 }
 529
 530 static void tilcdc_debugfs_cleanup(struct drm_minor *minor)
 531 {
 532         struct tilcdc_module *mod;
 533         drm_debugfs_remove_files(tilcdc_debugfs_list,
 534                         ARRAY_SIZE(tilcdc_debugfs_list), minor);
 535
 536         list_for_each_entry(mod, &module_list, list)
 537                 if (mod->funcs->debugfs_cleanup)
 538                         mod->funcs->debugfs_cleanup(mod, minor);
 539 }
 540 #endif
 541
 542 static const struct file_operations fops = {
 543         .owner              = THIS_MODULE,
 544         .open               = drm_open,
 545         .release            = drm_release,
 546         .unlocked_ioctl     = drm_ioctl,
 547 #ifdef CONFIG_COMPAT
 548         .compat_ioctl       = drm_compat_ioctl,
 549 #endif
 550         .poll               = drm_poll,
 551         .read               = drm_read,
 552         .llseek             = no_llseek,
 553         .mmap               = drm_gem_cma_mmap,
 554 };
 555
 556 static struct drm_driver tilcdc_driver = {
 557         .driver_features    = (DRIVER_HAVE_IRQ | DRIVER_GEM | DRIVER_MODESET |
 558                                DRIVER_PRIME | DRIVER_ATOMIC),
 559         .load               = tilcdc_load,
 560         .unload             = tilcdc_unload,
 561         .lastclose          = tilcdc_lastclose,
 562         .irq_handler        = tilcdc_irq,
 563         .get_vblank_counter = drm_vblank_no_hw_counter,
 564         .enable_vblank      = tilcdc_enable_vblank,
 565         .disable_vblank     = tilcdc_disable_vblank,
 566         .gem_free_object_unlocked = drm_gem_cma_free_object,
 567         .gem_vm_ops         = &drm_gem_cma_vm_ops,
 568         .dumb_create        = drm_gem_cma_dumb_create,
 569         .dumb_map_offset    = drm_gem_cma_dumb_map_offset,
 570         .dumb_destroy       = drm_gem_dumb_destroy,
 571
 572         .prime_handle_to_fd     = drm_gem_prime_handle_to_fd,
 573         .prime_fd_to_handle     = drm_gem_prime_fd_to_handle,
 574         .gem_prime_import       = drm_gem_prime_import,
 575         .gem_prime_export       = drm_gem_prime_export,
 576         .gem_prime_get_sg_table = drm_gem_cma_prime_get_sg_table,
 577         .gem_prime_import_sg_table = drm_gem_cma_prime_import_sg_table,
 578         .gem_prime_vmap         = drm_gem_cma_prime_vmap,
 579         .gem_prime_vunmap       = drm_gem_cma_prime_vunmap,
 580         .gem_prime_mmap         = drm_gem_cma_prime_mmap,
 581 #ifdef CONFIG_DEBUG_FS
 582         .debugfs_init       = tilcdc_debugfs_init,
 583         .debugfs_cleanup    = tilcdc_debugfs_cleanup,
 584 #endif
 585         .fops               = &fops,
 586         .name               = "tilcdc",
 587         .desc               = "TI LCD Controller DRM",
 588         .date               = "20121205",
 589         .major              = 1,
 590         .minor              = 0,
 591 };
 592
 593 /*
 594  * Power management:
 595  */
 596
 597 #ifdef CONFIG_PM_SLEEP
 598 static int tilcdc_pm_suspend(struct device *dev)
 599 {
 600         struct drm_device *ddev = dev_get_drvdata(dev);
 601         struct tilcdc_drm_private *priv = ddev->dev_private;
 602
 603         priv->saved_state = drm_atomic_helper_suspend(ddev);
 604
 605         /* Select sleep pin state */
 606         pinctrl_pm_select_sleep_state(dev);
 607
 608         return 0;
 609 }
 610
 611 static int tilcdc_pm_resume(struct device *dev)
 612 {
 613         struct drm_device *ddev = dev_get_drvdata(dev);
 614         struct tilcdc_drm_private *priv = ddev->dev_private;
 615         int ret = 0;
 616
 617         /* Select default pin state */
 618         pinctrl_pm_select_default_state(dev);
 619
 620         if (priv->saved_state)
 621                 ret = drm_atomic_helper_resume(ddev, priv->saved_state);
 622
 623         return ret;
 624 }
 625 #endif
 626
 627 static const struct dev_pm_ops tilcdc_pm_ops = {
 628         SET_SYSTEM_SLEEP_PM_OPS(tilcdc_pm_suspend, tilcdc_pm_resume)
 629 };
 630
 631 /*
 632  * Platform driver:
 633  */
 634
 635 static int tilcdc_bind(struct device *dev)
 636 {
 637         return drm_platform_init(&tilcdc_driver, to_platform_device(dev));
 638 }
 639
 640 static void tilcdc_unbind(struct device *dev)
 641 {
 642         struct drm_device *ddev = dev_get_drvdata(dev);
 643
 644         /* Check if a subcomponent has already triggered the unloading. */
 645         if (!ddev->dev_private)
 646                 return;
 647
 648         drm_put_dev(dev_get_drvdata(dev));
 649 }
 650
 651 static const struct component_master_ops tilcdc_comp_ops = {
 652         .bind = tilcdc_bind,
 653         .unbind = tilcdc_unbind,
 654 };
 655
 656 static int tilcdc_pdev_probe(struct platform_device *pdev)
 657 {
 658         struct component_match *match = NULL;
 659         int ret;
 660
 661         /* bail out early if no DT data: */
 662         if (!pdev->dev.of_node) {
 663                 dev_err(&pdev->dev, "device-tree data is missing\n");
 664                 return -ENXIO;
 665         }
 666
 667         ret = tilcdc_get_external_components(&pdev->dev, &match);
 668         if (ret < 0)
 669                 return ret;
 670         else if (ret == 0)
 671                 return drm_platform_init(&tilcdc_driver, pdev);
 672         else
 673                 return component_master_add_with_match(&pdev->dev,
 674                                                        &tilcdc_comp_ops,
 675                                                        match);
 676 }
 677
 678 static int tilcdc_pdev_remove(struct platform_device *pdev)
 679 {
 680         int ret;
 681
 682         ret = tilcdc_get_external_components(&pdev->dev, NULL);
 683         if (ret < 0)
 684                 return ret;
 685         else if (ret == 0)
 686                 drm_put_dev(platform_get_drvdata(pdev));
 687         else
 688                 component_master_del(&pdev->dev, &tilcdc_comp_ops);
 689
 690         return 0;
 691 }
 692
 693 static struct of_device_id tilcdc_of_match[] = {
 694                 { .compatible = "ti,am33xx-tilcdc", },
 695                 { },
 696 };
 697 MODULE_DEVICE_TABLE(of, tilcdc_of_match);
 698
 699 static struct platform_driver tilcdc_platform_driver = {
 700         .probe      = tilcdc_pdev_probe,
 701         .remove     = tilcdc_pdev_remove,
 702         .driver     = {
 703                 .name   = "tilcdc",
 704                 .pm     = &tilcdc_pm_ops,
 705                 .of_match_table = tilcdc_of_match,
 706         },
 707 };
 708
 709 static int __init tilcdc_drm_init(void)
 710 {
 711         DBG("init");
 712         tilcdc_tfp410_init();
 713         tilcdc_panel_init();
 714         return platform_driver_register(&tilcdc_platform_driver);
 715 }
 716
 717 static void __exit tilcdc_drm_fini(void)
 718 {
 719         DBG("fini");
 720         platform_driver_unregister(&tilcdc_platform_driver);
 721         tilcdc_panel_fini();
 722         tilcdc_tfp410_fini();
 723 }
 724
 725 module_init(tilcdc_drm_init);
 726 module_exit(tilcdc_drm_fini);
 727
 728 MODULE_AUTHOR("Rob Clark <robdclark@gmail.com");
 729 MODULE_DESCRIPTION("TI LCD Controller DRM Driver");
 730 MODULE_LICENSE("GPL");