drivers/gpu/drm/tilcdc/tilcdc_crtc.c

   1 /*
   2  * Copyright (C) 2012 Texas Instruments
   3  * Author: Rob Clark <robdclark@gmail.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 as published by
   7  * the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program.  If not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18 #include "drm_flip_work.h"
  19 #include <drm/drm_plane_helper.h>
  20
  21 #include "tilcdc_drv.h"
  22 #include "tilcdc_regs.h"
  23
  24 #define TILCDC_VBLANK_SAFETY_THRESHOLD_US 1000
  25
  26 struct tilcdc_crtc {
  27         struct drm_crtc base;
  28
  29         const struct tilcdc_panel_info *info;
  30         struct drm_pending_vblank_event *event;
  31         int dpms;
  32         wait_queue_head_t frame_done_wq;
  33         bool frame_done;
  34         spinlock_t irq_lock;
  35
  36         ktime_t last_vblank;
  37
  38         struct drm_framebuffer *curr_fb;
  39         struct drm_framebuffer *next_fb;
  40
  41         /* for deferred fb unref's: */
  42         struct drm_flip_work unref_work;
  43
  44         /* Only set if an external encoder is connected */
  45         bool simulate_vesa_sync;
  46
  47         int sync_lost_count;
  48         bool frame_intact;
  49 };
  50 #define to_tilcdc_crtc(x) container_of(x, struct tilcdc_crtc, base)
  51
  52 static void unref_worker(struct drm_flip_work *work, void *val)
  53 {
  54         struct tilcdc_crtc *tilcdc_crtc =
  55                 container_of(work, struct tilcdc_crtc, unref_work);
  56         struct drm_device *dev = tilcdc_crtc->base.dev;
  57
  58         mutex_lock(&dev->mode_config.mutex);
  59         drm_framebuffer_unreference(val);
  60         mutex_unlock(&dev->mode_config.mutex);
  61 }
  62
  63 static void set_scanout(struct drm_crtc *crtc, struct drm_framebuffer *fb)
  64 {
  65         struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
  66         struct drm_device *dev = crtc->dev;
  67         struct drm_gem_cma_object *gem;
  68         unsigned int depth, bpp;
  69         dma_addr_t start, end;
  70
  71         drm_fb_get_bpp_depth(fb->pixel_format, &depth, &bpp);
  72         gem = drm_fb_cma_get_gem_obj(fb, 0);
  73
  74         start = gem->paddr + fb->offsets[0] +
  75                 crtc->y * fb->pitches[0] +
  76                 crtc->x * bpp / 8;
  77
  78         end = start + (crtc->mode.vdisplay * fb->pitches[0]);
  79
  80         tilcdc_write(dev, LCDC_DMA_FB_BASE_ADDR_0_REG, start);
  81         tilcdc_write(dev, LCDC_DMA_FB_CEILING_ADDR_0_REG, end);
  82
  83         if (tilcdc_crtc->curr_fb)
  84                 drm_flip_work_queue(&tilcdc_crtc->unref_work,
  85                         tilcdc_crtc->curr_fb);
  86
  87         tilcdc_crtc->curr_fb = fb;
  88 }
  89
  90 static void reset(struct drm_crtc *crtc)
  91 {
  92         struct drm_device *dev = crtc->dev;
  93         struct tilcdc_drm_private *priv = dev->dev_private;
  94
  95         if (priv->rev != 2)
  96                 return;
  97
  98         tilcdc_set(dev, LCDC_CLK_RESET_REG, LCDC_CLK_MAIN_RESET);
  99         usleep_range(250, 1000);
 100         tilcdc_clear(dev, LCDC_CLK_RESET_REG, LCDC_CLK_MAIN_RESET);
 101 }
 102
 103 static void start(struct drm_crtc *crtc)
 104 {
 105         struct drm_device *dev = crtc->dev;
 106
 107         reset(crtc);
 108
 109         tilcdc_clear(dev, LCDC_DMA_CTRL_REG, LCDC_DUAL_FRAME_BUFFER_ENABLE);
 110         tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_PALETTE_LOAD_MODE(DATA_ONLY));
 111         tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ENABLE);
 112
 113         drm_crtc_vblank_on(crtc);
 114 }
 115
 116 static void stop(struct drm_crtc *crtc)
 117 {
 118         struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
 119         struct drm_device *dev = crtc->dev;
 120         struct tilcdc_drm_private *priv = dev->dev_private;
 121
 122         tilcdc_crtc->frame_done = false;
 123         tilcdc_clear(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ENABLE);
 124
 125         /*
 126          * if necessary wait for framedone irq which will still come
 127          * before putting things to sleep..
 128          */
 129         if (priv->rev == 2) {
 130                 int ret = wait_event_timeout(tilcdc_crtc->frame_done_wq,
 131                                              tilcdc_crtc->frame_done,
 132                                              msecs_to_jiffies(500));
 133                 if (ret == 0)
 134                         dev_err(dev->dev, "%s: timeout waiting for framedone\n",
 135                                 __func__);
 136         }
 137
 138         drm_crtc_vblank_off(crtc);
 139 }
 140
 141 static void tilcdc_crtc_destroy(struct drm_crtc *crtc)
 142 {
 143         struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
 144
 145         tilcdc_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
 146
 147         of_node_put(crtc->port);
 148         drm_crtc_cleanup(crtc);
 149         drm_flip_work_cleanup(&tilcdc_crtc->unref_work);
 150 }
 151
 152 static int tilcdc_verify_fb(struct drm_crtc *crtc, struct drm_framebuffer *fb)
 153 {
 154         struct drm_device *dev = crtc->dev;
 155         unsigned int depth, bpp;
 156
 157         drm_fb_get_bpp_depth(fb->pixel_format, &depth, &bpp);
 158
 159         if (fb->pitches[0] != crtc->mode.hdisplay * bpp / 8) {
 160                 dev_err(dev->dev,
 161                         "Invalid pitch: fb and crtc widths must be the same");
 162                 return -EINVAL;
 163         }
 164
 165         return 0;
 166 }
 167
 168 static int tilcdc_crtc_page_flip(struct drm_crtc *crtc,
 169                 struct drm_framebuffer *fb,
 170                 struct drm_pending_vblank_event *event,
 171                 uint32_t page_flip_flags)
 172 {
 173         struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
 174         struct drm_device *dev = crtc->dev;
 175         int r;
 176         unsigned long flags;
 177         s64 tdiff;
 178         ktime_t next_vblank;
 179
 180         r = tilcdc_verify_fb(crtc, fb);
 181         if (r)
 182                 return r;
 183
 184         if (tilcdc_crtc->event) {
 185                 dev_err(dev->dev, "already pending page flip!\n");
 186                 return -EBUSY;
 187         }
 188
 189         drm_framebuffer_reference(fb);
 190
 191         crtc->primary->fb = fb;
 192
 193         pm_runtime_get_sync(dev->dev);
 194
 195         spin_lock_irqsave(&tilcdc_crtc->irq_lock, flags);
 196
 197         next_vblank = ktime_add_us(tilcdc_crtc->last_vblank,
 198                 1000000 / crtc->hwmode.vrefresh);
 199
 200         tdiff = ktime_to_us(ktime_sub(next_vblank, ktime_get()));
 201
 202         if (tdiff >= TILCDC_VBLANK_SAFETY_THRESHOLD_US)
 203                 set_scanout(crtc, fb);
 204         else
 205                 tilcdc_crtc->next_fb = fb;
 206
 207         tilcdc_crtc->event = event;
 208
 209         spin_unlock_irqrestore(&tilcdc_crtc->irq_lock, flags);
 210
 211         pm_runtime_put_sync(dev->dev);
 212
 213         return 0;
 214 }
 215
 216 void tilcdc_crtc_dpms(struct drm_crtc *crtc, int mode)
 217 {
 218         struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
 219         struct drm_device *dev = crtc->dev;
 220         struct tilcdc_drm_private *priv = dev->dev_private;
 221
 222         /* we really only care about on or off: */
 223         if (mode != DRM_MODE_DPMS_ON)
 224                 mode = DRM_MODE_DPMS_OFF;
 225
 226         if (tilcdc_crtc->dpms == mode)
 227                 return;
 228
 229         tilcdc_crtc->dpms = mode;
 230
 231         if (mode == DRM_MODE_DPMS_ON) {
 232                 pm_runtime_get_sync(dev->dev);
 233                 start(crtc);
 234         } else {
 235                 stop(crtc);
 236                 pm_runtime_put_sync(dev->dev);
 237
 238                 if (tilcdc_crtc->next_fb) {
 239                         drm_flip_work_queue(&tilcdc_crtc->unref_work,
 240                                             tilcdc_crtc->next_fb);
 241                         tilcdc_crtc->next_fb = NULL;
 242                 }
 243
 244                 if (tilcdc_crtc->curr_fb) {
 245                         drm_flip_work_queue(&tilcdc_crtc->unref_work,
 246                                             tilcdc_crtc->curr_fb);
 247                         tilcdc_crtc->curr_fb = NULL;
 248                 }
 249
 250                 drm_flip_work_commit(&tilcdc_crtc->unref_work, priv->wq);
 251         }
 252 }
 253
 254 int tilcdc_crtc_current_dpms_state(struct drm_crtc *crtc)
 255 {
 256         struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
 257
 258         return tilcdc_crtc->dpms;
 259 }
 260
 261 static bool tilcdc_crtc_mode_fixup(struct drm_crtc *crtc,
 262                 const struct drm_display_mode *mode,
 263                 struct drm_display_mode *adjusted_mode)
 264 {
 265         struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
 266
 267         if (!tilcdc_crtc->simulate_vesa_sync)
 268                 return true;
 269
 270         /*
 271          * tilcdc does not generate VESA-compliant sync but aligns
 272          * VS on the second edge of HS instead of first edge.
 273          * We use adjusted_mode, to fixup sync by aligning both rising
 274          * edges and add HSKEW offset to fix the sync.
 275          */
 276         adjusted_mode->hskew = mode->hsync_end - mode->hsync_start;
 277         adjusted_mode->flags |= DRM_MODE_FLAG_HSKEW;
 278
 279         if (mode->flags & DRM_MODE_FLAG_NHSYNC) {
 280                 adjusted_mode->flags |= DRM_MODE_FLAG_PHSYNC;
 281                 adjusted_mode->flags &= ~DRM_MODE_FLAG_NHSYNC;
 282         } else {
 283                 adjusted_mode->flags |= DRM_MODE_FLAG_NHSYNC;
 284                 adjusted_mode->flags &= ~DRM_MODE_FLAG_PHSYNC;
 285         }
 286
 287         return true;
 288 }
 289
 290 static void tilcdc_crtc_prepare(struct drm_crtc *crtc)
 291 {
 292         tilcdc_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
 293 }
 294
 295 static void tilcdc_crtc_commit(struct drm_crtc *crtc)
 296 {
 297         tilcdc_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
 298 }
 299
 300 static int tilcdc_crtc_mode_set(struct drm_crtc *crtc,
 301                 struct drm_display_mode *mode,
 302                 struct drm_display_mode *adjusted_mode,
 303                 int x, int y,
 304                 struct drm_framebuffer *old_fb)
 305 {
 306         struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
 307         struct drm_device *dev = crtc->dev;
 308         struct tilcdc_drm_private *priv = dev->dev_private;
 309         const struct tilcdc_panel_info *info = tilcdc_crtc->info;
 310         uint32_t reg, hbp, hfp, hsw, vbp, vfp, vsw;
 311         int ret;
 312
 313         ret = tilcdc_crtc_mode_valid(crtc, mode);
 314         if (WARN_ON(ret))
 315                 return ret;
 316
 317         if (WARN_ON(!info))
 318                 return -EINVAL;
 319
 320         ret = tilcdc_verify_fb(crtc, crtc->primary->fb);
 321         if (ret)
 322                 return ret;
 323
 324         pm_runtime_get_sync(dev->dev);
 325
 326         /* Configure the Burst Size and fifo threshold of DMA: */
 327         reg = tilcdc_read(dev, LCDC_DMA_CTRL_REG) & ~0x00000770;
 328         switch (info->dma_burst_sz) {
 329         case 1:
 330                 reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_1);
 331                 break;
 332         case 2:
 333                 reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_2);
 334                 break;
 335         case 4:
 336                 reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_4);
 337                 break;
 338         case 8:
 339                 reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_8);
 340                 break;
 341         case 16:
 342                 reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_16);
 343                 break;
 344         default:
 345                 return -EINVAL;
 346         }
 347         reg |= (info->fifo_th << 8);
 348         tilcdc_write(dev, LCDC_DMA_CTRL_REG, reg);
 349
 350         /* Configure timings: */
 351         hbp = mode->htotal - mode->hsync_end;
 352         hfp = mode->hsync_start - mode->hdisplay;
 353         hsw = mode->hsync_end - mode->hsync_start;
 354         vbp = mode->vtotal - mode->vsync_end;
 355         vfp = mode->vsync_start - mode->vdisplay;
 356         vsw = mode->vsync_end - mode->vsync_start;
 357
 358         DBG("%dx%d, hbp=%u, hfp=%u, hsw=%u, vbp=%u, vfp=%u, vsw=%u",
 359                         mode->hdisplay, mode->vdisplay, hbp, hfp, hsw, vbp, vfp, vsw);
 360
 361         /* Configure the AC Bias Period and Number of Transitions per Interrupt: */
 362         reg = tilcdc_read(dev, LCDC_RASTER_TIMING_2_REG) & ~0x000fff00;
 363         reg |= LCDC_AC_BIAS_FREQUENCY(info->ac_bias) |
 364                 LCDC_AC_BIAS_TRANSITIONS_PER_INT(info->ac_bias_intrpt);
 365
 366         /*
 367          * subtract one from hfp, hbp, hsw because the hardware uses
 368          * a value of 0 as 1
 369          */
 370         if (priv->rev == 2) {
 371                 /* clear bits we're going to set */
 372                 reg &= ~0x78000033;
 373                 reg |= ((hfp-1) & 0x300) >> 8;
 374                 reg |= ((hbp-1) & 0x300) >> 4;
 375                 reg |= ((hsw-1) & 0x3c0) << 21;
 376         }
 377         tilcdc_write(dev, LCDC_RASTER_TIMING_2_REG, reg);
 378
 379         reg = (((mode->hdisplay >> 4) - 1) << 4) |
 380                 (((hbp-1) & 0xff) << 24) |
 381                 (((hfp-1) & 0xff) << 16) |
 382                 (((hsw-1) & 0x3f) << 10);
 383         if (priv->rev == 2)
 384                 reg |= (((mode->hdisplay >> 4) - 1) & 0x40) >> 3;
 385         tilcdc_write(dev, LCDC_RASTER_TIMING_0_REG, reg);
 386
 387         reg = ((mode->vdisplay - 1) & 0x3ff) |
 388                 ((vbp & 0xff) << 24) |
 389                 ((vfp & 0xff) << 16) |
 390                 (((vsw-1) & 0x3f) << 10);
 391         tilcdc_write(dev, LCDC_RASTER_TIMING_1_REG, reg);
 392
 393         /*
 394          * be sure to set Bit 10 for the V2 LCDC controller,
 395          * otherwise limited to 1024 pixels width, stopping
 396          * 1920x1080 being suppoted.
 397          */
 398         if (priv->rev == 2) {
 399                 if ((mode->vdisplay - 1) & 0x400) {
 400                         tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG,
 401                                 LCDC_LPP_B10);
 402                 } else {
 403                         tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG,
 404                                 LCDC_LPP_B10);
 405                 }
 406         }
 407
 408         /* Configure display type: */
 409         reg = tilcdc_read(dev, LCDC_RASTER_CTRL_REG) &
 410                 ~(LCDC_TFT_MODE | LCDC_MONO_8BIT_MODE | LCDC_MONOCHROME_MODE |
 411                         LCDC_V2_TFT_24BPP_MODE | LCDC_V2_TFT_24BPP_UNPACK | 0x000ff000);
 412         reg |= LCDC_TFT_MODE; /* no monochrome/passive support */
 413         if (info->tft_alt_mode)
 414                 reg |= LCDC_TFT_ALT_ENABLE;
 415         if (priv->rev == 2) {
 416                 unsigned int depth, bpp;
 417
 418                 drm_fb_get_bpp_depth(crtc->primary->fb->pixel_format, &depth, &bpp);
 419                 switch (bpp) {
 420                 case 16:
 421                         break;
 422                 case 32:
 423                         reg |= LCDC_V2_TFT_24BPP_UNPACK;
 424                         /* fallthrough */
 425                 case 24:
 426                         reg |= LCDC_V2_TFT_24BPP_MODE;
 427                         break;
 428                 default:
 429                         dev_err(dev->dev, "invalid pixel format\n");
 430                         return -EINVAL;
 431                 }
 432         }
 433         reg |= info->fdd < 12;
 434         tilcdc_write(dev, LCDC_RASTER_CTRL_REG, reg);
 435
 436         if (info->invert_pxl_clk)
 437                 tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_PIXEL_CLOCK);
 438         else
 439                 tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_PIXEL_CLOCK);
 440
 441         if (info->sync_ctrl)
 442                 tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_CTRL);
 443         else
 444                 tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_CTRL);
 445
 446         if (info->sync_edge)
 447                 tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_EDGE);
 448         else
 449                 tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_EDGE);
 450
 451         /*
 452          * use value from adjusted_mode here as this might have been
 453          * changed as part of the fixup for slave encoders to solve the
 454          * issue where tilcdc timings are not VESA compliant
 455          */
 456         if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
 457                 tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_HSYNC);
 458         else
 459                 tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_HSYNC);
 460
 461         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
 462                 tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_VSYNC);
 463         else
 464                 tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_VSYNC);
 465
 466         if (info->raster_order)
 467                 tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ORDER);
 468         else
 469                 tilcdc_clear(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ORDER);
 470
 471         drm_framebuffer_reference(crtc->primary->fb);
 472
 473         set_scanout(crtc, crtc->primary->fb);
 474
 475         tilcdc_crtc_update_clk(crtc);
 476
 477         pm_runtime_put_sync(dev->dev);
 478
 479         return 0;
 480 }
 481
 482 static int tilcdc_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
 483                 struct drm_framebuffer *old_fb)
 484 {
 485         struct drm_device *dev = crtc->dev;
 486         int r;
 487
 488         r = tilcdc_verify_fb(crtc, crtc->primary->fb);
 489         if (r)
 490                 return r;
 491
 492         drm_framebuffer_reference(crtc->primary->fb);
 493
 494         pm_runtime_get_sync(dev->dev);
 495
 496         set_scanout(crtc, crtc->primary->fb);
 497
 498         pm_runtime_put_sync(dev->dev);
 499
 500         return 0;
 501 }
 502
 503 static const struct drm_crtc_funcs tilcdc_crtc_funcs = {
 504                 .destroy        = tilcdc_crtc_destroy,
 505                 .set_config     = drm_crtc_helper_set_config,
 506                 .page_flip      = tilcdc_crtc_page_flip,
 507 };
 508
 509 static const struct drm_crtc_helper_funcs tilcdc_crtc_helper_funcs = {
 510                 .dpms           = tilcdc_crtc_dpms,
 511                 .mode_fixup     = tilcdc_crtc_mode_fixup,
 512                 .prepare        = tilcdc_crtc_prepare,
 513                 .commit         = tilcdc_crtc_commit,
 514                 .mode_set       = tilcdc_crtc_mode_set,
 515                 .mode_set_base  = tilcdc_crtc_mode_set_base,
 516 };
 517
 518 int tilcdc_crtc_max_width(struct drm_crtc *crtc)
 519 {
 520         struct drm_device *dev = crtc->dev;
 521         struct tilcdc_drm_private *priv = dev->dev_private;
 522         int max_width = 0;
 523
 524         if (priv->rev == 1)
 525                 max_width = 1024;
 526         else if (priv->rev == 2)
 527                 max_width = 2048;
 528
 529         return max_width;
 530 }
 531
 532 int tilcdc_crtc_mode_valid(struct drm_crtc *crtc, struct drm_display_mode *mode)
 533 {
 534         struct tilcdc_drm_private *priv = crtc->dev->dev_private;
 535         unsigned int bandwidth;
 536         uint32_t hbp, hfp, hsw, vbp, vfp, vsw;
 537
 538         /*
 539          * check to see if the width is within the range that
 540          * the LCD Controller physically supports
 541          */
 542         if (mode->hdisplay > tilcdc_crtc_max_width(crtc))
 543                 return MODE_VIRTUAL_X;
 544
 545         /* width must be multiple of 16 */
 546         if (mode->hdisplay & 0xf)
 547                 return MODE_VIRTUAL_X;
 548
 549         if (mode->vdisplay > 2048)
 550                 return MODE_VIRTUAL_Y;
 551
 552         DBG("Processing mode %dx%d@%d with pixel clock %d",
 553                 mode->hdisplay, mode->vdisplay,
 554                 drm_mode_vrefresh(mode), mode->clock);
 555
 556         hbp = mode->htotal - mode->hsync_end;
 557         hfp = mode->hsync_start - mode->hdisplay;
 558         hsw = mode->hsync_end - mode->hsync_start;
 559         vbp = mode->vtotal - mode->vsync_end;
 560         vfp = mode->vsync_start - mode->vdisplay;
 561         vsw = mode->vsync_end - mode->vsync_start;
 562
 563         if ((hbp-1) & ~0x3ff) {
 564                 DBG("Pruning mode: Horizontal Back Porch out of range");
 565                 return MODE_HBLANK_WIDE;
 566         }
 567
 568         if ((hfp-1) & ~0x3ff) {
 569                 DBG("Pruning mode: Horizontal Front Porch out of range");
 570                 return MODE_HBLANK_WIDE;
 571         }
 572
 573         if ((hsw-1) & ~0x3ff) {
 574                 DBG("Pruning mode: Horizontal Sync Width out of range");
 575                 return MODE_HSYNC_WIDE;
 576         }
 577
 578         if (vbp & ~0xff) {
 579                 DBG("Pruning mode: Vertical Back Porch out of range");
 580                 return MODE_VBLANK_WIDE;
 581         }
 582
 583         if (vfp & ~0xff) {
 584                 DBG("Pruning mode: Vertical Front Porch out of range");
 585                 return MODE_VBLANK_WIDE;
 586         }
 587
 588         if ((vsw-1) & ~0x3f) {
 589                 DBG("Pruning mode: Vertical Sync Width out of range");
 590                 return MODE_VSYNC_WIDE;
 591         }
 592
 593         /*
 594          * some devices have a maximum allowed pixel clock
 595          * configured from the DT
 596          */
 597         if (mode->clock > priv->max_pixelclock) {
 598                 DBG("Pruning mode: pixel clock too high");
 599                 return MODE_CLOCK_HIGH;
 600         }
 601
 602         /*
 603          * some devices further limit the max horizontal resolution
 604          * configured from the DT
 605          */
 606         if (mode->hdisplay > priv->max_width)
 607                 return MODE_BAD_WIDTH;
 608
 609         /* filter out modes that would require too much memory bandwidth: */
 610         bandwidth = mode->hdisplay * mode->vdisplay *
 611                 drm_mode_vrefresh(mode);
 612         if (bandwidth > priv->max_bandwidth) {
 613                 DBG("Pruning mode: exceeds defined bandwidth limit");
 614                 return MODE_BAD;
 615         }
 616
 617         return MODE_OK;
 618 }
 619
 620 void tilcdc_crtc_set_panel_info(struct drm_crtc *crtc,
 621                 const struct tilcdc_panel_info *info)
 622 {
 623         struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
 624         tilcdc_crtc->info = info;
 625 }
 626
 627 void tilcdc_crtc_set_simulate_vesa_sync(struct drm_crtc *crtc,
 628                                         bool simulate_vesa_sync)
 629 {
 630         struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
 631
 632         tilcdc_crtc->simulate_vesa_sync = simulate_vesa_sync;
 633 }
 634
 635 void tilcdc_crtc_update_clk(struct drm_crtc *crtc)
 636 {
 637         struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
 638         struct drm_device *dev = crtc->dev;
 639         struct tilcdc_drm_private *priv = dev->dev_private;
 640         int dpms = tilcdc_crtc->dpms;
 641         unsigned long lcd_clk;
 642         const unsigned clkdiv = 2; /* using a fixed divider of 2 */
 643         int ret;
 644
 645         pm_runtime_get_sync(dev->dev);
 646
 647         if (dpms == DRM_MODE_DPMS_ON)
 648                 tilcdc_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
 649
 650         /* mode.clock is in KHz, set_rate wants parameter in Hz */
 651         ret = clk_set_rate(priv->clk, crtc->mode.clock * 1000 * clkdiv);
 652         if (ret < 0) {
 653                 dev_err(dev->dev, "failed to set display clock rate to: %d\n",
 654                                 crtc->mode.clock);
 655                 goto out;
 656         }
 657
 658         lcd_clk = clk_get_rate(priv->clk);
 659
 660         DBG("lcd_clk=%lu, mode clock=%d, div=%u",
 661                 lcd_clk, crtc->mode.clock, clkdiv);
 662
 663         /* Configure the LCD clock divisor. */
 664         tilcdc_write(dev, LCDC_CTRL_REG, LCDC_CLK_DIVISOR(clkdiv) |
 665                         LCDC_RASTER_MODE);
 666
 667         if (priv->rev == 2)
 668                 tilcdc_set(dev, LCDC_CLK_ENABLE_REG,
 669                                 LCDC_V2_DMA_CLK_EN | LCDC_V2_LIDD_CLK_EN |
 670                                 LCDC_V2_CORE_CLK_EN);
 671
 672         if (dpms == DRM_MODE_DPMS_ON)
 673                 tilcdc_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
 674
 675 out:
 676         pm_runtime_put_sync(dev->dev);
 677 }
 678
 679 #define SYNC_LOST_COUNT_LIMIT 50
 680
 681 irqreturn_t tilcdc_crtc_irq(struct drm_crtc *crtc)
 682 {
 683         struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
 684         struct drm_device *dev = crtc->dev;
 685         struct tilcdc_drm_private *priv = dev->dev_private;
 686         uint32_t stat;
 687
 688         stat = tilcdc_read_irqstatus(dev);
 689         tilcdc_clear_irqstatus(dev, stat);
 690
 691         if (stat & LCDC_END_OF_FRAME0) {
 692                 unsigned long flags;
 693                 bool skip_event = false;
 694                 ktime_t now;
 695
 696                 now = ktime_get();
 697
 698                 drm_flip_work_commit(&tilcdc_crtc->unref_work, priv->wq);
 699
 700                 spin_lock_irqsave(&tilcdc_crtc->irq_lock, flags);
 701
 702                 tilcdc_crtc->last_vblank = now;
 703
 704                 if (tilcdc_crtc->next_fb) {
 705                         set_scanout(crtc, tilcdc_crtc->next_fb);
 706                         tilcdc_crtc->next_fb = NULL;
 707                         skip_event = true;
 708                 }
 709
 710                 spin_unlock_irqrestore(&tilcdc_crtc->irq_lock, flags);
 711
 712                 drm_crtc_handle_vblank(crtc);
 713
 714                 if (!skip_event) {
 715                         struct drm_pending_vblank_event *event;
 716
 717                         spin_lock_irqsave(&dev->event_lock, flags);
 718
 719                         event = tilcdc_crtc->event;
 720                         tilcdc_crtc->event = NULL;
 721                         if (event)
 722                                 drm_crtc_send_vblank_event(crtc, event);
 723
 724                         spin_unlock_irqrestore(&dev->event_lock, flags);
 725                 }
 726
 727                 if (tilcdc_crtc->frame_intact)
 728                         tilcdc_crtc->sync_lost_count = 0;
 729                 else
 730                         tilcdc_crtc->frame_intact = true;
 731         }
 732
 733         if (stat & LCDC_FIFO_UNDERFLOW)
 734                 dev_err_ratelimited(dev->dev, "%s(0x%08x): FIFO underfow",
 735                                     __func__, stat);
 736
 737         /* For revision 2 only */
 738         if (priv->rev == 2) {
 739                 if (stat & LCDC_FRAME_DONE) {
 740                         tilcdc_crtc->frame_done = true;
 741                         wake_up(&tilcdc_crtc->frame_done_wq);
 742                 }
 743
 744                 if (stat & LCDC_SYNC_LOST) {
 745                         dev_err_ratelimited(dev->dev, "%s(0x%08x): Sync lost",
 746                                             __func__, stat);
 747                         tilcdc_crtc->frame_intact = false;
 748                         if (tilcdc_crtc->sync_lost_count++ >
 749                             SYNC_LOST_COUNT_LIMIT) {
 750                                 dev_err(dev->dev, "%s(0x%08x): Sync lost flood detected, disabling the interrupt", __func__, stat);
 751                                 tilcdc_write(dev, LCDC_INT_ENABLE_CLR_REG,
 752                                              LCDC_SYNC_LOST);
 753                         }
 754                 }
 755
 756                 /* Indicate to LCDC that the interrupt service routine has
 757                  * completed, see 13.3.6.1.6 in AM335x TRM.
 758                  */
 759                 tilcdc_write(dev, LCDC_END_OF_INT_IND_REG, 0);
 760         }
 761
 762         return IRQ_HANDLED;
 763 }
 764
 765 struct drm_crtc *tilcdc_crtc_create(struct drm_device *dev)
 766 {
 767         struct tilcdc_drm_private *priv = dev->dev_private;
 768         struct tilcdc_crtc *tilcdc_crtc;
 769         struct drm_crtc *crtc;
 770         int ret;
 771
 772         tilcdc_crtc = devm_kzalloc(dev->dev, sizeof(*tilcdc_crtc), GFP_KERNEL);
 773         if (!tilcdc_crtc) {
 774                 dev_err(dev->dev, "allocation failed\n");
 775                 return NULL;
 776         }
 777
 778         crtc = &tilcdc_crtc->base;
 779
 780         tilcdc_crtc->dpms = DRM_MODE_DPMS_OFF;
 781         init_waitqueue_head(&tilcdc_crtc->frame_done_wq);
 782
 783         drm_flip_work_init(&tilcdc_crtc->unref_work,
 784                         "unref", unref_worker);
 785
 786         spin_lock_init(&tilcdc_crtc->irq_lock);
 787
 788         ret = drm_crtc_init(dev, crtc, &tilcdc_crtc_funcs);
 789         if (ret < 0)
 790                 goto fail;
 791
 792         drm_crtc_helper_add(crtc, &tilcdc_crtc_helper_funcs);
 793
 794         if (priv->is_componentized) {
 795                 struct device_node *ports =
 796                         of_get_child_by_name(dev->dev->of_node, "ports");
 797
 798                 if (ports) {
 799                         crtc->port = of_get_child_by_name(ports, "port");
 800                         of_node_put(ports);
 801                 } else {
 802                         crtc->port =
 803                                 of_get_child_by_name(dev->dev->of_node, "port");
 804                 }
 805                 if (!crtc->port) { /* This should never happen */
 806                         dev_err(dev->dev, "Port node not found in %s\n",
 807                                 dev->dev->of_node->full_name);
 808                         goto fail;
 809                 }
 810         }
 811
 812         return crtc;
 813
 814 fail:
 815         tilcdc_crtc_destroy(crtc);
 816         return NULL;
 817 }