drivers/gpu/drm/tilcdc/tilcdc_crtc.c

   1 /*
   2  * Copyright (C) 2012 Texas Instruments
   3  * Author: Rob Clark <robdclark@gmail.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 as published by
   7  * the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program.  If not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18 #include "drm_flip_work.h"
  19 #include <drm/drm_plane_helper.h>
  20 #include <drm/drm_atomic_helper.h>
  21 #include <linux/workqueue.h>
  22
  23 #include "tilcdc_drv.h"
  24 #include "tilcdc_regs.h"
  25
  26 #define TILCDC_VBLANK_SAFETY_THRESHOLD_US 1000
  27
  28 struct tilcdc_crtc {
  29         struct drm_crtc base;
  30
  31         struct drm_plane primary;
  32         const struct tilcdc_panel_info *info;
  33         struct drm_pending_vblank_event *event;
  34         bool enabled;
  35         wait_queue_head_t frame_done_wq;
  36         bool frame_done;
  37         spinlock_t irq_lock;
  38
  39         unsigned int lcd_fck_rate;
  40
  41         ktime_t last_vblank;
  42
  43         struct drm_framebuffer *curr_fb;
  44         struct drm_framebuffer *next_fb;
  45
  46         /* for deferred fb unref's: */
  47         struct drm_flip_work unref_work;
  48
  49         /* Only set if an external encoder is connected */
  50         bool simulate_vesa_sync;
  51
  52         int sync_lost_count;
  53         bool frame_intact;
  54 };
  55 #define to_tilcdc_crtc(x) container_of(x, struct tilcdc_crtc, base)
  56
  57 static void unref_worker(struct drm_flip_work *work, void *val)
  58 {
  59         struct tilcdc_crtc *tilcdc_crtc =
  60                 container_of(work, struct tilcdc_crtc, unref_work);
  61         struct drm_device *dev = tilcdc_crtc->base.dev;
  62
  63         mutex_lock(&dev->mode_config.mutex);
  64         drm_framebuffer_unreference(val);
  65         mutex_unlock(&dev->mode_config.mutex);
  66 }
  67
  68 static void set_scanout(struct drm_crtc *crtc, struct drm_framebuffer *fb)
  69 {
  70         struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
  71         struct drm_device *dev = crtc->dev;
  72         struct drm_gem_cma_object *gem;
  73         unsigned int depth, bpp;
  74         dma_addr_t start, end;
  75         u64 dma_base_and_ceiling;
  76
  77         drm_fb_get_bpp_depth(fb->pixel_format, &depth, &bpp);
  78         gem = drm_fb_cma_get_gem_obj(fb, 0);
  79
  80         start = gem->paddr + fb->offsets[0] +
  81                 crtc->y * fb->pitches[0] +
  82                 crtc->x * bpp / 8;
  83
  84         end = start + (crtc->mode.vdisplay * fb->pitches[0]);
  85
  86         /* Write LCDC_DMA_FB_BASE_ADDR_0_REG and LCDC_DMA_FB_CEILING_ADDR_0_REG
  87          * with a single insruction, if available. This should make it more
  88          * unlikely that LCDC would fetch the DMA addresses in the middle of
  89          * an update.
  90          */
  91         dma_base_and_ceiling = (u64)(end - 1) << 32 | start;
  92         tilcdc_write64(dev, LCDC_DMA_FB_BASE_ADDR_0_REG, dma_base_and_ceiling);
  93
  94         if (tilcdc_crtc->curr_fb)
  95                 drm_flip_work_queue(&tilcdc_crtc->unref_work,
  96                         tilcdc_crtc->curr_fb);
  97
  98         tilcdc_crtc->curr_fb = fb;
  99 }
 100
 101 static void tilcdc_crtc_enable_irqs(struct drm_device *dev)
 102 {
 103         struct tilcdc_drm_private *priv = dev->dev_private;
 104
 105         tilcdc_clear_irqstatus(dev, 0xffffffff);
 106
 107         if (priv->rev == 1) {
 108                 tilcdc_set(dev, LCDC_RASTER_CTRL_REG,
 109                         LCDC_V1_UNDERFLOW_INT_ENA);
 110                 tilcdc_set(dev, LCDC_DMA_CTRL_REG,
 111                         LCDC_V1_END_OF_FRAME_INT_ENA);
 112         } else {
 113                 tilcdc_write(dev, LCDC_INT_ENABLE_SET_REG,
 114                         LCDC_V2_UNDERFLOW_INT_ENA |
 115                         LCDC_V2_END_OF_FRAME0_INT_ENA |
 116                         LCDC_FRAME_DONE | LCDC_SYNC_LOST);
 117         }
 118 }
 119
 120 static void tilcdc_crtc_disable_irqs(struct drm_device *dev)
 121 {
 122         struct tilcdc_drm_private *priv = dev->dev_private;
 123
 124         /* disable irqs that we might have enabled: */
 125         if (priv->rev == 1) {
 126                 tilcdc_clear(dev, LCDC_RASTER_CTRL_REG,
 127                         LCDC_V1_UNDERFLOW_INT_ENA | LCDC_V1_PL_INT_ENA);
 128                 tilcdc_clear(dev, LCDC_DMA_CTRL_REG,
 129                         LCDC_V1_END_OF_FRAME_INT_ENA);
 130         } else {
 131                 tilcdc_write(dev, LCDC_INT_ENABLE_CLR_REG,
 132                         LCDC_V2_UNDERFLOW_INT_ENA | LCDC_V2_PL_INT_ENA |
 133                         LCDC_V2_END_OF_FRAME0_INT_ENA |
 134                         LCDC_FRAME_DONE | LCDC_SYNC_LOST);
 135         }
 136 }
 137
 138 static void reset(struct drm_crtc *crtc)
 139 {
 140         struct drm_device *dev = crtc->dev;
 141         struct tilcdc_drm_private *priv = dev->dev_private;
 142
 143         if (priv->rev != 2)
 144                 return;
 145
 146         tilcdc_set(dev, LCDC_CLK_RESET_REG, LCDC_CLK_MAIN_RESET);
 147         usleep_range(250, 1000);
 148         tilcdc_clear(dev, LCDC_CLK_RESET_REG, LCDC_CLK_MAIN_RESET);
 149 }
 150
 151 static void tilcdc_crtc_enable(struct drm_crtc *crtc)
 152 {
 153         struct drm_device *dev = crtc->dev;
 154         struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
 155
 156         if (tilcdc_crtc->enabled)
 157                 return;
 158
 159         pm_runtime_get_sync(dev->dev);
 160
 161         reset(crtc);
 162
 163         tilcdc_crtc_enable_irqs(dev);
 164
 165         tilcdc_clear(dev, LCDC_DMA_CTRL_REG, LCDC_DUAL_FRAME_BUFFER_ENABLE);
 166         tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_PALETTE_LOAD_MODE(DATA_ONLY));
 167         tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ENABLE);
 168
 169         drm_crtc_vblank_on(crtc);
 170
 171         tilcdc_crtc->enabled = true;
 172 }
 173
 174 void tilcdc_crtc_disable(struct drm_crtc *crtc)
 175 {
 176         struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
 177         struct drm_device *dev = crtc->dev;
 178         struct tilcdc_drm_private *priv = dev->dev_private;
 179
 180         if (!tilcdc_crtc->enabled)
 181                 return;
 182
 183         tilcdc_crtc->frame_done = false;
 184         tilcdc_clear(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ENABLE);
 185
 186         /*
 187          * if necessary wait for framedone irq which will still come
 188          * before putting things to sleep..
 189          */
 190         if (priv->rev == 2) {
 191                 int ret = wait_event_timeout(tilcdc_crtc->frame_done_wq,
 192                                              tilcdc_crtc->frame_done,
 193                                              msecs_to_jiffies(500));
 194                 if (ret == 0)
 195                         dev_err(dev->dev, "%s: timeout waiting for framedone\n",
 196                                 __func__);
 197         }
 198
 199         drm_crtc_vblank_off(crtc);
 200
 201         tilcdc_crtc_disable_irqs(dev);
 202
 203         pm_runtime_put_sync(dev->dev);
 204
 205         if (tilcdc_crtc->next_fb) {
 206                 drm_flip_work_queue(&tilcdc_crtc->unref_work,
 207                                     tilcdc_crtc->next_fb);
 208                 tilcdc_crtc->next_fb = NULL;
 209         }
 210
 211         if (tilcdc_crtc->curr_fb) {
 212                 drm_flip_work_queue(&tilcdc_crtc->unref_work,
 213                                     tilcdc_crtc->curr_fb);
 214                 tilcdc_crtc->curr_fb = NULL;
 215         }
 216
 217         drm_flip_work_commit(&tilcdc_crtc->unref_work, priv->wq);
 218         tilcdc_crtc->last_vblank = ktime_set(0, 0);
 219
 220         tilcdc_crtc->enabled = false;
 221 }
 222
 223 static bool tilcdc_crtc_is_on(struct drm_crtc *crtc)
 224 {
 225         return crtc->state && crtc->state->enable && crtc->state->active;
 226 }
 227
 228 static void tilcdc_crtc_destroy(struct drm_crtc *crtc)
 229 {
 230         struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
 231         struct tilcdc_drm_private *priv = crtc->dev->dev_private;
 232
 233         drm_modeset_lock_crtc(crtc, NULL);
 234         tilcdc_crtc_disable(crtc);
 235         drm_modeset_unlock_crtc(crtc);
 236
 237         flush_workqueue(priv->wq);
 238
 239         of_node_put(crtc->port);
 240         drm_crtc_cleanup(crtc);
 241         drm_flip_work_cleanup(&tilcdc_crtc->unref_work);
 242 }
 243
 244 int tilcdc_crtc_update_fb(struct drm_crtc *crtc,
 245                 struct drm_framebuffer *fb,
 246                 struct drm_pending_vblank_event *event)
 247 {
 248         struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
 249         struct drm_device *dev = crtc->dev;
 250         unsigned long flags;
 251
 252         if (tilcdc_crtc->event) {
 253                 dev_err(dev->dev, "already pending page flip!\n");
 254                 return -EBUSY;
 255         }
 256
 257         drm_framebuffer_reference(fb);
 258
 259         crtc->primary->fb = fb;
 260
 261         spin_lock_irqsave(&tilcdc_crtc->irq_lock, flags);
 262
 263         if (crtc->hwmode.vrefresh && ktime_to_ns(tilcdc_crtc->last_vblank)) {
 264                 ktime_t next_vblank;
 265                 s64 tdiff;
 266
 267                 next_vblank = ktime_add_us(tilcdc_crtc->last_vblank,
 268                         1000000 / crtc->hwmode.vrefresh);
 269
 270                 tdiff = ktime_to_us(ktime_sub(next_vblank, ktime_get()));
 271
 272                 if (tdiff < TILCDC_VBLANK_SAFETY_THRESHOLD_US)
 273                         tilcdc_crtc->next_fb = fb;
 274         }
 275
 276         if (tilcdc_crtc->next_fb != fb)
 277                 set_scanout(crtc, fb);
 278
 279         tilcdc_crtc->event = event;
 280
 281         spin_unlock_irqrestore(&tilcdc_crtc->irq_lock, flags);
 282
 283         return 0;
 284 }
 285
 286 static bool tilcdc_crtc_mode_fixup(struct drm_crtc *crtc,
 287                 const struct drm_display_mode *mode,
 288                 struct drm_display_mode *adjusted_mode)
 289 {
 290         struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
 291
 292         if (!tilcdc_crtc->simulate_vesa_sync)
 293                 return true;
 294
 295         /*
 296          * tilcdc does not generate VESA-compliant sync but aligns
 297          * VS on the second edge of HS instead of first edge.
 298          * We use adjusted_mode, to fixup sync by aligning both rising
 299          * edges and add HSKEW offset to fix the sync.
 300          */
 301         adjusted_mode->hskew = mode->hsync_end - mode->hsync_start;
 302         adjusted_mode->flags |= DRM_MODE_FLAG_HSKEW;
 303
 304         if (mode->flags & DRM_MODE_FLAG_NHSYNC) {
 305                 adjusted_mode->flags |= DRM_MODE_FLAG_PHSYNC;
 306                 adjusted_mode->flags &= ~DRM_MODE_FLAG_NHSYNC;
 307         } else {
 308                 adjusted_mode->flags |= DRM_MODE_FLAG_NHSYNC;
 309                 adjusted_mode->flags &= ~DRM_MODE_FLAG_PHSYNC;
 310         }
 311
 312         return true;
 313 }
 314
 315 static void tilcdc_crtc_set_clk(struct drm_crtc *crtc)
 316 {
 317         struct drm_device *dev = crtc->dev;
 318         struct tilcdc_drm_private *priv = dev->dev_private;
 319         struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
 320         const unsigned clkdiv = 2; /* using a fixed divider of 2 */
 321         int ret;
 322
 323         /* mode.clock is in KHz, set_rate wants parameter in Hz */
 324         ret = clk_set_rate(priv->clk, crtc->mode.clock * 1000 * clkdiv);
 325         if (ret < 0) {
 326                 dev_err(dev->dev, "failed to set display clock rate to: %d\n",
 327                         crtc->mode.clock);
 328                 return;
 329         }
 330
 331         tilcdc_crtc->lcd_fck_rate = clk_get_rate(priv->clk);
 332
 333         DBG("lcd_clk=%u, mode clock=%d, div=%u",
 334             tilcdc_crtc->lcd_fck_rate, crtc->mode.clock, clkdiv);
 335
 336         /* Configure the LCD clock divisor. */
 337         tilcdc_write(dev, LCDC_CTRL_REG, LCDC_CLK_DIVISOR(clkdiv) |
 338                      LCDC_RASTER_MODE);
 339
 340         if (priv->rev == 2)
 341                 tilcdc_set(dev, LCDC_CLK_ENABLE_REG,
 342                                 LCDC_V2_DMA_CLK_EN | LCDC_V2_LIDD_CLK_EN |
 343                                 LCDC_V2_CORE_CLK_EN);
 344 }
 345
 346 static void tilcdc_crtc_mode_set_nofb(struct drm_crtc *crtc)
 347 {
 348         struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
 349         struct drm_device *dev = crtc->dev;
 350         struct tilcdc_drm_private *priv = dev->dev_private;
 351         const struct tilcdc_panel_info *info = tilcdc_crtc->info;
 352         uint32_t reg, hbp, hfp, hsw, vbp, vfp, vsw;
 353         struct drm_display_mode *mode = &crtc->state->adjusted_mode;
 354         struct drm_framebuffer *fb = crtc->primary->state->fb;
 355
 356         if (WARN_ON(!info))
 357                 return;
 358
 359         if (WARN_ON(!fb))
 360                 return;
 361
 362         /* Configure the Burst Size and fifo threshold of DMA: */
 363         reg = tilcdc_read(dev, LCDC_DMA_CTRL_REG) & ~0x00000770;
 364         switch (info->dma_burst_sz) {
 365         case 1:
 366                 reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_1);
 367                 break;
 368         case 2:
 369                 reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_2);
 370                 break;
 371         case 4:
 372                 reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_4);
 373                 break;
 374         case 8:
 375                 reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_8);
 376                 break;
 377         case 16:
 378                 reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_16);
 379                 break;
 380         default:
 381                 dev_err(dev->dev, "invalid burst size\n");
 382                 return;
 383         }
 384         reg |= (info->fifo_th << 8);
 385         tilcdc_write(dev, LCDC_DMA_CTRL_REG, reg);
 386
 387         /* Configure timings: */
 388         hbp = mode->htotal - mode->hsync_end;
 389         hfp = mode->hsync_start - mode->hdisplay;
 390         hsw = mode->hsync_end - mode->hsync_start;
 391         vbp = mode->vtotal - mode->vsync_end;
 392         vfp = mode->vsync_start - mode->vdisplay;
 393         vsw = mode->vsync_end - mode->vsync_start;
 394
 395         DBG("%dx%d, hbp=%u, hfp=%u, hsw=%u, vbp=%u, vfp=%u, vsw=%u",
 396             mode->hdisplay, mode->vdisplay, hbp, hfp, hsw, vbp, vfp, vsw);
 397
 398         /* Set AC Bias Period and Number of Transitions per Interrupt: */
 399         reg = tilcdc_read(dev, LCDC_RASTER_TIMING_2_REG) & ~0x000fff00;
 400         reg |= LCDC_AC_BIAS_FREQUENCY(info->ac_bias) |
 401                 LCDC_AC_BIAS_TRANSITIONS_PER_INT(info->ac_bias_intrpt);
 402
 403         /*
 404          * subtract one from hfp, hbp, hsw because the hardware uses
 405          * a value of 0 as 1
 406          */
 407         if (priv->rev == 2) {
 408                 /* clear bits we're going to set */
 409                 reg &= ~0x78000033;
 410                 reg |= ((hfp-1) & 0x300) >> 8;
 411                 reg |= ((hbp-1) & 0x300) >> 4;
 412                 reg |= ((hsw-1) & 0x3c0) << 21;
 413         }
 414         tilcdc_write(dev, LCDC_RASTER_TIMING_2_REG, reg);
 415
 416         reg = (((mode->hdisplay >> 4) - 1) << 4) |
 417                 (((hbp-1) & 0xff) << 24) |
 418                 (((hfp-1) & 0xff) << 16) |
 419                 (((hsw-1) & 0x3f) << 10);
 420         if (priv->rev == 2)
 421                 reg |= (((mode->hdisplay >> 4) - 1) & 0x40) >> 3;
 422         tilcdc_write(dev, LCDC_RASTER_TIMING_0_REG, reg);
 423
 424         reg = ((mode->vdisplay - 1) & 0x3ff) |
 425                 ((vbp & 0xff) << 24) |
 426                 ((vfp & 0xff) << 16) |
 427                 (((vsw-1) & 0x3f) << 10);
 428         tilcdc_write(dev, LCDC_RASTER_TIMING_1_REG, reg);
 429
 430         /*
 431          * be sure to set Bit 10 for the V2 LCDC controller,
 432          * otherwise limited to 1024 pixels width, stopping
 433          * 1920x1080 being supported.
 434          */
 435         if (priv->rev == 2) {
 436                 if ((mode->vdisplay - 1) & 0x400) {
 437                         tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG,
 438                                 LCDC_LPP_B10);
 439                 } else {
 440                         tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG,
 441                                 LCDC_LPP_B10);
 442                 }
 443         }
 444
 445         /* Configure display type: */
 446         reg = tilcdc_read(dev, LCDC_RASTER_CTRL_REG) &
 447                 ~(LCDC_TFT_MODE | LCDC_MONO_8BIT_MODE | LCDC_MONOCHROME_MODE |
 448                   LCDC_V2_TFT_24BPP_MODE | LCDC_V2_TFT_24BPP_UNPACK |
 449                   0x000ff000 /* Palette Loading Delay bits */);
 450         reg |= LCDC_TFT_MODE; /* no monochrome/passive support */
 451         if (info->tft_alt_mode)
 452                 reg |= LCDC_TFT_ALT_ENABLE;
 453         if (priv->rev == 2) {
 454                 unsigned int depth, bpp;
 455
 456                 drm_fb_get_bpp_depth(fb->pixel_format, &depth, &bpp);
 457                 switch (bpp) {
 458                 case 16:
 459                         break;
 460                 case 32:
 461                         reg |= LCDC_V2_TFT_24BPP_UNPACK;
 462                         /* fallthrough */
 463                 case 24:
 464                         reg |= LCDC_V2_TFT_24BPP_MODE;
 465                         break;
 466                 default:
 467                         dev_err(dev->dev, "invalid pixel format\n");
 468                         return;
 469                 }
 470         }
 471         reg |= info->fdd < 12;
 472         tilcdc_write(dev, LCDC_RASTER_CTRL_REG, reg);
 473
 474         if (info->invert_pxl_clk)
 475                 tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_PIXEL_CLOCK);
 476         else
 477                 tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_PIXEL_CLOCK);
 478
 479         if (info->sync_ctrl)
 480                 tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_CTRL);
 481         else
 482                 tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_CTRL);
 483
 484         if (info->sync_edge)
 485                 tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_EDGE);
 486         else
 487                 tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_EDGE);
 488
 489         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
 490                 tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_HSYNC);
 491         else
 492                 tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_HSYNC);
 493
 494         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
 495                 tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_VSYNC);
 496         else
 497                 tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_VSYNC);
 498
 499         if (info->raster_order)
 500                 tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ORDER);
 501         else
 502                 tilcdc_clear(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ORDER);
 503
 504         drm_framebuffer_reference(fb);
 505
 506         set_scanout(crtc, fb);
 507
 508         tilcdc_crtc_set_clk(crtc);
 509
 510         crtc->hwmode = crtc->state->adjusted_mode;
 511 }
 512
 513 static int tilcdc_crtc_atomic_check(struct drm_crtc *crtc,
 514                                     struct drm_crtc_state *state)
 515 {
 516         struct drm_display_mode *mode = &state->mode;
 517         int ret;
 518
 519         /* If we are not active we don't care */
 520         if (!state->active)
 521                 return 0;
 522
 523         if (state->state->planes[0].ptr != crtc->primary ||
 524             state->state->planes[0].state == NULL ||
 525             state->state->planes[0].state->crtc != crtc) {
 526                 dev_dbg(crtc->dev->dev, "CRTC primary plane must be present");
 527                 return -EINVAL;
 528         }
 529
 530         ret = tilcdc_crtc_mode_valid(crtc, mode);
 531         if (ret) {
 532                 dev_dbg(crtc->dev->dev, "Mode \"%s\" not valid", mode->name);
 533                 return -EINVAL;
 534         }
 535
 536         return 0;
 537 }
 538
 539 static const struct drm_crtc_funcs tilcdc_crtc_funcs = {
 540         .destroy        = tilcdc_crtc_destroy,
 541         .set_config     = drm_atomic_helper_set_config,
 542         .page_flip      = drm_atomic_helper_page_flip,
 543         .reset          = drm_atomic_helper_crtc_reset,
 544         .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
 545         .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
 546 };
 547
 548 static const struct drm_crtc_helper_funcs tilcdc_crtc_helper_funcs = {
 549                 .mode_fixup     = tilcdc_crtc_mode_fixup,
 550                 .enable         = tilcdc_crtc_enable,
 551                 .disable        = tilcdc_crtc_disable,
 552                 .atomic_check   = tilcdc_crtc_atomic_check,
 553                 .mode_set_nofb  = tilcdc_crtc_mode_set_nofb,
 554 };
 555
 556 int tilcdc_crtc_max_width(struct drm_crtc *crtc)
 557 {
 558         struct drm_device *dev = crtc->dev;
 559         struct tilcdc_drm_private *priv = dev->dev_private;
 560         int max_width = 0;
 561
 562         if (priv->rev == 1)
 563                 max_width = 1024;
 564         else if (priv->rev == 2)
 565                 max_width = 2048;
 566
 567         return max_width;
 568 }
 569
 570 int tilcdc_crtc_mode_valid(struct drm_crtc *crtc, struct drm_display_mode *mode)
 571 {
 572         struct tilcdc_drm_private *priv = crtc->dev->dev_private;
 573         unsigned int bandwidth;
 574         uint32_t hbp, hfp, hsw, vbp, vfp, vsw;
 575
 576         /*
 577          * check to see if the width is within the range that
 578          * the LCD Controller physically supports
 579          */
 580         if (mode->hdisplay > tilcdc_crtc_max_width(crtc))
 581                 return MODE_VIRTUAL_X;
 582
 583         /* width must be multiple of 16 */
 584         if (mode->hdisplay & 0xf)
 585                 return MODE_VIRTUAL_X;
 586
 587         if (mode->vdisplay > 2048)
 588                 return MODE_VIRTUAL_Y;
 589
 590         DBG("Processing mode %dx%d@%d with pixel clock %d",
 591                 mode->hdisplay, mode->vdisplay,
 592                 drm_mode_vrefresh(mode), mode->clock);
 593
 594         hbp = mode->htotal - mode->hsync_end;
 595         hfp = mode->hsync_start - mode->hdisplay;
 596         hsw = mode->hsync_end - mode->hsync_start;
 597         vbp = mode->vtotal - mode->vsync_end;
 598         vfp = mode->vsync_start - mode->vdisplay;
 599         vsw = mode->vsync_end - mode->vsync_start;
 600
 601         if ((hbp-1) & ~0x3ff) {
 602                 DBG("Pruning mode: Horizontal Back Porch out of range");
 603                 return MODE_HBLANK_WIDE;
 604         }
 605
 606         if ((hfp-1) & ~0x3ff) {
 607                 DBG("Pruning mode: Horizontal Front Porch out of range");
 608                 return MODE_HBLANK_WIDE;
 609         }
 610
 611         if ((hsw-1) & ~0x3ff) {
 612                 DBG("Pruning mode: Horizontal Sync Width out of range");
 613                 return MODE_HSYNC_WIDE;
 614         }
 615
 616         if (vbp & ~0xff) {
 617                 DBG("Pruning mode: Vertical Back Porch out of range");
 618                 return MODE_VBLANK_WIDE;
 619         }
 620
 621         if (vfp & ~0xff) {
 622                 DBG("Pruning mode: Vertical Front Porch out of range");
 623                 return MODE_VBLANK_WIDE;
 624         }
 625
 626         if ((vsw-1) & ~0x3f) {
 627                 DBG("Pruning mode: Vertical Sync Width out of range");
 628                 return MODE_VSYNC_WIDE;
 629         }
 630
 631         /*
 632          * some devices have a maximum allowed pixel clock
 633          * configured from the DT
 634          */
 635         if (mode->clock > priv->max_pixelclock) {
 636                 DBG("Pruning mode: pixel clock too high");
 637                 return MODE_CLOCK_HIGH;
 638         }
 639
 640         /*
 641          * some devices further limit the max horizontal resolution
 642          * configured from the DT
 643          */
 644         if (mode->hdisplay > priv->max_width)
 645                 return MODE_BAD_WIDTH;
 646
 647         /* filter out modes that would require too much memory bandwidth: */
 648         bandwidth = mode->hdisplay * mode->vdisplay *
 649                 drm_mode_vrefresh(mode);
 650         if (bandwidth > priv->max_bandwidth) {
 651                 DBG("Pruning mode: exceeds defined bandwidth limit");
 652                 return MODE_BAD;
 653         }
 654
 655         return MODE_OK;
 656 }
 657
 658 void tilcdc_crtc_set_panel_info(struct drm_crtc *crtc,
 659                 const struct tilcdc_panel_info *info)
 660 {
 661         struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
 662         tilcdc_crtc->info = info;
 663 }
 664
 665 void tilcdc_crtc_set_simulate_vesa_sync(struct drm_crtc *crtc,
 666                                         bool simulate_vesa_sync)
 667 {
 668         struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
 669
 670         tilcdc_crtc->simulate_vesa_sync = simulate_vesa_sync;
 671 }
 672
 673 void tilcdc_crtc_update_clk(struct drm_crtc *crtc)
 674 {
 675         struct drm_device *dev = crtc->dev;
 676         struct tilcdc_drm_private *priv = dev->dev_private;
 677         struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
 678
 679         drm_modeset_lock_crtc(crtc, NULL);
 680         if (tilcdc_crtc->lcd_fck_rate != clk_get_rate(priv->clk)) {
 681                 if (tilcdc_crtc_is_on(crtc)) {
 682                         pm_runtime_get_sync(dev->dev);
 683                         tilcdc_crtc_disable(crtc);
 684
 685                         tilcdc_crtc_set_clk(crtc);
 686
 687                         tilcdc_crtc_enable(crtc);
 688                         pm_runtime_put_sync(dev->dev);
 689                 }
 690         }
 691         drm_modeset_unlock_crtc(crtc);
 692 }
 693
 694 #define SYNC_LOST_COUNT_LIMIT 50
 695
 696 irqreturn_t tilcdc_crtc_irq(struct drm_crtc *crtc)
 697 {
 698         struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
 699         struct drm_device *dev = crtc->dev;
 700         struct tilcdc_drm_private *priv = dev->dev_private;
 701         uint32_t stat;
 702
 703         stat = tilcdc_read_irqstatus(dev);
 704         tilcdc_clear_irqstatus(dev, stat);
 705
 706         if (stat & LCDC_END_OF_FRAME0) {
 707                 unsigned long flags;
 708                 bool skip_event = false;
 709                 ktime_t now;
 710
 711                 now = ktime_get();
 712
 713                 drm_flip_work_commit(&tilcdc_crtc->unref_work, priv->wq);
 714
 715                 spin_lock_irqsave(&tilcdc_crtc->irq_lock, flags);
 716
 717                 tilcdc_crtc->last_vblank = now;
 718
 719                 if (tilcdc_crtc->next_fb) {
 720                         set_scanout(crtc, tilcdc_crtc->next_fb);
 721                         tilcdc_crtc->next_fb = NULL;
 722                         skip_event = true;
 723                 }
 724
 725                 spin_unlock_irqrestore(&tilcdc_crtc->irq_lock, flags);
 726
 727                 drm_crtc_handle_vblank(crtc);
 728
 729                 if (!skip_event) {
 730                         struct drm_pending_vblank_event *event;
 731
 732                         spin_lock_irqsave(&dev->event_lock, flags);
 733
 734                         event = tilcdc_crtc->event;
 735                         tilcdc_crtc->event = NULL;
 736                         if (event)
 737                                 drm_crtc_send_vblank_event(crtc, event);
 738
 739                         spin_unlock_irqrestore(&dev->event_lock, flags);
 740                 }
 741
 742                 if (tilcdc_crtc->frame_intact)
 743                         tilcdc_crtc->sync_lost_count = 0;
 744                 else
 745                         tilcdc_crtc->frame_intact = true;
 746         }
 747
 748         if (stat & LCDC_FIFO_UNDERFLOW)
 749                 dev_err_ratelimited(dev->dev, "%s(0x%08x): FIFO underfow",
 750                                     __func__, stat);
 751
 752         /* For revision 2 only */
 753         if (priv->rev == 2) {
 754                 if (stat & LCDC_FRAME_DONE) {
 755                         tilcdc_crtc->frame_done = true;
 756                         wake_up(&tilcdc_crtc->frame_done_wq);
 757                 }
 758
 759                 if (stat & LCDC_SYNC_LOST) {
 760                         dev_err_ratelimited(dev->dev, "%s(0x%08x): Sync lost",
 761                                             __func__, stat);
 762                         tilcdc_crtc->frame_intact = false;
 763                         if (tilcdc_crtc->sync_lost_count++ >
 764                             SYNC_LOST_COUNT_LIMIT) {
 765                                 dev_err(dev->dev, "%s(0x%08x): Sync lost flood detected, disabling the interrupt", __func__, stat);
 766                                 tilcdc_write(dev, LCDC_INT_ENABLE_CLR_REG,
 767                                              LCDC_SYNC_LOST);
 768                         }
 769                 }
 770
 771                 /* Indicate to LCDC that the interrupt service routine has
 772                  * completed, see 13.3.6.1.6 in AM335x TRM.
 773                  */
 774                 tilcdc_write(dev, LCDC_END_OF_INT_IND_REG, 0);
 775         }
 776
 777         return IRQ_HANDLED;
 778 }
 779
 780 struct drm_crtc *tilcdc_crtc_create(struct drm_device *dev)
 781 {
 782         struct tilcdc_drm_private *priv = dev->dev_private;
 783         struct tilcdc_crtc *tilcdc_crtc;
 784         struct drm_crtc *crtc;
 785         int ret;
 786
 787         tilcdc_crtc = devm_kzalloc(dev->dev, sizeof(*tilcdc_crtc), GFP_KERNEL);
 788         if (!tilcdc_crtc) {
 789                 dev_err(dev->dev, "allocation failed\n");
 790                 return NULL;
 791         }
 792
 793         crtc = &tilcdc_crtc->base;
 794
 795         ret = tilcdc_plane_init(dev, &tilcdc_crtc->primary);
 796         if (ret < 0)
 797                 goto fail;
 798
 799         init_waitqueue_head(&tilcdc_crtc->frame_done_wq);
 800
 801         drm_flip_work_init(&tilcdc_crtc->unref_work,
 802                         "unref", unref_worker);
 803
 804         spin_lock_init(&tilcdc_crtc->irq_lock);
 805
 806         ret = drm_crtc_init_with_planes(dev, crtc,
 807                                         &tilcdc_crtc->primary,
 808                                         NULL,
 809                                         &tilcdc_crtc_funcs,
 810                                         "tilcdc crtc");
 811         if (ret < 0)
 812                 goto fail;
 813
 814         drm_crtc_helper_add(crtc, &tilcdc_crtc_helper_funcs);
 815
 816         if (priv->is_componentized) {
 817                 struct device_node *ports =
 818                         of_get_child_by_name(dev->dev->of_node, "ports");
 819
 820                 if (ports) {
 821                         crtc->port = of_get_child_by_name(ports, "port");
 822                         of_node_put(ports);
 823                 } else {
 824                         crtc->port =
 825                                 of_get_child_by_name(dev->dev->of_node, "port");
 826                 }
 827                 if (!crtc->port) { /* This should never happen */
 828                         dev_err(dev->dev, "Port node not found in %s\n",
 829                                 dev->dev->of_node->full_name);
 830                         goto fail;
 831                 }
 832         }
 833
 834         return crtc;
 835
 836 fail:
 837         tilcdc_crtc_destroy(crtc);
 838         return NULL;
 839 }