drivers/gpu/drm/tilcdc/tilcdc_crtc.c

   1 /*
   2  * Copyright (C) 2012 Texas Instruments
   3  * Author: Rob Clark <robdclark@gmail.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 as published by
   7  * the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program.  If not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18 #include <drm/drm_atomic.h>
  19 #include <drm/drm_atomic_helper.h>
  20 #include <drm/drm_crtc.h>
  21 #include <drm/drm_flip_work.h>
  22 #include <drm/drm_plane_helper.h>
  23 #include <linux/workqueue.h>
  24 #include <linux/completion.h>
  25 #include <linux/dma-mapping.h>
  26
  27 #include "tilcdc_drv.h"
  28 #include "tilcdc_regs.h"
  29
  30 #define TILCDC_VBLANK_SAFETY_THRESHOLD_US       1000
  31 #define TILCDC_PALETTE_SIZE                     32
  32 #define TILCDC_PALETTE_FIRST_ENTRY              0x4000
  33
  34 struct tilcdc_crtc {
  35         struct drm_crtc base;
  36
  37         struct drm_plane primary;
  38         const struct tilcdc_panel_info *info;
  39         struct drm_pending_vblank_event *event;
  40         struct mutex enable_lock;
  41         bool enabled;
  42         bool shutdown;
  43         wait_queue_head_t frame_done_wq;
  44         bool frame_done;
  45         spinlock_t irq_lock;
  46
  47         unsigned int lcd_fck_rate;
  48
  49         ktime_t last_vblank;
  50
  51         struct drm_framebuffer *curr_fb;
  52         struct drm_framebuffer *next_fb;
  53
  54         /* for deferred fb unref's: */
  55         struct drm_flip_work unref_work;
  56
  57         /* Only set if an external encoder is connected */
  58         bool simulate_vesa_sync;
  59
  60         int sync_lost_count;
  61         bool frame_intact;
  62         struct work_struct recover_work;
  63
  64         dma_addr_t palette_dma_handle;
  65         u16 *palette_base;
  66         struct completion palette_loaded;
  67 };
  68 #define to_tilcdc_crtc(x) container_of(x, struct tilcdc_crtc, base)
  69
  70 static void unref_worker(struct drm_flip_work *work, void *val)
  71 {
  72         struct tilcdc_crtc *tilcdc_crtc =
  73                 container_of(work, struct tilcdc_crtc, unref_work);
  74         struct drm_device *dev = tilcdc_crtc->base.dev;
  75
  76         mutex_lock(&dev->mode_config.mutex);
  77         drm_framebuffer_unreference(val);
  78         mutex_unlock(&dev->mode_config.mutex);
  79 }
  80
  81 static void set_scanout(struct drm_crtc *crtc, struct drm_framebuffer *fb)
  82 {
  83         struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
  84         struct drm_device *dev = crtc->dev;
  85         struct tilcdc_drm_private *priv = dev->dev_private;
  86         struct drm_gem_cma_object *gem;
  87         dma_addr_t start, end;
  88         u64 dma_base_and_ceiling;
  89
  90         gem = drm_fb_cma_get_gem_obj(fb, 0);
  91
  92         start = gem->paddr + fb->offsets[0] +
  93                 crtc->y * fb->pitches[0] +
  94                 crtc->x * drm_format_plane_cpp(fb->pixel_format, 0);
  95
  96         end = start + (crtc->mode.vdisplay * fb->pitches[0]);
  97
  98         /* Write LCDC_DMA_FB_BASE_ADDR_0_REG and LCDC_DMA_FB_CEILING_ADDR_0_REG
  99          * with a single insruction, if available. This should make it more
 100          * unlikely that LCDC would fetch the DMA addresses in the middle of
 101          * an update.
 102          */
 103         if (priv->rev == 1)
 104                 end -= 1;
 105
 106         dma_base_and_ceiling = (u64)end << 32 | start;
 107         tilcdc_write64(dev, LCDC_DMA_FB_BASE_ADDR_0_REG, dma_base_and_ceiling);
 108
 109         if (tilcdc_crtc->curr_fb)
 110                 drm_flip_work_queue(&tilcdc_crtc->unref_work,
 111                         tilcdc_crtc->curr_fb);
 112
 113         tilcdc_crtc->curr_fb = fb;
 114 }
 115
 116 /*
 117  * The driver currently only supports only true color formats. For
 118  * true color the palette block is bypassed, but a 32 byte palette
 119  * should still be loaded. The first 16-bit entry must be 0x4000 while
 120  * all other entries must be zeroed.
 121  */
 122 static void tilcdc_crtc_load_palette(struct drm_crtc *crtc)
 123 {
 124         u32 dma_fb_base, dma_fb_ceiling, raster_ctl;
 125         struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
 126         struct drm_device *dev = crtc->dev;
 127         struct tilcdc_drm_private *priv = dev->dev_private;
 128
 129         dma_fb_base = tilcdc_read(dev, LCDC_DMA_FB_BASE_ADDR_0_REG);
 130         dma_fb_ceiling = tilcdc_read(dev, LCDC_DMA_FB_CEILING_ADDR_0_REG);
 131         raster_ctl = tilcdc_read(dev, LCDC_RASTER_CTRL_REG);
 132
 133         /* Tell the LCDC where the palette is located. */
 134         tilcdc_write(dev, LCDC_DMA_FB_BASE_ADDR_0_REG,
 135                      tilcdc_crtc->palette_dma_handle);
 136         tilcdc_write(dev, LCDC_DMA_FB_CEILING_ADDR_0_REG,
 137                      (u32) tilcdc_crtc->palette_dma_handle +
 138                      TILCDC_PALETTE_SIZE - 1);
 139
 140         /* Set dma load mode for palette loading only. */
 141         tilcdc_write_mask(dev, LCDC_RASTER_CTRL_REG,
 142                           LCDC_PALETTE_LOAD_MODE(PALETTE_ONLY),
 143                           LCDC_PALETTE_LOAD_MODE_MASK);
 144
 145         /* Enable DMA Palette Loaded Interrupt */
 146         if (priv->rev == 1)
 147                 tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_V1_PL_INT_ENA);
 148         else
 149                 tilcdc_write(dev, LCDC_INT_ENABLE_SET_REG, LCDC_V2_PL_INT_ENA);
 150
 151         /* Enable LCDC DMA and wait for palette to be loaded. */
 152         tilcdc_clear_irqstatus(dev, 0xffffffff);
 153         tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ENABLE);
 154
 155         wait_for_completion(&tilcdc_crtc->palette_loaded);
 156
 157         /* Disable LCDC DMA and DMA Palette Loaded Interrupt. */
 158         tilcdc_clear(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ENABLE);
 159         if (priv->rev == 1)
 160                 tilcdc_clear(dev, LCDC_RASTER_CTRL_REG, LCDC_V1_PL_INT_ENA);
 161         else
 162                 tilcdc_write(dev, LCDC_INT_ENABLE_CLR_REG, LCDC_V2_PL_INT_ENA);
 163
 164         /* Restore the registers. */
 165         tilcdc_write(dev, LCDC_DMA_FB_BASE_ADDR_0_REG, dma_fb_base);
 166         tilcdc_write(dev, LCDC_DMA_FB_CEILING_ADDR_0_REG, dma_fb_ceiling);
 167         tilcdc_write(dev, LCDC_RASTER_CTRL_REG, raster_ctl);
 168 }
 169
 170 static void tilcdc_crtc_enable_irqs(struct drm_device *dev)
 171 {
 172         struct tilcdc_drm_private *priv = dev->dev_private;
 173
 174         tilcdc_clear_irqstatus(dev, 0xffffffff);
 175
 176         if (priv->rev == 1) {
 177                 tilcdc_set(dev, LCDC_RASTER_CTRL_REG,
 178                         LCDC_V1_SYNC_LOST_INT_ENA |
 179                         LCDC_V1_UNDERFLOW_INT_ENA);
 180                 tilcdc_set(dev, LCDC_DMA_CTRL_REG,
 181                         LCDC_V1_END_OF_FRAME_INT_ENA);
 182         } else {
 183                 tilcdc_write(dev, LCDC_INT_ENABLE_SET_REG,
 184                         LCDC_V2_UNDERFLOW_INT_ENA |
 185                         LCDC_V2_END_OF_FRAME0_INT_ENA |
 186                         LCDC_FRAME_DONE | LCDC_SYNC_LOST);
 187         }
 188 }
 189
 190 static void tilcdc_crtc_disable_irqs(struct drm_device *dev)
 191 {
 192         struct tilcdc_drm_private *priv = dev->dev_private;
 193
 194         /* disable irqs that we might have enabled: */
 195         if (priv->rev == 1) {
 196                 tilcdc_clear(dev, LCDC_RASTER_CTRL_REG,
 197                         LCDC_V1_SYNC_LOST_INT_ENA |
 198                         LCDC_V1_UNDERFLOW_INT_ENA | LCDC_V1_PL_INT_ENA);
 199                 tilcdc_clear(dev, LCDC_DMA_CTRL_REG,
 200                         LCDC_V1_END_OF_FRAME_INT_ENA);
 201         } else {
 202                 tilcdc_write(dev, LCDC_INT_ENABLE_CLR_REG,
 203                         LCDC_V2_UNDERFLOW_INT_ENA | LCDC_V2_PL_INT_ENA |
 204                         LCDC_V2_END_OF_FRAME0_INT_ENA |
 205                         LCDC_FRAME_DONE | LCDC_SYNC_LOST);
 206         }
 207 }
 208
 209 static void reset(struct drm_crtc *crtc)
 210 {
 211         struct drm_device *dev = crtc->dev;
 212         struct tilcdc_drm_private *priv = dev->dev_private;
 213
 214         if (priv->rev != 2)
 215                 return;
 216
 217         tilcdc_set(dev, LCDC_CLK_RESET_REG, LCDC_CLK_MAIN_RESET);
 218         usleep_range(250, 1000);
 219         tilcdc_clear(dev, LCDC_CLK_RESET_REG, LCDC_CLK_MAIN_RESET);
 220 }
 221
 222 static void tilcdc_crtc_enable(struct drm_crtc *crtc)
 223 {
 224         struct drm_device *dev = crtc->dev;
 225         struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
 226
 227         WARN_ON(!drm_modeset_is_locked(&crtc->mutex));
 228         mutex_lock(&tilcdc_crtc->enable_lock);
 229         if (tilcdc_crtc->enabled || tilcdc_crtc->shutdown) {
 230                 mutex_unlock(&tilcdc_crtc->enable_lock);
 231                 return;
 232         }
 233
 234         pm_runtime_get_sync(dev->dev);
 235
 236         reset(crtc);
 237
 238         if (!completion_done(&tilcdc_crtc->palette_loaded))
 239                 tilcdc_crtc_load_palette(crtc);
 240
 241         tilcdc_crtc_enable_irqs(dev);
 242
 243         tilcdc_clear(dev, LCDC_DMA_CTRL_REG, LCDC_DUAL_FRAME_BUFFER_ENABLE);
 244         tilcdc_write_mask(dev, LCDC_RASTER_CTRL_REG,
 245                           LCDC_PALETTE_LOAD_MODE(DATA_ONLY),
 246                           LCDC_PALETTE_LOAD_MODE_MASK);
 247         tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ENABLE);
 248
 249         drm_crtc_vblank_on(crtc);
 250
 251         tilcdc_crtc->enabled = true;
 252         mutex_unlock(&tilcdc_crtc->enable_lock);
 253 }
 254
 255 static void tilcdc_crtc_off(struct drm_crtc *crtc, bool shutdown)
 256 {
 257         struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
 258         struct drm_device *dev = crtc->dev;
 259         struct tilcdc_drm_private *priv = dev->dev_private;
 260
 261         mutex_lock(&tilcdc_crtc->enable_lock);
 262         if (shutdown)
 263                 tilcdc_crtc->shutdown = true;
 264         if (!tilcdc_crtc->enabled) {
 265                 mutex_unlock(&tilcdc_crtc->enable_lock);
 266                 return;
 267         }
 268         tilcdc_crtc->frame_done = false;
 269         tilcdc_clear(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ENABLE);
 270
 271         /*
 272          * if necessary wait for framedone irq which will still come
 273          * before putting things to sleep..
 274          */
 275         if (priv->rev == 2) {
 276                 int ret = wait_event_timeout(tilcdc_crtc->frame_done_wq,
 277                                              tilcdc_crtc->frame_done,
 278                                              msecs_to_jiffies(500));
 279                 if (ret == 0)
 280                         dev_err(dev->dev, "%s: timeout waiting for framedone\n",
 281                                 __func__);
 282         }
 283
 284         /*
 285          * LCDC will not retain the palette when reset. Make sure it gets
 286          * reloaded on tilcdc_crtc_enable().
 287          */
 288         reinit_completion(&tilcdc_crtc->palette_loaded);
 289
 290         drm_crtc_vblank_off(crtc);
 291
 292         tilcdc_crtc_disable_irqs(dev);
 293
 294         pm_runtime_put_sync(dev->dev);
 295
 296         if (tilcdc_crtc->next_fb) {
 297                 drm_flip_work_queue(&tilcdc_crtc->unref_work,
 298                                     tilcdc_crtc->next_fb);
 299                 tilcdc_crtc->next_fb = NULL;
 300         }
 301
 302         if (tilcdc_crtc->curr_fb) {
 303                 drm_flip_work_queue(&tilcdc_crtc->unref_work,
 304                                     tilcdc_crtc->curr_fb);
 305                 tilcdc_crtc->curr_fb = NULL;
 306         }
 307
 308         drm_flip_work_commit(&tilcdc_crtc->unref_work, priv->wq);
 309         tilcdc_crtc->last_vblank = ktime_set(0, 0);
 310
 311         tilcdc_crtc->enabled = false;
 312         mutex_unlock(&tilcdc_crtc->enable_lock);
 313 }
 314
 315 static void tilcdc_crtc_disable(struct drm_crtc *crtc)
 316 {
 317         WARN_ON(!drm_modeset_is_locked(&crtc->mutex));
 318         tilcdc_crtc_off(crtc, false);
 319 }
 320
 321 void tilcdc_crtc_shutdown(struct drm_crtc *crtc)
 322 {
 323         tilcdc_crtc_off(crtc, true);
 324 }
 325
 326 static bool tilcdc_crtc_is_on(struct drm_crtc *crtc)
 327 {
 328         return crtc->state && crtc->state->enable && crtc->state->active;
 329 }
 330
 331 static void tilcdc_crtc_recover_work(struct work_struct *work)
 332 {
 333         struct tilcdc_crtc *tilcdc_crtc =
 334                 container_of(work, struct tilcdc_crtc, recover_work);
 335         struct drm_crtc *crtc = &tilcdc_crtc->base;
 336
 337         dev_info(crtc->dev->dev, "%s: Reset CRTC", __func__);
 338
 339         drm_modeset_lock_crtc(crtc, NULL);
 340
 341         if (!tilcdc_crtc_is_on(crtc))
 342                 goto out;
 343
 344         tilcdc_crtc_disable(crtc);
 345         tilcdc_crtc_enable(crtc);
 346 out:
 347         drm_modeset_unlock_crtc(crtc);
 348 }
 349
 350 static void tilcdc_crtc_destroy(struct drm_crtc *crtc)
 351 {
 352         struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
 353         struct tilcdc_drm_private *priv = crtc->dev->dev_private;
 354
 355         drm_modeset_lock_crtc(crtc, NULL);
 356         tilcdc_crtc_disable(crtc);
 357         drm_modeset_unlock_crtc(crtc);
 358
 359         flush_workqueue(priv->wq);
 360
 361         of_node_put(crtc->port);
 362         drm_crtc_cleanup(crtc);
 363         drm_flip_work_cleanup(&tilcdc_crtc->unref_work);
 364 }
 365
 366 int tilcdc_crtc_update_fb(struct drm_crtc *crtc,
 367                 struct drm_framebuffer *fb,
 368                 struct drm_pending_vblank_event *event)
 369 {
 370         struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
 371         struct drm_device *dev = crtc->dev;
 372         unsigned long flags;
 373
 374         WARN_ON(!drm_modeset_is_locked(&crtc->mutex));
 375
 376         if (tilcdc_crtc->event) {
 377                 dev_err(dev->dev, "already pending page flip!\n");
 378                 return -EBUSY;
 379         }
 380
 381         drm_framebuffer_reference(fb);
 382
 383         crtc->primary->fb = fb;
 384
 385         spin_lock_irqsave(&tilcdc_crtc->irq_lock, flags);
 386
 387         if (crtc->hwmode.vrefresh && ktime_to_ns(tilcdc_crtc->last_vblank)) {
 388                 ktime_t next_vblank;
 389                 s64 tdiff;
 390
 391                 next_vblank = ktime_add_us(tilcdc_crtc->last_vblank,
 392                         1000000 / crtc->hwmode.vrefresh);
 393
 394                 tdiff = ktime_to_us(ktime_sub(next_vblank, ktime_get()));
 395
 396                 if (tdiff < TILCDC_VBLANK_SAFETY_THRESHOLD_US)
 397                         tilcdc_crtc->next_fb = fb;
 398         }
 399
 400         if (tilcdc_crtc->next_fb != fb)
 401                 set_scanout(crtc, fb);
 402
 403         tilcdc_crtc->event = event;
 404
 405         spin_unlock_irqrestore(&tilcdc_crtc->irq_lock, flags);
 406
 407         return 0;
 408 }
 409
 410 static bool tilcdc_crtc_mode_fixup(struct drm_crtc *crtc,
 411                 const struct drm_display_mode *mode,
 412                 struct drm_display_mode *adjusted_mode)
 413 {
 414         struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
 415
 416         if (!tilcdc_crtc->simulate_vesa_sync)
 417                 return true;
 418
 419         /*
 420          * tilcdc does not generate VESA-compliant sync but aligns
 421          * VS on the second edge of HS instead of first edge.
 422          * We use adjusted_mode, to fixup sync by aligning both rising
 423          * edges and add HSKEW offset to fix the sync.
 424          */
 425         adjusted_mode->hskew = mode->hsync_end - mode->hsync_start;
 426         adjusted_mode->flags |= DRM_MODE_FLAG_HSKEW;
 427
 428         if (mode->flags & DRM_MODE_FLAG_NHSYNC) {
 429                 adjusted_mode->flags |= DRM_MODE_FLAG_PHSYNC;
 430                 adjusted_mode->flags &= ~DRM_MODE_FLAG_NHSYNC;
 431         } else {
 432                 adjusted_mode->flags |= DRM_MODE_FLAG_NHSYNC;
 433                 adjusted_mode->flags &= ~DRM_MODE_FLAG_PHSYNC;
 434         }
 435
 436         return true;
 437 }
 438
 439 /*
 440  * Calculate the percentage difference between the requested pixel clock rate
 441  * and the effective rate resulting from calculating the clock divider value.
 442  */
 443 static unsigned int tilcdc_pclk_diff(unsigned long rate,
 444                                      unsigned long real_rate)
 445 {
 446         int r = rate / 100, rr = real_rate / 100;
 447
 448         return (unsigned int)(abs(((rr - r) * 100) / r));
 449 }
 450
 451 static void tilcdc_crtc_set_clk(struct drm_crtc *crtc)
 452 {
 453         struct drm_device *dev = crtc->dev;
 454         struct tilcdc_drm_private *priv = dev->dev_private;
 455         struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
 456         unsigned long clk_rate, real_rate, req_rate;
 457         unsigned int clkdiv;
 458         int ret;
 459
 460         clkdiv = 2; /* first try using a standard divider of 2 */
 461
 462         /* mode.clock is in KHz, set_rate wants parameter in Hz */
 463         req_rate = crtc->mode.clock * 1000;
 464
 465         ret = clk_set_rate(priv->clk, req_rate * clkdiv);
 466         clk_rate = clk_get_rate(priv->clk);
 467         if (ret < 0) {
 468                 /*
 469                  * If we fail to set the clock rate (some architectures don't
 470                  * use the common clock framework yet and may not implement
 471                  * all the clk API calls for every clock), try the next best
 472                  * thing: adjusting the clock divider, unless clk_get_rate()
 473                  * failed as well.
 474                  */
 475                 if (!clk_rate) {
 476                         /* Nothing more we can do. Just bail out. */
 477                         dev_err(dev->dev,
 478                                 "failed to set the pixel clock - unable to read current lcdc clock rate\n");
 479                         return;
 480                 }
 481
 482                 clkdiv = DIV_ROUND_CLOSEST(clk_rate, req_rate);
 483
 484                 /*
 485                  * Emit a warning if the real clock rate resulting from the
 486                  * calculated divider differs much from the requested rate.
 487                  *
 488                  * 5% is an arbitrary value - LCDs are usually quite tolerant
 489                  * about pixel clock rates.
 490                  */
 491                 real_rate = clkdiv * req_rate;
 492
 493                 if (tilcdc_pclk_diff(clk_rate, real_rate) > 5) {
 494                         dev_warn(dev->dev,
 495                                  "effective pixel clock rate (%luHz) differs from the calculated rate (%luHz)\n",
 496                                  clk_rate, real_rate);
 497                 }
 498         }
 499
 500         tilcdc_crtc->lcd_fck_rate = clk_rate;
 501
 502         DBG("lcd_clk=%u, mode clock=%d, div=%u",
 503             tilcdc_crtc->lcd_fck_rate, crtc->mode.clock, clkdiv);
 504
 505         /* Configure the LCD clock divisor. */
 506         tilcdc_write(dev, LCDC_CTRL_REG, LCDC_CLK_DIVISOR(clkdiv) |
 507                      LCDC_RASTER_MODE);
 508
 509         if (priv->rev == 2)
 510                 tilcdc_set(dev, LCDC_CLK_ENABLE_REG,
 511                                 LCDC_V2_DMA_CLK_EN | LCDC_V2_LIDD_CLK_EN |
 512                                 LCDC_V2_CORE_CLK_EN);
 513 }
 514
 515 static void tilcdc_crtc_mode_set_nofb(struct drm_crtc *crtc)
 516 {
 517         struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
 518         struct drm_device *dev = crtc->dev;
 519         struct tilcdc_drm_private *priv = dev->dev_private;
 520         const struct tilcdc_panel_info *info = tilcdc_crtc->info;
 521         uint32_t reg, hbp, hfp, hsw, vbp, vfp, vsw;
 522         struct drm_display_mode *mode = &crtc->state->adjusted_mode;
 523         struct drm_framebuffer *fb = crtc->primary->state->fb;
 524
 525         WARN_ON(!drm_modeset_is_locked(&crtc->mutex));
 526
 527         if (WARN_ON(!info))
 528                 return;
 529
 530         if (WARN_ON(!fb))
 531                 return;
 532
 533         /* Configure the Burst Size and fifo threshold of DMA: */
 534         reg = tilcdc_read(dev, LCDC_DMA_CTRL_REG) & ~0x00000770;
 535         switch (info->dma_burst_sz) {
 536         case 1:
 537                 reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_1);
 538                 break;
 539         case 2:
 540                 reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_2);
 541                 break;
 542         case 4:
 543                 reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_4);
 544                 break;
 545         case 8:
 546                 reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_8);
 547                 break;
 548         case 16:
 549                 reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_16);
 550                 break;
 551         default:
 552                 dev_err(dev->dev, "invalid burst size\n");
 553                 return;
 554         }
 555         reg |= (info->fifo_th << 8);
 556         tilcdc_write(dev, LCDC_DMA_CTRL_REG, reg);
 557
 558         /* Configure timings: */
 559         hbp = mode->htotal - mode->hsync_end;
 560         hfp = mode->hsync_start - mode->hdisplay;
 561         hsw = mode->hsync_end - mode->hsync_start;
 562         vbp = mode->vtotal - mode->vsync_end;
 563         vfp = mode->vsync_start - mode->vdisplay;
 564         vsw = mode->vsync_end - mode->vsync_start;
 565
 566         DBG("%dx%d, hbp=%u, hfp=%u, hsw=%u, vbp=%u, vfp=%u, vsw=%u",
 567             mode->hdisplay, mode->vdisplay, hbp, hfp, hsw, vbp, vfp, vsw);
 568
 569         /* Set AC Bias Period and Number of Transitions per Interrupt: */
 570         reg = tilcdc_read(dev, LCDC_RASTER_TIMING_2_REG) & ~0x000fff00;
 571         reg |= LCDC_AC_BIAS_FREQUENCY(info->ac_bias) |
 572                 LCDC_AC_BIAS_TRANSITIONS_PER_INT(info->ac_bias_intrpt);
 573
 574         /*
 575          * subtract one from hfp, hbp, hsw because the hardware uses
 576          * a value of 0 as 1
 577          */
 578         if (priv->rev == 2) {
 579                 /* clear bits we're going to set */
 580                 reg &= ~0x78000033;
 581                 reg |= ((hfp-1) & 0x300) >> 8;
 582                 reg |= ((hbp-1) & 0x300) >> 4;
 583                 reg |= ((hsw-1) & 0x3c0) << 21;
 584         }
 585         tilcdc_write(dev, LCDC_RASTER_TIMING_2_REG, reg);
 586
 587         reg = (((mode->hdisplay >> 4) - 1) << 4) |
 588                 (((hbp-1) & 0xff) << 24) |
 589                 (((hfp-1) & 0xff) << 16) |
 590                 (((hsw-1) & 0x3f) << 10);
 591         if (priv->rev == 2)
 592                 reg |= (((mode->hdisplay >> 4) - 1) & 0x40) >> 3;
 593         tilcdc_write(dev, LCDC_RASTER_TIMING_0_REG, reg);
 594
 595         reg = ((mode->vdisplay - 1) & 0x3ff) |
 596                 ((vbp & 0xff) << 24) |
 597                 ((vfp & 0xff) << 16) |
 598                 (((vsw-1) & 0x3f) << 10);
 599         tilcdc_write(dev, LCDC_RASTER_TIMING_1_REG, reg);
 600
 601         /*
 602          * be sure to set Bit 10 for the V2 LCDC controller,
 603          * otherwise limited to 1024 pixels width, stopping
 604          * 1920x1080 being supported.
 605          */
 606         if (priv->rev == 2) {
 607                 if ((mode->vdisplay - 1) & 0x400) {
 608                         tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG,
 609                                 LCDC_LPP_B10);
 610                 } else {
 611                         tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG,
 612                                 LCDC_LPP_B10);
 613                 }
 614         }
 615
 616         /* Configure display type: */
 617         reg = tilcdc_read(dev, LCDC_RASTER_CTRL_REG) &
 618                 ~(LCDC_TFT_MODE | LCDC_MONO_8BIT_MODE | LCDC_MONOCHROME_MODE |
 619                   LCDC_V2_TFT_24BPP_MODE | LCDC_V2_TFT_24BPP_UNPACK |
 620                   0x000ff000 /* Palette Loading Delay bits */);
 621         reg |= LCDC_TFT_MODE; /* no monochrome/passive support */
 622         if (info->tft_alt_mode)
 623                 reg |= LCDC_TFT_ALT_ENABLE;
 624         if (priv->rev == 2) {
 625                 switch (fb->pixel_format) {
 626                 case DRM_FORMAT_BGR565:
 627                 case DRM_FORMAT_RGB565:
 628                         break;
 629                 case DRM_FORMAT_XBGR8888:
 630                 case DRM_FORMAT_XRGB8888:
 631                         reg |= LCDC_V2_TFT_24BPP_UNPACK;
 632                         /* fallthrough */
 633                 case DRM_FORMAT_BGR888:
 634                 case DRM_FORMAT_RGB888:
 635                         reg |= LCDC_V2_TFT_24BPP_MODE;
 636                         break;
 637                 default:
 638                         dev_err(dev->dev, "invalid pixel format\n");
 639                         return;
 640                 }
 641         }
 642         reg |= info->fdd < 12;
 643         tilcdc_write(dev, LCDC_RASTER_CTRL_REG, reg);
 644
 645         if (info->invert_pxl_clk)
 646                 tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_PIXEL_CLOCK);
 647         else
 648                 tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_PIXEL_CLOCK);
 649
 650         if (info->sync_ctrl)
 651                 tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_CTRL);
 652         else
 653                 tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_CTRL);
 654
 655         if (info->sync_edge)
 656                 tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_EDGE);
 657         else
 658                 tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_EDGE);
 659
 660         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
 661                 tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_HSYNC);
 662         else
 663                 tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_HSYNC);
 664
 665         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
 666                 tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_VSYNC);
 667         else
 668                 tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_VSYNC);
 669
 670         if (info->raster_order)
 671                 tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ORDER);
 672         else
 673                 tilcdc_clear(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ORDER);
 674
 675         drm_framebuffer_reference(fb);
 676
 677         set_scanout(crtc, fb);
 678
 679         tilcdc_crtc_set_clk(crtc);
 680
 681         crtc->hwmode = crtc->state->adjusted_mode;
 682 }
 683
 684 static int tilcdc_crtc_atomic_check(struct drm_crtc *crtc,
 685                                     struct drm_crtc_state *state)
 686 {
 687         struct drm_display_mode *mode = &state->mode;
 688         int ret;
 689
 690         /* If we are not active we don't care */
 691         if (!state->active)
 692                 return 0;
 693
 694         if (state->state->planes[0].ptr != crtc->primary ||
 695             state->state->planes[0].state == NULL ||
 696             state->state->planes[0].state->crtc != crtc) {
 697                 dev_dbg(crtc->dev->dev, "CRTC primary plane must be present");
 698                 return -EINVAL;
 699         }
 700
 701         ret = tilcdc_crtc_mode_valid(crtc, mode);
 702         if (ret) {
 703                 dev_dbg(crtc->dev->dev, "Mode \"%s\" not valid", mode->name);
 704                 return -EINVAL;
 705         }
 706
 707         return 0;
 708 }
 709
 710 static const struct drm_crtc_funcs tilcdc_crtc_funcs = {
 711         .destroy        = tilcdc_crtc_destroy,
 712         .set_config     = drm_atomic_helper_set_config,
 713         .page_flip      = drm_atomic_helper_page_flip,
 714         .reset          = drm_atomic_helper_crtc_reset,
 715         .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
 716         .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
 717 };
 718
 719 static const struct drm_crtc_helper_funcs tilcdc_crtc_helper_funcs = {
 720                 .mode_fixup     = tilcdc_crtc_mode_fixup,
 721                 .enable         = tilcdc_crtc_enable,
 722                 .disable        = tilcdc_crtc_disable,
 723                 .atomic_check   = tilcdc_crtc_atomic_check,
 724                 .mode_set_nofb  = tilcdc_crtc_mode_set_nofb,
 725 };
 726
 727 int tilcdc_crtc_max_width(struct drm_crtc *crtc)
 728 {
 729         struct drm_device *dev = crtc->dev;
 730         struct tilcdc_drm_private *priv = dev->dev_private;
 731         int max_width = 0;
 732
 733         if (priv->rev == 1)
 734                 max_width = 1024;
 735         else if (priv->rev == 2)
 736                 max_width = 2048;
 737
 738         return max_width;
 739 }
 740
 741 int tilcdc_crtc_mode_valid(struct drm_crtc *crtc, struct drm_display_mode *mode)
 742 {
 743         struct tilcdc_drm_private *priv = crtc->dev->dev_private;
 744         unsigned int bandwidth;
 745         uint32_t hbp, hfp, hsw, vbp, vfp, vsw;
 746
 747         /*
 748          * check to see if the width is within the range that
 749          * the LCD Controller physically supports
 750          */
 751         if (mode->hdisplay > tilcdc_crtc_max_width(crtc))
 752                 return MODE_VIRTUAL_X;
 753
 754         /* width must be multiple of 16 */
 755         if (mode->hdisplay & 0xf)
 756                 return MODE_VIRTUAL_X;
 757
 758         if (mode->vdisplay > 2048)
 759                 return MODE_VIRTUAL_Y;
 760
 761         DBG("Processing mode %dx%d@%d with pixel clock %d",
 762                 mode->hdisplay, mode->vdisplay,
 763                 drm_mode_vrefresh(mode), mode->clock);
 764
 765         hbp = mode->htotal - mode->hsync_end;
 766         hfp = mode->hsync_start - mode->hdisplay;
 767         hsw = mode->hsync_end - mode->hsync_start;
 768         vbp = mode->vtotal - mode->vsync_end;
 769         vfp = mode->vsync_start - mode->vdisplay;
 770         vsw = mode->vsync_end - mode->vsync_start;
 771
 772         if ((hbp-1) & ~0x3ff) {
 773                 DBG("Pruning mode: Horizontal Back Porch out of range");
 774                 return MODE_HBLANK_WIDE;
 775         }
 776
 777         if ((hfp-1) & ~0x3ff) {
 778                 DBG("Pruning mode: Horizontal Front Porch out of range");
 779                 return MODE_HBLANK_WIDE;
 780         }
 781
 782         if ((hsw-1) & ~0x3ff) {
 783                 DBG("Pruning mode: Horizontal Sync Width out of range");
 784                 return MODE_HSYNC_WIDE;
 785         }
 786
 787         if (vbp & ~0xff) {
 788                 DBG("Pruning mode: Vertical Back Porch out of range");
 789                 return MODE_VBLANK_WIDE;
 790         }
 791
 792         if (vfp & ~0xff) {
 793                 DBG("Pruning mode: Vertical Front Porch out of range");
 794                 return MODE_VBLANK_WIDE;
 795         }
 796
 797         if ((vsw-1) & ~0x3f) {
 798                 DBG("Pruning mode: Vertical Sync Width out of range");
 799                 return MODE_VSYNC_WIDE;
 800         }
 801
 802         /*
 803          * some devices have a maximum allowed pixel clock
 804          * configured from the DT
 805          */
 806         if (mode->clock > priv->max_pixelclock) {
 807                 DBG("Pruning mode: pixel clock too high");
 808                 return MODE_CLOCK_HIGH;
 809         }
 810
 811         /*
 812          * some devices further limit the max horizontal resolution
 813          * configured from the DT
 814          */
 815         if (mode->hdisplay > priv->max_width)
 816                 return MODE_BAD_WIDTH;
 817
 818         /* filter out modes that would require too much memory bandwidth: */
 819         bandwidth = mode->hdisplay * mode->vdisplay *
 820                 drm_mode_vrefresh(mode);
 821         if (bandwidth > priv->max_bandwidth) {
 822                 DBG("Pruning mode: exceeds defined bandwidth limit");
 823                 return MODE_BAD;
 824         }
 825
 826         return MODE_OK;
 827 }
 828
 829 void tilcdc_crtc_set_panel_info(struct drm_crtc *crtc,
 830                 const struct tilcdc_panel_info *info)
 831 {
 832         struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
 833         tilcdc_crtc->info = info;
 834 }
 835
 836 void tilcdc_crtc_set_simulate_vesa_sync(struct drm_crtc *crtc,
 837                                         bool simulate_vesa_sync)
 838 {
 839         struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
 840
 841         tilcdc_crtc->simulate_vesa_sync = simulate_vesa_sync;
 842 }
 843
 844 void tilcdc_crtc_update_clk(struct drm_crtc *crtc)
 845 {
 846         struct drm_device *dev = crtc->dev;
 847         struct tilcdc_drm_private *priv = dev->dev_private;
 848         struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
 849
 850         drm_modeset_lock_crtc(crtc, NULL);
 851         if (tilcdc_crtc->lcd_fck_rate != clk_get_rate(priv->clk)) {
 852                 if (tilcdc_crtc_is_on(crtc)) {
 853                         pm_runtime_get_sync(dev->dev);
 854                         tilcdc_crtc_disable(crtc);
 855
 856                         tilcdc_crtc_set_clk(crtc);
 857
 858                         tilcdc_crtc_enable(crtc);
 859                         pm_runtime_put_sync(dev->dev);
 860                 }
 861         }
 862         drm_modeset_unlock_crtc(crtc);
 863 }
 864
 865 #define SYNC_LOST_COUNT_LIMIT 50
 866
 867 irqreturn_t tilcdc_crtc_irq(struct drm_crtc *crtc)
 868 {
 869         struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
 870         struct drm_device *dev = crtc->dev;
 871         struct tilcdc_drm_private *priv = dev->dev_private;
 872         uint32_t stat;
 873
 874         stat = tilcdc_read_irqstatus(dev);
 875         tilcdc_clear_irqstatus(dev, stat);
 876
 877         if (stat & LCDC_END_OF_FRAME0) {
 878                 unsigned long flags;
 879                 bool skip_event = false;
 880                 ktime_t now;
 881
 882                 now = ktime_get();
 883
 884                 drm_flip_work_commit(&tilcdc_crtc->unref_work, priv->wq);
 885
 886                 spin_lock_irqsave(&tilcdc_crtc->irq_lock, flags);
 887
 888                 tilcdc_crtc->last_vblank = now;
 889
 890                 if (tilcdc_crtc->next_fb) {
 891                         set_scanout(crtc, tilcdc_crtc->next_fb);
 892                         tilcdc_crtc->next_fb = NULL;
 893                         skip_event = true;
 894                 }
 895
 896                 spin_unlock_irqrestore(&tilcdc_crtc->irq_lock, flags);
 897
 898                 drm_crtc_handle_vblank(crtc);
 899
 900                 if (!skip_event) {
 901                         struct drm_pending_vblank_event *event;
 902
 903                         spin_lock_irqsave(&dev->event_lock, flags);
 904
 905                         event = tilcdc_crtc->event;
 906                         tilcdc_crtc->event = NULL;
 907                         if (event)
 908                                 drm_crtc_send_vblank_event(crtc, event);
 909
 910                         spin_unlock_irqrestore(&dev->event_lock, flags);
 911                 }
 912
 913                 if (tilcdc_crtc->frame_intact)
 914                         tilcdc_crtc->sync_lost_count = 0;
 915                 else
 916                         tilcdc_crtc->frame_intact = true;
 917         }
 918
 919         if (stat & LCDC_FIFO_UNDERFLOW)
 920                 dev_err_ratelimited(dev->dev, "%s(0x%08x): FIFO underflow",
 921                                     __func__, stat);
 922
 923         if (stat & LCDC_PL_LOAD_DONE) {
 924                 complete(&tilcdc_crtc->palette_loaded);
 925                 if (priv->rev == 1)
 926                         tilcdc_clear(dev, LCDC_RASTER_CTRL_REG,
 927                                      LCDC_V1_PL_INT_ENA);
 928                 else
 929                         tilcdc_write(dev, LCDC_INT_ENABLE_CLR_REG,
 930                                      LCDC_V2_PL_INT_ENA);
 931         }
 932
 933         if (stat & LCDC_SYNC_LOST) {
 934                 dev_err_ratelimited(dev->dev, "%s(0x%08x): Sync lost",
 935                                     __func__, stat);
 936                 tilcdc_crtc->frame_intact = false;
 937                 if (tilcdc_crtc->sync_lost_count++ >
 938                     SYNC_LOST_COUNT_LIMIT) {
 939                         dev_err(dev->dev, "%s(0x%08x): Sync lost flood detected, recovering", __func__, stat);
 940                         queue_work(system_wq, &tilcdc_crtc->recover_work);
 941                         if (priv->rev == 1)
 942                                 tilcdc_clear(dev, LCDC_RASTER_CTRL_REG,
 943                                              LCDC_V1_SYNC_LOST_INT_ENA);
 944                         else
 945                                 tilcdc_write(dev, LCDC_INT_ENABLE_CLR_REG,
 946                                              LCDC_SYNC_LOST);
 947                         tilcdc_crtc->sync_lost_count = 0;
 948                 }
 949         }
 950
 951         /* For revision 2 only */
 952         if (priv->rev == 2) {
 953                 if (stat & LCDC_FRAME_DONE) {
 954                         tilcdc_crtc->frame_done = true;
 955                         wake_up(&tilcdc_crtc->frame_done_wq);
 956                 }
 957
 958                 /* Indicate to LCDC that the interrupt service routine has
 959                  * completed, see 13.3.6.1.6 in AM335x TRM.
 960                  */
 961                 tilcdc_write(dev, LCDC_END_OF_INT_IND_REG, 0);
 962         }
 963
 964         return IRQ_HANDLED;
 965 }
 966
 967 int tilcdc_crtc_create(struct drm_device *dev)
 968 {
 969         struct tilcdc_drm_private *priv = dev->dev_private;
 970         struct tilcdc_crtc *tilcdc_crtc;
 971         struct drm_crtc *crtc;
 972         int ret;
 973
 974         tilcdc_crtc = devm_kzalloc(dev->dev, sizeof(*tilcdc_crtc), GFP_KERNEL);
 975         if (!tilcdc_crtc) {
 976                 dev_err(dev->dev, "allocation failed\n");
 977                 return -ENOMEM;
 978         }
 979
 980         init_completion(&tilcdc_crtc->palette_loaded);
 981         tilcdc_crtc->palette_base = dmam_alloc_coherent(dev->dev,
 982                                         TILCDC_PALETTE_SIZE,
 983                                         &tilcdc_crtc->palette_dma_handle,
 984                                         GFP_KERNEL | __GFP_ZERO);
 985         if (!tilcdc_crtc->palette_base)
 986                 return -ENOMEM;
 987         *tilcdc_crtc->palette_base = TILCDC_PALETTE_FIRST_ENTRY;
 988
 989         crtc = &tilcdc_crtc->base;
 990
 991         ret = tilcdc_plane_init(dev, &tilcdc_crtc->primary);
 992         if (ret < 0)
 993                 goto fail;
 994
 995         mutex_init(&tilcdc_crtc->enable_lock);
 996
 997         init_waitqueue_head(&tilcdc_crtc->frame_done_wq);
 998
 999         drm_flip_work_init(&tilcdc_crtc->unref_work,
1000                         "unref", unref_worker);
1001
1002         spin_lock_init(&tilcdc_crtc->irq_lock);
1003         INIT_WORK(&tilcdc_crtc->recover_work, tilcdc_crtc_recover_work);
1004
1005         ret = drm_crtc_init_with_planes(dev, crtc,
1006                                         &tilcdc_crtc->primary,
1007                                         NULL,
1008                                         &tilcdc_crtc_funcs,
1009                                         "tilcdc crtc");
1010         if (ret < 0)
1011                 goto fail;
1012
1013         drm_crtc_helper_add(crtc, &tilcdc_crtc_helper_funcs);
1014
1015         if (priv->is_componentized) {
1016                 struct device_node *ports =
1017                         of_get_child_by_name(dev->dev->of_node, "ports");
1018
1019                 if (ports) {
1020                         crtc->port = of_get_child_by_name(ports, "port");
1021                         of_node_put(ports);
1022                 } else {
1023                         crtc->port =
1024                                 of_get_child_by_name(dev->dev->of_node, "port");
1025                 }
1026                 if (!crtc->port) { /* This should never happen */
1027                         dev_err(dev->dev, "Port node not found in %s\n",
1028                                 dev->dev->of_node->full_name);
1029                         ret = -EINVAL;
1030                         goto fail;
1031                 }
1032         }
1033
1034         priv->crtc = crtc;
1035         return 0;
1036
1037 fail:
1038         tilcdc_crtc_destroy(crtc);
1039         return -ENOMEM;
1040 }