drivers/gpu/drm/tilcdc/tilcdc_crtc.c

   1 /*
   2  * Copyright (C) 2012 Texas Instruments
   3  * Author: Rob Clark <robdclark@gmail.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 as published by
   7  * the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program.  If not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18 #include "drm_flip_work.h"
  19 #include <drm/drm_plane_helper.h>
  20
  21 #include "tilcdc_drv.h"
  22 #include "tilcdc_regs.h"
  23
  24 #define TILCDC_VBLANK_SAFETY_THRESHOLD_US 1000
  25
  26 struct tilcdc_crtc {
  27         struct drm_crtc base;
  28
  29         const struct tilcdc_panel_info *info;
  30         struct drm_pending_vblank_event *event;
  31         int dpms;
  32         wait_queue_head_t frame_done_wq;
  33         bool frame_done;
  34         spinlock_t irq_lock;
  35
  36         ktime_t last_vblank;
  37
  38         struct drm_framebuffer *curr_fb;
  39         struct drm_framebuffer *next_fb;
  40
  41         /* for deferred fb unref's: */
  42         struct drm_flip_work unref_work;
  43
  44         /* Only set if an external encoder is connected */
  45         bool simulate_vesa_sync;
  46
  47         int sync_lost_count;
  48         bool frame_intact;
  49 };
  50 #define to_tilcdc_crtc(x) container_of(x, struct tilcdc_crtc, base)
  51
  52 static void unref_worker(struct drm_flip_work *work, void *val)
  53 {
  54         struct tilcdc_crtc *tilcdc_crtc =
  55                 container_of(work, struct tilcdc_crtc, unref_work);
  56         struct drm_device *dev = tilcdc_crtc->base.dev;
  57
  58         mutex_lock(&dev->mode_config.mutex);
  59         drm_framebuffer_unreference(val);
  60         mutex_unlock(&dev->mode_config.mutex);
  61 }
  62
  63 static void set_scanout(struct drm_crtc *crtc, struct drm_framebuffer *fb)
  64 {
  65         struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
  66         struct drm_device *dev = crtc->dev;
  67         struct drm_gem_cma_object *gem;
  68         unsigned int depth, bpp;
  69         dma_addr_t start, end;
  70
  71         drm_fb_get_bpp_depth(fb->pixel_format, &depth, &bpp);
  72         gem = drm_fb_cma_get_gem_obj(fb, 0);
  73
  74         start = gem->paddr + fb->offsets[0] +
  75                 crtc->y * fb->pitches[0] +
  76                 crtc->x * bpp / 8;
  77
  78         end = start + (crtc->mode.vdisplay * fb->pitches[0]);
  79
  80         tilcdc_write(dev, LCDC_DMA_FB_BASE_ADDR_0_REG, start);
  81         tilcdc_write(dev, LCDC_DMA_FB_CEILING_ADDR_0_REG, end);
  82
  83         if (tilcdc_crtc->curr_fb)
  84                 drm_flip_work_queue(&tilcdc_crtc->unref_work,
  85                         tilcdc_crtc->curr_fb);
  86
  87         tilcdc_crtc->curr_fb = fb;
  88 }
  89
  90 static void reset(struct drm_crtc *crtc)
  91 {
  92         struct drm_device *dev = crtc->dev;
  93         struct tilcdc_drm_private *priv = dev->dev_private;
  94
  95         if (priv->rev != 2)
  96                 return;
  97
  98         tilcdc_set(dev, LCDC_CLK_RESET_REG, LCDC_CLK_MAIN_RESET);
  99         usleep_range(250, 1000);
 100         tilcdc_clear(dev, LCDC_CLK_RESET_REG, LCDC_CLK_MAIN_RESET);
 101 }
 102
 103 static void start(struct drm_crtc *crtc)
 104 {
 105         struct drm_device *dev = crtc->dev;
 106
 107         reset(crtc);
 108
 109         tilcdc_clear(dev, LCDC_DMA_CTRL_REG, LCDC_DUAL_FRAME_BUFFER_ENABLE);
 110         tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_PALETTE_LOAD_MODE(DATA_ONLY));
 111         tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ENABLE);
 112 }
 113
 114 static void stop(struct drm_crtc *crtc)
 115 {
 116         struct drm_device *dev = crtc->dev;
 117
 118         tilcdc_clear(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ENABLE);
 119 }
 120
 121 static void tilcdc_crtc_destroy(struct drm_crtc *crtc)
 122 {
 123         struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
 124
 125         tilcdc_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
 126
 127         of_node_put(crtc->port);
 128         drm_crtc_cleanup(crtc);
 129         drm_flip_work_cleanup(&tilcdc_crtc->unref_work);
 130 }
 131
 132 static int tilcdc_verify_fb(struct drm_crtc *crtc, struct drm_framebuffer *fb)
 133 {
 134         struct drm_device *dev = crtc->dev;
 135         unsigned int depth, bpp;
 136
 137         drm_fb_get_bpp_depth(fb->pixel_format, &depth, &bpp);
 138
 139         if (fb->pitches[0] != crtc->mode.hdisplay * bpp / 8) {
 140                 dev_err(dev->dev,
 141                         "Invalid pitch: fb and crtc widths must be the same");
 142                 return -EINVAL;
 143         }
 144
 145         return 0;
 146 }
 147
 148 static int tilcdc_crtc_page_flip(struct drm_crtc *crtc,
 149                 struct drm_framebuffer *fb,
 150                 struct drm_pending_vblank_event *event,
 151                 uint32_t page_flip_flags)
 152 {
 153         struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
 154         struct drm_device *dev = crtc->dev;
 155         int r;
 156         unsigned long flags;
 157         s64 tdiff;
 158         ktime_t next_vblank;
 159
 160         r = tilcdc_verify_fb(crtc, fb);
 161         if (r)
 162                 return r;
 163
 164         if (tilcdc_crtc->event) {
 165                 dev_err(dev->dev, "already pending page flip!\n");
 166                 return -EBUSY;
 167         }
 168
 169         drm_framebuffer_reference(fb);
 170
 171         crtc->primary->fb = fb;
 172
 173         pm_runtime_get_sync(dev->dev);
 174
 175         spin_lock_irqsave(&tilcdc_crtc->irq_lock, flags);
 176
 177         next_vblank = ktime_add_us(tilcdc_crtc->last_vblank,
 178                 1000000 / crtc->hwmode.vrefresh);
 179
 180         tdiff = ktime_to_us(ktime_sub(next_vblank, ktime_get()));
 181
 182         if (tdiff >= TILCDC_VBLANK_SAFETY_THRESHOLD_US)
 183                 set_scanout(crtc, fb);
 184         else
 185                 tilcdc_crtc->next_fb = fb;
 186
 187         tilcdc_crtc->event = event;
 188
 189         spin_unlock_irqrestore(&tilcdc_crtc->irq_lock, flags);
 190
 191         pm_runtime_put_sync(dev->dev);
 192
 193         return 0;
 194 }
 195
 196 void tilcdc_crtc_dpms(struct drm_crtc *crtc, int mode)
 197 {
 198         struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
 199         struct drm_device *dev = crtc->dev;
 200         struct tilcdc_drm_private *priv = dev->dev_private;
 201
 202         /* we really only care about on or off: */
 203         if (mode != DRM_MODE_DPMS_ON)
 204                 mode = DRM_MODE_DPMS_OFF;
 205
 206         if (tilcdc_crtc->dpms == mode)
 207                 return;
 208
 209         tilcdc_crtc->dpms = mode;
 210
 211         if (mode == DRM_MODE_DPMS_ON) {
 212                 pm_runtime_get_sync(dev->dev);
 213                 start(crtc);
 214         } else {
 215                 tilcdc_crtc->frame_done = false;
 216                 stop(crtc);
 217
 218                 /*
 219                  * if necessary wait for framedone irq which will still come
 220                  * before putting things to sleep..
 221                  */
 222                 if (priv->rev == 2) {
 223                         int ret = wait_event_timeout(
 224                                         tilcdc_crtc->frame_done_wq,
 225                                         tilcdc_crtc->frame_done,
 226                                         msecs_to_jiffies(50));
 227                         if (ret == 0)
 228                                 dev_err(dev->dev, "timeout waiting for framedone\n");
 229                 }
 230
 231                 pm_runtime_put_sync(dev->dev);
 232
 233                 if (tilcdc_crtc->next_fb) {
 234                         drm_flip_work_queue(&tilcdc_crtc->unref_work,
 235                                             tilcdc_crtc->next_fb);
 236                         tilcdc_crtc->next_fb = NULL;
 237                 }
 238
 239                 if (tilcdc_crtc->curr_fb) {
 240                         drm_flip_work_queue(&tilcdc_crtc->unref_work,
 241                                             tilcdc_crtc->curr_fb);
 242                         tilcdc_crtc->curr_fb = NULL;
 243                 }
 244
 245                 drm_flip_work_commit(&tilcdc_crtc->unref_work, priv->wq);
 246         }
 247 }
 248
 249 int tilcdc_crtc_current_dpms_state(struct drm_crtc *crtc)
 250 {
 251         struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
 252
 253         return tilcdc_crtc->dpms;
 254 }
 255
 256 static bool tilcdc_crtc_mode_fixup(struct drm_crtc *crtc,
 257                 const struct drm_display_mode *mode,
 258                 struct drm_display_mode *adjusted_mode)
 259 {
 260         struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
 261
 262         if (!tilcdc_crtc->simulate_vesa_sync)
 263                 return true;
 264
 265         /*
 266          * tilcdc does not generate VESA-compliant sync but aligns
 267          * VS on the second edge of HS instead of first edge.
 268          * We use adjusted_mode, to fixup sync by aligning both rising
 269          * edges and add HSKEW offset to fix the sync.
 270          */
 271         adjusted_mode->hskew = mode->hsync_end - mode->hsync_start;
 272         adjusted_mode->flags |= DRM_MODE_FLAG_HSKEW;
 273
 274         if (mode->flags & DRM_MODE_FLAG_NHSYNC) {
 275                 adjusted_mode->flags |= DRM_MODE_FLAG_PHSYNC;
 276                 adjusted_mode->flags &= ~DRM_MODE_FLAG_NHSYNC;
 277         } else {
 278                 adjusted_mode->flags |= DRM_MODE_FLAG_NHSYNC;
 279                 adjusted_mode->flags &= ~DRM_MODE_FLAG_PHSYNC;
 280         }
 281
 282         return true;
 283 }
 284
 285 static void tilcdc_crtc_prepare(struct drm_crtc *crtc)
 286 {
 287         tilcdc_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
 288 }
 289
 290 static void tilcdc_crtc_commit(struct drm_crtc *crtc)
 291 {
 292         tilcdc_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
 293 }
 294
 295 static int tilcdc_crtc_mode_set(struct drm_crtc *crtc,
 296                 struct drm_display_mode *mode,
 297                 struct drm_display_mode *adjusted_mode,
 298                 int x, int y,
 299                 struct drm_framebuffer *old_fb)
 300 {
 301         struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
 302         struct drm_device *dev = crtc->dev;
 303         struct tilcdc_drm_private *priv = dev->dev_private;
 304         const struct tilcdc_panel_info *info = tilcdc_crtc->info;
 305         uint32_t reg, hbp, hfp, hsw, vbp, vfp, vsw;
 306         int ret;
 307
 308         ret = tilcdc_crtc_mode_valid(crtc, mode);
 309         if (WARN_ON(ret))
 310                 return ret;
 311
 312         if (WARN_ON(!info))
 313                 return -EINVAL;
 314
 315         ret = tilcdc_verify_fb(crtc, crtc->primary->fb);
 316         if (ret)
 317                 return ret;
 318
 319         pm_runtime_get_sync(dev->dev);
 320
 321         /* Configure the Burst Size and fifo threshold of DMA: */
 322         reg = tilcdc_read(dev, LCDC_DMA_CTRL_REG) & ~0x00000770;
 323         switch (info->dma_burst_sz) {
 324         case 1:
 325                 reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_1);
 326                 break;
 327         case 2:
 328                 reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_2);
 329                 break;
 330         case 4:
 331                 reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_4);
 332                 break;
 333         case 8:
 334                 reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_8);
 335                 break;
 336         case 16:
 337                 reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_16);
 338                 break;
 339         default:
 340                 return -EINVAL;
 341         }
 342         reg |= (info->fifo_th << 8);
 343         tilcdc_write(dev, LCDC_DMA_CTRL_REG, reg);
 344
 345         /* Configure timings: */
 346         hbp = mode->htotal - mode->hsync_end;
 347         hfp = mode->hsync_start - mode->hdisplay;
 348         hsw = mode->hsync_end - mode->hsync_start;
 349         vbp = mode->vtotal - mode->vsync_end;
 350         vfp = mode->vsync_start - mode->vdisplay;
 351         vsw = mode->vsync_end - mode->vsync_start;
 352
 353         DBG("%dx%d, hbp=%u, hfp=%u, hsw=%u, vbp=%u, vfp=%u, vsw=%u",
 354                         mode->hdisplay, mode->vdisplay, hbp, hfp, hsw, vbp, vfp, vsw);
 355
 356         /* Configure the AC Bias Period and Number of Transitions per Interrupt: */
 357         reg = tilcdc_read(dev, LCDC_RASTER_TIMING_2_REG) & ~0x000fff00;
 358         reg |= LCDC_AC_BIAS_FREQUENCY(info->ac_bias) |
 359                 LCDC_AC_BIAS_TRANSITIONS_PER_INT(info->ac_bias_intrpt);
 360
 361         /*
 362          * subtract one from hfp, hbp, hsw because the hardware uses
 363          * a value of 0 as 1
 364          */
 365         if (priv->rev == 2) {
 366                 /* clear bits we're going to set */
 367                 reg &= ~0x78000033;
 368                 reg |= ((hfp-1) & 0x300) >> 8;
 369                 reg |= ((hbp-1) & 0x300) >> 4;
 370                 reg |= ((hsw-1) & 0x3c0) << 21;
 371         }
 372         tilcdc_write(dev, LCDC_RASTER_TIMING_2_REG, reg);
 373
 374         reg = (((mode->hdisplay >> 4) - 1) << 4) |
 375                 (((hbp-1) & 0xff) << 24) |
 376                 (((hfp-1) & 0xff) << 16) |
 377                 (((hsw-1) & 0x3f) << 10);
 378         if (priv->rev == 2)
 379                 reg |= (((mode->hdisplay >> 4) - 1) & 0x40) >> 3;
 380         tilcdc_write(dev, LCDC_RASTER_TIMING_0_REG, reg);
 381
 382         reg = ((mode->vdisplay - 1) & 0x3ff) |
 383                 ((vbp & 0xff) << 24) |
 384                 ((vfp & 0xff) << 16) |
 385                 (((vsw-1) & 0x3f) << 10);
 386         tilcdc_write(dev, LCDC_RASTER_TIMING_1_REG, reg);
 387
 388         /*
 389          * be sure to set Bit 10 for the V2 LCDC controller,
 390          * otherwise limited to 1024 pixels width, stopping
 391          * 1920x1080 being suppoted.
 392          */
 393         if (priv->rev == 2) {
 394                 if ((mode->vdisplay - 1) & 0x400) {
 395                         tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG,
 396                                 LCDC_LPP_B10);
 397                 } else {
 398                         tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG,
 399                                 LCDC_LPP_B10);
 400                 }
 401         }
 402
 403         /* Configure display type: */
 404         reg = tilcdc_read(dev, LCDC_RASTER_CTRL_REG) &
 405                 ~(LCDC_TFT_MODE | LCDC_MONO_8BIT_MODE | LCDC_MONOCHROME_MODE |
 406                         LCDC_V2_TFT_24BPP_MODE | LCDC_V2_TFT_24BPP_UNPACK | 0x000ff000);
 407         reg |= LCDC_TFT_MODE; /* no monochrome/passive support */
 408         if (info->tft_alt_mode)
 409                 reg |= LCDC_TFT_ALT_ENABLE;
 410         if (priv->rev == 2) {
 411                 unsigned int depth, bpp;
 412
 413                 drm_fb_get_bpp_depth(crtc->primary->fb->pixel_format, &depth, &bpp);
 414                 switch (bpp) {
 415                 case 16:
 416                         break;
 417                 case 32:
 418                         reg |= LCDC_V2_TFT_24BPP_UNPACK;
 419                         /* fallthrough */
 420                 case 24:
 421                         reg |= LCDC_V2_TFT_24BPP_MODE;
 422                         break;
 423                 default:
 424                         dev_err(dev->dev, "invalid pixel format\n");
 425                         return -EINVAL;
 426                 }
 427         }
 428         reg |= info->fdd < 12;
 429         tilcdc_write(dev, LCDC_RASTER_CTRL_REG, reg);
 430
 431         if (info->invert_pxl_clk)
 432                 tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_PIXEL_CLOCK);
 433         else
 434                 tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_PIXEL_CLOCK);
 435
 436         if (info->sync_ctrl)
 437                 tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_CTRL);
 438         else
 439                 tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_CTRL);
 440
 441         if (info->sync_edge)
 442                 tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_EDGE);
 443         else
 444                 tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_EDGE);
 445
 446         /*
 447          * use value from adjusted_mode here as this might have been
 448          * changed as part of the fixup for slave encoders to solve the
 449          * issue where tilcdc timings are not VESA compliant
 450          */
 451         if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
 452                 tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_HSYNC);
 453         else
 454                 tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_HSYNC);
 455
 456         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
 457                 tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_VSYNC);
 458         else
 459                 tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_VSYNC);
 460
 461         if (info->raster_order)
 462                 tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ORDER);
 463         else
 464                 tilcdc_clear(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ORDER);
 465
 466         drm_framebuffer_reference(crtc->primary->fb);
 467
 468         set_scanout(crtc, crtc->primary->fb);
 469
 470         tilcdc_crtc_update_clk(crtc);
 471
 472         pm_runtime_put_sync(dev->dev);
 473
 474         return 0;
 475 }
 476
 477 static int tilcdc_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
 478                 struct drm_framebuffer *old_fb)
 479 {
 480         struct drm_device *dev = crtc->dev;
 481         int r;
 482
 483         r = tilcdc_verify_fb(crtc, crtc->primary->fb);
 484         if (r)
 485                 return r;
 486
 487         drm_framebuffer_reference(crtc->primary->fb);
 488
 489         pm_runtime_get_sync(dev->dev);
 490
 491         set_scanout(crtc, crtc->primary->fb);
 492
 493         pm_runtime_put_sync(dev->dev);
 494
 495         return 0;
 496 }
 497
 498 static const struct drm_crtc_funcs tilcdc_crtc_funcs = {
 499                 .destroy        = tilcdc_crtc_destroy,
 500                 .set_config     = drm_crtc_helper_set_config,
 501                 .page_flip      = tilcdc_crtc_page_flip,
 502 };
 503
 504 static const struct drm_crtc_helper_funcs tilcdc_crtc_helper_funcs = {
 505                 .dpms           = tilcdc_crtc_dpms,
 506                 .mode_fixup     = tilcdc_crtc_mode_fixup,
 507                 .prepare        = tilcdc_crtc_prepare,
 508                 .commit         = tilcdc_crtc_commit,
 509                 .mode_set       = tilcdc_crtc_mode_set,
 510                 .mode_set_base  = tilcdc_crtc_mode_set_base,
 511 };
 512
 513 int tilcdc_crtc_max_width(struct drm_crtc *crtc)
 514 {
 515         struct drm_device *dev = crtc->dev;
 516         struct tilcdc_drm_private *priv = dev->dev_private;
 517         int max_width = 0;
 518
 519         if (priv->rev == 1)
 520                 max_width = 1024;
 521         else if (priv->rev == 2)
 522                 max_width = 2048;
 523
 524         return max_width;
 525 }
 526
 527 int tilcdc_crtc_mode_valid(struct drm_crtc *crtc, struct drm_display_mode *mode)
 528 {
 529         struct tilcdc_drm_private *priv = crtc->dev->dev_private;
 530         unsigned int bandwidth;
 531         uint32_t hbp, hfp, hsw, vbp, vfp, vsw;
 532
 533         /*
 534          * check to see if the width is within the range that
 535          * the LCD Controller physically supports
 536          */
 537         if (mode->hdisplay > tilcdc_crtc_max_width(crtc))
 538                 return MODE_VIRTUAL_X;
 539
 540         /* width must be multiple of 16 */
 541         if (mode->hdisplay & 0xf)
 542                 return MODE_VIRTUAL_X;
 543
 544         if (mode->vdisplay > 2048)
 545                 return MODE_VIRTUAL_Y;
 546
 547         DBG("Processing mode %dx%d@%d with pixel clock %d",
 548                 mode->hdisplay, mode->vdisplay,
 549                 drm_mode_vrefresh(mode), mode->clock);
 550
 551         hbp = mode->htotal - mode->hsync_end;
 552         hfp = mode->hsync_start - mode->hdisplay;
 553         hsw = mode->hsync_end - mode->hsync_start;
 554         vbp = mode->vtotal - mode->vsync_end;
 555         vfp = mode->vsync_start - mode->vdisplay;
 556         vsw = mode->vsync_end - mode->vsync_start;
 557
 558         if ((hbp-1) & ~0x3ff) {
 559                 DBG("Pruning mode: Horizontal Back Porch out of range");
 560                 return MODE_HBLANK_WIDE;
 561         }
 562
 563         if ((hfp-1) & ~0x3ff) {
 564                 DBG("Pruning mode: Horizontal Front Porch out of range");
 565                 return MODE_HBLANK_WIDE;
 566         }
 567
 568         if ((hsw-1) & ~0x3ff) {
 569                 DBG("Pruning mode: Horizontal Sync Width out of range");
 570                 return MODE_HSYNC_WIDE;
 571         }
 572
 573         if (vbp & ~0xff) {
 574                 DBG("Pruning mode: Vertical Back Porch out of range");
 575                 return MODE_VBLANK_WIDE;
 576         }
 577
 578         if (vfp & ~0xff) {
 579                 DBG("Pruning mode: Vertical Front Porch out of range");
 580                 return MODE_VBLANK_WIDE;
 581         }
 582
 583         if ((vsw-1) & ~0x3f) {
 584                 DBG("Pruning mode: Vertical Sync Width out of range");
 585                 return MODE_VSYNC_WIDE;
 586         }
 587
 588         /*
 589          * some devices have a maximum allowed pixel clock
 590          * configured from the DT
 591          */
 592         if (mode->clock > priv->max_pixelclock) {
 593                 DBG("Pruning mode: pixel clock too high");
 594                 return MODE_CLOCK_HIGH;
 595         }
 596
 597         /*
 598          * some devices further limit the max horizontal resolution
 599          * configured from the DT
 600          */
 601         if (mode->hdisplay > priv->max_width)
 602                 return MODE_BAD_WIDTH;
 603
 604         /* filter out modes that would require too much memory bandwidth: */
 605         bandwidth = mode->hdisplay * mode->vdisplay *
 606                 drm_mode_vrefresh(mode);
 607         if (bandwidth > priv->max_bandwidth) {
 608                 DBG("Pruning mode: exceeds defined bandwidth limit");
 609                 return MODE_BAD;
 610         }
 611
 612         return MODE_OK;
 613 }
 614
 615 void tilcdc_crtc_set_panel_info(struct drm_crtc *crtc,
 616                 const struct tilcdc_panel_info *info)
 617 {
 618         struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
 619         tilcdc_crtc->info = info;
 620 }
 621
 622 void tilcdc_crtc_set_simulate_vesa_sync(struct drm_crtc *crtc,
 623                                         bool simulate_vesa_sync)
 624 {
 625         struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
 626
 627         tilcdc_crtc->simulate_vesa_sync = simulate_vesa_sync;
 628 }
 629
 630 void tilcdc_crtc_update_clk(struct drm_crtc *crtc)
 631 {
 632         struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
 633         struct drm_device *dev = crtc->dev;
 634         struct tilcdc_drm_private *priv = dev->dev_private;
 635         int dpms = tilcdc_crtc->dpms;
 636         unsigned long lcd_clk;
 637         const unsigned clkdiv = 2; /* using a fixed divider of 2 */
 638         int ret;
 639
 640         pm_runtime_get_sync(dev->dev);
 641
 642         if (dpms == DRM_MODE_DPMS_ON)
 643                 tilcdc_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
 644
 645         /* mode.clock is in KHz, set_rate wants parameter in Hz */
 646         ret = clk_set_rate(priv->clk, crtc->mode.clock * 1000 * clkdiv);
 647         if (ret < 0) {
 648                 dev_err(dev->dev, "failed to set display clock rate to: %d\n",
 649                                 crtc->mode.clock);
 650                 goto out;
 651         }
 652
 653         lcd_clk = clk_get_rate(priv->clk);
 654
 655         DBG("lcd_clk=%lu, mode clock=%d, div=%u",
 656                 lcd_clk, crtc->mode.clock, clkdiv);
 657
 658         /* Configure the LCD clock divisor. */
 659         tilcdc_write(dev, LCDC_CTRL_REG, LCDC_CLK_DIVISOR(clkdiv) |
 660                         LCDC_RASTER_MODE);
 661
 662         if (priv->rev == 2)
 663                 tilcdc_set(dev, LCDC_CLK_ENABLE_REG,
 664                                 LCDC_V2_DMA_CLK_EN | LCDC_V2_LIDD_CLK_EN |
 665                                 LCDC_V2_CORE_CLK_EN);
 666
 667         if (dpms == DRM_MODE_DPMS_ON)
 668                 tilcdc_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
 669
 670 out:
 671         pm_runtime_put_sync(dev->dev);
 672 }
 673
 674 #define SYNC_LOST_COUNT_LIMIT 50
 675
 676 irqreturn_t tilcdc_crtc_irq(struct drm_crtc *crtc)
 677 {
 678         struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
 679         struct drm_device *dev = crtc->dev;
 680         struct tilcdc_drm_private *priv = dev->dev_private;
 681         uint32_t stat;
 682
 683         stat = tilcdc_read_irqstatus(dev);
 684         tilcdc_clear_irqstatus(dev, stat);
 685
 686         if (stat & LCDC_END_OF_FRAME0) {
 687                 unsigned long flags;
 688                 bool skip_event = false;
 689                 ktime_t now;
 690
 691                 now = ktime_get();
 692
 693                 drm_flip_work_commit(&tilcdc_crtc->unref_work, priv->wq);
 694
 695                 spin_lock_irqsave(&tilcdc_crtc->irq_lock, flags);
 696
 697                 tilcdc_crtc->last_vblank = now;
 698
 699                 if (tilcdc_crtc->next_fb) {
 700                         set_scanout(crtc, tilcdc_crtc->next_fb);
 701                         tilcdc_crtc->next_fb = NULL;
 702                         skip_event = true;
 703                 }
 704
 705                 spin_unlock_irqrestore(&tilcdc_crtc->irq_lock, flags);
 706
 707                 drm_crtc_handle_vblank(crtc);
 708
 709                 if (!skip_event) {
 710                         struct drm_pending_vblank_event *event;
 711
 712                         spin_lock_irqsave(&dev->event_lock, flags);
 713
 714                         event = tilcdc_crtc->event;
 715                         tilcdc_crtc->event = NULL;
 716                         if (event)
 717                                 drm_crtc_send_vblank_event(crtc, event);
 718
 719                         spin_unlock_irqrestore(&dev->event_lock, flags);
 720                 }
 721
 722                 if (tilcdc_crtc->frame_intact)
 723                         tilcdc_crtc->sync_lost_count = 0;
 724                 else
 725                         tilcdc_crtc->frame_intact = true;
 726         }
 727
 728         if (priv->rev == 2) {
 729                 if (stat & LCDC_FRAME_DONE) {
 730                         tilcdc_crtc->frame_done = true;
 731                         wake_up(&tilcdc_crtc->frame_done_wq);
 732                 }
 733                 tilcdc_write(dev, LCDC_END_OF_INT_IND_REG, 0);
 734
 735                 if (stat & LCDC_SYNC_LOST) {
 736                         dev_err_ratelimited(dev->dev, "%s(0x%08x): Sync lost",
 737                                             __func__, stat);
 738                         tilcdc_crtc->frame_intact = false;
 739                         if (tilcdc_crtc->sync_lost_count++ >
 740                             SYNC_LOST_COUNT_LIMIT) {
 741                                 dev_err(dev->dev, "%s(0x%08x): Sync lost flood detected, disabling the interrupt", __func__, stat);
 742                                 tilcdc_write(dev, LCDC_INT_ENABLE_CLR_REG,
 743                                              LCDC_SYNC_LOST);
 744                         }
 745                 }
 746         }
 747
 748         if (stat & LCDC_FIFO_UNDERFLOW)
 749                 dev_err_ratelimited(dev->dev, "%s(0x%08x): FIFO underfow",
 750                                     __func__, stat);
 751
 752         return IRQ_HANDLED;
 753 }
 754
 755 struct drm_crtc *tilcdc_crtc_create(struct drm_device *dev)
 756 {
 757         struct tilcdc_drm_private *priv = dev->dev_private;
 758         struct tilcdc_crtc *tilcdc_crtc;
 759         struct drm_crtc *crtc;
 760         int ret;
 761
 762         tilcdc_crtc = devm_kzalloc(dev->dev, sizeof(*tilcdc_crtc), GFP_KERNEL);
 763         if (!tilcdc_crtc) {
 764                 dev_err(dev->dev, "allocation failed\n");
 765                 return NULL;
 766         }
 767
 768         crtc = &tilcdc_crtc->base;
 769
 770         tilcdc_crtc->dpms = DRM_MODE_DPMS_OFF;
 771         init_waitqueue_head(&tilcdc_crtc->frame_done_wq);
 772
 773         drm_flip_work_init(&tilcdc_crtc->unref_work,
 774                         "unref", unref_worker);
 775
 776         spin_lock_init(&tilcdc_crtc->irq_lock);
 777
 778         ret = drm_crtc_init(dev, crtc, &tilcdc_crtc_funcs);
 779         if (ret < 0)
 780                 goto fail;
 781
 782         drm_crtc_helper_add(crtc, &tilcdc_crtc_helper_funcs);
 783
 784         if (priv->is_componentized) {
 785                 struct device_node *ports =
 786                         of_get_child_by_name(dev->dev->of_node, "ports");
 787
 788                 if (ports) {
 789                         crtc->port = of_get_child_by_name(ports, "port");
 790                         of_node_put(ports);
 791                 } else {
 792                         crtc->port =
 793                                 of_get_child_by_name(dev->dev->of_node, "port");
 794                 }
 795                 if (!crtc->port) { /* This should never happen */
 796                         dev_err(dev->dev, "Port node not found in %s\n",
 797                                 dev->dev->of_node->full_name);
 798                         goto fail;
 799                 }
 800         }
 801
 802         return crtc;
 803
 804 fail:
 805         tilcdc_crtc_destroy(crtc);
 806         return NULL;
 807 }