drivers/gpu/drm/tilcdc/tilcdc_crtc.c

   1 /*
   2  * Copyright (C) 2012 Texas Instruments
   3  * Author: Rob Clark <robdclark@gmail.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 as published by
   7  * the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program.  If not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18 #include "drm_flip_work.h"
  19 #include <drm/drm_plane_helper.h>
  20 #include <drm/drm_atomic_helper.h>
  21 #include <linux/workqueue.h>
  22
  23 #include "tilcdc_drv.h"
  24 #include "tilcdc_regs.h"
  25
  26 #define TILCDC_VBLANK_SAFETY_THRESHOLD_US 1000
  27
  28 struct tilcdc_crtc {
  29         struct drm_crtc base;
  30
  31         struct drm_plane primary;
  32         const struct tilcdc_panel_info *info;
  33         struct drm_pending_vblank_event *event;
  34         bool enabled;
  35         wait_queue_head_t frame_done_wq;
  36         bool frame_done;
  37         spinlock_t irq_lock;
  38
  39         unsigned int lcd_fck_rate;
  40
  41         ktime_t last_vblank;
  42
  43         struct drm_framebuffer *curr_fb;
  44         struct drm_framebuffer *next_fb;
  45
  46         /* for deferred fb unref's: */
  47         struct drm_flip_work unref_work;
  48
  49         /* Only set if an external encoder is connected */
  50         bool simulate_vesa_sync;
  51
  52         int sync_lost_count;
  53         bool frame_intact;
  54 };
  55 #define to_tilcdc_crtc(x) container_of(x, struct tilcdc_crtc, base)
  56
  57 static void unref_worker(struct drm_flip_work *work, void *val)
  58 {
  59         struct tilcdc_crtc *tilcdc_crtc =
  60                 container_of(work, struct tilcdc_crtc, unref_work);
  61         struct drm_device *dev = tilcdc_crtc->base.dev;
  62
  63         mutex_lock(&dev->mode_config.mutex);
  64         drm_framebuffer_unreference(val);
  65         mutex_unlock(&dev->mode_config.mutex);
  66 }
  67
  68 static void set_scanout(struct drm_crtc *crtc, struct drm_framebuffer *fb)
  69 {
  70         struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
  71         struct drm_device *dev = crtc->dev;
  72         struct drm_gem_cma_object *gem;
  73         unsigned int depth, bpp;
  74         dma_addr_t start, end;
  75         u64 dma_base_and_ceiling;
  76
  77         drm_fb_get_bpp_depth(fb->pixel_format, &depth, &bpp);
  78         gem = drm_fb_cma_get_gem_obj(fb, 0);
  79
  80         start = gem->paddr + fb->offsets[0] +
  81                 crtc->y * fb->pitches[0] +
  82                 crtc->x * bpp / 8;
  83
  84         end = start + (crtc->mode.vdisplay * fb->pitches[0]);
  85
  86         /* Write LCDC_DMA_FB_BASE_ADDR_0_REG and LCDC_DMA_FB_CEILING_ADDR_0_REG
  87          * with a single insruction, if available. This should make it more
  88          * unlikely that LCDC would fetch the DMA addresses in the middle of
  89          * an update.
  90          */
  91         dma_base_and_ceiling = (u64)(end - 1) << 32 | start;
  92         tilcdc_write64(dev, LCDC_DMA_FB_BASE_ADDR_0_REG, dma_base_and_ceiling);
  93
  94         if (tilcdc_crtc->curr_fb)
  95                 drm_flip_work_queue(&tilcdc_crtc->unref_work,
  96                         tilcdc_crtc->curr_fb);
  97
  98         tilcdc_crtc->curr_fb = fb;
  99 }
 100
 101 static void tilcdc_crtc_enable_irqs(struct drm_device *dev)
 102 {
 103         struct tilcdc_drm_private *priv = dev->dev_private;
 104
 105         tilcdc_clear_irqstatus(dev, 0xffffffff);
 106
 107         if (priv->rev == 1) {
 108                 tilcdc_set(dev, LCDC_RASTER_CTRL_REG,
 109                         LCDC_V1_UNDERFLOW_INT_ENA);
 110                 tilcdc_set(dev, LCDC_DMA_CTRL_REG,
 111                         LCDC_V1_END_OF_FRAME_INT_ENA);
 112         } else {
 113                 tilcdc_write(dev, LCDC_INT_ENABLE_SET_REG,
 114                         LCDC_V2_UNDERFLOW_INT_ENA |
 115                         LCDC_V2_END_OF_FRAME0_INT_ENA |
 116                         LCDC_FRAME_DONE | LCDC_SYNC_LOST);
 117         }
 118 }
 119
 120 static void tilcdc_crtc_disable_irqs(struct drm_device *dev)
 121 {
 122         struct tilcdc_drm_private *priv = dev->dev_private;
 123
 124         /* disable irqs that we might have enabled: */
 125         if (priv->rev == 1) {
 126                 tilcdc_clear(dev, LCDC_RASTER_CTRL_REG,
 127                         LCDC_V1_UNDERFLOW_INT_ENA | LCDC_V1_PL_INT_ENA);
 128                 tilcdc_clear(dev, LCDC_DMA_CTRL_REG,
 129                         LCDC_V1_END_OF_FRAME_INT_ENA);
 130         } else {
 131                 tilcdc_write(dev, LCDC_INT_ENABLE_CLR_REG,
 132                         LCDC_V2_UNDERFLOW_INT_ENA | LCDC_V2_PL_INT_ENA |
 133                         LCDC_V2_END_OF_FRAME0_INT_ENA |
 134                         LCDC_FRAME_DONE | LCDC_SYNC_LOST);
 135         }
 136 }
 137
 138 static void reset(struct drm_crtc *crtc)
 139 {
 140         struct drm_device *dev = crtc->dev;
 141         struct tilcdc_drm_private *priv = dev->dev_private;
 142
 143         if (priv->rev != 2)
 144                 return;
 145
 146         tilcdc_set(dev, LCDC_CLK_RESET_REG, LCDC_CLK_MAIN_RESET);
 147         usleep_range(250, 1000);
 148         tilcdc_clear(dev, LCDC_CLK_RESET_REG, LCDC_CLK_MAIN_RESET);
 149 }
 150
 151 static void tilcdc_crtc_enable(struct drm_crtc *crtc)
 152 {
 153         struct drm_device *dev = crtc->dev;
 154         struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
 155
 156         if (tilcdc_crtc->enabled)
 157                 return;
 158
 159         pm_runtime_get_sync(dev->dev);
 160
 161         reset(crtc);
 162
 163         tilcdc_crtc_enable_irqs(dev);
 164
 165         tilcdc_clear(dev, LCDC_DMA_CTRL_REG, LCDC_DUAL_FRAME_BUFFER_ENABLE);
 166         tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_PALETTE_LOAD_MODE(DATA_ONLY));
 167         tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ENABLE);
 168
 169         drm_crtc_vblank_on(crtc);
 170
 171         tilcdc_crtc->enabled = true;
 172 }
 173
 174 void tilcdc_crtc_disable(struct drm_crtc *crtc)
 175 {
 176         struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
 177         struct drm_device *dev = crtc->dev;
 178         struct tilcdc_drm_private *priv = dev->dev_private;
 179
 180         if (!tilcdc_crtc->enabled)
 181                 return;
 182
 183         tilcdc_crtc->frame_done = false;
 184         tilcdc_clear(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ENABLE);
 185
 186         /*
 187          * if necessary wait for framedone irq which will still come
 188          * before putting things to sleep..
 189          */
 190         if (priv->rev == 2) {
 191                 int ret = wait_event_timeout(tilcdc_crtc->frame_done_wq,
 192                                              tilcdc_crtc->frame_done,
 193                                              msecs_to_jiffies(500));
 194                 if (ret == 0)
 195                         dev_err(dev->dev, "%s: timeout waiting for framedone\n",
 196                                 __func__);
 197         }
 198
 199         drm_crtc_vblank_off(crtc);
 200
 201         tilcdc_crtc_disable_irqs(dev);
 202
 203         pm_runtime_put_sync(dev->dev);
 204
 205         if (tilcdc_crtc->next_fb) {
 206                 drm_flip_work_queue(&tilcdc_crtc->unref_work,
 207                                     tilcdc_crtc->next_fb);
 208                 tilcdc_crtc->next_fb = NULL;
 209         }
 210
 211         if (tilcdc_crtc->curr_fb) {
 212                 drm_flip_work_queue(&tilcdc_crtc->unref_work,
 213                                     tilcdc_crtc->curr_fb);
 214                 tilcdc_crtc->curr_fb = NULL;
 215         }
 216
 217         drm_flip_work_commit(&tilcdc_crtc->unref_work, priv->wq);
 218         tilcdc_crtc->last_vblank = ktime_set(0, 0);
 219
 220         tilcdc_crtc->enabled = false;
 221 }
 222
 223 static bool tilcdc_crtc_is_on(struct drm_crtc *crtc)
 224 {
 225         return crtc->state && crtc->state->enable && crtc->state->active;
 226 }
 227
 228 static void tilcdc_crtc_destroy(struct drm_crtc *crtc)
 229 {
 230         struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
 231         struct tilcdc_drm_private *priv = crtc->dev->dev_private;
 232
 233         tilcdc_crtc_disable(crtc);
 234
 235         flush_workqueue(priv->wq);
 236
 237         of_node_put(crtc->port);
 238         drm_crtc_cleanup(crtc);
 239         drm_flip_work_cleanup(&tilcdc_crtc->unref_work);
 240 }
 241
 242 int tilcdc_crtc_update_fb(struct drm_crtc *crtc,
 243                 struct drm_framebuffer *fb,
 244                 struct drm_pending_vblank_event *event)
 245 {
 246         struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
 247         struct drm_device *dev = crtc->dev;
 248         unsigned long flags;
 249
 250         if (tilcdc_crtc->event) {
 251                 dev_err(dev->dev, "already pending page flip!\n");
 252                 return -EBUSY;
 253         }
 254
 255         drm_framebuffer_reference(fb);
 256
 257         crtc->primary->fb = fb;
 258
 259         spin_lock_irqsave(&tilcdc_crtc->irq_lock, flags);
 260
 261         if (crtc->hwmode.vrefresh && ktime_to_ns(tilcdc_crtc->last_vblank)) {
 262                 ktime_t next_vblank;
 263                 s64 tdiff;
 264
 265                 next_vblank = ktime_add_us(tilcdc_crtc->last_vblank,
 266                         1000000 / crtc->hwmode.vrefresh);
 267
 268                 tdiff = ktime_to_us(ktime_sub(next_vblank, ktime_get()));
 269
 270                 if (tdiff < TILCDC_VBLANK_SAFETY_THRESHOLD_US)
 271                         tilcdc_crtc->next_fb = fb;
 272         }
 273
 274         if (tilcdc_crtc->next_fb != fb)
 275                 set_scanout(crtc, fb);
 276
 277         tilcdc_crtc->event = event;
 278
 279         spin_unlock_irqrestore(&tilcdc_crtc->irq_lock, flags);
 280
 281         return 0;
 282 }
 283
 284 static bool tilcdc_crtc_mode_fixup(struct drm_crtc *crtc,
 285                 const struct drm_display_mode *mode,
 286                 struct drm_display_mode *adjusted_mode)
 287 {
 288         struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
 289
 290         if (!tilcdc_crtc->simulate_vesa_sync)
 291                 return true;
 292
 293         /*
 294          * tilcdc does not generate VESA-compliant sync but aligns
 295          * VS on the second edge of HS instead of first edge.
 296          * We use adjusted_mode, to fixup sync by aligning both rising
 297          * edges and add HSKEW offset to fix the sync.
 298          */
 299         adjusted_mode->hskew = mode->hsync_end - mode->hsync_start;
 300         adjusted_mode->flags |= DRM_MODE_FLAG_HSKEW;
 301
 302         if (mode->flags & DRM_MODE_FLAG_NHSYNC) {
 303                 adjusted_mode->flags |= DRM_MODE_FLAG_PHSYNC;
 304                 adjusted_mode->flags &= ~DRM_MODE_FLAG_NHSYNC;
 305         } else {
 306                 adjusted_mode->flags |= DRM_MODE_FLAG_NHSYNC;
 307                 adjusted_mode->flags &= ~DRM_MODE_FLAG_PHSYNC;
 308         }
 309
 310         return true;
 311 }
 312
 313 static void tilcdc_crtc_set_clk(struct drm_crtc *crtc)
 314 {
 315         struct drm_device *dev = crtc->dev;
 316         struct tilcdc_drm_private *priv = dev->dev_private;
 317         struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
 318         const unsigned clkdiv = 2; /* using a fixed divider of 2 */
 319         int ret;
 320
 321         /* mode.clock is in KHz, set_rate wants parameter in Hz */
 322         ret = clk_set_rate(priv->clk, crtc->mode.clock * 1000 * clkdiv);
 323         if (ret < 0) {
 324                 dev_err(dev->dev, "failed to set display clock rate to: %d\n",
 325                         crtc->mode.clock);
 326                 return;
 327         }
 328
 329         tilcdc_crtc->lcd_fck_rate = clk_get_rate(priv->clk);
 330
 331         DBG("lcd_clk=%u, mode clock=%d, div=%u",
 332             tilcdc_crtc->lcd_fck_rate, crtc->mode.clock, clkdiv);
 333
 334         /* Configure the LCD clock divisor. */
 335         tilcdc_write(dev, LCDC_CTRL_REG, LCDC_CLK_DIVISOR(clkdiv) |
 336                      LCDC_RASTER_MODE);
 337
 338         if (priv->rev == 2)
 339                 tilcdc_set(dev, LCDC_CLK_ENABLE_REG,
 340                                 LCDC_V2_DMA_CLK_EN | LCDC_V2_LIDD_CLK_EN |
 341                                 LCDC_V2_CORE_CLK_EN);
 342 }
 343
 344 static void tilcdc_crtc_mode_set_nofb(struct drm_crtc *crtc)
 345 {
 346         struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
 347         struct drm_device *dev = crtc->dev;
 348         struct tilcdc_drm_private *priv = dev->dev_private;
 349         const struct tilcdc_panel_info *info = tilcdc_crtc->info;
 350         uint32_t reg, hbp, hfp, hsw, vbp, vfp, vsw;
 351         struct drm_display_mode *mode = &crtc->state->adjusted_mode;
 352         struct drm_framebuffer *fb = crtc->primary->state->fb;
 353
 354         if (WARN_ON(!info))
 355                 return;
 356
 357         if (WARN_ON(!fb))
 358                 return;
 359
 360         /* Configure the Burst Size and fifo threshold of DMA: */
 361         reg = tilcdc_read(dev, LCDC_DMA_CTRL_REG) & ~0x00000770;
 362         switch (info->dma_burst_sz) {
 363         case 1:
 364                 reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_1);
 365                 break;
 366         case 2:
 367                 reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_2);
 368                 break;
 369         case 4:
 370                 reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_4);
 371                 break;
 372         case 8:
 373                 reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_8);
 374                 break;
 375         case 16:
 376                 reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_16);
 377                 break;
 378         default:
 379                 dev_err(dev->dev, "invalid burst size\n");
 380                 return;
 381         }
 382         reg |= (info->fifo_th << 8);
 383         tilcdc_write(dev, LCDC_DMA_CTRL_REG, reg);
 384
 385         /* Configure timings: */
 386         hbp = mode->htotal - mode->hsync_end;
 387         hfp = mode->hsync_start - mode->hdisplay;
 388         hsw = mode->hsync_end - mode->hsync_start;
 389         vbp = mode->vtotal - mode->vsync_end;
 390         vfp = mode->vsync_start - mode->vdisplay;
 391         vsw = mode->vsync_end - mode->vsync_start;
 392
 393         DBG("%dx%d, hbp=%u, hfp=%u, hsw=%u, vbp=%u, vfp=%u, vsw=%u",
 394             mode->hdisplay, mode->vdisplay, hbp, hfp, hsw, vbp, vfp, vsw);
 395
 396         /* Set AC Bias Period and Number of Transitions per Interrupt: */
 397         reg = tilcdc_read(dev, LCDC_RASTER_TIMING_2_REG) & ~0x000fff00;
 398         reg |= LCDC_AC_BIAS_FREQUENCY(info->ac_bias) |
 399                 LCDC_AC_BIAS_TRANSITIONS_PER_INT(info->ac_bias_intrpt);
 400
 401         /*
 402          * subtract one from hfp, hbp, hsw because the hardware uses
 403          * a value of 0 as 1
 404          */
 405         if (priv->rev == 2) {
 406                 /* clear bits we're going to set */
 407                 reg &= ~0x78000033;
 408                 reg |= ((hfp-1) & 0x300) >> 8;
 409                 reg |= ((hbp-1) & 0x300) >> 4;
 410                 reg |= ((hsw-1) & 0x3c0) << 21;
 411         }
 412         tilcdc_write(dev, LCDC_RASTER_TIMING_2_REG, reg);
 413
 414         reg = (((mode->hdisplay >> 4) - 1) << 4) |
 415                 (((hbp-1) & 0xff) << 24) |
 416                 (((hfp-1) & 0xff) << 16) |
 417                 (((hsw-1) & 0x3f) << 10);
 418         if (priv->rev == 2)
 419                 reg |= (((mode->hdisplay >> 4) - 1) & 0x40) >> 3;
 420         tilcdc_write(dev, LCDC_RASTER_TIMING_0_REG, reg);
 421
 422         reg = ((mode->vdisplay - 1) & 0x3ff) |
 423                 ((vbp & 0xff) << 24) |
 424                 ((vfp & 0xff) << 16) |
 425                 (((vsw-1) & 0x3f) << 10);
 426         tilcdc_write(dev, LCDC_RASTER_TIMING_1_REG, reg);
 427
 428         /*
 429          * be sure to set Bit 10 for the V2 LCDC controller,
 430          * otherwise limited to 1024 pixels width, stopping
 431          * 1920x1080 being supported.
 432          */
 433         if (priv->rev == 2) {
 434                 if ((mode->vdisplay - 1) & 0x400) {
 435                         tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG,
 436                                 LCDC_LPP_B10);
 437                 } else {
 438                         tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG,
 439                                 LCDC_LPP_B10);
 440                 }
 441         }
 442
 443         /* Configure display type: */
 444         reg = tilcdc_read(dev, LCDC_RASTER_CTRL_REG) &
 445                 ~(LCDC_TFT_MODE | LCDC_MONO_8BIT_MODE | LCDC_MONOCHROME_MODE |
 446                   LCDC_V2_TFT_24BPP_MODE | LCDC_V2_TFT_24BPP_UNPACK |
 447                   0x000ff000 /* Palette Loading Delay bits */);
 448         reg |= LCDC_TFT_MODE; /* no monochrome/passive support */
 449         if (info->tft_alt_mode)
 450                 reg |= LCDC_TFT_ALT_ENABLE;
 451         if (priv->rev == 2) {
 452                 unsigned int depth, bpp;
 453
 454                 drm_fb_get_bpp_depth(fb->pixel_format, &depth, &bpp);
 455                 switch (bpp) {
 456                 case 16:
 457                         break;
 458                 case 32:
 459                         reg |= LCDC_V2_TFT_24BPP_UNPACK;
 460                         /* fallthrough */
 461                 case 24:
 462                         reg |= LCDC_V2_TFT_24BPP_MODE;
 463                         break;
 464                 default:
 465                         dev_err(dev->dev, "invalid pixel format\n");
 466                         return;
 467                 }
 468         }
 469         reg |= info->fdd < 12;
 470         tilcdc_write(dev, LCDC_RASTER_CTRL_REG, reg);
 471
 472         if (info->invert_pxl_clk)
 473                 tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_PIXEL_CLOCK);
 474         else
 475                 tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_PIXEL_CLOCK);
 476
 477         if (info->sync_ctrl)
 478                 tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_CTRL);
 479         else
 480                 tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_CTRL);
 481
 482         if (info->sync_edge)
 483                 tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_EDGE);
 484         else
 485                 tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_EDGE);
 486
 487         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
 488                 tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_HSYNC);
 489         else
 490                 tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_HSYNC);
 491
 492         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
 493                 tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_VSYNC);
 494         else
 495                 tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_VSYNC);
 496
 497         if (info->raster_order)
 498                 tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ORDER);
 499         else
 500                 tilcdc_clear(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ORDER);
 501
 502         drm_framebuffer_reference(fb);
 503
 504         set_scanout(crtc, fb);
 505
 506         tilcdc_crtc_set_clk(crtc);
 507
 508         crtc->hwmode = crtc->state->adjusted_mode;
 509 }
 510
 511 static int tilcdc_crtc_atomic_check(struct drm_crtc *crtc,
 512                                     struct drm_crtc_state *state)
 513 {
 514         struct drm_display_mode *mode = &state->mode;
 515         int ret;
 516
 517         /* If we are not active we don't care */
 518         if (!state->active)
 519                 return 0;
 520
 521         if (state->state->planes[0].ptr != crtc->primary ||
 522             state->state->planes[0].state == NULL ||
 523             state->state->planes[0].state->crtc != crtc) {
 524                 dev_dbg(crtc->dev->dev, "CRTC primary plane must be present");
 525                 return -EINVAL;
 526         }
 527
 528         ret = tilcdc_crtc_mode_valid(crtc, mode);
 529         if (ret) {
 530                 dev_dbg(crtc->dev->dev, "Mode \"%s\" not valid", mode->name);
 531                 return -EINVAL;
 532         }
 533
 534         return 0;
 535 }
 536
 537 static const struct drm_crtc_funcs tilcdc_crtc_funcs = {
 538         .destroy        = tilcdc_crtc_destroy,
 539         .set_config     = drm_atomic_helper_set_config,
 540         .page_flip      = drm_atomic_helper_page_flip,
 541         .reset          = drm_atomic_helper_crtc_reset,
 542         .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
 543         .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
 544 };
 545
 546 static const struct drm_crtc_helper_funcs tilcdc_crtc_helper_funcs = {
 547                 .mode_fixup     = tilcdc_crtc_mode_fixup,
 548                 .enable         = tilcdc_crtc_enable,
 549                 .disable        = tilcdc_crtc_disable,
 550                 .atomic_check   = tilcdc_crtc_atomic_check,
 551                 .mode_set_nofb  = tilcdc_crtc_mode_set_nofb,
 552 };
 553
 554 int tilcdc_crtc_max_width(struct drm_crtc *crtc)
 555 {
 556         struct drm_device *dev = crtc->dev;
 557         struct tilcdc_drm_private *priv = dev->dev_private;
 558         int max_width = 0;
 559
 560         if (priv->rev == 1)
 561                 max_width = 1024;
 562         else if (priv->rev == 2)
 563                 max_width = 2048;
 564
 565         return max_width;
 566 }
 567
 568 int tilcdc_crtc_mode_valid(struct drm_crtc *crtc, struct drm_display_mode *mode)
 569 {
 570         struct tilcdc_drm_private *priv = crtc->dev->dev_private;
 571         unsigned int bandwidth;
 572         uint32_t hbp, hfp, hsw, vbp, vfp, vsw;
 573
 574         /*
 575          * check to see if the width is within the range that
 576          * the LCD Controller physically supports
 577          */
 578         if (mode->hdisplay > tilcdc_crtc_max_width(crtc))
 579                 return MODE_VIRTUAL_X;
 580
 581         /* width must be multiple of 16 */
 582         if (mode->hdisplay & 0xf)
 583                 return MODE_VIRTUAL_X;
 584
 585         if (mode->vdisplay > 2048)
 586                 return MODE_VIRTUAL_Y;
 587
 588         DBG("Processing mode %dx%d@%d with pixel clock %d",
 589                 mode->hdisplay, mode->vdisplay,
 590                 drm_mode_vrefresh(mode), mode->clock);
 591
 592         hbp = mode->htotal - mode->hsync_end;
 593         hfp = mode->hsync_start - mode->hdisplay;
 594         hsw = mode->hsync_end - mode->hsync_start;
 595         vbp = mode->vtotal - mode->vsync_end;
 596         vfp = mode->vsync_start - mode->vdisplay;
 597         vsw = mode->vsync_end - mode->vsync_start;
 598
 599         if ((hbp-1) & ~0x3ff) {
 600                 DBG("Pruning mode: Horizontal Back Porch out of range");
 601                 return MODE_HBLANK_WIDE;
 602         }
 603
 604         if ((hfp-1) & ~0x3ff) {
 605                 DBG("Pruning mode: Horizontal Front Porch out of range");
 606                 return MODE_HBLANK_WIDE;
 607         }
 608
 609         if ((hsw-1) & ~0x3ff) {
 610                 DBG("Pruning mode: Horizontal Sync Width out of range");
 611                 return MODE_HSYNC_WIDE;
 612         }
 613
 614         if (vbp & ~0xff) {
 615                 DBG("Pruning mode: Vertical Back Porch out of range");
 616                 return MODE_VBLANK_WIDE;
 617         }
 618
 619         if (vfp & ~0xff) {
 620                 DBG("Pruning mode: Vertical Front Porch out of range");
 621                 return MODE_VBLANK_WIDE;
 622         }
 623
 624         if ((vsw-1) & ~0x3f) {
 625                 DBG("Pruning mode: Vertical Sync Width out of range");
 626                 return MODE_VSYNC_WIDE;
 627         }
 628
 629         /*
 630          * some devices have a maximum allowed pixel clock
 631          * configured from the DT
 632          */
 633         if (mode->clock > priv->max_pixelclock) {
 634                 DBG("Pruning mode: pixel clock too high");
 635                 return MODE_CLOCK_HIGH;
 636         }
 637
 638         /*
 639          * some devices further limit the max horizontal resolution
 640          * configured from the DT
 641          */
 642         if (mode->hdisplay > priv->max_width)
 643                 return MODE_BAD_WIDTH;
 644
 645         /* filter out modes that would require too much memory bandwidth: */
 646         bandwidth = mode->hdisplay * mode->vdisplay *
 647                 drm_mode_vrefresh(mode);
 648         if (bandwidth > priv->max_bandwidth) {
 649                 DBG("Pruning mode: exceeds defined bandwidth limit");
 650                 return MODE_BAD;
 651         }
 652
 653         return MODE_OK;
 654 }
 655
 656 void tilcdc_crtc_set_panel_info(struct drm_crtc *crtc,
 657                 const struct tilcdc_panel_info *info)
 658 {
 659         struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
 660         tilcdc_crtc->info = info;
 661 }
 662
 663 void tilcdc_crtc_set_simulate_vesa_sync(struct drm_crtc *crtc,
 664                                         bool simulate_vesa_sync)
 665 {
 666         struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
 667
 668         tilcdc_crtc->simulate_vesa_sync = simulate_vesa_sync;
 669 }
 670
 671 void tilcdc_crtc_update_clk(struct drm_crtc *crtc)
 672 {
 673         struct drm_device *dev = crtc->dev;
 674         struct tilcdc_drm_private *priv = dev->dev_private;
 675         struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
 676
 677         drm_modeset_lock_crtc(crtc, NULL);
 678         if (tilcdc_crtc->lcd_fck_rate != clk_get_rate(priv->clk)) {
 679                 if (tilcdc_crtc_is_on(crtc)) {
 680                         pm_runtime_get_sync(dev->dev);
 681                         tilcdc_crtc_disable(crtc);
 682
 683                         tilcdc_crtc_set_clk(crtc);
 684
 685                         tilcdc_crtc_enable(crtc);
 686                         pm_runtime_put_sync(dev->dev);
 687                 }
 688         }
 689         drm_modeset_unlock_crtc(crtc);
 690 }
 691
 692 #define SYNC_LOST_COUNT_LIMIT 50
 693
 694 irqreturn_t tilcdc_crtc_irq(struct drm_crtc *crtc)
 695 {
 696         struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
 697         struct drm_device *dev = crtc->dev;
 698         struct tilcdc_drm_private *priv = dev->dev_private;
 699         uint32_t stat;
 700
 701         stat = tilcdc_read_irqstatus(dev);
 702         tilcdc_clear_irqstatus(dev, stat);
 703
 704         if (stat & LCDC_END_OF_FRAME0) {
 705                 unsigned long flags;
 706                 bool skip_event = false;
 707                 ktime_t now;
 708
 709                 now = ktime_get();
 710
 711                 drm_flip_work_commit(&tilcdc_crtc->unref_work, priv->wq);
 712
 713                 spin_lock_irqsave(&tilcdc_crtc->irq_lock, flags);
 714
 715                 tilcdc_crtc->last_vblank = now;
 716
 717                 if (tilcdc_crtc->next_fb) {
 718                         set_scanout(crtc, tilcdc_crtc->next_fb);
 719                         tilcdc_crtc->next_fb = NULL;
 720                         skip_event = true;
 721                 }
 722
 723                 spin_unlock_irqrestore(&tilcdc_crtc->irq_lock, flags);
 724
 725                 drm_crtc_handle_vblank(crtc);
 726
 727                 if (!skip_event) {
 728                         struct drm_pending_vblank_event *event;
 729
 730                         spin_lock_irqsave(&dev->event_lock, flags);
 731
 732                         event = tilcdc_crtc->event;
 733                         tilcdc_crtc->event = NULL;
 734                         if (event)
 735                                 drm_crtc_send_vblank_event(crtc, event);
 736
 737                         spin_unlock_irqrestore(&dev->event_lock, flags);
 738                 }
 739
 740                 if (tilcdc_crtc->frame_intact)
 741                         tilcdc_crtc->sync_lost_count = 0;
 742                 else
 743                         tilcdc_crtc->frame_intact = true;
 744         }
 745
 746         if (stat & LCDC_FIFO_UNDERFLOW)
 747                 dev_err_ratelimited(dev->dev, "%s(0x%08x): FIFO underfow",
 748                                     __func__, stat);
 749
 750         /* For revision 2 only */
 751         if (priv->rev == 2) {
 752                 if (stat & LCDC_FRAME_DONE) {
 753                         tilcdc_crtc->frame_done = true;
 754                         wake_up(&tilcdc_crtc->frame_done_wq);
 755                 }
 756
 757                 if (stat & LCDC_SYNC_LOST) {
 758                         dev_err_ratelimited(dev->dev, "%s(0x%08x): Sync lost",
 759                                             __func__, stat);
 760                         tilcdc_crtc->frame_intact = false;
 761                         if (tilcdc_crtc->sync_lost_count++ >
 762                             SYNC_LOST_COUNT_LIMIT) {
 763                                 dev_err(dev->dev, "%s(0x%08x): Sync lost flood detected, disabling the interrupt", __func__, stat);
 764                                 tilcdc_write(dev, LCDC_INT_ENABLE_CLR_REG,
 765                                              LCDC_SYNC_LOST);
 766                         }
 767                 }
 768
 769                 /* Indicate to LCDC that the interrupt service routine has
 770                  * completed, see 13.3.6.1.6 in AM335x TRM.
 771                  */
 772                 tilcdc_write(dev, LCDC_END_OF_INT_IND_REG, 0);
 773         }
 774
 775         return IRQ_HANDLED;
 776 }
 777
 778 struct drm_crtc *tilcdc_crtc_create(struct drm_device *dev)
 779 {
 780         struct tilcdc_drm_private *priv = dev->dev_private;
 781         struct tilcdc_crtc *tilcdc_crtc;
 782         struct drm_crtc *crtc;
 783         int ret;
 784
 785         tilcdc_crtc = devm_kzalloc(dev->dev, sizeof(*tilcdc_crtc), GFP_KERNEL);
 786         if (!tilcdc_crtc) {
 787                 dev_err(dev->dev, "allocation failed\n");
 788                 return NULL;
 789         }
 790
 791         crtc = &tilcdc_crtc->base;
 792
 793         ret = tilcdc_plane_init(dev, &tilcdc_crtc->primary);
 794         if (ret < 0)
 795                 goto fail;
 796
 797         init_waitqueue_head(&tilcdc_crtc->frame_done_wq);
 798
 799         drm_flip_work_init(&tilcdc_crtc->unref_work,
 800                         "unref", unref_worker);
 801
 802         spin_lock_init(&tilcdc_crtc->irq_lock);
 803
 804         ret = drm_crtc_init_with_planes(dev, crtc,
 805                                         &tilcdc_crtc->primary,
 806                                         NULL,
 807                                         &tilcdc_crtc_funcs,
 808                                         "tilcdc crtc");
 809         if (ret < 0)
 810                 goto fail;
 811
 812         drm_crtc_helper_add(crtc, &tilcdc_crtc_helper_funcs);
 813
 814         if (priv->is_componentized) {
 815                 struct device_node *ports =
 816                         of_get_child_by_name(dev->dev->of_node, "ports");
 817
 818                 if (ports) {
 819                         crtc->port = of_get_child_by_name(ports, "port");
 820                         of_node_put(ports);
 821                 } else {
 822                         crtc->port =
 823                                 of_get_child_by_name(dev->dev->of_node, "port");
 824                 }
 825                 if (!crtc->port) { /* This should never happen */
 826                         dev_err(dev->dev, "Port node not found in %s\n",
 827                                 dev->dev->of_node->full_name);
 828                         goto fail;
 829                 }
 830         }
 831
 832         return crtc;
 833
 834 fail:
 835         tilcdc_crtc_destroy(crtc);
 836         return NULL;
 837 }