1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/
4 * Author: Jyri Sarha <jsarha@ti.com>
8 #include <linux/delay.h>
9 #include <linux/dma-mapping.h>
10 #include <linux/err.h>
11 #include <linux/interrupt.h>
13 #include <linux/kernel.h>
14 #include <linux/media-bus-format.h>
15 #include <linux/module.h>
16 #include <linux/mfd/syscon.h>
18 #include <linux/platform_device.h>
19 #include <linux/pm_runtime.h>
20 #include <linux/regmap.h>
21 #include <linux/sys_soc.h>
23 #include <drm/drm_blend.h>
24 #include <drm/drm_fourcc.h>
25 #include <drm/drm_fb_dma_helper.h>
26 #include <drm/drm_framebuffer.h>
27 #include <drm/drm_gem_dma_helper.h>
28 #include <drm/drm_panel.h>
30 #include "tidss_crtc.h"
31 #include "tidss_dispc.h"
32 #include "tidss_drv.h"
33 #include "tidss_irq.h"
34 #include "tidss_plane.h"
36 #include "tidss_dispc_regs.h"
37 #include "tidss_scale_coefs.h"
39 static const u16 tidss_k2g_common_regs[DISPC_COMMON_REG_TABLE_LEN] = {
40 [DSS_REVISION_OFF] = 0x00,
41 [DSS_SYSCONFIG_OFF] = 0x04,
42 [DSS_SYSSTATUS_OFF] = 0x08,
43 [DISPC_IRQ_EOI_OFF] = 0x20,
44 [DISPC_IRQSTATUS_RAW_OFF] = 0x24,
45 [DISPC_IRQSTATUS_OFF] = 0x28,
46 [DISPC_IRQENABLE_SET_OFF] = 0x2c,
47 [DISPC_IRQENABLE_CLR_OFF] = 0x30,
49 [DISPC_GLOBAL_MFLAG_ATTRIBUTE_OFF] = 0x40,
50 [DISPC_GLOBAL_BUFFER_OFF] = 0x44,
52 [DISPC_DBG_CONTROL_OFF] = 0x4c,
53 [DISPC_DBG_STATUS_OFF] = 0x50,
55 [DISPC_CLKGATING_DISABLE_OFF] = 0x54,
58 const struct dispc_features dispc_k2g_feats = {
62 [DISPC_VP_DPI] = 150000,
66 * XXX According TRM the RGB input buffer width up to 2560 should
67 * work on 3 taps, but in practice it only works up to 1280.
70 .in_width_max_5tap_rgb = 1280,
71 .in_width_max_3tap_rgb = 1280,
72 .in_width_max_5tap_yuv = 2560,
73 .in_width_max_3tap_yuv = 2560,
75 .downscale_limit_5tap = 4,
76 .downscale_limit_3tap = 2,
78 * The max supported pixel inc value is 255. The value
79 * of pixel inc is calculated like this: 1+(xinc-1)*bpp.
80 * The maximum bpp of all formats supported by the HW
81 * is 8. So the maximum supported xinc value is 32,
82 * because 1+(32-1)*8 < 255 < 1+(33-1)*4.
91 .common_regs = tidss_k2g_common_regs,
95 .ovr_name = { "ovr1" },
96 .vpclk_name = { "vp1" },
97 .vp_bus_type = { DISPC_VP_DPI },
99 .vp_feat = { .color = {
102 .gamma_type = TIDSS_GAMMA_8BIT,
107 .vid_name = { "vid1" },
108 .vid_lite = { false },
112 static const u16 tidss_am65x_common_regs[DISPC_COMMON_REG_TABLE_LEN] = {
113 [DSS_REVISION_OFF] = 0x4,
114 [DSS_SYSCONFIG_OFF] = 0x8,
115 [DSS_SYSSTATUS_OFF] = 0x20,
116 [DISPC_IRQ_EOI_OFF] = 0x24,
117 [DISPC_IRQSTATUS_RAW_OFF] = 0x28,
118 [DISPC_IRQSTATUS_OFF] = 0x2c,
119 [DISPC_IRQENABLE_SET_OFF] = 0x30,
120 [DISPC_IRQENABLE_CLR_OFF] = 0x40,
121 [DISPC_VID_IRQENABLE_OFF] = 0x44,
122 [DISPC_VID_IRQSTATUS_OFF] = 0x58,
123 [DISPC_VP_IRQENABLE_OFF] = 0x70,
124 [DISPC_VP_IRQSTATUS_OFF] = 0x7c,
126 [WB_IRQENABLE_OFF] = 0x88,
127 [WB_IRQSTATUS_OFF] = 0x8c,
129 [DISPC_GLOBAL_MFLAG_ATTRIBUTE_OFF] = 0x90,
130 [DISPC_GLOBAL_OUTPUT_ENABLE_OFF] = 0x94,
131 [DISPC_GLOBAL_BUFFER_OFF] = 0x98,
132 [DSS_CBA_CFG_OFF] = 0x9c,
133 [DISPC_DBG_CONTROL_OFF] = 0xa0,
134 [DISPC_DBG_STATUS_OFF] = 0xa4,
135 [DISPC_CLKGATING_DISABLE_OFF] = 0xa8,
136 [DISPC_SECURE_DISABLE_OFF] = 0xac,
139 const struct dispc_features dispc_am65x_feats = {
141 [DISPC_VP_DPI] = 165000,
142 [DISPC_VP_OLDI] = 165000,
146 .in_width_max_5tap_rgb = 1280,
147 .in_width_max_3tap_rgb = 2560,
148 .in_width_max_5tap_yuv = 2560,
149 .in_width_max_3tap_yuv = 4096,
151 .downscale_limit_5tap = 4,
152 .downscale_limit_3tap = 2,
154 * The max supported pixel inc value is 255. The value
155 * of pixel inc is calculated like this: 1+(xinc-1)*bpp.
156 * The maximum bpp of all formats supported by the HW
157 * is 8. So the maximum supported xinc value is 32,
158 * because 1+(32-1)*8 < 255 < 1+(33-1)*4.
163 .subrev = DISPC_AM65X,
166 .common_regs = tidss_am65x_common_regs,
169 .vp_name = { "vp1", "vp2" },
170 .ovr_name = { "ovr1", "ovr2" },
171 .vpclk_name = { "vp1", "vp2" },
172 .vp_bus_type = { DISPC_VP_OLDI, DISPC_VP_DPI },
174 .vp_feat = { .color = {
177 .gamma_type = TIDSS_GAMMA_8BIT,
182 /* note: vid is plane_id 0 and vidl1 is plane_id 1 */
183 .vid_name = { "vid", "vidl1" },
184 .vid_lite = { false, true, },
185 .vid_order = { 1, 0 },
188 static const u16 tidss_j721e_common_regs[DISPC_COMMON_REG_TABLE_LEN] = {
189 [DSS_REVISION_OFF] = 0x4,
190 [DSS_SYSCONFIG_OFF] = 0x8,
191 [DSS_SYSSTATUS_OFF] = 0x20,
192 [DISPC_IRQ_EOI_OFF] = 0x80,
193 [DISPC_IRQSTATUS_RAW_OFF] = 0x28,
194 [DISPC_IRQSTATUS_OFF] = 0x2c,
195 [DISPC_IRQENABLE_SET_OFF] = 0x30,
196 [DISPC_IRQENABLE_CLR_OFF] = 0x34,
197 [DISPC_VID_IRQENABLE_OFF] = 0x38,
198 [DISPC_VID_IRQSTATUS_OFF] = 0x48,
199 [DISPC_VP_IRQENABLE_OFF] = 0x58,
200 [DISPC_VP_IRQSTATUS_OFF] = 0x68,
202 [WB_IRQENABLE_OFF] = 0x78,
203 [WB_IRQSTATUS_OFF] = 0x7c,
205 [DISPC_GLOBAL_MFLAG_ATTRIBUTE_OFF] = 0x98,
206 [DISPC_GLOBAL_OUTPUT_ENABLE_OFF] = 0x9c,
207 [DISPC_GLOBAL_BUFFER_OFF] = 0xa0,
208 [DSS_CBA_CFG_OFF] = 0xa4,
209 [DISPC_DBG_CONTROL_OFF] = 0xa8,
210 [DISPC_DBG_STATUS_OFF] = 0xac,
211 [DISPC_CLKGATING_DISABLE_OFF] = 0xb0,
212 [DISPC_SECURE_DISABLE_OFF] = 0x90,
214 [FBDC_REVISION_1_OFF] = 0xb8,
215 [FBDC_REVISION_2_OFF] = 0xbc,
216 [FBDC_REVISION_3_OFF] = 0xc0,
217 [FBDC_REVISION_4_OFF] = 0xc4,
218 [FBDC_REVISION_5_OFF] = 0xc8,
219 [FBDC_REVISION_6_OFF] = 0xcc,
220 [FBDC_COMMON_CONTROL_OFF] = 0xd0,
221 [FBDC_CONSTANT_COLOR_0_OFF] = 0xd4,
222 [FBDC_CONSTANT_COLOR_1_OFF] = 0xd8,
223 [DISPC_CONNECTIONS_OFF] = 0xe4,
224 [DISPC_MSS_VP1_OFF] = 0xe8,
225 [DISPC_MSS_VP3_OFF] = 0xec,
228 const struct dispc_features dispc_j721e_feats = {
230 [DISPC_VP_DPI] = 170000,
231 [DISPC_VP_INTERNAL] = 600000,
235 .in_width_max_5tap_rgb = 2048,
236 .in_width_max_3tap_rgb = 4096,
237 .in_width_max_5tap_yuv = 4096,
238 .in_width_max_3tap_yuv = 4096,
240 .downscale_limit_5tap = 4,
241 .downscale_limit_3tap = 2,
243 * The max supported pixel inc value is 255. The value
244 * of pixel inc is calculated like this: 1+(xinc-1)*bpp.
245 * The maximum bpp of all formats supported by the HW
246 * is 8. So the maximum supported xinc value is 32,
247 * because 1+(32-1)*8 < 255 < 1+(33-1)*4.
252 .subrev = DISPC_J721E,
254 .common = "common_m",
255 .common_regs = tidss_j721e_common_regs,
258 .vp_name = { "vp1", "vp2", "vp3", "vp4" },
259 .ovr_name = { "ovr1", "ovr2", "ovr3", "ovr4" },
260 .vpclk_name = { "vp1", "vp2", "vp3", "vp4" },
261 /* Currently hard coded VP routing (see dispc_initial_config()) */
262 .vp_bus_type = { DISPC_VP_INTERNAL, DISPC_VP_DPI,
263 DISPC_VP_INTERNAL, DISPC_VP_DPI, },
264 .vp_feat = { .color = {
267 .gamma_type = TIDSS_GAMMA_10BIT,
271 .vid_name = { "vid1", "vidl1", "vid2", "vidl2" },
272 .vid_lite = { 0, 1, 0, 1, },
273 .vid_order = { 1, 3, 0, 2 },
276 const struct dispc_features dispc_am625_feats = {
278 [DISPC_VP_DPI] = 165000,
279 [DISPC_VP_INTERNAL] = 170000,
283 .in_width_max_5tap_rgb = 1280,
284 .in_width_max_3tap_rgb = 2560,
285 .in_width_max_5tap_yuv = 2560,
286 .in_width_max_3tap_yuv = 4096,
288 .downscale_limit_5tap = 4,
289 .downscale_limit_3tap = 2,
291 * The max supported pixel inc value is 255. The value
292 * of pixel inc is calculated like this: 1+(xinc-1)*bpp.
293 * The maximum bpp of all formats supported by the HW
294 * is 8. So the maximum supported xinc value is 32,
295 * because 1+(32-1)*8 < 255 < 1+(33-1)*4.
300 .subrev = DISPC_AM625,
303 .common_regs = tidss_am65x_common_regs,
306 .vp_name = { "vp1", "vp2" },
307 .ovr_name = { "ovr1", "ovr2" },
308 .vpclk_name = { "vp1", "vp2" },
309 .vp_bus_type = { DISPC_VP_INTERNAL, DISPC_VP_DPI },
311 .vp_feat = { .color = {
314 .gamma_type = TIDSS_GAMMA_8BIT,
319 /* note: vid is plane_id 0 and vidl1 is plane_id 1 */
320 .vid_name = { "vid", "vidl1" },
321 .vid_lite = { false, true, },
322 .vid_order = { 1, 0 },
325 static const u16 *dispc_common_regmap;
331 struct dispc_device {
332 struct tidss_device *tidss;
335 void __iomem *base_common;
336 void __iomem *base_vid[TIDSS_MAX_PLANES];
337 void __iomem *base_ovr[TIDSS_MAX_PORTS];
338 void __iomem *base_vp[TIDSS_MAX_PORTS];
340 struct regmap *oldi_io_ctrl;
342 struct clk *vp_clk[TIDSS_MAX_PORTS];
344 const struct dispc_features *feat;
350 struct dss_vp_data vp_data[TIDSS_MAX_PORTS];
355 u32 memory_bandwidth_limit;
357 struct dispc_errata errata;
360 static void dispc_write(struct dispc_device *dispc, u16 reg, u32 val)
362 iowrite32(val, dispc->base_common + reg);
365 static u32 dispc_read(struct dispc_device *dispc, u16 reg)
367 return ioread32(dispc->base_common + reg);
371 void dispc_vid_write(struct dispc_device *dispc, u32 hw_plane, u16 reg, u32 val)
373 void __iomem *base = dispc->base_vid[hw_plane];
375 iowrite32(val, base + reg);
378 static u32 dispc_vid_read(struct dispc_device *dispc, u32 hw_plane, u16 reg)
380 void __iomem *base = dispc->base_vid[hw_plane];
382 return ioread32(base + reg);
385 static void dispc_ovr_write(struct dispc_device *dispc, u32 hw_videoport,
388 void __iomem *base = dispc->base_ovr[hw_videoport];
390 iowrite32(val, base + reg);
393 static u32 dispc_ovr_read(struct dispc_device *dispc, u32 hw_videoport, u16 reg)
395 void __iomem *base = dispc->base_ovr[hw_videoport];
397 return ioread32(base + reg);
400 static void dispc_vp_write(struct dispc_device *dispc, u32 hw_videoport,
403 void __iomem *base = dispc->base_vp[hw_videoport];
405 iowrite32(val, base + reg);
408 static u32 dispc_vp_read(struct dispc_device *dispc, u32 hw_videoport, u16 reg)
410 void __iomem *base = dispc->base_vp[hw_videoport];
412 return ioread32(base + reg);
416 * TRM gives bitfields as start:end, where start is the higher bit
417 * number. For example 7:0
420 static u32 FLD_MASK(u32 start, u32 end)
422 return ((1 << (start - end + 1)) - 1) << end;
425 static u32 FLD_VAL(u32 val, u32 start, u32 end)
427 return (val << end) & FLD_MASK(start, end);
430 static u32 FLD_GET(u32 val, u32 start, u32 end)
432 return (val & FLD_MASK(start, end)) >> end;
435 static u32 FLD_MOD(u32 orig, u32 val, u32 start, u32 end)
437 return (orig & ~FLD_MASK(start, end)) | FLD_VAL(val, start, end);
440 static u32 REG_GET(struct dispc_device *dispc, u32 idx, u32 start, u32 end)
442 return FLD_GET(dispc_read(dispc, idx), start, end);
445 static void REG_FLD_MOD(struct dispc_device *dispc, u32 idx, u32 val,
448 dispc_write(dispc, idx, FLD_MOD(dispc_read(dispc, idx), val,
452 static u32 VID_REG_GET(struct dispc_device *dispc, u32 hw_plane, u32 idx,
455 return FLD_GET(dispc_vid_read(dispc, hw_plane, idx), start, end);
458 static void VID_REG_FLD_MOD(struct dispc_device *dispc, u32 hw_plane, u32 idx,
459 u32 val, u32 start, u32 end)
461 dispc_vid_write(dispc, hw_plane, idx,
462 FLD_MOD(dispc_vid_read(dispc, hw_plane, idx),
466 static u32 VP_REG_GET(struct dispc_device *dispc, u32 vp, u32 idx,
469 return FLD_GET(dispc_vp_read(dispc, vp, idx), start, end);
472 static void VP_REG_FLD_MOD(struct dispc_device *dispc, u32 vp, u32 idx, u32 val,
475 dispc_vp_write(dispc, vp, idx, FLD_MOD(dispc_vp_read(dispc, vp, idx),
480 static u32 OVR_REG_GET(struct dispc_device *dispc, u32 ovr, u32 idx,
483 return FLD_GET(dispc_ovr_read(dispc, ovr, idx), start, end);
486 static void OVR_REG_FLD_MOD(struct dispc_device *dispc, u32 ovr, u32 idx,
487 u32 val, u32 start, u32 end)
489 dispc_ovr_write(dispc, ovr, idx,
490 FLD_MOD(dispc_ovr_read(dispc, ovr, idx),
494 static dispc_irq_t dispc_vp_irq_from_raw(u32 stat, u32 hw_videoport)
496 dispc_irq_t vp_stat = 0;
499 vp_stat |= DSS_IRQ_VP_FRAME_DONE(hw_videoport);
501 vp_stat |= DSS_IRQ_VP_VSYNC_EVEN(hw_videoport);
503 vp_stat |= DSS_IRQ_VP_VSYNC_ODD(hw_videoport);
505 vp_stat |= DSS_IRQ_VP_SYNC_LOST(hw_videoport);
510 static u32 dispc_vp_irq_to_raw(dispc_irq_t vpstat, u32 hw_videoport)
514 if (vpstat & DSS_IRQ_VP_FRAME_DONE(hw_videoport))
516 if (vpstat & DSS_IRQ_VP_VSYNC_EVEN(hw_videoport))
518 if (vpstat & DSS_IRQ_VP_VSYNC_ODD(hw_videoport))
520 if (vpstat & DSS_IRQ_VP_SYNC_LOST(hw_videoport))
526 static dispc_irq_t dispc_vid_irq_from_raw(u32 stat, u32 hw_plane)
528 dispc_irq_t vid_stat = 0;
531 vid_stat |= DSS_IRQ_PLANE_FIFO_UNDERFLOW(hw_plane);
536 static u32 dispc_vid_irq_to_raw(dispc_irq_t vidstat, u32 hw_plane)
540 if (vidstat & DSS_IRQ_PLANE_FIFO_UNDERFLOW(hw_plane))
546 static dispc_irq_t dispc_k2g_vp_read_irqstatus(struct dispc_device *dispc,
549 u32 stat = dispc_vp_read(dispc, hw_videoport, DISPC_VP_K2G_IRQSTATUS);
551 return dispc_vp_irq_from_raw(stat, hw_videoport);
554 static void dispc_k2g_vp_write_irqstatus(struct dispc_device *dispc,
555 u32 hw_videoport, dispc_irq_t vpstat)
557 u32 stat = dispc_vp_irq_to_raw(vpstat, hw_videoport);
559 dispc_vp_write(dispc, hw_videoport, DISPC_VP_K2G_IRQSTATUS, stat);
562 static dispc_irq_t dispc_k2g_vid_read_irqstatus(struct dispc_device *dispc,
565 u32 stat = dispc_vid_read(dispc, hw_plane, DISPC_VID_K2G_IRQSTATUS);
567 return dispc_vid_irq_from_raw(stat, hw_plane);
570 static void dispc_k2g_vid_write_irqstatus(struct dispc_device *dispc,
571 u32 hw_plane, dispc_irq_t vidstat)
573 u32 stat = dispc_vid_irq_to_raw(vidstat, hw_plane);
575 dispc_vid_write(dispc, hw_plane, DISPC_VID_K2G_IRQSTATUS, stat);
578 static dispc_irq_t dispc_k2g_vp_read_irqenable(struct dispc_device *dispc,
581 u32 stat = dispc_vp_read(dispc, hw_videoport, DISPC_VP_K2G_IRQENABLE);
583 return dispc_vp_irq_from_raw(stat, hw_videoport);
586 static void dispc_k2g_vp_set_irqenable(struct dispc_device *dispc,
587 u32 hw_videoport, dispc_irq_t vpstat)
589 u32 stat = dispc_vp_irq_to_raw(vpstat, hw_videoport);
591 dispc_vp_write(dispc, hw_videoport, DISPC_VP_K2G_IRQENABLE, stat);
594 static dispc_irq_t dispc_k2g_vid_read_irqenable(struct dispc_device *dispc,
597 u32 stat = dispc_vid_read(dispc, hw_plane, DISPC_VID_K2G_IRQENABLE);
599 return dispc_vid_irq_from_raw(stat, hw_plane);
602 static void dispc_k2g_vid_set_irqenable(struct dispc_device *dispc,
603 u32 hw_plane, dispc_irq_t vidstat)
605 u32 stat = dispc_vid_irq_to_raw(vidstat, hw_plane);
607 dispc_vid_write(dispc, hw_plane, DISPC_VID_K2G_IRQENABLE, stat);
610 static void dispc_k2g_clear_irqstatus(struct dispc_device *dispc,
613 dispc_k2g_vp_write_irqstatus(dispc, 0, mask);
614 dispc_k2g_vid_write_irqstatus(dispc, 0, mask);
618 dispc_irq_t dispc_k2g_read_and_clear_irqstatus(struct dispc_device *dispc)
620 dispc_irq_t stat = 0;
622 /* always clear the top level irqstatus */
623 dispc_write(dispc, DISPC_IRQSTATUS,
624 dispc_read(dispc, DISPC_IRQSTATUS));
626 stat |= dispc_k2g_vp_read_irqstatus(dispc, 0);
627 stat |= dispc_k2g_vid_read_irqstatus(dispc, 0);
629 dispc_k2g_clear_irqstatus(dispc, stat);
634 static dispc_irq_t dispc_k2g_read_irqenable(struct dispc_device *dispc)
636 dispc_irq_t stat = 0;
638 stat |= dispc_k2g_vp_read_irqenable(dispc, 0);
639 stat |= dispc_k2g_vid_read_irqenable(dispc, 0);
645 void dispc_k2g_set_irqenable(struct dispc_device *dispc, dispc_irq_t mask)
647 dispc_irq_t old_mask = dispc_k2g_read_irqenable(dispc);
649 /* clear the irqstatus for newly enabled irqs */
650 dispc_k2g_clear_irqstatus(dispc, (mask ^ old_mask) & mask);
652 dispc_k2g_vp_set_irqenable(dispc, 0, mask);
653 dispc_k2g_vid_set_irqenable(dispc, 0, mask);
655 dispc_write(dispc, DISPC_IRQENABLE_SET, (1 << 0) | (1 << 7));
657 /* flush posted write */
658 dispc_k2g_read_irqenable(dispc);
661 static dispc_irq_t dispc_k3_vp_read_irqstatus(struct dispc_device *dispc,
664 u32 stat = dispc_read(dispc, DISPC_VP_IRQSTATUS(hw_videoport));
666 return dispc_vp_irq_from_raw(stat, hw_videoport);
669 static void dispc_k3_vp_write_irqstatus(struct dispc_device *dispc,
670 u32 hw_videoport, dispc_irq_t vpstat)
672 u32 stat = dispc_vp_irq_to_raw(vpstat, hw_videoport);
674 dispc_write(dispc, DISPC_VP_IRQSTATUS(hw_videoport), stat);
677 static dispc_irq_t dispc_k3_vid_read_irqstatus(struct dispc_device *dispc,
680 u32 stat = dispc_read(dispc, DISPC_VID_IRQSTATUS(hw_plane));
682 return dispc_vid_irq_from_raw(stat, hw_plane);
685 static void dispc_k3_vid_write_irqstatus(struct dispc_device *dispc,
686 u32 hw_plane, dispc_irq_t vidstat)
688 u32 stat = dispc_vid_irq_to_raw(vidstat, hw_plane);
690 dispc_write(dispc, DISPC_VID_IRQSTATUS(hw_plane), stat);
693 static dispc_irq_t dispc_k3_vp_read_irqenable(struct dispc_device *dispc,
696 u32 stat = dispc_read(dispc, DISPC_VP_IRQENABLE(hw_videoport));
698 return dispc_vp_irq_from_raw(stat, hw_videoport);
701 static void dispc_k3_vp_set_irqenable(struct dispc_device *dispc,
702 u32 hw_videoport, dispc_irq_t vpstat)
704 u32 stat = dispc_vp_irq_to_raw(vpstat, hw_videoport);
706 dispc_write(dispc, DISPC_VP_IRQENABLE(hw_videoport), stat);
709 static dispc_irq_t dispc_k3_vid_read_irqenable(struct dispc_device *dispc,
712 u32 stat = dispc_read(dispc, DISPC_VID_IRQENABLE(hw_plane));
714 return dispc_vid_irq_from_raw(stat, hw_plane);
717 static void dispc_k3_vid_set_irqenable(struct dispc_device *dispc,
718 u32 hw_plane, dispc_irq_t vidstat)
720 u32 stat = dispc_vid_irq_to_raw(vidstat, hw_plane);
722 dispc_write(dispc, DISPC_VID_IRQENABLE(hw_plane), stat);
726 void dispc_k3_clear_irqstatus(struct dispc_device *dispc, dispc_irq_t clearmask)
731 for (i = 0; i < dispc->feat->num_vps; ++i) {
732 if (clearmask & DSS_IRQ_VP_MASK(i)) {
733 dispc_k3_vp_write_irqstatus(dispc, i, clearmask);
737 for (i = 0; i < dispc->feat->num_planes; ++i) {
738 if (clearmask & DSS_IRQ_PLANE_MASK(i)) {
739 dispc_k3_vid_write_irqstatus(dispc, i, clearmask);
740 top_clear |= BIT(4 + i);
743 if (dispc->feat->subrev == DISPC_K2G)
746 dispc_write(dispc, DISPC_IRQSTATUS, top_clear);
748 /* Flush posted writes */
749 dispc_read(dispc, DISPC_IRQSTATUS);
753 dispc_irq_t dispc_k3_read_and_clear_irqstatus(struct dispc_device *dispc)
755 dispc_irq_t status = 0;
758 for (i = 0; i < dispc->feat->num_vps; ++i)
759 status |= dispc_k3_vp_read_irqstatus(dispc, i);
761 for (i = 0; i < dispc->feat->num_planes; ++i)
762 status |= dispc_k3_vid_read_irqstatus(dispc, i);
764 dispc_k3_clear_irqstatus(dispc, status);
769 static dispc_irq_t dispc_k3_read_irqenable(struct dispc_device *dispc)
771 dispc_irq_t enable = 0;
774 for (i = 0; i < dispc->feat->num_vps; ++i)
775 enable |= dispc_k3_vp_read_irqenable(dispc, i);
777 for (i = 0; i < dispc->feat->num_planes; ++i)
778 enable |= dispc_k3_vid_read_irqenable(dispc, i);
783 static void dispc_k3_set_irqenable(struct dispc_device *dispc,
787 u32 main_enable = 0, main_disable = 0;
788 dispc_irq_t old_mask;
790 old_mask = dispc_k3_read_irqenable(dispc);
792 /* clear the irqstatus for newly enabled irqs */
793 dispc_k3_clear_irqstatus(dispc, (old_mask ^ mask) & mask);
795 for (i = 0; i < dispc->feat->num_vps; ++i) {
796 dispc_k3_vp_set_irqenable(dispc, i, mask);
797 if (mask & DSS_IRQ_VP_MASK(i))
798 main_enable |= BIT(i); /* VP IRQ */
800 main_disable |= BIT(i); /* VP IRQ */
803 for (i = 0; i < dispc->feat->num_planes; ++i) {
804 dispc_k3_vid_set_irqenable(dispc, i, mask);
805 if (mask & DSS_IRQ_PLANE_MASK(i))
806 main_enable |= BIT(i + 4); /* VID IRQ */
808 main_disable |= BIT(i + 4); /* VID IRQ */
812 dispc_write(dispc, DISPC_IRQENABLE_SET, main_enable);
815 dispc_write(dispc, DISPC_IRQENABLE_CLR, main_disable);
817 /* Flush posted writes */
818 dispc_read(dispc, DISPC_IRQENABLE_SET);
821 dispc_irq_t dispc_read_and_clear_irqstatus(struct dispc_device *dispc)
823 switch (dispc->feat->subrev) {
825 return dispc_k2g_read_and_clear_irqstatus(dispc);
829 return dispc_k3_read_and_clear_irqstatus(dispc);
836 void dispc_set_irqenable(struct dispc_device *dispc, dispc_irq_t mask)
838 switch (dispc->feat->subrev) {
840 dispc_k2g_set_irqenable(dispc, mask);
845 dispc_k3_set_irqenable(dispc, mask);
853 enum dispc_oldi_mode_reg_val { SPWG_18 = 0, JEIDA_24 = 1, SPWG_24 = 2 };
855 struct dispc_bus_format {
859 enum dispc_oldi_mode_reg_val oldi_mode_reg_val;
862 static const struct dispc_bus_format dispc_bus_formats[] = {
863 { MEDIA_BUS_FMT_RGB444_1X12, 12, false, 0 },
864 { MEDIA_BUS_FMT_RGB565_1X16, 16, false, 0 },
865 { MEDIA_BUS_FMT_RGB666_1X18, 18, false, 0 },
866 { MEDIA_BUS_FMT_RGB888_1X24, 24, false, 0 },
867 { MEDIA_BUS_FMT_RGB101010_1X30, 30, false, 0 },
868 { MEDIA_BUS_FMT_RGB121212_1X36, 36, false, 0 },
869 { MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 18, true, SPWG_18 },
870 { MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 24, true, SPWG_24 },
871 { MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 24, true, JEIDA_24 },
875 struct dispc_bus_format *dispc_vp_find_bus_fmt(struct dispc_device *dispc,
877 u32 bus_fmt, u32 bus_flags)
881 for (i = 0; i < ARRAY_SIZE(dispc_bus_formats); ++i) {
882 if (dispc_bus_formats[i].bus_fmt == bus_fmt)
883 return &dispc_bus_formats[i];
889 int dispc_vp_bus_check(struct dispc_device *dispc, u32 hw_videoport,
890 const struct drm_crtc_state *state)
892 const struct tidss_crtc_state *tstate = to_tidss_crtc_state(state);
893 const struct dispc_bus_format *fmt;
895 fmt = dispc_vp_find_bus_fmt(dispc, hw_videoport, tstate->bus_format,
898 dev_dbg(dispc->dev, "%s: Unsupported bus format: %u\n",
899 __func__, tstate->bus_format);
903 if (dispc->feat->vp_bus_type[hw_videoport] != DISPC_VP_OLDI &&
905 dev_dbg(dispc->dev, "%s: %s is not OLDI-port\n",
906 __func__, dispc->feat->vp_name[hw_videoport]);
913 static void dispc_oldi_tx_power(struct dispc_device *dispc, bool power)
915 u32 val = power ? 0 : OLDI_PWRDN_TX;
917 if (WARN_ON(!dispc->oldi_io_ctrl))
920 regmap_update_bits(dispc->oldi_io_ctrl, OLDI_DAT0_IO_CTRL,
922 regmap_update_bits(dispc->oldi_io_ctrl, OLDI_DAT1_IO_CTRL,
924 regmap_update_bits(dispc->oldi_io_ctrl, OLDI_DAT2_IO_CTRL,
926 regmap_update_bits(dispc->oldi_io_ctrl, OLDI_DAT3_IO_CTRL,
928 regmap_update_bits(dispc->oldi_io_ctrl, OLDI_CLK_IO_CTRL,
932 static void dispc_set_num_datalines(struct dispc_device *dispc,
933 u32 hw_videoport, int num_lines)
955 VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONTROL, v, 10, 8);
958 static void dispc_enable_oldi(struct dispc_device *dispc, u32 hw_videoport,
959 const struct dispc_bus_format *fmt)
962 u32 oldi_reset_bit = BIT(5 + hw_videoport);
966 * For the moment DUALMODESYNC, MASTERSLAVE, MODE, and SRC
967 * bits of DISPC_VP_DSS_OLDI_CFG are set statically to 0.
970 if (fmt->data_width == 24)
971 oldi_cfg |= BIT(8); /* MSB */
972 else if (fmt->data_width != 18)
973 dev_warn(dispc->dev, "%s: %d port width not supported\n",
974 __func__, fmt->data_width);
976 oldi_cfg |= BIT(7); /* DEPOL */
978 oldi_cfg = FLD_MOD(oldi_cfg, fmt->oldi_mode_reg_val, 3, 1);
980 oldi_cfg |= BIT(12); /* SOFTRST */
982 oldi_cfg |= BIT(0); /* ENABLE */
984 dispc_vp_write(dispc, hw_videoport, DISPC_VP_DSS_OLDI_CFG, oldi_cfg);
986 while (!(oldi_reset_bit & dispc_read(dispc, DSS_SYSSTATUS)) &&
990 if (!(oldi_reset_bit & dispc_read(dispc, DSS_SYSSTATUS)))
991 dev_warn(dispc->dev, "%s: timeout waiting OLDI reset done\n",
995 void dispc_vp_prepare(struct dispc_device *dispc, u32 hw_videoport,
996 const struct drm_crtc_state *state)
998 const struct tidss_crtc_state *tstate = to_tidss_crtc_state(state);
999 const struct dispc_bus_format *fmt;
1001 fmt = dispc_vp_find_bus_fmt(dispc, hw_videoport, tstate->bus_format,
1007 if (dispc->feat->vp_bus_type[hw_videoport] == DISPC_VP_OLDI) {
1008 dispc_oldi_tx_power(dispc, true);
1010 dispc_enable_oldi(dispc, hw_videoport, fmt);
1014 void dispc_vp_enable(struct dispc_device *dispc, u32 hw_videoport,
1015 const struct drm_crtc_state *state)
1017 const struct drm_display_mode *mode = &state->adjusted_mode;
1018 const struct tidss_crtc_state *tstate = to_tidss_crtc_state(state);
1019 bool align, onoff, rf, ieo, ipc, ihs, ivs;
1020 const struct dispc_bus_format *fmt;
1021 u32 hsw, hfp, hbp, vsw, vfp, vbp;
1023 fmt = dispc_vp_find_bus_fmt(dispc, hw_videoport, tstate->bus_format,
1029 dispc_set_num_datalines(dispc, hw_videoport, fmt->data_width);
1031 hfp = mode->hsync_start - mode->hdisplay;
1032 hsw = mode->hsync_end - mode->hsync_start;
1033 hbp = mode->htotal - mode->hsync_end;
1035 vfp = mode->vsync_start - mode->vdisplay;
1036 vsw = mode->vsync_end - mode->vsync_start;
1037 vbp = mode->vtotal - mode->vsync_end;
1039 dispc_vp_write(dispc, hw_videoport, DISPC_VP_TIMING_H,
1040 FLD_VAL(hsw - 1, 7, 0) |
1041 FLD_VAL(hfp - 1, 19, 8) |
1042 FLD_VAL(hbp - 1, 31, 20));
1044 dispc_vp_write(dispc, hw_videoport, DISPC_VP_TIMING_V,
1045 FLD_VAL(vsw - 1, 7, 0) |
1046 FLD_VAL(vfp, 19, 8) |
1047 FLD_VAL(vbp, 31, 20));
1049 ivs = !!(mode->flags & DRM_MODE_FLAG_NVSYNC);
1051 ihs = !!(mode->flags & DRM_MODE_FLAG_NHSYNC);
1053 ieo = !!(tstate->bus_flags & DRM_BUS_FLAG_DE_LOW);
1055 ipc = !!(tstate->bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE);
1057 /* always use the 'rf' setting */
1060 rf = !!(tstate->bus_flags & DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE);
1062 /* always use aligned syncs */
1065 /* always use DE_HIGH for OLDI */
1066 if (dispc->feat->vp_bus_type[hw_videoport] == DISPC_VP_OLDI)
1069 dispc_vp_write(dispc, hw_videoport, DISPC_VP_POL_FREQ,
1070 FLD_VAL(align, 18, 18) |
1071 FLD_VAL(onoff, 17, 17) |
1072 FLD_VAL(rf, 16, 16) |
1073 FLD_VAL(ieo, 15, 15) |
1074 FLD_VAL(ipc, 14, 14) |
1075 FLD_VAL(ihs, 13, 13) |
1076 FLD_VAL(ivs, 12, 12));
1078 dispc_vp_write(dispc, hw_videoport, DISPC_VP_SIZE_SCREEN,
1079 FLD_VAL(mode->hdisplay - 1, 11, 0) |
1080 FLD_VAL(mode->vdisplay - 1, 27, 16));
1082 VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONTROL, 1, 0, 0);
1085 void dispc_vp_disable(struct dispc_device *dispc, u32 hw_videoport)
1087 VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONTROL, 0, 0, 0);
1090 void dispc_vp_unprepare(struct dispc_device *dispc, u32 hw_videoport)
1092 if (dispc->feat->vp_bus_type[hw_videoport] == DISPC_VP_OLDI) {
1093 dispc_vp_write(dispc, hw_videoport, DISPC_VP_DSS_OLDI_CFG, 0);
1095 dispc_oldi_tx_power(dispc, false);
1099 bool dispc_vp_go_busy(struct dispc_device *dispc, u32 hw_videoport)
1101 return VP_REG_GET(dispc, hw_videoport, DISPC_VP_CONTROL, 5, 5);
1104 void dispc_vp_go(struct dispc_device *dispc, u32 hw_videoport)
1106 WARN_ON(VP_REG_GET(dispc, hw_videoport, DISPC_VP_CONTROL, 5, 5));
1107 VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONTROL, 1, 5, 5);
1110 enum c8_to_c12_mode { C8_TO_C12_REPLICATE, C8_TO_C12_MAX, C8_TO_C12_MIN };
1112 static u16 c8_to_c12(u8 c8, enum c8_to_c12_mode mode)
1119 case C8_TO_C12_REPLICATE:
1120 /* Copy c8 4 MSB to 4 LSB for full scale c12 */
1134 static u64 argb8888_to_argb12121212(u32 argb8888, enum c8_to_c12_mode m)
1139 a = (argb8888 >> 24) & 0xff;
1140 r = (argb8888 >> 16) & 0xff;
1141 g = (argb8888 >> 8) & 0xff;
1142 b = (argb8888 >> 0) & 0xff;
1144 v = ((u64)c8_to_c12(a, m) << 36) | ((u64)c8_to_c12(r, m) << 24) |
1145 ((u64)c8_to_c12(g, m) << 12) | (u64)c8_to_c12(b, m);
1150 static void dispc_vp_set_default_color(struct dispc_device *dispc,
1151 u32 hw_videoport, u32 default_color)
1155 v = argb8888_to_argb12121212(default_color, C8_TO_C12_REPLICATE);
1157 dispc_ovr_write(dispc, hw_videoport,
1158 DISPC_OVR_DEFAULT_COLOR, v & 0xffffffff);
1159 dispc_ovr_write(dispc, hw_videoport,
1160 DISPC_OVR_DEFAULT_COLOR2, (v >> 32) & 0xffff);
1163 enum drm_mode_status dispc_vp_mode_valid(struct dispc_device *dispc,
1165 const struct drm_display_mode *mode)
1167 u32 hsw, hfp, hbp, vsw, vfp, vbp;
1168 enum dispc_vp_bus_type bus_type;
1171 bus_type = dispc->feat->vp_bus_type[hw_videoport];
1173 max_pclk = dispc->feat->max_pclk_khz[bus_type];
1175 if (WARN_ON(max_pclk == 0))
1178 if (mode->clock < dispc->feat->min_pclk_khz)
1179 return MODE_CLOCK_LOW;
1181 if (mode->clock > max_pclk)
1182 return MODE_CLOCK_HIGH;
1184 if (mode->hdisplay > 4096)
1187 if (mode->vdisplay > 4096)
1190 /* TODO: add interlace support */
1191 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1192 return MODE_NO_INTERLACE;
1195 * Enforce the output width is divisible by 2. Actually this
1196 * is only needed in following cases:
1197 * - YUV output selected (BT656, BT1120)
1198 * - Dithering enabled
1199 * - TDM with TDMCycleFormat == 3
1200 * But for simplicity we enforce that always.
1202 if ((mode->hdisplay % 2) != 0)
1203 return MODE_BAD_HVALUE;
1205 hfp = mode->hsync_start - mode->hdisplay;
1206 hsw = mode->hsync_end - mode->hsync_start;
1207 hbp = mode->htotal - mode->hsync_end;
1209 vfp = mode->vsync_start - mode->vdisplay;
1210 vsw = mode->vsync_end - mode->vsync_start;
1211 vbp = mode->vtotal - mode->vsync_end;
1213 if (hsw < 1 || hsw > 256 ||
1214 hfp < 1 || hfp > 4096 ||
1215 hbp < 1 || hbp > 4096)
1216 return MODE_BAD_HVALUE;
1218 if (vsw < 1 || vsw > 256 ||
1219 vfp > 4095 || vbp > 4095)
1220 return MODE_BAD_VVALUE;
1222 if (dispc->memory_bandwidth_limit) {
1223 const unsigned int bpp = 4;
1226 bandwidth = 1000 * mode->clock;
1227 bandwidth = bandwidth * mode->hdisplay * mode->vdisplay * bpp;
1228 bandwidth = div_u64(bandwidth, mode->htotal * mode->vtotal);
1230 if (dispc->memory_bandwidth_limit < bandwidth)
1237 int dispc_vp_enable_clk(struct dispc_device *dispc, u32 hw_videoport)
1239 int ret = clk_prepare_enable(dispc->vp_clk[hw_videoport]);
1242 dev_err(dispc->dev, "%s: enabling clk failed: %d\n", __func__,
1248 void dispc_vp_disable_clk(struct dispc_device *dispc, u32 hw_videoport)
1250 clk_disable_unprepare(dispc->vp_clk[hw_videoport]);
1254 * Calculate the percentage difference between the requested pixel clock rate
1255 * and the effective rate resulting from calculating the clock divider value.
1258 unsigned int dispc_pclk_diff(unsigned long rate, unsigned long real_rate)
1260 int r = rate / 100, rr = real_rate / 100;
1262 return (unsigned int)(abs(((rr - r) * 100) / r));
1265 int dispc_vp_set_clk_rate(struct dispc_device *dispc, u32 hw_videoport,
1269 unsigned long new_rate;
1271 r = clk_set_rate(dispc->vp_clk[hw_videoport], rate);
1273 dev_err(dispc->dev, "vp%d: failed to set clk rate to %lu\n",
1274 hw_videoport, rate);
1278 new_rate = clk_get_rate(dispc->vp_clk[hw_videoport]);
1280 if (dispc_pclk_diff(rate, new_rate) > 5)
1281 dev_warn(dispc->dev,
1282 "vp%d: Clock rate %lu differs over 5%% from requested %lu\n",
1283 hw_videoport, new_rate, rate);
1285 dev_dbg(dispc->dev, "vp%d: new rate %lu Hz (requested %lu Hz)\n",
1286 hw_videoport, clk_get_rate(dispc->vp_clk[hw_videoport]), rate);
1292 static void dispc_k2g_ovr_set_plane(struct dispc_device *dispc,
1293 u32 hw_plane, u32 hw_videoport,
1294 u32 x, u32 y, u32 layer)
1296 /* On k2g there is only one plane and no need for ovr */
1297 dispc_vid_write(dispc, hw_plane, DISPC_VID_K2G_POSITION,
1301 static void dispc_am65x_ovr_set_plane(struct dispc_device *dispc,
1302 u32 hw_plane, u32 hw_videoport,
1303 u32 x, u32 y, u32 layer)
1305 OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES(layer),
1307 OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES(layer),
1309 OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES(layer),
1313 static void dispc_j721e_ovr_set_plane(struct dispc_device *dispc,
1314 u32 hw_plane, u32 hw_videoport,
1315 u32 x, u32 y, u32 layer)
1317 OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES(layer),
1319 OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES2(layer),
1321 OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES2(layer),
1325 void dispc_ovr_set_plane(struct dispc_device *dispc, u32 hw_plane,
1326 u32 hw_videoport, u32 x, u32 y, u32 layer)
1328 switch (dispc->feat->subrev) {
1330 dispc_k2g_ovr_set_plane(dispc, hw_plane, hw_videoport,
1335 dispc_am65x_ovr_set_plane(dispc, hw_plane, hw_videoport,
1339 dispc_j721e_ovr_set_plane(dispc, hw_plane, hw_videoport,
1348 void dispc_ovr_enable_layer(struct dispc_device *dispc,
1349 u32 hw_videoport, u32 layer, bool enable)
1351 if (dispc->feat->subrev == DISPC_K2G)
1354 OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES(layer),
1360 CSC_RR, CSC_RG, CSC_RB,
1361 CSC_GR, CSC_GG, CSC_GB,
1362 CSC_BR, CSC_BG, CSC_BB,
1366 CSC_RY, CSC_RCB, CSC_RCR,
1367 CSC_GY, CSC_GCB, CSC_GCR,
1368 CSC_BY, CSC_BCB, CSC_BCR,
1372 CSC_YR, CSC_YG, CSC_YB,
1373 CSC_CBR, CSC_CBG, CSC_CBB,
1374 CSC_CRR, CSC_CRG, CSC_CRB,
1377 struct dispc_csc_coef {
1378 void (*to_regval)(const struct dispc_csc_coef *csc, u32 *regval);
1382 enum { CLIP_LIMITED_RANGE = 0, CLIP_FULL_RANGE = 1, } cliping;
1386 #define DISPC_CSC_REGVAL_LEN 8
1389 void dispc_csc_offset_regval(const struct dispc_csc_coef *csc, u32 *regval)
1391 #define OVAL(x, y) (FLD_VAL(x, 15, 3) | FLD_VAL(y, 31, 19))
1392 regval[5] = OVAL(csc->preoffset[0], csc->preoffset[1]);
1393 regval[6] = OVAL(csc->preoffset[2], csc->postoffset[0]);
1394 regval[7] = OVAL(csc->postoffset[1], csc->postoffset[2]);
1398 #define CVAL(x, y) (FLD_VAL(x, 10, 0) | FLD_VAL(y, 26, 16))
1400 void dispc_csc_yuv2rgb_regval(const struct dispc_csc_coef *csc, u32 *regval)
1402 regval[0] = CVAL(csc->m[CSC_RY], csc->m[CSC_RCR]);
1403 regval[1] = CVAL(csc->m[CSC_RCB], csc->m[CSC_GY]);
1404 regval[2] = CVAL(csc->m[CSC_GCR], csc->m[CSC_GCB]);
1405 regval[3] = CVAL(csc->m[CSC_BY], csc->m[CSC_BCR]);
1406 regval[4] = CVAL(csc->m[CSC_BCB], 0);
1408 dispc_csc_offset_regval(csc, regval);
1411 __maybe_unused static
1412 void dispc_csc_rgb2yuv_regval(const struct dispc_csc_coef *csc, u32 *regval)
1414 regval[0] = CVAL(csc->m[CSC_YR], csc->m[CSC_YG]);
1415 regval[1] = CVAL(csc->m[CSC_YB], csc->m[CSC_CRR]);
1416 regval[2] = CVAL(csc->m[CSC_CRG], csc->m[CSC_CRB]);
1417 regval[3] = CVAL(csc->m[CSC_CBR], csc->m[CSC_CBG]);
1418 regval[4] = CVAL(csc->m[CSC_CBB], 0);
1420 dispc_csc_offset_regval(csc, regval);
1423 static void dispc_csc_cpr_regval(const struct dispc_csc_coef *csc,
1426 regval[0] = CVAL(csc->m[CSC_RR], csc->m[CSC_RG]);
1427 regval[1] = CVAL(csc->m[CSC_RB], csc->m[CSC_GR]);
1428 regval[2] = CVAL(csc->m[CSC_GG], csc->m[CSC_GB]);
1429 regval[3] = CVAL(csc->m[CSC_BR], csc->m[CSC_BG]);
1430 regval[4] = CVAL(csc->m[CSC_BB], 0);
1432 dispc_csc_offset_regval(csc, regval);
1437 static void dispc_k2g_vid_write_csc(struct dispc_device *dispc, u32 hw_plane,
1438 const struct dispc_csc_coef *csc)
1440 static const u16 dispc_vid_csc_coef_reg[] = {
1441 DISPC_VID_CSC_COEF(0), DISPC_VID_CSC_COEF(1),
1442 DISPC_VID_CSC_COEF(2), DISPC_VID_CSC_COEF(3),
1443 DISPC_VID_CSC_COEF(4), DISPC_VID_CSC_COEF(5),
1444 DISPC_VID_CSC_COEF(6), /* K2G has no post offset support */
1446 u32 regval[DISPC_CSC_REGVAL_LEN];
1449 csc->to_regval(csc, regval);
1452 dev_warn(dispc->dev, "%s: No post offset support for %s\n",
1453 __func__, csc->name);
1455 for (i = 0; i < ARRAY_SIZE(dispc_vid_csc_coef_reg); i++)
1456 dispc_vid_write(dispc, hw_plane, dispc_vid_csc_coef_reg[i],
1460 static void dispc_k3_vid_write_csc(struct dispc_device *dispc, u32 hw_plane,
1461 const struct dispc_csc_coef *csc)
1463 static const u16 dispc_vid_csc_coef_reg[DISPC_CSC_REGVAL_LEN] = {
1464 DISPC_VID_CSC_COEF(0), DISPC_VID_CSC_COEF(1),
1465 DISPC_VID_CSC_COEF(2), DISPC_VID_CSC_COEF(3),
1466 DISPC_VID_CSC_COEF(4), DISPC_VID_CSC_COEF(5),
1467 DISPC_VID_CSC_COEF(6), DISPC_VID_CSC_COEF7,
1469 u32 regval[DISPC_CSC_REGVAL_LEN];
1472 csc->to_regval(csc, regval);
1474 for (i = 0; i < ARRAY_SIZE(dispc_vid_csc_coef_reg); i++)
1475 dispc_vid_write(dispc, hw_plane, dispc_vid_csc_coef_reg[i],
1479 /* YUV -> RGB, ITU-R BT.601, full range */
1480 static const struct dispc_csc_coef csc_yuv2rgb_bt601_full = {
1481 dispc_csc_yuv2rgb_regval,
1482 { 256, 0, 358, /* ry, rcb, rcr |1.000 0.000 1.402|*/
1483 256, -88, -182, /* gy, gcb, gcr |1.000 -0.344 -0.714|*/
1484 256, 452, 0, }, /* by, bcb, bcr |1.000 1.772 0.000|*/
1485 { 0, -2048, -2048, }, /* full range */
1491 /* YUV -> RGB, ITU-R BT.601, limited range */
1492 static const struct dispc_csc_coef csc_yuv2rgb_bt601_lim = {
1493 dispc_csc_yuv2rgb_regval,
1494 { 298, 0, 409, /* ry, rcb, rcr |1.164 0.000 1.596|*/
1495 298, -100, -208, /* gy, gcb, gcr |1.164 -0.392 -0.813|*/
1496 298, 516, 0, }, /* by, bcb, bcr |1.164 2.017 0.000|*/
1497 { -256, -2048, -2048, }, /* limited range */
1503 /* YUV -> RGB, ITU-R BT.709, full range */
1504 static const struct dispc_csc_coef csc_yuv2rgb_bt709_full = {
1505 dispc_csc_yuv2rgb_regval,
1506 { 256, 0, 402, /* ry, rcb, rcr |1.000 0.000 1.570|*/
1507 256, -48, -120, /* gy, gcb, gcr |1.000 -0.187 -0.467|*/
1508 256, 475, 0, }, /* by, bcb, bcr |1.000 1.856 0.000|*/
1509 { 0, -2048, -2048, }, /* full range */
1515 /* YUV -> RGB, ITU-R BT.709, limited range */
1516 static const struct dispc_csc_coef csc_yuv2rgb_bt709_lim = {
1517 dispc_csc_yuv2rgb_regval,
1518 { 298, 0, 459, /* ry, rcb, rcr |1.164 0.000 1.793|*/
1519 298, -55, -136, /* gy, gcb, gcr |1.164 -0.213 -0.533|*/
1520 298, 541, 0, }, /* by, bcb, bcr |1.164 2.112 0.000|*/
1521 { -256, -2048, -2048, }, /* limited range */
1527 static const struct {
1528 enum drm_color_encoding encoding;
1529 enum drm_color_range range;
1530 const struct dispc_csc_coef *csc;
1531 } dispc_csc_table[] = {
1532 { DRM_COLOR_YCBCR_BT601, DRM_COLOR_YCBCR_FULL_RANGE,
1533 &csc_yuv2rgb_bt601_full, },
1534 { DRM_COLOR_YCBCR_BT601, DRM_COLOR_YCBCR_LIMITED_RANGE,
1535 &csc_yuv2rgb_bt601_lim, },
1536 { DRM_COLOR_YCBCR_BT709, DRM_COLOR_YCBCR_FULL_RANGE,
1537 &csc_yuv2rgb_bt709_full, },
1538 { DRM_COLOR_YCBCR_BT709, DRM_COLOR_YCBCR_LIMITED_RANGE,
1539 &csc_yuv2rgb_bt709_lim, },
1543 struct dispc_csc_coef *dispc_find_csc(enum drm_color_encoding encoding,
1544 enum drm_color_range range)
1548 for (i = 0; i < ARRAY_SIZE(dispc_csc_table); i++) {
1549 if (dispc_csc_table[i].encoding == encoding &&
1550 dispc_csc_table[i].range == range) {
1551 return dispc_csc_table[i].csc;
1557 static void dispc_vid_csc_setup(struct dispc_device *dispc, u32 hw_plane,
1558 const struct drm_plane_state *state)
1560 const struct dispc_csc_coef *coef;
1562 coef = dispc_find_csc(state->color_encoding, state->color_range);
1564 dev_err(dispc->dev, "%s: CSC (%u,%u) not found\n",
1565 __func__, state->color_encoding, state->color_range);
1569 if (dispc->feat->subrev == DISPC_K2G)
1570 dispc_k2g_vid_write_csc(dispc, hw_plane, coef);
1572 dispc_k3_vid_write_csc(dispc, hw_plane, coef);
1575 static void dispc_vid_csc_enable(struct dispc_device *dispc, u32 hw_plane,
1578 VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, !!enable, 9, 9);
1583 static u32 dispc_calc_fir_inc(u32 in, u32 out)
1585 return (u32)div_u64(0x200000ull * in, out);
1588 enum dispc_vid_fir_coef_set {
1589 DISPC_VID_FIR_COEF_HORIZ,
1590 DISPC_VID_FIR_COEF_HORIZ_UV,
1591 DISPC_VID_FIR_COEF_VERT,
1592 DISPC_VID_FIR_COEF_VERT_UV,
1595 static void dispc_vid_write_fir_coefs(struct dispc_device *dispc,
1597 enum dispc_vid_fir_coef_set coef_set,
1598 const struct tidss_scale_coefs *coefs)
1600 static const u16 c0_regs[] = {
1601 [DISPC_VID_FIR_COEF_HORIZ] = DISPC_VID_FIR_COEFS_H0,
1602 [DISPC_VID_FIR_COEF_HORIZ_UV] = DISPC_VID_FIR_COEFS_H0_C,
1603 [DISPC_VID_FIR_COEF_VERT] = DISPC_VID_FIR_COEFS_V0,
1604 [DISPC_VID_FIR_COEF_VERT_UV] = DISPC_VID_FIR_COEFS_V0_C,
1607 static const u16 c12_regs[] = {
1608 [DISPC_VID_FIR_COEF_HORIZ] = DISPC_VID_FIR_COEFS_H12,
1609 [DISPC_VID_FIR_COEF_HORIZ_UV] = DISPC_VID_FIR_COEFS_H12_C,
1610 [DISPC_VID_FIR_COEF_VERT] = DISPC_VID_FIR_COEFS_V12,
1611 [DISPC_VID_FIR_COEF_VERT_UV] = DISPC_VID_FIR_COEFS_V12_C,
1614 const u16 c0_base = c0_regs[coef_set];
1615 const u16 c12_base = c12_regs[coef_set];
1619 dev_err(dispc->dev, "%s: No coefficients given.\n", __func__);
1623 for (phase = 0; phase <= 8; ++phase) {
1624 u16 reg = c0_base + phase * 4;
1625 u16 c0 = coefs->c0[phase];
1627 dispc_vid_write(dispc, hw_plane, reg, c0);
1630 for (phase = 0; phase <= 15; ++phase) {
1631 u16 reg = c12_base + phase * 4;
1635 c1 = coefs->c1[phase];
1636 c2 = coefs->c2[phase];
1637 c12 = FLD_VAL(c1, 19, 10) | FLD_VAL(c2, 29, 20);
1639 dispc_vid_write(dispc, hw_plane, reg, c12);
1643 static bool dispc_fourcc_is_yuv(u32 fourcc)
1646 case DRM_FORMAT_YUYV:
1647 case DRM_FORMAT_UYVY:
1648 case DRM_FORMAT_NV12:
1655 struct dispc_scaling_params {
1657 u32 in_w, in_h, in_w_uv, in_h_uv;
1658 u32 fir_xinc, fir_yinc, fir_xinc_uv, fir_yinc_uv;
1659 bool scale_x, scale_y;
1660 const struct tidss_scale_coefs *xcoef, *ycoef, *xcoef_uv, *ycoef_uv;
1664 static int dispc_vid_calc_scaling(struct dispc_device *dispc,
1665 const struct drm_plane_state *state,
1666 struct dispc_scaling_params *sp,
1669 const struct dispc_features_scaling *f = &dispc->feat->scaling;
1670 u32 fourcc = state->fb->format->format;
1671 u32 in_width_max_5tap = f->in_width_max_5tap_rgb;
1672 u32 in_width_max_3tap = f->in_width_max_3tap_rgb;
1673 u32 downscale_limit;
1676 memset(sp, 0, sizeof(*sp));
1679 sp->in_w = state->src_w >> 16;
1680 sp->in_w_uv = sp->in_w;
1681 sp->in_h = state->src_h >> 16;
1682 sp->in_h_uv = sp->in_h;
1684 sp->scale_x = sp->in_w != state->crtc_w;
1685 sp->scale_y = sp->in_h != state->crtc_h;
1687 if (dispc_fourcc_is_yuv(fourcc)) {
1688 in_width_max_5tap = f->in_width_max_5tap_yuv;
1689 in_width_max_3tap = f->in_width_max_3tap_yuv;
1694 if (fourcc == DRM_FORMAT_NV12) {
1700 /* Skip the rest if no scaling is used */
1701 if ((!sp->scale_x && !sp->scale_y) || lite_plane)
1704 if (sp->in_w > in_width_max_5tap) {
1705 sp->five_taps = false;
1706 in_width_max = in_width_max_3tap;
1707 downscale_limit = f->downscale_limit_3tap;
1709 sp->five_taps = true;
1710 in_width_max = in_width_max_5tap;
1711 downscale_limit = f->downscale_limit_5tap;
1715 sp->fir_xinc = dispc_calc_fir_inc(sp->in_w, state->crtc_w);
1717 if (sp->fir_xinc < dispc_calc_fir_inc(1, f->upscale_limit)) {
1719 "%s: X-scaling factor %u/%u > %u\n",
1720 __func__, state->crtc_w, state->src_w >> 16,
1725 if (sp->fir_xinc >= dispc_calc_fir_inc(downscale_limit, 1)) {
1726 sp->xinc = DIV_ROUND_UP(DIV_ROUND_UP(sp->in_w,
1730 if (sp->xinc > f->xinc_max) {
1732 "%s: X-scaling factor %u/%u < 1/%u\n",
1733 __func__, state->crtc_w,
1735 downscale_limit * f->xinc_max);
1739 sp->in_w = (state->src_w >> 16) / sp->xinc;
1742 while (sp->in_w > in_width_max) {
1744 sp->in_w = (state->src_w >> 16) / sp->xinc;
1747 if (sp->xinc > f->xinc_max) {
1749 "%s: Too wide input buffer %u > %u\n", __func__,
1750 state->src_w >> 16, in_width_max * f->xinc_max);
1755 * We need even line length for YUV formats. Decimation
1756 * can lead to odd length, so we need to make it even
1759 if (dispc_fourcc_is_yuv(fourcc))
1762 sp->fir_xinc = dispc_calc_fir_inc(sp->in_w, state->crtc_w);
1766 sp->fir_yinc = dispc_calc_fir_inc(sp->in_h, state->crtc_h);
1768 if (sp->fir_yinc < dispc_calc_fir_inc(1, f->upscale_limit)) {
1770 "%s: Y-scaling factor %u/%u > %u\n",
1771 __func__, state->crtc_h, state->src_h >> 16,
1776 if (sp->fir_yinc >= dispc_calc_fir_inc(downscale_limit, 1)) {
1777 sp->yinc = DIV_ROUND_UP(DIV_ROUND_UP(sp->in_h,
1781 sp->in_h /= sp->yinc;
1782 sp->fir_yinc = dispc_calc_fir_inc(sp->in_h,
1788 "%s: %ux%u decim %ux%u -> %ux%u firinc %u.%03ux%u.%03u taps %u -> %ux%u\n",
1789 __func__, state->src_w >> 16, state->src_h >> 16,
1790 sp->xinc, sp->yinc, sp->in_w, sp->in_h,
1791 sp->fir_xinc / 0x200000u,
1792 ((sp->fir_xinc & 0x1FFFFFu) * 999u) / 0x1FFFFFu,
1793 sp->fir_yinc / 0x200000u,
1794 ((sp->fir_yinc & 0x1FFFFFu) * 999u) / 0x1FFFFFu,
1795 sp->five_taps ? 5 : 3,
1796 state->crtc_w, state->crtc_h);
1798 if (dispc_fourcc_is_yuv(fourcc)) {
1800 sp->in_w_uv /= sp->xinc;
1801 sp->fir_xinc_uv = dispc_calc_fir_inc(sp->in_w_uv,
1803 sp->xcoef_uv = tidss_get_scale_coefs(dispc->dev,
1808 sp->in_h_uv /= sp->yinc;
1809 sp->fir_yinc_uv = dispc_calc_fir_inc(sp->in_h_uv,
1811 sp->ycoef_uv = tidss_get_scale_coefs(dispc->dev,
1818 sp->xcoef = tidss_get_scale_coefs(dispc->dev, sp->fir_xinc,
1822 sp->ycoef = tidss_get_scale_coefs(dispc->dev, sp->fir_yinc,
1828 static void dispc_vid_set_scaling(struct dispc_device *dispc,
1830 struct dispc_scaling_params *sp,
1833 /* HORIZONTAL RESIZE ENABLE */
1834 VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES,
1837 /* VERTICAL RESIZE ENABLE */
1838 VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES,
1841 /* Skip the rest if no scaling is used */
1842 if (!sp->scale_x && !sp->scale_y)
1845 /* VERTICAL 5-TAPS */
1846 VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES,
1847 sp->five_taps, 21, 21);
1849 if (dispc_fourcc_is_yuv(fourcc)) {
1851 dispc_vid_write(dispc, hw_plane, DISPC_VID_FIRH2,
1853 dispc_vid_write_fir_coefs(dispc, hw_plane,
1854 DISPC_VID_FIR_COEF_HORIZ_UV,
1858 dispc_vid_write(dispc, hw_plane, DISPC_VID_FIRV2,
1860 dispc_vid_write_fir_coefs(dispc, hw_plane,
1861 DISPC_VID_FIR_COEF_VERT_UV,
1867 dispc_vid_write(dispc, hw_plane, DISPC_VID_FIRH, sp->fir_xinc);
1868 dispc_vid_write_fir_coefs(dispc, hw_plane,
1869 DISPC_VID_FIR_COEF_HORIZ,
1874 dispc_vid_write(dispc, hw_plane, DISPC_VID_FIRV, sp->fir_yinc);
1875 dispc_vid_write_fir_coefs(dispc, hw_plane,
1876 DISPC_VID_FIR_COEF_VERT, sp->ycoef);
1882 static const struct {
1885 } dispc_color_formats[] = {
1886 { DRM_FORMAT_ARGB4444, 0x0, },
1887 { DRM_FORMAT_ABGR4444, 0x1, },
1888 { DRM_FORMAT_RGBA4444, 0x2, },
1890 { DRM_FORMAT_RGB565, 0x3, },
1891 { DRM_FORMAT_BGR565, 0x4, },
1893 { DRM_FORMAT_ARGB1555, 0x5, },
1894 { DRM_FORMAT_ABGR1555, 0x6, },
1896 { DRM_FORMAT_ARGB8888, 0x7, },
1897 { DRM_FORMAT_ABGR8888, 0x8, },
1898 { DRM_FORMAT_RGBA8888, 0x9, },
1899 { DRM_FORMAT_BGRA8888, 0xa, },
1901 { DRM_FORMAT_RGB888, 0xb, },
1902 { DRM_FORMAT_BGR888, 0xc, },
1904 { DRM_FORMAT_ARGB2101010, 0xe, },
1905 { DRM_FORMAT_ABGR2101010, 0xf, },
1907 { DRM_FORMAT_XRGB4444, 0x20, },
1908 { DRM_FORMAT_XBGR4444, 0x21, },
1909 { DRM_FORMAT_RGBX4444, 0x22, },
1911 { DRM_FORMAT_XRGB1555, 0x25, },
1912 { DRM_FORMAT_XBGR1555, 0x26, },
1914 { DRM_FORMAT_XRGB8888, 0x27, },
1915 { DRM_FORMAT_XBGR8888, 0x28, },
1916 { DRM_FORMAT_RGBX8888, 0x29, },
1917 { DRM_FORMAT_BGRX8888, 0x2a, },
1919 { DRM_FORMAT_XRGB2101010, 0x2e, },
1920 { DRM_FORMAT_XBGR2101010, 0x2f, },
1922 { DRM_FORMAT_YUYV, 0x3e, },
1923 { DRM_FORMAT_UYVY, 0x3f, },
1925 { DRM_FORMAT_NV12, 0x3d, },
1928 static void dispc_plane_set_pixel_format(struct dispc_device *dispc,
1929 u32 hw_plane, u32 fourcc)
1933 for (i = 0; i < ARRAY_SIZE(dispc_color_formats); ++i) {
1934 if (dispc_color_formats[i].fourcc == fourcc) {
1935 VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES,
1936 dispc_color_formats[i].dss_code,
1945 const u32 *dispc_plane_formats(struct dispc_device *dispc, unsigned int *len)
1947 WARN_ON(!dispc->fourccs);
1949 *len = dispc->num_fourccs;
1951 return dispc->fourccs;
1954 static s32 pixinc(int pixels, u8 ps)
1958 else if (pixels > 1)
1959 return 1 + (pixels - 1) * ps;
1960 else if (pixels < 0)
1961 return 1 - (-pixels + 1) * ps;
1967 int dispc_plane_check(struct dispc_device *dispc, u32 hw_plane,
1968 const struct drm_plane_state *state,
1971 bool lite = dispc->feat->vid_lite[hw_plane];
1972 u32 fourcc = state->fb->format->format;
1973 bool need_scaling = state->src_w >> 16 != state->crtc_w ||
1974 state->src_h >> 16 != state->crtc_h;
1975 struct dispc_scaling_params scaling;
1978 if (dispc_fourcc_is_yuv(fourcc)) {
1979 if (!dispc_find_csc(state->color_encoding,
1980 state->color_range)) {
1982 "%s: Unsupported CSC (%u,%u) for HW plane %u\n",
1983 __func__, state->color_encoding,
1984 state->color_range, hw_plane);
1992 "%s: Lite plane %u can't scale %ux%u!=%ux%u\n",
1994 state->src_w >> 16, state->src_h >> 16,
1995 state->crtc_w, state->crtc_h);
1998 ret = dispc_vid_calc_scaling(dispc, state, &scaling, false);
2007 dma_addr_t dispc_plane_state_dma_addr(const struct drm_plane_state *state)
2009 struct drm_framebuffer *fb = state->fb;
2010 struct drm_gem_dma_object *gem;
2011 u32 x = state->src_x >> 16;
2012 u32 y = state->src_y >> 16;
2014 gem = drm_fb_dma_get_gem_obj(state->fb, 0);
2016 return gem->dma_addr + fb->offsets[0] + x * fb->format->cpp[0] +
2021 dma_addr_t dispc_plane_state_p_uv_addr(const struct drm_plane_state *state)
2023 struct drm_framebuffer *fb = state->fb;
2024 struct drm_gem_dma_object *gem;
2025 u32 x = state->src_x >> 16;
2026 u32 y = state->src_y >> 16;
2028 if (WARN_ON(state->fb->format->num_planes != 2))
2031 gem = drm_fb_dma_get_gem_obj(fb, 1);
2033 return gem->dma_addr + fb->offsets[1] +
2034 (x * fb->format->cpp[1] / fb->format->hsub) +
2035 (y * fb->pitches[1] / fb->format->vsub);
2038 void dispc_plane_setup(struct dispc_device *dispc, u32 hw_plane,
2039 const struct drm_plane_state *state,
2042 bool lite = dispc->feat->vid_lite[hw_plane];
2043 u32 fourcc = state->fb->format->format;
2044 u16 cpp = state->fb->format->cpp[0];
2045 u32 fb_width = state->fb->pitches[0] / cpp;
2046 dma_addr_t dma_addr = dispc_plane_state_dma_addr(state);
2047 struct dispc_scaling_params scale;
2049 dispc_vid_calc_scaling(dispc, state, &scale, lite);
2051 dispc_plane_set_pixel_format(dispc, hw_plane, fourcc);
2053 dispc_vid_write(dispc, hw_plane, DISPC_VID_BA_0, dma_addr & 0xffffffff);
2054 dispc_vid_write(dispc, hw_plane, DISPC_VID_BA_EXT_0, (u64)dma_addr >> 32);
2055 dispc_vid_write(dispc, hw_plane, DISPC_VID_BA_1, dma_addr & 0xffffffff);
2056 dispc_vid_write(dispc, hw_plane, DISPC_VID_BA_EXT_1, (u64)dma_addr >> 32);
2058 dispc_vid_write(dispc, hw_plane, DISPC_VID_PICTURE_SIZE,
2059 (scale.in_w - 1) | ((scale.in_h - 1) << 16));
2061 /* For YUV422 format we use the macropixel size for pixel inc */
2062 if (fourcc == DRM_FORMAT_YUYV || fourcc == DRM_FORMAT_UYVY)
2063 dispc_vid_write(dispc, hw_plane, DISPC_VID_PIXEL_INC,
2064 pixinc(scale.xinc, cpp * 2));
2066 dispc_vid_write(dispc, hw_plane, DISPC_VID_PIXEL_INC,
2067 pixinc(scale.xinc, cpp));
2069 dispc_vid_write(dispc, hw_plane, DISPC_VID_ROW_INC,
2070 pixinc(1 + (scale.yinc * fb_width -
2071 scale.xinc * scale.in_w),
2074 if (state->fb->format->num_planes == 2) {
2075 u16 cpp_uv = state->fb->format->cpp[1];
2076 u32 fb_width_uv = state->fb->pitches[1] / cpp_uv;
2077 dma_addr_t p_uv_addr = dispc_plane_state_p_uv_addr(state);
2079 dispc_vid_write(dispc, hw_plane,
2080 DISPC_VID_BA_UV_0, p_uv_addr & 0xffffffff);
2081 dispc_vid_write(dispc, hw_plane,
2082 DISPC_VID_BA_UV_EXT_0, (u64)p_uv_addr >> 32);
2083 dispc_vid_write(dispc, hw_plane,
2084 DISPC_VID_BA_UV_1, p_uv_addr & 0xffffffff);
2085 dispc_vid_write(dispc, hw_plane,
2086 DISPC_VID_BA_UV_EXT_1, (u64)p_uv_addr >> 32);
2088 dispc_vid_write(dispc, hw_plane, DISPC_VID_ROW_INC_UV,
2089 pixinc(1 + (scale.yinc * fb_width_uv -
2090 scale.xinc * scale.in_w_uv),
2095 dispc_vid_write(dispc, hw_plane, DISPC_VID_SIZE,
2096 (state->crtc_w - 1) |
2097 ((state->crtc_h - 1) << 16));
2099 dispc_vid_set_scaling(dispc, hw_plane, &scale, fourcc);
2102 /* enable YUV->RGB color conversion */
2103 if (dispc_fourcc_is_yuv(fourcc)) {
2104 dispc_vid_csc_setup(dispc, hw_plane, state);
2105 dispc_vid_csc_enable(dispc, hw_plane, true);
2107 dispc_vid_csc_enable(dispc, hw_plane, false);
2110 dispc_vid_write(dispc, hw_plane, DISPC_VID_GLOBAL_ALPHA,
2111 0xFF & (state->alpha >> 8));
2113 if (state->pixel_blend_mode == DRM_MODE_BLEND_PREMULTI)
2114 VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, 1,
2117 VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, 0,
2121 void dispc_plane_enable(struct dispc_device *dispc, u32 hw_plane, bool enable)
2123 VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, !!enable, 0, 0);
2126 static u32 dispc_vid_get_fifo_size(struct dispc_device *dispc, u32 hw_plane)
2128 return VID_REG_GET(dispc, hw_plane, DISPC_VID_BUF_SIZE_STATUS, 15, 0);
2131 static void dispc_vid_set_mflag_threshold(struct dispc_device *dispc,
2132 u32 hw_plane, u32 low, u32 high)
2134 dispc_vid_write(dispc, hw_plane, DISPC_VID_MFLAG_THRESHOLD,
2135 FLD_VAL(high, 31, 16) | FLD_VAL(low, 15, 0));
2138 static void dispc_vid_set_buf_threshold(struct dispc_device *dispc,
2139 u32 hw_plane, u32 low, u32 high)
2141 dispc_vid_write(dispc, hw_plane, DISPC_VID_BUF_THRESHOLD,
2142 FLD_VAL(high, 31, 16) | FLD_VAL(low, 15, 0));
2145 static void dispc_k2g_plane_init(struct dispc_device *dispc)
2147 unsigned int hw_plane;
2149 dev_dbg(dispc->dev, "%s()\n", __func__);
2151 /* MFLAG_CTRL = ENABLED */
2152 REG_FLD_MOD(dispc, DISPC_GLOBAL_MFLAG_ATTRIBUTE, 2, 1, 0);
2153 /* MFLAG_START = MFLAGNORMALSTARTMODE */
2154 REG_FLD_MOD(dispc, DISPC_GLOBAL_MFLAG_ATTRIBUTE, 0, 6, 6);
2156 for (hw_plane = 0; hw_plane < dispc->feat->num_planes; hw_plane++) {
2157 u32 size = dispc_vid_get_fifo_size(dispc, hw_plane);
2158 u32 thr_low, thr_high;
2159 u32 mflag_low, mflag_high;
2162 thr_high = size - 1;
2165 mflag_high = size * 2 / 3;
2166 mflag_low = size / 3;
2171 "%s: bufsize %u, buf_threshold %u/%u, mflag threshold %u/%u preload %u\n",
2172 dispc->feat->vid_name[hw_plane],
2175 mflag_high, mflag_low,
2178 dispc_vid_set_buf_threshold(dispc, hw_plane,
2180 dispc_vid_set_mflag_threshold(dispc, hw_plane,
2181 mflag_low, mflag_high);
2183 dispc_vid_write(dispc, hw_plane, DISPC_VID_PRELOAD, preload);
2186 * Prefetch up to fifo high-threshold value to minimize the
2187 * possibility of underflows. Note that this means the PRELOAD
2188 * register is ignored.
2190 VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, 1,
2195 static void dispc_k3_plane_init(struct dispc_device *dispc)
2197 unsigned int hw_plane;
2201 dev_dbg(dispc->dev, "%s()\n", __func__);
2203 REG_FLD_MOD(dispc, DSS_CBA_CFG, cba_lo_pri, 2, 0);
2204 REG_FLD_MOD(dispc, DSS_CBA_CFG, cba_hi_pri, 5, 3);
2206 /* MFLAG_CTRL = ENABLED */
2207 REG_FLD_MOD(dispc, DISPC_GLOBAL_MFLAG_ATTRIBUTE, 2, 1, 0);
2208 /* MFLAG_START = MFLAGNORMALSTARTMODE */
2209 REG_FLD_MOD(dispc, DISPC_GLOBAL_MFLAG_ATTRIBUTE, 0, 6, 6);
2211 for (hw_plane = 0; hw_plane < dispc->feat->num_planes; hw_plane++) {
2212 u32 size = dispc_vid_get_fifo_size(dispc, hw_plane);
2213 u32 thr_low, thr_high;
2214 u32 mflag_low, mflag_high;
2217 thr_high = size - 1;
2220 mflag_high = size * 2 / 3;
2221 mflag_low = size / 3;
2226 "%s: bufsize %u, buf_threshold %u/%u, mflag threshold %u/%u preload %u\n",
2227 dispc->feat->vid_name[hw_plane],
2230 mflag_high, mflag_low,
2233 dispc_vid_set_buf_threshold(dispc, hw_plane,
2235 dispc_vid_set_mflag_threshold(dispc, hw_plane,
2236 mflag_low, mflag_high);
2238 dispc_vid_write(dispc, hw_plane, DISPC_VID_PRELOAD, preload);
2240 /* Prefech up to PRELOAD value */
2241 VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, 0,
2246 static void dispc_plane_init(struct dispc_device *dispc)
2248 switch (dispc->feat->subrev) {
2250 dispc_k2g_plane_init(dispc);
2255 dispc_k3_plane_init(dispc);
2262 static void dispc_vp_init(struct dispc_device *dispc)
2266 dev_dbg(dispc->dev, "%s()\n", __func__);
2268 /* Enable the gamma Shadow bit-field for all VPs*/
2269 for (i = 0; i < dispc->feat->num_vps; i++)
2270 VP_REG_FLD_MOD(dispc, i, DISPC_VP_CONFIG, 1, 2, 2);
2273 static void dispc_initial_config(struct dispc_device *dispc)
2275 dispc_plane_init(dispc);
2276 dispc_vp_init(dispc);
2278 /* Note: Hardcoded DPI routing on J721E for now */
2279 if (dispc->feat->subrev == DISPC_J721E) {
2280 dispc_write(dispc, DISPC_CONNECTIONS,
2281 FLD_VAL(2, 3, 0) | /* VP1 to DPI0 */
2282 FLD_VAL(8, 7, 4) /* VP3 to DPI1 */
2287 static void dispc_k2g_vp_write_gamma_table(struct dispc_device *dispc,
2290 u32 *table = dispc->vp_data[hw_videoport].gamma_table;
2291 u32 hwlen = dispc->feat->vp_feat.color.gamma_size;
2294 dev_dbg(dispc->dev, "%s: hw_videoport %d\n", __func__, hw_videoport);
2296 if (WARN_ON(dispc->feat->vp_feat.color.gamma_type != TIDSS_GAMMA_8BIT))
2299 for (i = 0; i < hwlen; ++i) {
2304 dispc_vp_write(dispc, hw_videoport, DISPC_VP_K2G_GAMMA_TABLE,
2309 static void dispc_am65x_vp_write_gamma_table(struct dispc_device *dispc,
2312 u32 *table = dispc->vp_data[hw_videoport].gamma_table;
2313 u32 hwlen = dispc->feat->vp_feat.color.gamma_size;
2316 dev_dbg(dispc->dev, "%s: hw_videoport %d\n", __func__, hw_videoport);
2318 if (WARN_ON(dispc->feat->vp_feat.color.gamma_type != TIDSS_GAMMA_8BIT))
2321 for (i = 0; i < hwlen; ++i) {
2326 dispc_vp_write(dispc, hw_videoport, DISPC_VP_GAMMA_TABLE, v);
2330 static void dispc_j721e_vp_write_gamma_table(struct dispc_device *dispc,
2333 u32 *table = dispc->vp_data[hw_videoport].gamma_table;
2334 u32 hwlen = dispc->feat->vp_feat.color.gamma_size;
2337 dev_dbg(dispc->dev, "%s: hw_videoport %d\n", __func__, hw_videoport);
2339 if (WARN_ON(dispc->feat->vp_feat.color.gamma_type != TIDSS_GAMMA_10BIT))
2342 for (i = 0; i < hwlen; ++i) {
2348 dispc_vp_write(dispc, hw_videoport, DISPC_VP_GAMMA_TABLE, v);
2352 static void dispc_vp_write_gamma_table(struct dispc_device *dispc,
2355 switch (dispc->feat->subrev) {
2357 dispc_k2g_vp_write_gamma_table(dispc, hw_videoport);
2361 dispc_am65x_vp_write_gamma_table(dispc, hw_videoport);
2364 dispc_j721e_vp_write_gamma_table(dispc, hw_videoport);
2372 static const struct drm_color_lut dispc_vp_gamma_default_lut[] = {
2373 { .red = 0, .green = 0, .blue = 0, },
2374 { .red = U16_MAX, .green = U16_MAX, .blue = U16_MAX, },
2377 static void dispc_vp_set_gamma(struct dispc_device *dispc,
2379 const struct drm_color_lut *lut,
2380 unsigned int length)
2382 u32 *table = dispc->vp_data[hw_videoport].gamma_table;
2383 u32 hwlen = dispc->feat->vp_feat.color.gamma_size;
2387 dev_dbg(dispc->dev, "%s: hw_videoport %d, lut len %u, hw len %u\n",
2388 __func__, hw_videoport, length, hwlen);
2390 if (dispc->feat->vp_feat.color.gamma_type == TIDSS_GAMMA_10BIT)
2395 if (!lut || length < 2) {
2396 lut = dispc_vp_gamma_default_lut;
2397 length = ARRAY_SIZE(dispc_vp_gamma_default_lut);
2400 for (i = 0; i < length - 1; ++i) {
2401 unsigned int first = i * (hwlen - 1) / (length - 1);
2402 unsigned int last = (i + 1) * (hwlen - 1) / (length - 1);
2403 unsigned int w = last - first;
2410 for (j = 0; j <= w; j++) {
2411 r = (lut[i].red * (w - j) + lut[i + 1].red * j) / w;
2412 g = (lut[i].green * (w - j) + lut[i + 1].green * j) / w;
2413 b = (lut[i].blue * (w - j) + lut[i + 1].blue * j) / w;
2419 table[first + j] = (r << (hwbits * 2)) |
2424 dispc_vp_write_gamma_table(dispc, hw_videoport);
2427 static s16 dispc_S31_32_to_s2_8(s64 coef)
2429 u64 sign_bit = 1ULL << 63;
2430 u64 cbits = (u64)coef;
2433 if (cbits & sign_bit)
2434 ret = -clamp_val(((cbits & ~sign_bit) >> 24), 0, 0x200);
2436 ret = clamp_val(((cbits & ~sign_bit) >> 24), 0, 0x1FF);
2441 static void dispc_k2g_cpr_from_ctm(const struct drm_color_ctm *ctm,
2442 struct dispc_csc_coef *cpr)
2444 memset(cpr, 0, sizeof(*cpr));
2446 cpr->to_regval = dispc_csc_cpr_regval;
2447 cpr->m[CSC_RR] = dispc_S31_32_to_s2_8(ctm->matrix[0]);
2448 cpr->m[CSC_RG] = dispc_S31_32_to_s2_8(ctm->matrix[1]);
2449 cpr->m[CSC_RB] = dispc_S31_32_to_s2_8(ctm->matrix[2]);
2450 cpr->m[CSC_GR] = dispc_S31_32_to_s2_8(ctm->matrix[3]);
2451 cpr->m[CSC_GG] = dispc_S31_32_to_s2_8(ctm->matrix[4]);
2452 cpr->m[CSC_GB] = dispc_S31_32_to_s2_8(ctm->matrix[5]);
2453 cpr->m[CSC_BR] = dispc_S31_32_to_s2_8(ctm->matrix[6]);
2454 cpr->m[CSC_BG] = dispc_S31_32_to_s2_8(ctm->matrix[7]);
2455 cpr->m[CSC_BB] = dispc_S31_32_to_s2_8(ctm->matrix[8]);
2458 #define CVAL(xR, xG, xB) (FLD_VAL(xR, 9, 0) | FLD_VAL(xG, 20, 11) | \
2459 FLD_VAL(xB, 31, 22))
2461 static void dispc_k2g_vp_csc_cpr_regval(const struct dispc_csc_coef *csc,
2464 regval[0] = CVAL(csc->m[CSC_BB], csc->m[CSC_BG], csc->m[CSC_BR]);
2465 regval[1] = CVAL(csc->m[CSC_GB], csc->m[CSC_GG], csc->m[CSC_GR]);
2466 regval[2] = CVAL(csc->m[CSC_RB], csc->m[CSC_RG], csc->m[CSC_RR]);
2471 static void dispc_k2g_vp_write_csc(struct dispc_device *dispc, u32 hw_videoport,
2472 const struct dispc_csc_coef *csc)
2474 static const u16 dispc_vp_cpr_coef_reg[] = {
2475 DISPC_VP_CSC_COEF0, DISPC_VP_CSC_COEF1, DISPC_VP_CSC_COEF2,
2476 /* K2G CPR is packed to three registers. */
2478 u32 regval[DISPC_CSC_REGVAL_LEN];
2481 dispc_k2g_vp_csc_cpr_regval(csc, regval);
2483 for (i = 0; i < ARRAY_SIZE(dispc_vp_cpr_coef_reg); i++)
2484 dispc_vp_write(dispc, hw_videoport, dispc_vp_cpr_coef_reg[i],
2488 static void dispc_k2g_vp_set_ctm(struct dispc_device *dispc, u32 hw_videoport,
2489 struct drm_color_ctm *ctm)
2494 struct dispc_csc_coef cpr;
2496 dispc_k2g_cpr_from_ctm(ctm, &cpr);
2497 dispc_k2g_vp_write_csc(dispc, hw_videoport, &cpr);
2501 VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONFIG,
2505 static s16 dispc_S31_32_to_s3_8(s64 coef)
2507 u64 sign_bit = 1ULL << 63;
2508 u64 cbits = (u64)coef;
2511 if (cbits & sign_bit)
2512 ret = -clamp_val(((cbits & ~sign_bit) >> 24), 0, 0x400);
2514 ret = clamp_val(((cbits & ~sign_bit) >> 24), 0, 0x3FF);
2519 static void dispc_csc_from_ctm(const struct drm_color_ctm *ctm,
2520 struct dispc_csc_coef *cpr)
2522 memset(cpr, 0, sizeof(*cpr));
2524 cpr->to_regval = dispc_csc_cpr_regval;
2525 cpr->m[CSC_RR] = dispc_S31_32_to_s3_8(ctm->matrix[0]);
2526 cpr->m[CSC_RG] = dispc_S31_32_to_s3_8(ctm->matrix[1]);
2527 cpr->m[CSC_RB] = dispc_S31_32_to_s3_8(ctm->matrix[2]);
2528 cpr->m[CSC_GR] = dispc_S31_32_to_s3_8(ctm->matrix[3]);
2529 cpr->m[CSC_GG] = dispc_S31_32_to_s3_8(ctm->matrix[4]);
2530 cpr->m[CSC_GB] = dispc_S31_32_to_s3_8(ctm->matrix[5]);
2531 cpr->m[CSC_BR] = dispc_S31_32_to_s3_8(ctm->matrix[6]);
2532 cpr->m[CSC_BG] = dispc_S31_32_to_s3_8(ctm->matrix[7]);
2533 cpr->m[CSC_BB] = dispc_S31_32_to_s3_8(ctm->matrix[8]);
2536 static void dispc_k3_vp_write_csc(struct dispc_device *dispc, u32 hw_videoport,
2537 const struct dispc_csc_coef *csc)
2539 static const u16 dispc_vp_csc_coef_reg[DISPC_CSC_REGVAL_LEN] = {
2540 DISPC_VP_CSC_COEF0, DISPC_VP_CSC_COEF1, DISPC_VP_CSC_COEF2,
2541 DISPC_VP_CSC_COEF3, DISPC_VP_CSC_COEF4, DISPC_VP_CSC_COEF5,
2542 DISPC_VP_CSC_COEF6, DISPC_VP_CSC_COEF7,
2544 u32 regval[DISPC_CSC_REGVAL_LEN];
2547 csc->to_regval(csc, regval);
2549 for (i = 0; i < ARRAY_SIZE(regval); i++)
2550 dispc_vp_write(dispc, hw_videoport, dispc_vp_csc_coef_reg[i],
2554 static void dispc_k3_vp_set_ctm(struct dispc_device *dispc, u32 hw_videoport,
2555 struct drm_color_ctm *ctm)
2557 u32 colorconvenable = 0;
2560 struct dispc_csc_coef csc;
2562 dispc_csc_from_ctm(ctm, &csc);
2563 dispc_k3_vp_write_csc(dispc, hw_videoport, &csc);
2564 colorconvenable = 1;
2567 VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONFIG,
2568 colorconvenable, 24, 24);
2571 static void dispc_vp_set_color_mgmt(struct dispc_device *dispc,
2573 const struct drm_crtc_state *state,
2576 struct drm_color_lut *lut = NULL;
2577 struct drm_color_ctm *ctm = NULL;
2578 unsigned int length = 0;
2580 if (!(state->color_mgmt_changed || newmodeset))
2583 if (state->gamma_lut) {
2584 lut = (struct drm_color_lut *)state->gamma_lut->data;
2585 length = state->gamma_lut->length / sizeof(*lut);
2588 dispc_vp_set_gamma(dispc, hw_videoport, lut, length);
2591 ctm = (struct drm_color_ctm *)state->ctm->data;
2593 if (dispc->feat->subrev == DISPC_K2G)
2594 dispc_k2g_vp_set_ctm(dispc, hw_videoport, ctm);
2596 dispc_k3_vp_set_ctm(dispc, hw_videoport, ctm);
2599 void dispc_vp_setup(struct dispc_device *dispc, u32 hw_videoport,
2600 const struct drm_crtc_state *state, bool newmodeset)
2602 dispc_vp_set_default_color(dispc, hw_videoport, 0);
2603 dispc_vp_set_color_mgmt(dispc, hw_videoport, state, newmodeset);
2606 int dispc_runtime_suspend(struct dispc_device *dispc)
2608 dev_dbg(dispc->dev, "suspend\n");
2610 dispc->is_enabled = false;
2612 clk_disable_unprepare(dispc->fclk);
2617 int dispc_runtime_resume(struct dispc_device *dispc)
2619 dev_dbg(dispc->dev, "resume\n");
2621 clk_prepare_enable(dispc->fclk);
2623 if (REG_GET(dispc, DSS_SYSSTATUS, 0, 0) == 0)
2624 dev_warn(dispc->dev, "DSS FUNC RESET not done!\n");
2626 dev_dbg(dispc->dev, "OMAP DSS7 rev 0x%x\n",
2627 dispc_read(dispc, DSS_REVISION));
2629 dev_dbg(dispc->dev, "VP RESETDONE %d,%d,%d\n",
2630 REG_GET(dispc, DSS_SYSSTATUS, 1, 1),
2631 REG_GET(dispc, DSS_SYSSTATUS, 2, 2),
2632 REG_GET(dispc, DSS_SYSSTATUS, 3, 3));
2634 if (dispc->feat->subrev == DISPC_AM625 ||
2635 dispc->feat->subrev == DISPC_AM65X)
2636 dev_dbg(dispc->dev, "OLDI RESETDONE %d,%d,%d\n",
2637 REG_GET(dispc, DSS_SYSSTATUS, 5, 5),
2638 REG_GET(dispc, DSS_SYSSTATUS, 6, 6),
2639 REG_GET(dispc, DSS_SYSSTATUS, 7, 7));
2641 dev_dbg(dispc->dev, "DISPC IDLE %d\n",
2642 REG_GET(dispc, DSS_SYSSTATUS, 9, 9));
2644 dispc_initial_config(dispc);
2646 dispc->is_enabled = true;
2648 tidss_irq_resume(dispc->tidss);
2653 void dispc_remove(struct tidss_device *tidss)
2655 dev_dbg(tidss->dev, "%s\n", __func__);
2657 tidss->dispc = NULL;
2660 static int dispc_iomap_resource(struct platform_device *pdev, const char *name,
2661 void __iomem **base)
2665 b = devm_platform_ioremap_resource_byname(pdev, name);
2667 dev_err(&pdev->dev, "cannot ioremap resource '%s'\n", name);
2676 static int dispc_init_am65x_oldi_io_ctrl(struct device *dev,
2677 struct dispc_device *dispc)
2679 dispc->oldi_io_ctrl =
2680 syscon_regmap_lookup_by_phandle(dev->of_node,
2681 "ti,am65x-oldi-io-ctrl");
2682 if (PTR_ERR(dispc->oldi_io_ctrl) == -ENODEV) {
2683 dispc->oldi_io_ctrl = NULL;
2684 } else if (IS_ERR(dispc->oldi_io_ctrl)) {
2685 dev_err(dev, "%s: syscon_regmap_lookup_by_phandle failed %ld\n",
2686 __func__, PTR_ERR(dispc->oldi_io_ctrl));
2687 return PTR_ERR(dispc->oldi_io_ctrl);
2692 static void dispc_init_errata(struct dispc_device *dispc)
2694 static const struct soc_device_attribute am65x_sr10_soc_devices[] = {
2695 { .family = "AM65X", .revision = "SR1.0" },
2699 if (soc_device_match(am65x_sr10_soc_devices)) {
2700 dispc->errata.i2000 = true;
2701 dev_info(dispc->dev, "WA for erratum i2000: YUV formats disabled\n");
2705 static int dispc_softreset(struct dispc_device *dispc)
2710 /* K2G display controller does not support soft reset */
2711 if (dispc->feat->subrev == DISPC_K2G)
2715 REG_FLD_MOD(dispc, DSS_SYSCONFIG, 1, 1, 1);
2716 /* Wait for reset to complete */
2717 ret = readl_poll_timeout(dispc->base_common + DSS_SYSSTATUS,
2718 val, val & 1, 100, 5000);
2720 dev_err(dispc->dev, "failed to reset dispc\n");
2727 static int dispc_init_hw(struct dispc_device *dispc)
2729 struct device *dev = dispc->dev;
2732 ret = pm_runtime_set_active(dev);
2734 dev_err(dev, "Failed to set DSS PM to active\n");
2738 ret = clk_prepare_enable(dispc->fclk);
2740 dev_err(dev, "Failed to enable DSS fclk\n");
2741 goto err_runtime_suspend;
2744 ret = dispc_softreset(dispc);
2746 goto err_clk_disable;
2748 clk_disable_unprepare(dispc->fclk);
2749 ret = pm_runtime_set_suspended(dev);
2751 dev_err(dev, "Failed to set DSS PM to suspended\n");
2758 clk_disable_unprepare(dispc->fclk);
2760 err_runtime_suspend:
2761 ret = pm_runtime_set_suspended(dev);
2763 dev_err(dev, "Failed to set DSS PM to suspended\n");
2770 int dispc_init(struct tidss_device *tidss)
2772 struct device *dev = tidss->dev;
2773 struct platform_device *pdev = to_platform_device(dev);
2774 struct dispc_device *dispc;
2775 const struct dispc_features *feat;
2776 unsigned int i, num_fourccs;
2779 dev_dbg(dev, "%s\n", __func__);
2783 if (feat->subrev != DISPC_K2G) {
2784 r = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(48));
2786 dev_warn(dev, "cannot set DMA masks to 48-bit\n");
2789 dma_set_max_seg_size(dev, UINT_MAX);
2791 dispc = devm_kzalloc(dev, sizeof(*dispc), GFP_KERNEL);
2795 dispc->tidss = tidss;
2799 dispc_init_errata(dispc);
2801 dispc->fourccs = devm_kcalloc(dev, ARRAY_SIZE(dispc_color_formats),
2802 sizeof(*dispc->fourccs), GFP_KERNEL);
2803 if (!dispc->fourccs)
2807 for (i = 0; i < ARRAY_SIZE(dispc_color_formats); ++i) {
2808 if (dispc->errata.i2000 &&
2809 dispc_fourcc_is_yuv(dispc_color_formats[i].fourcc)) {
2812 dispc->fourccs[num_fourccs++] = dispc_color_formats[i].fourcc;
2815 dispc->num_fourccs = num_fourccs;
2817 dispc_common_regmap = dispc->feat->common_regs;
2819 r = dispc_iomap_resource(pdev, dispc->feat->common,
2820 &dispc->base_common);
2824 for (i = 0; i < dispc->feat->num_planes; i++) {
2825 r = dispc_iomap_resource(pdev, dispc->feat->vid_name[i],
2826 &dispc->base_vid[i]);
2831 for (i = 0; i < dispc->feat->num_vps; i++) {
2832 u32 gamma_size = dispc->feat->vp_feat.color.gamma_size;
2836 r = dispc_iomap_resource(pdev, dispc->feat->ovr_name[i],
2837 &dispc->base_ovr[i]);
2841 r = dispc_iomap_resource(pdev, dispc->feat->vp_name[i],
2842 &dispc->base_vp[i]);
2846 clk = devm_clk_get(dev, dispc->feat->vpclk_name[i]);
2848 dev_err(dev, "%s: Failed to get clk %s:%ld\n", __func__,
2849 dispc->feat->vpclk_name[i], PTR_ERR(clk));
2850 return PTR_ERR(clk);
2852 dispc->vp_clk[i] = clk;
2854 gamma_table = devm_kmalloc_array(dev, gamma_size,
2855 sizeof(*gamma_table),
2859 dispc->vp_data[i].gamma_table = gamma_table;
2862 if (feat->subrev == DISPC_AM65X) {
2863 r = dispc_init_am65x_oldi_io_ctrl(dev, dispc);
2868 dispc->fclk = devm_clk_get(dev, "fck");
2869 if (IS_ERR(dispc->fclk)) {
2870 dev_err(dev, "%s: Failed to get fclk: %ld\n",
2871 __func__, PTR_ERR(dispc->fclk));
2872 return PTR_ERR(dispc->fclk);
2874 dev_dbg(dev, "DSS fclk %lu Hz\n", clk_get_rate(dispc->fclk));
2876 of_property_read_u32(dispc->dev->of_node, "max-memory-bandwidth",
2877 &dispc->memory_bandwidth_limit);
2879 r = dispc_init_hw(dispc);
2883 tidss->dispc = dispc;