1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2012 Avionic Design GmbH
4 * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
8 #include <linux/debugfs.h>
9 #include <linux/delay.h>
10 #include <linux/iommu.h>
11 #include <linux/module.h>
12 #include <linux/of_device.h>
13 #include <linux/pm_runtime.h>
14 #include <linux/reset.h>
16 #include <soc/tegra/pmc.h>
18 #include <drm/drm_atomic.h>
19 #include <drm/drm_atomic_helper.h>
20 #include <drm/drm_debugfs.h>
21 #include <drm/drm_fourcc.h>
22 #include <drm/drm_plane_helper.h>
23 #include <drm/drm_vblank.h>
31 static void tegra_crtc_atomic_destroy_state(struct drm_crtc *crtc,
32 struct drm_crtc_state *state);
34 static void tegra_dc_stats_reset(struct tegra_dc_stats *stats)
42 /* Reads the active copy of a register. */
43 static u32 tegra_dc_readl_active(struct tegra_dc *dc, unsigned long offset)
47 tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS);
48 value = tegra_dc_readl(dc, offset);
49 tegra_dc_writel(dc, 0, DC_CMD_STATE_ACCESS);
54 static inline unsigned int tegra_plane_offset(struct tegra_plane *plane,
57 if (offset >= 0x500 && offset <= 0x638) {
58 offset = 0x000 + (offset - 0x500);
59 return plane->offset + offset;
62 if (offset >= 0x700 && offset <= 0x719) {
63 offset = 0x180 + (offset - 0x700);
64 return plane->offset + offset;
67 if (offset >= 0x800 && offset <= 0x839) {
68 offset = 0x1c0 + (offset - 0x800);
69 return plane->offset + offset;
72 dev_WARN(plane->dc->dev, "invalid offset: %x\n", offset);
74 return plane->offset + offset;
77 static inline u32 tegra_plane_readl(struct tegra_plane *plane,
80 return tegra_dc_readl(plane->dc, tegra_plane_offset(plane, offset));
83 static inline void tegra_plane_writel(struct tegra_plane *plane, u32 value,
86 tegra_dc_writel(plane->dc, value, tegra_plane_offset(plane, offset));
89 bool tegra_dc_has_output(struct tegra_dc *dc, struct device *dev)
91 struct device_node *np = dc->dev->of_node;
92 struct of_phandle_iterator it;
95 of_for_each_phandle(&it, err, np, "nvidia,outputs", NULL, 0)
96 if (it.node == dev->of_node)
103 * Double-buffered registers have two copies: ASSEMBLY and ACTIVE. When the
104 * *_ACT_REQ bits are set the ASSEMBLY copy is latched into the ACTIVE copy.
105 * Latching happens mmediately if the display controller is in STOP mode or
106 * on the next frame boundary otherwise.
108 * Triple-buffered registers have three copies: ASSEMBLY, ARM and ACTIVE. The
109 * ASSEMBLY copy is latched into the ARM copy immediately after *_UPDATE bits
110 * are written. When the *_ACT_REQ bits are written, the ARM copy is latched
111 * into the ACTIVE copy, either immediately if the display controller is in
112 * STOP mode, or at the next frame boundary otherwise.
114 void tegra_dc_commit(struct tegra_dc *dc)
116 tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
117 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
120 static inline u32 compute_dda_inc(unsigned int in, unsigned int out, bool v,
123 fixed20_12 outf = dfixed_init(out);
124 fixed20_12 inf = dfixed_init(in);
145 outf.full = max_t(u32, outf.full - dfixed_const(1), dfixed_const(1));
146 inf.full -= dfixed_const(1);
148 dda_inc = dfixed_div(inf, outf);
149 dda_inc = min_t(u32, dda_inc, dfixed_const(max));
154 static inline u32 compute_initial_dda(unsigned int in)
156 fixed20_12 inf = dfixed_init(in);
157 return dfixed_frac(inf);
160 static void tegra_plane_setup_blending_legacy(struct tegra_plane *plane)
162 u32 background[3] = {
163 BLEND_WEIGHT1(0) | BLEND_WEIGHT0(0) | BLEND_COLOR_KEY_NONE,
164 BLEND_WEIGHT1(0) | BLEND_WEIGHT0(0) | BLEND_COLOR_KEY_NONE,
165 BLEND_WEIGHT1(0) | BLEND_WEIGHT0(0) | BLEND_COLOR_KEY_NONE,
167 u32 foreground = BLEND_WEIGHT1(255) | BLEND_WEIGHT0(255) |
168 BLEND_COLOR_KEY_NONE;
169 u32 blendnokey = BLEND_WEIGHT1(255) | BLEND_WEIGHT0(255);
170 struct tegra_plane_state *state;
174 /* disable blending for non-overlapping case */
175 tegra_plane_writel(plane, blendnokey, DC_WIN_BLEND_NOKEY);
176 tegra_plane_writel(plane, foreground, DC_WIN_BLEND_1WIN);
178 state = to_tegra_plane_state(plane->base.state);
182 * Since custom fix-weight blending isn't utilized and weight
183 * of top window is set to max, we can enforce dependent
184 * blending which in this case results in transparent bottom
185 * window if top window is opaque and if top window enables
186 * alpha blending, then bottom window is getting alpha value
187 * of 1 minus the sum of alpha components of the overlapping
190 background[0] |= BLEND_CONTROL_DEPENDENT;
191 background[1] |= BLEND_CONTROL_DEPENDENT;
194 * The region where three windows overlap is the intersection
195 * of the two regions where two windows overlap. It contributes
196 * to the area if all of the windows on top of it have an alpha
199 switch (state->base.normalized_zpos) {
201 if (state->blending[0].alpha &&
202 state->blending[1].alpha)
203 background[2] |= BLEND_CONTROL_DEPENDENT;
207 background[2] |= BLEND_CONTROL_DEPENDENT;
212 * Enable alpha blending if pixel format has an alpha
215 foreground |= BLEND_CONTROL_ALPHA;
218 * If any of the windows on top of this window is opaque, it
219 * will completely conceal this window within that area. If
220 * top window has an alpha component, it is blended over the
223 for (i = 0; i < 2; i++) {
224 if (state->blending[i].alpha &&
225 state->blending[i].top)
226 background[i] |= BLEND_CONTROL_DEPENDENT;
229 switch (state->base.normalized_zpos) {
231 if (state->blending[0].alpha &&
232 state->blending[1].alpha)
233 background[2] |= BLEND_CONTROL_DEPENDENT;
238 * When both middle and topmost windows have an alpha,
239 * these windows a mixed together and then the result
240 * is blended over the bottom window.
242 if (state->blending[0].alpha &&
243 state->blending[0].top)
244 background[2] |= BLEND_CONTROL_ALPHA;
246 if (state->blending[1].alpha &&
247 state->blending[1].top)
248 background[2] |= BLEND_CONTROL_ALPHA;
253 switch (state->base.normalized_zpos) {
255 tegra_plane_writel(plane, background[0], DC_WIN_BLEND_2WIN_X);
256 tegra_plane_writel(plane, background[1], DC_WIN_BLEND_2WIN_Y);
257 tegra_plane_writel(plane, background[2], DC_WIN_BLEND_3WIN_XY);
262 * If window B / C is topmost, then X / Y registers are
263 * matching the order of blending[...] state indices,
264 * otherwise a swap is required.
266 if (!state->blending[0].top && state->blending[1].top) {
267 blending[0] = foreground;
268 blending[1] = background[1];
270 blending[0] = background[0];
271 blending[1] = foreground;
274 tegra_plane_writel(plane, blending[0], DC_WIN_BLEND_2WIN_X);
275 tegra_plane_writel(plane, blending[1], DC_WIN_BLEND_2WIN_Y);
276 tegra_plane_writel(plane, background[2], DC_WIN_BLEND_3WIN_XY);
280 tegra_plane_writel(plane, foreground, DC_WIN_BLEND_2WIN_X);
281 tegra_plane_writel(plane, foreground, DC_WIN_BLEND_2WIN_Y);
282 tegra_plane_writel(plane, foreground, DC_WIN_BLEND_3WIN_XY);
287 static void tegra_plane_setup_blending(struct tegra_plane *plane,
288 const struct tegra_dc_window *window)
292 value = BLEND_FACTOR_DST_ALPHA_ZERO | BLEND_FACTOR_SRC_ALPHA_K2 |
293 BLEND_FACTOR_DST_COLOR_NEG_K1_TIMES_SRC |
294 BLEND_FACTOR_SRC_COLOR_K1_TIMES_SRC;
295 tegra_plane_writel(plane, value, DC_WIN_BLEND_MATCH_SELECT);
297 value = BLEND_FACTOR_DST_ALPHA_ZERO | BLEND_FACTOR_SRC_ALPHA_K2 |
298 BLEND_FACTOR_DST_COLOR_NEG_K1_TIMES_SRC |
299 BLEND_FACTOR_SRC_COLOR_K1_TIMES_SRC;
300 tegra_plane_writel(plane, value, DC_WIN_BLEND_NOMATCH_SELECT);
302 value = K2(255) | K1(255) | WINDOW_LAYER_DEPTH(255 - window->zpos);
303 tegra_plane_writel(plane, value, DC_WIN_BLEND_LAYER_CONTROL);
307 tegra_plane_use_horizontal_filtering(struct tegra_plane *plane,
308 const struct tegra_dc_window *window)
310 struct tegra_dc *dc = plane->dc;
312 if (window->src.w == window->dst.w)
315 if (plane->index == 0 && dc->soc->has_win_a_without_filters)
322 tegra_plane_use_vertical_filtering(struct tegra_plane *plane,
323 const struct tegra_dc_window *window)
325 struct tegra_dc *dc = plane->dc;
327 if (window->src.h == window->dst.h)
330 if (plane->index == 0 && dc->soc->has_win_a_without_filters)
333 if (plane->index == 2 && dc->soc->has_win_c_without_vert_filter)
339 static void tegra_dc_setup_window(struct tegra_plane *plane,
340 const struct tegra_dc_window *window)
342 unsigned h_offset, v_offset, h_size, v_size, h_dda, v_dda, bpp;
343 struct tegra_dc *dc = plane->dc;
348 * For YUV planar modes, the number of bytes per pixel takes into
349 * account only the luma component and therefore is 1.
351 yuv = tegra_plane_format_is_yuv(window->format, &planar);
353 bpp = window->bits_per_pixel / 8;
355 bpp = planar ? 1 : 2;
357 tegra_plane_writel(plane, window->format, DC_WIN_COLOR_DEPTH);
358 tegra_plane_writel(plane, window->swap, DC_WIN_BYTE_SWAP);
360 value = V_POSITION(window->dst.y) | H_POSITION(window->dst.x);
361 tegra_plane_writel(plane, value, DC_WIN_POSITION);
363 value = V_SIZE(window->dst.h) | H_SIZE(window->dst.w);
364 tegra_plane_writel(plane, value, DC_WIN_SIZE);
366 h_offset = window->src.x * bpp;
367 v_offset = window->src.y;
368 h_size = window->src.w * bpp;
369 v_size = window->src.h;
371 if (window->reflect_x)
372 h_offset += (window->src.w - 1) * bpp;
374 if (window->reflect_y)
375 v_offset += window->src.h - 1;
377 value = V_PRESCALED_SIZE(v_size) | H_PRESCALED_SIZE(h_size);
378 tegra_plane_writel(plane, value, DC_WIN_PRESCALED_SIZE);
381 * For DDA computations the number of bytes per pixel for YUV planar
382 * modes needs to take into account all Y, U and V components.
387 h_dda = compute_dda_inc(window->src.w, window->dst.w, false, bpp);
388 v_dda = compute_dda_inc(window->src.h, window->dst.h, true, bpp);
390 value = V_DDA_INC(v_dda) | H_DDA_INC(h_dda);
391 tegra_plane_writel(plane, value, DC_WIN_DDA_INC);
393 h_dda = compute_initial_dda(window->src.x);
394 v_dda = compute_initial_dda(window->src.y);
396 tegra_plane_writel(plane, h_dda, DC_WIN_H_INITIAL_DDA);
397 tegra_plane_writel(plane, v_dda, DC_WIN_V_INITIAL_DDA);
399 tegra_plane_writel(plane, 0, DC_WIN_UV_BUF_STRIDE);
400 tegra_plane_writel(plane, 0, DC_WIN_BUF_STRIDE);
402 tegra_plane_writel(plane, window->base[0], DC_WINBUF_START_ADDR);
405 tegra_plane_writel(plane, window->base[1], DC_WINBUF_START_ADDR_U);
406 tegra_plane_writel(plane, window->base[2], DC_WINBUF_START_ADDR_V);
407 value = window->stride[1] << 16 | window->stride[0];
408 tegra_plane_writel(plane, value, DC_WIN_LINE_STRIDE);
410 tegra_plane_writel(plane, window->stride[0], DC_WIN_LINE_STRIDE);
413 tegra_plane_writel(plane, h_offset, DC_WINBUF_ADDR_H_OFFSET);
414 tegra_plane_writel(plane, v_offset, DC_WINBUF_ADDR_V_OFFSET);
416 if (dc->soc->supports_block_linear) {
417 unsigned long height = window->tiling.value;
419 switch (window->tiling.mode) {
420 case TEGRA_BO_TILING_MODE_PITCH:
421 value = DC_WINBUF_SURFACE_KIND_PITCH;
424 case TEGRA_BO_TILING_MODE_TILED:
425 value = DC_WINBUF_SURFACE_KIND_TILED;
428 case TEGRA_BO_TILING_MODE_BLOCK:
429 value = DC_WINBUF_SURFACE_KIND_BLOCK_HEIGHT(height) |
430 DC_WINBUF_SURFACE_KIND_BLOCK;
434 tegra_plane_writel(plane, value, DC_WINBUF_SURFACE_KIND);
436 switch (window->tiling.mode) {
437 case TEGRA_BO_TILING_MODE_PITCH:
438 value = DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV |
439 DC_WIN_BUFFER_ADDR_MODE_LINEAR;
442 case TEGRA_BO_TILING_MODE_TILED:
443 value = DC_WIN_BUFFER_ADDR_MODE_TILE_UV |
444 DC_WIN_BUFFER_ADDR_MODE_TILE;
447 case TEGRA_BO_TILING_MODE_BLOCK:
449 * No need to handle this here because ->atomic_check
450 * will already have filtered it out.
455 tegra_plane_writel(plane, value, DC_WIN_BUFFER_ADDR_MODE);
461 /* setup default colorspace conversion coefficients */
462 tegra_plane_writel(plane, 0x00f0, DC_WIN_CSC_YOF);
463 tegra_plane_writel(plane, 0x012a, DC_WIN_CSC_KYRGB);
464 tegra_plane_writel(plane, 0x0000, DC_WIN_CSC_KUR);
465 tegra_plane_writel(plane, 0x0198, DC_WIN_CSC_KVR);
466 tegra_plane_writel(plane, 0x039b, DC_WIN_CSC_KUG);
467 tegra_plane_writel(plane, 0x032f, DC_WIN_CSC_KVG);
468 tegra_plane_writel(plane, 0x0204, DC_WIN_CSC_KUB);
469 tegra_plane_writel(plane, 0x0000, DC_WIN_CSC_KVB);
472 } else if (window->bits_per_pixel < 24) {
473 value |= COLOR_EXPAND;
476 if (window->reflect_x)
477 value |= H_DIRECTION;
479 if (window->reflect_y)
480 value |= V_DIRECTION;
482 if (tegra_plane_use_horizontal_filtering(plane, window)) {
484 * Enable horizontal 6-tap filter and set filtering
485 * coefficients to the default values defined in TRM.
487 tegra_plane_writel(plane, 0x00008000, DC_WIN_H_FILTER_P(0));
488 tegra_plane_writel(plane, 0x3e087ce1, DC_WIN_H_FILTER_P(1));
489 tegra_plane_writel(plane, 0x3b117ac1, DC_WIN_H_FILTER_P(2));
490 tegra_plane_writel(plane, 0x591b73aa, DC_WIN_H_FILTER_P(3));
491 tegra_plane_writel(plane, 0x57256d9a, DC_WIN_H_FILTER_P(4));
492 tegra_plane_writel(plane, 0x552f668b, DC_WIN_H_FILTER_P(5));
493 tegra_plane_writel(plane, 0x73385e8b, DC_WIN_H_FILTER_P(6));
494 tegra_plane_writel(plane, 0x72435583, DC_WIN_H_FILTER_P(7));
495 tegra_plane_writel(plane, 0x714c4c8b, DC_WIN_H_FILTER_P(8));
496 tegra_plane_writel(plane, 0x70554393, DC_WIN_H_FILTER_P(9));
497 tegra_plane_writel(plane, 0x715e389b, DC_WIN_H_FILTER_P(10));
498 tegra_plane_writel(plane, 0x71662faa, DC_WIN_H_FILTER_P(11));
499 tegra_plane_writel(plane, 0x536d25ba, DC_WIN_H_FILTER_P(12));
500 tegra_plane_writel(plane, 0x55731bca, DC_WIN_H_FILTER_P(13));
501 tegra_plane_writel(plane, 0x387a11d9, DC_WIN_H_FILTER_P(14));
502 tegra_plane_writel(plane, 0x3c7c08f1, DC_WIN_H_FILTER_P(15));
507 if (tegra_plane_use_vertical_filtering(plane, window)) {
511 * Enable vertical 2-tap filter and set filtering
512 * coefficients to the default values defined in TRM.
514 for (i = 0, k = 128; i < 16; i++, k -= 8)
515 tegra_plane_writel(plane, k, DC_WIN_V_FILTER_P(i));
520 tegra_plane_writel(plane, value, DC_WIN_WIN_OPTIONS);
522 if (dc->soc->has_legacy_blending)
523 tegra_plane_setup_blending_legacy(plane);
525 tegra_plane_setup_blending(plane, window);
528 static const u32 tegra20_primary_formats[] = {
535 /* non-native formats */
542 static const u64 tegra20_modifiers[] = {
543 DRM_FORMAT_MOD_LINEAR,
544 DRM_FORMAT_MOD_NVIDIA_TEGRA_TILED,
545 DRM_FORMAT_MOD_INVALID
548 static const u32 tegra114_primary_formats[] = {
555 /* new on Tegra114 */
570 static const u32 tegra124_primary_formats[] = {
577 /* new on Tegra114 */
590 /* new on Tegra124 */
595 static const u64 tegra124_modifiers[] = {
596 DRM_FORMAT_MOD_LINEAR,
597 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(0),
598 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(1),
599 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(2),
600 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(3),
601 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(4),
602 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(5),
603 DRM_FORMAT_MOD_INVALID
606 static int tegra_plane_atomic_check(struct drm_plane *plane,
607 struct drm_atomic_state *state)
609 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state,
611 struct tegra_plane_state *plane_state = to_tegra_plane_state(new_plane_state);
612 unsigned int supported_rotation = DRM_MODE_ROTATE_0 |
615 unsigned int rotation = new_plane_state->rotation;
616 struct tegra_bo_tiling *tiling = &plane_state->tiling;
617 struct tegra_plane *tegra = to_tegra_plane(plane);
618 struct tegra_dc *dc = to_tegra_dc(new_plane_state->crtc);
621 /* no need for further checks if the plane is being disabled */
622 if (!new_plane_state->crtc)
625 err = tegra_plane_format(new_plane_state->fb->format->format,
626 &plane_state->format,
632 * Tegra20 and Tegra30 are special cases here because they support
633 * only variants of specific formats with an alpha component, but not
634 * the corresponding opaque formats. However, the opaque formats can
635 * be emulated by disabling alpha blending for the plane.
637 if (dc->soc->has_legacy_blending) {
638 err = tegra_plane_setup_legacy_state(tegra, plane_state);
643 err = tegra_fb_get_tiling(new_plane_state->fb, tiling);
647 if (tiling->mode == TEGRA_BO_TILING_MODE_BLOCK &&
648 !dc->soc->supports_block_linear) {
649 DRM_ERROR("hardware doesn't support block linear mode\n");
654 * Older userspace used custom BO flag in order to specify the Y
655 * reflection, while modern userspace uses the generic DRM rotation
656 * property in order to achieve the same result. The legacy BO flag
657 * duplicates the DRM rotation property when both are set.
659 if (tegra_fb_is_bottom_up(new_plane_state->fb))
660 rotation |= DRM_MODE_REFLECT_Y;
662 rotation = drm_rotation_simplify(rotation, supported_rotation);
664 if (rotation & DRM_MODE_REFLECT_X)
665 plane_state->reflect_x = true;
667 plane_state->reflect_x = false;
669 if (rotation & DRM_MODE_REFLECT_Y)
670 plane_state->reflect_y = true;
672 plane_state->reflect_y = false;
675 * Tegra doesn't support different strides for U and V planes so we
676 * error out if the user tries to display a framebuffer with such a
679 if (new_plane_state->fb->format->num_planes > 2) {
680 if (new_plane_state->fb->pitches[2] != new_plane_state->fb->pitches[1]) {
681 DRM_ERROR("unsupported UV-plane configuration\n");
686 err = tegra_plane_state_add(tegra, new_plane_state);
693 static void tegra_plane_atomic_disable(struct drm_plane *plane,
694 struct drm_atomic_state *state)
696 struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state,
698 struct tegra_plane *p = to_tegra_plane(plane);
701 /* rien ne va plus */
702 if (!old_state || !old_state->crtc)
705 value = tegra_plane_readl(p, DC_WIN_WIN_OPTIONS);
706 value &= ~WIN_ENABLE;
707 tegra_plane_writel(p, value, DC_WIN_WIN_OPTIONS);
710 static void tegra_plane_atomic_update(struct drm_plane *plane,
711 struct drm_atomic_state *state)
713 struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state,
715 struct tegra_plane_state *tegra_plane_state = to_tegra_plane_state(new_state);
716 struct drm_framebuffer *fb = new_state->fb;
717 struct tegra_plane *p = to_tegra_plane(plane);
718 struct tegra_dc_window window;
721 /* rien ne va plus */
722 if (!new_state->crtc || !new_state->fb)
725 if (!new_state->visible)
726 return tegra_plane_atomic_disable(plane, state);
728 memset(&window, 0, sizeof(window));
729 window.src.x = new_state->src.x1 >> 16;
730 window.src.y = new_state->src.y1 >> 16;
731 window.src.w = drm_rect_width(&new_state->src) >> 16;
732 window.src.h = drm_rect_height(&new_state->src) >> 16;
733 window.dst.x = new_state->dst.x1;
734 window.dst.y = new_state->dst.y1;
735 window.dst.w = drm_rect_width(&new_state->dst);
736 window.dst.h = drm_rect_height(&new_state->dst);
737 window.bits_per_pixel = fb->format->cpp[0] * 8;
738 window.reflect_x = tegra_plane_state->reflect_x;
739 window.reflect_y = tegra_plane_state->reflect_y;
741 /* copy from state */
742 window.zpos = new_state->normalized_zpos;
743 window.tiling = tegra_plane_state->tiling;
744 window.format = tegra_plane_state->format;
745 window.swap = tegra_plane_state->swap;
747 for (i = 0; i < fb->format->num_planes; i++) {
748 window.base[i] = tegra_plane_state->iova[i] + fb->offsets[i];
751 * Tegra uses a shared stride for UV planes. Framebuffers are
752 * already checked for this in the tegra_plane_atomic_check()
753 * function, so it's safe to ignore the V-plane pitch here.
756 window.stride[i] = fb->pitches[i];
759 tegra_dc_setup_window(p, &window);
762 static const struct drm_plane_helper_funcs tegra_plane_helper_funcs = {
763 .prepare_fb = tegra_plane_prepare_fb,
764 .cleanup_fb = tegra_plane_cleanup_fb,
765 .atomic_check = tegra_plane_atomic_check,
766 .atomic_disable = tegra_plane_atomic_disable,
767 .atomic_update = tegra_plane_atomic_update,
770 static unsigned long tegra_plane_get_possible_crtcs(struct drm_device *drm)
773 * Ideally this would use drm_crtc_mask(), but that would require the
774 * CRTC to already be in the mode_config's list of CRTCs. However, it
775 * will only be added to that list in the drm_crtc_init_with_planes()
776 * (in tegra_dc_init()), which in turn requires registration of these
777 * planes. So we have ourselves a nice little chicken and egg problem
780 * We work around this by manually creating the mask from the number
781 * of CRTCs that have been registered, and should therefore always be
782 * the same as drm_crtc_index() after registration.
784 return 1 << drm->mode_config.num_crtc;
787 static struct drm_plane *tegra_primary_plane_create(struct drm_device *drm,
790 unsigned long possible_crtcs = tegra_plane_get_possible_crtcs(drm);
791 enum drm_plane_type type = DRM_PLANE_TYPE_PRIMARY;
792 struct tegra_plane *plane;
793 unsigned int num_formats;
794 const u64 *modifiers;
798 plane = kzalloc(sizeof(*plane), GFP_KERNEL);
800 return ERR_PTR(-ENOMEM);
802 /* Always use window A as primary window */
803 plane->offset = 0xa00;
807 num_formats = dc->soc->num_primary_formats;
808 formats = dc->soc->primary_formats;
809 modifiers = dc->soc->modifiers;
811 err = drm_universal_plane_init(drm, &plane->base, possible_crtcs,
812 &tegra_plane_funcs, formats,
813 num_formats, modifiers, type, NULL);
819 drm_plane_helper_add(&plane->base, &tegra_plane_helper_funcs);
820 drm_plane_create_zpos_property(&plane->base, plane->index, 0, 255);
822 err = drm_plane_create_rotation_property(&plane->base,
825 DRM_MODE_ROTATE_180 |
829 dev_err(dc->dev, "failed to create rotation property: %d\n",
835 static const u32 tegra_cursor_plane_formats[] = {
839 static int tegra_cursor_atomic_check(struct drm_plane *plane,
840 struct drm_atomic_state *state)
842 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state,
844 struct tegra_plane *tegra = to_tegra_plane(plane);
847 /* no need for further checks if the plane is being disabled */
848 if (!new_plane_state->crtc)
851 /* scaling not supported for cursor */
852 if ((new_plane_state->src_w >> 16 != new_plane_state->crtc_w) ||
853 (new_plane_state->src_h >> 16 != new_plane_state->crtc_h))
856 /* only square cursors supported */
857 if (new_plane_state->src_w != new_plane_state->src_h)
860 if (new_plane_state->crtc_w != 32 && new_plane_state->crtc_w != 64 &&
861 new_plane_state->crtc_w != 128 && new_plane_state->crtc_w != 256)
864 err = tegra_plane_state_add(tegra, new_plane_state);
871 static void tegra_cursor_atomic_update(struct drm_plane *plane,
872 struct drm_atomic_state *state)
874 struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state,
876 struct tegra_plane_state *tegra_plane_state = to_tegra_plane_state(new_state);
877 struct tegra_dc *dc = to_tegra_dc(new_state->crtc);
878 u32 value = CURSOR_CLIP_DISPLAY;
880 /* rien ne va plus */
881 if (!new_state->crtc || !new_state->fb)
884 switch (new_state->crtc_w) {
886 value |= CURSOR_SIZE_32x32;
890 value |= CURSOR_SIZE_64x64;
894 value |= CURSOR_SIZE_128x128;
898 value |= CURSOR_SIZE_256x256;
902 WARN(1, "cursor size %ux%u not supported\n",
903 new_state->crtc_w, new_state->crtc_h);
907 value |= (tegra_plane_state->iova[0] >> 10) & 0x3fffff;
908 tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR);
910 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
911 value = (tegra_plane_state->iova[0] >> 32) & 0x3;
912 tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR_HI);
915 /* enable cursor and set blend mode */
916 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
917 value |= CURSOR_ENABLE;
918 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
920 value = tegra_dc_readl(dc, DC_DISP_BLEND_CURSOR_CONTROL);
921 value &= ~CURSOR_DST_BLEND_MASK;
922 value &= ~CURSOR_SRC_BLEND_MASK;
923 value |= CURSOR_MODE_NORMAL;
924 value |= CURSOR_DST_BLEND_NEG_K1_TIMES_SRC;
925 value |= CURSOR_SRC_BLEND_K1_TIMES_SRC;
926 value |= CURSOR_ALPHA;
927 tegra_dc_writel(dc, value, DC_DISP_BLEND_CURSOR_CONTROL);
929 /* position the cursor */
930 value = (new_state->crtc_y & 0x3fff) << 16 |
931 (new_state->crtc_x & 0x3fff);
932 tegra_dc_writel(dc, value, DC_DISP_CURSOR_POSITION);
935 static void tegra_cursor_atomic_disable(struct drm_plane *plane,
936 struct drm_atomic_state *state)
938 struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state,
943 /* rien ne va plus */
944 if (!old_state || !old_state->crtc)
947 dc = to_tegra_dc(old_state->crtc);
949 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
950 value &= ~CURSOR_ENABLE;
951 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
954 static const struct drm_plane_helper_funcs tegra_cursor_plane_helper_funcs = {
955 .prepare_fb = tegra_plane_prepare_fb,
956 .cleanup_fb = tegra_plane_cleanup_fb,
957 .atomic_check = tegra_cursor_atomic_check,
958 .atomic_update = tegra_cursor_atomic_update,
959 .atomic_disable = tegra_cursor_atomic_disable,
962 static struct drm_plane *tegra_dc_cursor_plane_create(struct drm_device *drm,
965 unsigned long possible_crtcs = tegra_plane_get_possible_crtcs(drm);
966 struct tegra_plane *plane;
967 unsigned int num_formats;
971 plane = kzalloc(sizeof(*plane), GFP_KERNEL);
973 return ERR_PTR(-ENOMEM);
976 * This index is kind of fake. The cursor isn't a regular plane, but
977 * its update and activation request bits in DC_CMD_STATE_CONTROL do
978 * use the same programming. Setting this fake index here allows the
979 * code in tegra_add_plane_state() to do the right thing without the
980 * need to special-casing the cursor plane.
985 num_formats = ARRAY_SIZE(tegra_cursor_plane_formats);
986 formats = tegra_cursor_plane_formats;
988 err = drm_universal_plane_init(drm, &plane->base, possible_crtcs,
989 &tegra_plane_funcs, formats,
991 DRM_PLANE_TYPE_CURSOR, NULL);
997 drm_plane_helper_add(&plane->base, &tegra_cursor_plane_helper_funcs);
998 drm_plane_create_zpos_immutable_property(&plane->base, 255);
1000 return &plane->base;
1003 static const u32 tegra20_overlay_formats[] = {
1004 DRM_FORMAT_ARGB4444,
1005 DRM_FORMAT_ARGB1555,
1007 DRM_FORMAT_RGBA5551,
1008 DRM_FORMAT_ABGR8888,
1009 DRM_FORMAT_ARGB8888,
1010 /* non-native formats */
1011 DRM_FORMAT_XRGB1555,
1012 DRM_FORMAT_RGBX5551,
1013 DRM_FORMAT_XBGR8888,
1014 DRM_FORMAT_XRGB8888,
1015 /* planar formats */
1022 static const u32 tegra114_overlay_formats[] = {
1023 DRM_FORMAT_ARGB4444,
1024 DRM_FORMAT_ARGB1555,
1026 DRM_FORMAT_RGBA5551,
1027 DRM_FORMAT_ABGR8888,
1028 DRM_FORMAT_ARGB8888,
1029 /* new on Tegra114 */
1030 DRM_FORMAT_ABGR4444,
1031 DRM_FORMAT_ABGR1555,
1032 DRM_FORMAT_BGRA5551,
1033 DRM_FORMAT_XRGB1555,
1034 DRM_FORMAT_RGBX5551,
1035 DRM_FORMAT_XBGR1555,
1036 DRM_FORMAT_BGRX5551,
1038 DRM_FORMAT_BGRA8888,
1039 DRM_FORMAT_RGBA8888,
1040 DRM_FORMAT_XRGB8888,
1041 DRM_FORMAT_XBGR8888,
1042 /* planar formats */
1049 static const u32 tegra124_overlay_formats[] = {
1050 DRM_FORMAT_ARGB4444,
1051 DRM_FORMAT_ARGB1555,
1053 DRM_FORMAT_RGBA5551,
1054 DRM_FORMAT_ABGR8888,
1055 DRM_FORMAT_ARGB8888,
1056 /* new on Tegra114 */
1057 DRM_FORMAT_ABGR4444,
1058 DRM_FORMAT_ABGR1555,
1059 DRM_FORMAT_BGRA5551,
1060 DRM_FORMAT_XRGB1555,
1061 DRM_FORMAT_RGBX5551,
1062 DRM_FORMAT_XBGR1555,
1063 DRM_FORMAT_BGRX5551,
1065 DRM_FORMAT_BGRA8888,
1066 DRM_FORMAT_RGBA8888,
1067 DRM_FORMAT_XRGB8888,
1068 DRM_FORMAT_XBGR8888,
1069 /* new on Tegra124 */
1070 DRM_FORMAT_RGBX8888,
1071 DRM_FORMAT_BGRX8888,
1072 /* planar formats */
1079 static struct drm_plane *tegra_dc_overlay_plane_create(struct drm_device *drm,
1080 struct tegra_dc *dc,
1084 unsigned long possible_crtcs = tegra_plane_get_possible_crtcs(drm);
1085 struct tegra_plane *plane;
1086 unsigned int num_formats;
1087 enum drm_plane_type type;
1091 plane = kzalloc(sizeof(*plane), GFP_KERNEL);
1093 return ERR_PTR(-ENOMEM);
1095 plane->offset = 0xa00 + 0x200 * index;
1096 plane->index = index;
1099 num_formats = dc->soc->num_overlay_formats;
1100 formats = dc->soc->overlay_formats;
1103 type = DRM_PLANE_TYPE_OVERLAY;
1105 type = DRM_PLANE_TYPE_CURSOR;
1107 err = drm_universal_plane_init(drm, &plane->base, possible_crtcs,
1108 &tegra_plane_funcs, formats,
1109 num_formats, NULL, type, NULL);
1112 return ERR_PTR(err);
1115 drm_plane_helper_add(&plane->base, &tegra_plane_helper_funcs);
1116 drm_plane_create_zpos_property(&plane->base, plane->index, 0, 255);
1118 err = drm_plane_create_rotation_property(&plane->base,
1121 DRM_MODE_ROTATE_180 |
1122 DRM_MODE_REFLECT_X |
1123 DRM_MODE_REFLECT_Y);
1125 dev_err(dc->dev, "failed to create rotation property: %d\n",
1128 return &plane->base;
1131 static struct drm_plane *tegra_dc_add_shared_planes(struct drm_device *drm,
1132 struct tegra_dc *dc)
1134 struct drm_plane *plane, *primary = NULL;
1137 for (i = 0; i < dc->soc->num_wgrps; i++) {
1138 const struct tegra_windowgroup_soc *wgrp = &dc->soc->wgrps[i];
1140 if (wgrp->dc == dc->pipe) {
1141 for (j = 0; j < wgrp->num_windows; j++) {
1142 unsigned int index = wgrp->windows[j];
1144 plane = tegra_shared_plane_create(drm, dc,
1151 * Choose the first shared plane owned by this
1152 * head as the primary plane.
1155 plane->type = DRM_PLANE_TYPE_PRIMARY;
1165 static struct drm_plane *tegra_dc_add_planes(struct drm_device *drm,
1166 struct tegra_dc *dc)
1168 struct drm_plane *planes[2], *primary;
1169 unsigned int planes_num;
1173 primary = tegra_primary_plane_create(drm, dc);
1174 if (IS_ERR(primary))
1177 if (dc->soc->supports_cursor)
1182 for (i = 0; i < planes_num; i++) {
1183 planes[i] = tegra_dc_overlay_plane_create(drm, dc, 1 + i,
1185 if (IS_ERR(planes[i])) {
1186 err = PTR_ERR(planes[i]);
1189 tegra_plane_funcs.destroy(planes[i]);
1191 tegra_plane_funcs.destroy(primary);
1192 return ERR_PTR(err);
1199 static void tegra_dc_destroy(struct drm_crtc *crtc)
1201 drm_crtc_cleanup(crtc);
1204 static void tegra_crtc_reset(struct drm_crtc *crtc)
1206 struct tegra_dc_state *state = kzalloc(sizeof(*state), GFP_KERNEL);
1209 tegra_crtc_atomic_destroy_state(crtc, crtc->state);
1211 __drm_atomic_helper_crtc_reset(crtc, &state->base);
1214 static struct drm_crtc_state *
1215 tegra_crtc_atomic_duplicate_state(struct drm_crtc *crtc)
1217 struct tegra_dc_state *state = to_dc_state(crtc->state);
1218 struct tegra_dc_state *copy;
1220 copy = kmalloc(sizeof(*copy), GFP_KERNEL);
1224 __drm_atomic_helper_crtc_duplicate_state(crtc, ©->base);
1225 copy->clk = state->clk;
1226 copy->pclk = state->pclk;
1227 copy->div = state->div;
1228 copy->planes = state->planes;
1233 static void tegra_crtc_atomic_destroy_state(struct drm_crtc *crtc,
1234 struct drm_crtc_state *state)
1236 __drm_atomic_helper_crtc_destroy_state(state);
1240 #define DEBUGFS_REG32(_name) { .name = #_name, .offset = _name }
1242 static const struct debugfs_reg32 tegra_dc_regs[] = {
1243 DEBUGFS_REG32(DC_CMD_GENERAL_INCR_SYNCPT),
1244 DEBUGFS_REG32(DC_CMD_GENERAL_INCR_SYNCPT_CNTRL),
1245 DEBUGFS_REG32(DC_CMD_GENERAL_INCR_SYNCPT_ERROR),
1246 DEBUGFS_REG32(DC_CMD_WIN_A_INCR_SYNCPT),
1247 DEBUGFS_REG32(DC_CMD_WIN_A_INCR_SYNCPT_CNTRL),
1248 DEBUGFS_REG32(DC_CMD_WIN_A_INCR_SYNCPT_ERROR),
1249 DEBUGFS_REG32(DC_CMD_WIN_B_INCR_SYNCPT),
1250 DEBUGFS_REG32(DC_CMD_WIN_B_INCR_SYNCPT_CNTRL),
1251 DEBUGFS_REG32(DC_CMD_WIN_B_INCR_SYNCPT_ERROR),
1252 DEBUGFS_REG32(DC_CMD_WIN_C_INCR_SYNCPT),
1253 DEBUGFS_REG32(DC_CMD_WIN_C_INCR_SYNCPT_CNTRL),
1254 DEBUGFS_REG32(DC_CMD_WIN_C_INCR_SYNCPT_ERROR),
1255 DEBUGFS_REG32(DC_CMD_CONT_SYNCPT_VSYNC),
1256 DEBUGFS_REG32(DC_CMD_DISPLAY_COMMAND_OPTION0),
1257 DEBUGFS_REG32(DC_CMD_DISPLAY_COMMAND),
1258 DEBUGFS_REG32(DC_CMD_SIGNAL_RAISE),
1259 DEBUGFS_REG32(DC_CMD_DISPLAY_POWER_CONTROL),
1260 DEBUGFS_REG32(DC_CMD_INT_STATUS),
1261 DEBUGFS_REG32(DC_CMD_INT_MASK),
1262 DEBUGFS_REG32(DC_CMD_INT_ENABLE),
1263 DEBUGFS_REG32(DC_CMD_INT_TYPE),
1264 DEBUGFS_REG32(DC_CMD_INT_POLARITY),
1265 DEBUGFS_REG32(DC_CMD_SIGNAL_RAISE1),
1266 DEBUGFS_REG32(DC_CMD_SIGNAL_RAISE2),
1267 DEBUGFS_REG32(DC_CMD_SIGNAL_RAISE3),
1268 DEBUGFS_REG32(DC_CMD_STATE_ACCESS),
1269 DEBUGFS_REG32(DC_CMD_STATE_CONTROL),
1270 DEBUGFS_REG32(DC_CMD_DISPLAY_WINDOW_HEADER),
1271 DEBUGFS_REG32(DC_CMD_REG_ACT_CONTROL),
1272 DEBUGFS_REG32(DC_COM_CRC_CONTROL),
1273 DEBUGFS_REG32(DC_COM_CRC_CHECKSUM),
1274 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_ENABLE(0)),
1275 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_ENABLE(1)),
1276 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_ENABLE(2)),
1277 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_ENABLE(3)),
1278 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_POLARITY(0)),
1279 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_POLARITY(1)),
1280 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_POLARITY(2)),
1281 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_POLARITY(3)),
1282 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_DATA(0)),
1283 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_DATA(1)),
1284 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_DATA(2)),
1285 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_DATA(3)),
1286 DEBUGFS_REG32(DC_COM_PIN_INPUT_ENABLE(0)),
1287 DEBUGFS_REG32(DC_COM_PIN_INPUT_ENABLE(1)),
1288 DEBUGFS_REG32(DC_COM_PIN_INPUT_ENABLE(2)),
1289 DEBUGFS_REG32(DC_COM_PIN_INPUT_ENABLE(3)),
1290 DEBUGFS_REG32(DC_COM_PIN_INPUT_DATA(0)),
1291 DEBUGFS_REG32(DC_COM_PIN_INPUT_DATA(1)),
1292 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(0)),
1293 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(1)),
1294 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(2)),
1295 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(3)),
1296 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(4)),
1297 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(5)),
1298 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(6)),
1299 DEBUGFS_REG32(DC_COM_PIN_MISC_CONTROL),
1300 DEBUGFS_REG32(DC_COM_PIN_PM0_CONTROL),
1301 DEBUGFS_REG32(DC_COM_PIN_PM0_DUTY_CYCLE),
1302 DEBUGFS_REG32(DC_COM_PIN_PM1_CONTROL),
1303 DEBUGFS_REG32(DC_COM_PIN_PM1_DUTY_CYCLE),
1304 DEBUGFS_REG32(DC_COM_SPI_CONTROL),
1305 DEBUGFS_REG32(DC_COM_SPI_START_BYTE),
1306 DEBUGFS_REG32(DC_COM_HSPI_WRITE_DATA_AB),
1307 DEBUGFS_REG32(DC_COM_HSPI_WRITE_DATA_CD),
1308 DEBUGFS_REG32(DC_COM_HSPI_CS_DC),
1309 DEBUGFS_REG32(DC_COM_SCRATCH_REGISTER_A),
1310 DEBUGFS_REG32(DC_COM_SCRATCH_REGISTER_B),
1311 DEBUGFS_REG32(DC_COM_GPIO_CTRL),
1312 DEBUGFS_REG32(DC_COM_GPIO_DEBOUNCE_COUNTER),
1313 DEBUGFS_REG32(DC_COM_CRC_CHECKSUM_LATCHED),
1314 DEBUGFS_REG32(DC_DISP_DISP_SIGNAL_OPTIONS0),
1315 DEBUGFS_REG32(DC_DISP_DISP_SIGNAL_OPTIONS1),
1316 DEBUGFS_REG32(DC_DISP_DISP_WIN_OPTIONS),
1317 DEBUGFS_REG32(DC_DISP_DISP_MEM_HIGH_PRIORITY),
1318 DEBUGFS_REG32(DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER),
1319 DEBUGFS_REG32(DC_DISP_DISP_TIMING_OPTIONS),
1320 DEBUGFS_REG32(DC_DISP_REF_TO_SYNC),
1321 DEBUGFS_REG32(DC_DISP_SYNC_WIDTH),
1322 DEBUGFS_REG32(DC_DISP_BACK_PORCH),
1323 DEBUGFS_REG32(DC_DISP_ACTIVE),
1324 DEBUGFS_REG32(DC_DISP_FRONT_PORCH),
1325 DEBUGFS_REG32(DC_DISP_H_PULSE0_CONTROL),
1326 DEBUGFS_REG32(DC_DISP_H_PULSE0_POSITION_A),
1327 DEBUGFS_REG32(DC_DISP_H_PULSE0_POSITION_B),
1328 DEBUGFS_REG32(DC_DISP_H_PULSE0_POSITION_C),
1329 DEBUGFS_REG32(DC_DISP_H_PULSE0_POSITION_D),
1330 DEBUGFS_REG32(DC_DISP_H_PULSE1_CONTROL),
1331 DEBUGFS_REG32(DC_DISP_H_PULSE1_POSITION_A),
1332 DEBUGFS_REG32(DC_DISP_H_PULSE1_POSITION_B),
1333 DEBUGFS_REG32(DC_DISP_H_PULSE1_POSITION_C),
1334 DEBUGFS_REG32(DC_DISP_H_PULSE1_POSITION_D),
1335 DEBUGFS_REG32(DC_DISP_H_PULSE2_CONTROL),
1336 DEBUGFS_REG32(DC_DISP_H_PULSE2_POSITION_A),
1337 DEBUGFS_REG32(DC_DISP_H_PULSE2_POSITION_B),
1338 DEBUGFS_REG32(DC_DISP_H_PULSE2_POSITION_C),
1339 DEBUGFS_REG32(DC_DISP_H_PULSE2_POSITION_D),
1340 DEBUGFS_REG32(DC_DISP_V_PULSE0_CONTROL),
1341 DEBUGFS_REG32(DC_DISP_V_PULSE0_POSITION_A),
1342 DEBUGFS_REG32(DC_DISP_V_PULSE0_POSITION_B),
1343 DEBUGFS_REG32(DC_DISP_V_PULSE0_POSITION_C),
1344 DEBUGFS_REG32(DC_DISP_V_PULSE1_CONTROL),
1345 DEBUGFS_REG32(DC_DISP_V_PULSE1_POSITION_A),
1346 DEBUGFS_REG32(DC_DISP_V_PULSE1_POSITION_B),
1347 DEBUGFS_REG32(DC_DISP_V_PULSE1_POSITION_C),
1348 DEBUGFS_REG32(DC_DISP_V_PULSE2_CONTROL),
1349 DEBUGFS_REG32(DC_DISP_V_PULSE2_POSITION_A),
1350 DEBUGFS_REG32(DC_DISP_V_PULSE3_CONTROL),
1351 DEBUGFS_REG32(DC_DISP_V_PULSE3_POSITION_A),
1352 DEBUGFS_REG32(DC_DISP_M0_CONTROL),
1353 DEBUGFS_REG32(DC_DISP_M1_CONTROL),
1354 DEBUGFS_REG32(DC_DISP_DI_CONTROL),
1355 DEBUGFS_REG32(DC_DISP_PP_CONTROL),
1356 DEBUGFS_REG32(DC_DISP_PP_SELECT_A),
1357 DEBUGFS_REG32(DC_DISP_PP_SELECT_B),
1358 DEBUGFS_REG32(DC_DISP_PP_SELECT_C),
1359 DEBUGFS_REG32(DC_DISP_PP_SELECT_D),
1360 DEBUGFS_REG32(DC_DISP_DISP_CLOCK_CONTROL),
1361 DEBUGFS_REG32(DC_DISP_DISP_INTERFACE_CONTROL),
1362 DEBUGFS_REG32(DC_DISP_DISP_COLOR_CONTROL),
1363 DEBUGFS_REG32(DC_DISP_SHIFT_CLOCK_OPTIONS),
1364 DEBUGFS_REG32(DC_DISP_DATA_ENABLE_OPTIONS),
1365 DEBUGFS_REG32(DC_DISP_SERIAL_INTERFACE_OPTIONS),
1366 DEBUGFS_REG32(DC_DISP_LCD_SPI_OPTIONS),
1367 DEBUGFS_REG32(DC_DISP_BORDER_COLOR),
1368 DEBUGFS_REG32(DC_DISP_COLOR_KEY0_LOWER),
1369 DEBUGFS_REG32(DC_DISP_COLOR_KEY0_UPPER),
1370 DEBUGFS_REG32(DC_DISP_COLOR_KEY1_LOWER),
1371 DEBUGFS_REG32(DC_DISP_COLOR_KEY1_UPPER),
1372 DEBUGFS_REG32(DC_DISP_CURSOR_FOREGROUND),
1373 DEBUGFS_REG32(DC_DISP_CURSOR_BACKGROUND),
1374 DEBUGFS_REG32(DC_DISP_CURSOR_START_ADDR),
1375 DEBUGFS_REG32(DC_DISP_CURSOR_START_ADDR_NS),
1376 DEBUGFS_REG32(DC_DISP_CURSOR_POSITION),
1377 DEBUGFS_REG32(DC_DISP_CURSOR_POSITION_NS),
1378 DEBUGFS_REG32(DC_DISP_INIT_SEQ_CONTROL),
1379 DEBUGFS_REG32(DC_DISP_SPI_INIT_SEQ_DATA_A),
1380 DEBUGFS_REG32(DC_DISP_SPI_INIT_SEQ_DATA_B),
1381 DEBUGFS_REG32(DC_DISP_SPI_INIT_SEQ_DATA_C),
1382 DEBUGFS_REG32(DC_DISP_SPI_INIT_SEQ_DATA_D),
1383 DEBUGFS_REG32(DC_DISP_DC_MCCIF_FIFOCTRL),
1384 DEBUGFS_REG32(DC_DISP_MCCIF_DISPLAY0A_HYST),
1385 DEBUGFS_REG32(DC_DISP_MCCIF_DISPLAY0B_HYST),
1386 DEBUGFS_REG32(DC_DISP_MCCIF_DISPLAY1A_HYST),
1387 DEBUGFS_REG32(DC_DISP_MCCIF_DISPLAY1B_HYST),
1388 DEBUGFS_REG32(DC_DISP_DAC_CRT_CTRL),
1389 DEBUGFS_REG32(DC_DISP_DISP_MISC_CONTROL),
1390 DEBUGFS_REG32(DC_DISP_SD_CONTROL),
1391 DEBUGFS_REG32(DC_DISP_SD_CSC_COEFF),
1392 DEBUGFS_REG32(DC_DISP_SD_LUT(0)),
1393 DEBUGFS_REG32(DC_DISP_SD_LUT(1)),
1394 DEBUGFS_REG32(DC_DISP_SD_LUT(2)),
1395 DEBUGFS_REG32(DC_DISP_SD_LUT(3)),
1396 DEBUGFS_REG32(DC_DISP_SD_LUT(4)),
1397 DEBUGFS_REG32(DC_DISP_SD_LUT(5)),
1398 DEBUGFS_REG32(DC_DISP_SD_LUT(6)),
1399 DEBUGFS_REG32(DC_DISP_SD_LUT(7)),
1400 DEBUGFS_REG32(DC_DISP_SD_LUT(8)),
1401 DEBUGFS_REG32(DC_DISP_SD_FLICKER_CONTROL),
1402 DEBUGFS_REG32(DC_DISP_DC_PIXEL_COUNT),
1403 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(0)),
1404 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(1)),
1405 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(2)),
1406 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(3)),
1407 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(4)),
1408 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(5)),
1409 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(6)),
1410 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(7)),
1411 DEBUGFS_REG32(DC_DISP_SD_BL_TF(0)),
1412 DEBUGFS_REG32(DC_DISP_SD_BL_TF(1)),
1413 DEBUGFS_REG32(DC_DISP_SD_BL_TF(2)),
1414 DEBUGFS_REG32(DC_DISP_SD_BL_TF(3)),
1415 DEBUGFS_REG32(DC_DISP_SD_BL_CONTROL),
1416 DEBUGFS_REG32(DC_DISP_SD_HW_K_VALUES),
1417 DEBUGFS_REG32(DC_DISP_SD_MAN_K_VALUES),
1418 DEBUGFS_REG32(DC_DISP_CURSOR_START_ADDR_HI),
1419 DEBUGFS_REG32(DC_DISP_BLEND_CURSOR_CONTROL),
1420 DEBUGFS_REG32(DC_WIN_WIN_OPTIONS),
1421 DEBUGFS_REG32(DC_WIN_BYTE_SWAP),
1422 DEBUGFS_REG32(DC_WIN_BUFFER_CONTROL),
1423 DEBUGFS_REG32(DC_WIN_COLOR_DEPTH),
1424 DEBUGFS_REG32(DC_WIN_POSITION),
1425 DEBUGFS_REG32(DC_WIN_SIZE),
1426 DEBUGFS_REG32(DC_WIN_PRESCALED_SIZE),
1427 DEBUGFS_REG32(DC_WIN_H_INITIAL_DDA),
1428 DEBUGFS_REG32(DC_WIN_V_INITIAL_DDA),
1429 DEBUGFS_REG32(DC_WIN_DDA_INC),
1430 DEBUGFS_REG32(DC_WIN_LINE_STRIDE),
1431 DEBUGFS_REG32(DC_WIN_BUF_STRIDE),
1432 DEBUGFS_REG32(DC_WIN_UV_BUF_STRIDE),
1433 DEBUGFS_REG32(DC_WIN_BUFFER_ADDR_MODE),
1434 DEBUGFS_REG32(DC_WIN_DV_CONTROL),
1435 DEBUGFS_REG32(DC_WIN_BLEND_NOKEY),
1436 DEBUGFS_REG32(DC_WIN_BLEND_1WIN),
1437 DEBUGFS_REG32(DC_WIN_BLEND_2WIN_X),
1438 DEBUGFS_REG32(DC_WIN_BLEND_2WIN_Y),
1439 DEBUGFS_REG32(DC_WIN_BLEND_3WIN_XY),
1440 DEBUGFS_REG32(DC_WIN_HP_FETCH_CONTROL),
1441 DEBUGFS_REG32(DC_WINBUF_START_ADDR),
1442 DEBUGFS_REG32(DC_WINBUF_START_ADDR_NS),
1443 DEBUGFS_REG32(DC_WINBUF_START_ADDR_U),
1444 DEBUGFS_REG32(DC_WINBUF_START_ADDR_U_NS),
1445 DEBUGFS_REG32(DC_WINBUF_START_ADDR_V),
1446 DEBUGFS_REG32(DC_WINBUF_START_ADDR_V_NS),
1447 DEBUGFS_REG32(DC_WINBUF_ADDR_H_OFFSET),
1448 DEBUGFS_REG32(DC_WINBUF_ADDR_H_OFFSET_NS),
1449 DEBUGFS_REG32(DC_WINBUF_ADDR_V_OFFSET),
1450 DEBUGFS_REG32(DC_WINBUF_ADDR_V_OFFSET_NS),
1451 DEBUGFS_REG32(DC_WINBUF_UFLOW_STATUS),
1452 DEBUGFS_REG32(DC_WINBUF_AD_UFLOW_STATUS),
1453 DEBUGFS_REG32(DC_WINBUF_BD_UFLOW_STATUS),
1454 DEBUGFS_REG32(DC_WINBUF_CD_UFLOW_STATUS),
1457 static int tegra_dc_show_regs(struct seq_file *s, void *data)
1459 struct drm_info_node *node = s->private;
1460 struct tegra_dc *dc = node->info_ent->data;
1464 drm_modeset_lock(&dc->base.mutex, NULL);
1466 if (!dc->base.state->active) {
1471 for (i = 0; i < ARRAY_SIZE(tegra_dc_regs); i++) {
1472 unsigned int offset = tegra_dc_regs[i].offset;
1474 seq_printf(s, "%-40s %#05x %08x\n", tegra_dc_regs[i].name,
1475 offset, tegra_dc_readl(dc, offset));
1479 drm_modeset_unlock(&dc->base.mutex);
1483 static int tegra_dc_show_crc(struct seq_file *s, void *data)
1485 struct drm_info_node *node = s->private;
1486 struct tegra_dc *dc = node->info_ent->data;
1490 drm_modeset_lock(&dc->base.mutex, NULL);
1492 if (!dc->base.state->active) {
1497 value = DC_COM_CRC_CONTROL_ACTIVE_DATA | DC_COM_CRC_CONTROL_ENABLE;
1498 tegra_dc_writel(dc, value, DC_COM_CRC_CONTROL);
1499 tegra_dc_commit(dc);
1501 drm_crtc_wait_one_vblank(&dc->base);
1502 drm_crtc_wait_one_vblank(&dc->base);
1504 value = tegra_dc_readl(dc, DC_COM_CRC_CHECKSUM);
1505 seq_printf(s, "%08x\n", value);
1507 tegra_dc_writel(dc, 0, DC_COM_CRC_CONTROL);
1510 drm_modeset_unlock(&dc->base.mutex);
1514 static int tegra_dc_show_stats(struct seq_file *s, void *data)
1516 struct drm_info_node *node = s->private;
1517 struct tegra_dc *dc = node->info_ent->data;
1519 seq_printf(s, "frames: %lu\n", dc->stats.frames);
1520 seq_printf(s, "vblank: %lu\n", dc->stats.vblank);
1521 seq_printf(s, "underflow: %lu\n", dc->stats.underflow);
1522 seq_printf(s, "overflow: %lu\n", dc->stats.overflow);
1527 static struct drm_info_list debugfs_files[] = {
1528 { "regs", tegra_dc_show_regs, 0, NULL },
1529 { "crc", tegra_dc_show_crc, 0, NULL },
1530 { "stats", tegra_dc_show_stats, 0, NULL },
1533 static int tegra_dc_late_register(struct drm_crtc *crtc)
1535 unsigned int i, count = ARRAY_SIZE(debugfs_files);
1536 struct drm_minor *minor = crtc->dev->primary;
1537 struct dentry *root;
1538 struct tegra_dc *dc = to_tegra_dc(crtc);
1540 #ifdef CONFIG_DEBUG_FS
1541 root = crtc->debugfs_entry;
1546 dc->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
1548 if (!dc->debugfs_files)
1551 for (i = 0; i < count; i++)
1552 dc->debugfs_files[i].data = dc;
1554 drm_debugfs_create_files(dc->debugfs_files, count, root, minor);
1559 static void tegra_dc_early_unregister(struct drm_crtc *crtc)
1561 unsigned int count = ARRAY_SIZE(debugfs_files);
1562 struct drm_minor *minor = crtc->dev->primary;
1563 struct tegra_dc *dc = to_tegra_dc(crtc);
1565 drm_debugfs_remove_files(dc->debugfs_files, count, minor);
1566 kfree(dc->debugfs_files);
1567 dc->debugfs_files = NULL;
1570 static u32 tegra_dc_get_vblank_counter(struct drm_crtc *crtc)
1572 struct tegra_dc *dc = to_tegra_dc(crtc);
1574 /* XXX vblank syncpoints don't work with nvdisplay yet */
1575 if (dc->syncpt && !dc->soc->has_nvdisplay)
1576 return host1x_syncpt_read(dc->syncpt);
1578 /* fallback to software emulated VBLANK counter */
1579 return (u32)drm_crtc_vblank_count(&dc->base);
1582 static int tegra_dc_enable_vblank(struct drm_crtc *crtc)
1584 struct tegra_dc *dc = to_tegra_dc(crtc);
1587 value = tegra_dc_readl(dc, DC_CMD_INT_MASK);
1588 value |= VBLANK_INT;
1589 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
1594 static void tegra_dc_disable_vblank(struct drm_crtc *crtc)
1596 struct tegra_dc *dc = to_tegra_dc(crtc);
1599 value = tegra_dc_readl(dc, DC_CMD_INT_MASK);
1600 value &= ~VBLANK_INT;
1601 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
1604 static const struct drm_crtc_funcs tegra_crtc_funcs = {
1605 .page_flip = drm_atomic_helper_page_flip,
1606 .set_config = drm_atomic_helper_set_config,
1607 .destroy = tegra_dc_destroy,
1608 .reset = tegra_crtc_reset,
1609 .atomic_duplicate_state = tegra_crtc_atomic_duplicate_state,
1610 .atomic_destroy_state = tegra_crtc_atomic_destroy_state,
1611 .late_register = tegra_dc_late_register,
1612 .early_unregister = tegra_dc_early_unregister,
1613 .get_vblank_counter = tegra_dc_get_vblank_counter,
1614 .enable_vblank = tegra_dc_enable_vblank,
1615 .disable_vblank = tegra_dc_disable_vblank,
1618 static int tegra_dc_set_timings(struct tegra_dc *dc,
1619 struct drm_display_mode *mode)
1621 unsigned int h_ref_to_sync = 1;
1622 unsigned int v_ref_to_sync = 1;
1623 unsigned long value;
1625 if (!dc->soc->has_nvdisplay) {
1626 tegra_dc_writel(dc, 0x0, DC_DISP_DISP_TIMING_OPTIONS);
1628 value = (v_ref_to_sync << 16) | h_ref_to_sync;
1629 tegra_dc_writel(dc, value, DC_DISP_REF_TO_SYNC);
1632 value = ((mode->vsync_end - mode->vsync_start) << 16) |
1633 ((mode->hsync_end - mode->hsync_start) << 0);
1634 tegra_dc_writel(dc, value, DC_DISP_SYNC_WIDTH);
1636 value = ((mode->vtotal - mode->vsync_end) << 16) |
1637 ((mode->htotal - mode->hsync_end) << 0);
1638 tegra_dc_writel(dc, value, DC_DISP_BACK_PORCH);
1640 value = ((mode->vsync_start - mode->vdisplay) << 16) |
1641 ((mode->hsync_start - mode->hdisplay) << 0);
1642 tegra_dc_writel(dc, value, DC_DISP_FRONT_PORCH);
1644 value = (mode->vdisplay << 16) | mode->hdisplay;
1645 tegra_dc_writel(dc, value, DC_DISP_ACTIVE);
1651 * tegra_dc_state_setup_clock - check clock settings and store them in atomic
1653 * @dc: display controller
1654 * @crtc_state: CRTC atomic state
1655 * @clk: parent clock for display controller
1656 * @pclk: pixel clock
1657 * @div: shift clock divider
1660 * 0 on success or a negative error-code on failure.
1662 int tegra_dc_state_setup_clock(struct tegra_dc *dc,
1663 struct drm_crtc_state *crtc_state,
1664 struct clk *clk, unsigned long pclk,
1667 struct tegra_dc_state *state = to_dc_state(crtc_state);
1669 if (!clk_has_parent(dc->clk, clk))
1679 static void tegra_dc_commit_state(struct tegra_dc *dc,
1680 struct tegra_dc_state *state)
1685 err = clk_set_parent(dc->clk, state->clk);
1687 dev_err(dc->dev, "failed to set parent clock: %d\n", err);
1690 * Outputs may not want to change the parent clock rate. This is only
1691 * relevant to Tegra20 where only a single display PLL is available.
1692 * Since that PLL would typically be used for HDMI, an internal LVDS
1693 * panel would need to be driven by some other clock such as PLL_P
1694 * which is shared with other peripherals. Changing the clock rate
1695 * should therefore be avoided.
1697 if (state->pclk > 0) {
1698 err = clk_set_rate(state->clk, state->pclk);
1701 "failed to set clock rate to %lu Hz\n",
1705 DRM_DEBUG_KMS("rate: %lu, div: %u\n", clk_get_rate(dc->clk),
1707 DRM_DEBUG_KMS("pclk: %lu\n", state->pclk);
1709 if (!dc->soc->has_nvdisplay) {
1710 value = SHIFT_CLK_DIVIDER(state->div) | PIXEL_CLK_DIVIDER_PCD1;
1711 tegra_dc_writel(dc, value, DC_DISP_DISP_CLOCK_CONTROL);
1714 err = clk_set_rate(dc->clk, state->pclk);
1716 dev_err(dc->dev, "failed to set clock %pC to %lu Hz: %d\n",
1717 dc->clk, state->pclk, err);
1720 static void tegra_dc_stop(struct tegra_dc *dc)
1724 /* stop the display controller */
1725 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);
1726 value &= ~DISP_CTRL_MODE_MASK;
1727 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
1729 tegra_dc_commit(dc);
1732 static bool tegra_dc_idle(struct tegra_dc *dc)
1736 value = tegra_dc_readl_active(dc, DC_CMD_DISPLAY_COMMAND);
1738 return (value & DISP_CTRL_MODE_MASK) == 0;
1741 static int tegra_dc_wait_idle(struct tegra_dc *dc, unsigned long timeout)
1743 timeout = jiffies + msecs_to_jiffies(timeout);
1745 while (time_before(jiffies, timeout)) {
1746 if (tegra_dc_idle(dc))
1749 usleep_range(1000, 2000);
1752 dev_dbg(dc->dev, "timeout waiting for DC to become idle\n");
1756 static void tegra_crtc_atomic_disable(struct drm_crtc *crtc,
1757 struct drm_atomic_state *state)
1759 struct tegra_dc *dc = to_tegra_dc(crtc);
1763 if (!tegra_dc_idle(dc)) {
1767 * Ignore the return value, there isn't anything useful to do
1768 * in case this fails.
1770 tegra_dc_wait_idle(dc, 100);
1774 * This should really be part of the RGB encoder driver, but clearing
1775 * these bits has the side-effect of stopping the display controller.
1776 * When that happens no VBLANK interrupts will be raised. At the same
1777 * time the encoder is disabled before the display controller, so the
1778 * above code is always going to timeout waiting for the controller
1781 * Given the close coupling between the RGB encoder and the display
1782 * controller doing it here is still kind of okay. None of the other
1783 * encoder drivers require these bits to be cleared.
1785 * XXX: Perhaps given that the display controller is switched off at
1786 * this point anyway maybe clearing these bits isn't even useful for
1790 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL);
1791 value &= ~(PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
1792 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE);
1793 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
1796 tegra_dc_stats_reset(&dc->stats);
1797 drm_crtc_vblank_off(crtc);
1799 spin_lock_irq(&crtc->dev->event_lock);
1801 if (crtc->state->event) {
1802 drm_crtc_send_vblank_event(crtc, crtc->state->event);
1803 crtc->state->event = NULL;
1806 spin_unlock_irq(&crtc->dev->event_lock);
1808 err = host1x_client_suspend(&dc->client);
1810 dev_err(dc->dev, "failed to suspend: %d\n", err);
1813 static void tegra_crtc_atomic_enable(struct drm_crtc *crtc,
1814 struct drm_atomic_state *state)
1816 struct drm_display_mode *mode = &crtc->state->adjusted_mode;
1817 struct tegra_dc_state *crtc_state = to_dc_state(crtc->state);
1818 struct tegra_dc *dc = to_tegra_dc(crtc);
1822 err = host1x_client_resume(&dc->client);
1824 dev_err(dc->dev, "failed to resume: %d\n", err);
1828 /* initialize display controller */
1830 u32 syncpt = host1x_syncpt_id(dc->syncpt), enable;
1832 if (dc->soc->has_nvdisplay)
1837 value = SYNCPT_CNTRL_NO_STALL;
1838 tegra_dc_writel(dc, value, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
1840 value = enable | syncpt;
1841 tegra_dc_writel(dc, value, DC_CMD_CONT_SYNCPT_VSYNC);
1844 if (dc->soc->has_nvdisplay) {
1845 value = DSC_TO_UF_INT | DSC_BBUF_UF_INT | DSC_RBUF_UF_INT |
1847 tegra_dc_writel(dc, value, DC_CMD_INT_TYPE);
1849 value = DSC_TO_UF_INT | DSC_BBUF_UF_INT | DSC_RBUF_UF_INT |
1850 DSC_OBUF_UF_INT | SD3_BUCKET_WALK_DONE_INT |
1851 HEAD_UF_INT | MSF_INT | REG_TMOUT_INT |
1852 REGION_CRC_INT | V_PULSE2_INT | V_PULSE3_INT |
1853 VBLANK_INT | FRAME_END_INT;
1854 tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY);
1856 value = SD3_BUCKET_WALK_DONE_INT | HEAD_UF_INT | VBLANK_INT |
1858 tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE);
1860 value = HEAD_UF_INT | REG_TMOUT_INT | FRAME_END_INT;
1861 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
1863 tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS);
1865 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
1866 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
1867 tegra_dc_writel(dc, value, DC_CMD_INT_TYPE);
1869 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
1870 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
1871 tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY);
1873 /* initialize timer */
1874 value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(0x20) |
1875 WINDOW_B_THRESHOLD(0x20) | WINDOW_C_THRESHOLD(0x20);
1876 tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY);
1878 value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(1) |
1879 WINDOW_B_THRESHOLD(1) | WINDOW_C_THRESHOLD(1);
1880 tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER);
1882 value = VBLANK_INT | WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
1883 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
1884 tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE);
1886 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
1887 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
1888 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
1891 if (dc->soc->supports_background_color)
1892 tegra_dc_writel(dc, 0, DC_DISP_BLEND_BACKGROUND_COLOR);
1894 tegra_dc_writel(dc, 0, DC_DISP_BORDER_COLOR);
1896 /* apply PLL and pixel clock changes */
1897 tegra_dc_commit_state(dc, crtc_state);
1899 /* program display mode */
1900 tegra_dc_set_timings(dc, mode);
1902 /* interlacing isn't supported yet, so disable it */
1903 if (dc->soc->supports_interlacing) {
1904 value = tegra_dc_readl(dc, DC_DISP_INTERLACE_CONTROL);
1905 value &= ~INTERLACE_ENABLE;
1906 tegra_dc_writel(dc, value, DC_DISP_INTERLACE_CONTROL);
1909 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);
1910 value &= ~DISP_CTRL_MODE_MASK;
1911 value |= DISP_CTRL_MODE_C_DISPLAY;
1912 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
1914 if (!dc->soc->has_nvdisplay) {
1915 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL);
1916 value |= PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
1917 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE;
1918 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
1921 /* enable underflow reporting and display red for missing pixels */
1922 if (dc->soc->has_nvdisplay) {
1923 value = UNDERFLOW_MODE_RED | UNDERFLOW_REPORT_ENABLE;
1924 tegra_dc_writel(dc, value, DC_COM_RG_UNDERFLOW);
1927 tegra_dc_commit(dc);
1929 drm_crtc_vblank_on(crtc);
1932 static void tegra_crtc_atomic_begin(struct drm_crtc *crtc,
1933 struct drm_atomic_state *state)
1935 unsigned long flags;
1937 if (crtc->state->event) {
1938 spin_lock_irqsave(&crtc->dev->event_lock, flags);
1940 if (drm_crtc_vblank_get(crtc) != 0)
1941 drm_crtc_send_vblank_event(crtc, crtc->state->event);
1943 drm_crtc_arm_vblank_event(crtc, crtc->state->event);
1945 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
1947 crtc->state->event = NULL;
1951 static void tegra_crtc_atomic_flush(struct drm_crtc *crtc,
1952 struct drm_atomic_state *state)
1954 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,
1956 struct tegra_dc_state *dc_state = to_dc_state(crtc_state);
1957 struct tegra_dc *dc = to_tegra_dc(crtc);
1960 value = dc_state->planes << 8 | GENERAL_UPDATE;
1961 tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);
1962 value = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
1964 value = dc_state->planes | GENERAL_ACT_REQ;
1965 tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);
1966 value = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
1969 static const struct drm_crtc_helper_funcs tegra_crtc_helper_funcs = {
1970 .atomic_begin = tegra_crtc_atomic_begin,
1971 .atomic_flush = tegra_crtc_atomic_flush,
1972 .atomic_enable = tegra_crtc_atomic_enable,
1973 .atomic_disable = tegra_crtc_atomic_disable,
1976 static irqreturn_t tegra_dc_irq(int irq, void *data)
1978 struct tegra_dc *dc = data;
1979 unsigned long status;
1981 status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
1982 tegra_dc_writel(dc, status, DC_CMD_INT_STATUS);
1984 if (status & FRAME_END_INT) {
1986 dev_dbg(dc->dev, "%s(): frame end\n", __func__);
1991 if (status & VBLANK_INT) {
1993 dev_dbg(dc->dev, "%s(): vertical blank\n", __func__);
1995 drm_crtc_handle_vblank(&dc->base);
1999 if (status & (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT)) {
2001 dev_dbg(dc->dev, "%s(): underflow\n", __func__);
2003 dc->stats.underflow++;
2006 if (status & (WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT)) {
2008 dev_dbg(dc->dev, "%s(): overflow\n", __func__);
2010 dc->stats.overflow++;
2013 if (status & HEAD_UF_INT) {
2014 dev_dbg_ratelimited(dc->dev, "%s(): head underflow\n", __func__);
2015 dc->stats.underflow++;
2021 static bool tegra_dc_has_window_groups(struct tegra_dc *dc)
2025 if (!dc->soc->wgrps)
2028 for (i = 0; i < dc->soc->num_wgrps; i++) {
2029 const struct tegra_windowgroup_soc *wgrp = &dc->soc->wgrps[i];
2031 if (wgrp->dc == dc->pipe && wgrp->num_windows > 0)
2038 static int tegra_dc_init(struct host1x_client *client)
2040 struct drm_device *drm = dev_get_drvdata(client->host);
2041 unsigned long flags = HOST1X_SYNCPT_CLIENT_MANAGED;
2042 struct tegra_dc *dc = host1x_client_to_dc(client);
2043 struct tegra_drm *tegra = drm->dev_private;
2044 struct drm_plane *primary = NULL;
2045 struct drm_plane *cursor = NULL;
2049 * XXX do not register DCs with no window groups because we cannot
2050 * assign a primary plane to them, which in turn will cause KMS to
2053 if (!tegra_dc_has_window_groups(dc))
2057 * Set the display hub as the host1x client parent for the display
2058 * controller. This is needed for the runtime reference counting that
2059 * ensures the display hub is always powered when any of the display
2062 if (dc->soc->has_nvdisplay)
2063 client->parent = &tegra->hub->client;
2065 dc->syncpt = host1x_syncpt_request(client, flags);
2067 dev_warn(dc->dev, "failed to allocate syncpoint\n");
2069 err = host1x_client_iommu_attach(client);
2070 if (err < 0 && err != -ENODEV) {
2071 dev_err(client->dev, "failed to attach to domain: %d\n", err);
2076 primary = tegra_dc_add_shared_planes(drm, dc);
2078 primary = tegra_dc_add_planes(drm, dc);
2080 if (IS_ERR(primary)) {
2081 err = PTR_ERR(primary);
2085 if (dc->soc->supports_cursor) {
2086 cursor = tegra_dc_cursor_plane_create(drm, dc);
2087 if (IS_ERR(cursor)) {
2088 err = PTR_ERR(cursor);
2092 /* dedicate one overlay to mouse cursor */
2093 cursor = tegra_dc_overlay_plane_create(drm, dc, 2, true);
2094 if (IS_ERR(cursor)) {
2095 err = PTR_ERR(cursor);
2100 err = drm_crtc_init_with_planes(drm, &dc->base, primary, cursor,
2101 &tegra_crtc_funcs, NULL);
2105 drm_crtc_helper_add(&dc->base, &tegra_crtc_helper_funcs);
2108 * Keep track of the minimum pitch alignment across all display
2111 if (dc->soc->pitch_align > tegra->pitch_align)
2112 tegra->pitch_align = dc->soc->pitch_align;
2114 err = tegra_dc_rgb_init(drm, dc);
2115 if (err < 0 && err != -ENODEV) {
2116 dev_err(dc->dev, "failed to initialize RGB output: %d\n", err);
2120 err = devm_request_irq(dc->dev, dc->irq, tegra_dc_irq, 0,
2121 dev_name(dc->dev), dc);
2123 dev_err(dc->dev, "failed to request IRQ#%u: %d\n", dc->irq,
2129 * Inherit the DMA parameters (such as maximum segment size) from the
2130 * parent host1x device.
2132 client->dev->dma_parms = client->host->dma_parms;
2137 if (!IS_ERR_OR_NULL(cursor))
2138 drm_plane_cleanup(cursor);
2140 if (!IS_ERR(primary))
2141 drm_plane_cleanup(primary);
2143 host1x_client_iommu_detach(client);
2144 host1x_syncpt_free(dc->syncpt);
2149 static int tegra_dc_exit(struct host1x_client *client)
2151 struct tegra_dc *dc = host1x_client_to_dc(client);
2154 if (!tegra_dc_has_window_groups(dc))
2157 /* avoid a dangling pointer just in case this disappears */
2158 client->dev->dma_parms = NULL;
2160 devm_free_irq(dc->dev, dc->irq, dc);
2162 err = tegra_dc_rgb_exit(dc);
2164 dev_err(dc->dev, "failed to shutdown RGB output: %d\n", err);
2168 host1x_client_iommu_detach(client);
2169 host1x_syncpt_free(dc->syncpt);
2174 static int tegra_dc_runtime_suspend(struct host1x_client *client)
2176 struct tegra_dc *dc = host1x_client_to_dc(client);
2177 struct device *dev = client->dev;
2180 err = reset_control_assert(dc->rst);
2182 dev_err(dev, "failed to assert reset: %d\n", err);
2186 if (dc->soc->has_powergate)
2187 tegra_powergate_power_off(dc->powergate);
2189 clk_disable_unprepare(dc->clk);
2190 pm_runtime_put_sync(dev);
2195 static int tegra_dc_runtime_resume(struct host1x_client *client)
2197 struct tegra_dc *dc = host1x_client_to_dc(client);
2198 struct device *dev = client->dev;
2201 err = pm_runtime_resume_and_get(dev);
2203 dev_err(dev, "failed to get runtime PM: %d\n", err);
2207 if (dc->soc->has_powergate) {
2208 err = tegra_powergate_sequence_power_up(dc->powergate, dc->clk,
2211 dev_err(dev, "failed to power partition: %d\n", err);
2215 err = clk_prepare_enable(dc->clk);
2217 dev_err(dev, "failed to enable clock: %d\n", err);
2221 err = reset_control_deassert(dc->rst);
2223 dev_err(dev, "failed to deassert reset: %d\n", err);
2231 clk_disable_unprepare(dc->clk);
2233 pm_runtime_put_sync(dev);
2237 static const struct host1x_client_ops dc_client_ops = {
2238 .init = tegra_dc_init,
2239 .exit = tegra_dc_exit,
2240 .suspend = tegra_dc_runtime_suspend,
2241 .resume = tegra_dc_runtime_resume,
2244 static const struct tegra_dc_soc_info tegra20_dc_soc_info = {
2245 .supports_background_color = false,
2246 .supports_interlacing = false,
2247 .supports_cursor = false,
2248 .supports_block_linear = false,
2249 .has_legacy_blending = true,
2251 .has_powergate = false,
2253 .has_nvdisplay = false,
2254 .num_primary_formats = ARRAY_SIZE(tegra20_primary_formats),
2255 .primary_formats = tegra20_primary_formats,
2256 .num_overlay_formats = ARRAY_SIZE(tegra20_overlay_formats),
2257 .overlay_formats = tegra20_overlay_formats,
2258 .modifiers = tegra20_modifiers,
2259 .has_win_a_without_filters = true,
2260 .has_win_c_without_vert_filter = true,
2263 static const struct tegra_dc_soc_info tegra30_dc_soc_info = {
2264 .supports_background_color = false,
2265 .supports_interlacing = false,
2266 .supports_cursor = false,
2267 .supports_block_linear = false,
2268 .has_legacy_blending = true,
2270 .has_powergate = false,
2271 .coupled_pm = false,
2272 .has_nvdisplay = false,
2273 .num_primary_formats = ARRAY_SIZE(tegra20_primary_formats),
2274 .primary_formats = tegra20_primary_formats,
2275 .num_overlay_formats = ARRAY_SIZE(tegra20_overlay_formats),
2276 .overlay_formats = tegra20_overlay_formats,
2277 .modifiers = tegra20_modifiers,
2278 .has_win_a_without_filters = false,
2279 .has_win_c_without_vert_filter = false,
2282 static const struct tegra_dc_soc_info tegra114_dc_soc_info = {
2283 .supports_background_color = false,
2284 .supports_interlacing = false,
2285 .supports_cursor = false,
2286 .supports_block_linear = false,
2287 .has_legacy_blending = true,
2289 .has_powergate = true,
2290 .coupled_pm = false,
2291 .has_nvdisplay = false,
2292 .num_primary_formats = ARRAY_SIZE(tegra114_primary_formats),
2293 .primary_formats = tegra114_primary_formats,
2294 .num_overlay_formats = ARRAY_SIZE(tegra114_overlay_formats),
2295 .overlay_formats = tegra114_overlay_formats,
2296 .modifiers = tegra20_modifiers,
2297 .has_win_a_without_filters = false,
2298 .has_win_c_without_vert_filter = false,
2301 static const struct tegra_dc_soc_info tegra124_dc_soc_info = {
2302 .supports_background_color = true,
2303 .supports_interlacing = true,
2304 .supports_cursor = true,
2305 .supports_block_linear = true,
2306 .has_legacy_blending = false,
2308 .has_powergate = true,
2309 .coupled_pm = false,
2310 .has_nvdisplay = false,
2311 .num_primary_formats = ARRAY_SIZE(tegra124_primary_formats),
2312 .primary_formats = tegra124_primary_formats,
2313 .num_overlay_formats = ARRAY_SIZE(tegra124_overlay_formats),
2314 .overlay_formats = tegra124_overlay_formats,
2315 .modifiers = tegra124_modifiers,
2316 .has_win_a_without_filters = false,
2317 .has_win_c_without_vert_filter = false,
2320 static const struct tegra_dc_soc_info tegra210_dc_soc_info = {
2321 .supports_background_color = true,
2322 .supports_interlacing = true,
2323 .supports_cursor = true,
2324 .supports_block_linear = true,
2325 .has_legacy_blending = false,
2327 .has_powergate = true,
2328 .coupled_pm = false,
2329 .has_nvdisplay = false,
2330 .num_primary_formats = ARRAY_SIZE(tegra114_primary_formats),
2331 .primary_formats = tegra114_primary_formats,
2332 .num_overlay_formats = ARRAY_SIZE(tegra114_overlay_formats),
2333 .overlay_formats = tegra114_overlay_formats,
2334 .modifiers = tegra124_modifiers,
2335 .has_win_a_without_filters = false,
2336 .has_win_c_without_vert_filter = false,
2339 static const struct tegra_windowgroup_soc tegra186_dc_wgrps[] = {
2343 .windows = (const unsigned int[]) { 0 },
2348 .windows = (const unsigned int[]) { 1 },
2353 .windows = (const unsigned int[]) { 2 },
2358 .windows = (const unsigned int[]) { 3 },
2363 .windows = (const unsigned int[]) { 4 },
2368 .windows = (const unsigned int[]) { 5 },
2373 static const struct tegra_dc_soc_info tegra186_dc_soc_info = {
2374 .supports_background_color = true,
2375 .supports_interlacing = true,
2376 .supports_cursor = true,
2377 .supports_block_linear = true,
2378 .has_legacy_blending = false,
2380 .has_powergate = false,
2381 .coupled_pm = false,
2382 .has_nvdisplay = true,
2383 .wgrps = tegra186_dc_wgrps,
2384 .num_wgrps = ARRAY_SIZE(tegra186_dc_wgrps),
2387 static const struct tegra_windowgroup_soc tegra194_dc_wgrps[] = {
2391 .windows = (const unsigned int[]) { 0 },
2396 .windows = (const unsigned int[]) { 1 },
2401 .windows = (const unsigned int[]) { 2 },
2406 .windows = (const unsigned int[]) { 3 },
2411 .windows = (const unsigned int[]) { 4 },
2416 .windows = (const unsigned int[]) { 5 },
2421 static const struct tegra_dc_soc_info tegra194_dc_soc_info = {
2422 .supports_background_color = true,
2423 .supports_interlacing = true,
2424 .supports_cursor = true,
2425 .supports_block_linear = true,
2426 .has_legacy_blending = false,
2428 .has_powergate = false,
2429 .coupled_pm = false,
2430 .has_nvdisplay = true,
2431 .wgrps = tegra194_dc_wgrps,
2432 .num_wgrps = ARRAY_SIZE(tegra194_dc_wgrps),
2435 static const struct of_device_id tegra_dc_of_match[] = {
2437 .compatible = "nvidia,tegra194-dc",
2438 .data = &tegra194_dc_soc_info,
2440 .compatible = "nvidia,tegra186-dc",
2441 .data = &tegra186_dc_soc_info,
2443 .compatible = "nvidia,tegra210-dc",
2444 .data = &tegra210_dc_soc_info,
2446 .compatible = "nvidia,tegra124-dc",
2447 .data = &tegra124_dc_soc_info,
2449 .compatible = "nvidia,tegra114-dc",
2450 .data = &tegra114_dc_soc_info,
2452 .compatible = "nvidia,tegra30-dc",
2453 .data = &tegra30_dc_soc_info,
2455 .compatible = "nvidia,tegra20-dc",
2456 .data = &tegra20_dc_soc_info,
2461 MODULE_DEVICE_TABLE(of, tegra_dc_of_match);
2463 static int tegra_dc_parse_dt(struct tegra_dc *dc)
2465 struct device_node *np;
2469 err = of_property_read_u32(dc->dev->of_node, "nvidia,head", &value);
2471 dev_err(dc->dev, "missing \"nvidia,head\" property\n");
2474 * If the nvidia,head property isn't present, try to find the
2475 * correct head number by looking up the position of this
2476 * display controller's node within the device tree. Assuming
2477 * that the nodes are ordered properly in the DTS file and
2478 * that the translation into a flattened device tree blob
2479 * preserves that ordering this will actually yield the right
2482 * If those assumptions don't hold, this will still work for
2483 * cases where only a single display controller is used.
2485 for_each_matching_node(np, tegra_dc_of_match) {
2486 if (np == dc->dev->of_node) {
2500 static int tegra_dc_match_by_pipe(struct device *dev, const void *data)
2502 struct tegra_dc *dc = dev_get_drvdata(dev);
2503 unsigned int pipe = (unsigned long)(void *)data;
2505 return dc->pipe == pipe;
2508 static int tegra_dc_couple(struct tegra_dc *dc)
2511 * On Tegra20, DC1 requires DC0 to be taken out of reset in order to
2512 * be enabled, otherwise CPU hangs on writing to CMD_DISPLAY_COMMAND /
2513 * POWER_CONTROL registers during CRTC enabling.
2515 if (dc->soc->coupled_pm && dc->pipe == 1) {
2516 u32 flags = DL_FLAG_PM_RUNTIME | DL_FLAG_AUTOREMOVE_CONSUMER;
2517 struct device_link *link;
2518 struct device *partner;
2520 partner = driver_find_device(dc->dev->driver, NULL, NULL,
2521 tegra_dc_match_by_pipe);
2523 return -EPROBE_DEFER;
2525 link = device_link_add(dc->dev, partner, flags);
2527 dev_err(dc->dev, "failed to link controllers\n");
2531 dev_dbg(dc->dev, "coupled to %s\n", dev_name(partner));
2537 static int tegra_dc_probe(struct platform_device *pdev)
2539 struct tegra_dc *dc;
2542 dc = devm_kzalloc(&pdev->dev, sizeof(*dc), GFP_KERNEL);
2546 dc->soc = of_device_get_match_data(&pdev->dev);
2548 INIT_LIST_HEAD(&dc->list);
2549 dc->dev = &pdev->dev;
2551 err = tegra_dc_parse_dt(dc);
2555 err = tegra_dc_couple(dc);
2559 dc->clk = devm_clk_get(&pdev->dev, NULL);
2560 if (IS_ERR(dc->clk)) {
2561 dev_err(&pdev->dev, "failed to get clock\n");
2562 return PTR_ERR(dc->clk);
2565 dc->rst = devm_reset_control_get(&pdev->dev, "dc");
2566 if (IS_ERR(dc->rst)) {
2567 dev_err(&pdev->dev, "failed to get reset\n");
2568 return PTR_ERR(dc->rst);
2571 /* assert reset and disable clock */
2572 err = clk_prepare_enable(dc->clk);
2576 usleep_range(2000, 4000);
2578 err = reset_control_assert(dc->rst);
2582 usleep_range(2000, 4000);
2584 clk_disable_unprepare(dc->clk);
2586 if (dc->soc->has_powergate) {
2588 dc->powergate = TEGRA_POWERGATE_DIS;
2590 dc->powergate = TEGRA_POWERGATE_DISB;
2592 tegra_powergate_power_off(dc->powergate);
2595 dc->regs = devm_platform_ioremap_resource(pdev, 0);
2596 if (IS_ERR(dc->regs))
2597 return PTR_ERR(dc->regs);
2599 dc->irq = platform_get_irq(pdev, 0);
2603 err = tegra_dc_rgb_probe(dc);
2604 if (err < 0 && err != -ENODEV) {
2605 const char *level = KERN_ERR;
2607 if (err == -EPROBE_DEFER)
2610 dev_printk(level, dc->dev, "failed to probe RGB output: %d\n",
2615 platform_set_drvdata(pdev, dc);
2616 pm_runtime_enable(&pdev->dev);
2618 INIT_LIST_HEAD(&dc->client.list);
2619 dc->client.ops = &dc_client_ops;
2620 dc->client.dev = &pdev->dev;
2622 err = host1x_client_register(&dc->client);
2624 dev_err(&pdev->dev, "failed to register host1x client: %d\n",
2632 pm_runtime_disable(&pdev->dev);
2633 tegra_dc_rgb_remove(dc);
2638 static int tegra_dc_remove(struct platform_device *pdev)
2640 struct tegra_dc *dc = platform_get_drvdata(pdev);
2643 err = host1x_client_unregister(&dc->client);
2645 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
2650 err = tegra_dc_rgb_remove(dc);
2652 dev_err(&pdev->dev, "failed to remove RGB output: %d\n", err);
2656 pm_runtime_disable(&pdev->dev);
2661 struct platform_driver tegra_dc_driver = {
2664 .of_match_table = tegra_dc_of_match,
2666 .probe = tegra_dc_probe,
2667 .remove = tegra_dc_remove,