drivers/gpu/drm/tegra/dc.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2012 Avionic Design GmbH
   4  * Copyright (C) 2012 NVIDIA CORPORATION.  All rights reserved.
   5  */
   6
   7 #include <linux/clk.h>
   8 #include <linux/debugfs.h>
   9 #include <linux/delay.h>
  10 #include <linux/iommu.h>
  11 #include <linux/interconnect.h>
  12 #include <linux/module.h>
  13 #include <linux/of_device.h>
  14 #include <linux/pm_runtime.h>
  15 #include <linux/reset.h>
  16
  17 #include <soc/tegra/pmc.h>
  18
  19 #include <drm/drm_atomic.h>
  20 #include <drm/drm_atomic_helper.h>
  21 #include <drm/drm_debugfs.h>
  22 #include <drm/drm_fourcc.h>
  23 #include <drm/drm_plane_helper.h>
  24 #include <drm/drm_vblank.h>
  25
  26 #include "dc.h"
  27 #include "drm.h"
  28 #include "gem.h"
  29 #include "hub.h"
  30 #include "plane.h"
  31
  32 static void tegra_crtc_atomic_destroy_state(struct drm_crtc *crtc,
  33                                             struct drm_crtc_state *state);
  34
  35 static void tegra_dc_stats_reset(struct tegra_dc_stats *stats)
  36 {
  37         stats->frames = 0;
  38         stats->vblank = 0;
  39         stats->underflow = 0;
  40         stats->overflow = 0;
  41 }
  42
  43 /* Reads the active copy of a register. */
  44 static u32 tegra_dc_readl_active(struct tegra_dc *dc, unsigned long offset)
  45 {
  46         u32 value;
  47
  48         tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS);
  49         value = tegra_dc_readl(dc, offset);
  50         tegra_dc_writel(dc, 0, DC_CMD_STATE_ACCESS);
  51
  52         return value;
  53 }
  54
  55 static inline unsigned int tegra_plane_offset(struct tegra_plane *plane,
  56                                               unsigned int offset)
  57 {
  58         if (offset >= 0x500 && offset <= 0x638) {
  59                 offset = 0x000 + (offset - 0x500);
  60                 return plane->offset + offset;
  61         }
  62
  63         if (offset >= 0x700 && offset <= 0x719) {
  64                 offset = 0x180 + (offset - 0x700);
  65                 return plane->offset + offset;
  66         }
  67
  68         if (offset >= 0x800 && offset <= 0x839) {
  69                 offset = 0x1c0 + (offset - 0x800);
  70                 return plane->offset + offset;
  71         }
  72
  73         dev_WARN(plane->dc->dev, "invalid offset: %x\n", offset);
  74
  75         return plane->offset + offset;
  76 }
  77
  78 static inline u32 tegra_plane_readl(struct tegra_plane *plane,
  79                                     unsigned int offset)
  80 {
  81         return tegra_dc_readl(plane->dc, tegra_plane_offset(plane, offset));
  82 }
  83
  84 static inline void tegra_plane_writel(struct tegra_plane *plane, u32 value,
  85                                       unsigned int offset)
  86 {
  87         tegra_dc_writel(plane->dc, value, tegra_plane_offset(plane, offset));
  88 }
  89
  90 bool tegra_dc_has_output(struct tegra_dc *dc, struct device *dev)
  91 {
  92         struct device_node *np = dc->dev->of_node;
  93         struct of_phandle_iterator it;
  94         int err;
  95
  96         of_for_each_phandle(&it, err, np, "nvidia,outputs", NULL, 0)
  97                 if (it.node == dev->of_node)
  98                         return true;
  99
 100         return false;
 101 }
 102
 103 /*
 104  * Double-buffered registers have two copies: ASSEMBLY and ACTIVE. When the
 105  * *_ACT_REQ bits are set the ASSEMBLY copy is latched into the ACTIVE copy.
 106  * Latching happens mmediately if the display controller is in STOP mode or
 107  * on the next frame boundary otherwise.
 108  *
 109  * Triple-buffered registers have three copies: ASSEMBLY, ARM and ACTIVE. The
 110  * ASSEMBLY copy is latched into the ARM copy immediately after *_UPDATE bits
 111  * are written. When the *_ACT_REQ bits are written, the ARM copy is latched
 112  * into the ACTIVE copy, either immediately if the display controller is in
 113  * STOP mode, or at the next frame boundary otherwise.
 114  */
 115 void tegra_dc_commit(struct tegra_dc *dc)
 116 {
 117         tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
 118         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
 119 }
 120
 121 static inline u32 compute_dda_inc(unsigned int in, unsigned int out, bool v,
 122                                   unsigned int bpp)
 123 {
 124         fixed20_12 outf = dfixed_init(out);
 125         fixed20_12 inf = dfixed_init(in);
 126         u32 dda_inc;
 127         int max;
 128
 129         if (v)
 130                 max = 15;
 131         else {
 132                 switch (bpp) {
 133                 case 2:
 134                         max = 8;
 135                         break;
 136
 137                 default:
 138                         WARN_ON_ONCE(1);
 139                         fallthrough;
 140                 case 4:
 141                         max = 4;
 142                         break;
 143                 }
 144         }
 145
 146         outf.full = max_t(u32, outf.full - dfixed_const(1), dfixed_const(1));
 147         inf.full -= dfixed_const(1);
 148
 149         dda_inc = dfixed_div(inf, outf);
 150         dda_inc = min_t(u32, dda_inc, dfixed_const(max));
 151
 152         return dda_inc;
 153 }
 154
 155 static inline u32 compute_initial_dda(unsigned int in)
 156 {
 157         fixed20_12 inf = dfixed_init(in);
 158         return dfixed_frac(inf);
 159 }
 160
 161 static void tegra_plane_setup_blending_legacy(struct tegra_plane *plane)
 162 {
 163         u32 background[3] = {
 164                 BLEND_WEIGHT1(0) | BLEND_WEIGHT0(0) | BLEND_COLOR_KEY_NONE,
 165                 BLEND_WEIGHT1(0) | BLEND_WEIGHT0(0) | BLEND_COLOR_KEY_NONE,
 166                 BLEND_WEIGHT1(0) | BLEND_WEIGHT0(0) | BLEND_COLOR_KEY_NONE,
 167         };
 168         u32 foreground = BLEND_WEIGHT1(255) | BLEND_WEIGHT0(255) |
 169                          BLEND_COLOR_KEY_NONE;
 170         u32 blendnokey = BLEND_WEIGHT1(255) | BLEND_WEIGHT0(255);
 171         struct tegra_plane_state *state;
 172         u32 blending[2];
 173         unsigned int i;
 174
 175         /* disable blending for non-overlapping case */
 176         tegra_plane_writel(plane, blendnokey, DC_WIN_BLEND_NOKEY);
 177         tegra_plane_writel(plane, foreground, DC_WIN_BLEND_1WIN);
 178
 179         state = to_tegra_plane_state(plane->base.state);
 180
 181         if (state->opaque) {
 182                 /*
 183                  * Since custom fix-weight blending isn't utilized and weight
 184                  * of top window is set to max, we can enforce dependent
 185                  * blending which in this case results in transparent bottom
 186                  * window if top window is opaque and if top window enables
 187                  * alpha blending, then bottom window is getting alpha value
 188                  * of 1 minus the sum of alpha components of the overlapping
 189                  * plane.
 190                  */
 191                 background[0] |= BLEND_CONTROL_DEPENDENT;
 192                 background[1] |= BLEND_CONTROL_DEPENDENT;
 193
 194                 /*
 195                  * The region where three windows overlap is the intersection
 196                  * of the two regions where two windows overlap. It contributes
 197                  * to the area if all of the windows on top of it have an alpha
 198                  * component.
 199                  */
 200                 switch (state->base.normalized_zpos) {
 201                 case 0:
 202                         if (state->blending[0].alpha &&
 203                             state->blending[1].alpha)
 204                                 background[2] |= BLEND_CONTROL_DEPENDENT;
 205                         break;
 206
 207                 case 1:
 208                         background[2] |= BLEND_CONTROL_DEPENDENT;
 209                         break;
 210                 }
 211         } else {
 212                 /*
 213                  * Enable alpha blending if pixel format has an alpha
 214                  * component.
 215                  */
 216                 foreground |= BLEND_CONTROL_ALPHA;
 217
 218                 /*
 219                  * If any of the windows on top of this window is opaque, it
 220                  * will completely conceal this window within that area. If
 221                  * top window has an alpha component, it is blended over the
 222                  * bottom window.
 223                  */
 224                 for (i = 0; i < 2; i++) {
 225                         if (state->blending[i].alpha &&
 226                             state->blending[i].top)
 227                                 background[i] |= BLEND_CONTROL_DEPENDENT;
 228                 }
 229
 230                 switch (state->base.normalized_zpos) {
 231                 case 0:
 232                         if (state->blending[0].alpha &&
 233                             state->blending[1].alpha)
 234                                 background[2] |= BLEND_CONTROL_DEPENDENT;
 235                         break;
 236
 237                 case 1:
 238                         /*
 239                          * When both middle and topmost windows have an alpha,
 240                          * these windows a mixed together and then the result
 241                          * is blended over the bottom window.
 242                          */
 243                         if (state->blending[0].alpha &&
 244                             state->blending[0].top)
 245                                 background[2] |= BLEND_CONTROL_ALPHA;
 246
 247                         if (state->blending[1].alpha &&
 248                             state->blending[1].top)
 249                                 background[2] |= BLEND_CONTROL_ALPHA;
 250                         break;
 251                 }
 252         }
 253
 254         switch (state->base.normalized_zpos) {
 255         case 0:
 256                 tegra_plane_writel(plane, background[0], DC_WIN_BLEND_2WIN_X);
 257                 tegra_plane_writel(plane, background[1], DC_WIN_BLEND_2WIN_Y);
 258                 tegra_plane_writel(plane, background[2], DC_WIN_BLEND_3WIN_XY);
 259                 break;
 260
 261         case 1:
 262                 /*
 263                  * If window B / C is topmost, then X / Y registers are
 264                  * matching the order of blending[...] state indices,
 265                  * otherwise a swap is required.
 266                  */
 267                 if (!state->blending[0].top && state->blending[1].top) {
 268                         blending[0] = foreground;
 269                         blending[1] = background[1];
 270                 } else {
 271                         blending[0] = background[0];
 272                         blending[1] = foreground;
 273                 }
 274
 275                 tegra_plane_writel(plane, blending[0], DC_WIN_BLEND_2WIN_X);
 276                 tegra_plane_writel(plane, blending[1], DC_WIN_BLEND_2WIN_Y);
 277                 tegra_plane_writel(plane, background[2], DC_WIN_BLEND_3WIN_XY);
 278                 break;
 279
 280         case 2:
 281                 tegra_plane_writel(plane, foreground, DC_WIN_BLEND_2WIN_X);
 282                 tegra_plane_writel(plane, foreground, DC_WIN_BLEND_2WIN_Y);
 283                 tegra_plane_writel(plane, foreground, DC_WIN_BLEND_3WIN_XY);
 284                 break;
 285         }
 286 }
 287
 288 static void tegra_plane_setup_blending(struct tegra_plane *plane,
 289                                        const struct tegra_dc_window *window)
 290 {
 291         u32 value;
 292
 293         value = BLEND_FACTOR_DST_ALPHA_ZERO | BLEND_FACTOR_SRC_ALPHA_K2 |
 294                 BLEND_FACTOR_DST_COLOR_NEG_K1_TIMES_SRC |
 295                 BLEND_FACTOR_SRC_COLOR_K1_TIMES_SRC;
 296         tegra_plane_writel(plane, value, DC_WIN_BLEND_MATCH_SELECT);
 297
 298         value = BLEND_FACTOR_DST_ALPHA_ZERO | BLEND_FACTOR_SRC_ALPHA_K2 |
 299                 BLEND_FACTOR_DST_COLOR_NEG_K1_TIMES_SRC |
 300                 BLEND_FACTOR_SRC_COLOR_K1_TIMES_SRC;
 301         tegra_plane_writel(plane, value, DC_WIN_BLEND_NOMATCH_SELECT);
 302
 303         value = K2(255) | K1(255) | WINDOW_LAYER_DEPTH(255 - window->zpos);
 304         tegra_plane_writel(plane, value, DC_WIN_BLEND_LAYER_CONTROL);
 305 }
 306
 307 static bool
 308 tegra_plane_use_horizontal_filtering(struct tegra_plane *plane,
 309                                      const struct tegra_dc_window *window)
 310 {
 311         struct tegra_dc *dc = plane->dc;
 312
 313         if (window->src.w == window->dst.w)
 314                 return false;
 315
 316         if (plane->index == 0 && dc->soc->has_win_a_without_filters)
 317                 return false;
 318
 319         return true;
 320 }
 321
 322 static bool
 323 tegra_plane_use_vertical_filtering(struct tegra_plane *plane,
 324                                    const struct tegra_dc_window *window)
 325 {
 326         struct tegra_dc *dc = plane->dc;
 327
 328         if (window->src.h == window->dst.h)
 329                 return false;
 330
 331         if (plane->index == 0 && dc->soc->has_win_a_without_filters)
 332                 return false;
 333
 334         if (plane->index == 2 && dc->soc->has_win_c_without_vert_filter)
 335                 return false;
 336
 337         return true;
 338 }
 339
 340 static void tegra_dc_setup_window(struct tegra_plane *plane,
 341                                   const struct tegra_dc_window *window)
 342 {
 343         unsigned h_offset, v_offset, h_size, v_size, h_dda, v_dda, bpp;
 344         struct tegra_dc *dc = plane->dc;
 345         bool yuv, planar;
 346         u32 value;
 347
 348         /*
 349          * For YUV planar modes, the number of bytes per pixel takes into
 350          * account only the luma component and therefore is 1.
 351          */
 352         yuv = tegra_plane_format_is_yuv(window->format, &planar, NULL);
 353         if (!yuv)
 354                 bpp = window->bits_per_pixel / 8;
 355         else
 356                 bpp = planar ? 1 : 2;
 357
 358         tegra_plane_writel(plane, window->format, DC_WIN_COLOR_DEPTH);
 359         tegra_plane_writel(plane, window->swap, DC_WIN_BYTE_SWAP);
 360
 361         value = V_POSITION(window->dst.y) | H_POSITION(window->dst.x);
 362         tegra_plane_writel(plane, value, DC_WIN_POSITION);
 363
 364         value = V_SIZE(window->dst.h) | H_SIZE(window->dst.w);
 365         tegra_plane_writel(plane, value, DC_WIN_SIZE);
 366
 367         h_offset = window->src.x * bpp;
 368         v_offset = window->src.y;
 369         h_size = window->src.w * bpp;
 370         v_size = window->src.h;
 371
 372         if (window->reflect_x)
 373                 h_offset += (window->src.w - 1) * bpp;
 374
 375         if (window->reflect_y)
 376                 v_offset += window->src.h - 1;
 377
 378         value = V_PRESCALED_SIZE(v_size) | H_PRESCALED_SIZE(h_size);
 379         tegra_plane_writel(plane, value, DC_WIN_PRESCALED_SIZE);
 380
 381         /*
 382          * For DDA computations the number of bytes per pixel for YUV planar
 383          * modes needs to take into account all Y, U and V components.
 384          */
 385         if (yuv && planar)
 386                 bpp = 2;
 387
 388         h_dda = compute_dda_inc(window->src.w, window->dst.w, false, bpp);
 389         v_dda = compute_dda_inc(window->src.h, window->dst.h, true, bpp);
 390
 391         value = V_DDA_INC(v_dda) | H_DDA_INC(h_dda);
 392         tegra_plane_writel(plane, value, DC_WIN_DDA_INC);
 393
 394         h_dda = compute_initial_dda(window->src.x);
 395         v_dda = compute_initial_dda(window->src.y);
 396
 397         tegra_plane_writel(plane, h_dda, DC_WIN_H_INITIAL_DDA);
 398         tegra_plane_writel(plane, v_dda, DC_WIN_V_INITIAL_DDA);
 399
 400         tegra_plane_writel(plane, 0, DC_WIN_UV_BUF_STRIDE);
 401         tegra_plane_writel(plane, 0, DC_WIN_BUF_STRIDE);
 402
 403         tegra_plane_writel(plane, window->base[0], DC_WINBUF_START_ADDR);
 404
 405         if (yuv && planar) {
 406                 tegra_plane_writel(plane, window->base[1], DC_WINBUF_START_ADDR_U);
 407                 tegra_plane_writel(plane, window->base[2], DC_WINBUF_START_ADDR_V);
 408                 value = window->stride[1] << 16 | window->stride[0];
 409                 tegra_plane_writel(plane, value, DC_WIN_LINE_STRIDE);
 410         } else {
 411                 tegra_plane_writel(plane, window->stride[0], DC_WIN_LINE_STRIDE);
 412         }
 413
 414         tegra_plane_writel(plane, h_offset, DC_WINBUF_ADDR_H_OFFSET);
 415         tegra_plane_writel(plane, v_offset, DC_WINBUF_ADDR_V_OFFSET);
 416
 417         if (dc->soc->supports_block_linear) {
 418                 unsigned long height = window->tiling.value;
 419
 420                 switch (window->tiling.mode) {
 421                 case TEGRA_BO_TILING_MODE_PITCH:
 422                         value = DC_WINBUF_SURFACE_KIND_PITCH;
 423                         break;
 424
 425                 case TEGRA_BO_TILING_MODE_TILED:
 426                         value = DC_WINBUF_SURFACE_KIND_TILED;
 427                         break;
 428
 429                 case TEGRA_BO_TILING_MODE_BLOCK:
 430                         value = DC_WINBUF_SURFACE_KIND_BLOCK_HEIGHT(height) |
 431                                 DC_WINBUF_SURFACE_KIND_BLOCK;
 432                         break;
 433                 }
 434
 435                 tegra_plane_writel(plane, value, DC_WINBUF_SURFACE_KIND);
 436         } else {
 437                 switch (window->tiling.mode) {
 438                 case TEGRA_BO_TILING_MODE_PITCH:
 439                         value = DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV |
 440                                 DC_WIN_BUFFER_ADDR_MODE_LINEAR;
 441                         break;
 442
 443                 case TEGRA_BO_TILING_MODE_TILED:
 444                         value = DC_WIN_BUFFER_ADDR_MODE_TILE_UV |
 445                                 DC_WIN_BUFFER_ADDR_MODE_TILE;
 446                         break;
 447
 448                 case TEGRA_BO_TILING_MODE_BLOCK:
 449                         /*
 450                          * No need to handle this here because ->atomic_check
 451                          * will already have filtered it out.
 452                          */
 453                         break;
 454                 }
 455
 456                 tegra_plane_writel(plane, value, DC_WIN_BUFFER_ADDR_MODE);
 457         }
 458
 459         value = WIN_ENABLE;
 460
 461         if (yuv) {
 462                 /* setup default colorspace conversion coefficients */
 463                 tegra_plane_writel(plane, 0x00f0, DC_WIN_CSC_YOF);
 464                 tegra_plane_writel(plane, 0x012a, DC_WIN_CSC_KYRGB);
 465                 tegra_plane_writel(plane, 0x0000, DC_WIN_CSC_KUR);
 466                 tegra_plane_writel(plane, 0x0198, DC_WIN_CSC_KVR);
 467                 tegra_plane_writel(plane, 0x039b, DC_WIN_CSC_KUG);
 468                 tegra_plane_writel(plane, 0x032f, DC_WIN_CSC_KVG);
 469                 tegra_plane_writel(plane, 0x0204, DC_WIN_CSC_KUB);
 470                 tegra_plane_writel(plane, 0x0000, DC_WIN_CSC_KVB);
 471
 472                 value |= CSC_ENABLE;
 473         } else if (window->bits_per_pixel < 24) {
 474                 value |= COLOR_EXPAND;
 475         }
 476
 477         if (window->reflect_x)
 478                 value |= H_DIRECTION;
 479
 480         if (window->reflect_y)
 481                 value |= V_DIRECTION;
 482
 483         if (tegra_plane_use_horizontal_filtering(plane, window)) {
 484                 /*
 485                  * Enable horizontal 6-tap filter and set filtering
 486                  * coefficients to the default values defined in TRM.
 487                  */
 488                 tegra_plane_writel(plane, 0x00008000, DC_WIN_H_FILTER_P(0));
 489                 tegra_plane_writel(plane, 0x3e087ce1, DC_WIN_H_FILTER_P(1));
 490                 tegra_plane_writel(plane, 0x3b117ac1, DC_WIN_H_FILTER_P(2));
 491                 tegra_plane_writel(plane, 0x591b73aa, DC_WIN_H_FILTER_P(3));
 492                 tegra_plane_writel(plane, 0x57256d9a, DC_WIN_H_FILTER_P(4));
 493                 tegra_plane_writel(plane, 0x552f668b, DC_WIN_H_FILTER_P(5));
 494                 tegra_plane_writel(plane, 0x73385e8b, DC_WIN_H_FILTER_P(6));
 495                 tegra_plane_writel(plane, 0x72435583, DC_WIN_H_FILTER_P(7));
 496                 tegra_plane_writel(plane, 0x714c4c8b, DC_WIN_H_FILTER_P(8));
 497                 tegra_plane_writel(plane, 0x70554393, DC_WIN_H_FILTER_P(9));
 498                 tegra_plane_writel(plane, 0x715e389b, DC_WIN_H_FILTER_P(10));
 499                 tegra_plane_writel(plane, 0x71662faa, DC_WIN_H_FILTER_P(11));
 500                 tegra_plane_writel(plane, 0x536d25ba, DC_WIN_H_FILTER_P(12));
 501                 tegra_plane_writel(plane, 0x55731bca, DC_WIN_H_FILTER_P(13));
 502                 tegra_plane_writel(plane, 0x387a11d9, DC_WIN_H_FILTER_P(14));
 503                 tegra_plane_writel(plane, 0x3c7c08f1, DC_WIN_H_FILTER_P(15));
 504
 505                 value |= H_FILTER;
 506         }
 507
 508         if (tegra_plane_use_vertical_filtering(plane, window)) {
 509                 unsigned int i, k;
 510
 511                 /*
 512                  * Enable vertical 2-tap filter and set filtering
 513                  * coefficients to the default values defined in TRM.
 514                  */
 515                 for (i = 0, k = 128; i < 16; i++, k -= 8)
 516                         tegra_plane_writel(plane, k, DC_WIN_V_FILTER_P(i));
 517
 518                 value |= V_FILTER;
 519         }
 520
 521         tegra_plane_writel(plane, value, DC_WIN_WIN_OPTIONS);
 522
 523         if (dc->soc->has_legacy_blending)
 524                 tegra_plane_setup_blending_legacy(plane);
 525         else
 526                 tegra_plane_setup_blending(plane, window);
 527 }
 528
 529 static const u32 tegra20_primary_formats[] = {
 530         DRM_FORMAT_ARGB4444,
 531         DRM_FORMAT_ARGB1555,
 532         DRM_FORMAT_RGB565,
 533         DRM_FORMAT_RGBA5551,
 534         DRM_FORMAT_ABGR8888,
 535         DRM_FORMAT_ARGB8888,
 536         /* non-native formats */
 537         DRM_FORMAT_XRGB1555,
 538         DRM_FORMAT_RGBX5551,
 539         DRM_FORMAT_XBGR8888,
 540         DRM_FORMAT_XRGB8888,
 541 };
 542
 543 static const u64 tegra20_modifiers[] = {
 544         DRM_FORMAT_MOD_LINEAR,
 545         DRM_FORMAT_MOD_NVIDIA_TEGRA_TILED,
 546         DRM_FORMAT_MOD_INVALID
 547 };
 548
 549 static const u32 tegra114_primary_formats[] = {
 550         DRM_FORMAT_ARGB4444,
 551         DRM_FORMAT_ARGB1555,
 552         DRM_FORMAT_RGB565,
 553         DRM_FORMAT_RGBA5551,
 554         DRM_FORMAT_ABGR8888,
 555         DRM_FORMAT_ARGB8888,
 556         /* new on Tegra114 */
 557         DRM_FORMAT_ABGR4444,
 558         DRM_FORMAT_ABGR1555,
 559         DRM_FORMAT_BGRA5551,
 560         DRM_FORMAT_XRGB1555,
 561         DRM_FORMAT_RGBX5551,
 562         DRM_FORMAT_XBGR1555,
 563         DRM_FORMAT_BGRX5551,
 564         DRM_FORMAT_BGR565,
 565         DRM_FORMAT_BGRA8888,
 566         DRM_FORMAT_RGBA8888,
 567         DRM_FORMAT_XRGB8888,
 568         DRM_FORMAT_XBGR8888,
 569 };
 570
 571 static const u32 tegra124_primary_formats[] = {
 572         DRM_FORMAT_ARGB4444,
 573         DRM_FORMAT_ARGB1555,
 574         DRM_FORMAT_RGB565,
 575         DRM_FORMAT_RGBA5551,
 576         DRM_FORMAT_ABGR8888,
 577         DRM_FORMAT_ARGB8888,
 578         /* new on Tegra114 */
 579         DRM_FORMAT_ABGR4444,
 580         DRM_FORMAT_ABGR1555,
 581         DRM_FORMAT_BGRA5551,
 582         DRM_FORMAT_XRGB1555,
 583         DRM_FORMAT_RGBX5551,
 584         DRM_FORMAT_XBGR1555,
 585         DRM_FORMAT_BGRX5551,
 586         DRM_FORMAT_BGR565,
 587         DRM_FORMAT_BGRA8888,
 588         DRM_FORMAT_RGBA8888,
 589         DRM_FORMAT_XRGB8888,
 590         DRM_FORMAT_XBGR8888,
 591         /* new on Tegra124 */
 592         DRM_FORMAT_RGBX8888,
 593         DRM_FORMAT_BGRX8888,
 594 };
 595
 596 static const u64 tegra124_modifiers[] = {
 597         DRM_FORMAT_MOD_LINEAR,
 598         DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(0),
 599         DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(1),
 600         DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(2),
 601         DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(3),
 602         DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(4),
 603         DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(5),
 604         DRM_FORMAT_MOD_INVALID
 605 };
 606
 607 static int tegra_plane_atomic_check(struct drm_plane *plane,
 608                                     struct drm_atomic_state *state)
 609 {
 610         struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state,
 611                                                                                  plane);
 612         struct tegra_plane_state *plane_state = to_tegra_plane_state(new_plane_state);
 613         unsigned int supported_rotation = DRM_MODE_ROTATE_0 |
 614                                           DRM_MODE_REFLECT_X |
 615                                           DRM_MODE_REFLECT_Y;
 616         unsigned int rotation = new_plane_state->rotation;
 617         struct tegra_bo_tiling *tiling = &plane_state->tiling;
 618         struct tegra_plane *tegra = to_tegra_plane(plane);
 619         struct tegra_dc *dc = to_tegra_dc(new_plane_state->crtc);
 620         int err;
 621
 622         plane_state->peak_memory_bandwidth = 0;
 623         plane_state->avg_memory_bandwidth = 0;
 624
 625         /* no need for further checks if the plane is being disabled */
 626         if (!new_plane_state->crtc) {
 627                 plane_state->total_peak_memory_bandwidth = 0;
 628                 return 0;
 629         }
 630
 631         err = tegra_plane_format(new_plane_state->fb->format->format,
 632                                  &plane_state->format,
 633                                  &plane_state->swap);
 634         if (err < 0)
 635                 return err;
 636
 637         /*
 638          * Tegra20 and Tegra30 are special cases here because they support
 639          * only variants of specific formats with an alpha component, but not
 640          * the corresponding opaque formats. However, the opaque formats can
 641          * be emulated by disabling alpha blending for the plane.
 642          */
 643         if (dc->soc->has_legacy_blending) {
 644                 err = tegra_plane_setup_legacy_state(tegra, plane_state);
 645                 if (err < 0)
 646                         return err;
 647         }
 648
 649         err = tegra_fb_get_tiling(new_plane_state->fb, tiling);
 650         if (err < 0)
 651                 return err;
 652
 653         if (tiling->mode == TEGRA_BO_TILING_MODE_BLOCK &&
 654             !dc->soc->supports_block_linear) {
 655                 DRM_ERROR("hardware doesn't support block linear mode\n");
 656                 return -EINVAL;
 657         }
 658
 659         /*
 660          * Older userspace used custom BO flag in order to specify the Y
 661          * reflection, while modern userspace uses the generic DRM rotation
 662          * property in order to achieve the same result.  The legacy BO flag
 663          * duplicates the DRM rotation property when both are set.
 664          */
 665         if (tegra_fb_is_bottom_up(new_plane_state->fb))
 666                 rotation |= DRM_MODE_REFLECT_Y;
 667
 668         rotation = drm_rotation_simplify(rotation, supported_rotation);
 669
 670         if (rotation & DRM_MODE_REFLECT_X)
 671                 plane_state->reflect_x = true;
 672         else
 673                 plane_state->reflect_x = false;
 674
 675         if (rotation & DRM_MODE_REFLECT_Y)
 676                 plane_state->reflect_y = true;
 677         else
 678                 plane_state->reflect_y = false;
 679
 680         /*
 681          * Tegra doesn't support different strides for U and V planes so we
 682          * error out if the user tries to display a framebuffer with such a
 683          * configuration.
 684          */
 685         if (new_plane_state->fb->format->num_planes > 2) {
 686                 if (new_plane_state->fb->pitches[2] != new_plane_state->fb->pitches[1]) {
 687                         DRM_ERROR("unsupported UV-plane configuration\n");
 688                         return -EINVAL;
 689                 }
 690         }
 691
 692         err = tegra_plane_state_add(tegra, new_plane_state);
 693         if (err < 0)
 694                 return err;
 695
 696         return 0;
 697 }
 698
 699 static void tegra_plane_atomic_disable(struct drm_plane *plane,
 700                                        struct drm_atomic_state *state)
 701 {
 702         struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state,
 703                                                                            plane);
 704         struct tegra_plane *p = to_tegra_plane(plane);
 705         u32 value;
 706
 707         /* rien ne va plus */
 708         if (!old_state || !old_state->crtc)
 709                 return;
 710
 711         value = tegra_plane_readl(p, DC_WIN_WIN_OPTIONS);
 712         value &= ~WIN_ENABLE;
 713         tegra_plane_writel(p, value, DC_WIN_WIN_OPTIONS);
 714 }
 715
 716 static void tegra_plane_atomic_update(struct drm_plane *plane,
 717                                       struct drm_atomic_state *state)
 718 {
 719         struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state,
 720                                                                            plane);
 721         struct tegra_plane_state *tegra_plane_state = to_tegra_plane_state(new_state);
 722         struct drm_framebuffer *fb = new_state->fb;
 723         struct tegra_plane *p = to_tegra_plane(plane);
 724         struct tegra_dc_window window;
 725         unsigned int i;
 726
 727         /* rien ne va plus */
 728         if (!new_state->crtc || !new_state->fb)
 729                 return;
 730
 731         if (!new_state->visible)
 732                 return tegra_plane_atomic_disable(plane, state);
 733
 734         memset(&window, 0, sizeof(window));
 735         window.src.x = new_state->src.x1 >> 16;
 736         window.src.y = new_state->src.y1 >> 16;
 737         window.src.w = drm_rect_width(&new_state->src) >> 16;
 738         window.src.h = drm_rect_height(&new_state->src) >> 16;
 739         window.dst.x = new_state->dst.x1;
 740         window.dst.y = new_state->dst.y1;
 741         window.dst.w = drm_rect_width(&new_state->dst);
 742         window.dst.h = drm_rect_height(&new_state->dst);
 743         window.bits_per_pixel = fb->format->cpp[0] * 8;
 744         window.reflect_x = tegra_plane_state->reflect_x;
 745         window.reflect_y = tegra_plane_state->reflect_y;
 746
 747         /* copy from state */
 748         window.zpos = new_state->normalized_zpos;
 749         window.tiling = tegra_plane_state->tiling;
 750         window.format = tegra_plane_state->format;
 751         window.swap = tegra_plane_state->swap;
 752
 753         for (i = 0; i < fb->format->num_planes; i++) {
 754                 window.base[i] = tegra_plane_state->iova[i] + fb->offsets[i];
 755
 756                 /*
 757                  * Tegra uses a shared stride for UV planes. Framebuffers are
 758                  * already checked for this in the tegra_plane_atomic_check()
 759                  * function, so it's safe to ignore the V-plane pitch here.
 760                  */
 761                 if (i < 2)
 762                         window.stride[i] = fb->pitches[i];
 763         }
 764
 765         tegra_dc_setup_window(p, &window);
 766 }
 767
 768 static const struct drm_plane_helper_funcs tegra_plane_helper_funcs = {
 769         .prepare_fb = tegra_plane_prepare_fb,
 770         .cleanup_fb = tegra_plane_cleanup_fb,
 771         .atomic_check = tegra_plane_atomic_check,
 772         .atomic_disable = tegra_plane_atomic_disable,
 773         .atomic_update = tegra_plane_atomic_update,
 774 };
 775
 776 static unsigned long tegra_plane_get_possible_crtcs(struct drm_device *drm)
 777 {
 778         /*
 779          * Ideally this would use drm_crtc_mask(), but that would require the
 780          * CRTC to already be in the mode_config's list of CRTCs. However, it
 781          * will only be added to that list in the drm_crtc_init_with_planes()
 782          * (in tegra_dc_init()), which in turn requires registration of these
 783          * planes. So we have ourselves a nice little chicken and egg problem
 784          * here.
 785          *
 786          * We work around this by manually creating the mask from the number
 787          * of CRTCs that have been registered, and should therefore always be
 788          * the same as drm_crtc_index() after registration.
 789          */
 790         return 1 << drm->mode_config.num_crtc;
 791 }
 792
 793 static struct drm_plane *tegra_primary_plane_create(struct drm_device *drm,
 794                                                     struct tegra_dc *dc)
 795 {
 796         unsigned long possible_crtcs = tegra_plane_get_possible_crtcs(drm);
 797         enum drm_plane_type type = DRM_PLANE_TYPE_PRIMARY;
 798         struct tegra_plane *plane;
 799         unsigned int num_formats;
 800         const u64 *modifiers;
 801         const u32 *formats;
 802         int err;
 803
 804         plane = kzalloc(sizeof(*plane), GFP_KERNEL);
 805         if (!plane)
 806                 return ERR_PTR(-ENOMEM);
 807
 808         /* Always use window A as primary window */
 809         plane->offset = 0xa00;
 810         plane->index = 0;
 811         plane->dc = dc;
 812
 813         num_formats = dc->soc->num_primary_formats;
 814         formats = dc->soc->primary_formats;
 815         modifiers = dc->soc->modifiers;
 816
 817         err = tegra_plane_interconnect_init(plane);
 818         if (err) {
 819                 kfree(plane);
 820                 return ERR_PTR(err);
 821         }
 822
 823         err = drm_universal_plane_init(drm, &plane->base, possible_crtcs,
 824                                        &tegra_plane_funcs, formats,
 825                                        num_formats, modifiers, type, NULL);
 826         if (err < 0) {
 827                 kfree(plane);
 828                 return ERR_PTR(err);
 829         }
 830
 831         drm_plane_helper_add(&plane->base, &tegra_plane_helper_funcs);
 832         drm_plane_create_zpos_property(&plane->base, plane->index, 0, 255);
 833
 834         err = drm_plane_create_rotation_property(&plane->base,
 835                                                  DRM_MODE_ROTATE_0,
 836                                                  DRM_MODE_ROTATE_0 |
 837                                                  DRM_MODE_ROTATE_180 |
 838                                                  DRM_MODE_REFLECT_X |
 839                                                  DRM_MODE_REFLECT_Y);
 840         if (err < 0)
 841                 dev_err(dc->dev, "failed to create rotation property: %d\n",
 842                         err);
 843
 844         return &plane->base;
 845 }
 846
 847 static const u32 tegra_legacy_cursor_plane_formats[] = {
 848         DRM_FORMAT_RGBA8888,
 849 };
 850
 851 static const u32 tegra_cursor_plane_formats[] = {
 852         DRM_FORMAT_ARGB8888,
 853 };
 854
 855 static int tegra_cursor_atomic_check(struct drm_plane *plane,
 856                                      struct drm_atomic_state *state)
 857 {
 858         struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state,
 859                                                                                  plane);
 860         struct tegra_plane_state *plane_state = to_tegra_plane_state(new_plane_state);
 861         struct tegra_plane *tegra = to_tegra_plane(plane);
 862         int err;
 863
 864         plane_state->peak_memory_bandwidth = 0;
 865         plane_state->avg_memory_bandwidth = 0;
 866
 867         /* no need for further checks if the plane is being disabled */
 868         if (!new_plane_state->crtc) {
 869                 plane_state->total_peak_memory_bandwidth = 0;
 870                 return 0;
 871         }
 872
 873         /* scaling not supported for cursor */
 874         if ((new_plane_state->src_w >> 16 != new_plane_state->crtc_w) ||
 875             (new_plane_state->src_h >> 16 != new_plane_state->crtc_h))
 876                 return -EINVAL;
 877
 878         /* only square cursors supported */
 879         if (new_plane_state->src_w != new_plane_state->src_h)
 880                 return -EINVAL;
 881
 882         if (new_plane_state->crtc_w != 32 && new_plane_state->crtc_w != 64 &&
 883             new_plane_state->crtc_w != 128 && new_plane_state->crtc_w != 256)
 884                 return -EINVAL;
 885
 886         err = tegra_plane_state_add(tegra, new_plane_state);
 887         if (err < 0)
 888                 return err;
 889
 890         return 0;
 891 }
 892
 893 static void tegra_cursor_atomic_update(struct drm_plane *plane,
 894                                        struct drm_atomic_state *state)
 895 {
 896         struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state,
 897                                                                            plane);
 898         struct tegra_plane_state *tegra_plane_state = to_tegra_plane_state(new_state);
 899         struct tegra_dc *dc = to_tegra_dc(new_state->crtc);
 900         struct tegra_drm *tegra = plane->dev->dev_private;
 901 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
 902         u64 dma_mask = *dc->dev->dma_mask;
 903 #endif
 904         unsigned int x, y;
 905         u32 value = 0;
 906
 907         /* rien ne va plus */
 908         if (!new_state->crtc || !new_state->fb)
 909                 return;
 910
 911         /*
 912          * Legacy display supports hardware clipping of the cursor, but
 913          * nvdisplay relies on software to clip the cursor to the screen.
 914          */
 915         if (!dc->soc->has_nvdisplay)
 916                 value |= CURSOR_CLIP_DISPLAY;
 917
 918         switch (new_state->crtc_w) {
 919         case 32:
 920                 value |= CURSOR_SIZE_32x32;
 921                 break;
 922
 923         case 64:
 924                 value |= CURSOR_SIZE_64x64;
 925                 break;
 926
 927         case 128:
 928                 value |= CURSOR_SIZE_128x128;
 929                 break;
 930
 931         case 256:
 932                 value |= CURSOR_SIZE_256x256;
 933                 break;
 934
 935         default:
 936                 WARN(1, "cursor size %ux%u not supported\n",
 937                      new_state->crtc_w, new_state->crtc_h);
 938                 return;
 939         }
 940
 941         value |= (tegra_plane_state->iova[0] >> 10) & 0x3fffff;
 942         tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR);
 943
 944 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
 945         value = (tegra_plane_state->iova[0] >> 32) & (dma_mask >> 32);
 946         tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR_HI);
 947 #endif
 948
 949         /* enable cursor and set blend mode */
 950         value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
 951         value |= CURSOR_ENABLE;
 952         tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
 953
 954         value = tegra_dc_readl(dc, DC_DISP_BLEND_CURSOR_CONTROL);
 955         value &= ~CURSOR_DST_BLEND_MASK;
 956         value &= ~CURSOR_SRC_BLEND_MASK;
 957
 958         if (dc->soc->has_nvdisplay)
 959                 value &= ~CURSOR_COMPOSITION_MODE_XOR;
 960         else
 961                 value |= CURSOR_MODE_NORMAL;
 962
 963         value |= CURSOR_DST_BLEND_NEG_K1_TIMES_SRC;
 964         value |= CURSOR_SRC_BLEND_K1_TIMES_SRC;
 965         value |= CURSOR_ALPHA;
 966         tegra_dc_writel(dc, value, DC_DISP_BLEND_CURSOR_CONTROL);
 967
 968         /* nvdisplay relies on software for clipping */
 969         if (dc->soc->has_nvdisplay) {
 970                 struct drm_rect src;
 971
 972                 x = new_state->dst.x1;
 973                 y = new_state->dst.y1;
 974
 975                 drm_rect_fp_to_int(&src, &new_state->src);
 976
 977                 value = (src.y1 & tegra->vmask) << 16 | (src.x1 & tegra->hmask);
 978                 tegra_dc_writel(dc, value, DC_DISP_PCALC_HEAD_SET_CROPPED_POINT_IN_CURSOR);
 979
 980                 value = (drm_rect_height(&src) & tegra->vmask) << 16 |
 981                         (drm_rect_width(&src) & tegra->hmask);
 982                 tegra_dc_writel(dc, value, DC_DISP_PCALC_HEAD_SET_CROPPED_SIZE_IN_CURSOR);
 983         } else {
 984                 x = new_state->crtc_x;
 985                 y = new_state->crtc_y;
 986         }
 987
 988         /* position the cursor */
 989         value = ((y & tegra->vmask) << 16) | (x & tegra->hmask);
 990         tegra_dc_writel(dc, value, DC_DISP_CURSOR_POSITION);
 991 }
 992
 993 static void tegra_cursor_atomic_disable(struct drm_plane *plane,
 994                                         struct drm_atomic_state *state)
 995 {
 996         struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state,
 997                                                                            plane);
 998         struct tegra_dc *dc;
 999         u32 value;
1000
1001         /* rien ne va plus */
1002         if (!old_state || !old_state->crtc)
1003                 return;
1004
1005         dc = to_tegra_dc(old_state->crtc);
1006
1007         value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
1008         value &= ~CURSOR_ENABLE;
1009         tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
1010 }
1011
1012 static const struct drm_plane_helper_funcs tegra_cursor_plane_helper_funcs = {
1013         .prepare_fb = tegra_plane_prepare_fb,
1014         .cleanup_fb = tegra_plane_cleanup_fb,
1015         .atomic_check = tegra_cursor_atomic_check,
1016         .atomic_update = tegra_cursor_atomic_update,
1017         .atomic_disable = tegra_cursor_atomic_disable,
1018 };
1019
1020 static const uint64_t linear_modifiers[] = {
1021         DRM_FORMAT_MOD_LINEAR,
1022         DRM_FORMAT_MOD_INVALID
1023 };
1024
1025 static struct drm_plane *tegra_dc_cursor_plane_create(struct drm_device *drm,
1026                                                       struct tegra_dc *dc)
1027 {
1028         unsigned long possible_crtcs = tegra_plane_get_possible_crtcs(drm);
1029         struct tegra_plane *plane;
1030         unsigned int num_formats;
1031         const u32 *formats;
1032         int err;
1033
1034         plane = kzalloc(sizeof(*plane), GFP_KERNEL);
1035         if (!plane)
1036                 return ERR_PTR(-ENOMEM);
1037
1038         /*
1039          * This index is kind of fake. The cursor isn't a regular plane, but
1040          * its update and activation request bits in DC_CMD_STATE_CONTROL do
1041          * use the same programming. Setting this fake index here allows the
1042          * code in tegra_add_plane_state() to do the right thing without the
1043          * need to special-casing the cursor plane.
1044          */
1045         plane->index = 6;
1046         plane->dc = dc;
1047
1048         if (!dc->soc->has_nvdisplay) {
1049                 num_formats = ARRAY_SIZE(tegra_legacy_cursor_plane_formats);
1050                 formats = tegra_legacy_cursor_plane_formats;
1051
1052                 err = tegra_plane_interconnect_init(plane);
1053                 if (err) {
1054                         kfree(plane);
1055                         return ERR_PTR(err);
1056                 }
1057         } else {
1058                 num_formats = ARRAY_SIZE(tegra_cursor_plane_formats);
1059                 formats = tegra_cursor_plane_formats;
1060         }
1061
1062         err = drm_universal_plane_init(drm, &plane->base, possible_crtcs,
1063                                        &tegra_plane_funcs, formats,
1064                                        num_formats, linear_modifiers,
1065                                        DRM_PLANE_TYPE_CURSOR, NULL);
1066         if (err < 0) {
1067                 kfree(plane);
1068                 return ERR_PTR(err);
1069         }
1070
1071         drm_plane_helper_add(&plane->base, &tegra_cursor_plane_helper_funcs);
1072         drm_plane_create_zpos_immutable_property(&plane->base, 255);
1073
1074         return &plane->base;
1075 }
1076
1077 static const u32 tegra20_overlay_formats[] = {
1078         DRM_FORMAT_ARGB4444,
1079         DRM_FORMAT_ARGB1555,
1080         DRM_FORMAT_RGB565,
1081         DRM_FORMAT_RGBA5551,
1082         DRM_FORMAT_ABGR8888,
1083         DRM_FORMAT_ARGB8888,
1084         /* non-native formats */
1085         DRM_FORMAT_XRGB1555,
1086         DRM_FORMAT_RGBX5551,
1087         DRM_FORMAT_XBGR8888,
1088         DRM_FORMAT_XRGB8888,
1089         /* planar formats */
1090         DRM_FORMAT_UYVY,
1091         DRM_FORMAT_YUYV,
1092         DRM_FORMAT_YUV420,
1093         DRM_FORMAT_YUV422,
1094 };
1095
1096 static const u32 tegra114_overlay_formats[] = {
1097         DRM_FORMAT_ARGB4444,
1098         DRM_FORMAT_ARGB1555,
1099         DRM_FORMAT_RGB565,
1100         DRM_FORMAT_RGBA5551,
1101         DRM_FORMAT_ABGR8888,
1102         DRM_FORMAT_ARGB8888,
1103         /* new on Tegra114 */
1104         DRM_FORMAT_ABGR4444,
1105         DRM_FORMAT_ABGR1555,
1106         DRM_FORMAT_BGRA5551,
1107         DRM_FORMAT_XRGB1555,
1108         DRM_FORMAT_RGBX5551,
1109         DRM_FORMAT_XBGR1555,
1110         DRM_FORMAT_BGRX5551,
1111         DRM_FORMAT_BGR565,
1112         DRM_FORMAT_BGRA8888,
1113         DRM_FORMAT_RGBA8888,
1114         DRM_FORMAT_XRGB8888,
1115         DRM_FORMAT_XBGR8888,
1116         /* planar formats */
1117         DRM_FORMAT_UYVY,
1118         DRM_FORMAT_YUYV,
1119         DRM_FORMAT_YUV420,
1120         DRM_FORMAT_YUV422,
1121 };
1122
1123 static const u32 tegra124_overlay_formats[] = {
1124         DRM_FORMAT_ARGB4444,
1125         DRM_FORMAT_ARGB1555,
1126         DRM_FORMAT_RGB565,
1127         DRM_FORMAT_RGBA5551,
1128         DRM_FORMAT_ABGR8888,
1129         DRM_FORMAT_ARGB8888,
1130         /* new on Tegra114 */
1131         DRM_FORMAT_ABGR4444,
1132         DRM_FORMAT_ABGR1555,
1133         DRM_FORMAT_BGRA5551,
1134         DRM_FORMAT_XRGB1555,
1135         DRM_FORMAT_RGBX5551,
1136         DRM_FORMAT_XBGR1555,
1137         DRM_FORMAT_BGRX5551,
1138         DRM_FORMAT_BGR565,
1139         DRM_FORMAT_BGRA8888,
1140         DRM_FORMAT_RGBA8888,
1141         DRM_FORMAT_XRGB8888,
1142         DRM_FORMAT_XBGR8888,
1143         /* new on Tegra124 */
1144         DRM_FORMAT_RGBX8888,
1145         DRM_FORMAT_BGRX8888,
1146         /* planar formats */
1147         DRM_FORMAT_UYVY,
1148         DRM_FORMAT_YUYV,
1149         DRM_FORMAT_YUV420,
1150         DRM_FORMAT_YUV422,
1151 };
1152
1153 static struct drm_plane *tegra_dc_overlay_plane_create(struct drm_device *drm,
1154                                                        struct tegra_dc *dc,
1155                                                        unsigned int index,
1156                                                        bool cursor)
1157 {
1158         unsigned long possible_crtcs = tegra_plane_get_possible_crtcs(drm);
1159         struct tegra_plane *plane;
1160         unsigned int num_formats;
1161         enum drm_plane_type type;
1162         const u32 *formats;
1163         int err;
1164
1165         plane = kzalloc(sizeof(*plane), GFP_KERNEL);
1166         if (!plane)
1167                 return ERR_PTR(-ENOMEM);
1168
1169         plane->offset = 0xa00 + 0x200 * index;
1170         plane->index = index;
1171         plane->dc = dc;
1172
1173         num_formats = dc->soc->num_overlay_formats;
1174         formats = dc->soc->overlay_formats;
1175
1176         err = tegra_plane_interconnect_init(plane);
1177         if (err) {
1178                 kfree(plane);
1179                 return ERR_PTR(err);
1180         }
1181
1182         if (!cursor)
1183                 type = DRM_PLANE_TYPE_OVERLAY;
1184         else
1185                 type = DRM_PLANE_TYPE_CURSOR;
1186
1187         err = drm_universal_plane_init(drm, &plane->base, possible_crtcs,
1188                                        &tegra_plane_funcs, formats,
1189                                        num_formats, linear_modifiers,
1190                                        type, NULL);
1191         if (err < 0) {
1192                 kfree(plane);
1193                 return ERR_PTR(err);
1194         }
1195
1196         drm_plane_helper_add(&plane->base, &tegra_plane_helper_funcs);
1197         drm_plane_create_zpos_property(&plane->base, plane->index, 0, 255);
1198
1199         err = drm_plane_create_rotation_property(&plane->base,
1200                                                  DRM_MODE_ROTATE_0,
1201                                                  DRM_MODE_ROTATE_0 |
1202                                                  DRM_MODE_ROTATE_180 |
1203                                                  DRM_MODE_REFLECT_X |
1204                                                  DRM_MODE_REFLECT_Y);
1205         if (err < 0)
1206                 dev_err(dc->dev, "failed to create rotation property: %d\n",
1207                         err);
1208
1209         return &plane->base;
1210 }
1211
1212 static struct drm_plane *tegra_dc_add_shared_planes(struct drm_device *drm,
1213                                                     struct tegra_dc *dc)
1214 {
1215         struct drm_plane *plane, *primary = NULL;
1216         unsigned int i, j;
1217
1218         for (i = 0; i < dc->soc->num_wgrps; i++) {
1219                 const struct tegra_windowgroup_soc *wgrp = &dc->soc->wgrps[i];
1220
1221                 if (wgrp->dc == dc->pipe) {
1222                         for (j = 0; j < wgrp->num_windows; j++) {
1223                                 unsigned int index = wgrp->windows[j];
1224
1225                                 plane = tegra_shared_plane_create(drm, dc,
1226                                                                   wgrp->index,
1227                                                                   index);
1228                                 if (IS_ERR(plane))
1229                                         return plane;
1230
1231                                 /*
1232                                  * Choose the first shared plane owned by this
1233                                  * head as the primary plane.
1234                                  */
1235                                 if (!primary) {
1236                                         plane->type = DRM_PLANE_TYPE_PRIMARY;
1237                                         primary = plane;
1238                                 }
1239                         }
1240                 }
1241         }
1242
1243         return primary;
1244 }
1245
1246 static struct drm_plane *tegra_dc_add_planes(struct drm_device *drm,
1247                                              struct tegra_dc *dc)
1248 {
1249         struct drm_plane *planes[2], *primary;
1250         unsigned int planes_num;
1251         unsigned int i;
1252         int err;
1253
1254         primary = tegra_primary_plane_create(drm, dc);
1255         if (IS_ERR(primary))
1256                 return primary;
1257
1258         if (dc->soc->supports_cursor)
1259                 planes_num = 2;
1260         else
1261                 planes_num = 1;
1262
1263         for (i = 0; i < planes_num; i++) {
1264                 planes[i] = tegra_dc_overlay_plane_create(drm, dc, 1 + i,
1265                                                           false);
1266                 if (IS_ERR(planes[i])) {
1267                         err = PTR_ERR(planes[i]);
1268
1269                         while (i--)
1270                                 tegra_plane_funcs.destroy(planes[i]);
1271
1272                         tegra_plane_funcs.destroy(primary);
1273                         return ERR_PTR(err);
1274                 }
1275         }
1276
1277         return primary;
1278 }
1279
1280 static void tegra_dc_destroy(struct drm_crtc *crtc)
1281 {
1282         drm_crtc_cleanup(crtc);
1283 }
1284
1285 static void tegra_crtc_reset(struct drm_crtc *crtc)
1286 {
1287         struct tegra_dc_state *state = kzalloc(sizeof(*state), GFP_KERNEL);
1288
1289         if (crtc->state)
1290                 tegra_crtc_atomic_destroy_state(crtc, crtc->state);
1291
1292         __drm_atomic_helper_crtc_reset(crtc, &state->base);
1293 }
1294
1295 static struct drm_crtc_state *
1296 tegra_crtc_atomic_duplicate_state(struct drm_crtc *crtc)
1297 {
1298         struct tegra_dc_state *state = to_dc_state(crtc->state);
1299         struct tegra_dc_state *copy;
1300
1301         copy = kmalloc(sizeof(*copy), GFP_KERNEL);
1302         if (!copy)
1303                 return NULL;
1304
1305         __drm_atomic_helper_crtc_duplicate_state(crtc, &copy->base);
1306         copy->clk = state->clk;
1307         copy->pclk = state->pclk;
1308         copy->div = state->div;
1309         copy->planes = state->planes;
1310
1311         return &copy->base;
1312 }
1313
1314 static void tegra_crtc_atomic_destroy_state(struct drm_crtc *crtc,
1315                                             struct drm_crtc_state *state)
1316 {
1317         __drm_atomic_helper_crtc_destroy_state(state);
1318         kfree(state);
1319 }
1320
1321 #define DEBUGFS_REG32(_name) { .name = #_name, .offset = _name }
1322
1323 static const struct debugfs_reg32 tegra_dc_regs[] = {
1324         DEBUGFS_REG32(DC_CMD_GENERAL_INCR_SYNCPT),
1325         DEBUGFS_REG32(DC_CMD_GENERAL_INCR_SYNCPT_CNTRL),
1326         DEBUGFS_REG32(DC_CMD_GENERAL_INCR_SYNCPT_ERROR),
1327         DEBUGFS_REG32(DC_CMD_WIN_A_INCR_SYNCPT),
1328         DEBUGFS_REG32(DC_CMD_WIN_A_INCR_SYNCPT_CNTRL),
1329         DEBUGFS_REG32(DC_CMD_WIN_A_INCR_SYNCPT_ERROR),
1330         DEBUGFS_REG32(DC_CMD_WIN_B_INCR_SYNCPT),
1331         DEBUGFS_REG32(DC_CMD_WIN_B_INCR_SYNCPT_CNTRL),
1332         DEBUGFS_REG32(DC_CMD_WIN_B_INCR_SYNCPT_ERROR),
1333         DEBUGFS_REG32(DC_CMD_WIN_C_INCR_SYNCPT),
1334         DEBUGFS_REG32(DC_CMD_WIN_C_INCR_SYNCPT_CNTRL),
1335         DEBUGFS_REG32(DC_CMD_WIN_C_INCR_SYNCPT_ERROR),
1336         DEBUGFS_REG32(DC_CMD_CONT_SYNCPT_VSYNC),
1337         DEBUGFS_REG32(DC_CMD_DISPLAY_COMMAND_OPTION0),
1338         DEBUGFS_REG32(DC_CMD_DISPLAY_COMMAND),
1339         DEBUGFS_REG32(DC_CMD_SIGNAL_RAISE),
1340         DEBUGFS_REG32(DC_CMD_DISPLAY_POWER_CONTROL),
1341         DEBUGFS_REG32(DC_CMD_INT_STATUS),
1342         DEBUGFS_REG32(DC_CMD_INT_MASK),
1343         DEBUGFS_REG32(DC_CMD_INT_ENABLE),
1344         DEBUGFS_REG32(DC_CMD_INT_TYPE),
1345         DEBUGFS_REG32(DC_CMD_INT_POLARITY),
1346         DEBUGFS_REG32(DC_CMD_SIGNAL_RAISE1),
1347         DEBUGFS_REG32(DC_CMD_SIGNAL_RAISE2),
1348         DEBUGFS_REG32(DC_CMD_SIGNAL_RAISE3),
1349         DEBUGFS_REG32(DC_CMD_STATE_ACCESS),
1350         DEBUGFS_REG32(DC_CMD_STATE_CONTROL),
1351         DEBUGFS_REG32(DC_CMD_DISPLAY_WINDOW_HEADER),
1352         DEBUGFS_REG32(DC_CMD_REG_ACT_CONTROL),
1353         DEBUGFS_REG32(DC_COM_CRC_CONTROL),
1354         DEBUGFS_REG32(DC_COM_CRC_CHECKSUM),
1355         DEBUGFS_REG32(DC_COM_PIN_OUTPUT_ENABLE(0)),
1356         DEBUGFS_REG32(DC_COM_PIN_OUTPUT_ENABLE(1)),
1357         DEBUGFS_REG32(DC_COM_PIN_OUTPUT_ENABLE(2)),
1358         DEBUGFS_REG32(DC_COM_PIN_OUTPUT_ENABLE(3)),
1359         DEBUGFS_REG32(DC_COM_PIN_OUTPUT_POLARITY(0)),
1360         DEBUGFS_REG32(DC_COM_PIN_OUTPUT_POLARITY(1)),
1361         DEBUGFS_REG32(DC_COM_PIN_OUTPUT_POLARITY(2)),
1362         DEBUGFS_REG32(DC_COM_PIN_OUTPUT_POLARITY(3)),
1363         DEBUGFS_REG32(DC_COM_PIN_OUTPUT_DATA(0)),
1364         DEBUGFS_REG32(DC_COM_PIN_OUTPUT_DATA(1)),
1365         DEBUGFS_REG32(DC_COM_PIN_OUTPUT_DATA(2)),
1366         DEBUGFS_REG32(DC_COM_PIN_OUTPUT_DATA(3)),
1367         DEBUGFS_REG32(DC_COM_PIN_INPUT_ENABLE(0)),
1368         DEBUGFS_REG32(DC_COM_PIN_INPUT_ENABLE(1)),
1369         DEBUGFS_REG32(DC_COM_PIN_INPUT_ENABLE(2)),
1370         DEBUGFS_REG32(DC_COM_PIN_INPUT_ENABLE(3)),
1371         DEBUGFS_REG32(DC_COM_PIN_INPUT_DATA(0)),
1372         DEBUGFS_REG32(DC_COM_PIN_INPUT_DATA(1)),
1373         DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(0)),
1374         DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(1)),
1375         DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(2)),
1376         DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(3)),
1377         DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(4)),
1378         DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(5)),
1379         DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(6)),
1380         DEBUGFS_REG32(DC_COM_PIN_MISC_CONTROL),
1381         DEBUGFS_REG32(DC_COM_PIN_PM0_CONTROL),
1382         DEBUGFS_REG32(DC_COM_PIN_PM0_DUTY_CYCLE),
1383         DEBUGFS_REG32(DC_COM_PIN_PM1_CONTROL),
1384         DEBUGFS_REG32(DC_COM_PIN_PM1_DUTY_CYCLE),
1385         DEBUGFS_REG32(DC_COM_SPI_CONTROL),
1386         DEBUGFS_REG32(DC_COM_SPI_START_BYTE),
1387         DEBUGFS_REG32(DC_COM_HSPI_WRITE_DATA_AB),
1388         DEBUGFS_REG32(DC_COM_HSPI_WRITE_DATA_CD),
1389         DEBUGFS_REG32(DC_COM_HSPI_CS_DC),
1390         DEBUGFS_REG32(DC_COM_SCRATCH_REGISTER_A),
1391         DEBUGFS_REG32(DC_COM_SCRATCH_REGISTER_B),
1392         DEBUGFS_REG32(DC_COM_GPIO_CTRL),
1393         DEBUGFS_REG32(DC_COM_GPIO_DEBOUNCE_COUNTER),
1394         DEBUGFS_REG32(DC_COM_CRC_CHECKSUM_LATCHED),
1395         DEBUGFS_REG32(DC_DISP_DISP_SIGNAL_OPTIONS0),
1396         DEBUGFS_REG32(DC_DISP_DISP_SIGNAL_OPTIONS1),
1397         DEBUGFS_REG32(DC_DISP_DISP_WIN_OPTIONS),
1398         DEBUGFS_REG32(DC_DISP_DISP_MEM_HIGH_PRIORITY),
1399         DEBUGFS_REG32(DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER),
1400         DEBUGFS_REG32(DC_DISP_DISP_TIMING_OPTIONS),
1401         DEBUGFS_REG32(DC_DISP_REF_TO_SYNC),
1402         DEBUGFS_REG32(DC_DISP_SYNC_WIDTH),
1403         DEBUGFS_REG32(DC_DISP_BACK_PORCH),
1404         DEBUGFS_REG32(DC_DISP_ACTIVE),
1405         DEBUGFS_REG32(DC_DISP_FRONT_PORCH),
1406         DEBUGFS_REG32(DC_DISP_H_PULSE0_CONTROL),
1407         DEBUGFS_REG32(DC_DISP_H_PULSE0_POSITION_A),
1408         DEBUGFS_REG32(DC_DISP_H_PULSE0_POSITION_B),
1409         DEBUGFS_REG32(DC_DISP_H_PULSE0_POSITION_C),
1410         DEBUGFS_REG32(DC_DISP_H_PULSE0_POSITION_D),
1411         DEBUGFS_REG32(DC_DISP_H_PULSE1_CONTROL),
1412         DEBUGFS_REG32(DC_DISP_H_PULSE1_POSITION_A),
1413         DEBUGFS_REG32(DC_DISP_H_PULSE1_POSITION_B),
1414         DEBUGFS_REG32(DC_DISP_H_PULSE1_POSITION_C),
1415         DEBUGFS_REG32(DC_DISP_H_PULSE1_POSITION_D),
1416         DEBUGFS_REG32(DC_DISP_H_PULSE2_CONTROL),
1417         DEBUGFS_REG32(DC_DISP_H_PULSE2_POSITION_A),
1418         DEBUGFS_REG32(DC_DISP_H_PULSE2_POSITION_B),
1419         DEBUGFS_REG32(DC_DISP_H_PULSE2_POSITION_C),
1420         DEBUGFS_REG32(DC_DISP_H_PULSE2_POSITION_D),
1421         DEBUGFS_REG32(DC_DISP_V_PULSE0_CONTROL),
1422         DEBUGFS_REG32(DC_DISP_V_PULSE0_POSITION_A),
1423         DEBUGFS_REG32(DC_DISP_V_PULSE0_POSITION_B),
1424         DEBUGFS_REG32(DC_DISP_V_PULSE0_POSITION_C),
1425         DEBUGFS_REG32(DC_DISP_V_PULSE1_CONTROL),
1426         DEBUGFS_REG32(DC_DISP_V_PULSE1_POSITION_A),
1427         DEBUGFS_REG32(DC_DISP_V_PULSE1_POSITION_B),
1428         DEBUGFS_REG32(DC_DISP_V_PULSE1_POSITION_C),
1429         DEBUGFS_REG32(DC_DISP_V_PULSE2_CONTROL),
1430         DEBUGFS_REG32(DC_DISP_V_PULSE2_POSITION_A),
1431         DEBUGFS_REG32(DC_DISP_V_PULSE3_CONTROL),
1432         DEBUGFS_REG32(DC_DISP_V_PULSE3_POSITION_A),
1433         DEBUGFS_REG32(DC_DISP_M0_CONTROL),
1434         DEBUGFS_REG32(DC_DISP_M1_CONTROL),
1435         DEBUGFS_REG32(DC_DISP_DI_CONTROL),
1436         DEBUGFS_REG32(DC_DISP_PP_CONTROL),
1437         DEBUGFS_REG32(DC_DISP_PP_SELECT_A),
1438         DEBUGFS_REG32(DC_DISP_PP_SELECT_B),
1439         DEBUGFS_REG32(DC_DISP_PP_SELECT_C),
1440         DEBUGFS_REG32(DC_DISP_PP_SELECT_D),
1441         DEBUGFS_REG32(DC_DISP_DISP_CLOCK_CONTROL),
1442         DEBUGFS_REG32(DC_DISP_DISP_INTERFACE_CONTROL),
1443         DEBUGFS_REG32(DC_DISP_DISP_COLOR_CONTROL),
1444         DEBUGFS_REG32(DC_DISP_SHIFT_CLOCK_OPTIONS),
1445         DEBUGFS_REG32(DC_DISP_DATA_ENABLE_OPTIONS),
1446         DEBUGFS_REG32(DC_DISP_SERIAL_INTERFACE_OPTIONS),
1447         DEBUGFS_REG32(DC_DISP_LCD_SPI_OPTIONS),
1448         DEBUGFS_REG32(DC_DISP_BORDER_COLOR),
1449         DEBUGFS_REG32(DC_DISP_COLOR_KEY0_LOWER),
1450         DEBUGFS_REG32(DC_DISP_COLOR_KEY0_UPPER),
1451         DEBUGFS_REG32(DC_DISP_COLOR_KEY1_LOWER),
1452         DEBUGFS_REG32(DC_DISP_COLOR_KEY1_UPPER),
1453         DEBUGFS_REG32(DC_DISP_CURSOR_FOREGROUND),
1454         DEBUGFS_REG32(DC_DISP_CURSOR_BACKGROUND),
1455         DEBUGFS_REG32(DC_DISP_CURSOR_START_ADDR),
1456         DEBUGFS_REG32(DC_DISP_CURSOR_START_ADDR_NS),
1457         DEBUGFS_REG32(DC_DISP_CURSOR_POSITION),
1458         DEBUGFS_REG32(DC_DISP_CURSOR_POSITION_NS),
1459         DEBUGFS_REG32(DC_DISP_INIT_SEQ_CONTROL),
1460         DEBUGFS_REG32(DC_DISP_SPI_INIT_SEQ_DATA_A),
1461         DEBUGFS_REG32(DC_DISP_SPI_INIT_SEQ_DATA_B),
1462         DEBUGFS_REG32(DC_DISP_SPI_INIT_SEQ_DATA_C),
1463         DEBUGFS_REG32(DC_DISP_SPI_INIT_SEQ_DATA_D),
1464         DEBUGFS_REG32(DC_DISP_DC_MCCIF_FIFOCTRL),
1465         DEBUGFS_REG32(DC_DISP_MCCIF_DISPLAY0A_HYST),
1466         DEBUGFS_REG32(DC_DISP_MCCIF_DISPLAY0B_HYST),
1467         DEBUGFS_REG32(DC_DISP_MCCIF_DISPLAY1A_HYST),
1468         DEBUGFS_REG32(DC_DISP_MCCIF_DISPLAY1B_HYST),
1469         DEBUGFS_REG32(DC_DISP_DAC_CRT_CTRL),
1470         DEBUGFS_REG32(DC_DISP_DISP_MISC_CONTROL),
1471         DEBUGFS_REG32(DC_DISP_SD_CONTROL),
1472         DEBUGFS_REG32(DC_DISP_SD_CSC_COEFF),
1473         DEBUGFS_REG32(DC_DISP_SD_LUT(0)),
1474         DEBUGFS_REG32(DC_DISP_SD_LUT(1)),
1475         DEBUGFS_REG32(DC_DISP_SD_LUT(2)),
1476         DEBUGFS_REG32(DC_DISP_SD_LUT(3)),
1477         DEBUGFS_REG32(DC_DISP_SD_LUT(4)),
1478         DEBUGFS_REG32(DC_DISP_SD_LUT(5)),
1479         DEBUGFS_REG32(DC_DISP_SD_LUT(6)),
1480         DEBUGFS_REG32(DC_DISP_SD_LUT(7)),
1481         DEBUGFS_REG32(DC_DISP_SD_LUT(8)),
1482         DEBUGFS_REG32(DC_DISP_SD_FLICKER_CONTROL),
1483         DEBUGFS_REG32(DC_DISP_DC_PIXEL_COUNT),
1484         DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(0)),
1485         DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(1)),
1486         DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(2)),
1487         DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(3)),
1488         DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(4)),
1489         DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(5)),
1490         DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(6)),
1491         DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(7)),
1492         DEBUGFS_REG32(DC_DISP_SD_BL_TF(0)),
1493         DEBUGFS_REG32(DC_DISP_SD_BL_TF(1)),
1494         DEBUGFS_REG32(DC_DISP_SD_BL_TF(2)),
1495         DEBUGFS_REG32(DC_DISP_SD_BL_TF(3)),
1496         DEBUGFS_REG32(DC_DISP_SD_BL_CONTROL),
1497         DEBUGFS_REG32(DC_DISP_SD_HW_K_VALUES),
1498         DEBUGFS_REG32(DC_DISP_SD_MAN_K_VALUES),
1499         DEBUGFS_REG32(DC_DISP_CURSOR_START_ADDR_HI),
1500         DEBUGFS_REG32(DC_DISP_BLEND_CURSOR_CONTROL),
1501         DEBUGFS_REG32(DC_WIN_WIN_OPTIONS),
1502         DEBUGFS_REG32(DC_WIN_BYTE_SWAP),
1503         DEBUGFS_REG32(DC_WIN_BUFFER_CONTROL),
1504         DEBUGFS_REG32(DC_WIN_COLOR_DEPTH),
1505         DEBUGFS_REG32(DC_WIN_POSITION),
1506         DEBUGFS_REG32(DC_WIN_SIZE),
1507         DEBUGFS_REG32(DC_WIN_PRESCALED_SIZE),
1508         DEBUGFS_REG32(DC_WIN_H_INITIAL_DDA),
1509         DEBUGFS_REG32(DC_WIN_V_INITIAL_DDA),
1510         DEBUGFS_REG32(DC_WIN_DDA_INC),
1511         DEBUGFS_REG32(DC_WIN_LINE_STRIDE),
1512         DEBUGFS_REG32(DC_WIN_BUF_STRIDE),
1513         DEBUGFS_REG32(DC_WIN_UV_BUF_STRIDE),
1514         DEBUGFS_REG32(DC_WIN_BUFFER_ADDR_MODE),
1515         DEBUGFS_REG32(DC_WIN_DV_CONTROL),
1516         DEBUGFS_REG32(DC_WIN_BLEND_NOKEY),
1517         DEBUGFS_REG32(DC_WIN_BLEND_1WIN),
1518         DEBUGFS_REG32(DC_WIN_BLEND_2WIN_X),
1519         DEBUGFS_REG32(DC_WIN_BLEND_2WIN_Y),
1520         DEBUGFS_REG32(DC_WIN_BLEND_3WIN_XY),
1521         DEBUGFS_REG32(DC_WIN_HP_FETCH_CONTROL),
1522         DEBUGFS_REG32(DC_WINBUF_START_ADDR),
1523         DEBUGFS_REG32(DC_WINBUF_START_ADDR_NS),
1524         DEBUGFS_REG32(DC_WINBUF_START_ADDR_U),
1525         DEBUGFS_REG32(DC_WINBUF_START_ADDR_U_NS),
1526         DEBUGFS_REG32(DC_WINBUF_START_ADDR_V),
1527         DEBUGFS_REG32(DC_WINBUF_START_ADDR_V_NS),
1528         DEBUGFS_REG32(DC_WINBUF_ADDR_H_OFFSET),
1529         DEBUGFS_REG32(DC_WINBUF_ADDR_H_OFFSET_NS),
1530         DEBUGFS_REG32(DC_WINBUF_ADDR_V_OFFSET),
1531         DEBUGFS_REG32(DC_WINBUF_ADDR_V_OFFSET_NS),
1532         DEBUGFS_REG32(DC_WINBUF_UFLOW_STATUS),
1533         DEBUGFS_REG32(DC_WINBUF_AD_UFLOW_STATUS),
1534         DEBUGFS_REG32(DC_WINBUF_BD_UFLOW_STATUS),
1535         DEBUGFS_REG32(DC_WINBUF_CD_UFLOW_STATUS),
1536 };
1537
1538 static int tegra_dc_show_regs(struct seq_file *s, void *data)
1539 {
1540         struct drm_info_node *node = s->private;
1541         struct tegra_dc *dc = node->info_ent->data;
1542         unsigned int i;
1543         int err = 0;
1544
1545         drm_modeset_lock(&dc->base.mutex, NULL);
1546
1547         if (!dc->base.state->active) {
1548                 err = -EBUSY;
1549                 goto unlock;
1550         }
1551
1552         for (i = 0; i < ARRAY_SIZE(tegra_dc_regs); i++) {
1553                 unsigned int offset = tegra_dc_regs[i].offset;
1554
1555                 seq_printf(s, "%-40s %#05x %08x\n", tegra_dc_regs[i].name,
1556                            offset, tegra_dc_readl(dc, offset));
1557         }
1558
1559 unlock:
1560         drm_modeset_unlock(&dc->base.mutex);
1561         return err;
1562 }
1563
1564 static int tegra_dc_show_crc(struct seq_file *s, void *data)
1565 {
1566         struct drm_info_node *node = s->private;
1567         struct tegra_dc *dc = node->info_ent->data;
1568         int err = 0;
1569         u32 value;
1570
1571         drm_modeset_lock(&dc->base.mutex, NULL);
1572
1573         if (!dc->base.state->active) {
1574                 err = -EBUSY;
1575                 goto unlock;
1576         }
1577
1578         value = DC_COM_CRC_CONTROL_ACTIVE_DATA | DC_COM_CRC_CONTROL_ENABLE;
1579         tegra_dc_writel(dc, value, DC_COM_CRC_CONTROL);
1580         tegra_dc_commit(dc);
1581
1582         drm_crtc_wait_one_vblank(&dc->base);
1583         drm_crtc_wait_one_vblank(&dc->base);
1584
1585         value = tegra_dc_readl(dc, DC_COM_CRC_CHECKSUM);
1586         seq_printf(s, "%08x\n", value);
1587
1588         tegra_dc_writel(dc, 0, DC_COM_CRC_CONTROL);
1589
1590 unlock:
1591         drm_modeset_unlock(&dc->base.mutex);
1592         return err;
1593 }
1594
1595 static int tegra_dc_show_stats(struct seq_file *s, void *data)
1596 {
1597         struct drm_info_node *node = s->private;
1598         struct tegra_dc *dc = node->info_ent->data;
1599
1600         seq_printf(s, "frames: %lu\n", dc->stats.frames);
1601         seq_printf(s, "vblank: %lu\n", dc->stats.vblank);
1602         seq_printf(s, "underflow: %lu\n", dc->stats.underflow);
1603         seq_printf(s, "overflow: %lu\n", dc->stats.overflow);
1604
1605         seq_printf(s, "frames total: %lu\n", dc->stats.frames_total);
1606         seq_printf(s, "vblank total: %lu\n", dc->stats.vblank_total);
1607         seq_printf(s, "underflow total: %lu\n", dc->stats.underflow_total);
1608         seq_printf(s, "overflow total: %lu\n", dc->stats.overflow_total);
1609
1610         return 0;
1611 }
1612
1613 static struct drm_info_list debugfs_files[] = {
1614         { "regs", tegra_dc_show_regs, 0, NULL },
1615         { "crc", tegra_dc_show_crc, 0, NULL },
1616         { "stats", tegra_dc_show_stats, 0, NULL },
1617 };
1618
1619 static int tegra_dc_late_register(struct drm_crtc *crtc)
1620 {
1621         unsigned int i, count = ARRAY_SIZE(debugfs_files);
1622         struct drm_minor *minor = crtc->dev->primary;
1623         struct dentry *root;
1624         struct tegra_dc *dc = to_tegra_dc(crtc);
1625
1626 #ifdef CONFIG_DEBUG_FS
1627         root = crtc->debugfs_entry;
1628 #else
1629         root = NULL;
1630 #endif
1631
1632         dc->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
1633                                     GFP_KERNEL);
1634         if (!dc->debugfs_files)
1635                 return -ENOMEM;
1636
1637         for (i = 0; i < count; i++)
1638                 dc->debugfs_files[i].data = dc;
1639
1640         drm_debugfs_create_files(dc->debugfs_files, count, root, minor);
1641
1642         return 0;
1643 }
1644
1645 static void tegra_dc_early_unregister(struct drm_crtc *crtc)
1646 {
1647         unsigned int count = ARRAY_SIZE(debugfs_files);
1648         struct drm_minor *minor = crtc->dev->primary;
1649         struct tegra_dc *dc = to_tegra_dc(crtc);
1650
1651         drm_debugfs_remove_files(dc->debugfs_files, count, minor);
1652         kfree(dc->debugfs_files);
1653         dc->debugfs_files = NULL;
1654 }
1655
1656 static u32 tegra_dc_get_vblank_counter(struct drm_crtc *crtc)
1657 {
1658         struct tegra_dc *dc = to_tegra_dc(crtc);
1659
1660         /* XXX vblank syncpoints don't work with nvdisplay yet */
1661         if (dc->syncpt && !dc->soc->has_nvdisplay)
1662                 return host1x_syncpt_read(dc->syncpt);
1663
1664         /* fallback to software emulated VBLANK counter */
1665         return (u32)drm_crtc_vblank_count(&dc->base);
1666 }
1667
1668 static int tegra_dc_enable_vblank(struct drm_crtc *crtc)
1669 {
1670         struct tegra_dc *dc = to_tegra_dc(crtc);
1671         u32 value;
1672
1673         value = tegra_dc_readl(dc, DC_CMD_INT_MASK);
1674         value |= VBLANK_INT;
1675         tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
1676
1677         return 0;
1678 }
1679
1680 static void tegra_dc_disable_vblank(struct drm_crtc *crtc)
1681 {
1682         struct tegra_dc *dc = to_tegra_dc(crtc);
1683         u32 value;
1684
1685         value = tegra_dc_readl(dc, DC_CMD_INT_MASK);
1686         value &= ~VBLANK_INT;
1687         tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
1688 }
1689
1690 static const struct drm_crtc_funcs tegra_crtc_funcs = {
1691         .page_flip = drm_atomic_helper_page_flip,
1692         .set_config = drm_atomic_helper_set_config,
1693         .destroy = tegra_dc_destroy,
1694         .reset = tegra_crtc_reset,
1695         .atomic_duplicate_state = tegra_crtc_atomic_duplicate_state,
1696         .atomic_destroy_state = tegra_crtc_atomic_destroy_state,
1697         .late_register = tegra_dc_late_register,
1698         .early_unregister = tegra_dc_early_unregister,
1699         .get_vblank_counter = tegra_dc_get_vblank_counter,
1700         .enable_vblank = tegra_dc_enable_vblank,
1701         .disable_vblank = tegra_dc_disable_vblank,
1702 };
1703
1704 static int tegra_dc_set_timings(struct tegra_dc *dc,
1705                                 struct drm_display_mode *mode)
1706 {
1707         unsigned int h_ref_to_sync = 1;
1708         unsigned int v_ref_to_sync = 1;
1709         unsigned long value;
1710
1711         if (!dc->soc->has_nvdisplay) {
1712                 tegra_dc_writel(dc, 0x0, DC_DISP_DISP_TIMING_OPTIONS);
1713
1714                 value = (v_ref_to_sync << 16) | h_ref_to_sync;
1715                 tegra_dc_writel(dc, value, DC_DISP_REF_TO_SYNC);
1716         }
1717
1718         value = ((mode->vsync_end - mode->vsync_start) << 16) |
1719                 ((mode->hsync_end - mode->hsync_start) <<  0);
1720         tegra_dc_writel(dc, value, DC_DISP_SYNC_WIDTH);
1721
1722         value = ((mode->vtotal - mode->vsync_end) << 16) |
1723                 ((mode->htotal - mode->hsync_end) <<  0);
1724         tegra_dc_writel(dc, value, DC_DISP_BACK_PORCH);
1725
1726         value = ((mode->vsync_start - mode->vdisplay) << 16) |
1727                 ((mode->hsync_start - mode->hdisplay) <<  0);
1728         tegra_dc_writel(dc, value, DC_DISP_FRONT_PORCH);
1729
1730         value = (mode->vdisplay << 16) | mode->hdisplay;
1731         tegra_dc_writel(dc, value, DC_DISP_ACTIVE);
1732
1733         return 0;
1734 }
1735
1736 /**
1737  * tegra_dc_state_setup_clock - check clock settings and store them in atomic
1738  *     state
1739  * @dc: display controller
1740  * @crtc_state: CRTC atomic state
1741  * @clk: parent clock for display controller
1742  * @pclk: pixel clock
1743  * @div: shift clock divider
1744  *
1745  * Returns:
1746  * 0 on success or a negative error-code on failure.
1747  */
1748 int tegra_dc_state_setup_clock(struct tegra_dc *dc,
1749                                struct drm_crtc_state *crtc_state,
1750                                struct clk *clk, unsigned long pclk,
1751                                unsigned int div)
1752 {
1753         struct tegra_dc_state *state = to_dc_state(crtc_state);
1754
1755         if (!clk_has_parent(dc->clk, clk))
1756                 return -EINVAL;
1757
1758         state->clk = clk;
1759         state->pclk = pclk;
1760         state->div = div;
1761
1762         return 0;
1763 }
1764
1765 static void tegra_dc_commit_state(struct tegra_dc *dc,
1766                                   struct tegra_dc_state *state)
1767 {
1768         u32 value;
1769         int err;
1770
1771         err = clk_set_parent(dc->clk, state->clk);
1772         if (err < 0)
1773                 dev_err(dc->dev, "failed to set parent clock: %d\n", err);
1774
1775         /*
1776          * Outputs may not want to change the parent clock rate. This is only
1777          * relevant to Tegra20 where only a single display PLL is available.
1778          * Since that PLL would typically be used for HDMI, an internal LVDS
1779          * panel would need to be driven by some other clock such as PLL_P
1780          * which is shared with other peripherals. Changing the clock rate
1781          * should therefore be avoided.
1782          */
1783         if (state->pclk > 0) {
1784                 err = clk_set_rate(state->clk, state->pclk);
1785                 if (err < 0)
1786                         dev_err(dc->dev,
1787                                 "failed to set clock rate to %lu Hz\n",
1788                                 state->pclk);
1789
1790                 err = clk_set_rate(dc->clk, state->pclk);
1791                 if (err < 0)
1792                         dev_err(dc->dev, "failed to set clock %pC to %lu Hz: %d\n",
1793                                 dc->clk, state->pclk, err);
1794         }
1795
1796         DRM_DEBUG_KMS("rate: %lu, div: %u\n", clk_get_rate(dc->clk),
1797                       state->div);
1798         DRM_DEBUG_KMS("pclk: %lu\n", state->pclk);
1799
1800         if (!dc->soc->has_nvdisplay) {
1801                 value = SHIFT_CLK_DIVIDER(state->div) | PIXEL_CLK_DIVIDER_PCD1;
1802                 tegra_dc_writel(dc, value, DC_DISP_DISP_CLOCK_CONTROL);
1803         }
1804 }
1805
1806 static void tegra_dc_stop(struct tegra_dc *dc)
1807 {
1808         u32 value;
1809
1810         /* stop the display controller */
1811         value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);
1812         value &= ~DISP_CTRL_MODE_MASK;
1813         tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
1814
1815         tegra_dc_commit(dc);
1816 }
1817
1818 static bool tegra_dc_idle(struct tegra_dc *dc)
1819 {
1820         u32 value;
1821
1822         value = tegra_dc_readl_active(dc, DC_CMD_DISPLAY_COMMAND);
1823
1824         return (value & DISP_CTRL_MODE_MASK) == 0;
1825 }
1826
1827 static int tegra_dc_wait_idle(struct tegra_dc *dc, unsigned long timeout)
1828 {
1829         timeout = jiffies + msecs_to_jiffies(timeout);
1830
1831         while (time_before(jiffies, timeout)) {
1832                 if (tegra_dc_idle(dc))
1833                         return 0;
1834
1835                 usleep_range(1000, 2000);
1836         }
1837
1838         dev_dbg(dc->dev, "timeout waiting for DC to become idle\n");
1839         return -ETIMEDOUT;
1840 }
1841
1842 static void
1843 tegra_crtc_update_memory_bandwidth(struct drm_crtc *crtc,
1844                                    struct drm_atomic_state *state,
1845                                    bool prepare_bandwidth_transition)
1846 {
1847         const struct tegra_plane_state *old_tegra_state, *new_tegra_state;
1848         u32 i, new_avg_bw, old_avg_bw, new_peak_bw, old_peak_bw;
1849         const struct drm_plane_state *old_plane_state;
1850         const struct drm_crtc_state *old_crtc_state;
1851         struct tegra_dc_window window, old_window;
1852         struct tegra_dc *dc = to_tegra_dc(crtc);
1853         struct tegra_plane *tegra;
1854         struct drm_plane *plane;
1855
1856         if (dc->soc->has_nvdisplay)
1857                 return;
1858
1859         old_crtc_state = drm_atomic_get_old_crtc_state(state, crtc);
1860
1861         if (!crtc->state->active) {
1862                 if (!old_crtc_state->active)
1863                         return;
1864
1865                 /*
1866                  * When CRTC is disabled on DPMS, the state of attached planes
1867                  * is kept unchanged. Hence we need to enforce removal of the
1868                  * bandwidths from the ICC paths.
1869                  */
1870                 drm_atomic_crtc_for_each_plane(plane, crtc) {
1871                         tegra = to_tegra_plane(plane);
1872
1873                         icc_set_bw(tegra->icc_mem, 0, 0);
1874                         icc_set_bw(tegra->icc_mem_vfilter, 0, 0);
1875                 }
1876
1877                 return;
1878         }
1879
1880         for_each_old_plane_in_state(old_crtc_state->state, plane,
1881                                     old_plane_state, i) {
1882                 old_tegra_state = to_const_tegra_plane_state(old_plane_state);
1883                 new_tegra_state = to_const_tegra_plane_state(plane->state);
1884                 tegra = to_tegra_plane(plane);
1885
1886                 /*
1887                  * We're iterating over the global atomic state and it contains
1888                  * planes from another CRTC, hence we need to filter out the
1889                  * planes unrelated to this CRTC.
1890                  */
1891                 if (tegra->dc != dc)
1892                         continue;
1893
1894                 new_avg_bw = new_tegra_state->avg_memory_bandwidth;
1895                 old_avg_bw = old_tegra_state->avg_memory_bandwidth;
1896
1897                 new_peak_bw = new_tegra_state->total_peak_memory_bandwidth;
1898                 old_peak_bw = old_tegra_state->total_peak_memory_bandwidth;
1899
1900                 /*
1901                  * See the comment related to !crtc->state->active above,
1902                  * which explains why bandwidths need to be updated when
1903                  * CRTC is turning ON.
1904                  */
1905                 if (new_avg_bw == old_avg_bw && new_peak_bw == old_peak_bw &&
1906                     old_crtc_state->active)
1907                         continue;
1908
1909                 window.src.h = drm_rect_height(&plane->state->src) >> 16;
1910                 window.dst.h = drm_rect_height(&plane->state->dst);
1911
1912                 old_window.src.h = drm_rect_height(&old_plane_state->src) >> 16;
1913                 old_window.dst.h = drm_rect_height(&old_plane_state->dst);
1914
1915                 /*
1916                  * During the preparation phase (atomic_begin), the memory
1917                  * freq should go high before the DC changes are committed
1918                  * if bandwidth requirement goes up, otherwise memory freq
1919                  * should to stay high if BW requirement goes down.  The
1920                  * opposite applies to the completion phase (post_commit).
1921                  */
1922                 if (prepare_bandwidth_transition) {
1923                         new_avg_bw = max(old_avg_bw, new_avg_bw);
1924                         new_peak_bw = max(old_peak_bw, new_peak_bw);
1925
1926                         if (tegra_plane_use_vertical_filtering(tegra, &old_window))
1927                                 window = old_window;
1928                 }
1929
1930                 icc_set_bw(tegra->icc_mem, new_avg_bw, new_peak_bw);
1931
1932                 if (tegra_plane_use_vertical_filtering(tegra, &window))
1933                         icc_set_bw(tegra->icc_mem_vfilter, new_avg_bw, new_peak_bw);
1934                 else
1935                         icc_set_bw(tegra->icc_mem_vfilter, 0, 0);
1936         }
1937 }
1938
1939 static void tegra_crtc_atomic_disable(struct drm_crtc *crtc,
1940                                       struct drm_atomic_state *state)
1941 {
1942         struct tegra_dc *dc = to_tegra_dc(crtc);
1943         u32 value;
1944         int err;
1945
1946         if (!tegra_dc_idle(dc)) {
1947                 tegra_dc_stop(dc);
1948
1949                 /*
1950                  * Ignore the return value, there isn't anything useful to do
1951                  * in case this fails.
1952                  */
1953                 tegra_dc_wait_idle(dc, 100);
1954         }
1955
1956         /*
1957          * This should really be part of the RGB encoder driver, but clearing
1958          * these bits has the side-effect of stopping the display controller.
1959          * When that happens no VBLANK interrupts will be raised. At the same
1960          * time the encoder is disabled before the display controller, so the
1961          * above code is always going to timeout waiting for the controller
1962          * to go idle.
1963          *
1964          * Given the close coupling between the RGB encoder and the display
1965          * controller doing it here is still kind of okay. None of the other
1966          * encoder drivers require these bits to be cleared.
1967          *
1968          * XXX: Perhaps given that the display controller is switched off at
1969          * this point anyway maybe clearing these bits isn't even useful for
1970          * the RGB encoder?
1971          */
1972         if (dc->rgb) {
1973                 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL);
1974                 value &= ~(PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
1975                            PW4_ENABLE | PM0_ENABLE | PM1_ENABLE);
1976                 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
1977         }
1978
1979         tegra_dc_stats_reset(&dc->stats);
1980         drm_crtc_vblank_off(crtc);
1981
1982         spin_lock_irq(&crtc->dev->event_lock);
1983
1984         if (crtc->state->event) {
1985                 drm_crtc_send_vblank_event(crtc, crtc->state->event);
1986                 crtc->state->event = NULL;
1987         }
1988
1989         spin_unlock_irq(&crtc->dev->event_lock);
1990
1991         err = host1x_client_suspend(&dc->client);
1992         if (err < 0)
1993                 dev_err(dc->dev, "failed to suspend: %d\n", err);
1994 }
1995
1996 static void tegra_crtc_atomic_enable(struct drm_crtc *crtc,
1997                                      struct drm_atomic_state *state)
1998 {
1999         struct drm_display_mode *mode = &crtc->state->adjusted_mode;
2000         struct tegra_dc_state *crtc_state = to_dc_state(crtc->state);
2001         struct tegra_dc *dc = to_tegra_dc(crtc);
2002         u32 value;
2003         int err;
2004
2005         err = host1x_client_resume(&dc->client);
2006         if (err < 0) {
2007                 dev_err(dc->dev, "failed to resume: %d\n", err);
2008                 return;
2009         }
2010
2011         /* initialize display controller */
2012         if (dc->syncpt) {
2013                 u32 syncpt = host1x_syncpt_id(dc->syncpt), enable;
2014
2015                 if (dc->soc->has_nvdisplay)
2016                         enable = 1 << 31;
2017                 else
2018                         enable = 1 << 8;
2019
2020                 value = SYNCPT_CNTRL_NO_STALL;
2021                 tegra_dc_writel(dc, value, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
2022
2023                 value = enable | syncpt;
2024                 tegra_dc_writel(dc, value, DC_CMD_CONT_SYNCPT_VSYNC);
2025         }
2026
2027         if (dc->soc->has_nvdisplay) {
2028                 value = DSC_TO_UF_INT | DSC_BBUF_UF_INT | DSC_RBUF_UF_INT |
2029                         DSC_OBUF_UF_INT;
2030                 tegra_dc_writel(dc, value, DC_CMD_INT_TYPE);
2031
2032                 value = DSC_TO_UF_INT | DSC_BBUF_UF_INT | DSC_RBUF_UF_INT |
2033                         DSC_OBUF_UF_INT | SD3_BUCKET_WALK_DONE_INT |
2034                         HEAD_UF_INT | MSF_INT | REG_TMOUT_INT |
2035                         REGION_CRC_INT | V_PULSE2_INT | V_PULSE3_INT |
2036                         VBLANK_INT | FRAME_END_INT;
2037                 tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY);
2038
2039                 value = SD3_BUCKET_WALK_DONE_INT | HEAD_UF_INT | VBLANK_INT |
2040                         FRAME_END_INT;
2041                 tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE);
2042
2043                 value = HEAD_UF_INT | REG_TMOUT_INT | FRAME_END_INT;
2044                 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
2045
2046                 tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS);
2047         } else {
2048                 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
2049                         WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
2050                 tegra_dc_writel(dc, value, DC_CMD_INT_TYPE);
2051
2052                 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
2053                         WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
2054                 tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY);
2055
2056                 /* initialize timer */
2057                 value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(0x20) |
2058                         WINDOW_B_THRESHOLD(0x20) | WINDOW_C_THRESHOLD(0x20);
2059                 tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY);
2060
2061                 value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(1) |
2062                         WINDOW_B_THRESHOLD(1) | WINDOW_C_THRESHOLD(1);
2063                 tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER);
2064
2065                 value = VBLANK_INT | WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
2066                         WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
2067                 tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE);
2068
2069                 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
2070                         WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
2071                 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
2072         }
2073
2074         if (dc->soc->supports_background_color)
2075                 tegra_dc_writel(dc, 0, DC_DISP_BLEND_BACKGROUND_COLOR);
2076         else
2077                 tegra_dc_writel(dc, 0, DC_DISP_BORDER_COLOR);
2078
2079         /* apply PLL and pixel clock changes */
2080         tegra_dc_commit_state(dc, crtc_state);
2081
2082         /* program display mode */
2083         tegra_dc_set_timings(dc, mode);
2084
2085         /* interlacing isn't supported yet, so disable it */
2086         if (dc->soc->supports_interlacing) {
2087                 value = tegra_dc_readl(dc, DC_DISP_INTERLACE_CONTROL);
2088                 value &= ~INTERLACE_ENABLE;
2089                 tegra_dc_writel(dc, value, DC_DISP_INTERLACE_CONTROL);
2090         }
2091
2092         value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);
2093         value &= ~DISP_CTRL_MODE_MASK;
2094         value |= DISP_CTRL_MODE_C_DISPLAY;
2095         tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
2096
2097         if (!dc->soc->has_nvdisplay) {
2098                 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL);
2099                 value |= PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
2100                          PW4_ENABLE | PM0_ENABLE | PM1_ENABLE;
2101                 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
2102         }
2103
2104         /* enable underflow reporting and display red for missing pixels */
2105         if (dc->soc->has_nvdisplay) {
2106                 value = UNDERFLOW_MODE_RED | UNDERFLOW_REPORT_ENABLE;
2107                 tegra_dc_writel(dc, value, DC_COM_RG_UNDERFLOW);
2108         }
2109
2110         tegra_dc_commit(dc);
2111
2112         drm_crtc_vblank_on(crtc);
2113 }
2114
2115 static void tegra_crtc_atomic_begin(struct drm_crtc *crtc,
2116                                     struct drm_atomic_state *state)
2117 {
2118         unsigned long flags;
2119
2120         tegra_crtc_update_memory_bandwidth(crtc, state, true);
2121
2122         if (crtc->state->event) {
2123                 spin_lock_irqsave(&crtc->dev->event_lock, flags);
2124
2125                 if (drm_crtc_vblank_get(crtc) != 0)
2126                         drm_crtc_send_vblank_event(crtc, crtc->state->event);
2127                 else
2128                         drm_crtc_arm_vblank_event(crtc, crtc->state->event);
2129
2130                 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
2131
2132                 crtc->state->event = NULL;
2133         }
2134 }
2135
2136 static void tegra_crtc_atomic_flush(struct drm_crtc *crtc,
2137                                     struct drm_atomic_state *state)
2138 {
2139         struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,
2140                                                                           crtc);
2141         struct tegra_dc_state *dc_state = to_dc_state(crtc_state);
2142         struct tegra_dc *dc = to_tegra_dc(crtc);
2143         u32 value;
2144
2145         value = dc_state->planes << 8 | GENERAL_UPDATE;
2146         tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);
2147         value = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
2148
2149         value = dc_state->planes | GENERAL_ACT_REQ;
2150         tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);
2151         value = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
2152 }
2153
2154 static bool tegra_plane_is_cursor(const struct drm_plane_state *state)
2155 {
2156         const struct tegra_dc_soc_info *soc = to_tegra_dc(state->crtc)->soc;
2157         const struct drm_format_info *fmt = state->fb->format;
2158         unsigned int src_w = drm_rect_width(&state->src) >> 16;
2159         unsigned int dst_w = drm_rect_width(&state->dst);
2160
2161         if (state->plane->type != DRM_PLANE_TYPE_CURSOR)
2162                 return false;
2163
2164         if (soc->supports_cursor)
2165                 return true;
2166
2167         if (src_w != dst_w || fmt->num_planes != 1 || src_w * fmt->cpp[0] > 256)
2168                 return false;
2169
2170         return true;
2171 }
2172
2173 static unsigned long
2174 tegra_plane_overlap_mask(struct drm_crtc_state *state,
2175                          const struct drm_plane_state *plane_state)
2176 {
2177         const struct drm_plane_state *other_state;
2178         const struct tegra_plane *tegra;
2179         unsigned long overlap_mask = 0;
2180         struct drm_plane *plane;
2181         struct drm_rect rect;
2182
2183         if (!plane_state->visible || !plane_state->fb)
2184                 return 0;
2185
2186         /*
2187          * Data-prefetch FIFO will easily help to overcome temporal memory
2188          * pressure if other plane overlaps with the cursor plane.
2189          */
2190         if (tegra_plane_is_cursor(plane_state))
2191                 return 0;
2192
2193         drm_atomic_crtc_state_for_each_plane_state(plane, other_state, state) {
2194                 rect = plane_state->dst;
2195
2196                 tegra = to_tegra_plane(other_state->plane);
2197
2198                 if (!other_state->visible || !other_state->fb)
2199                         continue;
2200
2201                 /*
2202                  * Ignore cursor plane overlaps because it's not practical to
2203                  * assume that it contributes to the bandwidth in overlapping
2204                  * area if window width is small.
2205                  */
2206                 if (tegra_plane_is_cursor(other_state))
2207                         continue;
2208
2209                 if (drm_rect_intersect(&rect, &other_state->dst))
2210                         overlap_mask |= BIT(tegra->index);
2211         }
2212
2213         return overlap_mask;
2214 }
2215
2216 static int tegra_crtc_calculate_memory_bandwidth(struct drm_crtc *crtc,
2217                                                  struct drm_atomic_state *state)
2218 {
2219         ulong overlap_mask[TEGRA_DC_LEGACY_PLANES_NUM] = {}, mask;
2220         u32 plane_peak_bw[TEGRA_DC_LEGACY_PLANES_NUM] = {};
2221         bool all_planes_overlap_simultaneously = true;
2222         const struct tegra_plane_state *tegra_state;
2223         const struct drm_plane_state *plane_state;
2224         struct tegra_dc *dc = to_tegra_dc(crtc);
2225         const struct drm_crtc_state *old_state;
2226         struct drm_crtc_state *new_state;
2227         struct tegra_plane *tegra;
2228         struct drm_plane *plane;
2229
2230         /*
2231          * The nv-display uses shared planes.  The algorithm below assumes
2232          * maximum 3 planes per-CRTC, this assumption isn't applicable to
2233          * the nv-display.  Note that T124 support has additional windows,
2234          * but currently they aren't supported by the driver.
2235          */
2236         if (dc->soc->has_nvdisplay)
2237                 return 0;
2238
2239         new_state = drm_atomic_get_new_crtc_state(state, crtc);
2240         old_state = drm_atomic_get_old_crtc_state(state, crtc);
2241
2242         /*
2243          * For overlapping planes pixel's data is fetched for each plane at
2244          * the same time, hence bandwidths are accumulated in this case.
2245          * This needs to be taken into account for calculating total bandwidth
2246          * consumed by all planes.
2247          *
2248          * Here we get the overlapping state of each plane, which is a
2249          * bitmask of plane indices telling with what planes there is an
2250          * overlap. Note that bitmask[plane] includes BIT(plane) in order
2251          * to make further code nicer and simpler.
2252          */
2253         drm_atomic_crtc_state_for_each_plane_state(plane, plane_state, new_state) {
2254                 tegra_state = to_const_tegra_plane_state(plane_state);
2255                 tegra = to_tegra_plane(plane);
2256
2257                 if (WARN_ON_ONCE(tegra->index >= TEGRA_DC_LEGACY_PLANES_NUM))
2258                         return -EINVAL;
2259
2260                 plane_peak_bw[tegra->index] = tegra_state->peak_memory_bandwidth;
2261                 mask = tegra_plane_overlap_mask(new_state, plane_state);
2262                 overlap_mask[tegra->index] = mask;
2263
2264                 if (hweight_long(mask) != 3)
2265                         all_planes_overlap_simultaneously = false;
2266         }
2267
2268         /*
2269          * Then we calculate maximum bandwidth of each plane state.
2270          * The bandwidth includes the plane BW + BW of the "simultaneously"
2271          * overlapping planes, where "simultaneously" means areas where DC
2272          * fetches from the planes simultaneously during of scan-out process.
2273          *
2274          * For example, if plane A overlaps with planes B and C, but B and C
2275          * don't overlap, then the peak bandwidth will be either in area where
2276          * A-and-B or A-and-C planes overlap.
2277          *
2278          * The plane_peak_bw[] contains peak memory bandwidth values of
2279          * each plane, this information is needed by interconnect provider
2280          * in order to set up latency allowance based on the peak BW, see
2281          * tegra_crtc_update_memory_bandwidth().
2282          */
2283         drm_atomic_crtc_state_for_each_plane_state(plane, plane_state, new_state) {
2284                 u32 i, old_peak_bw, new_peak_bw, overlap_bw = 0;
2285
2286                 /*
2287                  * Note that plane's atomic check doesn't touch the
2288                  * total_peak_memory_bandwidth of enabled plane, hence the
2289                  * current state contains the old bandwidth state from the
2290                  * previous CRTC commit.
2291                  */
2292                 tegra_state = to_const_tegra_plane_state(plane_state);
2293                 tegra = to_tegra_plane(plane);
2294
2295                 for_each_set_bit(i, &overlap_mask[tegra->index], 3) {
2296                         if (i == tegra->index)
2297                                 continue;
2298
2299                         if (all_planes_overlap_simultaneously)
2300                                 overlap_bw += plane_peak_bw[i];
2301                         else
2302                                 overlap_bw = max(overlap_bw, plane_peak_bw[i]);
2303                 }
2304
2305                 new_peak_bw = plane_peak_bw[tegra->index] + overlap_bw;
2306                 old_peak_bw = tegra_state->total_peak_memory_bandwidth;
2307
2308                 /*
2309                  * If plane's peak bandwidth changed (for example plane isn't
2310                  * overlapped anymore) and plane isn't in the atomic state,
2311                  * then add plane to the state in order to have the bandwidth
2312                  * updated.
2313                  */
2314                 if (old_peak_bw != new_peak_bw) {
2315                         struct tegra_plane_state *new_tegra_state;
2316                         struct drm_plane_state *new_plane_state;
2317
2318                         new_plane_state = drm_atomic_get_plane_state(state, plane);
2319                         if (IS_ERR(new_plane_state))
2320                                 return PTR_ERR(new_plane_state);
2321
2322                         new_tegra_state = to_tegra_plane_state(new_plane_state);
2323                         new_tegra_state->total_peak_memory_bandwidth = new_peak_bw;
2324                 }
2325         }
2326
2327         return 0;
2328 }
2329
2330 static int tegra_crtc_atomic_check(struct drm_crtc *crtc,
2331                                    struct drm_atomic_state *state)
2332 {
2333         int err;
2334
2335         err = tegra_crtc_calculate_memory_bandwidth(crtc, state);
2336         if (err)
2337                 return err;
2338
2339         return 0;
2340 }
2341
2342 void tegra_crtc_atomic_post_commit(struct drm_crtc *crtc,
2343                                    struct drm_atomic_state *state)
2344 {
2345         /*
2346          * Display bandwidth is allowed to go down only once hardware state
2347          * is known to be armed, i.e. state was committed and VBLANK event
2348          * received.
2349          */
2350         tegra_crtc_update_memory_bandwidth(crtc, state, false);
2351 }
2352
2353 static const struct drm_crtc_helper_funcs tegra_crtc_helper_funcs = {
2354         .atomic_check = tegra_crtc_atomic_check,
2355         .atomic_begin = tegra_crtc_atomic_begin,
2356         .atomic_flush = tegra_crtc_atomic_flush,
2357         .atomic_enable = tegra_crtc_atomic_enable,
2358         .atomic_disable = tegra_crtc_atomic_disable,
2359 };
2360
2361 static irqreturn_t tegra_dc_irq(int irq, void *data)
2362 {
2363         struct tegra_dc *dc = data;
2364         unsigned long status;
2365
2366         status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
2367         tegra_dc_writel(dc, status, DC_CMD_INT_STATUS);
2368
2369         if (status & FRAME_END_INT) {
2370                 /*
2371                 dev_dbg(dc->dev, "%s(): frame end\n", __func__);
2372                 */
2373                 dc->stats.frames_total++;
2374                 dc->stats.frames++;
2375         }
2376
2377         if (status & VBLANK_INT) {
2378                 /*
2379                 dev_dbg(dc->dev, "%s(): vertical blank\n", __func__);
2380                 */
2381                 drm_crtc_handle_vblank(&dc->base);
2382                 dc->stats.vblank_total++;
2383                 dc->stats.vblank++;
2384         }
2385
2386         if (status & (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT)) {
2387                 /*
2388                 dev_dbg(dc->dev, "%s(): underflow\n", __func__);
2389                 */
2390                 dc->stats.underflow_total++;
2391                 dc->stats.underflow++;
2392         }
2393
2394         if (status & (WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT)) {
2395                 /*
2396                 dev_dbg(dc->dev, "%s(): overflow\n", __func__);
2397                 */
2398                 dc->stats.overflow_total++;
2399                 dc->stats.overflow++;
2400         }
2401
2402         if (status & HEAD_UF_INT) {
2403                 dev_dbg_ratelimited(dc->dev, "%s(): head underflow\n", __func__);
2404                 dc->stats.underflow_total++;
2405                 dc->stats.underflow++;
2406         }
2407
2408         return IRQ_HANDLED;
2409 }
2410
2411 static bool tegra_dc_has_window_groups(struct tegra_dc *dc)
2412 {
2413         unsigned int i;
2414
2415         if (!dc->soc->wgrps)
2416                 return true;
2417
2418         for (i = 0; i < dc->soc->num_wgrps; i++) {
2419                 const struct tegra_windowgroup_soc *wgrp = &dc->soc->wgrps[i];
2420
2421                 if (wgrp->dc == dc->pipe && wgrp->num_windows > 0)
2422                         return true;
2423         }
2424
2425         return false;
2426 }
2427
2428 static int tegra_dc_early_init(struct host1x_client *client)
2429 {
2430         struct drm_device *drm = dev_get_drvdata(client->host);
2431         struct tegra_drm *tegra = drm->dev_private;
2432
2433         tegra->num_crtcs++;
2434
2435         return 0;
2436 }
2437
2438 static int tegra_dc_init(struct host1x_client *client)
2439 {
2440         struct drm_device *drm = dev_get_drvdata(client->host);
2441         unsigned long flags = HOST1X_SYNCPT_CLIENT_MANAGED;
2442         struct tegra_dc *dc = host1x_client_to_dc(client);
2443         struct tegra_drm *tegra = drm->dev_private;
2444         struct drm_plane *primary = NULL;
2445         struct drm_plane *cursor = NULL;
2446         int err;
2447
2448         /*
2449          * DC has been reset by now, so VBLANK syncpoint can be released
2450          * for general use.
2451          */
2452         host1x_syncpt_release_vblank_reservation(client, 26 + dc->pipe);
2453
2454         /*
2455          * XXX do not register DCs with no window groups because we cannot
2456          * assign a primary plane to them, which in turn will cause KMS to
2457          * crash.
2458          */
2459         if (!tegra_dc_has_window_groups(dc))
2460                 return 0;
2461
2462         /*
2463          * Set the display hub as the host1x client parent for the display
2464          * controller. This is needed for the runtime reference counting that
2465          * ensures the display hub is always powered when any of the display
2466          * controllers are.
2467          */
2468         if (dc->soc->has_nvdisplay)
2469                 client->parent = &tegra->hub->client;
2470
2471         dc->syncpt = host1x_syncpt_request(client, flags);
2472         if (!dc->syncpt)
2473                 dev_warn(dc->dev, "failed to allocate syncpoint\n");
2474
2475         err = host1x_client_iommu_attach(client);
2476         if (err < 0 && err != -ENODEV) {
2477                 dev_err(client->dev, "failed to attach to domain: %d\n", err);
2478                 return err;
2479         }
2480
2481         if (dc->soc->wgrps)
2482                 primary = tegra_dc_add_shared_planes(drm, dc);
2483         else
2484                 primary = tegra_dc_add_planes(drm, dc);
2485
2486         if (IS_ERR(primary)) {
2487                 err = PTR_ERR(primary);
2488                 goto cleanup;
2489         }
2490
2491         if (dc->soc->supports_cursor) {
2492                 cursor = tegra_dc_cursor_plane_create(drm, dc);
2493                 if (IS_ERR(cursor)) {
2494                         err = PTR_ERR(cursor);
2495                         goto cleanup;
2496                 }
2497         } else {
2498                 /* dedicate one overlay to mouse cursor */
2499                 cursor = tegra_dc_overlay_plane_create(drm, dc, 2, true);
2500                 if (IS_ERR(cursor)) {
2501                         err = PTR_ERR(cursor);
2502                         goto cleanup;
2503                 }
2504         }
2505
2506         err = drm_crtc_init_with_planes(drm, &dc->base, primary, cursor,
2507                                         &tegra_crtc_funcs, NULL);
2508         if (err < 0)
2509                 goto cleanup;
2510
2511         drm_crtc_helper_add(&dc->base, &tegra_crtc_helper_funcs);
2512
2513         /*
2514          * Keep track of the minimum pitch alignment across all display
2515          * controllers.
2516          */
2517         if (dc->soc->pitch_align > tegra->pitch_align)
2518                 tegra->pitch_align = dc->soc->pitch_align;
2519
2520         /* track maximum resolution */
2521         if (dc->soc->has_nvdisplay)
2522                 drm->mode_config.max_width = drm->mode_config.max_height = 16384;
2523         else
2524                 drm->mode_config.max_width = drm->mode_config.max_height = 4096;
2525
2526         err = tegra_dc_rgb_init(drm, dc);
2527         if (err < 0 && err != -ENODEV) {
2528                 dev_err(dc->dev, "failed to initialize RGB output: %d\n", err);
2529                 goto cleanup;
2530         }
2531
2532         err = devm_request_irq(dc->dev, dc->irq, tegra_dc_irq, 0,
2533                                dev_name(dc->dev), dc);
2534         if (err < 0) {
2535                 dev_err(dc->dev, "failed to request IRQ#%u: %d\n", dc->irq,
2536                         err);
2537                 goto cleanup;
2538         }
2539
2540         /*
2541          * Inherit the DMA parameters (such as maximum segment size) from the
2542          * parent host1x device.
2543          */
2544         client->dev->dma_parms = client->host->dma_parms;
2545
2546         return 0;
2547
2548 cleanup:
2549         if (!IS_ERR_OR_NULL(cursor))
2550                 drm_plane_cleanup(cursor);
2551
2552         if (!IS_ERR(primary))
2553                 drm_plane_cleanup(primary);
2554
2555         host1x_client_iommu_detach(client);
2556         host1x_syncpt_put(dc->syncpt);
2557
2558         return err;
2559 }
2560
2561 static int tegra_dc_exit(struct host1x_client *client)
2562 {
2563         struct tegra_dc *dc = host1x_client_to_dc(client);
2564         int err;
2565
2566         if (!tegra_dc_has_window_groups(dc))
2567                 return 0;
2568
2569         /* avoid a dangling pointer just in case this disappears */
2570         client->dev->dma_parms = NULL;
2571
2572         devm_free_irq(dc->dev, dc->irq, dc);
2573
2574         err = tegra_dc_rgb_exit(dc);
2575         if (err) {
2576                 dev_err(dc->dev, "failed to shutdown RGB output: %d\n", err);
2577                 return err;
2578         }
2579
2580         host1x_client_iommu_detach(client);
2581         host1x_syncpt_put(dc->syncpt);
2582
2583         return 0;
2584 }
2585
2586 static int tegra_dc_late_exit(struct host1x_client *client)
2587 {
2588         struct drm_device *drm = dev_get_drvdata(client->host);
2589         struct tegra_drm *tegra = drm->dev_private;
2590
2591         tegra->num_crtcs--;
2592
2593         return 0;
2594 }
2595
2596 static int tegra_dc_runtime_suspend(struct host1x_client *client)
2597 {
2598         struct tegra_dc *dc = host1x_client_to_dc(client);
2599         struct device *dev = client->dev;
2600         int err;
2601
2602         err = reset_control_assert(dc->rst);
2603         if (err < 0) {
2604                 dev_err(dev, "failed to assert reset: %d\n", err);
2605                 return err;
2606         }
2607
2608         if (dc->soc->has_powergate)
2609                 tegra_powergate_power_off(dc->powergate);
2610
2611         clk_disable_unprepare(dc->clk);
2612         pm_runtime_put_sync(dev);
2613
2614         return 0;
2615 }
2616
2617 static int tegra_dc_runtime_resume(struct host1x_client *client)
2618 {
2619         struct tegra_dc *dc = host1x_client_to_dc(client);
2620         struct device *dev = client->dev;
2621         int err;
2622
2623         err = pm_runtime_resume_and_get(dev);
2624         if (err < 0) {
2625                 dev_err(dev, "failed to get runtime PM: %d\n", err);
2626                 return err;
2627         }
2628
2629         if (dc->soc->has_powergate) {
2630                 err = tegra_powergate_sequence_power_up(dc->powergate, dc->clk,
2631                                                         dc->rst);
2632                 if (err < 0) {
2633                         dev_err(dev, "failed to power partition: %d\n", err);
2634                         goto put_rpm;
2635                 }
2636         } else {
2637                 err = clk_prepare_enable(dc->clk);
2638                 if (err < 0) {
2639                         dev_err(dev, "failed to enable clock: %d\n", err);
2640                         goto put_rpm;
2641                 }
2642
2643                 err = reset_control_deassert(dc->rst);
2644                 if (err < 0) {
2645                         dev_err(dev, "failed to deassert reset: %d\n", err);
2646                         goto disable_clk;
2647                 }
2648         }
2649
2650         return 0;
2651
2652 disable_clk:
2653         clk_disable_unprepare(dc->clk);
2654 put_rpm:
2655         pm_runtime_put_sync(dev);
2656         return err;
2657 }
2658
2659 static const struct host1x_client_ops dc_client_ops = {
2660         .early_init = tegra_dc_early_init,
2661         .init = tegra_dc_init,
2662         .exit = tegra_dc_exit,
2663         .late_exit = tegra_dc_late_exit,
2664         .suspend = tegra_dc_runtime_suspend,
2665         .resume = tegra_dc_runtime_resume,
2666 };
2667
2668 static const struct tegra_dc_soc_info tegra20_dc_soc_info = {
2669         .supports_background_color = false,
2670         .supports_interlacing = false,
2671         .supports_cursor = false,
2672         .supports_block_linear = false,
2673         .supports_sector_layout = false,
2674         .has_legacy_blending = true,
2675         .pitch_align = 8,
2676         .has_powergate = false,
2677         .coupled_pm = true,
2678         .has_nvdisplay = false,
2679         .num_primary_formats = ARRAY_SIZE(tegra20_primary_formats),
2680         .primary_formats = tegra20_primary_formats,
2681         .num_overlay_formats = ARRAY_SIZE(tegra20_overlay_formats),
2682         .overlay_formats = tegra20_overlay_formats,
2683         .modifiers = tegra20_modifiers,
2684         .has_win_a_without_filters = true,
2685         .has_win_b_vfilter_mem_client = true,
2686         .has_win_c_without_vert_filter = true,
2687         .plane_tiled_memory_bandwidth_x2 = false,
2688 };
2689
2690 static const struct tegra_dc_soc_info tegra30_dc_soc_info = {
2691         .supports_background_color = false,
2692         .supports_interlacing = false,
2693         .supports_cursor = false,
2694         .supports_block_linear = false,
2695         .supports_sector_layout = false,
2696         .has_legacy_blending = true,
2697         .pitch_align = 8,
2698         .has_powergate = false,
2699         .coupled_pm = false,
2700         .has_nvdisplay = false,
2701         .num_primary_formats = ARRAY_SIZE(tegra20_primary_formats),
2702         .primary_formats = tegra20_primary_formats,
2703         .num_overlay_formats = ARRAY_SIZE(tegra20_overlay_formats),
2704         .overlay_formats = tegra20_overlay_formats,
2705         .modifiers = tegra20_modifiers,
2706         .has_win_a_without_filters = false,
2707         .has_win_b_vfilter_mem_client = true,
2708         .has_win_c_without_vert_filter = false,
2709         .plane_tiled_memory_bandwidth_x2 = true,
2710 };
2711
2712 static const struct tegra_dc_soc_info tegra114_dc_soc_info = {
2713         .supports_background_color = false,
2714         .supports_interlacing = false,
2715         .supports_cursor = false,
2716         .supports_block_linear = false,
2717         .supports_sector_layout = false,
2718         .has_legacy_blending = true,
2719         .pitch_align = 64,
2720         .has_powergate = true,
2721         .coupled_pm = false,
2722         .has_nvdisplay = false,
2723         .num_primary_formats = ARRAY_SIZE(tegra114_primary_formats),
2724         .primary_formats = tegra114_primary_formats,
2725         .num_overlay_formats = ARRAY_SIZE(tegra114_overlay_formats),
2726         .overlay_formats = tegra114_overlay_formats,
2727         .modifiers = tegra20_modifiers,
2728         .has_win_a_without_filters = false,
2729         .has_win_b_vfilter_mem_client = false,
2730         .has_win_c_without_vert_filter = false,
2731         .plane_tiled_memory_bandwidth_x2 = true,
2732 };
2733
2734 static const struct tegra_dc_soc_info tegra124_dc_soc_info = {
2735         .supports_background_color = true,
2736         .supports_interlacing = true,
2737         .supports_cursor = true,
2738         .supports_block_linear = true,
2739         .supports_sector_layout = false,
2740         .has_legacy_blending = false,
2741         .pitch_align = 64,
2742         .has_powergate = true,
2743         .coupled_pm = false,
2744         .has_nvdisplay = false,
2745         .num_primary_formats = ARRAY_SIZE(tegra124_primary_formats),
2746         .primary_formats = tegra124_primary_formats,
2747         .num_overlay_formats = ARRAY_SIZE(tegra124_overlay_formats),
2748         .overlay_formats = tegra124_overlay_formats,
2749         .modifiers = tegra124_modifiers,
2750         .has_win_a_without_filters = false,
2751         .has_win_b_vfilter_mem_client = false,
2752         .has_win_c_without_vert_filter = false,
2753         .plane_tiled_memory_bandwidth_x2 = false,
2754 };
2755
2756 static const struct tegra_dc_soc_info tegra210_dc_soc_info = {
2757         .supports_background_color = true,
2758         .supports_interlacing = true,
2759         .supports_cursor = true,
2760         .supports_block_linear = true,
2761         .supports_sector_layout = false,
2762         .has_legacy_blending = false,
2763         .pitch_align = 64,
2764         .has_powergate = true,
2765         .coupled_pm = false,
2766         .has_nvdisplay = false,
2767         .num_primary_formats = ARRAY_SIZE(tegra114_primary_formats),
2768         .primary_formats = tegra114_primary_formats,
2769         .num_overlay_formats = ARRAY_SIZE(tegra114_overlay_formats),
2770         .overlay_formats = tegra114_overlay_formats,
2771         .modifiers = tegra124_modifiers,
2772         .has_win_a_without_filters = false,
2773         .has_win_b_vfilter_mem_client = false,
2774         .has_win_c_without_vert_filter = false,
2775         .plane_tiled_memory_bandwidth_x2 = false,
2776 };
2777
2778 static const struct tegra_windowgroup_soc tegra186_dc_wgrps[] = {
2779         {
2780                 .index = 0,
2781                 .dc = 0,
2782                 .windows = (const unsigned int[]) { 0 },
2783                 .num_windows = 1,
2784         }, {
2785                 .index = 1,
2786                 .dc = 1,
2787                 .windows = (const unsigned int[]) { 1 },
2788                 .num_windows = 1,
2789         }, {
2790                 .index = 2,
2791                 .dc = 1,
2792                 .windows = (const unsigned int[]) { 2 },
2793                 .num_windows = 1,
2794         }, {
2795                 .index = 3,
2796                 .dc = 2,
2797                 .windows = (const unsigned int[]) { 3 },
2798                 .num_windows = 1,
2799         }, {
2800                 .index = 4,
2801                 .dc = 2,
2802                 .windows = (const unsigned int[]) { 4 },
2803                 .num_windows = 1,
2804         }, {
2805                 .index = 5,
2806                 .dc = 2,
2807                 .windows = (const unsigned int[]) { 5 },
2808                 .num_windows = 1,
2809         },
2810 };
2811
2812 static const struct tegra_dc_soc_info tegra186_dc_soc_info = {
2813         .supports_background_color = true,
2814         .supports_interlacing = true,
2815         .supports_cursor = true,
2816         .supports_block_linear = true,
2817         .supports_sector_layout = false,
2818         .has_legacy_blending = false,
2819         .pitch_align = 64,
2820         .has_powergate = false,
2821         .coupled_pm = false,
2822         .has_nvdisplay = true,
2823         .wgrps = tegra186_dc_wgrps,
2824         .num_wgrps = ARRAY_SIZE(tegra186_dc_wgrps),
2825         .plane_tiled_memory_bandwidth_x2 = false,
2826 };
2827
2828 static const struct tegra_windowgroup_soc tegra194_dc_wgrps[] = {
2829         {
2830                 .index = 0,
2831                 .dc = 0,
2832                 .windows = (const unsigned int[]) { 0 },
2833                 .num_windows = 1,
2834         }, {
2835                 .index = 1,
2836                 .dc = 1,
2837                 .windows = (const unsigned int[]) { 1 },
2838                 .num_windows = 1,
2839         }, {
2840                 .index = 2,
2841                 .dc = 1,
2842                 .windows = (const unsigned int[]) { 2 },
2843                 .num_windows = 1,
2844         }, {
2845                 .index = 3,
2846                 .dc = 2,
2847                 .windows = (const unsigned int[]) { 3 },
2848                 .num_windows = 1,
2849         }, {
2850                 .index = 4,
2851                 .dc = 2,
2852                 .windows = (const unsigned int[]) { 4 },
2853                 .num_windows = 1,
2854         }, {
2855                 .index = 5,
2856                 .dc = 2,
2857                 .windows = (const unsigned int[]) { 5 },
2858                 .num_windows = 1,
2859         },
2860 };
2861
2862 static const struct tegra_dc_soc_info tegra194_dc_soc_info = {
2863         .supports_background_color = true,
2864         .supports_interlacing = true,
2865         .supports_cursor = true,
2866         .supports_block_linear = true,
2867         .supports_sector_layout = true,
2868         .has_legacy_blending = false,
2869         .pitch_align = 64,
2870         .has_powergate = false,
2871         .coupled_pm = false,
2872         .has_nvdisplay = true,
2873         .wgrps = tegra194_dc_wgrps,
2874         .num_wgrps = ARRAY_SIZE(tegra194_dc_wgrps),
2875         .plane_tiled_memory_bandwidth_x2 = false,
2876 };
2877
2878 static const struct of_device_id tegra_dc_of_match[] = {
2879         {
2880                 .compatible = "nvidia,tegra194-dc",
2881                 .data = &tegra194_dc_soc_info,
2882         }, {
2883                 .compatible = "nvidia,tegra186-dc",
2884                 .data = &tegra186_dc_soc_info,
2885         }, {
2886                 .compatible = "nvidia,tegra210-dc",
2887                 .data = &tegra210_dc_soc_info,
2888         }, {
2889                 .compatible = "nvidia,tegra124-dc",
2890                 .data = &tegra124_dc_soc_info,
2891         }, {
2892                 .compatible = "nvidia,tegra114-dc",
2893                 .data = &tegra114_dc_soc_info,
2894         }, {
2895                 .compatible = "nvidia,tegra30-dc",
2896                 .data = &tegra30_dc_soc_info,
2897         }, {
2898                 .compatible = "nvidia,tegra20-dc",
2899                 .data = &tegra20_dc_soc_info,
2900         }, {
2901                 /* sentinel */
2902         }
2903 };
2904 MODULE_DEVICE_TABLE(of, tegra_dc_of_match);
2905
2906 static int tegra_dc_parse_dt(struct tegra_dc *dc)
2907 {
2908         struct device_node *np;
2909         u32 value = 0;
2910         int err;
2911
2912         err = of_property_read_u32(dc->dev->of_node, "nvidia,head", &value);
2913         if (err < 0) {
2914                 dev_err(dc->dev, "missing \"nvidia,head\" property\n");
2915
2916                 /*
2917                  * If the nvidia,head property isn't present, try to find the
2918                  * correct head number by looking up the position of this
2919                  * display controller's node within the device tree. Assuming
2920                  * that the nodes are ordered properly in the DTS file and
2921                  * that the translation into a flattened device tree blob
2922                  * preserves that ordering this will actually yield the right
2923                  * head number.
2924                  *
2925                  * If those assumptions don't hold, this will still work for
2926                  * cases where only a single display controller is used.
2927                  */
2928                 for_each_matching_node(np, tegra_dc_of_match) {
2929                         if (np == dc->dev->of_node) {
2930                                 of_node_put(np);
2931                                 break;
2932                         }
2933
2934                         value++;
2935                 }
2936         }
2937
2938         dc->pipe = value;
2939
2940         return 0;
2941 }
2942
2943 static int tegra_dc_match_by_pipe(struct device *dev, const void *data)
2944 {
2945         struct tegra_dc *dc = dev_get_drvdata(dev);
2946         unsigned int pipe = (unsigned long)(void *)data;
2947
2948         return dc->pipe == pipe;
2949 }
2950
2951 static int tegra_dc_couple(struct tegra_dc *dc)
2952 {
2953         /*
2954          * On Tegra20, DC1 requires DC0 to be taken out of reset in order to
2955          * be enabled, otherwise CPU hangs on writing to CMD_DISPLAY_COMMAND /
2956          * POWER_CONTROL registers during CRTC enabling.
2957          */
2958         if (dc->soc->coupled_pm && dc->pipe == 1) {
2959                 struct device *companion;
2960                 struct tegra_dc *parent;
2961
2962                 companion = driver_find_device(dc->dev->driver, NULL, (const void *)0,
2963                                                tegra_dc_match_by_pipe);
2964                 if (!companion)
2965                         return -EPROBE_DEFER;
2966
2967                 parent = dev_get_drvdata(companion);
2968                 dc->client.parent = &parent->client;
2969
2970                 dev_dbg(dc->dev, "coupled to %s\n", dev_name(companion));
2971         }
2972
2973         return 0;
2974 }
2975
2976 static int tegra_dc_probe(struct platform_device *pdev)
2977 {
2978         u64 dma_mask = dma_get_mask(pdev->dev.parent);
2979         struct tegra_dc *dc;
2980         int err;
2981
2982         err = dma_coerce_mask_and_coherent(&pdev->dev, dma_mask);
2983         if (err < 0) {
2984                 dev_err(&pdev->dev, "failed to set DMA mask: %d\n", err);
2985                 return err;
2986         }
2987
2988         dc = devm_kzalloc(&pdev->dev, sizeof(*dc), GFP_KERNEL);
2989         if (!dc)
2990                 return -ENOMEM;
2991
2992         dc->soc = of_device_get_match_data(&pdev->dev);
2993
2994         INIT_LIST_HEAD(&dc->list);
2995         dc->dev = &pdev->dev;
2996
2997         err = tegra_dc_parse_dt(dc);
2998         if (err < 0)
2999                 return err;
3000
3001         err = tegra_dc_couple(dc);
3002         if (err < 0)
3003                 return err;
3004
3005         dc->clk = devm_clk_get(&pdev->dev, NULL);
3006         if (IS_ERR(dc->clk)) {
3007                 dev_err(&pdev->dev, "failed to get clock\n");
3008                 return PTR_ERR(dc->clk);
3009         }
3010
3011         dc->rst = devm_reset_control_get(&pdev->dev, "dc");
3012         if (IS_ERR(dc->rst)) {
3013                 dev_err(&pdev->dev, "failed to get reset\n");
3014                 return PTR_ERR(dc->rst);
3015         }
3016
3017         /* assert reset and disable clock */
3018         err = clk_prepare_enable(dc->clk);
3019         if (err < 0)
3020                 return err;
3021
3022         usleep_range(2000, 4000);
3023
3024         err = reset_control_assert(dc->rst);
3025         if (err < 0)
3026                 return err;
3027
3028         usleep_range(2000, 4000);
3029
3030         clk_disable_unprepare(dc->clk);
3031
3032         if (dc->soc->has_powergate) {
3033                 if (dc->pipe == 0)
3034                         dc->powergate = TEGRA_POWERGATE_DIS;
3035                 else
3036                         dc->powergate = TEGRA_POWERGATE_DISB;
3037
3038                 tegra_powergate_power_off(dc->powergate);
3039         }
3040
3041         dc->regs = devm_platform_ioremap_resource(pdev, 0);
3042         if (IS_ERR(dc->regs))
3043                 return PTR_ERR(dc->regs);
3044
3045         dc->irq = platform_get_irq(pdev, 0);
3046         if (dc->irq < 0)
3047                 return -ENXIO;
3048
3049         err = tegra_dc_rgb_probe(dc);
3050         if (err < 0 && err != -ENODEV) {
3051                 const char *level = KERN_ERR;
3052
3053                 if (err == -EPROBE_DEFER)
3054                         level = KERN_DEBUG;
3055
3056                 dev_printk(level, dc->dev, "failed to probe RGB output: %d\n",
3057                            err);
3058                 return err;
3059         }
3060
3061         platform_set_drvdata(pdev, dc);
3062         pm_runtime_enable(&pdev->dev);
3063
3064         INIT_LIST_HEAD(&dc->client.list);
3065         dc->client.ops = &dc_client_ops;
3066         dc->client.dev = &pdev->dev;
3067
3068         err = host1x_client_register(&dc->client);
3069         if (err < 0) {
3070                 dev_err(&pdev->dev, "failed to register host1x client: %d\n",
3071                         err);
3072                 goto disable_pm;
3073         }
3074
3075         return 0;
3076
3077 disable_pm:
3078         pm_runtime_disable(&pdev->dev);
3079         tegra_dc_rgb_remove(dc);
3080
3081         return err;
3082 }
3083
3084 static int tegra_dc_remove(struct platform_device *pdev)
3085 {
3086         struct tegra_dc *dc = platform_get_drvdata(pdev);
3087         int err;
3088
3089         err = host1x_client_unregister(&dc->client);
3090         if (err < 0) {
3091                 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
3092                         err);
3093                 return err;
3094         }
3095
3096         err = tegra_dc_rgb_remove(dc);
3097         if (err < 0) {
3098                 dev_err(&pdev->dev, "failed to remove RGB output: %d\n", err);
3099                 return err;
3100         }
3101
3102         pm_runtime_disable(&pdev->dev);
3103
3104         return 0;
3105 }
3106
3107 struct platform_driver tegra_dc_driver = {
3108         .driver = {
3109                 .name = "tegra-dc",
3110                 .of_match_table = tegra_dc_of_match,
3111         },
3112         .probe = tegra_dc_probe,
3113         .remove = tegra_dc_remove,
3114 };