2 * Copyright (C) STMicroelectronics SA 2017
4 * Authors: Philippe Cornu <philippe.cornu@st.com>
5 * Yannick Fertre <yannick.fertre@st.com>
7 * License terms: GNU General Public License (GPL), version 2
10 #include <linux/clk.h>
11 #include <linux/iopoll.h>
12 #include <linux/module.h>
14 #include <drm/drm_mipi_dsi.h>
15 #include <drm/bridge/dw_mipi_dsi.h>
16 #include <video/mipi_display.h>
18 /* DSI wrapper register & bit definitions */
19 /* Note: registers are named as in the Reference Manual */
20 #define DSI_WCFGR 0x0400 /* Wrapper ConFiGuration Reg */
21 #define WCFGR_DSIM BIT(0) /* DSI Mode */
22 #define WCFGR_COLMUX GENMASK(3, 1) /* COLor MUltipleXing */
24 #define DSI_WCR 0x0404 /* Wrapper Control Reg */
25 #define WCR_DSIEN BIT(3) /* DSI ENable */
27 #define DSI_WISR 0x040C /* Wrapper Interrupt and Status Reg */
28 #define WISR_PLLLS BIT(8) /* PLL Lock Status */
29 #define WISR_RRS BIT(12) /* Regulator Ready Status */
31 #define DSI_WPCR0 0x0418 /* Wrapper Phy Conf Reg 0 */
32 #define WPCR0_UIX4 GENMASK(5, 0) /* Unit Interval X 4 */
33 #define WPCR0_TDDL BIT(16) /* Turn Disable Data Lanes */
35 #define DSI_WRPCR 0x0430 /* Wrapper Regulator & Pll Ctrl Reg */
36 #define WRPCR_PLLEN BIT(0) /* PLL ENable */
37 #define WRPCR_NDIV GENMASK(8, 2) /* pll loop DIVision Factor */
38 #define WRPCR_IDF GENMASK(14, 11) /* pll Input Division Factor */
39 #define WRPCR_ODF GENMASK(17, 16) /* pll Output Division Factor */
40 #define WRPCR_REGEN BIT(24) /* REGulator ENable */
41 #define WRPCR_BGREN BIT(28) /* BandGap Reference ENable */
49 /* dsi color format coding according to the datasheet */
59 #define LANE_MIN_KBPS 31250
60 #define LANE_MAX_KBPS 500000
62 /* Sleep & timeout for regulator on/off, pll lock/unlock & fifo empty */
64 #define TIMEOUT_US 200000
66 struct dw_mipi_dsi_stm {
68 struct clk *pllref_clk;
71 static inline void dsi_write(struct dw_mipi_dsi_stm *dsi, u32 reg, u32 val)
73 writel(val, dsi->base + reg);
76 static inline u32 dsi_read(struct dw_mipi_dsi_stm *dsi, u32 reg)
78 return readl(dsi->base + reg);
81 static inline void dsi_set(struct dw_mipi_dsi_stm *dsi, u32 reg, u32 mask)
83 dsi_write(dsi, reg, dsi_read(dsi, reg) | mask);
86 static inline void dsi_clear(struct dw_mipi_dsi_stm *dsi, u32 reg, u32 mask)
88 dsi_write(dsi, reg, dsi_read(dsi, reg) & ~mask);
91 static inline void dsi_update_bits(struct dw_mipi_dsi_stm *dsi, u32 reg,
94 dsi_write(dsi, reg, (dsi_read(dsi, reg) & ~mask) | val);
97 static enum dsi_color dsi_color_from_mipi(enum mipi_dsi_pixel_format fmt)
100 case MIPI_DSI_FMT_RGB888:
102 case MIPI_DSI_FMT_RGB666:
103 return DSI_RGB666_CONF2;
104 case MIPI_DSI_FMT_RGB666_PACKED:
105 return DSI_RGB666_CONF1;
106 case MIPI_DSI_FMT_RGB565:
107 return DSI_RGB565_CONF1;
109 DRM_DEBUG_DRIVER("MIPI color invalid, so we use rgb888\n");
114 static int dsi_pll_get_clkout_khz(int clkin_khz, int idf, int ndiv, int odf)
116 /* prevent from division by 0 */
118 return DIV_ROUND_CLOSEST(clkin_khz * ndiv, idf * odf);
123 static int dsi_pll_get_params(int clkin_khz, int clkout_khz,
124 int *idf, int *ndiv, int *odf)
126 int i, o, n, n_min, n_max;
127 int fvco_min, fvco_max, delta, best_delta; /* all in khz */
129 /* Early checks preventing division by 0 & odd results */
130 if ((clkin_khz <= 0) || (clkout_khz <= 0))
133 fvco_min = LANE_MIN_KBPS * 2 * ODF_MAX;
134 fvco_max = LANE_MAX_KBPS * 2 * ODF_MIN;
136 best_delta = 1000000; /* big started value (1000000khz) */
138 for (i = IDF_MIN; i <= IDF_MAX; i++) {
139 /* Compute ndiv range according to Fvco */
140 n_min = ((fvco_min * i) / (2 * clkin_khz)) + 1;
141 n_max = (fvco_max * i) / (2 * clkin_khz);
143 /* No need to continue idf loop if we reach ndiv max */
144 if (n_min >= NDIV_MAX)
147 /* Clamp ndiv to valid values */
148 if (n_min < NDIV_MIN)
150 if (n_max > NDIV_MAX)
153 for (o = ODF_MIN; o <= ODF_MAX; o *= 2) {
154 n = DIV_ROUND_CLOSEST(i * o * clkout_khz, clkin_khz);
155 /* Check ndiv according to vco range */
156 if ((n < n_min) || (n > n_max))
158 /* Check if new delta is better & saves parameters */
159 delta = dsi_pll_get_clkout_khz(clkin_khz, i, n, o) -
163 if (delta < best_delta) {
169 /* fast return in case of "perfect result" */
178 static int dw_mipi_dsi_phy_init(void *priv_data)
180 struct dw_mipi_dsi_stm *dsi = priv_data;
184 /* Enable the regulator */
185 dsi_set(dsi, DSI_WRPCR, WRPCR_REGEN | WRPCR_BGREN);
186 ret = readl_poll_timeout(dsi->base + DSI_WISR, val, val & WISR_RRS,
187 SLEEP_US, TIMEOUT_US);
189 DRM_DEBUG_DRIVER("!TIMEOUT! waiting REGU, let's continue\n");
191 /* Enable the DSI PLL & wait for its lock */
192 dsi_set(dsi, DSI_WRPCR, WRPCR_PLLEN);
193 ret = readl_poll_timeout(dsi->base + DSI_WISR, val, val & WISR_PLLLS,
194 SLEEP_US, TIMEOUT_US);
196 DRM_DEBUG_DRIVER("!TIMEOUT! waiting PLL, let's continue\n");
198 /* Enable the DSI wrapper */
199 dsi_set(dsi, DSI_WCR, WCR_DSIEN);
205 dw_mipi_dsi_get_lane_mbps(void *priv_data, struct drm_display_mode *mode,
206 unsigned long mode_flags, u32 lanes, u32 format,
207 unsigned int *lane_mbps)
209 struct dw_mipi_dsi_stm *dsi = priv_data;
210 unsigned int idf, ndiv, odf, pll_in_khz, pll_out_khz;
214 pll_in_khz = (unsigned int)(clk_get_rate(dsi->pllref_clk) / 1000);
216 /* Compute requested pll out */
217 bpp = mipi_dsi_pixel_format_to_bpp(format);
218 pll_out_khz = mode->clock * bpp / lanes;
219 /* Add 20% to pll out to be higher than pixel bw (burst mode only) */
220 pll_out_khz = (pll_out_khz * 12) / 10;
221 if (pll_out_khz > LANE_MAX_KBPS) {
222 pll_out_khz = LANE_MAX_KBPS;
223 DRM_WARN("Warning max phy mbps is used\n");
225 if (pll_out_khz < LANE_MIN_KBPS) {
226 pll_out_khz = LANE_MIN_KBPS;
227 DRM_WARN("Warning min phy mbps is used\n");
230 /* Compute best pll parameters */
234 ret = dsi_pll_get_params(pll_in_khz, pll_out_khz, &idf, &ndiv, &odf);
236 DRM_WARN("Warning dsi_pll_get_params(): bad params\n");
238 /* Get the adjusted pll out value */
239 pll_out_khz = dsi_pll_get_clkout_khz(pll_in_khz, idf, ndiv, odf);
241 /* Set the PLL division factors */
242 dsi_update_bits(dsi, DSI_WRPCR, WRPCR_NDIV | WRPCR_IDF | WRPCR_ODF,
243 (ndiv << 2) | (idf << 11) | ((ffs(odf) - 1) << 16));
245 /* Compute uix4 & set the bit period in high-speed mode */
246 val = 4000000 / pll_out_khz;
247 dsi_update_bits(dsi, DSI_WPCR0, WPCR0_UIX4, val);
249 /* Select video mode by resetting DSIM bit */
250 dsi_clear(dsi, DSI_WCFGR, WCFGR_DSIM);
252 /* Select the color coding */
253 dsi_update_bits(dsi, DSI_WCFGR, WCFGR_COLMUX,
254 dsi_color_from_mipi(format) << 1);
256 *lane_mbps = pll_out_khz / 1000;
258 DRM_DEBUG_DRIVER("pll_in %ukHz pll_out %ukHz lane_mbps %uMHz\n",
259 pll_in_khz, pll_out_khz, *lane_mbps);
264 static const struct dw_mipi_dsi_phy_ops dw_mipi_dsi_stm_phy_ops = {
265 .init = dw_mipi_dsi_phy_init,
266 .get_lane_mbps = dw_mipi_dsi_get_lane_mbps,
269 static struct dw_mipi_dsi_plat_data dw_mipi_dsi_stm_plat_data = {
271 .phy_ops = &dw_mipi_dsi_stm_phy_ops,
274 static const struct of_device_id dw_mipi_dsi_stm_dt_ids[] = {
275 { .compatible = "st,stm32-dsi", .data = &dw_mipi_dsi_stm_plat_data, },
278 MODULE_DEVICE_TABLE(of, dw_mipi_dsi_stm_dt_ids);
280 static int dw_mipi_dsi_stm_probe(struct platform_device *pdev)
282 struct device *dev = &pdev->dev;
283 struct dw_mipi_dsi_stm *dsi;
284 struct resource *res;
287 dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);
291 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
293 DRM_ERROR("Unable to get resource\n");
297 dsi->base = devm_ioremap_resource(dev, res);
298 if (IS_ERR(dsi->base)) {
299 DRM_ERROR("Unable to get dsi registers\n");
300 return PTR_ERR(dsi->base);
303 dsi->pllref_clk = devm_clk_get(dev, "ref");
304 if (IS_ERR(dsi->pllref_clk)) {
305 ret = PTR_ERR(dsi->pllref_clk);
306 dev_err(dev, "Unable to get pll reference clock: %d\n", ret);
310 ret = clk_prepare_enable(dsi->pllref_clk);
312 dev_err(dev, "%s: Failed to enable pllref_clk\n", __func__);
316 dw_mipi_dsi_stm_plat_data.base = dsi->base;
317 dw_mipi_dsi_stm_plat_data.priv_data = dsi;
319 ret = dw_mipi_dsi_probe(pdev, &dw_mipi_dsi_stm_plat_data);
321 DRM_ERROR("Failed to initialize mipi dsi host\n");
322 clk_disable_unprepare(dsi->pllref_clk);
328 static int dw_mipi_dsi_stm_remove(struct platform_device *pdev)
330 struct dw_mipi_dsi_stm *dsi = dw_mipi_dsi_stm_plat_data.priv_data;
332 clk_disable_unprepare(dsi->pllref_clk);
333 dw_mipi_dsi_remove(pdev);
338 static struct platform_driver dw_mipi_dsi_stm_driver = {
339 .probe = dw_mipi_dsi_stm_probe,
340 .remove = dw_mipi_dsi_stm_remove,
342 .of_match_table = dw_mipi_dsi_stm_dt_ids,
343 .name = "dw_mipi_dsi-stm",
347 module_platform_driver(dw_mipi_dsi_stm_driver);
349 MODULE_AUTHOR("Philippe Cornu <philippe.cornu@st.com>");
350 MODULE_AUTHOR("Yannick Fertre <yannick.fertre@st.com>");
351 MODULE_DESCRIPTION("STMicroelectronics DW MIPI DSI host controller driver");
352 MODULE_LICENSE("GPL v2");