drivers/gpu/drm/sti/sti_hda.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) STMicroelectronics SA 2014
   4  * Author: Fabien Dessenne <fabien.dessenne@st.com> for STMicroelectronics.
   5  */
   6
   7 #include <linux/clk.h>
   8 #include <linux/component.h>
   9 #include <linux/io.h>
  10 #include <linux/mod_devicetable.h>
  11 #include <linux/module.h>
  12 #include <linux/platform_device.h>
  13 #include <linux/seq_file.h>
  14
  15 #include <drm/drm_atomic_helper.h>
  16 #include <drm/drm_bridge.h>
  17 #include <drm/drm_debugfs.h>
  18 #include <drm/drm_device.h>
  19 #include <drm/drm_file.h>
  20 #include <drm/drm_print.h>
  21 #include <drm/drm_probe_helper.h>
  22
  23 /* HDformatter registers */
  24 #define HDA_ANA_CFG                     0x0000
  25 #define HDA_ANA_SCALE_CTRL_Y            0x0004
  26 #define HDA_ANA_SCALE_CTRL_CB           0x0008
  27 #define HDA_ANA_SCALE_CTRL_CR           0x000C
  28 #define HDA_ANA_ANC_CTRL                0x0010
  29 #define HDA_ANA_SRC_Y_CFG               0x0014
  30 #define HDA_COEFF_Y_PH1_TAP123          0x0018
  31 #define HDA_COEFF_Y_PH1_TAP456          0x001C
  32 #define HDA_COEFF_Y_PH2_TAP123          0x0020
  33 #define HDA_COEFF_Y_PH2_TAP456          0x0024
  34 #define HDA_COEFF_Y_PH3_TAP123          0x0028
  35 #define HDA_COEFF_Y_PH3_TAP456          0x002C
  36 #define HDA_COEFF_Y_PH4_TAP123          0x0030
  37 #define HDA_COEFF_Y_PH4_TAP456          0x0034
  38 #define HDA_ANA_SRC_C_CFG               0x0040
  39 #define HDA_COEFF_C_PH1_TAP123          0x0044
  40 #define HDA_COEFF_C_PH1_TAP456          0x0048
  41 #define HDA_COEFF_C_PH2_TAP123          0x004C
  42 #define HDA_COEFF_C_PH2_TAP456          0x0050
  43 #define HDA_COEFF_C_PH3_TAP123          0x0054
  44 #define HDA_COEFF_C_PH3_TAP456          0x0058
  45 #define HDA_COEFF_C_PH4_TAP123          0x005C
  46 #define HDA_COEFF_C_PH4_TAP456          0x0060
  47 #define HDA_SYNC_AWGI                   0x0300
  48
  49 /* HDA_ANA_CFG */
  50 #define CFG_AWG_ASYNC_EN                BIT(0)
  51 #define CFG_AWG_ASYNC_HSYNC_MTD         BIT(1)
  52 #define CFG_AWG_ASYNC_VSYNC_MTD         BIT(2)
  53 #define CFG_AWG_SYNC_DEL                BIT(3)
  54 #define CFG_AWG_FLTR_MODE_SHIFT         4
  55 #define CFG_AWG_FLTR_MODE_MASK          (0xF << CFG_AWG_FLTR_MODE_SHIFT)
  56 #define CFG_AWG_FLTR_MODE_SD            (0 << CFG_AWG_FLTR_MODE_SHIFT)
  57 #define CFG_AWG_FLTR_MODE_ED            (1 << CFG_AWG_FLTR_MODE_SHIFT)
  58 #define CFG_AWG_FLTR_MODE_HD            (2 << CFG_AWG_FLTR_MODE_SHIFT)
  59 #define CFG_SYNC_ON_PBPR_MASK           BIT(8)
  60 #define CFG_PREFILTER_EN_MASK           BIT(9)
  61 #define CFG_PBPR_SYNC_OFF_SHIFT         16
  62 #define CFG_PBPR_SYNC_OFF_MASK          (0x7FF << CFG_PBPR_SYNC_OFF_SHIFT)
  63 #define CFG_PBPR_SYNC_OFF_VAL           0x117 /* Voltage dependent. stiH416 */
  64
  65 /* Default scaling values */
  66 #define SCALE_CTRL_Y_DFLT               0x00C50256
  67 #define SCALE_CTRL_CB_DFLT              0x00DB0249
  68 #define SCALE_CTRL_CR_DFLT              0x00DB0249
  69
  70 /* Video DACs control */
  71 #define DAC_CFG_HD_HZUVW_OFF_MASK       BIT(1)
  72
  73 /* Upsampler values for the alternative 2X Filter */
  74 #define SAMPLER_COEF_NB                 8
  75 #define HDA_ANA_SRC_Y_CFG_ALT_2X        0x01130000
  76 static u32 coef_y_alt_2x[] = {
  77         0x00FE83FB, 0x1F900401, 0x00000000, 0x00000000,
  78         0x00F408F9, 0x055F7C25, 0x00000000, 0x00000000
  79 };
  80
  81 #define HDA_ANA_SRC_C_CFG_ALT_2X        0x01750004
  82 static u32 coef_c_alt_2x[] = {
  83         0x001305F7, 0x05274BD0, 0x00000000, 0x00000000,
  84         0x0004907C, 0x09C80B9D, 0x00000000, 0x00000000
  85 };
  86
  87 /* Upsampler values for the 4X Filter */
  88 #define HDA_ANA_SRC_Y_CFG_4X            0x01ED0005
  89 #define HDA_ANA_SRC_C_CFG_4X            0x01ED0004
  90 static u32 coef_yc_4x[] = {
  91         0x00FC827F, 0x008FE20B, 0x00F684FC, 0x050F7C24,
  92         0x00F4857C, 0x0A1F402E, 0x00FA027F, 0x0E076E1D
  93 };
  94
  95 /* AWG instructions for some video modes */
  96 #define AWG_MAX_INST                    64
  97
  98 /* 720p@50 */
  99 static u32 AWGi_720p_50[] = {
 100         0x00000971, 0x00000C26, 0x0000013B, 0x00000CDA,
 101         0x00000104, 0x00000E7E, 0x00000E7F, 0x0000013B,
 102         0x00000D8E, 0x00000104, 0x00001804, 0x00000971,
 103         0x00000C26, 0x0000003B, 0x00000FB4, 0x00000FB5,
 104         0x00000104, 0x00001AE8
 105 };
 106
 107 #define NN_720p_50 ARRAY_SIZE(AWGi_720p_50)
 108
 109 /* 720p@60 */
 110 static u32 AWGi_720p_60[] = {
 111         0x00000971, 0x00000C26, 0x0000013B, 0x00000CDA,
 112         0x00000104, 0x00000E7E, 0x00000E7F, 0x0000013B,
 113         0x00000C44, 0x00000104, 0x00001804, 0x00000971,
 114         0x00000C26, 0x0000003B, 0x00000F0F, 0x00000F10,
 115         0x00000104, 0x00001AE8
 116 };
 117
 118 #define NN_720p_60 ARRAY_SIZE(AWGi_720p_60)
 119
 120 /* 1080p@30 */
 121 static u32 AWGi_1080p_30[] = {
 122         0x00000971, 0x00000C2A, 0x0000013B, 0x00000C56,
 123         0x00000104, 0x00000FDC, 0x00000FDD, 0x0000013B,
 124         0x00000C2A, 0x00000104, 0x00001804, 0x00000971,
 125         0x00000C2A, 0x0000003B, 0x00000EBE, 0x00000EBF,
 126         0x00000EBF, 0x00000104, 0x00001A2F, 0x00001C4B,
 127         0x00001C52
 128 };
 129
 130 #define NN_1080p_30 ARRAY_SIZE(AWGi_1080p_30)
 131
 132 /* 1080p@25 */
 133 static u32 AWGi_1080p_25[] = {
 134         0x00000971, 0x00000C2A, 0x0000013B, 0x00000C56,
 135         0x00000104, 0x00000FDC, 0x00000FDD, 0x0000013B,
 136         0x00000DE2, 0x00000104, 0x00001804, 0x00000971,
 137         0x00000C2A, 0x0000003B, 0x00000F51, 0x00000F51,
 138         0x00000F52, 0x00000104, 0x00001A2F, 0x00001C4B,
 139         0x00001C52
 140 };
 141
 142 #define NN_1080p_25 ARRAY_SIZE(AWGi_1080p_25)
 143
 144 /* 1080p@24 */
 145 static u32 AWGi_1080p_24[] = {
 146         0x00000971, 0x00000C2A, 0x0000013B, 0x00000C56,
 147         0x00000104, 0x00000FDC, 0x00000FDD, 0x0000013B,
 148         0x00000E50, 0x00000104, 0x00001804, 0x00000971,
 149         0x00000C2A, 0x0000003B, 0x00000F76, 0x00000F76,
 150         0x00000F76, 0x00000104, 0x00001A2F, 0x00001C4B,
 151         0x00001C52
 152 };
 153
 154 #define NN_1080p_24 ARRAY_SIZE(AWGi_1080p_24)
 155
 156 /* 720x480p@60 */
 157 static u32 AWGi_720x480p_60[] = {
 158         0x00000904, 0x00000F18, 0x0000013B, 0x00001805,
 159         0x00000904, 0x00000C3D, 0x0000003B, 0x00001A06
 160 };
 161
 162 #define NN_720x480p_60 ARRAY_SIZE(AWGi_720x480p_60)
 163
 164 /* Video mode category */
 165 enum sti_hda_vid_cat {
 166         VID_SD,
 167         VID_ED,
 168         VID_HD_74M,
 169         VID_HD_148M
 170 };
 171
 172 struct sti_hda_video_config {
 173         struct drm_display_mode mode;
 174         u32 *awg_instr;
 175         int nb_instr;
 176         enum sti_hda_vid_cat vid_cat;
 177 };
 178
 179 /* HD analog supported modes
 180  * Interlaced modes may be added when supported by the whole display chain
 181  */
 182 static const struct sti_hda_video_config hda_supported_modes[] = {
 183         /* 1080p30 74.250Mhz */
 184         {{DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
 185                    2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
 186                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC)},
 187          AWGi_1080p_30, NN_1080p_30, VID_HD_74M},
 188         /* 1080p30 74.176Mhz */
 189         {{DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74176, 1920, 2008,
 190                    2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
 191                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC)},
 192          AWGi_1080p_30, NN_1080p_30, VID_HD_74M},
 193         /* 1080p24 74.250Mhz */
 194         {{DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
 195                    2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
 196                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC)},
 197          AWGi_1080p_24, NN_1080p_24, VID_HD_74M},
 198         /* 1080p24 74.176Mhz */
 199         {{DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74176, 1920, 2558,
 200                    2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
 201                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC)},
 202          AWGi_1080p_24, NN_1080p_24, VID_HD_74M},
 203         /* 1080p25 74.250Mhz */
 204         {{DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
 205                    2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
 206                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC)},
 207          AWGi_1080p_25, NN_1080p_25, VID_HD_74M},
 208         /* 720p60 74.250Mhz */
 209         {{DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
 210                    1430, 1650, 0, 720, 725, 730, 750, 0,
 211                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC)},
 212          AWGi_720p_60, NN_720p_60, VID_HD_74M},
 213         /* 720p60 74.176Mhz */
 214         {{DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74176, 1280, 1390,
 215                    1430, 1650, 0, 720, 725, 730, 750, 0,
 216                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC)},
 217          AWGi_720p_60, NN_720p_60, VID_HD_74M},
 218         /* 720p50 74.250Mhz */
 219         {{DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
 220                    1760, 1980, 0, 720, 725, 730, 750, 0,
 221                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC)},
 222          AWGi_720p_50, NN_720p_50, VID_HD_74M},
 223         /* 720x480p60 27.027Mhz */
 224         {{DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27027, 720, 736,
 225                    798, 858, 0, 480, 489, 495, 525, 0,
 226                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC)},
 227          AWGi_720x480p_60, NN_720x480p_60, VID_ED},
 228         /* 720x480p60 27.000Mhz */
 229         {{DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
 230                    798, 858, 0, 480, 489, 495, 525, 0,
 231                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC)},
 232          AWGi_720x480p_60, NN_720x480p_60, VID_ED}
 233 };
 234
 235 /*
 236  * STI hd analog structure
 237  *
 238  * @dev: driver device
 239  * @drm_dev: pointer to drm device
 240  * @mode: current display mode selected
 241  * @regs: HD analog register
 242  * @video_dacs_ctrl: video DACS control register
 243  * @enabled: true if HD analog is enabled else false
 244  */
 245 struct sti_hda {
 246         struct device dev;
 247         struct drm_device *drm_dev;
 248         struct drm_display_mode mode;
 249         void __iomem *regs;
 250         void __iomem *video_dacs_ctrl;
 251         struct clk *clk_pix;
 252         struct clk *clk_hddac;
 253         bool enabled;
 254 };
 255
 256 struct sti_hda_connector {
 257         struct drm_connector drm_connector;
 258         struct drm_encoder *encoder;
 259         struct sti_hda *hda;
 260 };
 261
 262 #define to_sti_hda_connector(x) \
 263         container_of(x, struct sti_hda_connector, drm_connector)
 264
 265 static u32 hda_read(struct sti_hda *hda, int offset)
 266 {
 267         return readl(hda->regs + offset);
 268 }
 269
 270 static void hda_write(struct sti_hda *hda, u32 val, int offset)
 271 {
 272         writel(val, hda->regs + offset);
 273 }
 274
 275 /**
 276  * hda_get_mode_idx - Search for a video mode in the supported modes table
 277  *
 278  * @mode: mode being searched
 279  * @idx: index of the found mode
 280  *
 281  * Return true if mode is found
 282  */
 283 static bool hda_get_mode_idx(struct drm_display_mode mode, int *idx)
 284 {
 285         unsigned int i;
 286
 287         for (i = 0; i < ARRAY_SIZE(hda_supported_modes); i++)
 288                 if (drm_mode_equal(&hda_supported_modes[i].mode, &mode)) {
 289                         *idx = i;
 290                         return true;
 291                 }
 292         return false;
 293 }
 294
 295 /**
 296  * hda_enable_hd_dacs - Enable the HD DACS
 297  *
 298  * @hda: pointer to HD analog structure
 299  * @enable: true if HD DACS need to be enabled, else false
 300  */
 301 static void hda_enable_hd_dacs(struct sti_hda *hda, bool enable)
 302 {
 303         if (hda->video_dacs_ctrl) {
 304                 u32 val;
 305
 306                 val = readl(hda->video_dacs_ctrl);
 307                 if (enable)
 308                         val &= ~DAC_CFG_HD_HZUVW_OFF_MASK;
 309                 else
 310                         val |= DAC_CFG_HD_HZUVW_OFF_MASK;
 311
 312                 writel(val, hda->video_dacs_ctrl);
 313         }
 314 }
 315
 316 #define DBGFS_DUMP(reg) seq_printf(s, "\n  %-25s 0x%08X", #reg, \
 317                                    readl(hda->regs + reg))
 318
 319 static void hda_dbg_cfg(struct seq_file *s, int val)
 320 {
 321         seq_puts(s, "\tAWG ");
 322         seq_puts(s, val & CFG_AWG_ASYNC_EN ? "enabled" : "disabled");
 323 }
 324
 325 static void hda_dbg_awg_microcode(struct seq_file *s, void __iomem *reg)
 326 {
 327         unsigned int i;
 328
 329         seq_puts(s, "\n\n  HDA AWG microcode:");
 330         for (i = 0; i < AWG_MAX_INST; i++) {
 331                 if (i % 8 == 0)
 332                         seq_printf(s, "\n  %04X:", i);
 333                 seq_printf(s, " %04X", readl(reg + i * 4));
 334         }
 335 }
 336
 337 static void hda_dbg_video_dacs_ctrl(struct seq_file *s, void __iomem *reg)
 338 {
 339         u32 val = readl(reg);
 340
 341         seq_printf(s, "\n\n  %-25s 0x%08X", "VIDEO_DACS_CONTROL", val);
 342         seq_puts(s, "\tHD DACs ");
 343         seq_puts(s, val & DAC_CFG_HD_HZUVW_OFF_MASK ? "disabled" : "enabled");
 344 }
 345
 346 static int hda_dbg_show(struct seq_file *s, void *data)
 347 {
 348         struct drm_info_node *node = s->private;
 349         struct sti_hda *hda = (struct sti_hda *)node->info_ent->data;
 350
 351         seq_printf(s, "HD Analog: (vaddr = 0x%p)", hda->regs);
 352         DBGFS_DUMP(HDA_ANA_CFG);
 353         hda_dbg_cfg(s, readl(hda->regs + HDA_ANA_CFG));
 354         DBGFS_DUMP(HDA_ANA_SCALE_CTRL_Y);
 355         DBGFS_DUMP(HDA_ANA_SCALE_CTRL_CB);
 356         DBGFS_DUMP(HDA_ANA_SCALE_CTRL_CR);
 357         DBGFS_DUMP(HDA_ANA_ANC_CTRL);
 358         DBGFS_DUMP(HDA_ANA_SRC_Y_CFG);
 359         DBGFS_DUMP(HDA_ANA_SRC_C_CFG);
 360         hda_dbg_awg_microcode(s, hda->regs + HDA_SYNC_AWGI);
 361         if (hda->video_dacs_ctrl)
 362                 hda_dbg_video_dacs_ctrl(s, hda->video_dacs_ctrl);
 363         seq_putc(s, '\n');
 364         return 0;
 365 }
 366
 367 static struct drm_info_list hda_debugfs_files[] = {
 368         { "hda", hda_dbg_show, 0, NULL },
 369 };
 370
 371 static void hda_debugfs_init(struct sti_hda *hda, struct drm_minor *minor)
 372 {
 373         unsigned int i;
 374
 375         for (i = 0; i < ARRAY_SIZE(hda_debugfs_files); i++)
 376                 hda_debugfs_files[i].data = hda;
 377
 378         drm_debugfs_create_files(hda_debugfs_files,
 379                                  ARRAY_SIZE(hda_debugfs_files),
 380                                  minor->debugfs_root, minor);
 381 }
 382
 383 /**
 384  * sti_hda_configure_awg - Configure AWG, writing instructions
 385  *
 386  * @hda: pointer to HD analog structure
 387  * @awg_instr: pointer to AWG instructions table
 388  * @nb: nb of AWG instructions
 389  */
 390 static void sti_hda_configure_awg(struct sti_hda *hda, u32 *awg_instr, int nb)
 391 {
 392         unsigned int i;
 393
 394         DRM_DEBUG_DRIVER("\n");
 395
 396         for (i = 0; i < nb; i++)
 397                 hda_write(hda, awg_instr[i], HDA_SYNC_AWGI + i * 4);
 398         for (i = nb; i < AWG_MAX_INST; i++)
 399                 hda_write(hda, 0, HDA_SYNC_AWGI + i * 4);
 400 }
 401
 402 static void sti_hda_disable(struct drm_bridge *bridge)
 403 {
 404         struct sti_hda *hda = bridge->driver_private;
 405         u32 val;
 406
 407         if (!hda->enabled)
 408                 return;
 409
 410         DRM_DEBUG_DRIVER("\n");
 411
 412         /* Disable HD DAC and AWG */
 413         val = hda_read(hda, HDA_ANA_CFG);
 414         val &= ~CFG_AWG_ASYNC_EN;
 415         hda_write(hda, val, HDA_ANA_CFG);
 416         hda_write(hda, 0, HDA_ANA_ANC_CTRL);
 417
 418         hda_enable_hd_dacs(hda, false);
 419
 420         /* Disable/unprepare hda clock */
 421         clk_disable_unprepare(hda->clk_hddac);
 422         clk_disable_unprepare(hda->clk_pix);
 423
 424         hda->enabled = false;
 425 }
 426
 427 static void sti_hda_pre_enable(struct drm_bridge *bridge)
 428 {
 429         struct sti_hda *hda = bridge->driver_private;
 430         u32 val, i, mode_idx;
 431         u32 src_filter_y, src_filter_c;
 432         u32 *coef_y, *coef_c;
 433         u32 filter_mode;
 434
 435         DRM_DEBUG_DRIVER("\n");
 436
 437         if (hda->enabled)
 438                 return;
 439
 440         /* Prepare/enable clocks */
 441         if (clk_prepare_enable(hda->clk_pix))
 442                 DRM_ERROR("Failed to prepare/enable hda_pix clk\n");
 443         if (clk_prepare_enable(hda->clk_hddac))
 444                 DRM_ERROR("Failed to prepare/enable hda_hddac clk\n");
 445
 446         if (!hda_get_mode_idx(hda->mode, &mode_idx)) {
 447                 DRM_ERROR("Undefined mode\n");
 448                 return;
 449         }
 450
 451         switch (hda_supported_modes[mode_idx].vid_cat) {
 452         case VID_HD_148M:
 453                 DRM_ERROR("Beyond HD analog capabilities\n");
 454                 return;
 455         case VID_HD_74M:
 456                 /* HD use alternate 2x filter */
 457                 filter_mode = CFG_AWG_FLTR_MODE_HD;
 458                 src_filter_y = HDA_ANA_SRC_Y_CFG_ALT_2X;
 459                 src_filter_c = HDA_ANA_SRC_C_CFG_ALT_2X;
 460                 coef_y = coef_y_alt_2x;
 461                 coef_c = coef_c_alt_2x;
 462                 break;
 463         case VID_ED:
 464                 /* ED uses 4x filter */
 465                 filter_mode = CFG_AWG_FLTR_MODE_ED;
 466                 src_filter_y = HDA_ANA_SRC_Y_CFG_4X;
 467                 src_filter_c = HDA_ANA_SRC_C_CFG_4X;
 468                 coef_y = coef_yc_4x;
 469                 coef_c = coef_yc_4x;
 470                 break;
 471         case VID_SD:
 472                 DRM_ERROR("Not supported\n");
 473                 return;
 474         default:
 475                 DRM_ERROR("Undefined resolution\n");
 476                 return;
 477         }
 478         DRM_DEBUG_DRIVER("Using HDA mode #%d\n", mode_idx);
 479
 480         /* Enable HD Video DACs */
 481         hda_enable_hd_dacs(hda, true);
 482
 483         /* Configure scaler */
 484         hda_write(hda, SCALE_CTRL_Y_DFLT, HDA_ANA_SCALE_CTRL_Y);
 485         hda_write(hda, SCALE_CTRL_CB_DFLT, HDA_ANA_SCALE_CTRL_CB);
 486         hda_write(hda, SCALE_CTRL_CR_DFLT, HDA_ANA_SCALE_CTRL_CR);
 487
 488         /* Configure sampler */
 489         hda_write(hda , src_filter_y, HDA_ANA_SRC_Y_CFG);
 490         hda_write(hda, src_filter_c,  HDA_ANA_SRC_C_CFG);
 491         for (i = 0; i < SAMPLER_COEF_NB; i++) {
 492                 hda_write(hda, coef_y[i], HDA_COEFF_Y_PH1_TAP123 + i * 4);
 493                 hda_write(hda, coef_c[i], HDA_COEFF_C_PH1_TAP123 + i * 4);
 494         }
 495
 496         /* Configure main HDFormatter */
 497         val = 0;
 498         val |= (hda->mode.flags & DRM_MODE_FLAG_INTERLACE) ?
 499             0 : CFG_AWG_ASYNC_VSYNC_MTD;
 500         val |= (CFG_PBPR_SYNC_OFF_VAL << CFG_PBPR_SYNC_OFF_SHIFT);
 501         val |= filter_mode;
 502         hda_write(hda, val, HDA_ANA_CFG);
 503
 504         /* Configure AWG */
 505         sti_hda_configure_awg(hda, hda_supported_modes[mode_idx].awg_instr,
 506                               hda_supported_modes[mode_idx].nb_instr);
 507
 508         /* Enable AWG */
 509         val = hda_read(hda, HDA_ANA_CFG);
 510         val |= CFG_AWG_ASYNC_EN;
 511         hda_write(hda, val, HDA_ANA_CFG);
 512
 513         hda->enabled = true;
 514 }
 515
 516 static void sti_hda_set_mode(struct drm_bridge *bridge,
 517                              const struct drm_display_mode *mode,
 518                              const struct drm_display_mode *adjusted_mode)
 519 {
 520         struct sti_hda *hda = bridge->driver_private;
 521         u32 mode_idx;
 522         int hddac_rate;
 523         int ret;
 524
 525         DRM_DEBUG_DRIVER("\n");
 526
 527         drm_mode_copy(&hda->mode, mode);
 528
 529         if (!hda_get_mode_idx(hda->mode, &mode_idx)) {
 530                 DRM_ERROR("Undefined mode\n");
 531                 return;
 532         }
 533
 534         switch (hda_supported_modes[mode_idx].vid_cat) {
 535         case VID_HD_74M:
 536                 /* HD use alternate 2x filter */
 537                 hddac_rate = mode->clock * 1000 * 2;
 538                 break;
 539         case VID_ED:
 540                 /* ED uses 4x filter */
 541                 hddac_rate = mode->clock * 1000 * 4;
 542                 break;
 543         default:
 544                 DRM_ERROR("Undefined mode\n");
 545                 return;
 546         }
 547
 548         /* HD DAC = 148.5Mhz or 108 Mhz */
 549         ret = clk_set_rate(hda->clk_hddac, hddac_rate);
 550         if (ret < 0)
 551                 DRM_ERROR("Cannot set rate (%dHz) for hda_hddac clk\n",
 552                           hddac_rate);
 553
 554         /* HDformatter clock = compositor clock */
 555         ret = clk_set_rate(hda->clk_pix, mode->clock * 1000);
 556         if (ret < 0)
 557                 DRM_ERROR("Cannot set rate (%dHz) for hda_pix clk\n",
 558                           mode->clock * 1000);
 559 }
 560
 561 static void sti_hda_bridge_nope(struct drm_bridge *bridge)
 562 {
 563         /* do nothing */
 564 }
 565
 566 static const struct drm_bridge_funcs sti_hda_bridge_funcs = {
 567         .pre_enable = sti_hda_pre_enable,
 568         .enable = sti_hda_bridge_nope,
 569         .disable = sti_hda_disable,
 570         .post_disable = sti_hda_bridge_nope,
 571         .mode_set = sti_hda_set_mode,
 572 };
 573
 574 static int sti_hda_connector_get_modes(struct drm_connector *connector)
 575 {
 576         unsigned int i;
 577         int count = 0;
 578         struct sti_hda_connector *hda_connector
 579                 = to_sti_hda_connector(connector);
 580         struct sti_hda *hda = hda_connector->hda;
 581
 582         DRM_DEBUG_DRIVER("\n");
 583
 584         for (i = 0; i < ARRAY_SIZE(hda_supported_modes); i++) {
 585                 struct drm_display_mode *mode =
 586                         drm_mode_duplicate(hda->drm_dev,
 587                                         &hda_supported_modes[i].mode);
 588                 if (!mode)
 589                         continue;
 590
 591                 /* the first mode is the preferred mode */
 592                 if (i == 0)
 593                         mode->type |= DRM_MODE_TYPE_PREFERRED;
 594
 595                 drm_mode_probed_add(connector, mode);
 596                 count++;
 597         }
 598
 599         return count;
 600 }
 601
 602 #define CLK_TOLERANCE_HZ 50
 603
 604 static enum drm_mode_status
 605 sti_hda_connector_mode_valid(struct drm_connector *connector,
 606                              struct drm_display_mode *mode)
 607 {
 608         int target = mode->clock * 1000;
 609         int target_min = target - CLK_TOLERANCE_HZ;
 610         int target_max = target + CLK_TOLERANCE_HZ;
 611         int result;
 612         int idx;
 613         struct sti_hda_connector *hda_connector
 614                 = to_sti_hda_connector(connector);
 615         struct sti_hda *hda = hda_connector->hda;
 616
 617         if (!hda_get_mode_idx(*mode, &idx)) {
 618                 return MODE_BAD;
 619         } else {
 620                 result = clk_round_rate(hda->clk_pix, target);
 621
 622                 DRM_DEBUG_DRIVER("target rate = %d => available rate = %d\n",
 623                                  target, result);
 624
 625                 if ((result < target_min) || (result > target_max)) {
 626                         DRM_DEBUG_DRIVER("hda pixclk=%d not supported\n",
 627                                          target);
 628                         return MODE_BAD;
 629                 }
 630         }
 631
 632         return MODE_OK;
 633 }
 634
 635 static const
 636 struct drm_connector_helper_funcs sti_hda_connector_helper_funcs = {
 637         .get_modes = sti_hda_connector_get_modes,
 638         .mode_valid = sti_hda_connector_mode_valid,
 639 };
 640
 641 static int sti_hda_late_register(struct drm_connector *connector)
 642 {
 643         struct sti_hda_connector *hda_connector
 644                 = to_sti_hda_connector(connector);
 645         struct sti_hda *hda = hda_connector->hda;
 646
 647         hda_debugfs_init(hda, hda->drm_dev->primary);
 648
 649         return 0;
 650 }
 651
 652 static const struct drm_connector_funcs sti_hda_connector_funcs = {
 653         .fill_modes = drm_helper_probe_single_connector_modes,
 654         .destroy = drm_connector_cleanup,
 655         .reset = drm_atomic_helper_connector_reset,
 656         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
 657         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
 658         .late_register = sti_hda_late_register,
 659 };
 660
 661 static struct drm_encoder *sti_hda_find_encoder(struct drm_device *dev)
 662 {
 663         struct drm_encoder *encoder;
 664
 665         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 666                 if (encoder->encoder_type == DRM_MODE_ENCODER_DAC)
 667                         return encoder;
 668         }
 669
 670         return NULL;
 671 }
 672
 673 static int sti_hda_bind(struct device *dev, struct device *master, void *data)
 674 {
 675         struct sti_hda *hda = dev_get_drvdata(dev);
 676         struct drm_device *drm_dev = data;
 677         struct drm_encoder *encoder;
 678         struct sti_hda_connector *connector;
 679         struct drm_connector *drm_connector;
 680         struct drm_bridge *bridge;
 681         int err;
 682
 683         /* Set the drm device handle */
 684         hda->drm_dev = drm_dev;
 685
 686         encoder = sti_hda_find_encoder(drm_dev);
 687         if (!encoder)
 688                 return -ENOMEM;
 689
 690         connector = devm_kzalloc(dev, sizeof(*connector), GFP_KERNEL);
 691         if (!connector)
 692                 return -ENOMEM;
 693
 694         connector->hda = hda;
 695
 696                 bridge = devm_kzalloc(dev, sizeof(*bridge), GFP_KERNEL);
 697         if (!bridge)
 698                 return -ENOMEM;
 699
 700         bridge->driver_private = hda;
 701         bridge->funcs = &sti_hda_bridge_funcs;
 702         drm_bridge_attach(encoder, bridge, NULL, 0);
 703
 704         connector->encoder = encoder;
 705
 706         drm_connector = (struct drm_connector *)connector;
 707
 708         drm_connector->polled = DRM_CONNECTOR_POLL_HPD;
 709
 710         drm_connector_init(drm_dev, drm_connector,
 711                         &sti_hda_connector_funcs, DRM_MODE_CONNECTOR_Component);
 712         drm_connector_helper_add(drm_connector,
 713                         &sti_hda_connector_helper_funcs);
 714
 715         err = drm_connector_attach_encoder(drm_connector, encoder);
 716         if (err) {
 717                 DRM_ERROR("Failed to attach a connector to a encoder\n");
 718                 goto err_sysfs;
 719         }
 720
 721         /* force to disable hd dacs at startup */
 722         hda_enable_hd_dacs(hda, false);
 723
 724         return 0;
 725
 726 err_sysfs:
 727         return -EINVAL;
 728 }
 729
 730 static void sti_hda_unbind(struct device *dev,
 731                 struct device *master, void *data)
 732 {
 733 }
 734
 735 static const struct component_ops sti_hda_ops = {
 736         .bind = sti_hda_bind,
 737         .unbind = sti_hda_unbind,
 738 };
 739
 740 static int sti_hda_probe(struct platform_device *pdev)
 741 {
 742         struct device *dev = &pdev->dev;
 743         struct sti_hda *hda;
 744         struct resource *res;
 745
 746         DRM_INFO("%s\n", __func__);
 747
 748         hda = devm_kzalloc(dev, sizeof(*hda), GFP_KERNEL);
 749         if (!hda)
 750                 return -ENOMEM;
 751
 752         hda->dev = pdev->dev;
 753
 754         /* Get resources */
 755         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hda-reg");
 756         if (!res) {
 757                 DRM_ERROR("Invalid hda resource\n");
 758                 return -ENOMEM;
 759         }
 760         hda->regs = devm_ioremap(dev, res->start, resource_size(res));
 761         if (!hda->regs)
 762                 return -ENOMEM;
 763
 764         res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
 765                         "video-dacs-ctrl");
 766         if (res) {
 767                 hda->video_dacs_ctrl = devm_ioremap(dev, res->start,
 768                                 resource_size(res));
 769                 if (!hda->video_dacs_ctrl)
 770                         return -ENOMEM;
 771         } else {
 772                 /* If no existing video-dacs-ctrl resource continue the probe */
 773                 DRM_DEBUG_DRIVER("No video-dacs-ctrl resource\n");
 774                 hda->video_dacs_ctrl = NULL;
 775         }
 776
 777         /* Get clock resources */
 778         hda->clk_pix = devm_clk_get(dev, "pix");
 779         if (IS_ERR(hda->clk_pix)) {
 780                 DRM_ERROR("Cannot get hda_pix clock\n");
 781                 return PTR_ERR(hda->clk_pix);
 782         }
 783
 784         hda->clk_hddac = devm_clk_get(dev, "hddac");
 785         if (IS_ERR(hda->clk_hddac)) {
 786                 DRM_ERROR("Cannot get hda_hddac clock\n");
 787                 return PTR_ERR(hda->clk_hddac);
 788         }
 789
 790         platform_set_drvdata(pdev, hda);
 791
 792         return component_add(&pdev->dev, &sti_hda_ops);
 793 }
 794
 795 static int sti_hda_remove(struct platform_device *pdev)
 796 {
 797         component_del(&pdev->dev, &sti_hda_ops);
 798         return 0;
 799 }
 800
 801 static const struct of_device_id hda_of_match[] = {
 802         { .compatible = "st,stih416-hda", },
 803         { .compatible = "st,stih407-hda", },
 804         { /* end node */ }
 805 };
 806 MODULE_DEVICE_TABLE(of, hda_of_match);
 807
 808 struct platform_driver sti_hda_driver = {
 809         .driver = {
 810                 .name = "sti-hda",
 811                 .owner = THIS_MODULE,
 812                 .of_match_table = hda_of_match,
 813         },
 814         .probe = sti_hda_probe,
 815         .remove = sti_hda_remove,
 816 };
 817
 818 MODULE_AUTHOR("Benjamin Gaignard <benjamin.gaignard@st.com>");
 819 MODULE_DESCRIPTION("STMicroelectronics SoC DRM driver");
 820 MODULE_LICENSE("GPL");