drivers/gpu/drm/rockchip/rockchip_drm_vop.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
   4  * Author:Mark Yao <mark.yao@rock-chips.com>
   5  */
   6
   7 #include <linux/clk.h>
   8 #include <linux/component.h>
   9 #include <linux/delay.h>
  10 #include <linux/iopoll.h>
  11 #include <linux/kernel.h>
  12 #include <linux/log2.h>
  13 #include <linux/module.h>
  14 #include <linux/of.h>
  15 #include <linux/of_device.h>
  16 #include <linux/overflow.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/pm_runtime.h>
  19 #include <linux/reset.h>
  20
  21 #include <drm/drm.h>
  22 #include <drm/drm_atomic.h>
  23 #include <drm/drm_atomic_uapi.h>
  24 #include <drm/drm_blend.h>
  25 #include <drm/drm_crtc.h>
  26 #include <drm/drm_flip_work.h>
  27 #include <drm/drm_fourcc.h>
  28 #include <drm/drm_framebuffer.h>
  29 #include <drm/drm_gem_atomic_helper.h>
  30 #include <drm/drm_gem_framebuffer_helper.h>
  31 #include <drm/drm_probe_helper.h>
  32 #include <drm/drm_self_refresh_helper.h>
  33 #include <drm/drm_vblank.h>
  34
  35 #ifdef CONFIG_DRM_ANALOGIX_DP
  36 #include <drm/bridge/analogix_dp.h>
  37 #endif
  38
  39 #include "rockchip_drm_drv.h"
  40 #include "rockchip_drm_gem.h"
  41 #include "rockchip_drm_fb.h"
  42 #include "rockchip_drm_vop.h"
  43 #include "rockchip_rgb.h"
  44
  45 #define VOP_WIN_SET(vop, win, name, v) \
  46                 vop_reg_set(vop, &win->phy->name, win->base, ~0, v, #name)
  47 #define VOP_SCL_SET(vop, win, name, v) \
  48                 vop_reg_set(vop, &win->phy->scl->name, win->base, ~0, v, #name)
  49 #define VOP_SCL_SET_EXT(vop, win, name, v) \
  50                 vop_reg_set(vop, &win->phy->scl->ext->name, \
  51                             win->base, ~0, v, #name)
  52
  53 #define VOP_WIN_YUV2YUV_SET(vop, win_yuv2yuv, name, v) \
  54         do { \
  55                 if (win_yuv2yuv && win_yuv2yuv->name.mask) \
  56                         vop_reg_set(vop, &win_yuv2yuv->name, 0, ~0, v, #name); \
  57         } while (0)
  58
  59 #define VOP_WIN_YUV2YUV_COEFFICIENT_SET(vop, win_yuv2yuv, name, v) \
  60         do { \
  61                 if (win_yuv2yuv && win_yuv2yuv->phy->name.mask) \
  62                         vop_reg_set(vop, &win_yuv2yuv->phy->name, win_yuv2yuv->base, ~0, v, #name); \
  63         } while (0)
  64
  65 #define VOP_INTR_SET_MASK(vop, name, mask, v) \
  66                 vop_reg_set(vop, &vop->data->intr->name, 0, mask, v, #name)
  67
  68 #define VOP_REG_SET(vop, group, name, v) \
  69                     vop_reg_set(vop, &vop->data->group->name, 0, ~0, v, #name)
  70
  71 #define VOP_HAS_REG(vop, group, name) \
  72                 (!!(vop->data->group->name.mask))
  73
  74 #define VOP_INTR_SET_TYPE(vop, name, type, v) \
  75         do { \
  76                 int i, reg = 0, mask = 0; \
  77                 for (i = 0; i < vop->data->intr->nintrs; i++) { \
  78                         if (vop->data->intr->intrs[i] & type) { \
  79                                 reg |= (v) << i; \
  80                                 mask |= 1 << i; \
  81                         } \
  82                 } \
  83                 VOP_INTR_SET_MASK(vop, name, mask, reg); \
  84         } while (0)
  85 #define VOP_INTR_GET_TYPE(vop, name, type) \
  86                 vop_get_intr_type(vop, &vop->data->intr->name, type)
  87
  88 #define VOP_WIN_GET(vop, win, name) \
  89                 vop_read_reg(vop, win->base, &win->phy->name)
  90
  91 #define VOP_WIN_HAS_REG(win, name) \
  92         (!!(win->phy->name.mask))
  93
  94 #define VOP_WIN_GET_YRGBADDR(vop, win) \
  95                 vop_readl(vop, win->base + win->phy->yrgb_mst.offset)
  96
  97 #define VOP_WIN_TO_INDEX(vop_win) \
  98         ((vop_win) - (vop_win)->vop->win)
  99
 100 #define VOP_AFBC_SET(vop, name, v) \
 101         do { \
 102                 if ((vop)->data->afbc) \
 103                         vop_reg_set((vop), &(vop)->data->afbc->name, \
 104                                     0, ~0, v, #name); \
 105         } while (0)
 106
 107 #define to_vop(x) container_of(x, struct vop, crtc)
 108 #define to_vop_win(x) container_of(x, struct vop_win, base)
 109
 110 #define AFBC_FMT_RGB565         0x0
 111 #define AFBC_FMT_U8U8U8U8       0x5
 112 #define AFBC_FMT_U8U8U8         0x4
 113
 114 #define AFBC_TILE_16x16         BIT(4)
 115
 116 /*
 117  * The coefficients of the following matrix are all fixed points.
 118  * The format is S2.10 for the 3x3 part of the matrix, and S9.12 for the offsets.
 119  * They are all represented in two's complement.
 120  */
 121 static const uint32_t bt601_yuv2rgb[] = {
 122         0x4A8, 0x0,    0x662,
 123         0x4A8, 0x1E6F, 0x1CBF,
 124         0x4A8, 0x812,  0x0,
 125         0x321168, 0x0877CF, 0x2EB127
 126 };
 127
 128 enum vop_pending {
 129         VOP_PENDING_FB_UNREF,
 130 };
 131
 132 struct vop_win {
 133         struct drm_plane base;
 134         const struct vop_win_data *data;
 135         const struct vop_win_yuv2yuv_data *yuv2yuv_data;
 136         struct vop *vop;
 137 };
 138
 139 struct rockchip_rgb;
 140 struct vop {
 141         struct drm_crtc crtc;
 142         struct device *dev;
 143         struct drm_device *drm_dev;
 144         bool is_enabled;
 145
 146         struct completion dsp_hold_completion;
 147         unsigned int win_enabled;
 148
 149         /* protected by dev->event_lock */
 150         struct drm_pending_vblank_event *event;
 151
 152         struct drm_flip_work fb_unref_work;
 153         unsigned long pending;
 154
 155         struct completion line_flag_completion;
 156
 157         const struct vop_data *data;
 158
 159         uint32_t *regsbak;
 160         void __iomem *regs;
 161         void __iomem *lut_regs;
 162
 163         /* physical map length of vop register */
 164         uint32_t len;
 165
 166         /* one time only one process allowed to config the register */
 167         spinlock_t reg_lock;
 168         /* lock vop irq reg */
 169         spinlock_t irq_lock;
 170         /* protects crtc enable/disable */
 171         struct mutex vop_lock;
 172
 173         unsigned int irq;
 174
 175         /* vop AHP clk */
 176         struct clk *hclk;
 177         /* vop dclk */
 178         struct clk *dclk;
 179         /* vop share memory frequency */
 180         struct clk *aclk;
 181
 182         /* vop dclk reset */
 183         struct reset_control *dclk_rst;
 184
 185         /* optional internal rgb encoder */
 186         struct rockchip_rgb *rgb;
 187
 188         struct vop_win win[];
 189 };
 190
 191 static inline uint32_t vop_readl(struct vop *vop, uint32_t offset)
 192 {
 193         return readl(vop->regs + offset);
 194 }
 195
 196 static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base,
 197                                     const struct vop_reg *reg)
 198 {
 199         return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask;
 200 }
 201
 202 static void vop_reg_set(struct vop *vop, const struct vop_reg *reg,
 203                         uint32_t _offset, uint32_t _mask, uint32_t v,
 204                         const char *reg_name)
 205 {
 206         int offset, mask, shift;
 207
 208         if (!reg || !reg->mask) {
 209                 DRM_DEV_DEBUG(vop->dev, "Warning: not support %s\n", reg_name);
 210                 return;
 211         }
 212
 213         offset = reg->offset + _offset;
 214         mask = reg->mask & _mask;
 215         shift = reg->shift;
 216
 217         if (reg->write_mask) {
 218                 v = ((v << shift) & 0xffff) | (mask << (shift + 16));
 219         } else {
 220                 uint32_t cached_val = vop->regsbak[offset >> 2];
 221
 222                 v = (cached_val & ~(mask << shift)) | ((v & mask) << shift);
 223                 vop->regsbak[offset >> 2] = v;
 224         }
 225
 226         if (reg->relaxed)
 227                 writel_relaxed(v, vop->regs + offset);
 228         else
 229                 writel(v, vop->regs + offset);
 230 }
 231
 232 static inline uint32_t vop_get_intr_type(struct vop *vop,
 233                                          const struct vop_reg *reg, int type)
 234 {
 235         uint32_t i, ret = 0;
 236         uint32_t regs = vop_read_reg(vop, 0, reg);
 237
 238         for (i = 0; i < vop->data->intr->nintrs; i++) {
 239                 if ((type & vop->data->intr->intrs[i]) && (regs & 1 << i))
 240                         ret |= vop->data->intr->intrs[i];
 241         }
 242
 243         return ret;
 244 }
 245
 246 static inline void vop_cfg_done(struct vop *vop)
 247 {
 248         VOP_REG_SET(vop, common, cfg_done, 1);
 249 }
 250
 251 static bool has_rb_swapped(uint32_t format)
 252 {
 253         switch (format) {
 254         case DRM_FORMAT_XBGR8888:
 255         case DRM_FORMAT_ABGR8888:
 256         case DRM_FORMAT_BGR888:
 257         case DRM_FORMAT_BGR565:
 258                 return true;
 259         default:
 260                 return false;
 261         }
 262 }
 263
 264 static bool has_uv_swapped(uint32_t format)
 265 {
 266         switch (format) {
 267         case DRM_FORMAT_NV21:
 268         case DRM_FORMAT_NV61:
 269         case DRM_FORMAT_NV42:
 270                 return true;
 271         default:
 272                 return false;
 273         }
 274 }
 275
 276 static enum vop_data_format vop_convert_format(uint32_t format)
 277 {
 278         switch (format) {
 279         case DRM_FORMAT_XRGB8888:
 280         case DRM_FORMAT_ARGB8888:
 281         case DRM_FORMAT_XBGR8888:
 282         case DRM_FORMAT_ABGR8888:
 283                 return VOP_FMT_ARGB8888;
 284         case DRM_FORMAT_RGB888:
 285         case DRM_FORMAT_BGR888:
 286                 return VOP_FMT_RGB888;
 287         case DRM_FORMAT_RGB565:
 288         case DRM_FORMAT_BGR565:
 289                 return VOP_FMT_RGB565;
 290         case DRM_FORMAT_NV12:
 291         case DRM_FORMAT_NV21:
 292                 return VOP_FMT_YUV420SP;
 293         case DRM_FORMAT_NV16:
 294         case DRM_FORMAT_NV61:
 295                 return VOP_FMT_YUV422SP;
 296         case DRM_FORMAT_NV24:
 297         case DRM_FORMAT_NV42:
 298                 return VOP_FMT_YUV444SP;
 299         default:
 300                 DRM_ERROR("unsupported format[%08x]\n", format);
 301                 return -EINVAL;
 302         }
 303 }
 304
 305 static int vop_convert_afbc_format(uint32_t format)
 306 {
 307         switch (format) {
 308         case DRM_FORMAT_XRGB8888:
 309         case DRM_FORMAT_ARGB8888:
 310         case DRM_FORMAT_XBGR8888:
 311         case DRM_FORMAT_ABGR8888:
 312                 return AFBC_FMT_U8U8U8U8;
 313         case DRM_FORMAT_RGB888:
 314         case DRM_FORMAT_BGR888:
 315                 return AFBC_FMT_U8U8U8;
 316         case DRM_FORMAT_RGB565:
 317         case DRM_FORMAT_BGR565:
 318                 return AFBC_FMT_RGB565;
 319         default:
 320                 DRM_DEBUG_KMS("unsupported AFBC format[%08x]\n", format);
 321                 return -EINVAL;
 322         }
 323 }
 324
 325 static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src,
 326                                   uint32_t dst, bool is_horizontal,
 327                                   int vsu_mode, int *vskiplines)
 328 {
 329         uint16_t val = 1 << SCL_FT_DEFAULT_FIXPOINT_SHIFT;
 330
 331         if (vskiplines)
 332                 *vskiplines = 0;
 333
 334         if (is_horizontal) {
 335                 if (mode == SCALE_UP)
 336                         val = GET_SCL_FT_BIC(src, dst);
 337                 else if (mode == SCALE_DOWN)
 338                         val = GET_SCL_FT_BILI_DN(src, dst);
 339         } else {
 340                 if (mode == SCALE_UP) {
 341                         if (vsu_mode == SCALE_UP_BIL)
 342                                 val = GET_SCL_FT_BILI_UP(src, dst);
 343                         else
 344                                 val = GET_SCL_FT_BIC(src, dst);
 345                 } else if (mode == SCALE_DOWN) {
 346                         if (vskiplines) {
 347                                 *vskiplines = scl_get_vskiplines(src, dst);
 348                                 val = scl_get_bili_dn_vskip(src, dst,
 349                                                             *vskiplines);
 350                         } else {
 351                                 val = GET_SCL_FT_BILI_DN(src, dst);
 352                         }
 353                 }
 354         }
 355
 356         return val;
 357 }
 358
 359 static void scl_vop_cal_scl_fac(struct vop *vop, const struct vop_win_data *win,
 360                              uint32_t src_w, uint32_t src_h, uint32_t dst_w,
 361                              uint32_t dst_h, const struct drm_format_info *info)
 362 {
 363         uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode;
 364         uint16_t cbcr_hor_scl_mode = SCALE_NONE;
 365         uint16_t cbcr_ver_scl_mode = SCALE_NONE;
 366         bool is_yuv = false;
 367         uint16_t cbcr_src_w = src_w / info->hsub;
 368         uint16_t cbcr_src_h = src_h / info->vsub;
 369         uint16_t vsu_mode;
 370         uint16_t lb_mode;
 371         uint32_t val;
 372         int vskiplines;
 373
 374         if (info->is_yuv)
 375                 is_yuv = true;
 376
 377         if (dst_w > 3840) {
 378                 DRM_DEV_ERROR(vop->dev, "Maximum dst width (3840) exceeded\n");
 379                 return;
 380         }
 381
 382         if (!win->phy->scl->ext) {
 383                 VOP_SCL_SET(vop, win, scale_yrgb_x,
 384                             scl_cal_scale2(src_w, dst_w));
 385                 VOP_SCL_SET(vop, win, scale_yrgb_y,
 386                             scl_cal_scale2(src_h, dst_h));
 387                 if (is_yuv) {
 388                         VOP_SCL_SET(vop, win, scale_cbcr_x,
 389                                     scl_cal_scale2(cbcr_src_w, dst_w));
 390                         VOP_SCL_SET(vop, win, scale_cbcr_y,
 391                                     scl_cal_scale2(cbcr_src_h, dst_h));
 392                 }
 393                 return;
 394         }
 395
 396         yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w);
 397         yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h);
 398
 399         if (is_yuv) {
 400                 cbcr_hor_scl_mode = scl_get_scl_mode(cbcr_src_w, dst_w);
 401                 cbcr_ver_scl_mode = scl_get_scl_mode(cbcr_src_h, dst_h);
 402                 if (cbcr_hor_scl_mode == SCALE_DOWN)
 403                         lb_mode = scl_vop_cal_lb_mode(dst_w, true);
 404                 else
 405                         lb_mode = scl_vop_cal_lb_mode(cbcr_src_w, true);
 406         } else {
 407                 if (yrgb_hor_scl_mode == SCALE_DOWN)
 408                         lb_mode = scl_vop_cal_lb_mode(dst_w, false);
 409                 else
 410                         lb_mode = scl_vop_cal_lb_mode(src_w, false);
 411         }
 412
 413         VOP_SCL_SET_EXT(vop, win, lb_mode, lb_mode);
 414         if (lb_mode == LB_RGB_3840X2) {
 415                 if (yrgb_ver_scl_mode != SCALE_NONE) {
 416                         DRM_DEV_ERROR(vop->dev, "not allow yrgb ver scale\n");
 417                         return;
 418                 }
 419                 if (cbcr_ver_scl_mode != SCALE_NONE) {
 420                         DRM_DEV_ERROR(vop->dev, "not allow cbcr ver scale\n");
 421                         return;
 422                 }
 423                 vsu_mode = SCALE_UP_BIL;
 424         } else if (lb_mode == LB_RGB_2560X4) {
 425                 vsu_mode = SCALE_UP_BIL;
 426         } else {
 427                 vsu_mode = SCALE_UP_BIC;
 428         }
 429
 430         val = scl_vop_cal_scale(yrgb_hor_scl_mode, src_w, dst_w,
 431                                 true, 0, NULL);
 432         VOP_SCL_SET(vop, win, scale_yrgb_x, val);
 433         val = scl_vop_cal_scale(yrgb_ver_scl_mode, src_h, dst_h,
 434                                 false, vsu_mode, &vskiplines);
 435         VOP_SCL_SET(vop, win, scale_yrgb_y, val);
 436
 437         VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt4, vskiplines == 4);
 438         VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt2, vskiplines == 2);
 439
 440         VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, yrgb_hor_scl_mode);
 441         VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, yrgb_ver_scl_mode);
 442         VOP_SCL_SET_EXT(vop, win, yrgb_hsd_mode, SCALE_DOWN_BIL);
 443         VOP_SCL_SET_EXT(vop, win, yrgb_vsd_mode, SCALE_DOWN_BIL);
 444         VOP_SCL_SET_EXT(vop, win, yrgb_vsu_mode, vsu_mode);
 445         if (is_yuv) {
 446                 val = scl_vop_cal_scale(cbcr_hor_scl_mode, cbcr_src_w,
 447                                         dst_w, true, 0, NULL);
 448                 VOP_SCL_SET(vop, win, scale_cbcr_x, val);
 449                 val = scl_vop_cal_scale(cbcr_ver_scl_mode, cbcr_src_h,
 450                                         dst_h, false, vsu_mode, &vskiplines);
 451                 VOP_SCL_SET(vop, win, scale_cbcr_y, val);
 452
 453                 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt4, vskiplines == 4);
 454                 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt2, vskiplines == 2);
 455                 VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, cbcr_hor_scl_mode);
 456                 VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, cbcr_ver_scl_mode);
 457                 VOP_SCL_SET_EXT(vop, win, cbcr_hsd_mode, SCALE_DOWN_BIL);
 458                 VOP_SCL_SET_EXT(vop, win, cbcr_vsd_mode, SCALE_DOWN_BIL);
 459                 VOP_SCL_SET_EXT(vop, win, cbcr_vsu_mode, vsu_mode);
 460         }
 461 }
 462
 463 static void vop_dsp_hold_valid_irq_enable(struct vop *vop)
 464 {
 465         unsigned long flags;
 466
 467         if (WARN_ON(!vop->is_enabled))
 468                 return;
 469
 470         spin_lock_irqsave(&vop->irq_lock, flags);
 471
 472         VOP_INTR_SET_TYPE(vop, clear, DSP_HOLD_VALID_INTR, 1);
 473         VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 1);
 474
 475         spin_unlock_irqrestore(&vop->irq_lock, flags);
 476 }
 477
 478 static void vop_dsp_hold_valid_irq_disable(struct vop *vop)
 479 {
 480         unsigned long flags;
 481
 482         if (WARN_ON(!vop->is_enabled))
 483                 return;
 484
 485         spin_lock_irqsave(&vop->irq_lock, flags);
 486
 487         VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 0);
 488
 489         spin_unlock_irqrestore(&vop->irq_lock, flags);
 490 }
 491
 492 /*
 493  * (1) each frame starts at the start of the Vsync pulse which is signaled by
 494  *     the "FRAME_SYNC" interrupt.
 495  * (2) the active data region of each frame ends at dsp_vact_end
 496  * (3) we should program this same number (dsp_vact_end) into dsp_line_frag_num,
 497  *      to get "LINE_FLAG" interrupt at the end of the active on screen data.
 498  *
 499  * VOP_INTR_CTRL0.dsp_line_frag_num = VOP_DSP_VACT_ST_END.dsp_vact_end
 500  * Interrupts
 501  * LINE_FLAG -------------------------------+
 502  * FRAME_SYNC ----+                         |
 503  *                |                         |
 504  *                v                         v
 505  *                | Vsync | Vbp |  Vactive  | Vfp |
 506  *                        ^     ^           ^     ^
 507  *                        |     |           |     |
 508  *                        |     |           |     |
 509  * dsp_vs_end ------------+     |           |     |   VOP_DSP_VTOTAL_VS_END
 510  * dsp_vact_start --------------+           |     |   VOP_DSP_VACT_ST_END
 511  * dsp_vact_end ----------------------------+     |   VOP_DSP_VACT_ST_END
 512  * dsp_total -------------------------------------+   VOP_DSP_VTOTAL_VS_END
 513  */
 514 static bool vop_line_flag_irq_is_enabled(struct vop *vop)
 515 {
 516         uint32_t line_flag_irq;
 517         unsigned long flags;
 518
 519         spin_lock_irqsave(&vop->irq_lock, flags);
 520
 521         line_flag_irq = VOP_INTR_GET_TYPE(vop, enable, LINE_FLAG_INTR);
 522
 523         spin_unlock_irqrestore(&vop->irq_lock, flags);
 524
 525         return !!line_flag_irq;
 526 }
 527
 528 static void vop_line_flag_irq_enable(struct vop *vop)
 529 {
 530         unsigned long flags;
 531
 532         if (WARN_ON(!vop->is_enabled))
 533                 return;
 534
 535         spin_lock_irqsave(&vop->irq_lock, flags);
 536
 537         VOP_INTR_SET_TYPE(vop, clear, LINE_FLAG_INTR, 1);
 538         VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 1);
 539
 540         spin_unlock_irqrestore(&vop->irq_lock, flags);
 541 }
 542
 543 static void vop_line_flag_irq_disable(struct vop *vop)
 544 {
 545         unsigned long flags;
 546
 547         if (WARN_ON(!vop->is_enabled))
 548                 return;
 549
 550         spin_lock_irqsave(&vop->irq_lock, flags);
 551
 552         VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 0);
 553
 554         spin_unlock_irqrestore(&vop->irq_lock, flags);
 555 }
 556
 557 static int vop_core_clks_enable(struct vop *vop)
 558 {
 559         int ret;
 560
 561         ret = clk_enable(vop->hclk);
 562         if (ret < 0)
 563                 return ret;
 564
 565         ret = clk_enable(vop->aclk);
 566         if (ret < 0)
 567                 goto err_disable_hclk;
 568
 569         return 0;
 570
 571 err_disable_hclk:
 572         clk_disable(vop->hclk);
 573         return ret;
 574 }
 575
 576 static void vop_core_clks_disable(struct vop *vop)
 577 {
 578         clk_disable(vop->aclk);
 579         clk_disable(vop->hclk);
 580 }
 581
 582 static void vop_win_disable(struct vop *vop, const struct vop_win *vop_win)
 583 {
 584         const struct vop_win_data *win = vop_win->data;
 585
 586         if (win->phy->scl && win->phy->scl->ext) {
 587                 VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, SCALE_NONE);
 588                 VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, SCALE_NONE);
 589                 VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, SCALE_NONE);
 590                 VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, SCALE_NONE);
 591         }
 592
 593         VOP_WIN_SET(vop, win, enable, 0);
 594         vop->win_enabled &= ~BIT(VOP_WIN_TO_INDEX(vop_win));
 595 }
 596
 597 static int vop_enable(struct drm_crtc *crtc, struct drm_crtc_state *old_state)
 598 {
 599         struct vop *vop = to_vop(crtc);
 600         int ret, i;
 601
 602         ret = pm_runtime_resume_and_get(vop->dev);
 603         if (ret < 0) {
 604                 DRM_DEV_ERROR(vop->dev, "failed to get pm runtime: %d\n", ret);
 605                 return ret;
 606         }
 607
 608         ret = vop_core_clks_enable(vop);
 609         if (WARN_ON(ret < 0))
 610                 goto err_put_pm_runtime;
 611
 612         ret = clk_enable(vop->dclk);
 613         if (WARN_ON(ret < 0))
 614                 goto err_disable_core;
 615
 616         /*
 617          * Slave iommu shares power, irq and clock with vop.  It was associated
 618          * automatically with this master device via common driver code.
 619          * Now that we have enabled the clock we attach it to the shared drm
 620          * mapping.
 621          */
 622         ret = rockchip_drm_dma_attach_device(vop->drm_dev, vop->dev);
 623         if (ret) {
 624                 DRM_DEV_ERROR(vop->dev,
 625                               "failed to attach dma mapping, %d\n", ret);
 626                 goto err_disable_dclk;
 627         }
 628
 629         spin_lock(&vop->reg_lock);
 630         for (i = 0; i < vop->len; i += 4)
 631                 writel_relaxed(vop->regsbak[i / 4], vop->regs + i);
 632
 633         /*
 634          * We need to make sure that all windows are disabled before we
 635          * enable the crtc. Otherwise we might try to scan from a destroyed
 636          * buffer later.
 637          *
 638          * In the case of enable-after-PSR, we don't need to worry about this
 639          * case since the buffer is guaranteed to be valid and disabling the
 640          * window will result in screen glitches on PSR exit.
 641          */
 642         if (!old_state || !old_state->self_refresh_active) {
 643                 for (i = 0; i < vop->data->win_size; i++) {
 644                         struct vop_win *vop_win = &vop->win[i];
 645
 646                         vop_win_disable(vop, vop_win);
 647                 }
 648         }
 649
 650         if (vop->data->afbc) {
 651                 struct rockchip_crtc_state *s;
 652                 /*
 653                  * Disable AFBC and forget there was a vop window with AFBC
 654                  */
 655                 VOP_AFBC_SET(vop, enable, 0);
 656                 s = to_rockchip_crtc_state(crtc->state);
 657                 s->enable_afbc = false;
 658         }
 659
 660         vop_cfg_done(vop);
 661
 662         spin_unlock(&vop->reg_lock);
 663
 664         /*
 665          * At here, vop clock & iommu is enable, R/W vop regs would be safe.
 666          */
 667         vop->is_enabled = true;
 668
 669         spin_lock(&vop->reg_lock);
 670
 671         VOP_REG_SET(vop, common, standby, 1);
 672
 673         spin_unlock(&vop->reg_lock);
 674
 675         drm_crtc_vblank_on(crtc);
 676
 677         return 0;
 678
 679 err_disable_dclk:
 680         clk_disable(vop->dclk);
 681 err_disable_core:
 682         vop_core_clks_disable(vop);
 683 err_put_pm_runtime:
 684         pm_runtime_put_sync(vop->dev);
 685         return ret;
 686 }
 687
 688 static void rockchip_drm_set_win_enabled(struct drm_crtc *crtc, bool enabled)
 689 {
 690         struct vop *vop = to_vop(crtc);
 691         int i;
 692
 693         spin_lock(&vop->reg_lock);
 694
 695         for (i = 0; i < vop->data->win_size; i++) {
 696                 struct vop_win *vop_win = &vop->win[i];
 697                 const struct vop_win_data *win = vop_win->data;
 698
 699                 VOP_WIN_SET(vop, win, enable,
 700                             enabled && (vop->win_enabled & BIT(i)));
 701         }
 702         vop_cfg_done(vop);
 703
 704         spin_unlock(&vop->reg_lock);
 705 }
 706
 707 static void vop_crtc_atomic_disable(struct drm_crtc *crtc,
 708                                     struct drm_atomic_state *state)
 709 {
 710         struct vop *vop = to_vop(crtc);
 711
 712         WARN_ON(vop->event);
 713
 714         if (crtc->state->self_refresh_active)
 715                 rockchip_drm_set_win_enabled(crtc, false);
 716
 717         if (crtc->state->self_refresh_active)
 718                 goto out;
 719
 720         mutex_lock(&vop->vop_lock);
 721
 722         drm_crtc_vblank_off(crtc);
 723
 724         /*
 725          * Vop standby will take effect at end of current frame,
 726          * if dsp hold valid irq happen, it means standby complete.
 727          *
 728          * we must wait standby complete when we want to disable aclk,
 729          * if not, memory bus maybe dead.
 730          */
 731         reinit_completion(&vop->dsp_hold_completion);
 732         vop_dsp_hold_valid_irq_enable(vop);
 733
 734         spin_lock(&vop->reg_lock);
 735
 736         VOP_REG_SET(vop, common, standby, 1);
 737
 738         spin_unlock(&vop->reg_lock);
 739
 740         if (!wait_for_completion_timeout(&vop->dsp_hold_completion,
 741                                          msecs_to_jiffies(200)))
 742                 WARN(1, "%s: timed out waiting for DSP hold", crtc->name);
 743
 744         vop_dsp_hold_valid_irq_disable(vop);
 745
 746         vop->is_enabled = false;
 747
 748         /*
 749          * vop standby complete, so iommu detach is safe.
 750          */
 751         rockchip_drm_dma_detach_device(vop->drm_dev, vop->dev);
 752
 753         clk_disable(vop->dclk);
 754         vop_core_clks_disable(vop);
 755         pm_runtime_put(vop->dev);
 756
 757         mutex_unlock(&vop->vop_lock);
 758
 759 out:
 760         if (crtc->state->event && !crtc->state->active) {
 761                 spin_lock_irq(&crtc->dev->event_lock);
 762                 drm_crtc_send_vblank_event(crtc, crtc->state->event);
 763                 spin_unlock_irq(&crtc->dev->event_lock);
 764
 765                 crtc->state->event = NULL;
 766         }
 767 }
 768
 769 static void vop_plane_destroy(struct drm_plane *plane)
 770 {
 771         drm_plane_cleanup(plane);
 772 }
 773
 774 static inline bool rockchip_afbc(u64 modifier)
 775 {
 776         return modifier == ROCKCHIP_AFBC_MOD;
 777 }
 778
 779 static bool rockchip_mod_supported(struct drm_plane *plane,
 780                                    u32 format, u64 modifier)
 781 {
 782         if (modifier == DRM_FORMAT_MOD_LINEAR)
 783                 return true;
 784
 785         if (!rockchip_afbc(modifier)) {
 786                 DRM_DEBUG_KMS("Unsupported format modifier 0x%llx\n", modifier);
 787
 788                 return false;
 789         }
 790
 791         return vop_convert_afbc_format(format) >= 0;
 792 }
 793
 794 static int vop_plane_atomic_check(struct drm_plane *plane,
 795                            struct drm_atomic_state *state)
 796 {
 797         struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state,
 798                                                                                  plane);
 799         struct drm_crtc *crtc = new_plane_state->crtc;
 800         struct drm_crtc_state *crtc_state;
 801         struct drm_framebuffer *fb = new_plane_state->fb;
 802         struct vop_win *vop_win = to_vop_win(plane);
 803         const struct vop_win_data *win = vop_win->data;
 804         int ret;
 805         int min_scale = win->phy->scl ? FRAC_16_16(1, 8) :
 806                                         DRM_PLANE_NO_SCALING;
 807         int max_scale = win->phy->scl ? FRAC_16_16(8, 1) :
 808                                         DRM_PLANE_NO_SCALING;
 809
 810         if (!crtc || WARN_ON(!fb))
 811                 return 0;
 812
 813         crtc_state = drm_atomic_get_existing_crtc_state(state,
 814                                                         crtc);
 815         if (WARN_ON(!crtc_state))
 816                 return -EINVAL;
 817
 818         ret = drm_atomic_helper_check_plane_state(new_plane_state, crtc_state,
 819                                                   min_scale, max_scale,
 820                                                   true, true);
 821         if (ret)
 822                 return ret;
 823
 824         if (!new_plane_state->visible)
 825                 return 0;
 826
 827         ret = vop_convert_format(fb->format->format);
 828         if (ret < 0)
 829                 return ret;
 830
 831         /*
 832          * Src.x1 can be odd when do clip, but yuv plane start point
 833          * need align with 2 pixel.
 834          */
 835         if (fb->format->is_yuv && ((new_plane_state->src.x1 >> 16) % 2)) {
 836                 DRM_DEBUG_KMS("Invalid Source: Yuv format not support odd xpos\n");
 837                 return -EINVAL;
 838         }
 839
 840         if (fb->format->is_yuv && new_plane_state->rotation & DRM_MODE_REFLECT_Y) {
 841                 DRM_DEBUG_KMS("Invalid Source: Yuv format does not support this rotation\n");
 842                 return -EINVAL;
 843         }
 844
 845         if (rockchip_afbc(fb->modifier)) {
 846                 struct vop *vop = to_vop(crtc);
 847
 848                 if (!vop->data->afbc) {
 849                         DRM_DEBUG_KMS("vop does not support AFBC\n");
 850                         return -EINVAL;
 851                 }
 852
 853                 ret = vop_convert_afbc_format(fb->format->format);
 854                 if (ret < 0)
 855                         return ret;
 856
 857                 if (new_plane_state->src.x1 || new_plane_state->src.y1) {
 858                         DRM_DEBUG_KMS("AFBC does not support offset display, " \
 859                                       "xpos=%d, ypos=%d, offset=%d\n",
 860                                       new_plane_state->src.x1, new_plane_state->src.y1,
 861                                       fb->offsets[0]);
 862                         return -EINVAL;
 863                 }
 864
 865                 if (new_plane_state->rotation && new_plane_state->rotation != DRM_MODE_ROTATE_0) {
 866                         DRM_DEBUG_KMS("No rotation support in AFBC, rotation=%d\n",
 867                                       new_plane_state->rotation);
 868                         return -EINVAL;
 869                 }
 870         }
 871
 872         return 0;
 873 }
 874
 875 static void vop_plane_atomic_disable(struct drm_plane *plane,
 876                                      struct drm_atomic_state *state)
 877 {
 878         struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state,
 879                                                                            plane);
 880         struct vop_win *vop_win = to_vop_win(plane);
 881         struct vop *vop = to_vop(old_state->crtc);
 882
 883         if (!old_state->crtc)
 884                 return;
 885
 886         spin_lock(&vop->reg_lock);
 887
 888         vop_win_disable(vop, vop_win);
 889
 890         spin_unlock(&vop->reg_lock);
 891 }
 892
 893 static void vop_plane_atomic_update(struct drm_plane *plane,
 894                 struct drm_atomic_state *state)
 895 {
 896         struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state,
 897                                                                            plane);
 898         struct drm_crtc *crtc = new_state->crtc;
 899         struct vop_win *vop_win = to_vop_win(plane);
 900         const struct vop_win_data *win = vop_win->data;
 901         const struct vop_win_yuv2yuv_data *win_yuv2yuv = vop_win->yuv2yuv_data;
 902         struct vop *vop = to_vop(new_state->crtc);
 903         struct drm_framebuffer *fb = new_state->fb;
 904         unsigned int actual_w, actual_h;
 905         unsigned int dsp_stx, dsp_sty;
 906         uint32_t act_info, dsp_info, dsp_st;
 907         struct drm_rect *src = &new_state->src;
 908         struct drm_rect *dest = &new_state->dst;
 909         struct drm_gem_object *obj, *uv_obj;
 910         struct rockchip_gem_object *rk_obj, *rk_uv_obj;
 911         unsigned long offset;
 912         dma_addr_t dma_addr;
 913         uint32_t val;
 914         bool rb_swap, uv_swap;
 915         int win_index = VOP_WIN_TO_INDEX(vop_win);
 916         int format;
 917         int is_yuv = fb->format->is_yuv;
 918         int i;
 919
 920         /*
 921          * can't update plane when vop is disabled.
 922          */
 923         if (WARN_ON(!crtc))
 924                 return;
 925
 926         if (WARN_ON(!vop->is_enabled))
 927                 return;
 928
 929         if (!new_state->visible) {
 930                 vop_plane_atomic_disable(plane, state);
 931                 return;
 932         }
 933
 934         obj = fb->obj[0];
 935         rk_obj = to_rockchip_obj(obj);
 936
 937         actual_w = drm_rect_width(src) >> 16;
 938         actual_h = drm_rect_height(src) >> 16;
 939         act_info = (actual_h - 1) << 16 | ((actual_w - 1) & 0xffff);
 940
 941         dsp_info = (drm_rect_height(dest) - 1) << 16;
 942         dsp_info |= (drm_rect_width(dest) - 1) & 0xffff;
 943
 944         dsp_stx = dest->x1 + crtc->mode.htotal - crtc->mode.hsync_start;
 945         dsp_sty = dest->y1 + crtc->mode.vtotal - crtc->mode.vsync_start;
 946         dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff);
 947
 948         offset = (src->x1 >> 16) * fb->format->cpp[0];
 949         offset += (src->y1 >> 16) * fb->pitches[0];
 950         dma_addr = rk_obj->dma_addr + offset + fb->offsets[0];
 951
 952         /*
 953          * For y-mirroring we need to move address
 954          * to the beginning of the last line.
 955          */
 956         if (new_state->rotation & DRM_MODE_REFLECT_Y)
 957                 dma_addr += (actual_h - 1) * fb->pitches[0];
 958
 959         format = vop_convert_format(fb->format->format);
 960
 961         spin_lock(&vop->reg_lock);
 962
 963         if (rockchip_afbc(fb->modifier)) {
 964                 int afbc_format = vop_convert_afbc_format(fb->format->format);
 965
 966                 VOP_AFBC_SET(vop, format, afbc_format | AFBC_TILE_16x16);
 967                 VOP_AFBC_SET(vop, hreg_block_split, 0);
 968                 VOP_AFBC_SET(vop, win_sel, VOP_WIN_TO_INDEX(vop_win));
 969                 VOP_AFBC_SET(vop, hdr_ptr, dma_addr);
 970                 VOP_AFBC_SET(vop, pic_size, act_info);
 971         }
 972
 973         VOP_WIN_SET(vop, win, format, format);
 974         VOP_WIN_SET(vop, win, yrgb_vir, DIV_ROUND_UP(fb->pitches[0], 4));
 975         VOP_WIN_SET(vop, win, yrgb_mst, dma_addr);
 976         VOP_WIN_YUV2YUV_SET(vop, win_yuv2yuv, y2r_en, is_yuv);
 977         VOP_WIN_SET(vop, win, y_mir_en,
 978                     (new_state->rotation & DRM_MODE_REFLECT_Y) ? 1 : 0);
 979         VOP_WIN_SET(vop, win, x_mir_en,
 980                     (new_state->rotation & DRM_MODE_REFLECT_X) ? 1 : 0);
 981
 982         if (is_yuv) {
 983                 int hsub = fb->format->hsub;
 984                 int vsub = fb->format->vsub;
 985                 int bpp = fb->format->cpp[1];
 986
 987                 uv_obj = fb->obj[1];
 988                 rk_uv_obj = to_rockchip_obj(uv_obj);
 989
 990                 offset = (src->x1 >> 16) * bpp / hsub;
 991                 offset += (src->y1 >> 16) * fb->pitches[1] / vsub;
 992
 993                 dma_addr = rk_uv_obj->dma_addr + offset + fb->offsets[1];
 994                 VOP_WIN_SET(vop, win, uv_vir, DIV_ROUND_UP(fb->pitches[1], 4));
 995                 VOP_WIN_SET(vop, win, uv_mst, dma_addr);
 996
 997                 for (i = 0; i < NUM_YUV2YUV_COEFFICIENTS; i++) {
 998                         VOP_WIN_YUV2YUV_COEFFICIENT_SET(vop,
 999                                                         win_yuv2yuv,
1000                                                         y2r_coefficients[i],
1001                                                         bt601_yuv2rgb[i]);
1002                 }
1003
1004                 uv_swap = has_uv_swapped(fb->format->format);
1005                 VOP_WIN_SET(vop, win, uv_swap, uv_swap);
1006         }
1007
1008         if (win->phy->scl)
1009                 scl_vop_cal_scl_fac(vop, win, actual_w, actual_h,
1010                                     drm_rect_width(dest), drm_rect_height(dest),
1011                                     fb->format);
1012
1013         VOP_WIN_SET(vop, win, act_info, act_info);
1014         VOP_WIN_SET(vop, win, dsp_info, dsp_info);
1015         VOP_WIN_SET(vop, win, dsp_st, dsp_st);
1016
1017         rb_swap = has_rb_swapped(fb->format->format);
1018         VOP_WIN_SET(vop, win, rb_swap, rb_swap);
1019
1020         /*
1021          * Blending win0 with the background color doesn't seem to work
1022          * correctly. We only get the background color, no matter the contents
1023          * of the win0 framebuffer.  However, blending pre-multiplied color
1024          * with the default opaque black default background color is a no-op,
1025          * so we can just disable blending to get the correct result.
1026          */
1027         if (fb->format->has_alpha && win_index > 0) {
1028                 VOP_WIN_SET(vop, win, dst_alpha_ctl,
1029                             DST_FACTOR_M0(ALPHA_SRC_INVERSE));
1030                 val = SRC_ALPHA_EN(1) | SRC_COLOR_M0(ALPHA_SRC_PRE_MUL) |
1031                         SRC_ALPHA_M0(ALPHA_STRAIGHT) |
1032                         SRC_BLEND_M0(ALPHA_PER_PIX) |
1033                         SRC_ALPHA_CAL_M0(ALPHA_NO_SATURATION) |
1034                         SRC_FACTOR_M0(ALPHA_ONE);
1035                 VOP_WIN_SET(vop, win, src_alpha_ctl, val);
1036
1037                 VOP_WIN_SET(vop, win, alpha_pre_mul, ALPHA_SRC_PRE_MUL);
1038                 VOP_WIN_SET(vop, win, alpha_mode, ALPHA_PER_PIX);
1039                 VOP_WIN_SET(vop, win, alpha_en, 1);
1040         } else {
1041                 VOP_WIN_SET(vop, win, src_alpha_ctl, SRC_ALPHA_EN(0));
1042                 VOP_WIN_SET(vop, win, alpha_en, 0);
1043         }
1044
1045         VOP_WIN_SET(vop, win, enable, 1);
1046         vop->win_enabled |= BIT(win_index);
1047         spin_unlock(&vop->reg_lock);
1048 }
1049
1050 static int vop_plane_atomic_async_check(struct drm_plane *plane,
1051                                         struct drm_atomic_state *state)
1052 {
1053         struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state,
1054                                                                                  plane);
1055         struct vop_win *vop_win = to_vop_win(plane);
1056         const struct vop_win_data *win = vop_win->data;
1057         int min_scale = win->phy->scl ? FRAC_16_16(1, 8) :
1058                                         DRM_PLANE_NO_SCALING;
1059         int max_scale = win->phy->scl ? FRAC_16_16(8, 1) :
1060                                         DRM_PLANE_NO_SCALING;
1061         struct drm_crtc_state *crtc_state;
1062
1063         if (plane != new_plane_state->crtc->cursor)
1064                 return -EINVAL;
1065
1066         if (!plane->state)
1067                 return -EINVAL;
1068
1069         if (!plane->state->fb)
1070                 return -EINVAL;
1071
1072         if (state)
1073                 crtc_state = drm_atomic_get_existing_crtc_state(state,
1074                                                                 new_plane_state->crtc);
1075         else /* Special case for asynchronous cursor updates. */
1076                 crtc_state = plane->crtc->state;
1077
1078         return drm_atomic_helper_check_plane_state(plane->state, crtc_state,
1079                                                    min_scale, max_scale,
1080                                                    true, true);
1081 }
1082
1083 static void vop_plane_atomic_async_update(struct drm_plane *plane,
1084                                           struct drm_atomic_state *state)
1085 {
1086         struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state,
1087                                                                            plane);
1088         struct vop *vop = to_vop(plane->state->crtc);
1089         struct drm_framebuffer *old_fb = plane->state->fb;
1090
1091         plane->state->crtc_x = new_state->crtc_x;
1092         plane->state->crtc_y = new_state->crtc_y;
1093         plane->state->crtc_h = new_state->crtc_h;
1094         plane->state->crtc_w = new_state->crtc_w;
1095         plane->state->src_x = new_state->src_x;
1096         plane->state->src_y = new_state->src_y;
1097         plane->state->src_h = new_state->src_h;
1098         plane->state->src_w = new_state->src_w;
1099         swap(plane->state->fb, new_state->fb);
1100
1101         if (vop->is_enabled) {
1102                 vop_plane_atomic_update(plane, state);
1103                 spin_lock(&vop->reg_lock);
1104                 vop_cfg_done(vop);
1105                 spin_unlock(&vop->reg_lock);
1106
1107                 /*
1108                  * A scanout can still be occurring, so we can't drop the
1109                  * reference to the old framebuffer. To solve this we get a
1110                  * reference to old_fb and set a worker to release it later.
1111                  * FIXME: if we perform 500 async_update calls before the
1112                  * vblank, then we can have 500 different framebuffers waiting
1113                  * to be released.
1114                  */
1115                 if (old_fb && plane->state->fb != old_fb) {
1116                         drm_framebuffer_get(old_fb);
1117                         WARN_ON(drm_crtc_vblank_get(plane->state->crtc) != 0);
1118                         drm_flip_work_queue(&vop->fb_unref_work, old_fb);
1119                         set_bit(VOP_PENDING_FB_UNREF, &vop->pending);
1120                 }
1121         }
1122 }
1123
1124 static const struct drm_plane_helper_funcs plane_helper_funcs = {
1125         .atomic_check = vop_plane_atomic_check,
1126         .atomic_update = vop_plane_atomic_update,
1127         .atomic_disable = vop_plane_atomic_disable,
1128         .atomic_async_check = vop_plane_atomic_async_check,
1129         .atomic_async_update = vop_plane_atomic_async_update,
1130 };
1131
1132 static const struct drm_plane_funcs vop_plane_funcs = {
1133         .update_plane   = drm_atomic_helper_update_plane,
1134         .disable_plane  = drm_atomic_helper_disable_plane,
1135         .destroy = vop_plane_destroy,
1136         .reset = drm_atomic_helper_plane_reset,
1137         .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
1138         .atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
1139         .format_mod_supported = rockchip_mod_supported,
1140 };
1141
1142 static int vop_crtc_enable_vblank(struct drm_crtc *crtc)
1143 {
1144         struct vop *vop = to_vop(crtc);
1145         unsigned long flags;
1146
1147         if (WARN_ON(!vop->is_enabled))
1148                 return -EPERM;
1149
1150         spin_lock_irqsave(&vop->irq_lock, flags);
1151
1152         VOP_INTR_SET_TYPE(vop, clear, FS_INTR, 1);
1153         VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 1);
1154
1155         spin_unlock_irqrestore(&vop->irq_lock, flags);
1156
1157         return 0;
1158 }
1159
1160 static void vop_crtc_disable_vblank(struct drm_crtc *crtc)
1161 {
1162         struct vop *vop = to_vop(crtc);
1163         unsigned long flags;
1164
1165         if (WARN_ON(!vop->is_enabled))
1166                 return;
1167
1168         spin_lock_irqsave(&vop->irq_lock, flags);
1169
1170         VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 0);
1171
1172         spin_unlock_irqrestore(&vop->irq_lock, flags);
1173 }
1174
1175 static enum drm_mode_status vop_crtc_mode_valid(struct drm_crtc *crtc,
1176                                                 const struct drm_display_mode *mode)
1177 {
1178         struct vop *vop = to_vop(crtc);
1179
1180         if (vop->data->max_output.width && mode->hdisplay > vop->data->max_output.width)
1181                 return MODE_BAD_HVALUE;
1182
1183         return MODE_OK;
1184 }
1185
1186 static bool vop_crtc_mode_fixup(struct drm_crtc *crtc,
1187                                 const struct drm_display_mode *mode,
1188                                 struct drm_display_mode *adjusted_mode)
1189 {
1190         struct vop *vop = to_vop(crtc);
1191         unsigned long rate;
1192
1193         /*
1194          * Clock craziness.
1195          *
1196          * Key points:
1197          *
1198          * - DRM works in kHz.
1199          * - Clock framework works in Hz.
1200          * - Rockchip's clock driver picks the clock rate that is the
1201          *   same _OR LOWER_ than the one requested.
1202          *
1203          * Action plan:
1204          *
1205          * 1. Try to set the exact rate first, and confirm the clock framework
1206          *    can provide it.
1207          *
1208          * 2. If the clock framework cannot provide the exact rate, we should
1209          *    add 999 Hz to the requested rate.  That way if the clock we need
1210          *    is 60000001 Hz (~60 MHz) and DRM tells us to make 60000 kHz then
1211          *    the clock framework will actually give us the right clock.
1212          *
1213          * 3. Get the clock framework to round the rate for us to tell us
1214          *    what it will actually make.
1215          *
1216          * 4. Store the rounded up rate so that we don't need to worry about
1217          *    this in the actual clk_set_rate().
1218          */
1219         rate = clk_round_rate(vop->dclk, adjusted_mode->clock * 1000);
1220         if (rate / 1000 != adjusted_mode->clock)
1221                 rate = clk_round_rate(vop->dclk,
1222                                       adjusted_mode->clock * 1000 + 999);
1223         adjusted_mode->clock = DIV_ROUND_UP(rate, 1000);
1224
1225         return true;
1226 }
1227
1228 static bool vop_dsp_lut_is_enabled(struct vop *vop)
1229 {
1230         return vop_read_reg(vop, 0, &vop->data->common->dsp_lut_en);
1231 }
1232
1233 static u32 vop_lut_buffer_index(struct vop *vop)
1234 {
1235         return vop_read_reg(vop, 0, &vop->data->common->lut_buffer_index);
1236 }
1237
1238 static void vop_crtc_write_gamma_lut(struct vop *vop, struct drm_crtc *crtc)
1239 {
1240         struct drm_color_lut *lut = crtc->state->gamma_lut->data;
1241         unsigned int i, bpc = ilog2(vop->data->lut_size);
1242
1243         for (i = 0; i < crtc->gamma_size; i++) {
1244                 u32 word;
1245
1246                 word = (drm_color_lut_extract(lut[i].red, bpc) << (2 * bpc)) |
1247                        (drm_color_lut_extract(lut[i].green, bpc) << bpc) |
1248                         drm_color_lut_extract(lut[i].blue, bpc);
1249                 writel(word, vop->lut_regs + i * 4);
1250         }
1251 }
1252
1253 static void vop_crtc_gamma_set(struct vop *vop, struct drm_crtc *crtc,
1254                                struct drm_crtc_state *old_state)
1255 {
1256         struct drm_crtc_state *state = crtc->state;
1257         unsigned int idle;
1258         u32 lut_idx, old_idx;
1259         int ret;
1260
1261         if (!vop->lut_regs)
1262                 return;
1263
1264         if (!state->gamma_lut || !VOP_HAS_REG(vop, common, update_gamma_lut)) {
1265                 /*
1266                  * To disable gamma (gamma_lut is null) or to write
1267                  * an update to the LUT, clear dsp_lut_en.
1268                  */
1269                 spin_lock(&vop->reg_lock);
1270                 VOP_REG_SET(vop, common, dsp_lut_en, 0);
1271                 vop_cfg_done(vop);
1272                 spin_unlock(&vop->reg_lock);
1273
1274                 /*
1275                  * In order to write the LUT to the internal memory,
1276                  * we need to first make sure the dsp_lut_en bit is cleared.
1277                  */
1278                 ret = readx_poll_timeout(vop_dsp_lut_is_enabled, vop,
1279                                          idle, !idle, 5, 30 * 1000);
1280                 if (ret) {
1281                         DRM_DEV_ERROR(vop->dev, "display LUT RAM enable timeout!\n");
1282                         return;
1283                 }
1284
1285                 if (!state->gamma_lut)
1286                         return;
1287         } else {
1288                 /*
1289                  * On RK3399 the gamma LUT can updated without clearing dsp_lut_en,
1290                  * by setting update_gamma_lut then waiting for lut_buffer_index change
1291                  */
1292                 old_idx = vop_lut_buffer_index(vop);
1293         }
1294
1295         spin_lock(&vop->reg_lock);
1296         vop_crtc_write_gamma_lut(vop, crtc);
1297         VOP_REG_SET(vop, common, dsp_lut_en, 1);
1298         VOP_REG_SET(vop, common, update_gamma_lut, 1);
1299         vop_cfg_done(vop);
1300         spin_unlock(&vop->reg_lock);
1301
1302         if (VOP_HAS_REG(vop, common, update_gamma_lut)) {
1303                 ret = readx_poll_timeout(vop_lut_buffer_index, vop,
1304                                          lut_idx, lut_idx != old_idx, 5, 30 * 1000);
1305                 if (ret) {
1306                         DRM_DEV_ERROR(vop->dev, "gamma LUT update timeout!\n");
1307                         return;
1308                 }
1309
1310                 /*
1311                  * update_gamma_lut is auto cleared by HW, but write 0 to clear the bit
1312                  * in our backup of the regs.
1313                  */
1314                 spin_lock(&vop->reg_lock);
1315                 VOP_REG_SET(vop, common, update_gamma_lut, 0);
1316                 spin_unlock(&vop->reg_lock);
1317         }
1318 }
1319
1320 static void vop_crtc_atomic_begin(struct drm_crtc *crtc,
1321                                   struct drm_atomic_state *state)
1322 {
1323         struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,
1324                                                                           crtc);
1325         struct drm_crtc_state *old_crtc_state = drm_atomic_get_old_crtc_state(state,
1326                                                                               crtc);
1327         struct vop *vop = to_vop(crtc);
1328
1329         /*
1330          * Only update GAMMA if the 'active' flag is not changed,
1331          * otherwise it's updated by .atomic_enable.
1332          */
1333         if (crtc_state->color_mgmt_changed &&
1334             !crtc_state->active_changed)
1335                 vop_crtc_gamma_set(vop, crtc, old_crtc_state);
1336 }
1337
1338 static void vop_crtc_atomic_enable(struct drm_crtc *crtc,
1339                                    struct drm_atomic_state *state)
1340 {
1341         struct drm_crtc_state *old_state = drm_atomic_get_old_crtc_state(state,
1342                                                                          crtc);
1343         struct vop *vop = to_vop(crtc);
1344         const struct vop_data *vop_data = vop->data;
1345         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state);
1346         struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode;
1347         u16 hsync_len = adjusted_mode->hsync_end - adjusted_mode->hsync_start;
1348         u16 hdisplay = adjusted_mode->hdisplay;
1349         u16 htotal = adjusted_mode->htotal;
1350         u16 hact_st = adjusted_mode->htotal - adjusted_mode->hsync_start;
1351         u16 hact_end = hact_st + hdisplay;
1352         u16 vdisplay = adjusted_mode->vdisplay;
1353         u16 vtotal = adjusted_mode->vtotal;
1354         u16 vsync_len = adjusted_mode->vsync_end - adjusted_mode->vsync_start;
1355         u16 vact_st = adjusted_mode->vtotal - adjusted_mode->vsync_start;
1356         u16 vact_end = vact_st + vdisplay;
1357         uint32_t pin_pol, val;
1358         int dither_bpc = s->output_bpc ? s->output_bpc : 10;
1359         int ret;
1360
1361         if (old_state && old_state->self_refresh_active) {
1362                 drm_crtc_vblank_on(crtc);
1363                 rockchip_drm_set_win_enabled(crtc, true);
1364                 return;
1365         }
1366
1367         mutex_lock(&vop->vop_lock);
1368
1369         WARN_ON(vop->event);
1370
1371         ret = vop_enable(crtc, old_state);
1372         if (ret) {
1373                 mutex_unlock(&vop->vop_lock);
1374                 DRM_DEV_ERROR(vop->dev, "Failed to enable vop (%d)\n", ret);
1375                 return;
1376         }
1377         pin_pol = (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) ?
1378                    BIT(HSYNC_POSITIVE) : 0;
1379         pin_pol |= (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) ?
1380                    BIT(VSYNC_POSITIVE) : 0;
1381         VOP_REG_SET(vop, output, pin_pol, pin_pol);
1382         VOP_REG_SET(vop, output, mipi_dual_channel_en, 0);
1383
1384         switch (s->output_type) {
1385         case DRM_MODE_CONNECTOR_LVDS:
1386                 VOP_REG_SET(vop, output, rgb_dclk_pol, 1);
1387                 VOP_REG_SET(vop, output, rgb_pin_pol, pin_pol);
1388                 VOP_REG_SET(vop, output, rgb_en, 1);
1389                 break;
1390         case DRM_MODE_CONNECTOR_eDP:
1391                 VOP_REG_SET(vop, output, edp_dclk_pol, 1);
1392                 VOP_REG_SET(vop, output, edp_pin_pol, pin_pol);
1393                 VOP_REG_SET(vop, output, edp_en, 1);
1394                 break;
1395         case DRM_MODE_CONNECTOR_HDMIA:
1396                 VOP_REG_SET(vop, output, hdmi_dclk_pol, 1);
1397                 VOP_REG_SET(vop, output, hdmi_pin_pol, pin_pol);
1398                 VOP_REG_SET(vop, output, hdmi_en, 1);
1399                 break;
1400         case DRM_MODE_CONNECTOR_DSI:
1401                 VOP_REG_SET(vop, output, mipi_dclk_pol, 1);
1402                 VOP_REG_SET(vop, output, mipi_pin_pol, pin_pol);
1403                 VOP_REG_SET(vop, output, mipi_en, 1);
1404                 VOP_REG_SET(vop, output, mipi_dual_channel_en,
1405                             !!(s->output_flags & ROCKCHIP_OUTPUT_DSI_DUAL));
1406                 break;
1407         case DRM_MODE_CONNECTOR_DisplayPort:
1408                 VOP_REG_SET(vop, output, dp_dclk_pol, 0);
1409                 VOP_REG_SET(vop, output, dp_pin_pol, pin_pol);
1410                 VOP_REG_SET(vop, output, dp_en, 1);
1411                 break;
1412         default:
1413                 DRM_DEV_ERROR(vop->dev, "unsupported connector_type [%d]\n",
1414                               s->output_type);
1415         }
1416
1417         /*
1418          * if vop is not support RGB10 output, need force RGB10 to RGB888.
1419          */
1420         if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA &&
1421             !(vop_data->feature & VOP_FEATURE_OUTPUT_RGB10))
1422                 s->output_mode = ROCKCHIP_OUT_MODE_P888;
1423
1424         if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA && dither_bpc <= 8)
1425                 VOP_REG_SET(vop, common, pre_dither_down, 1);
1426         else
1427                 VOP_REG_SET(vop, common, pre_dither_down, 0);
1428
1429         if (dither_bpc == 6) {
1430                 VOP_REG_SET(vop, common, dither_down_sel, DITHER_DOWN_ALLEGRO);
1431                 VOP_REG_SET(vop, common, dither_down_mode, RGB888_TO_RGB666);
1432                 VOP_REG_SET(vop, common, dither_down_en, 1);
1433         } else {
1434                 VOP_REG_SET(vop, common, dither_down_en, 0);
1435         }
1436
1437         VOP_REG_SET(vop, common, out_mode, s->output_mode);
1438
1439         VOP_REG_SET(vop, modeset, htotal_pw, (htotal << 16) | hsync_len);
1440         val = hact_st << 16;
1441         val |= hact_end;
1442         VOP_REG_SET(vop, modeset, hact_st_end, val);
1443         VOP_REG_SET(vop, modeset, hpost_st_end, val);
1444
1445         VOP_REG_SET(vop, modeset, vtotal_pw, (vtotal << 16) | vsync_len);
1446         val = vact_st << 16;
1447         val |= vact_end;
1448         VOP_REG_SET(vop, modeset, vact_st_end, val);
1449         VOP_REG_SET(vop, modeset, vpost_st_end, val);
1450
1451         VOP_REG_SET(vop, intr, line_flag_num[0], vact_end);
1452
1453         clk_set_rate(vop->dclk, adjusted_mode->clock * 1000);
1454
1455         VOP_REG_SET(vop, common, standby, 0);
1456         mutex_unlock(&vop->vop_lock);
1457
1458         /*
1459          * If we have a GAMMA LUT in the state, then let's make sure
1460          * it's updated. We might be coming out of suspend,
1461          * which means the LUT internal memory needs to be re-written.
1462          */
1463         if (crtc->state->gamma_lut)
1464                 vop_crtc_gamma_set(vop, crtc, old_state);
1465 }
1466
1467 static bool vop_fs_irq_is_pending(struct vop *vop)
1468 {
1469         return VOP_INTR_GET_TYPE(vop, status, FS_INTR);
1470 }
1471
1472 static void vop_wait_for_irq_handler(struct vop *vop)
1473 {
1474         bool pending;
1475         int ret;
1476
1477         /*
1478          * Spin until frame start interrupt status bit goes low, which means
1479          * that interrupt handler was invoked and cleared it. The timeout of
1480          * 10 msecs is really too long, but it is just a safety measure if
1481          * something goes really wrong. The wait will only happen in the very
1482          * unlikely case of a vblank happening exactly at the same time and
1483          * shouldn't exceed microseconds range.
1484          */
1485         ret = readx_poll_timeout_atomic(vop_fs_irq_is_pending, vop, pending,
1486                                         !pending, 0, 10 * 1000);
1487         if (ret)
1488                 DRM_DEV_ERROR(vop->dev, "VOP vblank IRQ stuck for 10 ms\n");
1489
1490         synchronize_irq(vop->irq);
1491 }
1492
1493 static int vop_crtc_atomic_check(struct drm_crtc *crtc,
1494                                  struct drm_atomic_state *state)
1495 {
1496         struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,
1497                                                                           crtc);
1498         struct vop *vop = to_vop(crtc);
1499         struct drm_plane *plane;
1500         struct drm_plane_state *plane_state;
1501         struct rockchip_crtc_state *s;
1502         int afbc_planes = 0;
1503
1504         if (vop->lut_regs && crtc_state->color_mgmt_changed &&
1505             crtc_state->gamma_lut) {
1506                 unsigned int len;
1507
1508                 len = drm_color_lut_size(crtc_state->gamma_lut);
1509                 if (len != crtc->gamma_size) {
1510                         DRM_DEBUG_KMS("Invalid LUT size; got %d, expected %d\n",
1511                                       len, crtc->gamma_size);
1512                         return -EINVAL;
1513                 }
1514         }
1515
1516         drm_atomic_crtc_state_for_each_plane(plane, crtc_state) {
1517                 plane_state =
1518                         drm_atomic_get_plane_state(crtc_state->state, plane);
1519                 if (IS_ERR(plane_state)) {
1520                         DRM_DEBUG_KMS("Cannot get plane state for plane %s\n",
1521                                       plane->name);
1522                         return PTR_ERR(plane_state);
1523                 }
1524
1525                 if (drm_is_afbc(plane_state->fb->modifier))
1526                         ++afbc_planes;
1527         }
1528
1529         if (afbc_planes > 1) {
1530                 DRM_DEBUG_KMS("Invalid number of AFBC planes; got %d, expected at most 1\n", afbc_planes);
1531                 return -EINVAL;
1532         }
1533
1534         s = to_rockchip_crtc_state(crtc_state);
1535         s->enable_afbc = afbc_planes > 0;
1536
1537         return 0;
1538 }
1539
1540 static void vop_crtc_atomic_flush(struct drm_crtc *crtc,
1541                                   struct drm_atomic_state *state)
1542 {
1543         struct drm_crtc_state *old_crtc_state = drm_atomic_get_old_crtc_state(state,
1544                                                                               crtc);
1545         struct drm_atomic_state *old_state = old_crtc_state->state;
1546         struct drm_plane_state *old_plane_state, *new_plane_state;
1547         struct vop *vop = to_vop(crtc);
1548         struct drm_plane *plane;
1549         struct rockchip_crtc_state *s;
1550         int i;
1551
1552         if (WARN_ON(!vop->is_enabled))
1553                 return;
1554
1555         spin_lock(&vop->reg_lock);
1556
1557         /* Enable AFBC if there is some AFBC window, disable otherwise. */
1558         s = to_rockchip_crtc_state(crtc->state);
1559         VOP_AFBC_SET(vop, enable, s->enable_afbc);
1560         vop_cfg_done(vop);
1561
1562         spin_unlock(&vop->reg_lock);
1563
1564         /*
1565          * There is a (rather unlikely) possiblity that a vblank interrupt
1566          * fired before we set the cfg_done bit. To avoid spuriously
1567          * signalling flip completion we need to wait for it to finish.
1568          */
1569         vop_wait_for_irq_handler(vop);
1570
1571         spin_lock_irq(&crtc->dev->event_lock);
1572         if (crtc->state->event) {
1573                 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
1574                 WARN_ON(vop->event);
1575
1576                 vop->event = crtc->state->event;
1577                 crtc->state->event = NULL;
1578         }
1579         spin_unlock_irq(&crtc->dev->event_lock);
1580
1581         for_each_oldnew_plane_in_state(old_state, plane, old_plane_state,
1582                                        new_plane_state, i) {
1583                 if (!old_plane_state->fb)
1584                         continue;
1585
1586                 if (old_plane_state->fb == new_plane_state->fb)
1587                         continue;
1588
1589                 drm_framebuffer_get(old_plane_state->fb);
1590                 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
1591                 drm_flip_work_queue(&vop->fb_unref_work, old_plane_state->fb);
1592                 set_bit(VOP_PENDING_FB_UNREF, &vop->pending);
1593         }
1594 }
1595
1596 static const struct drm_crtc_helper_funcs vop_crtc_helper_funcs = {
1597         .mode_valid = vop_crtc_mode_valid,
1598         .mode_fixup = vop_crtc_mode_fixup,
1599         .atomic_check = vop_crtc_atomic_check,
1600         .atomic_begin = vop_crtc_atomic_begin,
1601         .atomic_flush = vop_crtc_atomic_flush,
1602         .atomic_enable = vop_crtc_atomic_enable,
1603         .atomic_disable = vop_crtc_atomic_disable,
1604 };
1605
1606 static void vop_crtc_destroy(struct drm_crtc *crtc)
1607 {
1608         drm_crtc_cleanup(crtc);
1609 }
1610
1611 static struct drm_crtc_state *vop_crtc_duplicate_state(struct drm_crtc *crtc)
1612 {
1613         struct rockchip_crtc_state *rockchip_state;
1614
1615         if (WARN_ON(!crtc->state))
1616                 return NULL;
1617
1618         rockchip_state = kzalloc(sizeof(*rockchip_state), GFP_KERNEL);
1619         if (!rockchip_state)
1620                 return NULL;
1621
1622         __drm_atomic_helper_crtc_duplicate_state(crtc, &rockchip_state->base);
1623         return &rockchip_state->base;
1624 }
1625
1626 static void vop_crtc_destroy_state(struct drm_crtc *crtc,
1627                                    struct drm_crtc_state *state)
1628 {
1629         struct rockchip_crtc_state *s = to_rockchip_crtc_state(state);
1630
1631         __drm_atomic_helper_crtc_destroy_state(&s->base);
1632         kfree(s);
1633 }
1634
1635 static void vop_crtc_reset(struct drm_crtc *crtc)
1636 {
1637         struct rockchip_crtc_state *crtc_state =
1638                 kzalloc(sizeof(*crtc_state), GFP_KERNEL);
1639
1640         if (crtc->state)
1641                 vop_crtc_destroy_state(crtc, crtc->state);
1642
1643         __drm_atomic_helper_crtc_reset(crtc, &crtc_state->base);
1644 }
1645
1646 #ifdef CONFIG_DRM_ANALOGIX_DP
1647 static struct drm_connector *vop_get_edp_connector(struct vop *vop)
1648 {
1649         struct drm_connector *connector;
1650         struct drm_connector_list_iter conn_iter;
1651
1652         drm_connector_list_iter_begin(vop->drm_dev, &conn_iter);
1653         drm_for_each_connector_iter(connector, &conn_iter) {
1654                 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1655                         drm_connector_list_iter_end(&conn_iter);
1656                         return connector;
1657                 }
1658         }
1659         drm_connector_list_iter_end(&conn_iter);
1660
1661         return NULL;
1662 }
1663
1664 static int vop_crtc_set_crc_source(struct drm_crtc *crtc,
1665                                    const char *source_name)
1666 {
1667         struct vop *vop = to_vop(crtc);
1668         struct drm_connector *connector;
1669         int ret;
1670
1671         connector = vop_get_edp_connector(vop);
1672         if (!connector)
1673                 return -EINVAL;
1674
1675         if (source_name && strcmp(source_name, "auto") == 0)
1676                 ret = analogix_dp_start_crc(connector);
1677         else if (!source_name)
1678                 ret = analogix_dp_stop_crc(connector);
1679         else
1680                 ret = -EINVAL;
1681
1682         return ret;
1683 }
1684
1685 static int
1686 vop_crtc_verify_crc_source(struct drm_crtc *crtc, const char *source_name,
1687                            size_t *values_cnt)
1688 {
1689         if (source_name && strcmp(source_name, "auto") != 0)
1690                 return -EINVAL;
1691
1692         *values_cnt = 3;
1693         return 0;
1694 }
1695
1696 #else
1697 static int vop_crtc_set_crc_source(struct drm_crtc *crtc,
1698                                    const char *source_name)
1699 {
1700         return -ENODEV;
1701 }
1702
1703 static int
1704 vop_crtc_verify_crc_source(struct drm_crtc *crtc, const char *source_name,
1705                            size_t *values_cnt)
1706 {
1707         return -ENODEV;
1708 }
1709 #endif
1710
1711 static const struct drm_crtc_funcs vop_crtc_funcs = {
1712         .set_config = drm_atomic_helper_set_config,
1713         .page_flip = drm_atomic_helper_page_flip,
1714         .destroy = vop_crtc_destroy,
1715         .reset = vop_crtc_reset,
1716         .atomic_duplicate_state = vop_crtc_duplicate_state,
1717         .atomic_destroy_state = vop_crtc_destroy_state,
1718         .enable_vblank = vop_crtc_enable_vblank,
1719         .disable_vblank = vop_crtc_disable_vblank,
1720         .set_crc_source = vop_crtc_set_crc_source,
1721         .verify_crc_source = vop_crtc_verify_crc_source,
1722 };
1723
1724 static void vop_fb_unref_worker(struct drm_flip_work *work, void *val)
1725 {
1726         struct vop *vop = container_of(work, struct vop, fb_unref_work);
1727         struct drm_framebuffer *fb = val;
1728
1729         drm_crtc_vblank_put(&vop->crtc);
1730         drm_framebuffer_put(fb);
1731 }
1732
1733 static void vop_handle_vblank(struct vop *vop)
1734 {
1735         struct drm_device *drm = vop->drm_dev;
1736         struct drm_crtc *crtc = &vop->crtc;
1737
1738         spin_lock(&drm->event_lock);
1739         if (vop->event) {
1740                 drm_crtc_send_vblank_event(crtc, vop->event);
1741                 drm_crtc_vblank_put(crtc);
1742                 vop->event = NULL;
1743         }
1744         spin_unlock(&drm->event_lock);
1745
1746         if (test_and_clear_bit(VOP_PENDING_FB_UNREF, &vop->pending))
1747                 drm_flip_work_commit(&vop->fb_unref_work, system_unbound_wq);
1748 }
1749
1750 static irqreturn_t vop_isr(int irq, void *data)
1751 {
1752         struct vop *vop = data;
1753         struct drm_crtc *crtc = &vop->crtc;
1754         uint32_t active_irqs;
1755         int ret = IRQ_NONE;
1756
1757         /*
1758          * The irq is shared with the iommu. If the runtime-pm state of the
1759          * vop-device is disabled the irq has to be targeted at the iommu.
1760          */
1761         if (!pm_runtime_get_if_in_use(vop->dev))
1762                 return IRQ_NONE;
1763
1764         if (vop_core_clks_enable(vop)) {
1765                 DRM_DEV_ERROR_RATELIMITED(vop->dev, "couldn't enable clocks\n");
1766                 goto out;
1767         }
1768
1769         /*
1770          * interrupt register has interrupt status, enable and clear bits, we
1771          * must hold irq_lock to avoid a race with enable/disable_vblank().
1772         */
1773         spin_lock(&vop->irq_lock);
1774
1775         active_irqs = VOP_INTR_GET_TYPE(vop, status, INTR_MASK);
1776         /* Clear all active interrupt sources */
1777         if (active_irqs)
1778                 VOP_INTR_SET_TYPE(vop, clear, active_irqs, 1);
1779
1780         spin_unlock(&vop->irq_lock);
1781
1782         /* This is expected for vop iommu irqs, since the irq is shared */
1783         if (!active_irqs)
1784                 goto out_disable;
1785
1786         if (active_irqs & DSP_HOLD_VALID_INTR) {
1787                 complete(&vop->dsp_hold_completion);
1788                 active_irqs &= ~DSP_HOLD_VALID_INTR;
1789                 ret = IRQ_HANDLED;
1790         }
1791
1792         if (active_irqs & LINE_FLAG_INTR) {
1793                 complete(&vop->line_flag_completion);
1794                 active_irqs &= ~LINE_FLAG_INTR;
1795                 ret = IRQ_HANDLED;
1796         }
1797
1798         if (active_irqs & FS_INTR) {
1799                 drm_crtc_handle_vblank(crtc);
1800                 vop_handle_vblank(vop);
1801                 active_irqs &= ~FS_INTR;
1802                 ret = IRQ_HANDLED;
1803         }
1804
1805         /* Unhandled irqs are spurious. */
1806         if (active_irqs)
1807                 DRM_DEV_ERROR(vop->dev, "Unknown VOP IRQs: %#02x\n",
1808                               active_irqs);
1809
1810 out_disable:
1811         vop_core_clks_disable(vop);
1812 out:
1813         pm_runtime_put(vop->dev);
1814         return ret;
1815 }
1816
1817 static void vop_plane_add_properties(struct drm_plane *plane,
1818                                      const struct vop_win_data *win_data)
1819 {
1820         unsigned int flags = 0;
1821
1822         flags |= VOP_WIN_HAS_REG(win_data, x_mir_en) ? DRM_MODE_REFLECT_X : 0;
1823         flags |= VOP_WIN_HAS_REG(win_data, y_mir_en) ? DRM_MODE_REFLECT_Y : 0;
1824         if (flags)
1825                 drm_plane_create_rotation_property(plane, DRM_MODE_ROTATE_0,
1826                                                    DRM_MODE_ROTATE_0 | flags);
1827 }
1828
1829 static int vop_create_crtc(struct vop *vop)
1830 {
1831         const struct vop_data *vop_data = vop->data;
1832         struct device *dev = vop->dev;
1833         struct drm_device *drm_dev = vop->drm_dev;
1834         struct drm_plane *primary = NULL, *cursor = NULL, *plane, *tmp;
1835         struct drm_crtc *crtc = &vop->crtc;
1836         struct device_node *port;
1837         int ret;
1838         int i;
1839
1840         /*
1841          * Create drm_plane for primary and cursor planes first, since we need
1842          * to pass them to drm_crtc_init_with_planes, which sets the
1843          * "possible_crtcs" to the newly initialized crtc.
1844          */
1845         for (i = 0; i < vop_data->win_size; i++) {
1846                 struct vop_win *vop_win = &vop->win[i];
1847                 const struct vop_win_data *win_data = vop_win->data;
1848
1849                 if (win_data->type != DRM_PLANE_TYPE_PRIMARY &&
1850                     win_data->type != DRM_PLANE_TYPE_CURSOR)
1851                         continue;
1852
1853                 ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base,
1854                                                0, &vop_plane_funcs,
1855                                                win_data->phy->data_formats,
1856                                                win_data->phy->nformats,
1857                                                win_data->phy->format_modifiers,
1858                                                win_data->type, NULL);
1859                 if (ret) {
1860                         DRM_DEV_ERROR(vop->dev, "failed to init plane %d\n",
1861                                       ret);
1862                         goto err_cleanup_planes;
1863                 }
1864
1865                 plane = &vop_win->base;
1866                 drm_plane_helper_add(plane, &plane_helper_funcs);
1867                 vop_plane_add_properties(plane, win_data);
1868                 if (plane->type == DRM_PLANE_TYPE_PRIMARY)
1869                         primary = plane;
1870                 else if (plane->type == DRM_PLANE_TYPE_CURSOR)
1871                         cursor = plane;
1872         }
1873
1874         ret = drm_crtc_init_with_planes(drm_dev, crtc, primary, cursor,
1875                                         &vop_crtc_funcs, NULL);
1876         if (ret)
1877                 goto err_cleanup_planes;
1878
1879         drm_crtc_helper_add(crtc, &vop_crtc_helper_funcs);
1880         if (vop->lut_regs) {
1881                 drm_mode_crtc_set_gamma_size(crtc, vop_data->lut_size);
1882                 drm_crtc_enable_color_mgmt(crtc, 0, false, vop_data->lut_size);
1883         }
1884
1885         /*
1886          * Create drm_planes for overlay windows with possible_crtcs restricted
1887          * to the newly created crtc.
1888          */
1889         for (i = 0; i < vop_data->win_size; i++) {
1890                 struct vop_win *vop_win = &vop->win[i];
1891                 const struct vop_win_data *win_data = vop_win->data;
1892                 unsigned long possible_crtcs = drm_crtc_mask(crtc);
1893
1894                 if (win_data->type != DRM_PLANE_TYPE_OVERLAY)
1895                         continue;
1896
1897                 ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base,
1898                                                possible_crtcs,
1899                                                &vop_plane_funcs,
1900                                                win_data->phy->data_formats,
1901                                                win_data->phy->nformats,
1902                                                win_data->phy->format_modifiers,
1903                                                win_data->type, NULL);
1904                 if (ret) {
1905                         DRM_DEV_ERROR(vop->dev, "failed to init overlay %d\n",
1906                                       ret);
1907                         goto err_cleanup_crtc;
1908                 }
1909                 drm_plane_helper_add(&vop_win->base, &plane_helper_funcs);
1910                 vop_plane_add_properties(&vop_win->base, win_data);
1911         }
1912
1913         port = of_get_child_by_name(dev->of_node, "port");
1914         if (!port) {
1915                 DRM_DEV_ERROR(vop->dev, "no port node found in %pOF\n",
1916                               dev->of_node);
1917                 ret = -ENOENT;
1918                 goto err_cleanup_crtc;
1919         }
1920
1921         drm_flip_work_init(&vop->fb_unref_work, "fb_unref",
1922                            vop_fb_unref_worker);
1923
1924         init_completion(&vop->dsp_hold_completion);
1925         init_completion(&vop->line_flag_completion);
1926         crtc->port = port;
1927
1928         ret = drm_self_refresh_helper_init(crtc);
1929         if (ret)
1930                 DRM_DEV_DEBUG_KMS(vop->dev,
1931                         "Failed to init %s with SR helpers %d, ignoring\n",
1932                         crtc->name, ret);
1933
1934         return 0;
1935
1936 err_cleanup_crtc:
1937         drm_crtc_cleanup(crtc);
1938 err_cleanup_planes:
1939         list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list,
1940                                  head)
1941                 drm_plane_cleanup(plane);
1942         return ret;
1943 }
1944
1945 static void vop_destroy_crtc(struct vop *vop)
1946 {
1947         struct drm_crtc *crtc = &vop->crtc;
1948         struct drm_device *drm_dev = vop->drm_dev;
1949         struct drm_plane *plane, *tmp;
1950
1951         drm_self_refresh_helper_cleanup(crtc);
1952
1953         of_node_put(crtc->port);
1954
1955         /*
1956          * We need to cleanup the planes now.  Why?
1957          *
1958          * The planes are "&vop->win[i].base".  That means the memory is
1959          * all part of the big "struct vop" chunk of memory.  That memory
1960          * was devm allocated and associated with this component.  We need to
1961          * free it ourselves before vop_unbind() finishes.
1962          */
1963         list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list,
1964                                  head)
1965                 vop_plane_destroy(plane);
1966
1967         /*
1968          * Destroy CRTC after vop_plane_destroy() since vop_disable_plane()
1969          * references the CRTC.
1970          */
1971         drm_crtc_cleanup(crtc);
1972         drm_flip_work_cleanup(&vop->fb_unref_work);
1973 }
1974
1975 static int vop_initial(struct vop *vop)
1976 {
1977         struct reset_control *ahb_rst;
1978         int i, ret;
1979
1980         vop->hclk = devm_clk_get(vop->dev, "hclk_vop");
1981         if (IS_ERR(vop->hclk)) {
1982                 DRM_DEV_ERROR(vop->dev, "failed to get hclk source\n");
1983                 return PTR_ERR(vop->hclk);
1984         }
1985         vop->aclk = devm_clk_get(vop->dev, "aclk_vop");
1986         if (IS_ERR(vop->aclk)) {
1987                 DRM_DEV_ERROR(vop->dev, "failed to get aclk source\n");
1988                 return PTR_ERR(vop->aclk);
1989         }
1990         vop->dclk = devm_clk_get(vop->dev, "dclk_vop");
1991         if (IS_ERR(vop->dclk)) {
1992                 DRM_DEV_ERROR(vop->dev, "failed to get dclk source\n");
1993                 return PTR_ERR(vop->dclk);
1994         }
1995
1996         ret = pm_runtime_resume_and_get(vop->dev);
1997         if (ret < 0) {
1998                 DRM_DEV_ERROR(vop->dev, "failed to get pm runtime: %d\n", ret);
1999                 return ret;
2000         }
2001
2002         ret = clk_prepare(vop->dclk);
2003         if (ret < 0) {
2004                 DRM_DEV_ERROR(vop->dev, "failed to prepare dclk\n");
2005                 goto err_put_pm_runtime;
2006         }
2007
2008         /* Enable both the hclk and aclk to setup the vop */
2009         ret = clk_prepare_enable(vop->hclk);
2010         if (ret < 0) {
2011                 DRM_DEV_ERROR(vop->dev, "failed to prepare/enable hclk\n");
2012                 goto err_unprepare_dclk;
2013         }
2014
2015         ret = clk_prepare_enable(vop->aclk);
2016         if (ret < 0) {
2017                 DRM_DEV_ERROR(vop->dev, "failed to prepare/enable aclk\n");
2018                 goto err_disable_hclk;
2019         }
2020
2021         /*
2022          * do hclk_reset, reset all vop registers.
2023          */
2024         ahb_rst = devm_reset_control_get(vop->dev, "ahb");
2025         if (IS_ERR(ahb_rst)) {
2026                 DRM_DEV_ERROR(vop->dev, "failed to get ahb reset\n");
2027                 ret = PTR_ERR(ahb_rst);
2028                 goto err_disable_aclk;
2029         }
2030         reset_control_assert(ahb_rst);
2031         usleep_range(10, 20);
2032         reset_control_deassert(ahb_rst);
2033
2034         VOP_INTR_SET_TYPE(vop, clear, INTR_MASK, 1);
2035         VOP_INTR_SET_TYPE(vop, enable, INTR_MASK, 0);
2036
2037         for (i = 0; i < vop->len; i += sizeof(u32))
2038                 vop->regsbak[i / 4] = readl_relaxed(vop->regs + i);
2039
2040         VOP_REG_SET(vop, misc, global_regdone_en, 1);
2041         VOP_REG_SET(vop, common, dsp_blank, 0);
2042
2043         for (i = 0; i < vop->data->win_size; i++) {
2044                 struct vop_win *vop_win = &vop->win[i];
2045                 const struct vop_win_data *win = vop_win->data;
2046                 int channel = i * 2 + 1;
2047
2048                 VOP_WIN_SET(vop, win, channel, (channel + 1) << 4 | channel);
2049                 vop_win_disable(vop, vop_win);
2050                 VOP_WIN_SET(vop, win, gate, 1);
2051         }
2052
2053         vop_cfg_done(vop);
2054
2055         /*
2056          * do dclk_reset, let all config take affect.
2057          */
2058         vop->dclk_rst = devm_reset_control_get(vop->dev, "dclk");
2059         if (IS_ERR(vop->dclk_rst)) {
2060                 DRM_DEV_ERROR(vop->dev, "failed to get dclk reset\n");
2061                 ret = PTR_ERR(vop->dclk_rst);
2062                 goto err_disable_aclk;
2063         }
2064         reset_control_assert(vop->dclk_rst);
2065         usleep_range(10, 20);
2066         reset_control_deassert(vop->dclk_rst);
2067
2068         clk_disable(vop->hclk);
2069         clk_disable(vop->aclk);
2070
2071         vop->is_enabled = false;
2072
2073         pm_runtime_put_sync(vop->dev);
2074
2075         return 0;
2076
2077 err_disable_aclk:
2078         clk_disable_unprepare(vop->aclk);
2079 err_disable_hclk:
2080         clk_disable_unprepare(vop->hclk);
2081 err_unprepare_dclk:
2082         clk_unprepare(vop->dclk);
2083 err_put_pm_runtime:
2084         pm_runtime_put_sync(vop->dev);
2085         return ret;
2086 }
2087
2088 /*
2089  * Initialize the vop->win array elements.
2090  */
2091 static void vop_win_init(struct vop *vop)
2092 {
2093         const struct vop_data *vop_data = vop->data;
2094         unsigned int i;
2095
2096         for (i = 0; i < vop_data->win_size; i++) {
2097                 struct vop_win *vop_win = &vop->win[i];
2098                 const struct vop_win_data *win_data = &vop_data->win[i];
2099
2100                 vop_win->data = win_data;
2101                 vop_win->vop = vop;
2102
2103                 if (vop_data->win_yuv2yuv)
2104                         vop_win->yuv2yuv_data = &vop_data->win_yuv2yuv[i];
2105         }
2106 }
2107
2108 /**
2109  * rockchip_drm_wait_vact_end
2110  * @crtc: CRTC to enable line flag
2111  * @mstimeout: millisecond for timeout
2112  *
2113  * Wait for vact_end line flag irq or timeout.
2114  *
2115  * Returns:
2116  * Zero on success, negative errno on failure.
2117  */
2118 int rockchip_drm_wait_vact_end(struct drm_crtc *crtc, unsigned int mstimeout)
2119 {
2120         struct vop *vop = to_vop(crtc);
2121         unsigned long jiffies_left;
2122         int ret = 0;
2123
2124         if (!crtc || !vop->is_enabled)
2125                 return -ENODEV;
2126
2127         mutex_lock(&vop->vop_lock);
2128         if (mstimeout <= 0) {
2129                 ret = -EINVAL;
2130                 goto out;
2131         }
2132
2133         if (vop_line_flag_irq_is_enabled(vop)) {
2134                 ret = -EBUSY;
2135                 goto out;
2136         }
2137
2138         reinit_completion(&vop->line_flag_completion);
2139         vop_line_flag_irq_enable(vop);
2140
2141         jiffies_left = wait_for_completion_timeout(&vop->line_flag_completion,
2142                                                    msecs_to_jiffies(mstimeout));
2143         vop_line_flag_irq_disable(vop);
2144
2145         if (jiffies_left == 0) {
2146                 DRM_DEV_ERROR(vop->dev, "Timeout waiting for IRQ\n");
2147                 ret = -ETIMEDOUT;
2148                 goto out;
2149         }
2150
2151 out:
2152         mutex_unlock(&vop->vop_lock);
2153         return ret;
2154 }
2155 EXPORT_SYMBOL(rockchip_drm_wait_vact_end);
2156
2157 static int vop_bind(struct device *dev, struct device *master, void *data)
2158 {
2159         struct platform_device *pdev = to_platform_device(dev);
2160         const struct vop_data *vop_data;
2161         struct drm_device *drm_dev = data;
2162         struct vop *vop;
2163         struct resource *res;
2164         int ret, irq;
2165
2166         vop_data = of_device_get_match_data(dev);
2167         if (!vop_data)
2168                 return -ENODEV;
2169
2170         /* Allocate vop struct and its vop_win array */
2171         vop = devm_kzalloc(dev, struct_size(vop, win, vop_data->win_size),
2172                            GFP_KERNEL);
2173         if (!vop)
2174                 return -ENOMEM;
2175
2176         vop->dev = dev;
2177         vop->data = vop_data;
2178         vop->drm_dev = drm_dev;
2179         dev_set_drvdata(dev, vop);
2180
2181         vop_win_init(vop);
2182
2183         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2184         vop->regs = devm_ioremap_resource(dev, res);
2185         if (IS_ERR(vop->regs))
2186                 return PTR_ERR(vop->regs);
2187         vop->len = resource_size(res);
2188
2189         res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2190         if (res) {
2191                 if (vop_data->lut_size != 1024 && vop_data->lut_size != 256) {
2192                         DRM_DEV_ERROR(dev, "unsupported gamma LUT size %d\n", vop_data->lut_size);
2193                         return -EINVAL;
2194                 }
2195                 vop->lut_regs = devm_ioremap_resource(dev, res);
2196                 if (IS_ERR(vop->lut_regs))
2197                         return PTR_ERR(vop->lut_regs);
2198         }
2199
2200         vop->regsbak = devm_kzalloc(dev, vop->len, GFP_KERNEL);
2201         if (!vop->regsbak)
2202                 return -ENOMEM;
2203
2204         irq = platform_get_irq(pdev, 0);
2205         if (irq < 0) {
2206                 DRM_DEV_ERROR(dev, "cannot find irq for vop\n");
2207                 return irq;
2208         }
2209         vop->irq = (unsigned int)irq;
2210
2211         spin_lock_init(&vop->reg_lock);
2212         spin_lock_init(&vop->irq_lock);
2213         mutex_init(&vop->vop_lock);
2214
2215         ret = vop_create_crtc(vop);
2216         if (ret)
2217                 return ret;
2218
2219         pm_runtime_enable(&pdev->dev);
2220
2221         ret = vop_initial(vop);
2222         if (ret < 0) {
2223                 DRM_DEV_ERROR(&pdev->dev,
2224                               "cannot initial vop dev - err %d\n", ret);
2225                 goto err_disable_pm_runtime;
2226         }
2227
2228         ret = devm_request_irq(dev, vop->irq, vop_isr,
2229                                IRQF_SHARED, dev_name(dev), vop);
2230         if (ret)
2231                 goto err_disable_pm_runtime;
2232
2233         if (vop->data->feature & VOP_FEATURE_INTERNAL_RGB) {
2234                 vop->rgb = rockchip_rgb_init(dev, &vop->crtc, vop->drm_dev, 0);
2235                 if (IS_ERR(vop->rgb)) {
2236                         ret = PTR_ERR(vop->rgb);
2237                         goto err_disable_pm_runtime;
2238                 }
2239         }
2240
2241         rockchip_drm_dma_init_device(drm_dev, dev);
2242
2243         return 0;
2244
2245 err_disable_pm_runtime:
2246         pm_runtime_disable(&pdev->dev);
2247         vop_destroy_crtc(vop);
2248         return ret;
2249 }
2250
2251 static void vop_unbind(struct device *dev, struct device *master, void *data)
2252 {
2253         struct vop *vop = dev_get_drvdata(dev);
2254
2255         if (vop->rgb)
2256                 rockchip_rgb_fini(vop->rgb);
2257
2258         pm_runtime_disable(dev);
2259         vop_destroy_crtc(vop);
2260
2261         clk_unprepare(vop->aclk);
2262         clk_unprepare(vop->hclk);
2263         clk_unprepare(vop->dclk);
2264 }
2265
2266 const struct component_ops vop_component_ops = {
2267         .bind = vop_bind,
2268         .unbind = vop_unbind,
2269 };
2270 EXPORT_SYMBOL_GPL(vop_component_ops);