drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
   4  * Author:
   5  *      Chris Zhong <zyw@rock-chips.com>
   6  *      Nickey Yang <nickey.yang@rock-chips.com>
   7  */
   8
   9 #include <linux/clk.h>
  10 #include <linux/iopoll.h>
  11 #include <linux/math64.h>
  12 #include <linux/mfd/syscon.h>
  13 #include <linux/module.h>
  14 #include <linux/of_device.h>
  15 #include <linux/phy/phy.h>
  16 #include <linux/pm_runtime.h>
  17 #include <linux/regmap.h>
  18
  19 #include <video/mipi_display.h>
  20
  21 #include <drm/bridge/dw_mipi_dsi.h>
  22 #include <drm/drm_mipi_dsi.h>
  23 #include <drm/drm_of.h>
  24 #include <drm/drm_simple_kms_helper.h>
  25
  26 #include "rockchip_drm_drv.h"
  27 #include "rockchip_drm_vop.h"
  28
  29 #define DSI_PHY_RSTZ                    0xa0
  30 #define PHY_DISFORCEPLL                 0
  31 #define PHY_ENFORCEPLL                  BIT(3)
  32 #define PHY_DISABLECLK                  0
  33 #define PHY_ENABLECLK                   BIT(2)
  34 #define PHY_RSTZ                        0
  35 #define PHY_UNRSTZ                      BIT(1)
  36 #define PHY_SHUTDOWNZ                   0
  37 #define PHY_UNSHUTDOWNZ                 BIT(0)
  38
  39 #define DSI_PHY_IF_CFG                  0xa4
  40 #define N_LANES(n)                      ((((n) - 1) & 0x3) << 0)
  41 #define PHY_STOP_WAIT_TIME(cycle)       (((cycle) & 0xff) << 8)
  42
  43 #define DSI_PHY_STATUS                  0xb0
  44 #define LOCK                            BIT(0)
  45 #define STOP_STATE_CLK_LANE             BIT(2)
  46
  47 #define DSI_PHY_TST_CTRL0               0xb4
  48 #define PHY_TESTCLK                     BIT(1)
  49 #define PHY_UNTESTCLK                   0
  50 #define PHY_TESTCLR                     BIT(0)
  51 #define PHY_UNTESTCLR                   0
  52
  53 #define DSI_PHY_TST_CTRL1               0xb8
  54 #define PHY_TESTEN                      BIT(16)
  55 #define PHY_UNTESTEN                    0
  56 #define PHY_TESTDOUT(n)                 (((n) & 0xff) << 8)
  57 #define PHY_TESTDIN(n)                  (((n) & 0xff) << 0)
  58
  59 #define DSI_INT_ST0                     0xbc
  60 #define DSI_INT_ST1                     0xc0
  61 #define DSI_INT_MSK0                    0xc4
  62 #define DSI_INT_MSK1                    0xc8
  63
  64 #define PHY_STATUS_TIMEOUT_US           10000
  65 #define CMD_PKT_STATUS_TIMEOUT_US       20000
  66
  67 #define BYPASS_VCO_RANGE        BIT(7)
  68 #define VCO_RANGE_CON_SEL(val)  (((val) & 0x7) << 3)
  69 #define VCO_IN_CAP_CON_DEFAULT  (0x0 << 1)
  70 #define VCO_IN_CAP_CON_LOW      (0x1 << 1)
  71 #define VCO_IN_CAP_CON_HIGH     (0x2 << 1)
  72 #define REF_BIAS_CUR_SEL        BIT(0)
  73
  74 #define CP_CURRENT_3UA  0x1
  75 #define CP_CURRENT_4_5UA        0x2
  76 #define CP_CURRENT_7_5UA        0x6
  77 #define CP_CURRENT_6UA  0x9
  78 #define CP_CURRENT_12UA 0xb
  79 #define CP_CURRENT_SEL(val)     ((val) & 0xf)
  80 #define CP_PROGRAM_EN           BIT(7)
  81
  82 #define LPF_RESISTORS_15_5KOHM  0x1
  83 #define LPF_RESISTORS_13KOHM    0x2
  84 #define LPF_RESISTORS_11_5KOHM  0x4
  85 #define LPF_RESISTORS_10_5KOHM  0x8
  86 #define LPF_RESISTORS_8KOHM     0x10
  87 #define LPF_PROGRAM_EN          BIT(6)
  88 #define LPF_RESISTORS_SEL(val)  ((val) & 0x3f)
  89
  90 #define HSFREQRANGE_SEL(val)    (((val) & 0x3f) << 1)
  91
  92 #define INPUT_DIVIDER(val)      (((val) - 1) & 0x7f)
  93 #define LOW_PROGRAM_EN          0
  94 #define HIGH_PROGRAM_EN         BIT(7)
  95 #define LOOP_DIV_LOW_SEL(val)   (((val) - 1) & 0x1f)
  96 #define LOOP_DIV_HIGH_SEL(val)  ((((val) - 1) >> 5) & 0xf)
  97 #define PLL_LOOP_DIV_EN         BIT(5)
  98 #define PLL_INPUT_DIV_EN        BIT(4)
  99
 100 #define POWER_CONTROL           BIT(6)
 101 #define INTERNAL_REG_CURRENT    BIT(3)
 102 #define BIAS_BLOCK_ON           BIT(2)
 103 #define BANDGAP_ON              BIT(0)
 104
 105 #define TER_RESISTOR_HIGH       BIT(7)
 106 #define TER_RESISTOR_LOW        0
 107 #define LEVEL_SHIFTERS_ON       BIT(6)
 108 #define TER_CAL_DONE            BIT(5)
 109 #define SETRD_MAX               (0x7 << 2)
 110 #define POWER_MANAGE            BIT(1)
 111 #define TER_RESISTORS_ON        BIT(0)
 112
 113 #define BIASEXTR_SEL(val)       ((val) & 0x7)
 114 #define BANDGAP_SEL(val)        ((val) & 0x7)
 115 #define TLP_PROGRAM_EN          BIT(7)
 116 #define THS_PRE_PROGRAM_EN      BIT(7)
 117 #define THS_ZERO_PROGRAM_EN     BIT(6)
 118
 119 #define PLL_BIAS_CUR_SEL_CAP_VCO_CONTROL                0x10
 120 #define PLL_CP_CONTROL_PLL_LOCK_BYPASS                  0x11
 121 #define PLL_LPF_AND_CP_CONTROL                          0x12
 122 #define PLL_INPUT_DIVIDER_RATIO                         0x17
 123 #define PLL_LOOP_DIVIDER_RATIO                          0x18
 124 #define PLL_INPUT_AND_LOOP_DIVIDER_RATIOS_CONTROL       0x19
 125 #define BANDGAP_AND_BIAS_CONTROL                        0x20
 126 #define TERMINATION_RESISTER_CONTROL                    0x21
 127 #define AFE_BIAS_BANDGAP_ANALOG_PROGRAMMABILITY         0x22
 128 #define HS_RX_CONTROL_OF_LANE_0                         0x44
 129 #define HS_TX_CLOCK_LANE_REQUEST_STATE_TIME_CONTROL     0x60
 130 #define HS_TX_CLOCK_LANE_PREPARE_STATE_TIME_CONTROL     0x61
 131 #define HS_TX_CLOCK_LANE_HS_ZERO_STATE_TIME_CONTROL     0x62
 132 #define HS_TX_CLOCK_LANE_TRAIL_STATE_TIME_CONTROL       0x63
 133 #define HS_TX_CLOCK_LANE_EXIT_STATE_TIME_CONTROL        0x64
 134 #define HS_TX_CLOCK_LANE_POST_TIME_CONTROL              0x65
 135 #define HS_TX_DATA_LANE_REQUEST_STATE_TIME_CONTROL      0x70
 136 #define HS_TX_DATA_LANE_PREPARE_STATE_TIME_CONTROL      0x71
 137 #define HS_TX_DATA_LANE_HS_ZERO_STATE_TIME_CONTROL      0x72
 138 #define HS_TX_DATA_LANE_TRAIL_STATE_TIME_CONTROL        0x73
 139 #define HS_TX_DATA_LANE_EXIT_STATE_TIME_CONTROL         0x74
 140
 141 #define DW_MIPI_NEEDS_PHY_CFG_CLK       BIT(0)
 142 #define DW_MIPI_NEEDS_GRF_CLK           BIT(1)
 143
 144 #define PX30_GRF_PD_VO_CON1             0x0438
 145 #define PX30_DSI_FORCETXSTOPMODE        (0xf << 7)
 146 #define PX30_DSI_FORCERXMODE            BIT(6)
 147 #define PX30_DSI_TURNDISABLE            BIT(5)
 148 #define PX30_DSI_LCDC_SEL               BIT(0)
 149
 150 #define RK3288_GRF_SOC_CON6             0x025c
 151 #define RK3288_DSI0_LCDC_SEL            BIT(6)
 152 #define RK3288_DSI1_LCDC_SEL            BIT(9)
 153
 154 #define RK3399_GRF_SOC_CON20            0x6250
 155 #define RK3399_DSI0_LCDC_SEL            BIT(0)
 156 #define RK3399_DSI1_LCDC_SEL            BIT(4)
 157
 158 #define RK3399_GRF_SOC_CON22            0x6258
 159 #define RK3399_DSI0_TURNREQUEST         (0xf << 12)
 160 #define RK3399_DSI0_TURNDISABLE         (0xf << 8)
 161 #define RK3399_DSI0_FORCETXSTOPMODE     (0xf << 4)
 162 #define RK3399_DSI0_FORCERXMODE         (0xf << 0)
 163
 164 #define RK3399_GRF_SOC_CON23            0x625c
 165 #define RK3399_DSI1_TURNDISABLE         (0xf << 12)
 166 #define RK3399_DSI1_FORCETXSTOPMODE     (0xf << 8)
 167 #define RK3399_DSI1_FORCERXMODE         (0xf << 4)
 168 #define RK3399_DSI1_ENABLE              (0xf << 0)
 169
 170 #define RK3399_GRF_SOC_CON24            0x6260
 171 #define RK3399_TXRX_MASTERSLAVEZ        BIT(7)
 172 #define RK3399_TXRX_ENABLECLK           BIT(6)
 173 #define RK3399_TXRX_BASEDIR             BIT(5)
 174
 175 #define HIWORD_UPDATE(val, mask)        (val | (mask) << 16)
 176
 177 #define to_dsi(nm)      container_of(nm, struct dw_mipi_dsi_rockchip, nm)
 178
 179 enum {
 180         BANDGAP_97_07,
 181         BANDGAP_98_05,
 182         BANDGAP_99_02,
 183         BANDGAP_100_00,
 184         BANDGAP_93_17,
 185         BANDGAP_94_15,
 186         BANDGAP_95_12,
 187         BANDGAP_96_10,
 188 };
 189
 190 enum {
 191         BIASEXTR_87_1,
 192         BIASEXTR_91_5,
 193         BIASEXTR_95_9,
 194         BIASEXTR_100,
 195         BIASEXTR_105_94,
 196         BIASEXTR_111_88,
 197         BIASEXTR_118_8,
 198         BIASEXTR_127_7,
 199 };
 200
 201 struct rockchip_dw_dsi_chip_data {
 202         u32 reg;
 203
 204         u32 lcdsel_grf_reg;
 205         u32 lcdsel_big;
 206         u32 lcdsel_lit;
 207
 208         u32 enable_grf_reg;
 209         u32 enable;
 210
 211         u32 lanecfg1_grf_reg;
 212         u32 lanecfg1;
 213         u32 lanecfg2_grf_reg;
 214         u32 lanecfg2;
 215
 216         unsigned int flags;
 217         unsigned int max_data_lanes;
 218 };
 219
 220 struct dw_mipi_dsi_rockchip {
 221         struct device *dev;
 222         struct drm_encoder encoder;
 223         void __iomem *base;
 224
 225         struct regmap *grf_regmap;
 226         struct clk *pllref_clk;
 227         struct clk *grf_clk;
 228         struct clk *phy_cfg_clk;
 229
 230         /* dual-channel */
 231         bool is_slave;
 232         struct dw_mipi_dsi_rockchip *slave;
 233
 234         /* optional external dphy */
 235         struct phy *phy;
 236         union phy_configure_opts phy_opts;
 237
 238         unsigned int lane_mbps; /* per lane */
 239         u16 input_div;
 240         u16 feedback_div;
 241         u32 format;
 242
 243         struct dw_mipi_dsi *dmd;
 244         const struct rockchip_dw_dsi_chip_data *cdata;
 245         struct dw_mipi_dsi_plat_data pdata;
 246 };
 247
 248 struct dphy_pll_parameter_map {
 249         unsigned int max_mbps;
 250         u8 hsfreqrange;
 251         u8 icpctrl;
 252         u8 lpfctrl;
 253 };
 254
 255 /* The table is based on 27MHz DPHY pll reference clock. */
 256 static const struct dphy_pll_parameter_map dppa_map[] = {
 257         {  89, 0x00, CP_CURRENT_3UA, LPF_RESISTORS_13KOHM },
 258         {  99, 0x10, CP_CURRENT_3UA, LPF_RESISTORS_13KOHM },
 259         { 109, 0x20, CP_CURRENT_3UA, LPF_RESISTORS_13KOHM },
 260         { 129, 0x01, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM },
 261         { 139, 0x11, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM },
 262         { 149, 0x21, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM },
 263         { 169, 0x02, CP_CURRENT_6UA, LPF_RESISTORS_13KOHM },
 264         { 179, 0x12, CP_CURRENT_6UA, LPF_RESISTORS_13KOHM },
 265         { 199, 0x22, CP_CURRENT_6UA, LPF_RESISTORS_13KOHM },
 266         { 219, 0x03, CP_CURRENT_4_5UA, LPF_RESISTORS_13KOHM },
 267         { 239, 0x13, CP_CURRENT_4_5UA, LPF_RESISTORS_13KOHM },
 268         { 249, 0x23, CP_CURRENT_4_5UA, LPF_RESISTORS_13KOHM },
 269         { 269, 0x04, CP_CURRENT_6UA, LPF_RESISTORS_11_5KOHM },
 270         { 299, 0x14, CP_CURRENT_6UA, LPF_RESISTORS_11_5KOHM },
 271         { 329, 0x05, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM },
 272         { 359, 0x15, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM },
 273         { 399, 0x25, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM },
 274         { 449, 0x06, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM },
 275         { 499, 0x16, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM },
 276         { 549, 0x07, CP_CURRENT_7_5UA, LPF_RESISTORS_10_5KOHM },
 277         { 599, 0x17, CP_CURRENT_7_5UA, LPF_RESISTORS_10_5KOHM },
 278         { 649, 0x08, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM },
 279         { 699, 0x18, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM },
 280         { 749, 0x09, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM },
 281         { 799, 0x19, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM },
 282         { 849, 0x29, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM },
 283         { 899, 0x39, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM },
 284         { 949, 0x0a, CP_CURRENT_12UA, LPF_RESISTORS_8KOHM },
 285         { 999, 0x1a, CP_CURRENT_12UA, LPF_RESISTORS_8KOHM },
 286         {1049, 0x2a, CP_CURRENT_12UA, LPF_RESISTORS_8KOHM },
 287         {1099, 0x3a, CP_CURRENT_12UA, LPF_RESISTORS_8KOHM },
 288         {1149, 0x0b, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM },
 289         {1199, 0x1b, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM },
 290         {1249, 0x2b, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM },
 291         {1299, 0x3b, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM },
 292         {1349, 0x0c, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM },
 293         {1399, 0x1c, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM },
 294         {1449, 0x2c, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM },
 295         {1500, 0x3c, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM }
 296 };
 297
 298 static int max_mbps_to_parameter(unsigned int max_mbps)
 299 {
 300         int i;
 301
 302         for (i = 0; i < ARRAY_SIZE(dppa_map); i++)
 303                 if (dppa_map[i].max_mbps >= max_mbps)
 304                         return i;
 305
 306         return -EINVAL;
 307 }
 308
 309 static inline void dsi_write(struct dw_mipi_dsi_rockchip *dsi, u32 reg, u32 val)
 310 {
 311         writel(val, dsi->base + reg);
 312 }
 313
 314 static inline u32 dsi_read(struct dw_mipi_dsi_rockchip *dsi, u32 reg)
 315 {
 316         return readl(dsi->base + reg);
 317 }
 318
 319 static inline void dsi_update_bits(struct dw_mipi_dsi_rockchip *dsi, u32 reg,
 320                                    u32 mask, u32 val)
 321 {
 322         dsi_write(dsi, reg, (dsi_read(dsi, reg) & ~mask) | val);
 323 }
 324
 325 static void dw_mipi_dsi_phy_write(struct dw_mipi_dsi_rockchip *dsi,
 326                                   u8 test_code,
 327                                   u8 test_data)
 328 {
 329         /*
 330          * With the falling edge on TESTCLK, the TESTDIN[7:0] signal content
 331          * is latched internally as the current test code. Test data is
 332          * programmed internally by rising edge on TESTCLK.
 333          */
 334         dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR);
 335
 336         dsi_write(dsi, DSI_PHY_TST_CTRL1, PHY_TESTEN | PHY_TESTDOUT(0) |
 337                                           PHY_TESTDIN(test_code));
 338
 339         dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLK | PHY_UNTESTCLR);
 340
 341         dsi_write(dsi, DSI_PHY_TST_CTRL1, PHY_UNTESTEN | PHY_TESTDOUT(0) |
 342                                           PHY_TESTDIN(test_data));
 343
 344         dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR);
 345 }
 346
 347 /*
 348  * ns2bc - Nanoseconds to byte clock cycles
 349  */
 350 static inline unsigned int ns2bc(struct dw_mipi_dsi_rockchip *dsi, int ns)
 351 {
 352         return DIV_ROUND_UP(ns * dsi->lane_mbps / 8, 1000);
 353 }
 354
 355 /*
 356  * ns2ui - Nanoseconds to UI time periods
 357  */
 358 static inline unsigned int ns2ui(struct dw_mipi_dsi_rockchip *dsi, int ns)
 359 {
 360         return DIV_ROUND_UP(ns * dsi->lane_mbps, 1000);
 361 }
 362
 363 static int dw_mipi_dsi_phy_init(void *priv_data)
 364 {
 365         struct dw_mipi_dsi_rockchip *dsi = priv_data;
 366         int ret, i, vco;
 367
 368         if (dsi->phy)
 369                 return 0;
 370
 371         /*
 372          * Get vco from frequency(lane_mbps)
 373          * vco  frequency table
 374          * 000 - between   80 and  200 MHz
 375          * 001 - between  200 and  300 MHz
 376          * 010 - between  300 and  500 MHz
 377          * 011 - between  500 and  700 MHz
 378          * 100 - between  700 and  900 MHz
 379          * 101 - between  900 and 1100 MHz
 380          * 110 - between 1100 and 1300 MHz
 381          * 111 - between 1300 and 1500 MHz
 382          */
 383         vco = (dsi->lane_mbps < 200) ? 0 : (dsi->lane_mbps + 100) / 200;
 384
 385         i = max_mbps_to_parameter(dsi->lane_mbps);
 386         if (i < 0) {
 387                 DRM_DEV_ERROR(dsi->dev,
 388                               "failed to get parameter for %dmbps clock\n",
 389                               dsi->lane_mbps);
 390                 return i;
 391         }
 392
 393         ret = clk_prepare_enable(dsi->phy_cfg_clk);
 394         if (ret) {
 395                 DRM_DEV_ERROR(dsi->dev, "Failed to enable phy_cfg_clk\n");
 396                 return ret;
 397         }
 398
 399         dw_mipi_dsi_phy_write(dsi, PLL_BIAS_CUR_SEL_CAP_VCO_CONTROL,
 400                               BYPASS_VCO_RANGE |
 401                               VCO_RANGE_CON_SEL(vco) |
 402                               VCO_IN_CAP_CON_LOW |
 403                               REF_BIAS_CUR_SEL);
 404
 405         dw_mipi_dsi_phy_write(dsi, PLL_CP_CONTROL_PLL_LOCK_BYPASS,
 406                               CP_CURRENT_SEL(dppa_map[i].icpctrl));
 407         dw_mipi_dsi_phy_write(dsi, PLL_LPF_AND_CP_CONTROL,
 408                               CP_PROGRAM_EN | LPF_PROGRAM_EN |
 409                               LPF_RESISTORS_SEL(dppa_map[i].lpfctrl));
 410
 411         dw_mipi_dsi_phy_write(dsi, HS_RX_CONTROL_OF_LANE_0,
 412                               HSFREQRANGE_SEL(dppa_map[i].hsfreqrange));
 413
 414         dw_mipi_dsi_phy_write(dsi, PLL_INPUT_DIVIDER_RATIO,
 415                               INPUT_DIVIDER(dsi->input_div));
 416         dw_mipi_dsi_phy_write(dsi, PLL_LOOP_DIVIDER_RATIO,
 417                               LOOP_DIV_LOW_SEL(dsi->feedback_div) |
 418                               LOW_PROGRAM_EN);
 419         /*
 420          * We need set PLL_INPUT_AND_LOOP_DIVIDER_RATIOS_CONTROL immediately
 421          * to make the configured LSB effective according to IP simulation
 422          * and lab test results.
 423          * Only in this way can we get correct mipi phy pll frequency.
 424          */
 425         dw_mipi_dsi_phy_write(dsi, PLL_INPUT_AND_LOOP_DIVIDER_RATIOS_CONTROL,
 426                               PLL_LOOP_DIV_EN | PLL_INPUT_DIV_EN);
 427         dw_mipi_dsi_phy_write(dsi, PLL_LOOP_DIVIDER_RATIO,
 428                               LOOP_DIV_HIGH_SEL(dsi->feedback_div) |
 429                               HIGH_PROGRAM_EN);
 430         dw_mipi_dsi_phy_write(dsi, PLL_INPUT_AND_LOOP_DIVIDER_RATIOS_CONTROL,
 431                               PLL_LOOP_DIV_EN | PLL_INPUT_DIV_EN);
 432
 433         dw_mipi_dsi_phy_write(dsi, AFE_BIAS_BANDGAP_ANALOG_PROGRAMMABILITY,
 434                               LOW_PROGRAM_EN | BIASEXTR_SEL(BIASEXTR_127_7));
 435         dw_mipi_dsi_phy_write(dsi, AFE_BIAS_BANDGAP_ANALOG_PROGRAMMABILITY,
 436                               HIGH_PROGRAM_EN | BANDGAP_SEL(BANDGAP_96_10));
 437
 438         dw_mipi_dsi_phy_write(dsi, BANDGAP_AND_BIAS_CONTROL,
 439                               POWER_CONTROL | INTERNAL_REG_CURRENT |
 440                               BIAS_BLOCK_ON | BANDGAP_ON);
 441
 442         dw_mipi_dsi_phy_write(dsi, TERMINATION_RESISTER_CONTROL,
 443                               TER_RESISTOR_LOW | TER_CAL_DONE |
 444                               SETRD_MAX | TER_RESISTORS_ON);
 445         dw_mipi_dsi_phy_write(dsi, TERMINATION_RESISTER_CONTROL,
 446                               TER_RESISTOR_HIGH | LEVEL_SHIFTERS_ON |
 447                               SETRD_MAX | POWER_MANAGE |
 448                               TER_RESISTORS_ON);
 449
 450         dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_REQUEST_STATE_TIME_CONTROL,
 451                               TLP_PROGRAM_EN | ns2bc(dsi, 500));
 452         dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_PREPARE_STATE_TIME_CONTROL,
 453                               THS_PRE_PROGRAM_EN | ns2ui(dsi, 40));
 454         dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_HS_ZERO_STATE_TIME_CONTROL,
 455                               THS_ZERO_PROGRAM_EN | ns2bc(dsi, 300));
 456         dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_TRAIL_STATE_TIME_CONTROL,
 457                               THS_PRE_PROGRAM_EN | ns2ui(dsi, 100));
 458         dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_EXIT_STATE_TIME_CONTROL,
 459                               BIT(5) | ns2bc(dsi, 100));
 460         dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_POST_TIME_CONTROL,
 461                               BIT(5) | (ns2bc(dsi, 60) + 7));
 462
 463         dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_REQUEST_STATE_TIME_CONTROL,
 464                               TLP_PROGRAM_EN | ns2bc(dsi, 500));
 465         dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_PREPARE_STATE_TIME_CONTROL,
 466                               THS_PRE_PROGRAM_EN | (ns2ui(dsi, 50) + 20));
 467         dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_HS_ZERO_STATE_TIME_CONTROL,
 468                               THS_ZERO_PROGRAM_EN | (ns2bc(dsi, 140) + 2));
 469         dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_TRAIL_STATE_TIME_CONTROL,
 470                               THS_PRE_PROGRAM_EN | (ns2ui(dsi, 60) + 8));
 471         dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_EXIT_STATE_TIME_CONTROL,
 472                               BIT(5) | ns2bc(dsi, 100));
 473
 474         clk_disable_unprepare(dsi->phy_cfg_clk);
 475
 476         return ret;
 477 }
 478
 479 static void dw_mipi_dsi_phy_power_on(void *priv_data)
 480 {
 481         struct dw_mipi_dsi_rockchip *dsi = priv_data;
 482         int ret;
 483
 484         ret = phy_set_mode(dsi->phy, PHY_MODE_MIPI_DPHY);
 485         if (ret) {
 486                 DRM_DEV_ERROR(dsi->dev, "failed to set phy mode: %d\n", ret);
 487                 return;
 488         }
 489
 490         phy_configure(dsi->phy, &dsi->phy_opts);
 491         phy_power_on(dsi->phy);
 492 }
 493
 494 static void dw_mipi_dsi_phy_power_off(void *priv_data)
 495 {
 496         struct dw_mipi_dsi_rockchip *dsi = priv_data;
 497
 498         phy_power_off(dsi->phy);
 499 }
 500
 501 static int
 502 dw_mipi_dsi_get_lane_mbps(void *priv_data, const struct drm_display_mode *mode,
 503                           unsigned long mode_flags, u32 lanes, u32 format,
 504                           unsigned int *lane_mbps)
 505 {
 506         struct dw_mipi_dsi_rockchip *dsi = priv_data;
 507         int bpp;
 508         unsigned long mpclk, tmp;
 509         unsigned int target_mbps = 1000;
 510         unsigned int max_mbps = dppa_map[ARRAY_SIZE(dppa_map) - 1].max_mbps;
 511         unsigned long best_freq = 0;
 512         unsigned long fvco_min, fvco_max, fin, fout;
 513         unsigned int min_prediv, max_prediv;
 514         unsigned int _prediv, best_prediv;
 515         unsigned long _fbdiv, best_fbdiv;
 516         unsigned long min_delta = ULONG_MAX;
 517
 518         dsi->format = format;
 519         bpp = mipi_dsi_pixel_format_to_bpp(dsi->format);
 520         if (bpp < 0) {
 521                 DRM_DEV_ERROR(dsi->dev,
 522                               "failed to get bpp for pixel format %d\n",
 523                               dsi->format);
 524                 return bpp;
 525         }
 526
 527         mpclk = DIV_ROUND_UP(mode->clock, MSEC_PER_SEC);
 528         if (mpclk) {
 529                 /* take 1 / 0.8, since mbps must big than bandwidth of RGB */
 530                 tmp = mpclk * (bpp / lanes) * 10 / 8;
 531                 if (tmp < max_mbps)
 532                         target_mbps = tmp;
 533                 else
 534                         DRM_DEV_ERROR(dsi->dev,
 535                                       "DPHY clock frequency is out of range\n");
 536         }
 537
 538         /* for external phy only a the mipi_dphy_config is necessary */
 539         if (dsi->phy) {
 540                 phy_mipi_dphy_get_default_config(mode->clock * 1000 * 10 / 8,
 541                                                  bpp, lanes,
 542                                                  &dsi->phy_opts.mipi_dphy);
 543                 dsi->lane_mbps = target_mbps;
 544                 *lane_mbps = dsi->lane_mbps;
 545
 546                 return 0;
 547         }
 548
 549         fin = clk_get_rate(dsi->pllref_clk);
 550         fout = target_mbps * USEC_PER_SEC;
 551
 552         /* constraint: 5Mhz <= Fref / N <= 40MHz */
 553         min_prediv = DIV_ROUND_UP(fin, 40 * USEC_PER_SEC);
 554         max_prediv = fin / (5 * USEC_PER_SEC);
 555
 556         /* constraint: 80MHz <= Fvco <= 1500Mhz */
 557         fvco_min = 80 * USEC_PER_SEC;
 558         fvco_max = 1500 * USEC_PER_SEC;
 559
 560         for (_prediv = min_prediv; _prediv <= max_prediv; _prediv++) {
 561                 u64 tmp;
 562                 u32 delta;
 563                 /* Fvco = Fref * M / N */
 564                 tmp = (u64)fout * _prediv;
 565                 do_div(tmp, fin);
 566                 _fbdiv = tmp;
 567                 /*
 568                  * Due to the use of a "by 2 pre-scaler," the range of the
 569                  * feedback multiplication value M is limited to even division
 570                  * numbers, and m must be greater than 6, not bigger than 512.
 571                  */
 572                 if (_fbdiv < 6 || _fbdiv > 512)
 573                         continue;
 574
 575                 _fbdiv += _fbdiv % 2;
 576
 577                 tmp = (u64)_fbdiv * fin;
 578                 do_div(tmp, _prediv);
 579                 if (tmp < fvco_min || tmp > fvco_max)
 580                         continue;
 581
 582                 delta = abs(fout - tmp);
 583                 if (delta < min_delta) {
 584                         best_prediv = _prediv;
 585                         best_fbdiv = _fbdiv;
 586                         min_delta = delta;
 587                         best_freq = tmp;
 588                 }
 589         }
 590
 591         if (best_freq) {
 592                 dsi->lane_mbps = DIV_ROUND_UP(best_freq, USEC_PER_SEC);
 593                 *lane_mbps = dsi->lane_mbps;
 594                 dsi->input_div = best_prediv;
 595                 dsi->feedback_div = best_fbdiv;
 596         } else {
 597                 DRM_DEV_ERROR(dsi->dev, "Can not find best_freq for DPHY\n");
 598                 return -EINVAL;
 599         }
 600
 601         return 0;
 602 }
 603
 604 struct hstt {
 605         unsigned int maxfreq;
 606         struct dw_mipi_dsi_dphy_timing timing;
 607 };
 608
 609 #define HSTT(_maxfreq, _c_lp2hs, _c_hs2lp, _d_lp2hs, _d_hs2lp)  \
 610 {                                       \
 611         .maxfreq = _maxfreq,            \
 612         .timing = {                     \
 613                 .clk_lp2hs = _c_lp2hs,  \
 614                 .clk_hs2lp = _c_hs2lp,  \
 615                 .data_lp2hs = _d_lp2hs, \
 616                 .data_hs2lp = _d_hs2lp, \
 617         }                               \
 618 }
 619
 620 /* Table A-3 High-Speed Transition Times */
 621 struct hstt hstt_table[] = {
 622         HSTT(  90,  32, 20,  26, 13),
 623         HSTT( 100,  35, 23,  28, 14),
 624         HSTT( 110,  32, 22,  26, 13),
 625         HSTT( 130,  31, 20,  27, 13),
 626         HSTT( 140,  33, 22,  26, 14),
 627         HSTT( 150,  33, 21,  26, 14),
 628         HSTT( 170,  32, 20,  27, 13),
 629         HSTT( 180,  36, 23,  30, 15),
 630         HSTT( 200,  40, 22,  33, 15),
 631         HSTT( 220,  40, 22,  33, 15),
 632         HSTT( 240,  44, 24,  36, 16),
 633         HSTT( 250,  48, 24,  38, 17),
 634         HSTT( 270,  48, 24,  38, 17),
 635         HSTT( 300,  50, 27,  41, 18),
 636         HSTT( 330,  56, 28,  45, 18),
 637         HSTT( 360,  59, 28,  48, 19),
 638         HSTT( 400,  61, 30,  50, 20),
 639         HSTT( 450,  67, 31,  55, 21),
 640         HSTT( 500,  73, 31,  59, 22),
 641         HSTT( 550,  79, 36,  63, 24),
 642         HSTT( 600,  83, 37,  68, 25),
 643         HSTT( 650,  90, 38,  73, 27),
 644         HSTT( 700,  95, 40,  77, 28),
 645         HSTT( 750, 102, 40,  84, 28),
 646         HSTT( 800, 106, 42,  87, 30),
 647         HSTT( 850, 113, 44,  93, 31),
 648         HSTT( 900, 118, 47,  98, 32),
 649         HSTT( 950, 124, 47, 102, 34),
 650         HSTT(1000, 130, 49, 107, 35),
 651         HSTT(1050, 135, 51, 111, 37),
 652         HSTT(1100, 139, 51, 114, 38),
 653         HSTT(1150, 146, 54, 120, 40),
 654         HSTT(1200, 153, 57, 125, 41),
 655         HSTT(1250, 158, 58, 130, 42),
 656         HSTT(1300, 163, 58, 135, 44),
 657         HSTT(1350, 168, 60, 140, 45),
 658         HSTT(1400, 172, 64, 144, 47),
 659         HSTT(1450, 176, 65, 148, 48),
 660         HSTT(1500, 181, 66, 153, 50)
 661 };
 662
 663 static int
 664 dw_mipi_dsi_phy_get_timing(void *priv_data, unsigned int lane_mbps,
 665                            struct dw_mipi_dsi_dphy_timing *timing)
 666 {
 667         int i;
 668
 669         for (i = 0; i < ARRAY_SIZE(hstt_table); i++)
 670                 if (lane_mbps < hstt_table[i].maxfreq)
 671                         break;
 672
 673         if (i == ARRAY_SIZE(hstt_table))
 674                 i--;
 675
 676         *timing = hstt_table[i].timing;
 677
 678         return 0;
 679 }
 680
 681 static const struct dw_mipi_dsi_phy_ops dw_mipi_dsi_rockchip_phy_ops = {
 682         .init = dw_mipi_dsi_phy_init,
 683         .power_on = dw_mipi_dsi_phy_power_on,
 684         .power_off = dw_mipi_dsi_phy_power_off,
 685         .get_lane_mbps = dw_mipi_dsi_get_lane_mbps,
 686         .get_timing = dw_mipi_dsi_phy_get_timing,
 687 };
 688
 689 static void dw_mipi_dsi_rockchip_config(struct dw_mipi_dsi_rockchip *dsi)
 690 {
 691         if (dsi->cdata->lanecfg1_grf_reg)
 692                 regmap_write(dsi->grf_regmap, dsi->cdata->lanecfg1_grf_reg,
 693                                               dsi->cdata->lanecfg1);
 694
 695         if (dsi->cdata->lanecfg2_grf_reg)
 696                 regmap_write(dsi->grf_regmap, dsi->cdata->lanecfg2_grf_reg,
 697                                               dsi->cdata->lanecfg2);
 698
 699         if (dsi->cdata->enable_grf_reg)
 700                 regmap_write(dsi->grf_regmap, dsi->cdata->enable_grf_reg,
 701                                               dsi->cdata->enable);
 702 }
 703
 704 static void dw_mipi_dsi_rockchip_set_lcdsel(struct dw_mipi_dsi_rockchip *dsi,
 705                                             int mux)
 706 {
 707         regmap_write(dsi->grf_regmap, dsi->cdata->lcdsel_grf_reg,
 708                 mux ? dsi->cdata->lcdsel_lit : dsi->cdata->lcdsel_big);
 709 }
 710
 711 static int
 712 dw_mipi_dsi_encoder_atomic_check(struct drm_encoder *encoder,
 713                                  struct drm_crtc_state *crtc_state,
 714                                  struct drm_connector_state *conn_state)
 715 {
 716         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
 717         struct dw_mipi_dsi_rockchip *dsi = to_dsi(encoder);
 718
 719         switch (dsi->format) {
 720         case MIPI_DSI_FMT_RGB888:
 721                 s->output_mode = ROCKCHIP_OUT_MODE_P888;
 722                 break;
 723         case MIPI_DSI_FMT_RGB666:
 724                 s->output_mode = ROCKCHIP_OUT_MODE_P666;
 725                 break;
 726         case MIPI_DSI_FMT_RGB565:
 727                 s->output_mode = ROCKCHIP_OUT_MODE_P565;
 728                 break;
 729         default:
 730                 WARN_ON(1);
 731                 return -EINVAL;
 732         }
 733
 734         s->output_type = DRM_MODE_CONNECTOR_DSI;
 735         if (dsi->slave)
 736                 s->output_flags = ROCKCHIP_OUTPUT_DSI_DUAL;
 737
 738         return 0;
 739 }
 740
 741 static void dw_mipi_dsi_encoder_enable(struct drm_encoder *encoder)
 742 {
 743         struct dw_mipi_dsi_rockchip *dsi = to_dsi(encoder);
 744         int ret, mux;
 745
 746         mux = drm_of_encoder_active_endpoint_id(dsi->dev->of_node,
 747                                                 &dsi->encoder);
 748         if (mux < 0)
 749                 return;
 750
 751         pm_runtime_get_sync(dsi->dev);
 752         if (dsi->slave)
 753                 pm_runtime_get_sync(dsi->slave->dev);
 754
 755         /*
 756          * For the RK3399, the clk of grf must be enabled before writing grf
 757          * register. And for RK3288 or other soc, this grf_clk must be NULL,
 758          * the clk_prepare_enable return true directly.
 759          */
 760         ret = clk_prepare_enable(dsi->grf_clk);
 761         if (ret) {
 762                 DRM_DEV_ERROR(dsi->dev, "Failed to enable grf_clk: %d\n", ret);
 763                 return;
 764         }
 765
 766         dw_mipi_dsi_rockchip_set_lcdsel(dsi, mux);
 767         if (dsi->slave)
 768                 dw_mipi_dsi_rockchip_set_lcdsel(dsi->slave, mux);
 769
 770         clk_disable_unprepare(dsi->grf_clk);
 771 }
 772
 773 static void dw_mipi_dsi_encoder_disable(struct drm_encoder *encoder)
 774 {
 775         struct dw_mipi_dsi_rockchip *dsi = to_dsi(encoder);
 776
 777         if (dsi->slave)
 778                 pm_runtime_put(dsi->slave->dev);
 779         pm_runtime_put(dsi->dev);
 780 }
 781
 782 static const struct drm_encoder_helper_funcs
 783 dw_mipi_dsi_encoder_helper_funcs = {
 784         .atomic_check = dw_mipi_dsi_encoder_atomic_check,
 785         .enable = dw_mipi_dsi_encoder_enable,
 786         .disable = dw_mipi_dsi_encoder_disable,
 787 };
 788
 789 static int rockchip_dsi_drm_create_encoder(struct dw_mipi_dsi_rockchip *dsi,
 790                                            struct drm_device *drm_dev)
 791 {
 792         struct drm_encoder *encoder = &dsi->encoder;
 793         int ret;
 794
 795         encoder->possible_crtcs = drm_of_find_possible_crtcs(drm_dev,
 796                                                              dsi->dev->of_node);
 797
 798         ret = drm_simple_encoder_init(drm_dev, encoder, DRM_MODE_ENCODER_DSI);
 799         if (ret) {
 800                 DRM_ERROR("Failed to initialize encoder with drm\n");
 801                 return ret;
 802         }
 803
 804         drm_encoder_helper_add(encoder, &dw_mipi_dsi_encoder_helper_funcs);
 805
 806         return 0;
 807 }
 808
 809 static struct device
 810 *dw_mipi_dsi_rockchip_find_second(struct dw_mipi_dsi_rockchip *dsi)
 811 {
 812         const struct of_device_id *match;
 813         struct device_node *node = NULL, *local;
 814
 815         match = of_match_device(dsi->dev->driver->of_match_table, dsi->dev);
 816
 817         local = of_graph_get_remote_node(dsi->dev->of_node, 1, 0);
 818         if (!local)
 819                 return NULL;
 820
 821         while ((node = of_find_compatible_node(node, NULL,
 822                                                match->compatible))) {
 823                 struct device_node *remote;
 824
 825                 /* found ourself */
 826                 if (node == dsi->dev->of_node)
 827                         continue;
 828
 829                 remote = of_graph_get_remote_node(node, 1, 0);
 830                 if (!remote)
 831                         continue;
 832
 833                 /* same display device in port1-ep0 for both */
 834                 if (remote == local) {
 835                         struct dw_mipi_dsi_rockchip *dsi2;
 836                         struct platform_device *pdev;
 837
 838                         pdev = of_find_device_by_node(node);
 839
 840                         /*
 841                          * we have found the second, so will either return it
 842                          * or return with an error. In any case won't need the
 843                          * nodes anymore nor continue the loop.
 844                          */
 845                         of_node_put(remote);
 846                         of_node_put(node);
 847                         of_node_put(local);
 848
 849                         if (!pdev)
 850                                 return ERR_PTR(-EPROBE_DEFER);
 851
 852                         dsi2 = platform_get_drvdata(pdev);
 853                         if (!dsi2) {
 854                                 platform_device_put(pdev);
 855                                 return ERR_PTR(-EPROBE_DEFER);
 856                         }
 857
 858                         return &pdev->dev;
 859                 }
 860
 861                 of_node_put(remote);
 862         }
 863
 864         of_node_put(local);
 865
 866         return NULL;
 867 }
 868
 869 static int dw_mipi_dsi_rockchip_bind(struct device *dev,
 870                                      struct device *master,
 871                                      void *data)
 872 {
 873         struct dw_mipi_dsi_rockchip *dsi = dev_get_drvdata(dev);
 874         struct drm_device *drm_dev = data;
 875         struct device *second;
 876         bool master1, master2;
 877         int ret;
 878
 879         second = dw_mipi_dsi_rockchip_find_second(dsi);
 880         if (IS_ERR(second))
 881                 return PTR_ERR(second);
 882
 883         if (second) {
 884                 master1 = of_property_read_bool(dsi->dev->of_node,
 885                                                 "clock-master");
 886                 master2 = of_property_read_bool(second->of_node,
 887                                                 "clock-master");
 888
 889                 if (master1 && master2) {
 890                         DRM_DEV_ERROR(dsi->dev, "only one clock-master allowed\n");
 891                         return -EINVAL;
 892                 }
 893
 894                 if (!master1 && !master2) {
 895                         DRM_DEV_ERROR(dsi->dev, "no clock-master defined\n");
 896                         return -EINVAL;
 897                 }
 898
 899                 /* we are the slave in dual-DSI */
 900                 if (!master1) {
 901                         dsi->is_slave = true;
 902                         return 0;
 903                 }
 904
 905                 dsi->slave = dev_get_drvdata(second);
 906                 if (!dsi->slave) {
 907                         DRM_DEV_ERROR(dev, "could not get slaves data\n");
 908                         return -ENODEV;
 909                 }
 910
 911                 dsi->slave->is_slave = true;
 912                 dw_mipi_dsi_set_slave(dsi->dmd, dsi->slave->dmd);
 913                 put_device(second);
 914         }
 915
 916         ret = clk_prepare_enable(dsi->pllref_clk);
 917         if (ret) {
 918                 DRM_DEV_ERROR(dev, "Failed to enable pllref_clk: %d\n", ret);
 919                 return ret;
 920         }
 921
 922         /*
 923          * With the GRF clock running, write lane and dual-mode configurations
 924          * that won't change immediately. If we waited until enable() to do
 925          * this, things like panel preparation would not be able to send
 926          * commands over DSI.
 927          */
 928         ret = clk_prepare_enable(dsi->grf_clk);
 929         if (ret) {
 930                 DRM_DEV_ERROR(dsi->dev, "Failed to enable grf_clk: %d\n", ret);
 931                 return ret;
 932         }
 933
 934         dw_mipi_dsi_rockchip_config(dsi);
 935         if (dsi->slave)
 936                 dw_mipi_dsi_rockchip_config(dsi->slave);
 937
 938         clk_disable_unprepare(dsi->grf_clk);
 939
 940         ret = rockchip_dsi_drm_create_encoder(dsi, drm_dev);
 941         if (ret) {
 942                 DRM_DEV_ERROR(dev, "Failed to create drm encoder\n");
 943                 return ret;
 944         }
 945
 946         ret = dw_mipi_dsi_bind(dsi->dmd, &dsi->encoder);
 947         if (ret) {
 948                 DRM_DEV_ERROR(dev, "Failed to bind: %d\n", ret);
 949                 return ret;
 950         }
 951
 952         return 0;
 953 }
 954
 955 static void dw_mipi_dsi_rockchip_unbind(struct device *dev,
 956                                         struct device *master,
 957                                         void *data)
 958 {
 959         struct dw_mipi_dsi_rockchip *dsi = dev_get_drvdata(dev);
 960
 961         if (dsi->is_slave)
 962                 return;
 963
 964         dw_mipi_dsi_unbind(dsi->dmd);
 965
 966         clk_disable_unprepare(dsi->pllref_clk);
 967 }
 968
 969 static const struct component_ops dw_mipi_dsi_rockchip_ops = {
 970         .bind   = dw_mipi_dsi_rockchip_bind,
 971         .unbind = dw_mipi_dsi_rockchip_unbind,
 972 };
 973
 974 static int dw_mipi_dsi_rockchip_host_attach(void *priv_data,
 975                                             struct mipi_dsi_device *device)
 976 {
 977         struct dw_mipi_dsi_rockchip *dsi = priv_data;
 978         struct device *second;
 979         int ret;
 980
 981         ret = component_add(dsi->dev, &dw_mipi_dsi_rockchip_ops);
 982         if (ret) {
 983                 DRM_DEV_ERROR(dsi->dev, "Failed to register component: %d\n",
 984                                         ret);
 985                 return ret;
 986         }
 987
 988         second = dw_mipi_dsi_rockchip_find_second(dsi);
 989         if (IS_ERR(second))
 990                 return PTR_ERR(second);
 991         if (second) {
 992                 ret = component_add(second, &dw_mipi_dsi_rockchip_ops);
 993                 if (ret) {
 994                         DRM_DEV_ERROR(second,
 995                                       "Failed to register component: %d\n",
 996                                       ret);
 997                         return ret;
 998                 }
 999         }
1000
1001         return 0;
1002 }
1003
1004 static int dw_mipi_dsi_rockchip_host_detach(void *priv_data,
1005                                             struct mipi_dsi_device *device)
1006 {
1007         struct dw_mipi_dsi_rockchip *dsi = priv_data;
1008         struct device *second;
1009
1010         second = dw_mipi_dsi_rockchip_find_second(dsi);
1011         if (second && !IS_ERR(second))
1012                 component_del(second, &dw_mipi_dsi_rockchip_ops);
1013
1014         component_del(dsi->dev, &dw_mipi_dsi_rockchip_ops);
1015
1016         return 0;
1017 }
1018
1019 static const struct dw_mipi_dsi_host_ops dw_mipi_dsi_rockchip_host_ops = {
1020         .attach = dw_mipi_dsi_rockchip_host_attach,
1021         .detach = dw_mipi_dsi_rockchip_host_detach,
1022 };
1023
1024 static int dw_mipi_dsi_rockchip_probe(struct platform_device *pdev)
1025 {
1026         struct device *dev = &pdev->dev;
1027         struct device_node *np = dev->of_node;
1028         struct dw_mipi_dsi_rockchip *dsi;
1029         struct resource *res;
1030         const struct rockchip_dw_dsi_chip_data *cdata =
1031                                 of_device_get_match_data(dev);
1032         int ret, i;
1033
1034         dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);
1035         if (!dsi)
1036                 return -ENOMEM;
1037
1038         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1039         dsi->base = devm_ioremap_resource(dev, res);
1040         if (IS_ERR(dsi->base)) {
1041                 DRM_DEV_ERROR(dev, "Unable to get dsi registers\n");
1042                 return PTR_ERR(dsi->base);
1043         }
1044
1045         i = 0;
1046         while (cdata[i].reg) {
1047                 if (cdata[i].reg == res->start) {
1048                         dsi->cdata = &cdata[i];
1049                         break;
1050                 }
1051
1052                 i++;
1053         }
1054
1055         if (!dsi->cdata) {
1056                 DRM_DEV_ERROR(dev, "no dsi-config for %s node\n", np->name);
1057                 return -EINVAL;
1058         }
1059
1060         /* try to get a possible external dphy */
1061         dsi->phy = devm_phy_optional_get(dev, "dphy");
1062         if (IS_ERR(dsi->phy)) {
1063                 ret = PTR_ERR(dsi->phy);
1064                 DRM_DEV_ERROR(dev, "failed to get mipi dphy: %d\n", ret);
1065                 return ret;
1066         }
1067
1068         dsi->pllref_clk = devm_clk_get(dev, "ref");
1069         if (IS_ERR(dsi->pllref_clk)) {
1070                 if (dsi->phy) {
1071                         /*
1072                          * if external phy is present, pll will be
1073                          * generated there.
1074                          */
1075                         dsi->pllref_clk = NULL;
1076                 } else {
1077                         ret = PTR_ERR(dsi->pllref_clk);
1078                         DRM_DEV_ERROR(dev,
1079                                       "Unable to get pll reference clock: %d\n",
1080                                       ret);
1081                         return ret;
1082                 }
1083         }
1084
1085         if (dsi->cdata->flags & DW_MIPI_NEEDS_PHY_CFG_CLK) {
1086                 dsi->phy_cfg_clk = devm_clk_get(dev, "phy_cfg");
1087                 if (IS_ERR(dsi->phy_cfg_clk)) {
1088                         ret = PTR_ERR(dsi->phy_cfg_clk);
1089                         DRM_DEV_ERROR(dev,
1090                                       "Unable to get phy_cfg_clk: %d\n", ret);
1091                         return ret;
1092                 }
1093         }
1094
1095         if (dsi->cdata->flags & DW_MIPI_NEEDS_GRF_CLK) {
1096                 dsi->grf_clk = devm_clk_get(dev, "grf");
1097                 if (IS_ERR(dsi->grf_clk)) {
1098                         ret = PTR_ERR(dsi->grf_clk);
1099                         DRM_DEV_ERROR(dev, "Unable to get grf_clk: %d\n", ret);
1100                         return ret;
1101                 }
1102         }
1103
1104         dsi->grf_regmap = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
1105         if (IS_ERR(dsi->grf_regmap)) {
1106                 DRM_DEV_ERROR(dev, "Unable to get rockchip,grf\n");
1107                 return PTR_ERR(dsi->grf_regmap);
1108         }
1109
1110         dsi->dev = dev;
1111         dsi->pdata.base = dsi->base;
1112         dsi->pdata.max_data_lanes = dsi->cdata->max_data_lanes;
1113         dsi->pdata.phy_ops = &dw_mipi_dsi_rockchip_phy_ops;
1114         dsi->pdata.host_ops = &dw_mipi_dsi_rockchip_host_ops;
1115         dsi->pdata.priv_data = dsi;
1116         platform_set_drvdata(pdev, dsi);
1117
1118         dsi->dmd = dw_mipi_dsi_probe(pdev, &dsi->pdata);
1119         if (IS_ERR(dsi->dmd)) {
1120                 ret = PTR_ERR(dsi->dmd);
1121                 if (ret != -EPROBE_DEFER)
1122                         DRM_DEV_ERROR(dev,
1123                                       "Failed to probe dw_mipi_dsi: %d\n", ret);
1124                 goto err_clkdisable;
1125         }
1126
1127         return 0;
1128
1129 err_clkdisable:
1130         clk_disable_unprepare(dsi->pllref_clk);
1131         return ret;
1132 }
1133
1134 static int dw_mipi_dsi_rockchip_remove(struct platform_device *pdev)
1135 {
1136         struct dw_mipi_dsi_rockchip *dsi = platform_get_drvdata(pdev);
1137
1138         dw_mipi_dsi_remove(dsi->dmd);
1139
1140         return 0;
1141 }
1142
1143 static const struct rockchip_dw_dsi_chip_data px30_chip_data[] = {
1144         {
1145                 .reg = 0xff450000,
1146                 .lcdsel_grf_reg = PX30_GRF_PD_VO_CON1,
1147                 .lcdsel_big = HIWORD_UPDATE(0, PX30_DSI_LCDC_SEL),
1148                 .lcdsel_lit = HIWORD_UPDATE(PX30_DSI_LCDC_SEL,
1149                                             PX30_DSI_LCDC_SEL),
1150
1151                 .lanecfg1_grf_reg = PX30_GRF_PD_VO_CON1,
1152                 .lanecfg1 = HIWORD_UPDATE(0, PX30_DSI_TURNDISABLE |
1153                                              PX30_DSI_FORCERXMODE |
1154                                              PX30_DSI_FORCETXSTOPMODE),
1155
1156                 .max_data_lanes = 4,
1157         },
1158         { /* sentinel */ }
1159 };
1160
1161 static const struct rockchip_dw_dsi_chip_data rk3288_chip_data[] = {
1162         {
1163                 .reg = 0xff960000,
1164                 .lcdsel_grf_reg = RK3288_GRF_SOC_CON6,
1165                 .lcdsel_big = HIWORD_UPDATE(0, RK3288_DSI0_LCDC_SEL),
1166                 .lcdsel_lit = HIWORD_UPDATE(RK3288_DSI0_LCDC_SEL, RK3288_DSI0_LCDC_SEL),
1167
1168                 .max_data_lanes = 4,
1169         },
1170         {
1171                 .reg = 0xff964000,
1172                 .lcdsel_grf_reg = RK3288_GRF_SOC_CON6,
1173                 .lcdsel_big = HIWORD_UPDATE(0, RK3288_DSI1_LCDC_SEL),
1174                 .lcdsel_lit = HIWORD_UPDATE(RK3288_DSI1_LCDC_SEL, RK3288_DSI1_LCDC_SEL),
1175
1176                 .max_data_lanes = 4,
1177         },
1178         { /* sentinel */ }
1179 };
1180
1181 static const struct rockchip_dw_dsi_chip_data rk3399_chip_data[] = {
1182         {
1183                 .reg = 0xff960000,
1184                 .lcdsel_grf_reg = RK3399_GRF_SOC_CON20,
1185                 .lcdsel_big = HIWORD_UPDATE(0, RK3399_DSI0_LCDC_SEL),
1186                 .lcdsel_lit = HIWORD_UPDATE(RK3399_DSI0_LCDC_SEL,
1187                                             RK3399_DSI0_LCDC_SEL),
1188
1189                 .lanecfg1_grf_reg = RK3399_GRF_SOC_CON22,
1190                 .lanecfg1 = HIWORD_UPDATE(0, RK3399_DSI0_TURNREQUEST |
1191                                              RK3399_DSI0_TURNDISABLE |
1192                                              RK3399_DSI0_FORCETXSTOPMODE |
1193                                              RK3399_DSI0_FORCERXMODE),
1194
1195                 .flags = DW_MIPI_NEEDS_PHY_CFG_CLK | DW_MIPI_NEEDS_GRF_CLK,
1196                 .max_data_lanes = 4,
1197         },
1198         {
1199                 .reg = 0xff968000,
1200                 .lcdsel_grf_reg = RK3399_GRF_SOC_CON20,
1201                 .lcdsel_big = HIWORD_UPDATE(0, RK3399_DSI1_LCDC_SEL),
1202                 .lcdsel_lit = HIWORD_UPDATE(RK3399_DSI1_LCDC_SEL,
1203                                             RK3399_DSI1_LCDC_SEL),
1204
1205                 .lanecfg1_grf_reg = RK3399_GRF_SOC_CON23,
1206                 .lanecfg1 = HIWORD_UPDATE(0, RK3399_DSI1_TURNDISABLE |
1207                                              RK3399_DSI1_FORCETXSTOPMODE |
1208                                              RK3399_DSI1_FORCERXMODE |
1209                                              RK3399_DSI1_ENABLE),
1210
1211                 .lanecfg2_grf_reg = RK3399_GRF_SOC_CON24,
1212                 .lanecfg2 = HIWORD_UPDATE(RK3399_TXRX_MASTERSLAVEZ |
1213                                           RK3399_TXRX_ENABLECLK,
1214                                           RK3399_TXRX_MASTERSLAVEZ |
1215                                           RK3399_TXRX_ENABLECLK |
1216                                           RK3399_TXRX_BASEDIR),
1217
1218                 .enable_grf_reg = RK3399_GRF_SOC_CON23,
1219                 .enable = HIWORD_UPDATE(RK3399_DSI1_ENABLE, RK3399_DSI1_ENABLE),
1220
1221                 .flags = DW_MIPI_NEEDS_PHY_CFG_CLK | DW_MIPI_NEEDS_GRF_CLK,
1222                 .max_data_lanes = 4,
1223         },
1224         { /* sentinel */ }
1225 };
1226
1227 static const struct of_device_id dw_mipi_dsi_rockchip_dt_ids[] = {
1228         {
1229          .compatible = "rockchip,px30-mipi-dsi",
1230          .data = &px30_chip_data,
1231         }, {
1232          .compatible = "rockchip,rk3288-mipi-dsi",
1233          .data = &rk3288_chip_data,
1234         }, {
1235          .compatible = "rockchip,rk3399-mipi-dsi",
1236          .data = &rk3399_chip_data,
1237         },
1238         { /* sentinel */ }
1239 };
1240 MODULE_DEVICE_TABLE(of, dw_mipi_dsi_rockchip_dt_ids);
1241
1242 struct platform_driver dw_mipi_dsi_rockchip_driver = {
1243         .probe          = dw_mipi_dsi_rockchip_probe,
1244         .remove         = dw_mipi_dsi_rockchip_remove,
1245         .driver         = {
1246                 .of_match_table = dw_mipi_dsi_rockchip_dt_ids,
1247                 .name   = "dw-mipi-dsi-rockchip",
1248         },
1249 };