drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
   4  * Author:
   5  *      Chris Zhong <zyw@rock-chips.com>
   6  *      Nickey Yang <nickey.yang@rock-chips.com>
   7  */
   8
   9 #include <linux/clk.h>
  10 #include <linux/iopoll.h>
  11 #include <linux/math64.h>
  12 #include <linux/mfd/syscon.h>
  13 #include <linux/module.h>
  14 #include <linux/of_device.h>
  15 #include <linux/phy/phy.h>
  16 #include <linux/pm_runtime.h>
  17 #include <linux/phy/phy.h>
  18 #include <linux/regmap.h>
  19
  20 #include <video/mipi_display.h>
  21
  22 #include <drm/bridge/dw_mipi_dsi.h>
  23 #include <drm/drm_mipi_dsi.h>
  24 #include <drm/drm_of.h>
  25 #include <drm/drm_simple_kms_helper.h>
  26
  27 #include "rockchip_drm_drv.h"
  28 #include "rockchip_drm_vop.h"
  29
  30 #define DSI_PHY_RSTZ                    0xa0
  31 #define PHY_DISFORCEPLL                 0
  32 #define PHY_ENFORCEPLL                  BIT(3)
  33 #define PHY_DISABLECLK                  0
  34 #define PHY_ENABLECLK                   BIT(2)
  35 #define PHY_RSTZ                        0
  36 #define PHY_UNRSTZ                      BIT(1)
  37 #define PHY_SHUTDOWNZ                   0
  38 #define PHY_UNSHUTDOWNZ                 BIT(0)
  39
  40 #define DSI_PHY_IF_CFG                  0xa4
  41 #define N_LANES(n)                      ((((n) - 1) & 0x3) << 0)
  42 #define PHY_STOP_WAIT_TIME(cycle)       (((cycle) & 0xff) << 8)
  43
  44 #define DSI_PHY_STATUS                  0xb0
  45 #define LOCK                            BIT(0)
  46 #define STOP_STATE_CLK_LANE             BIT(2)
  47
  48 #define DSI_PHY_TST_CTRL0               0xb4
  49 #define PHY_TESTCLK                     BIT(1)
  50 #define PHY_UNTESTCLK                   0
  51 #define PHY_TESTCLR                     BIT(0)
  52 #define PHY_UNTESTCLR                   0
  53
  54 #define DSI_PHY_TST_CTRL1               0xb8
  55 #define PHY_TESTEN                      BIT(16)
  56 #define PHY_UNTESTEN                    0
  57 #define PHY_TESTDOUT(n)                 (((n) & 0xff) << 8)
  58 #define PHY_TESTDIN(n)                  (((n) & 0xff) << 0)
  59
  60 #define DSI_INT_ST0                     0xbc
  61 #define DSI_INT_ST1                     0xc0
  62 #define DSI_INT_MSK0                    0xc4
  63 #define DSI_INT_MSK1                    0xc8
  64
  65 #define PHY_STATUS_TIMEOUT_US           10000
  66 #define CMD_PKT_STATUS_TIMEOUT_US       20000
  67
  68 #define BYPASS_VCO_RANGE        BIT(7)
  69 #define VCO_RANGE_CON_SEL(val)  (((val) & 0x7) << 3)
  70 #define VCO_IN_CAP_CON_DEFAULT  (0x0 << 1)
  71 #define VCO_IN_CAP_CON_LOW      (0x1 << 1)
  72 #define VCO_IN_CAP_CON_HIGH     (0x2 << 1)
  73 #define REF_BIAS_CUR_SEL        BIT(0)
  74
  75 #define CP_CURRENT_3UA  0x1
  76 #define CP_CURRENT_4_5UA        0x2
  77 #define CP_CURRENT_7_5UA        0x6
  78 #define CP_CURRENT_6UA  0x9
  79 #define CP_CURRENT_12UA 0xb
  80 #define CP_CURRENT_SEL(val)     ((val) & 0xf)
  81 #define CP_PROGRAM_EN           BIT(7)
  82
  83 #define LPF_RESISTORS_15_5KOHM  0x1
  84 #define LPF_RESISTORS_13KOHM    0x2
  85 #define LPF_RESISTORS_11_5KOHM  0x4
  86 #define LPF_RESISTORS_10_5KOHM  0x8
  87 #define LPF_RESISTORS_8KOHM     0x10
  88 #define LPF_PROGRAM_EN          BIT(6)
  89 #define LPF_RESISTORS_SEL(val)  ((val) & 0x3f)
  90
  91 #define HSFREQRANGE_SEL(val)    (((val) & 0x3f) << 1)
  92
  93 #define INPUT_DIVIDER(val)      (((val) - 1) & 0x7f)
  94 #define LOW_PROGRAM_EN          0
  95 #define HIGH_PROGRAM_EN         BIT(7)
  96 #define LOOP_DIV_LOW_SEL(val)   (((val) - 1) & 0x1f)
  97 #define LOOP_DIV_HIGH_SEL(val)  ((((val) - 1) >> 5) & 0xf)
  98 #define PLL_LOOP_DIV_EN         BIT(5)
  99 #define PLL_INPUT_DIV_EN        BIT(4)
 100
 101 #define POWER_CONTROL           BIT(6)
 102 #define INTERNAL_REG_CURRENT    BIT(3)
 103 #define BIAS_BLOCK_ON           BIT(2)
 104 #define BANDGAP_ON              BIT(0)
 105
 106 #define TER_RESISTOR_HIGH       BIT(7)
 107 #define TER_RESISTOR_LOW        0
 108 #define LEVEL_SHIFTERS_ON       BIT(6)
 109 #define TER_CAL_DONE            BIT(5)
 110 #define SETRD_MAX               (0x7 << 2)
 111 #define POWER_MANAGE            BIT(1)
 112 #define TER_RESISTORS_ON        BIT(0)
 113
 114 #define BIASEXTR_SEL(val)       ((val) & 0x7)
 115 #define BANDGAP_SEL(val)        ((val) & 0x7)
 116 #define TLP_PROGRAM_EN          BIT(7)
 117 #define THS_PRE_PROGRAM_EN      BIT(7)
 118 #define THS_ZERO_PROGRAM_EN     BIT(6)
 119
 120 #define PLL_BIAS_CUR_SEL_CAP_VCO_CONTROL                0x10
 121 #define PLL_CP_CONTROL_PLL_LOCK_BYPASS                  0x11
 122 #define PLL_LPF_AND_CP_CONTROL                          0x12
 123 #define PLL_INPUT_DIVIDER_RATIO                         0x17
 124 #define PLL_LOOP_DIVIDER_RATIO                          0x18
 125 #define PLL_INPUT_AND_LOOP_DIVIDER_RATIOS_CONTROL       0x19
 126 #define BANDGAP_AND_BIAS_CONTROL                        0x20
 127 #define TERMINATION_RESISTER_CONTROL                    0x21
 128 #define AFE_BIAS_BANDGAP_ANALOG_PROGRAMMABILITY         0x22
 129 #define HS_RX_CONTROL_OF_LANE_CLK                       0x34
 130 #define HS_RX_CONTROL_OF_LANE_0                         0x44
 131 #define HS_RX_CONTROL_OF_LANE_1                         0x54
 132 #define HS_TX_CLOCK_LANE_REQUEST_STATE_TIME_CONTROL     0x60
 133 #define HS_TX_CLOCK_LANE_PREPARE_STATE_TIME_CONTROL     0x61
 134 #define HS_TX_CLOCK_LANE_HS_ZERO_STATE_TIME_CONTROL     0x62
 135 #define HS_TX_CLOCK_LANE_TRAIL_STATE_TIME_CONTROL       0x63
 136 #define HS_TX_CLOCK_LANE_EXIT_STATE_TIME_CONTROL        0x64
 137 #define HS_TX_CLOCK_LANE_POST_TIME_CONTROL              0x65
 138 #define HS_TX_DATA_LANE_REQUEST_STATE_TIME_CONTROL      0x70
 139 #define HS_TX_DATA_LANE_PREPARE_STATE_TIME_CONTROL      0x71
 140 #define HS_TX_DATA_LANE_HS_ZERO_STATE_TIME_CONTROL      0x72
 141 #define HS_TX_DATA_LANE_TRAIL_STATE_TIME_CONTROL        0x73
 142 #define HS_TX_DATA_LANE_EXIT_STATE_TIME_CONTROL         0x74
 143 #define HS_RX_DATA_LANE_THS_SETTLE_CONTROL              0x75
 144 #define HS_RX_CONTROL_OF_LANE_2                         0x84
 145 #define HS_RX_CONTROL_OF_LANE_3                         0x94
 146
 147 #define DW_MIPI_NEEDS_PHY_CFG_CLK       BIT(0)
 148 #define DW_MIPI_NEEDS_GRF_CLK           BIT(1)
 149
 150 #define PX30_GRF_PD_VO_CON1             0x0438
 151 #define PX30_DSI_FORCETXSTOPMODE        (0xf << 7)
 152 #define PX30_DSI_FORCERXMODE            BIT(6)
 153 #define PX30_DSI_TURNDISABLE            BIT(5)
 154 #define PX30_DSI_LCDC_SEL               BIT(0)
 155
 156 #define RK3288_GRF_SOC_CON6             0x025c
 157 #define RK3288_DSI0_LCDC_SEL            BIT(6)
 158 #define RK3288_DSI1_LCDC_SEL            BIT(9)
 159
 160 #define RK3399_GRF_SOC_CON20            0x6250
 161 #define RK3399_DSI0_LCDC_SEL            BIT(0)
 162 #define RK3399_DSI1_LCDC_SEL            BIT(4)
 163
 164 #define RK3399_GRF_SOC_CON22            0x6258
 165 #define RK3399_DSI0_TURNREQUEST         (0xf << 12)
 166 #define RK3399_DSI0_TURNDISABLE         (0xf << 8)
 167 #define RK3399_DSI0_FORCETXSTOPMODE     (0xf << 4)
 168 #define RK3399_DSI0_FORCERXMODE         (0xf << 0)
 169
 170 #define RK3399_GRF_SOC_CON23            0x625c
 171 #define RK3399_DSI1_TURNDISABLE         (0xf << 12)
 172 #define RK3399_DSI1_FORCETXSTOPMODE     (0xf << 8)
 173 #define RK3399_DSI1_FORCERXMODE         (0xf << 4)
 174 #define RK3399_DSI1_ENABLE              (0xf << 0)
 175
 176 #define RK3399_GRF_SOC_CON24            0x6260
 177 #define RK3399_TXRX_MASTERSLAVEZ        BIT(7)
 178 #define RK3399_TXRX_ENABLECLK           BIT(6)
 179 #define RK3399_TXRX_BASEDIR             BIT(5)
 180 #define RK3399_TXRX_SRC_SEL_ISP0        BIT(4)
 181 #define RK3399_TXRX_TURNREQUEST         GENMASK(3, 0)
 182
 183 #define HIWORD_UPDATE(val, mask)        (val | (mask) << 16)
 184
 185 #define to_dsi(nm)      container_of(nm, struct dw_mipi_dsi_rockchip, nm)
 186
 187 enum {
 188         DW_DSI_USAGE_IDLE,
 189         DW_DSI_USAGE_DSI,
 190         DW_DSI_USAGE_PHY,
 191 };
 192
 193 enum {
 194         BANDGAP_97_07,
 195         BANDGAP_98_05,
 196         BANDGAP_99_02,
 197         BANDGAP_100_00,
 198         BANDGAP_93_17,
 199         BANDGAP_94_15,
 200         BANDGAP_95_12,
 201         BANDGAP_96_10,
 202 };
 203
 204 enum {
 205         BIASEXTR_87_1,
 206         BIASEXTR_91_5,
 207         BIASEXTR_95_9,
 208         BIASEXTR_100,
 209         BIASEXTR_105_94,
 210         BIASEXTR_111_88,
 211         BIASEXTR_118_8,
 212         BIASEXTR_127_7,
 213 };
 214
 215 struct rockchip_dw_dsi_chip_data {
 216         u32 reg;
 217
 218         u32 lcdsel_grf_reg;
 219         u32 lcdsel_big;
 220         u32 lcdsel_lit;
 221
 222         u32 enable_grf_reg;
 223         u32 enable;
 224
 225         u32 lanecfg1_grf_reg;
 226         u32 lanecfg1;
 227         u32 lanecfg2_grf_reg;
 228         u32 lanecfg2;
 229
 230         int (*dphy_rx_init)(struct phy *phy);
 231         int (*dphy_rx_power_on)(struct phy *phy);
 232         int (*dphy_rx_power_off)(struct phy *phy);
 233
 234         unsigned int flags;
 235         unsigned int max_data_lanes;
 236 };
 237
 238 struct dw_mipi_dsi_rockchip {
 239         struct device *dev;
 240         struct drm_encoder encoder;
 241         void __iomem *base;
 242
 243         struct regmap *grf_regmap;
 244         struct clk *pclk;
 245         struct clk *pllref_clk;
 246         struct clk *grf_clk;
 247         struct clk *phy_cfg_clk;
 248
 249         /* dual-channel */
 250         bool is_slave;
 251         struct dw_mipi_dsi_rockchip *slave;
 252
 253         /* optional external dphy */
 254         struct phy *phy;
 255         union phy_configure_opts phy_opts;
 256
 257         /* being a phy for other mipi hosts */
 258         unsigned int usage_mode;
 259         struct mutex usage_mutex;
 260         struct phy *dphy;
 261         struct phy_configure_opts_mipi_dphy dphy_config;
 262
 263         unsigned int lane_mbps; /* per lane */
 264         u16 input_div;
 265         u16 feedback_div;
 266         u32 format;
 267
 268         struct dw_mipi_dsi *dmd;
 269         const struct rockchip_dw_dsi_chip_data *cdata;
 270         struct dw_mipi_dsi_plat_data pdata;
 271 };
 272
 273 struct dphy_pll_parameter_map {
 274         unsigned int max_mbps;
 275         u8 hsfreqrange;
 276         u8 icpctrl;
 277         u8 lpfctrl;
 278 };
 279
 280 /* The table is based on 27MHz DPHY pll reference clock. */
 281 static const struct dphy_pll_parameter_map dppa_map[] = {
 282         {  89, 0x00, CP_CURRENT_3UA, LPF_RESISTORS_13KOHM },
 283         {  99, 0x10, CP_CURRENT_3UA, LPF_RESISTORS_13KOHM },
 284         { 109, 0x20, CP_CURRENT_3UA, LPF_RESISTORS_13KOHM },
 285         { 129, 0x01, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM },
 286         { 139, 0x11, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM },
 287         { 149, 0x21, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM },
 288         { 169, 0x02, CP_CURRENT_6UA, LPF_RESISTORS_13KOHM },
 289         { 179, 0x12, CP_CURRENT_6UA, LPF_RESISTORS_13KOHM },
 290         { 199, 0x22, CP_CURRENT_6UA, LPF_RESISTORS_13KOHM },
 291         { 219, 0x03, CP_CURRENT_4_5UA, LPF_RESISTORS_13KOHM },
 292         { 239, 0x13, CP_CURRENT_4_5UA, LPF_RESISTORS_13KOHM },
 293         { 249, 0x23, CP_CURRENT_4_5UA, LPF_RESISTORS_13KOHM },
 294         { 269, 0x04, CP_CURRENT_6UA, LPF_RESISTORS_11_5KOHM },
 295         { 299, 0x14, CP_CURRENT_6UA, LPF_RESISTORS_11_5KOHM },
 296         { 329, 0x05, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM },
 297         { 359, 0x15, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM },
 298         { 399, 0x25, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM },
 299         { 449, 0x06, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM },
 300         { 499, 0x16, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM },
 301         { 549, 0x07, CP_CURRENT_7_5UA, LPF_RESISTORS_10_5KOHM },
 302         { 599, 0x17, CP_CURRENT_7_5UA, LPF_RESISTORS_10_5KOHM },
 303         { 649, 0x08, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM },
 304         { 699, 0x18, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM },
 305         { 749, 0x09, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM },
 306         { 799, 0x19, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM },
 307         { 849, 0x29, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM },
 308         { 899, 0x39, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM },
 309         { 949, 0x0a, CP_CURRENT_12UA, LPF_RESISTORS_8KOHM },
 310         { 999, 0x1a, CP_CURRENT_12UA, LPF_RESISTORS_8KOHM },
 311         {1049, 0x2a, CP_CURRENT_12UA, LPF_RESISTORS_8KOHM },
 312         {1099, 0x3a, CP_CURRENT_12UA, LPF_RESISTORS_8KOHM },
 313         {1149, 0x0b, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM },
 314         {1199, 0x1b, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM },
 315         {1249, 0x2b, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM },
 316         {1299, 0x3b, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM },
 317         {1349, 0x0c, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM },
 318         {1399, 0x1c, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM },
 319         {1449, 0x2c, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM },
 320         {1500, 0x3c, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM }
 321 };
 322
 323 static int max_mbps_to_parameter(unsigned int max_mbps)
 324 {
 325         int i;
 326
 327         for (i = 0; i < ARRAY_SIZE(dppa_map); i++)
 328                 if (dppa_map[i].max_mbps >= max_mbps)
 329                         return i;
 330
 331         return -EINVAL;
 332 }
 333
 334 static inline void dsi_write(struct dw_mipi_dsi_rockchip *dsi, u32 reg, u32 val)
 335 {
 336         writel(val, dsi->base + reg);
 337 }
 338
 339 static inline u32 dsi_read(struct dw_mipi_dsi_rockchip *dsi, u32 reg)
 340 {
 341         return readl(dsi->base + reg);
 342 }
 343
 344 static inline void dsi_update_bits(struct dw_mipi_dsi_rockchip *dsi, u32 reg,
 345                                    u32 mask, u32 val)
 346 {
 347         dsi_write(dsi, reg, (dsi_read(dsi, reg) & ~mask) | val);
 348 }
 349
 350 static void dw_mipi_dsi_phy_write(struct dw_mipi_dsi_rockchip *dsi,
 351                                   u8 test_code,
 352                                   u8 test_data)
 353 {
 354         /*
 355          * With the falling edge on TESTCLK, the TESTDIN[7:0] signal content
 356          * is latched internally as the current test code. Test data is
 357          * programmed internally by rising edge on TESTCLK.
 358          */
 359         dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR);
 360
 361         dsi_write(dsi, DSI_PHY_TST_CTRL1, PHY_TESTEN | PHY_TESTDOUT(0) |
 362                                           PHY_TESTDIN(test_code));
 363
 364         dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLK | PHY_UNTESTCLR);
 365
 366         dsi_write(dsi, DSI_PHY_TST_CTRL1, PHY_UNTESTEN | PHY_TESTDOUT(0) |
 367                                           PHY_TESTDIN(test_data));
 368
 369         dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR);
 370 }
 371
 372 /*
 373  * ns2bc - Nanoseconds to byte clock cycles
 374  */
 375 static inline unsigned int ns2bc(struct dw_mipi_dsi_rockchip *dsi, int ns)
 376 {
 377         return DIV_ROUND_UP(ns * dsi->lane_mbps / 8, 1000);
 378 }
 379
 380 /*
 381  * ns2ui - Nanoseconds to UI time periods
 382  */
 383 static inline unsigned int ns2ui(struct dw_mipi_dsi_rockchip *dsi, int ns)
 384 {
 385         return DIV_ROUND_UP(ns * dsi->lane_mbps, 1000);
 386 }
 387
 388 static int dw_mipi_dsi_phy_init(void *priv_data)
 389 {
 390         struct dw_mipi_dsi_rockchip *dsi = priv_data;
 391         int ret, i, vco;
 392
 393         if (dsi->phy)
 394                 return 0;
 395
 396         /*
 397          * Get vco from frequency(lane_mbps)
 398          * vco  frequency table
 399          * 000 - between   80 and  200 MHz
 400          * 001 - between  200 and  300 MHz
 401          * 010 - between  300 and  500 MHz
 402          * 011 - between  500 and  700 MHz
 403          * 100 - between  700 and  900 MHz
 404          * 101 - between  900 and 1100 MHz
 405          * 110 - between 1100 and 1300 MHz
 406          * 111 - between 1300 and 1500 MHz
 407          */
 408         vco = (dsi->lane_mbps < 200) ? 0 : (dsi->lane_mbps + 100) / 200;
 409
 410         i = max_mbps_to_parameter(dsi->lane_mbps);
 411         if (i < 0) {
 412                 DRM_DEV_ERROR(dsi->dev,
 413                               "failed to get parameter for %dmbps clock\n",
 414                               dsi->lane_mbps);
 415                 return i;
 416         }
 417
 418         ret = clk_prepare_enable(dsi->phy_cfg_clk);
 419         if (ret) {
 420                 DRM_DEV_ERROR(dsi->dev, "Failed to enable phy_cfg_clk\n");
 421                 return ret;
 422         }
 423
 424         dw_mipi_dsi_phy_write(dsi, PLL_BIAS_CUR_SEL_CAP_VCO_CONTROL,
 425                               BYPASS_VCO_RANGE |
 426                               VCO_RANGE_CON_SEL(vco) |
 427                               VCO_IN_CAP_CON_LOW |
 428                               REF_BIAS_CUR_SEL);
 429
 430         dw_mipi_dsi_phy_write(dsi, PLL_CP_CONTROL_PLL_LOCK_BYPASS,
 431                               CP_CURRENT_SEL(dppa_map[i].icpctrl));
 432         dw_mipi_dsi_phy_write(dsi, PLL_LPF_AND_CP_CONTROL,
 433                               CP_PROGRAM_EN | LPF_PROGRAM_EN |
 434                               LPF_RESISTORS_SEL(dppa_map[i].lpfctrl));
 435
 436         dw_mipi_dsi_phy_write(dsi, HS_RX_CONTROL_OF_LANE_0,
 437                               HSFREQRANGE_SEL(dppa_map[i].hsfreqrange));
 438
 439         dw_mipi_dsi_phy_write(dsi, PLL_INPUT_DIVIDER_RATIO,
 440                               INPUT_DIVIDER(dsi->input_div));
 441         dw_mipi_dsi_phy_write(dsi, PLL_LOOP_DIVIDER_RATIO,
 442                               LOOP_DIV_LOW_SEL(dsi->feedback_div) |
 443                               LOW_PROGRAM_EN);
 444         /*
 445          * We need set PLL_INPUT_AND_LOOP_DIVIDER_RATIOS_CONTROL immediately
 446          * to make the configured LSB effective according to IP simulation
 447          * and lab test results.
 448          * Only in this way can we get correct mipi phy pll frequency.
 449          */
 450         dw_mipi_dsi_phy_write(dsi, PLL_INPUT_AND_LOOP_DIVIDER_RATIOS_CONTROL,
 451                               PLL_LOOP_DIV_EN | PLL_INPUT_DIV_EN);
 452         dw_mipi_dsi_phy_write(dsi, PLL_LOOP_DIVIDER_RATIO,
 453                               LOOP_DIV_HIGH_SEL(dsi->feedback_div) |
 454                               HIGH_PROGRAM_EN);
 455         dw_mipi_dsi_phy_write(dsi, PLL_INPUT_AND_LOOP_DIVIDER_RATIOS_CONTROL,
 456                               PLL_LOOP_DIV_EN | PLL_INPUT_DIV_EN);
 457
 458         dw_mipi_dsi_phy_write(dsi, AFE_BIAS_BANDGAP_ANALOG_PROGRAMMABILITY,
 459                               LOW_PROGRAM_EN | BIASEXTR_SEL(BIASEXTR_127_7));
 460         dw_mipi_dsi_phy_write(dsi, AFE_BIAS_BANDGAP_ANALOG_PROGRAMMABILITY,
 461                               HIGH_PROGRAM_EN | BANDGAP_SEL(BANDGAP_96_10));
 462
 463         dw_mipi_dsi_phy_write(dsi, BANDGAP_AND_BIAS_CONTROL,
 464                               POWER_CONTROL | INTERNAL_REG_CURRENT |
 465                               BIAS_BLOCK_ON | BANDGAP_ON);
 466
 467         dw_mipi_dsi_phy_write(dsi, TERMINATION_RESISTER_CONTROL,
 468                               TER_RESISTOR_LOW | TER_CAL_DONE |
 469                               SETRD_MAX | TER_RESISTORS_ON);
 470         dw_mipi_dsi_phy_write(dsi, TERMINATION_RESISTER_CONTROL,
 471                               TER_RESISTOR_HIGH | LEVEL_SHIFTERS_ON |
 472                               SETRD_MAX | POWER_MANAGE |
 473                               TER_RESISTORS_ON);
 474
 475         dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_REQUEST_STATE_TIME_CONTROL,
 476                               TLP_PROGRAM_EN | ns2bc(dsi, 500));
 477         dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_PREPARE_STATE_TIME_CONTROL,
 478                               THS_PRE_PROGRAM_EN | ns2ui(dsi, 40));
 479         dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_HS_ZERO_STATE_TIME_CONTROL,
 480                               THS_ZERO_PROGRAM_EN | ns2bc(dsi, 300));
 481         dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_TRAIL_STATE_TIME_CONTROL,
 482                               THS_PRE_PROGRAM_EN | ns2ui(dsi, 100));
 483         dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_EXIT_STATE_TIME_CONTROL,
 484                               BIT(5) | ns2bc(dsi, 100));
 485         dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_POST_TIME_CONTROL,
 486                               BIT(5) | (ns2bc(dsi, 60) + 7));
 487
 488         dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_REQUEST_STATE_TIME_CONTROL,
 489                               TLP_PROGRAM_EN | ns2bc(dsi, 500));
 490         dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_PREPARE_STATE_TIME_CONTROL,
 491                               THS_PRE_PROGRAM_EN | (ns2ui(dsi, 50) + 20));
 492         dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_HS_ZERO_STATE_TIME_CONTROL,
 493                               THS_ZERO_PROGRAM_EN | (ns2bc(dsi, 140) + 2));
 494         dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_TRAIL_STATE_TIME_CONTROL,
 495                               THS_PRE_PROGRAM_EN | (ns2ui(dsi, 60) + 8));
 496         dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_EXIT_STATE_TIME_CONTROL,
 497                               BIT(5) | ns2bc(dsi, 100));
 498
 499         clk_disable_unprepare(dsi->phy_cfg_clk);
 500
 501         return ret;
 502 }
 503
 504 static void dw_mipi_dsi_phy_power_on(void *priv_data)
 505 {
 506         struct dw_mipi_dsi_rockchip *dsi = priv_data;
 507         int ret;
 508
 509         ret = phy_set_mode(dsi->phy, PHY_MODE_MIPI_DPHY);
 510         if (ret) {
 511                 DRM_DEV_ERROR(dsi->dev, "failed to set phy mode: %d\n", ret);
 512                 return;
 513         }
 514
 515         phy_configure(dsi->phy, &dsi->phy_opts);
 516         phy_power_on(dsi->phy);
 517 }
 518
 519 static void dw_mipi_dsi_phy_power_off(void *priv_data)
 520 {
 521         struct dw_mipi_dsi_rockchip *dsi = priv_data;
 522
 523         phy_power_off(dsi->phy);
 524 }
 525
 526 static int
 527 dw_mipi_dsi_get_lane_mbps(void *priv_data, const struct drm_display_mode *mode,
 528                           unsigned long mode_flags, u32 lanes, u32 format,
 529                           unsigned int *lane_mbps)
 530 {
 531         struct dw_mipi_dsi_rockchip *dsi = priv_data;
 532         int bpp;
 533         unsigned long mpclk, tmp;
 534         unsigned int target_mbps = 1000;
 535         unsigned int max_mbps = dppa_map[ARRAY_SIZE(dppa_map) - 1].max_mbps;
 536         unsigned long best_freq = 0;
 537         unsigned long fvco_min, fvco_max, fin, fout;
 538         unsigned int min_prediv, max_prediv;
 539         unsigned int _prediv, best_prediv;
 540         unsigned long _fbdiv, best_fbdiv;
 541         unsigned long min_delta = ULONG_MAX;
 542
 543         dsi->format = format;
 544         bpp = mipi_dsi_pixel_format_to_bpp(dsi->format);
 545         if (bpp < 0) {
 546                 DRM_DEV_ERROR(dsi->dev,
 547                               "failed to get bpp for pixel format %d\n",
 548                               dsi->format);
 549                 return bpp;
 550         }
 551
 552         mpclk = DIV_ROUND_UP(mode->clock, MSEC_PER_SEC);
 553         if (mpclk) {
 554                 /* take 1 / 0.8, since mbps must big than bandwidth of RGB */
 555                 tmp = mpclk * (bpp / lanes) * 10 / 8;
 556                 if (tmp < max_mbps)
 557                         target_mbps = tmp;
 558                 else
 559                         DRM_DEV_ERROR(dsi->dev,
 560                                       "DPHY clock frequency is out of range\n");
 561         }
 562
 563         /* for external phy only a the mipi_dphy_config is necessary */
 564         if (dsi->phy) {
 565                 phy_mipi_dphy_get_default_config(mode->clock * 1000 * 10 / 8,
 566                                                  bpp, lanes,
 567                                                  &dsi->phy_opts.mipi_dphy);
 568                 dsi->lane_mbps = target_mbps;
 569                 *lane_mbps = dsi->lane_mbps;
 570
 571                 return 0;
 572         }
 573
 574         fin = clk_get_rate(dsi->pllref_clk);
 575         fout = target_mbps * USEC_PER_SEC;
 576
 577         /* constraint: 5Mhz <= Fref / N <= 40MHz */
 578         min_prediv = DIV_ROUND_UP(fin, 40 * USEC_PER_SEC);
 579         max_prediv = fin / (5 * USEC_PER_SEC);
 580
 581         /* constraint: 80MHz <= Fvco <= 1500Mhz */
 582         fvco_min = 80 * USEC_PER_SEC;
 583         fvco_max = 1500 * USEC_PER_SEC;
 584
 585         for (_prediv = min_prediv; _prediv <= max_prediv; _prediv++) {
 586                 u64 tmp;
 587                 u32 delta;
 588                 /* Fvco = Fref * M / N */
 589                 tmp = (u64)fout * _prediv;
 590                 do_div(tmp, fin);
 591                 _fbdiv = tmp;
 592                 /*
 593                  * Due to the use of a "by 2 pre-scaler," the range of the
 594                  * feedback multiplication value M is limited to even division
 595                  * numbers, and m must be greater than 6, not bigger than 512.
 596                  */
 597                 if (_fbdiv < 6 || _fbdiv > 512)
 598                         continue;
 599
 600                 _fbdiv += _fbdiv % 2;
 601
 602                 tmp = (u64)_fbdiv * fin;
 603                 do_div(tmp, _prediv);
 604                 if (tmp < fvco_min || tmp > fvco_max)
 605                         continue;
 606
 607                 delta = abs(fout - tmp);
 608                 if (delta < min_delta) {
 609                         best_prediv = _prediv;
 610                         best_fbdiv = _fbdiv;
 611                         min_delta = delta;
 612                         best_freq = tmp;
 613                 }
 614         }
 615
 616         if (best_freq) {
 617                 dsi->lane_mbps = DIV_ROUND_UP(best_freq, USEC_PER_SEC);
 618                 *lane_mbps = dsi->lane_mbps;
 619                 dsi->input_div = best_prediv;
 620                 dsi->feedback_div = best_fbdiv;
 621         } else {
 622                 DRM_DEV_ERROR(dsi->dev, "Can not find best_freq for DPHY\n");
 623                 return -EINVAL;
 624         }
 625
 626         return 0;
 627 }
 628
 629 struct hstt {
 630         unsigned int maxfreq;
 631         struct dw_mipi_dsi_dphy_timing timing;
 632 };
 633
 634 #define HSTT(_maxfreq, _c_lp2hs, _c_hs2lp, _d_lp2hs, _d_hs2lp)  \
 635 {                                       \
 636         .maxfreq = _maxfreq,            \
 637         .timing = {                     \
 638                 .clk_lp2hs = _c_lp2hs,  \
 639                 .clk_hs2lp = _c_hs2lp,  \
 640                 .data_lp2hs = _d_lp2hs, \
 641                 .data_hs2lp = _d_hs2lp, \
 642         }                               \
 643 }
 644
 645 /* Table A-3 High-Speed Transition Times */
 646 struct hstt hstt_table[] = {
 647         HSTT(  90,  32, 20,  26, 13),
 648         HSTT( 100,  35, 23,  28, 14),
 649         HSTT( 110,  32, 22,  26, 13),
 650         HSTT( 130,  31, 20,  27, 13),
 651         HSTT( 140,  33, 22,  26, 14),
 652         HSTT( 150,  33, 21,  26, 14),
 653         HSTT( 170,  32, 20,  27, 13),
 654         HSTT( 180,  36, 23,  30, 15),
 655         HSTT( 200,  40, 22,  33, 15),
 656         HSTT( 220,  40, 22,  33, 15),
 657         HSTT( 240,  44, 24,  36, 16),
 658         HSTT( 250,  48, 24,  38, 17),
 659         HSTT( 270,  48, 24,  38, 17),
 660         HSTT( 300,  50, 27,  41, 18),
 661         HSTT( 330,  56, 28,  45, 18),
 662         HSTT( 360,  59, 28,  48, 19),
 663         HSTT( 400,  61, 30,  50, 20),
 664         HSTT( 450,  67, 31,  55, 21),
 665         HSTT( 500,  73, 31,  59, 22),
 666         HSTT( 550,  79, 36,  63, 24),
 667         HSTT( 600,  83, 37,  68, 25),
 668         HSTT( 650,  90, 38,  73, 27),
 669         HSTT( 700,  95, 40,  77, 28),
 670         HSTT( 750, 102, 40,  84, 28),
 671         HSTT( 800, 106, 42,  87, 30),
 672         HSTT( 850, 113, 44,  93, 31),
 673         HSTT( 900, 118, 47,  98, 32),
 674         HSTT( 950, 124, 47, 102, 34),
 675         HSTT(1000, 130, 49, 107, 35),
 676         HSTT(1050, 135, 51, 111, 37),
 677         HSTT(1100, 139, 51, 114, 38),
 678         HSTT(1150, 146, 54, 120, 40),
 679         HSTT(1200, 153, 57, 125, 41),
 680         HSTT(1250, 158, 58, 130, 42),
 681         HSTT(1300, 163, 58, 135, 44),
 682         HSTT(1350, 168, 60, 140, 45),
 683         HSTT(1400, 172, 64, 144, 47),
 684         HSTT(1450, 176, 65, 148, 48),
 685         HSTT(1500, 181, 66, 153, 50)
 686 };
 687
 688 static int
 689 dw_mipi_dsi_phy_get_timing(void *priv_data, unsigned int lane_mbps,
 690                            struct dw_mipi_dsi_dphy_timing *timing)
 691 {
 692         int i;
 693
 694         for (i = 0; i < ARRAY_SIZE(hstt_table); i++)
 695                 if (lane_mbps < hstt_table[i].maxfreq)
 696                         break;
 697
 698         if (i == ARRAY_SIZE(hstt_table))
 699                 i--;
 700
 701         *timing = hstt_table[i].timing;
 702
 703         return 0;
 704 }
 705
 706 static const struct dw_mipi_dsi_phy_ops dw_mipi_dsi_rockchip_phy_ops = {
 707         .init = dw_mipi_dsi_phy_init,
 708         .power_on = dw_mipi_dsi_phy_power_on,
 709         .power_off = dw_mipi_dsi_phy_power_off,
 710         .get_lane_mbps = dw_mipi_dsi_get_lane_mbps,
 711         .get_timing = dw_mipi_dsi_phy_get_timing,
 712 };
 713
 714 static void dw_mipi_dsi_rockchip_config(struct dw_mipi_dsi_rockchip *dsi)
 715 {
 716         if (dsi->cdata->lanecfg1_grf_reg)
 717                 regmap_write(dsi->grf_regmap, dsi->cdata->lanecfg1_grf_reg,
 718                                               dsi->cdata->lanecfg1);
 719
 720         if (dsi->cdata->lanecfg2_grf_reg)
 721                 regmap_write(dsi->grf_regmap, dsi->cdata->lanecfg2_grf_reg,
 722                                               dsi->cdata->lanecfg2);
 723
 724         if (dsi->cdata->enable_grf_reg)
 725                 regmap_write(dsi->grf_regmap, dsi->cdata->enable_grf_reg,
 726                                               dsi->cdata->enable);
 727 }
 728
 729 static void dw_mipi_dsi_rockchip_set_lcdsel(struct dw_mipi_dsi_rockchip *dsi,
 730                                             int mux)
 731 {
 732         regmap_write(dsi->grf_regmap, dsi->cdata->lcdsel_grf_reg,
 733                 mux ? dsi->cdata->lcdsel_lit : dsi->cdata->lcdsel_big);
 734 }
 735
 736 static int
 737 dw_mipi_dsi_encoder_atomic_check(struct drm_encoder *encoder,
 738                                  struct drm_crtc_state *crtc_state,
 739                                  struct drm_connector_state *conn_state)
 740 {
 741         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
 742         struct dw_mipi_dsi_rockchip *dsi = to_dsi(encoder);
 743
 744         switch (dsi->format) {
 745         case MIPI_DSI_FMT_RGB888:
 746                 s->output_mode = ROCKCHIP_OUT_MODE_P888;
 747                 break;
 748         case MIPI_DSI_FMT_RGB666:
 749                 s->output_mode = ROCKCHIP_OUT_MODE_P666;
 750                 break;
 751         case MIPI_DSI_FMT_RGB565:
 752                 s->output_mode = ROCKCHIP_OUT_MODE_P565;
 753                 break;
 754         default:
 755                 WARN_ON(1);
 756                 return -EINVAL;
 757         }
 758
 759         s->output_type = DRM_MODE_CONNECTOR_DSI;
 760         if (dsi->slave)
 761                 s->output_flags = ROCKCHIP_OUTPUT_DSI_DUAL;
 762
 763         return 0;
 764 }
 765
 766 static void dw_mipi_dsi_encoder_enable(struct drm_encoder *encoder)
 767 {
 768         struct dw_mipi_dsi_rockchip *dsi = to_dsi(encoder);
 769         int ret, mux;
 770
 771         mux = drm_of_encoder_active_endpoint_id(dsi->dev->of_node,
 772                                                 &dsi->encoder);
 773         if (mux < 0)
 774                 return;
 775
 776         pm_runtime_get_sync(dsi->dev);
 777         if (dsi->slave)
 778                 pm_runtime_get_sync(dsi->slave->dev);
 779
 780         /*
 781          * For the RK3399, the clk of grf must be enabled before writing grf
 782          * register. And for RK3288 or other soc, this grf_clk must be NULL,
 783          * the clk_prepare_enable return true directly.
 784          */
 785         ret = clk_prepare_enable(dsi->grf_clk);
 786         if (ret) {
 787                 DRM_DEV_ERROR(dsi->dev, "Failed to enable grf_clk: %d\n", ret);
 788                 return;
 789         }
 790
 791         dw_mipi_dsi_rockchip_set_lcdsel(dsi, mux);
 792         if (dsi->slave)
 793                 dw_mipi_dsi_rockchip_set_lcdsel(dsi->slave, mux);
 794
 795         clk_disable_unprepare(dsi->grf_clk);
 796 }
 797
 798 static void dw_mipi_dsi_encoder_disable(struct drm_encoder *encoder)
 799 {
 800         struct dw_mipi_dsi_rockchip *dsi = to_dsi(encoder);
 801
 802         if (dsi->slave)
 803                 pm_runtime_put(dsi->slave->dev);
 804         pm_runtime_put(dsi->dev);
 805 }
 806
 807 static const struct drm_encoder_helper_funcs
 808 dw_mipi_dsi_encoder_helper_funcs = {
 809         .atomic_check = dw_mipi_dsi_encoder_atomic_check,
 810         .enable = dw_mipi_dsi_encoder_enable,
 811         .disable = dw_mipi_dsi_encoder_disable,
 812 };
 813
 814 static int rockchip_dsi_drm_create_encoder(struct dw_mipi_dsi_rockchip *dsi,
 815                                            struct drm_device *drm_dev)
 816 {
 817         struct drm_encoder *encoder = &dsi->encoder;
 818         int ret;
 819
 820         encoder->possible_crtcs = drm_of_find_possible_crtcs(drm_dev,
 821                                                              dsi->dev->of_node);
 822
 823         ret = drm_simple_encoder_init(drm_dev, encoder, DRM_MODE_ENCODER_DSI);
 824         if (ret) {
 825                 DRM_ERROR("Failed to initialize encoder with drm\n");
 826                 return ret;
 827         }
 828
 829         drm_encoder_helper_add(encoder, &dw_mipi_dsi_encoder_helper_funcs);
 830
 831         return 0;
 832 }
 833
 834 static struct device
 835 *dw_mipi_dsi_rockchip_find_second(struct dw_mipi_dsi_rockchip *dsi)
 836 {
 837         const struct of_device_id *match;
 838         struct device_node *node = NULL, *local;
 839
 840         match = of_match_device(dsi->dev->driver->of_match_table, dsi->dev);
 841
 842         local = of_graph_get_remote_node(dsi->dev->of_node, 1, 0);
 843         if (!local)
 844                 return NULL;
 845
 846         while ((node = of_find_compatible_node(node, NULL,
 847                                                match->compatible))) {
 848                 struct device_node *remote;
 849
 850                 /* found ourself */
 851                 if (node == dsi->dev->of_node)
 852                         continue;
 853
 854                 remote = of_graph_get_remote_node(node, 1, 0);
 855                 if (!remote)
 856                         continue;
 857
 858                 /* same display device in port1-ep0 for both */
 859                 if (remote == local) {
 860                         struct dw_mipi_dsi_rockchip *dsi2;
 861                         struct platform_device *pdev;
 862
 863                         pdev = of_find_device_by_node(node);
 864
 865                         /*
 866                          * we have found the second, so will either return it
 867                          * or return with an error. In any case won't need the
 868                          * nodes anymore nor continue the loop.
 869                          */
 870                         of_node_put(remote);
 871                         of_node_put(node);
 872                         of_node_put(local);
 873
 874                         if (!pdev)
 875                                 return ERR_PTR(-EPROBE_DEFER);
 876
 877                         dsi2 = platform_get_drvdata(pdev);
 878                         if (!dsi2) {
 879                                 platform_device_put(pdev);
 880                                 return ERR_PTR(-EPROBE_DEFER);
 881                         }
 882
 883                         return &pdev->dev;
 884                 }
 885
 886                 of_node_put(remote);
 887         }
 888
 889         of_node_put(local);
 890
 891         return NULL;
 892 }
 893
 894 static int dw_mipi_dsi_rockchip_bind(struct device *dev,
 895                                      struct device *master,
 896                                      void *data)
 897 {
 898         struct dw_mipi_dsi_rockchip *dsi = dev_get_drvdata(dev);
 899         struct drm_device *drm_dev = data;
 900         struct device *second;
 901         bool master1, master2;
 902         int ret;
 903
 904         second = dw_mipi_dsi_rockchip_find_second(dsi);
 905         if (IS_ERR(second))
 906                 return PTR_ERR(second);
 907
 908         if (second) {
 909                 master1 = of_property_read_bool(dsi->dev->of_node,
 910                                                 "clock-master");
 911                 master2 = of_property_read_bool(second->of_node,
 912                                                 "clock-master");
 913
 914                 if (master1 && master2) {
 915                         DRM_DEV_ERROR(dsi->dev, "only one clock-master allowed\n");
 916                         return -EINVAL;
 917                 }
 918
 919                 if (!master1 && !master2) {
 920                         DRM_DEV_ERROR(dsi->dev, "no clock-master defined\n");
 921                         return -EINVAL;
 922                 }
 923
 924                 /* we are the slave in dual-DSI */
 925                 if (!master1) {
 926                         dsi->is_slave = true;
 927                         return 0;
 928                 }
 929
 930                 dsi->slave = dev_get_drvdata(second);
 931                 if (!dsi->slave) {
 932                         DRM_DEV_ERROR(dev, "could not get slaves data\n");
 933                         return -ENODEV;
 934                 }
 935
 936                 dsi->slave->is_slave = true;
 937                 dw_mipi_dsi_set_slave(dsi->dmd, dsi->slave->dmd);
 938                 put_device(second);
 939         }
 940
 941         ret = clk_prepare_enable(dsi->pllref_clk);
 942         if (ret) {
 943                 DRM_DEV_ERROR(dev, "Failed to enable pllref_clk: %d\n", ret);
 944                 return ret;
 945         }
 946
 947         /*
 948          * With the GRF clock running, write lane and dual-mode configurations
 949          * that won't change immediately. If we waited until enable() to do
 950          * this, things like panel preparation would not be able to send
 951          * commands over DSI.
 952          */
 953         ret = clk_prepare_enable(dsi->grf_clk);
 954         if (ret) {
 955                 DRM_DEV_ERROR(dsi->dev, "Failed to enable grf_clk: %d\n", ret);
 956                 return ret;
 957         }
 958
 959         dw_mipi_dsi_rockchip_config(dsi);
 960         if (dsi->slave)
 961                 dw_mipi_dsi_rockchip_config(dsi->slave);
 962
 963         clk_disable_unprepare(dsi->grf_clk);
 964
 965         ret = rockchip_dsi_drm_create_encoder(dsi, drm_dev);
 966         if (ret) {
 967                 DRM_DEV_ERROR(dev, "Failed to create drm encoder\n");
 968                 return ret;
 969         }
 970
 971         ret = dw_mipi_dsi_bind(dsi->dmd, &dsi->encoder);
 972         if (ret) {
 973                 DRM_DEV_ERROR(dev, "Failed to bind: %d\n", ret);
 974                 return ret;
 975         }
 976
 977         return 0;
 978 }
 979
 980 static void dw_mipi_dsi_rockchip_unbind(struct device *dev,
 981                                         struct device *master,
 982                                         void *data)
 983 {
 984         struct dw_mipi_dsi_rockchip *dsi = dev_get_drvdata(dev);
 985
 986         if (dsi->is_slave)
 987                 return;
 988
 989         dw_mipi_dsi_unbind(dsi->dmd);
 990
 991         clk_disable_unprepare(dsi->pllref_clk);
 992 }
 993
 994 static const struct component_ops dw_mipi_dsi_rockchip_ops = {
 995         .bind   = dw_mipi_dsi_rockchip_bind,
 996         .unbind = dw_mipi_dsi_rockchip_unbind,
 997 };
 998
 999 static int dw_mipi_dsi_rockchip_host_attach(void *priv_data,
1000                                             struct mipi_dsi_device *device)
1001 {
1002         struct dw_mipi_dsi_rockchip *dsi = priv_data;
1003         struct device *second;
1004         int ret;
1005
1006         mutex_lock(&dsi->usage_mutex);
1007
1008         if (dsi->usage_mode != DW_DSI_USAGE_IDLE) {
1009                 DRM_DEV_ERROR(dsi->dev, "dsi controller already in use\n");
1010                 mutex_unlock(&dsi->usage_mutex);
1011                 return -EBUSY;
1012         }
1013
1014         dsi->usage_mode = DW_DSI_USAGE_DSI;
1015         mutex_unlock(&dsi->usage_mutex);
1016
1017         ret = component_add(dsi->dev, &dw_mipi_dsi_rockchip_ops);
1018         if (ret) {
1019                 DRM_DEV_ERROR(dsi->dev, "Failed to register component: %d\n",
1020                                         ret);
1021                 return ret;
1022         }
1023
1024         second = dw_mipi_dsi_rockchip_find_second(dsi);
1025         if (IS_ERR(second))
1026                 return PTR_ERR(second);
1027         if (second) {
1028                 ret = component_add(second, &dw_mipi_dsi_rockchip_ops);
1029                 if (ret) {
1030                         DRM_DEV_ERROR(second,
1031                                       "Failed to register component: %d\n",
1032                                       ret);
1033                         return ret;
1034                 }
1035         }
1036
1037         return 0;
1038 }
1039
1040 static int dw_mipi_dsi_rockchip_host_detach(void *priv_data,
1041                                             struct mipi_dsi_device *device)
1042 {
1043         struct dw_mipi_dsi_rockchip *dsi = priv_data;
1044         struct device *second;
1045
1046         second = dw_mipi_dsi_rockchip_find_second(dsi);
1047         if (second && !IS_ERR(second))
1048                 component_del(second, &dw_mipi_dsi_rockchip_ops);
1049
1050         component_del(dsi->dev, &dw_mipi_dsi_rockchip_ops);
1051
1052         mutex_lock(&dsi->usage_mutex);
1053         dsi->usage_mode = DW_DSI_USAGE_IDLE;
1054         mutex_unlock(&dsi->usage_mutex);
1055
1056         return 0;
1057 }
1058
1059 static const struct dw_mipi_dsi_host_ops dw_mipi_dsi_rockchip_host_ops = {
1060         .attach = dw_mipi_dsi_rockchip_host_attach,
1061         .detach = dw_mipi_dsi_rockchip_host_detach,
1062 };
1063
1064 static int dw_mipi_dsi_rockchip_dphy_bind(struct device *dev,
1065                                           struct device *master,
1066                                           void *data)
1067 {
1068         /*
1069          * Nothing to do when used as a dphy.
1070          * Just make the rest of Rockchip-DRM happy
1071          * by being here.
1072          */
1073
1074         return 0;
1075 }
1076
1077 static void dw_mipi_dsi_rockchip_dphy_unbind(struct device *dev,
1078                                              struct device *master,
1079                                              void *data)
1080 {
1081         /* Nothing to do when used as a dphy. */
1082 }
1083
1084 static const struct component_ops dw_mipi_dsi_rockchip_dphy_ops = {
1085         .bind   = dw_mipi_dsi_rockchip_dphy_bind,
1086         .unbind = dw_mipi_dsi_rockchip_dphy_unbind,
1087 };
1088
1089 static int dw_mipi_dsi_dphy_init(struct phy *phy)
1090 {
1091         struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy);
1092         int ret;
1093
1094         mutex_lock(&dsi->usage_mutex);
1095
1096         if (dsi->usage_mode != DW_DSI_USAGE_IDLE) {
1097                 DRM_DEV_ERROR(dsi->dev, "dsi controller already in use\n");
1098                 mutex_unlock(&dsi->usage_mutex);
1099                 return -EBUSY;
1100         }
1101
1102         dsi->usage_mode = DW_DSI_USAGE_PHY;
1103         mutex_unlock(&dsi->usage_mutex);
1104
1105         ret = component_add(dsi->dev, &dw_mipi_dsi_rockchip_dphy_ops);
1106         if (ret < 0)
1107                 goto err_graph;
1108
1109         if (dsi->cdata->dphy_rx_init) {
1110                 ret = clk_prepare_enable(dsi->pclk);
1111                 if (ret < 0)
1112                         goto err_init;
1113
1114                 ret = clk_prepare_enable(dsi->grf_clk);
1115                 if (ret) {
1116                         clk_disable_unprepare(dsi->pclk);
1117                         goto err_init;
1118                 }
1119
1120                 ret = dsi->cdata->dphy_rx_init(phy);
1121                 clk_disable_unprepare(dsi->grf_clk);
1122                 clk_disable_unprepare(dsi->pclk);
1123                 if (ret < 0)
1124                         goto err_init;
1125         }
1126
1127         return 0;
1128
1129 err_init:
1130         component_del(dsi->dev, &dw_mipi_dsi_rockchip_dphy_ops);
1131 err_graph:
1132         mutex_lock(&dsi->usage_mutex);
1133         dsi->usage_mode = DW_DSI_USAGE_IDLE;
1134         mutex_unlock(&dsi->usage_mutex);
1135
1136         return ret;
1137 }
1138
1139 static int dw_mipi_dsi_dphy_exit(struct phy *phy)
1140 {
1141         struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy);
1142
1143         component_del(dsi->dev, &dw_mipi_dsi_rockchip_dphy_ops);
1144
1145         mutex_lock(&dsi->usage_mutex);
1146         dsi->usage_mode = DW_DSI_USAGE_IDLE;
1147         mutex_unlock(&dsi->usage_mutex);
1148
1149         return 0;
1150 }
1151
1152 static int dw_mipi_dsi_dphy_configure(struct phy *phy, union phy_configure_opts *opts)
1153 {
1154         struct phy_configure_opts_mipi_dphy *config = &opts->mipi_dphy;
1155         struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy);
1156         int ret;
1157
1158         ret = phy_mipi_dphy_config_validate(&opts->mipi_dphy);
1159         if (ret)
1160                 return ret;
1161
1162         dsi->dphy_config = *config;
1163         dsi->lane_mbps = div_u64(config->hs_clk_rate, 1000 * 1000 * 1);
1164
1165         return 0;
1166 }
1167
1168 static int dw_mipi_dsi_dphy_power_on(struct phy *phy)
1169 {
1170         struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy);
1171         int i, ret;
1172
1173         DRM_DEV_DEBUG(dsi->dev, "lanes %d - data_rate_mbps %u\n",
1174                       dsi->dphy_config.lanes, dsi->lane_mbps);
1175
1176         i = max_mbps_to_parameter(dsi->lane_mbps);
1177         if (i < 0) {
1178                 DRM_DEV_ERROR(dsi->dev, "failed to get parameter for %dmbps clock\n",
1179                               dsi->lane_mbps);
1180                 return i;
1181         }
1182
1183         ret = pm_runtime_get_sync(dsi->dev);
1184         if (ret < 0) {
1185                 DRM_DEV_ERROR(dsi->dev, "failed to enable device: %d\n", ret);
1186                 return ret;
1187         }
1188
1189         ret = clk_prepare_enable(dsi->pclk);
1190         if (ret) {
1191                 DRM_DEV_ERROR(dsi->dev, "Failed to enable pclk: %d\n", ret);
1192                 goto err_pclk;
1193         }
1194
1195         ret = clk_prepare_enable(dsi->grf_clk);
1196         if (ret) {
1197                 DRM_DEV_ERROR(dsi->dev, "Failed to enable grf_clk: %d\n", ret);
1198                 goto err_grf_clk;
1199         }
1200
1201         ret = clk_prepare_enable(dsi->phy_cfg_clk);
1202         if (ret) {
1203                 DRM_DEV_ERROR(dsi->dev, "Failed to enable phy_cfg_clk: %d\n", ret);
1204                 goto err_phy_cfg_clk;
1205         }
1206
1207         /* do soc-variant specific init */
1208         if (dsi->cdata->dphy_rx_power_on) {
1209                 ret = dsi->cdata->dphy_rx_power_on(phy);
1210                 if (ret < 0) {
1211                         DRM_DEV_ERROR(dsi->dev, "hardware-specific phy bringup failed: %d\n", ret);
1212                         goto err_pwr_on;
1213                 }
1214         }
1215
1216         /*
1217          * Configure hsfreqrange according to frequency values
1218          * Set clock lane and hsfreqrange by lane0(test code 0x44)
1219          */
1220         dw_mipi_dsi_phy_write(dsi, HS_RX_CONTROL_OF_LANE_CLK, 0);
1221         dw_mipi_dsi_phy_write(dsi, HS_RX_CONTROL_OF_LANE_0,
1222                               HSFREQRANGE_SEL(dppa_map[i].hsfreqrange));
1223         dw_mipi_dsi_phy_write(dsi, HS_RX_CONTROL_OF_LANE_1, 0);
1224         dw_mipi_dsi_phy_write(dsi, HS_RX_CONTROL_OF_LANE_2, 0);
1225         dw_mipi_dsi_phy_write(dsi, HS_RX_CONTROL_OF_LANE_3, 0);
1226
1227         /* Normal operation */
1228         dw_mipi_dsi_phy_write(dsi, 0x0, 0);
1229
1230         clk_disable_unprepare(dsi->phy_cfg_clk);
1231         clk_disable_unprepare(dsi->grf_clk);
1232
1233         return ret;
1234
1235 err_pwr_on:
1236         clk_disable_unprepare(dsi->phy_cfg_clk);
1237 err_phy_cfg_clk:
1238         clk_disable_unprepare(dsi->grf_clk);
1239 err_grf_clk:
1240         clk_disable_unprepare(dsi->pclk);
1241 err_pclk:
1242         pm_runtime_put(dsi->dev);
1243         return ret;
1244 }
1245
1246 static int dw_mipi_dsi_dphy_power_off(struct phy *phy)
1247 {
1248         struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy);
1249         int ret;
1250
1251         ret = clk_prepare_enable(dsi->grf_clk);
1252         if (ret) {
1253                 DRM_DEV_ERROR(dsi->dev, "Failed to enable grf_clk: %d\n", ret);
1254                 return ret;
1255         }
1256
1257         if (dsi->cdata->dphy_rx_power_off) {
1258                 ret = dsi->cdata->dphy_rx_power_off(phy);
1259                 if (ret < 0)
1260                         DRM_DEV_ERROR(dsi->dev, "hardware-specific phy shutdown failed: %d\n", ret);
1261         }
1262
1263         clk_disable_unprepare(dsi->grf_clk);
1264         clk_disable_unprepare(dsi->pclk);
1265
1266         pm_runtime_put(dsi->dev);
1267
1268         return ret;
1269 }
1270
1271 static const struct phy_ops dw_mipi_dsi_dphy_ops = {
1272         .configure      = dw_mipi_dsi_dphy_configure,
1273         .power_on       = dw_mipi_dsi_dphy_power_on,
1274         .power_off      = dw_mipi_dsi_dphy_power_off,
1275         .init           = dw_mipi_dsi_dphy_init,
1276         .exit           = dw_mipi_dsi_dphy_exit,
1277 };
1278
1279 static int dw_mipi_dsi_rockchip_probe(struct platform_device *pdev)
1280 {
1281         struct device *dev = &pdev->dev;
1282         struct device_node *np = dev->of_node;
1283         struct dw_mipi_dsi_rockchip *dsi;
1284         struct phy_provider *phy_provider;
1285         struct resource *res;
1286         const struct rockchip_dw_dsi_chip_data *cdata =
1287                                 of_device_get_match_data(dev);
1288         int ret, i;
1289
1290         dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);
1291         if (!dsi)
1292                 return -ENOMEM;
1293
1294         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1295         dsi->base = devm_ioremap_resource(dev, res);
1296         if (IS_ERR(dsi->base)) {
1297                 DRM_DEV_ERROR(dev, "Unable to get dsi registers\n");
1298                 return PTR_ERR(dsi->base);
1299         }
1300
1301         i = 0;
1302         while (cdata[i].reg) {
1303                 if (cdata[i].reg == res->start) {
1304                         dsi->cdata = &cdata[i];
1305                         break;
1306                 }
1307
1308                 i++;
1309         }
1310
1311         if (!dsi->cdata) {
1312                 DRM_DEV_ERROR(dev, "no dsi-config for %s node\n", np->name);
1313                 return -EINVAL;
1314         }
1315
1316         /* try to get a possible external dphy */
1317         dsi->phy = devm_phy_optional_get(dev, "dphy");
1318         if (IS_ERR(dsi->phy)) {
1319                 ret = PTR_ERR(dsi->phy);
1320                 DRM_DEV_ERROR(dev, "failed to get mipi dphy: %d\n", ret);
1321                 return ret;
1322         }
1323
1324         dsi->pclk = devm_clk_get(dev, "pclk");
1325         if (IS_ERR(dsi->pclk)) {
1326                 ret = PTR_ERR(dsi->pclk);
1327                 DRM_DEV_ERROR(dev, "Unable to get pclk: %d\n", ret);
1328                 return ret;
1329         }
1330
1331         dsi->pllref_clk = devm_clk_get(dev, "ref");
1332         if (IS_ERR(dsi->pllref_clk)) {
1333                 if (dsi->phy) {
1334                         /*
1335                          * if external phy is present, pll will be
1336                          * generated there.
1337                          */
1338                         dsi->pllref_clk = NULL;
1339                 } else {
1340                         ret = PTR_ERR(dsi->pllref_clk);
1341                         DRM_DEV_ERROR(dev,
1342                                       "Unable to get pll reference clock: %d\n",
1343                                       ret);
1344                         return ret;
1345                 }
1346         }
1347
1348         if (dsi->cdata->flags & DW_MIPI_NEEDS_PHY_CFG_CLK) {
1349                 dsi->phy_cfg_clk = devm_clk_get(dev, "phy_cfg");
1350                 if (IS_ERR(dsi->phy_cfg_clk)) {
1351                         ret = PTR_ERR(dsi->phy_cfg_clk);
1352                         DRM_DEV_ERROR(dev,
1353                                       "Unable to get phy_cfg_clk: %d\n", ret);
1354                         return ret;
1355                 }
1356         }
1357
1358         if (dsi->cdata->flags & DW_MIPI_NEEDS_GRF_CLK) {
1359                 dsi->grf_clk = devm_clk_get(dev, "grf");
1360                 if (IS_ERR(dsi->grf_clk)) {
1361                         ret = PTR_ERR(dsi->grf_clk);
1362                         DRM_DEV_ERROR(dev, "Unable to get grf_clk: %d\n", ret);
1363                         return ret;
1364                 }
1365         }
1366
1367         dsi->grf_regmap = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
1368         if (IS_ERR(dsi->grf_regmap)) {
1369                 DRM_DEV_ERROR(dev, "Unable to get rockchip,grf\n");
1370                 return PTR_ERR(dsi->grf_regmap);
1371         }
1372
1373         dsi->dev = dev;
1374         dsi->pdata.base = dsi->base;
1375         dsi->pdata.max_data_lanes = dsi->cdata->max_data_lanes;
1376         dsi->pdata.phy_ops = &dw_mipi_dsi_rockchip_phy_ops;
1377         dsi->pdata.host_ops = &dw_mipi_dsi_rockchip_host_ops;
1378         dsi->pdata.priv_data = dsi;
1379         platform_set_drvdata(pdev, dsi);
1380
1381         mutex_init(&dsi->usage_mutex);
1382
1383         dsi->dphy = devm_phy_create(dev, NULL, &dw_mipi_dsi_dphy_ops);
1384         if (IS_ERR(dsi->dphy)) {
1385                 DRM_DEV_ERROR(&pdev->dev, "failed to create PHY\n");
1386                 return PTR_ERR(dsi->dphy);
1387         }
1388
1389         phy_set_drvdata(dsi->dphy, dsi);
1390         phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
1391         if (IS_ERR(phy_provider))
1392                 return PTR_ERR(phy_provider);
1393
1394         dsi->dmd = dw_mipi_dsi_probe(pdev, &dsi->pdata);
1395         if (IS_ERR(dsi->dmd)) {
1396                 ret = PTR_ERR(dsi->dmd);
1397                 if (ret != -EPROBE_DEFER)
1398                         DRM_DEV_ERROR(dev,
1399                                       "Failed to probe dw_mipi_dsi: %d\n", ret);
1400                 goto err_clkdisable;
1401         }
1402
1403         return 0;
1404
1405 err_clkdisable:
1406         clk_disable_unprepare(dsi->pllref_clk);
1407         return ret;
1408 }
1409
1410 static int dw_mipi_dsi_rockchip_remove(struct platform_device *pdev)
1411 {
1412         struct dw_mipi_dsi_rockchip *dsi = platform_get_drvdata(pdev);
1413
1414         dw_mipi_dsi_remove(dsi->dmd);
1415
1416         return 0;
1417 }
1418
1419 static const struct rockchip_dw_dsi_chip_data px30_chip_data[] = {
1420         {
1421                 .reg = 0xff450000,
1422                 .lcdsel_grf_reg = PX30_GRF_PD_VO_CON1,
1423                 .lcdsel_big = HIWORD_UPDATE(0, PX30_DSI_LCDC_SEL),
1424                 .lcdsel_lit = HIWORD_UPDATE(PX30_DSI_LCDC_SEL,
1425                                             PX30_DSI_LCDC_SEL),
1426
1427                 .lanecfg1_grf_reg = PX30_GRF_PD_VO_CON1,
1428                 .lanecfg1 = HIWORD_UPDATE(0, PX30_DSI_TURNDISABLE |
1429                                              PX30_DSI_FORCERXMODE |
1430                                              PX30_DSI_FORCETXSTOPMODE),
1431
1432                 .max_data_lanes = 4,
1433         },
1434         { /* sentinel */ }
1435 };
1436
1437 static const struct rockchip_dw_dsi_chip_data rk3288_chip_data[] = {
1438         {
1439                 .reg = 0xff960000,
1440                 .lcdsel_grf_reg = RK3288_GRF_SOC_CON6,
1441                 .lcdsel_big = HIWORD_UPDATE(0, RK3288_DSI0_LCDC_SEL),
1442                 .lcdsel_lit = HIWORD_UPDATE(RK3288_DSI0_LCDC_SEL, RK3288_DSI0_LCDC_SEL),
1443
1444                 .max_data_lanes = 4,
1445         },
1446         {
1447                 .reg = 0xff964000,
1448                 .lcdsel_grf_reg = RK3288_GRF_SOC_CON6,
1449                 .lcdsel_big = HIWORD_UPDATE(0, RK3288_DSI1_LCDC_SEL),
1450                 .lcdsel_lit = HIWORD_UPDATE(RK3288_DSI1_LCDC_SEL, RK3288_DSI1_LCDC_SEL),
1451
1452                 .max_data_lanes = 4,
1453         },
1454         { /* sentinel */ }
1455 };
1456
1457 static int rk3399_dphy_tx1rx1_init(struct phy *phy)
1458 {
1459         struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy);
1460
1461         /*
1462          * Set TX1RX1 source to isp1.
1463          * Assume ISP0 is supplied by the RX0 dphy.
1464          */
1465         regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24,
1466                      HIWORD_UPDATE(0, RK3399_TXRX_SRC_SEL_ISP0));
1467         regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24,
1468                      HIWORD_UPDATE(0, RK3399_TXRX_MASTERSLAVEZ));
1469         regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24,
1470                      HIWORD_UPDATE(0, RK3399_TXRX_BASEDIR));
1471         regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23,
1472                      HIWORD_UPDATE(0, RK3399_DSI1_ENABLE));
1473
1474         return 0;
1475 }
1476
1477 static int rk3399_dphy_tx1rx1_power_on(struct phy *phy)
1478 {
1479         struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy);
1480
1481         /* tester reset pulse */
1482         dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_TESTCLR);
1483         usleep_range(100, 150);
1484
1485         regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24,
1486                      HIWORD_UPDATE(0, RK3399_TXRX_MASTERSLAVEZ));
1487         regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24,
1488                      HIWORD_UPDATE(RK3399_TXRX_BASEDIR, RK3399_TXRX_BASEDIR));
1489
1490         regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23,
1491                      HIWORD_UPDATE(0, RK3399_DSI1_FORCERXMODE));
1492         regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23,
1493                      HIWORD_UPDATE(0, RK3399_DSI1_FORCETXSTOPMODE));
1494
1495         /* Disable lane turn around, which is ignored in receive mode */
1496         regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24,
1497                      HIWORD_UPDATE(0, RK3399_TXRX_TURNREQUEST));
1498         regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23,
1499                      HIWORD_UPDATE(RK3399_DSI1_TURNDISABLE,
1500                                    RK3399_DSI1_TURNDISABLE));
1501         usleep_range(100, 150);
1502
1503         dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR);
1504         usleep_range(100, 150);
1505
1506         /* Enable dphy lanes */
1507         regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23,
1508                      HIWORD_UPDATE(GENMASK(dsi->dphy_config.lanes - 1, 0),
1509                                    RK3399_DSI1_ENABLE));
1510
1511         usleep_range(100, 150);
1512
1513         return 0;
1514 }
1515
1516 static int rk3399_dphy_tx1rx1_power_off(struct phy *phy)
1517 {
1518         struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy);
1519
1520         regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23,
1521                      HIWORD_UPDATE(0, RK3399_DSI1_ENABLE));
1522
1523         return 0;
1524 }
1525
1526 static const struct rockchip_dw_dsi_chip_data rk3399_chip_data[] = {
1527         {
1528                 .reg = 0xff960000,
1529                 .lcdsel_grf_reg = RK3399_GRF_SOC_CON20,
1530                 .lcdsel_big = HIWORD_UPDATE(0, RK3399_DSI0_LCDC_SEL),
1531                 .lcdsel_lit = HIWORD_UPDATE(RK3399_DSI0_LCDC_SEL,
1532                                             RK3399_DSI0_LCDC_SEL),
1533
1534                 .lanecfg1_grf_reg = RK3399_GRF_SOC_CON22,
1535                 .lanecfg1 = HIWORD_UPDATE(0, RK3399_DSI0_TURNREQUEST |
1536                                              RK3399_DSI0_TURNDISABLE |
1537                                              RK3399_DSI0_FORCETXSTOPMODE |
1538                                              RK3399_DSI0_FORCERXMODE),
1539
1540                 .flags = DW_MIPI_NEEDS_PHY_CFG_CLK | DW_MIPI_NEEDS_GRF_CLK,
1541                 .max_data_lanes = 4,
1542         },
1543         {
1544                 .reg = 0xff968000,
1545                 .lcdsel_grf_reg = RK3399_GRF_SOC_CON20,
1546                 .lcdsel_big = HIWORD_UPDATE(0, RK3399_DSI1_LCDC_SEL),
1547                 .lcdsel_lit = HIWORD_UPDATE(RK3399_DSI1_LCDC_SEL,
1548                                             RK3399_DSI1_LCDC_SEL),
1549
1550                 .lanecfg1_grf_reg = RK3399_GRF_SOC_CON23,
1551                 .lanecfg1 = HIWORD_UPDATE(0, RK3399_DSI1_TURNDISABLE |
1552                                              RK3399_DSI1_FORCETXSTOPMODE |
1553                                              RK3399_DSI1_FORCERXMODE |
1554                                              RK3399_DSI1_ENABLE),
1555
1556                 .lanecfg2_grf_reg = RK3399_GRF_SOC_CON24,
1557                 .lanecfg2 = HIWORD_UPDATE(RK3399_TXRX_MASTERSLAVEZ |
1558                                           RK3399_TXRX_ENABLECLK,
1559                                           RK3399_TXRX_MASTERSLAVEZ |
1560                                           RK3399_TXRX_ENABLECLK |
1561                                           RK3399_TXRX_BASEDIR),
1562
1563                 .enable_grf_reg = RK3399_GRF_SOC_CON23,
1564                 .enable = HIWORD_UPDATE(RK3399_DSI1_ENABLE, RK3399_DSI1_ENABLE),
1565
1566                 .flags = DW_MIPI_NEEDS_PHY_CFG_CLK | DW_MIPI_NEEDS_GRF_CLK,
1567                 .max_data_lanes = 4,
1568
1569                 .dphy_rx_init = rk3399_dphy_tx1rx1_init,
1570                 .dphy_rx_power_on = rk3399_dphy_tx1rx1_power_on,
1571                 .dphy_rx_power_off = rk3399_dphy_tx1rx1_power_off,
1572         },
1573         { /* sentinel */ }
1574 };
1575
1576 static const struct of_device_id dw_mipi_dsi_rockchip_dt_ids[] = {
1577         {
1578          .compatible = "rockchip,px30-mipi-dsi",
1579          .data = &px30_chip_data,
1580         }, {
1581          .compatible = "rockchip,rk3288-mipi-dsi",
1582          .data = &rk3288_chip_data,
1583         }, {
1584          .compatible = "rockchip,rk3399-mipi-dsi",
1585          .data = &rk3399_chip_data,
1586         },
1587         { /* sentinel */ }
1588 };
1589 MODULE_DEVICE_TABLE(of, dw_mipi_dsi_rockchip_dt_ids);
1590
1591 struct platform_driver dw_mipi_dsi_rockchip_driver = {
1592         .probe          = dw_mipi_dsi_rockchip_probe,
1593         .remove         = dw_mipi_dsi_rockchip_remove,
1594         .driver         = {
1595                 .of_match_table = dw_mipi_dsi_rockchip_dt_ids,
1596                 .name   = "dw-mipi-dsi-rockchip",
1597         },
1598 };