1 // SPDX-License-Identifier: GPL-2.0+
3 * rcar_du_crtc.c -- R-Car Display Unit CRTCs
5 * Copyright (C) 2013-2015 Renesas Electronics Corporation
7 * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
10 #include <linux/clk.h>
11 #include <linux/mutex.h>
12 #include <linux/platform_device.h>
13 #include <linux/sys_soc.h>
15 #include <drm/drm_atomic.h>
16 #include <drm/drm_atomic_helper.h>
17 #include <drm/drm_bridge.h>
18 #include <drm/drm_crtc.h>
19 #include <drm/drm_device.h>
20 #include <drm/drm_fb_cma_helper.h>
21 #include <drm/drm_gem_cma_helper.h>
22 #include <drm/drm_plane_helper.h>
23 #include <drm/drm_vblank.h>
26 #include "rcar_du_crtc.h"
27 #include "rcar_du_drv.h"
28 #include "rcar_du_encoder.h"
29 #include "rcar_du_kms.h"
30 #include "rcar_du_plane.h"
31 #include "rcar_du_regs.h"
32 #include "rcar_du_vsp.h"
33 #include "rcar_lvds.h"
35 static u32 rcar_du_crtc_read(struct rcar_du_crtc *rcrtc, u32 reg)
37 struct rcar_du_device *rcdu = rcrtc->dev;
39 return rcar_du_read(rcdu, rcrtc->mmio_offset + reg);
42 static void rcar_du_crtc_write(struct rcar_du_crtc *rcrtc, u32 reg, u32 data)
44 struct rcar_du_device *rcdu = rcrtc->dev;
46 rcar_du_write(rcdu, rcrtc->mmio_offset + reg, data);
49 static void rcar_du_crtc_clr(struct rcar_du_crtc *rcrtc, u32 reg, u32 clr)
51 struct rcar_du_device *rcdu = rcrtc->dev;
53 rcar_du_write(rcdu, rcrtc->mmio_offset + reg,
54 rcar_du_read(rcdu, rcrtc->mmio_offset + reg) & ~clr);
57 static void rcar_du_crtc_set(struct rcar_du_crtc *rcrtc, u32 reg, u32 set)
59 struct rcar_du_device *rcdu = rcrtc->dev;
61 rcar_du_write(rcdu, rcrtc->mmio_offset + reg,
62 rcar_du_read(rcdu, rcrtc->mmio_offset + reg) | set);
65 void rcar_du_crtc_dsysr_clr_set(struct rcar_du_crtc *rcrtc, u32 clr, u32 set)
67 struct rcar_du_device *rcdu = rcrtc->dev;
69 rcrtc->dsysr = (rcrtc->dsysr & ~clr) | set;
70 rcar_du_write(rcdu, rcrtc->mmio_offset + DSYSR, rcrtc->dsysr);
73 /* -----------------------------------------------------------------------------
84 static void rcar_du_dpll_divider(struct rcar_du_crtc *rcrtc,
85 struct dpll_info *dpll,
89 unsigned long best_diff = (unsigned long)-1;
96 * fin fvco fout fclkout
97 * in --> [1/M] --> |PD| -> [LPF] -> [VCO] -> [1/P] -+-> [1/FDPLL] -> out
100 * +---------------- [1/N] <------------+
102 * fclkout = fvco / P / FDPLL -- (1)
106 * fvco = fin * P * N / M -- (2)
108 * (1) + (2) indicates
110 * fclkout = fin * N / M / FDPLL
115 * FDPLL : (fdpll + 1)
117 * 2kHz < fvco < 4096MHz
119 * To minimize the jitter,
120 * N : as large as possible
121 * M : as small as possible
123 for (m = 0; m < 4; m++) {
124 for (n = 119; n > 38; n--) {
126 * This code only runs on 64-bit architectures, the
127 * unsigned long type can thus be used for 64-bit
128 * computation. It will still compile without any
129 * warning on 32-bit architectures.
131 * To optimize calculations, use fout instead of fvco
132 * to verify the VCO frequency constraint.
134 unsigned long fout = input * (n + 1) / (m + 1);
136 if (fout < 1000 || fout > 2048 * 1000 * 1000U)
139 for (fdpll = 1; fdpll < 32; fdpll++) {
140 unsigned long output;
142 output = fout / (fdpll + 1);
143 if (output >= 400 * 1000 * 1000)
146 diff = abs((long)output - (long)target);
147 if (best_diff > diff) {
152 dpll->output = output;
162 dev_dbg(rcrtc->dev->dev,
163 "output:%u, fdpll:%u, n:%u, m:%u, diff:%lu\n",
164 dpll->output, dpll->fdpll, dpll->n, dpll->m, best_diff);
167 struct du_clk_params {
174 static void rcar_du_escr_divider(struct clk *clk, unsigned long target,
175 u32 escr, struct du_clk_params *params)
182 * If the target rate has already been achieved perfectly we can't do
185 if (params->diff == 0)
189 * Compute the input clock rate and internal divisor values to obtain
190 * the clock rate closest to the target frequency.
192 rate = clk_round_rate(clk, target);
193 div = clamp(DIV_ROUND_CLOSEST(rate, target), 1UL, 64UL) - 1;
194 diff = abs(rate / (div + 1) - target);
197 * Store the parameters if the resulting frequency is better than any
198 * previously calculated value.
200 if (diff < params->diff) {
204 params->escr = escr | div;
208 static const struct soc_device_attribute rcar_du_r8a7795_es1[] = {
209 { .soc_id = "r8a7795", .revision = "ES1.*" },
213 static void rcar_du_crtc_set_display_timing(struct rcar_du_crtc *rcrtc)
215 const struct drm_display_mode *mode = &rcrtc->crtc.state->adjusted_mode;
216 struct rcar_du_device *rcdu = rcrtc->dev;
217 unsigned long mode_clock = mode->clock * 1000;
221 if (rcdu->info->dpll_mask & (1 << rcrtc->index)) {
222 unsigned long target = mode_clock;
223 struct dpll_info dpll = { 0 };
224 unsigned long extclk;
229 * DU channels that have a display PLL can't use the internal
230 * system clock, and have no internal clock divider.
234 * The H3 ES1.x exhibits dot clock duty cycle stability issues.
235 * We can work around them by configuring the DPLL to twice the
236 * desired frequency, coupled with a /2 post-divider. Restrict
237 * the workaround to H3 ES1.x as ES2.0 and all other SoCs have
238 * no post-divider when a display PLL is present (as shown by
239 * the workaround breaking HDMI output on M3-W during testing).
241 if (soc_device_match(rcar_du_r8a7795_es1)) {
246 extclk = clk_get_rate(rcrtc->extclock);
247 rcar_du_dpll_divider(rcrtc, &dpll, extclk, target);
249 dpllcr = DPLLCR_CODE | DPLLCR_CLKE
250 | DPLLCR_FDPLL(dpll.fdpll)
251 | DPLLCR_N(dpll.n) | DPLLCR_M(dpll.m)
254 if (rcrtc->index == 1)
255 dpllcr |= DPLLCR_PLCS1
256 | DPLLCR_INCS_DOTCLKIN1;
258 dpllcr |= DPLLCR_PLCS0
259 | DPLLCR_INCS_DOTCLKIN0;
261 rcar_du_group_write(rcrtc->group, DPLLCR, dpllcr);
263 escr = ESCR_DCLKSEL_DCLKIN | div;
264 } else if (rcdu->info->lvds_clk_mask & BIT(rcrtc->index)) {
266 * Use the LVDS PLL output as the dot clock when outputting to
267 * the LVDS encoder on an SoC that supports this clock routing
268 * option. We use the clock directly in that case, without any
269 * additional divider.
271 escr = ESCR_DCLKSEL_DCLKIN;
273 struct du_clk_params params = { .diff = (unsigned long)-1 };
275 rcar_du_escr_divider(rcrtc->clock, mode_clock,
276 ESCR_DCLKSEL_CLKS, ¶ms);
278 rcar_du_escr_divider(rcrtc->extclock, mode_clock,
279 ESCR_DCLKSEL_DCLKIN, ¶ms);
281 dev_dbg(rcrtc->dev->dev, "mode clock %lu %s rate %lu\n",
282 mode_clock, params.clk == rcrtc->clock ? "cpg" : "ext",
285 clk_set_rate(params.clk, params.rate);
289 dev_dbg(rcrtc->dev->dev, "%s: ESCR 0x%08x\n", __func__, escr);
291 rcar_du_crtc_write(rcrtc, rcrtc->index % 2 ? ESCR13 : ESCR02, escr);
292 rcar_du_crtc_write(rcrtc, rcrtc->index % 2 ? OTAR13 : OTAR02, 0);
294 /* Signal polarities */
295 dsmr = ((mode->flags & DRM_MODE_FLAG_PVSYNC) ? DSMR_VSL : 0)
296 | ((mode->flags & DRM_MODE_FLAG_PHSYNC) ? DSMR_HSL : 0)
297 | ((mode->flags & DRM_MODE_FLAG_INTERLACE) ? DSMR_ODEV : 0)
298 | DSMR_DIPM_DISP | DSMR_CSPM;
299 rcar_du_crtc_write(rcrtc, DSMR, dsmr);
301 /* Display timings */
302 rcar_du_crtc_write(rcrtc, HDSR, mode->htotal - mode->hsync_start - 19);
303 rcar_du_crtc_write(rcrtc, HDER, mode->htotal - mode->hsync_start +
304 mode->hdisplay - 19);
305 rcar_du_crtc_write(rcrtc, HSWR, mode->hsync_end -
306 mode->hsync_start - 1);
307 rcar_du_crtc_write(rcrtc, HCR, mode->htotal - 1);
309 rcar_du_crtc_write(rcrtc, VDSR, mode->crtc_vtotal -
310 mode->crtc_vsync_end - 2);
311 rcar_du_crtc_write(rcrtc, VDER, mode->crtc_vtotal -
312 mode->crtc_vsync_end +
313 mode->crtc_vdisplay - 2);
314 rcar_du_crtc_write(rcrtc, VSPR, mode->crtc_vtotal -
315 mode->crtc_vsync_end +
316 mode->crtc_vsync_start - 1);
317 rcar_du_crtc_write(rcrtc, VCR, mode->crtc_vtotal - 1);
319 rcar_du_crtc_write(rcrtc, DESR, mode->htotal - mode->hsync_start - 1);
320 rcar_du_crtc_write(rcrtc, DEWR, mode->hdisplay);
323 static unsigned int plane_zpos(struct rcar_du_plane *plane)
325 return plane->plane.state->normalized_zpos;
328 static const struct rcar_du_format_info *
329 plane_format(struct rcar_du_plane *plane)
331 return to_rcar_plane_state(plane->plane.state)->format;
334 static void rcar_du_crtc_update_planes(struct rcar_du_crtc *rcrtc)
336 struct rcar_du_plane *planes[RCAR_DU_NUM_HW_PLANES];
337 struct rcar_du_device *rcdu = rcrtc->dev;
338 unsigned int num_planes = 0;
339 unsigned int dptsr_planes;
340 unsigned int hwplanes = 0;
341 unsigned int prio = 0;
345 for (i = 0; i < rcrtc->group->num_planes; ++i) {
346 struct rcar_du_plane *plane = &rcrtc->group->planes[i];
349 if (plane->plane.state->crtc != &rcrtc->crtc ||
350 !plane->plane.state->visible)
353 /* Insert the plane in the sorted planes array. */
354 for (j = num_planes++; j > 0; --j) {
355 if (plane_zpos(planes[j-1]) <= plane_zpos(plane))
357 planes[j] = planes[j-1];
361 prio += plane_format(plane)->planes * 4;
364 for (i = 0; i < num_planes; ++i) {
365 struct rcar_du_plane *plane = planes[i];
366 struct drm_plane_state *state = plane->plane.state;
367 unsigned int index = to_rcar_plane_state(state)->hwindex;
370 dspr |= (index + 1) << prio;
371 hwplanes |= 1 << index;
373 if (plane_format(plane)->planes == 2) {
374 index = (index + 1) % 8;
377 dspr |= (index + 1) << prio;
378 hwplanes |= 1 << index;
382 /* If VSP+DU integration is enabled the plane assignment is fixed. */
383 if (rcar_du_has(rcdu, RCAR_DU_FEATURE_VSP1_SOURCE)) {
384 if (rcdu->info->gen < 3) {
385 dspr = (rcrtc->index % 2) + 1;
386 hwplanes = 1 << (rcrtc->index % 2);
388 dspr = (rcrtc->index % 2) ? 3 : 1;
389 hwplanes = 1 << ((rcrtc->index % 2) ? 2 : 0);
394 * Update the planes to display timing and dot clock generator
397 * Updating the DPTSR register requires restarting the CRTC group,
398 * resulting in visible flicker. To mitigate the issue only update the
399 * association if needed by enabled planes. Planes being disabled will
400 * keep their current association.
402 mutex_lock(&rcrtc->group->lock);
404 dptsr_planes = rcrtc->index % 2 ? rcrtc->group->dptsr_planes | hwplanes
405 : rcrtc->group->dptsr_planes & ~hwplanes;
407 if (dptsr_planes != rcrtc->group->dptsr_planes) {
408 rcar_du_group_write(rcrtc->group, DPTSR,
409 (dptsr_planes << 16) | dptsr_planes);
410 rcrtc->group->dptsr_planes = dptsr_planes;
412 if (rcrtc->group->used_crtcs)
413 rcar_du_group_restart(rcrtc->group);
416 /* Restart the group if plane sources have changed. */
417 if (rcrtc->group->need_restart)
418 rcar_du_group_restart(rcrtc->group);
420 mutex_unlock(&rcrtc->group->lock);
422 rcar_du_group_write(rcrtc->group, rcrtc->index % 2 ? DS2PR : DS1PR,
426 /* -----------------------------------------------------------------------------
430 void rcar_du_crtc_finish_page_flip(struct rcar_du_crtc *rcrtc)
432 struct drm_pending_vblank_event *event;
433 struct drm_device *dev = rcrtc->crtc.dev;
436 spin_lock_irqsave(&dev->event_lock, flags);
437 event = rcrtc->event;
439 spin_unlock_irqrestore(&dev->event_lock, flags);
444 spin_lock_irqsave(&dev->event_lock, flags);
445 drm_crtc_send_vblank_event(&rcrtc->crtc, event);
446 wake_up(&rcrtc->flip_wait);
447 spin_unlock_irqrestore(&dev->event_lock, flags);
449 drm_crtc_vblank_put(&rcrtc->crtc);
452 static bool rcar_du_crtc_page_flip_pending(struct rcar_du_crtc *rcrtc)
454 struct drm_device *dev = rcrtc->crtc.dev;
458 spin_lock_irqsave(&dev->event_lock, flags);
459 pending = rcrtc->event != NULL;
460 spin_unlock_irqrestore(&dev->event_lock, flags);
465 static void rcar_du_crtc_wait_page_flip(struct rcar_du_crtc *rcrtc)
467 struct rcar_du_device *rcdu = rcrtc->dev;
469 if (wait_event_timeout(rcrtc->flip_wait,
470 !rcar_du_crtc_page_flip_pending(rcrtc),
471 msecs_to_jiffies(50)))
474 dev_warn(rcdu->dev, "page flip timeout\n");
476 rcar_du_crtc_finish_page_flip(rcrtc);
479 /* -----------------------------------------------------------------------------
480 * Color Management Module (CMM)
483 static int rcar_du_cmm_check(struct drm_crtc *crtc,
484 struct drm_crtc_state *state)
486 struct drm_property_blob *drm_lut = state->gamma_lut;
487 struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
488 struct device *dev = rcrtc->dev->dev;
493 /* We only accept fully populated LUT tables. */
494 if (drm_color_lut_size(drm_lut) != CM2_LUT_SIZE) {
495 dev_err(dev, "invalid gamma lut size: %zu bytes\n",
503 static void rcar_du_cmm_setup(struct drm_crtc *crtc)
505 struct drm_property_blob *drm_lut = crtc->state->gamma_lut;
506 struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
507 struct rcar_cmm_config cmm_config = {};
513 cmm_config.lut.table = (struct drm_color_lut *)drm_lut->data;
515 rcar_cmm_setup(rcrtc->cmm, &cmm_config);
518 /* -----------------------------------------------------------------------------
519 * Start/Stop and Suspend/Resume
522 static void rcar_du_crtc_setup(struct rcar_du_crtc *rcrtc)
524 /* Set display off and background to black */
525 rcar_du_crtc_write(rcrtc, DOOR, DOOR_RGB(0, 0, 0));
526 rcar_du_crtc_write(rcrtc, BPOR, BPOR_RGB(0, 0, 0));
528 /* Configure display timings and output routing */
529 rcar_du_crtc_set_display_timing(rcrtc);
530 rcar_du_group_set_routing(rcrtc->group);
532 /* Start with all planes disabled. */
533 rcar_du_group_write(rcrtc->group, rcrtc->index % 2 ? DS2PR : DS1PR, 0);
535 /* Enable the VSP compositor. */
536 if (rcar_du_has(rcrtc->dev, RCAR_DU_FEATURE_VSP1_SOURCE))
537 rcar_du_vsp_enable(rcrtc);
539 /* Turn vertical blanking interrupt reporting on. */
540 drm_crtc_vblank_on(&rcrtc->crtc);
543 static int rcar_du_crtc_get(struct rcar_du_crtc *rcrtc)
548 * Guard against double-get, as the function is called from both the
549 * .atomic_enable() and .atomic_begin() handlers.
551 if (rcrtc->initialized)
554 ret = clk_prepare_enable(rcrtc->clock);
558 ret = clk_prepare_enable(rcrtc->extclock);
562 ret = rcar_du_group_get(rcrtc->group);
566 rcar_du_crtc_setup(rcrtc);
567 rcrtc->initialized = true;
572 clk_disable_unprepare(rcrtc->extclock);
574 clk_disable_unprepare(rcrtc->clock);
578 static void rcar_du_crtc_put(struct rcar_du_crtc *rcrtc)
580 rcar_du_group_put(rcrtc->group);
582 clk_disable_unprepare(rcrtc->extclock);
583 clk_disable_unprepare(rcrtc->clock);
585 rcrtc->initialized = false;
588 static void rcar_du_crtc_start(struct rcar_du_crtc *rcrtc)
593 * Select master sync mode. This enables display operation in master
594 * sync mode (with the HSYNC and VSYNC signals configured as outputs and
597 interlaced = rcrtc->crtc.mode.flags & DRM_MODE_FLAG_INTERLACE;
598 rcar_du_crtc_dsysr_clr_set(rcrtc, DSYSR_TVM_MASK | DSYSR_SCM_MASK,
599 (interlaced ? DSYSR_SCM_INT_VIDEO : 0) |
602 rcar_du_group_start_stop(rcrtc->group, true);
605 static void rcar_du_crtc_disable_planes(struct rcar_du_crtc *rcrtc)
607 struct rcar_du_device *rcdu = rcrtc->dev;
608 struct drm_crtc *crtc = &rcrtc->crtc;
611 /* Make sure vblank interrupts are enabled. */
612 drm_crtc_vblank_get(crtc);
615 * Disable planes and calculate how many vertical blanking interrupts we
616 * have to wait for. If a vertical blanking interrupt has been triggered
617 * but not processed yet, we don't know whether it occurred before or
618 * after the planes got disabled. We thus have to wait for two vblank
619 * interrupts in that case.
621 spin_lock_irq(&rcrtc->vblank_lock);
622 rcar_du_group_write(rcrtc->group, rcrtc->index % 2 ? DS2PR : DS1PR, 0);
623 status = rcar_du_crtc_read(rcrtc, DSSR);
624 rcrtc->vblank_count = status & DSSR_VBK ? 2 : 1;
625 spin_unlock_irq(&rcrtc->vblank_lock);
627 if (!wait_event_timeout(rcrtc->vblank_wait, rcrtc->vblank_count == 0,
628 msecs_to_jiffies(100)))
629 dev_warn(rcdu->dev, "vertical blanking timeout\n");
631 drm_crtc_vblank_put(crtc);
634 static void rcar_du_crtc_stop(struct rcar_du_crtc *rcrtc)
636 struct drm_crtc *crtc = &rcrtc->crtc;
639 * Disable all planes and wait for the change to take effect. This is
640 * required as the plane enable registers are updated on vblank, and no
641 * vblank will occur once the CRTC is stopped. Disabling planes when
642 * starting the CRTC thus wouldn't be enough as it would start scanning
643 * out immediately from old frame buffers until the next vblank.
645 * This increases the CRTC stop delay, especially when multiple CRTCs
646 * are stopped in one operation as we now wait for one vblank per CRTC.
647 * Whether this can be improved needs to be researched.
649 rcar_du_crtc_disable_planes(rcrtc);
652 * Disable vertical blanking interrupt reporting. We first need to wait
653 * for page flip completion before stopping the CRTC as userspace
654 * expects page flips to eventually complete.
656 rcar_du_crtc_wait_page_flip(rcrtc);
657 drm_crtc_vblank_off(crtc);
659 /* Disable the VSP compositor. */
660 if (rcar_du_has(rcrtc->dev, RCAR_DU_FEATURE_VSP1_SOURCE))
661 rcar_du_vsp_disable(rcrtc);
664 rcar_cmm_disable(rcrtc->cmm);
667 * Select switch sync mode. This stops display operation and configures
668 * the HSYNC and VSYNC signals as inputs.
670 * TODO: Find another way to stop the display for DUs that don't support
673 if (rcar_du_has(rcrtc->dev, RCAR_DU_FEATURE_TVM_SYNC))
674 rcar_du_crtc_dsysr_clr_set(rcrtc, DSYSR_TVM_MASK,
677 rcar_du_group_start_stop(rcrtc->group, false);
680 /* -----------------------------------------------------------------------------
684 static int rcar_du_crtc_atomic_check(struct drm_crtc *crtc,
685 struct drm_atomic_state *state)
687 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,
689 struct rcar_du_crtc_state *rstate = to_rcar_crtc_state(crtc_state);
690 struct drm_encoder *encoder;
693 ret = rcar_du_cmm_check(crtc, crtc_state);
697 /* Store the routes from the CRTC output to the DU outputs. */
700 drm_for_each_encoder_mask(encoder, crtc->dev,
701 crtc_state->encoder_mask) {
702 struct rcar_du_encoder *renc;
704 /* Skip the writeback encoder. */
705 if (encoder->encoder_type == DRM_MODE_ENCODER_VIRTUAL)
708 renc = to_rcar_encoder(encoder);
709 rstate->outputs |= BIT(renc->output);
715 static void rcar_du_crtc_atomic_enable(struct drm_crtc *crtc,
716 struct drm_atomic_state *state)
718 struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
719 struct rcar_du_crtc_state *rstate = to_rcar_crtc_state(crtc->state);
720 struct rcar_du_device *rcdu = rcrtc->dev;
723 rcar_cmm_enable(rcrtc->cmm);
724 rcar_du_crtc_get(rcrtc);
727 * On D3/E3 the dot clock is provided by the LVDS encoder attached to
728 * the DU channel. We need to enable its clock output explicitly if
729 * the LVDS output is disabled.
731 if (rcdu->info->lvds_clk_mask & BIT(rcrtc->index) &&
732 rstate->outputs == BIT(RCAR_DU_OUTPUT_DPAD0)) {
733 struct drm_bridge *bridge = rcdu->lvds[rcrtc->index];
734 const struct drm_display_mode *mode =
735 &crtc->state->adjusted_mode;
737 rcar_lvds_clk_enable(bridge, mode->clock * 1000);
740 rcar_du_crtc_start(rcrtc);
743 * TODO: The chip manual indicates that CMM tables should be written
744 * after the DU channel has been activated. Investigate the impact
745 * of this restriction on the first displayed frame.
747 rcar_du_cmm_setup(crtc);
750 static void rcar_du_crtc_atomic_disable(struct drm_crtc *crtc,
751 struct drm_atomic_state *state)
753 struct drm_crtc_state *old_state = drm_atomic_get_old_crtc_state(state,
755 struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
756 struct rcar_du_crtc_state *rstate = to_rcar_crtc_state(old_state);
757 struct rcar_du_device *rcdu = rcrtc->dev;
759 rcar_du_crtc_stop(rcrtc);
760 rcar_du_crtc_put(rcrtc);
762 if (rcdu->info->lvds_clk_mask & BIT(rcrtc->index) &&
763 rstate->outputs == BIT(RCAR_DU_OUTPUT_DPAD0)) {
764 struct drm_bridge *bridge = rcdu->lvds[rcrtc->index];
767 * Disable the LVDS clock output, see
768 * rcar_du_crtc_atomic_enable().
770 rcar_lvds_clk_disable(bridge);
773 spin_lock_irq(&crtc->dev->event_lock);
774 if (crtc->state->event) {
775 drm_crtc_send_vblank_event(crtc, crtc->state->event);
776 crtc->state->event = NULL;
778 spin_unlock_irq(&crtc->dev->event_lock);
781 static void rcar_du_crtc_atomic_begin(struct drm_crtc *crtc,
782 struct drm_atomic_state *state)
784 struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
786 WARN_ON(!crtc->state->enable);
789 * If a mode set is in progress we can be called with the CRTC disabled.
790 * We thus need to first get and setup the CRTC in order to configure
791 * planes. We must *not* put the CRTC in .atomic_flush(), as it must be
792 * kept awake until the .atomic_enable() call that will follow. The get
793 * operation in .atomic_enable() will in that case be a no-op, and the
794 * CRTC will be put later in .atomic_disable().
796 * If a mode set is not in progress the CRTC is enabled, and the
797 * following get call will be a no-op. There is thus no need to balance
798 * it in .atomic_flush() either.
800 rcar_du_crtc_get(rcrtc);
802 /* If the active state changed, we let .atomic_enable handle CMM. */
803 if (crtc->state->color_mgmt_changed && !crtc->state->active_changed)
804 rcar_du_cmm_setup(crtc);
806 if (rcar_du_has(rcrtc->dev, RCAR_DU_FEATURE_VSP1_SOURCE))
807 rcar_du_vsp_atomic_begin(rcrtc);
810 static void rcar_du_crtc_atomic_flush(struct drm_crtc *crtc,
811 struct drm_atomic_state *state)
813 struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
814 struct drm_device *dev = rcrtc->crtc.dev;
817 rcar_du_crtc_update_planes(rcrtc);
819 if (crtc->state->event) {
820 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
822 spin_lock_irqsave(&dev->event_lock, flags);
823 rcrtc->event = crtc->state->event;
824 crtc->state->event = NULL;
825 spin_unlock_irqrestore(&dev->event_lock, flags);
828 if (rcar_du_has(rcrtc->dev, RCAR_DU_FEATURE_VSP1_SOURCE))
829 rcar_du_vsp_atomic_flush(rcrtc);
832 static enum drm_mode_status
833 rcar_du_crtc_mode_valid(struct drm_crtc *crtc,
834 const struct drm_display_mode *mode)
836 struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
837 struct rcar_du_device *rcdu = rcrtc->dev;
838 bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
841 if (interlaced && !rcar_du_has(rcdu, RCAR_DU_FEATURE_INTERLACED))
842 return MODE_NO_INTERLACE;
845 * The hardware requires a minimum combined horizontal sync and back
846 * porch of 20 pixels and a minimum vertical back porch of 3 lines.
848 if (mode->htotal - mode->hsync_start < 20)
849 return MODE_HBLANK_NARROW;
851 vbp = (mode->vtotal - mode->vsync_end) / (interlaced ? 2 : 1);
853 return MODE_VBLANK_NARROW;
858 static const struct drm_crtc_helper_funcs crtc_helper_funcs = {
859 .atomic_check = rcar_du_crtc_atomic_check,
860 .atomic_begin = rcar_du_crtc_atomic_begin,
861 .atomic_flush = rcar_du_crtc_atomic_flush,
862 .atomic_enable = rcar_du_crtc_atomic_enable,
863 .atomic_disable = rcar_du_crtc_atomic_disable,
864 .mode_valid = rcar_du_crtc_mode_valid,
867 static void rcar_du_crtc_crc_init(struct rcar_du_crtc *rcrtc)
869 struct rcar_du_device *rcdu = rcrtc->dev;
870 const char **sources;
874 /* CRC available only on Gen3 HW. */
875 if (rcdu->info->gen < 3)
878 /* Reserve 1 for "auto" source. */
879 count = rcrtc->vsp->num_planes + 1;
881 sources = kmalloc_array(count, sizeof(*sources), GFP_KERNEL);
885 sources[0] = kstrdup("auto", GFP_KERNEL);
889 for (i = 0; i < rcrtc->vsp->num_planes; ++i) {
890 struct drm_plane *plane = &rcrtc->vsp->planes[i].plane;
893 sprintf(name, "plane%u", plane->base.id);
894 sources[i + 1] = kstrdup(name, GFP_KERNEL);
899 rcrtc->sources = sources;
900 rcrtc->sources_count = count;
911 static void rcar_du_crtc_crc_cleanup(struct rcar_du_crtc *rcrtc)
918 for (i = 0; i < rcrtc->sources_count; i++)
919 kfree(rcrtc->sources[i]);
920 kfree(rcrtc->sources);
922 rcrtc->sources = NULL;
923 rcrtc->sources_count = 0;
926 static struct drm_crtc_state *
927 rcar_du_crtc_atomic_duplicate_state(struct drm_crtc *crtc)
929 struct rcar_du_crtc_state *state;
930 struct rcar_du_crtc_state *copy;
932 if (WARN_ON(!crtc->state))
935 state = to_rcar_crtc_state(crtc->state);
936 copy = kmemdup(state, sizeof(*state), GFP_KERNEL);
940 __drm_atomic_helper_crtc_duplicate_state(crtc, ©->state);
945 static void rcar_du_crtc_atomic_destroy_state(struct drm_crtc *crtc,
946 struct drm_crtc_state *state)
948 __drm_atomic_helper_crtc_destroy_state(state);
949 kfree(to_rcar_crtc_state(state));
952 static void rcar_du_crtc_cleanup(struct drm_crtc *crtc)
954 struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
956 rcar_du_crtc_crc_cleanup(rcrtc);
958 return drm_crtc_cleanup(crtc);
961 static void rcar_du_crtc_reset(struct drm_crtc *crtc)
963 struct rcar_du_crtc_state *state;
966 rcar_du_crtc_atomic_destroy_state(crtc, crtc->state);
970 state = kzalloc(sizeof(*state), GFP_KERNEL);
974 state->crc.source = VSP1_DU_CRC_NONE;
975 state->crc.index = 0;
977 __drm_atomic_helper_crtc_reset(crtc, &state->state);
980 static int rcar_du_crtc_enable_vblank(struct drm_crtc *crtc)
982 struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
984 rcar_du_crtc_write(rcrtc, DSRCR, DSRCR_VBCL);
985 rcar_du_crtc_set(rcrtc, DIER, DIER_VBE);
986 rcrtc->vblank_enable = true;
991 static void rcar_du_crtc_disable_vblank(struct drm_crtc *crtc)
993 struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
995 rcar_du_crtc_clr(rcrtc, DIER, DIER_VBE);
996 rcrtc->vblank_enable = false;
999 static int rcar_du_crtc_parse_crc_source(struct rcar_du_crtc *rcrtc,
1000 const char *source_name,
1001 enum vsp1_du_crc_source *source)
1007 * Parse the source name. Supported values are "plane%u" to compute the
1008 * CRC on an input plane (%u is the plane ID), and "auto" to compute the
1009 * CRC on the composer (VSP) output.
1013 *source = VSP1_DU_CRC_NONE;
1015 } else if (!strcmp(source_name, "auto")) {
1016 *source = VSP1_DU_CRC_OUTPUT;
1018 } else if (strstarts(source_name, "plane")) {
1021 *source = VSP1_DU_CRC_PLANE;
1023 ret = kstrtouint(source_name + strlen("plane"), 10, &index);
1027 for (i = 0; i < rcrtc->vsp->num_planes; ++i) {
1028 if (index == rcrtc->vsp->planes[i].plane.base.id)
1036 static int rcar_du_crtc_verify_crc_source(struct drm_crtc *crtc,
1037 const char *source_name,
1040 struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
1041 enum vsp1_du_crc_source source;
1043 if (rcar_du_crtc_parse_crc_source(rcrtc, source_name, &source) < 0) {
1044 DRM_DEBUG_DRIVER("unknown source %s\n", source_name);
1052 static const char *const *
1053 rcar_du_crtc_get_crc_sources(struct drm_crtc *crtc, size_t *count)
1055 struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
1057 *count = rcrtc->sources_count;
1058 return rcrtc->sources;
1061 static int rcar_du_crtc_set_crc_source(struct drm_crtc *crtc,
1062 const char *source_name)
1064 struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
1065 struct drm_modeset_acquire_ctx ctx;
1066 struct drm_crtc_state *crtc_state;
1067 struct drm_atomic_state *state;
1068 enum vsp1_du_crc_source source;
1072 ret = rcar_du_crtc_parse_crc_source(rcrtc, source_name, &source);
1078 /* Perform an atomic commit to set the CRC source. */
1079 drm_modeset_acquire_init(&ctx, 0);
1081 state = drm_atomic_state_alloc(crtc->dev);
1087 state->acquire_ctx = &ctx;
1090 crtc_state = drm_atomic_get_crtc_state(state, crtc);
1091 if (!IS_ERR(crtc_state)) {
1092 struct rcar_du_crtc_state *rcrtc_state;
1094 rcrtc_state = to_rcar_crtc_state(crtc_state);
1095 rcrtc_state->crc.source = source;
1096 rcrtc_state->crc.index = index;
1098 ret = drm_atomic_commit(state);
1100 ret = PTR_ERR(crtc_state);
1103 if (ret == -EDEADLK) {
1104 drm_atomic_state_clear(state);
1105 drm_modeset_backoff(&ctx);
1109 drm_atomic_state_put(state);
1112 drm_modeset_drop_locks(&ctx);
1113 drm_modeset_acquire_fini(&ctx);
1118 static const struct drm_crtc_funcs crtc_funcs_gen2 = {
1119 .reset = rcar_du_crtc_reset,
1120 .destroy = drm_crtc_cleanup,
1121 .set_config = drm_atomic_helper_set_config,
1122 .page_flip = drm_atomic_helper_page_flip,
1123 .atomic_duplicate_state = rcar_du_crtc_atomic_duplicate_state,
1124 .atomic_destroy_state = rcar_du_crtc_atomic_destroy_state,
1125 .enable_vblank = rcar_du_crtc_enable_vblank,
1126 .disable_vblank = rcar_du_crtc_disable_vblank,
1129 static const struct drm_crtc_funcs crtc_funcs_gen3 = {
1130 .reset = rcar_du_crtc_reset,
1131 .destroy = rcar_du_crtc_cleanup,
1132 .set_config = drm_atomic_helper_set_config,
1133 .page_flip = drm_atomic_helper_page_flip,
1134 .atomic_duplicate_state = rcar_du_crtc_atomic_duplicate_state,
1135 .atomic_destroy_state = rcar_du_crtc_atomic_destroy_state,
1136 .enable_vblank = rcar_du_crtc_enable_vblank,
1137 .disable_vblank = rcar_du_crtc_disable_vblank,
1138 .set_crc_source = rcar_du_crtc_set_crc_source,
1139 .verify_crc_source = rcar_du_crtc_verify_crc_source,
1140 .get_crc_sources = rcar_du_crtc_get_crc_sources,
1143 /* -----------------------------------------------------------------------------
1144 * Interrupt Handling
1147 static irqreturn_t rcar_du_crtc_irq(int irq, void *arg)
1149 struct rcar_du_crtc *rcrtc = arg;
1150 struct rcar_du_device *rcdu = rcrtc->dev;
1151 irqreturn_t ret = IRQ_NONE;
1154 spin_lock(&rcrtc->vblank_lock);
1156 status = rcar_du_crtc_read(rcrtc, DSSR);
1157 rcar_du_crtc_write(rcrtc, DSRCR, status & DSRCR_MASK);
1159 if (status & DSSR_VBK) {
1161 * Wake up the vblank wait if the counter reaches 0. This must
1162 * be protected by the vblank_lock to avoid races in
1163 * rcar_du_crtc_disable_planes().
1165 if (rcrtc->vblank_count) {
1166 if (--rcrtc->vblank_count == 0)
1167 wake_up(&rcrtc->vblank_wait);
1171 spin_unlock(&rcrtc->vblank_lock);
1173 if (status & DSSR_VBK) {
1174 if (rcdu->info->gen < 3) {
1175 drm_crtc_handle_vblank(&rcrtc->crtc);
1176 rcar_du_crtc_finish_page_flip(rcrtc);
1185 /* -----------------------------------------------------------------------------
1189 int rcar_du_crtc_create(struct rcar_du_group *rgrp, unsigned int swindex,
1190 unsigned int hwindex)
1192 static const unsigned int mmio_offsets[] = {
1193 DU0_REG_OFFSET, DU1_REG_OFFSET, DU2_REG_OFFSET, DU3_REG_OFFSET
1196 struct rcar_du_device *rcdu = rgrp->dev;
1197 struct platform_device *pdev = to_platform_device(rcdu->dev);
1198 struct rcar_du_crtc *rcrtc = &rcdu->crtcs[swindex];
1199 struct drm_crtc *crtc = &rcrtc->crtc;
1200 struct drm_plane *primary;
1201 unsigned int irqflags;
1208 /* Get the CRTC clock and the optional external clock. */
1209 if (rcar_du_has(rcdu, RCAR_DU_FEATURE_CRTC_IRQ_CLOCK)) {
1210 sprintf(clk_name, "du.%u", hwindex);
1216 rcrtc->clock = devm_clk_get(rcdu->dev, name);
1217 if (IS_ERR(rcrtc->clock)) {
1218 dev_err(rcdu->dev, "no clock for DU channel %u\n", hwindex);
1219 return PTR_ERR(rcrtc->clock);
1222 sprintf(clk_name, "dclkin.%u", hwindex);
1223 clk = devm_clk_get(rcdu->dev, clk_name);
1225 rcrtc->extclock = clk;
1226 } else if (PTR_ERR(clk) == -EPROBE_DEFER) {
1227 return -EPROBE_DEFER;
1228 } else if (rcdu->info->dpll_mask & BIT(hwindex)) {
1230 * DU channels that have a display PLL can't use the internal
1231 * system clock and thus require an external clock.
1234 dev_err(rcdu->dev, "can't get dclkin.%u: %d\n", hwindex, ret);
1238 init_waitqueue_head(&rcrtc->flip_wait);
1239 init_waitqueue_head(&rcrtc->vblank_wait);
1240 spin_lock_init(&rcrtc->vblank_lock);
1243 rcrtc->group = rgrp;
1244 rcrtc->mmio_offset = mmio_offsets[hwindex];
1245 rcrtc->index = hwindex;
1246 rcrtc->dsysr = (rcrtc->index % 2 ? 0 : DSYSR_DRES) | DSYSR_TVM_TVSYNC;
1248 if (rcar_du_has(rcdu, RCAR_DU_FEATURE_VSP1_SOURCE))
1249 primary = &rcrtc->vsp->planes[rcrtc->vsp_pipe].plane;
1251 primary = &rgrp->planes[swindex % 2].plane;
1253 ret = drm_crtc_init_with_planes(&rcdu->ddev, crtc, primary, NULL,
1254 rcdu->info->gen <= 2 ?
1255 &crtc_funcs_gen2 : &crtc_funcs_gen3,
1260 /* CMM might be disabled for this CRTC. */
1261 if (rcdu->cmms[swindex]) {
1262 rcrtc->cmm = rcdu->cmms[swindex];
1263 rgrp->cmms_mask |= BIT(hwindex % 2);
1265 drm_mode_crtc_set_gamma_size(crtc, CM2_LUT_SIZE);
1266 drm_crtc_enable_color_mgmt(crtc, 0, false, CM2_LUT_SIZE);
1269 drm_crtc_helper_add(crtc, &crtc_helper_funcs);
1271 /* Register the interrupt handler. */
1272 if (rcar_du_has(rcdu, RCAR_DU_FEATURE_CRTC_IRQ_CLOCK)) {
1273 /* The IRQ's are associated with the CRTC (sw)index. */
1274 irq = platform_get_irq(pdev, swindex);
1277 irq = platform_get_irq(pdev, 0);
1278 irqflags = IRQF_SHARED;
1282 dev_err(rcdu->dev, "no IRQ for CRTC %u\n", swindex);
1286 ret = devm_request_irq(rcdu->dev, irq, rcar_du_crtc_irq, irqflags,
1287 dev_name(rcdu->dev), rcrtc);
1290 "failed to register IRQ for CRTC %u\n", swindex);
1294 rcar_du_crtc_crc_init(rcrtc);