drivers/gpu/drm/rcar-du/rcar_du_crtc.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * rcar_du_crtc.c  --  R-Car Display Unit CRTCs
   4  *
   5  * Copyright (C) 2013-2015 Renesas Electronics Corporation
   6  *
   7  * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
   8  */
   9
  10 #include <linux/clk.h>
  11 #include <linux/mutex.h>
  12 #include <linux/sys_soc.h>
  13
  14 #include <drm/drmP.h>
  15 #include <drm/drm_atomic.h>
  16 #include <drm/drm_atomic_helper.h>
  17 #include <drm/drm_crtc.h>
  18 #include <drm/drm_crtc_helper.h>
  19 #include <drm/drm_fb_cma_helper.h>
  20 #include <drm/drm_gem_cma_helper.h>
  21 #include <drm/drm_plane_helper.h>
  22
  23 #include "rcar_du_crtc.h"
  24 #include "rcar_du_drv.h"
  25 #include "rcar_du_kms.h"
  26 #include "rcar_du_plane.h"
  27 #include "rcar_du_regs.h"
  28 #include "rcar_du_vsp.h"
  29
  30 static u32 rcar_du_crtc_read(struct rcar_du_crtc *rcrtc, u32 reg)
  31 {
  32         struct rcar_du_device *rcdu = rcrtc->group->dev;
  33
  34         return rcar_du_read(rcdu, rcrtc->mmio_offset + reg);
  35 }
  36
  37 static void rcar_du_crtc_write(struct rcar_du_crtc *rcrtc, u32 reg, u32 data)
  38 {
  39         struct rcar_du_device *rcdu = rcrtc->group->dev;
  40
  41         rcar_du_write(rcdu, rcrtc->mmio_offset + reg, data);
  42 }
  43
  44 static void rcar_du_crtc_clr(struct rcar_du_crtc *rcrtc, u32 reg, u32 clr)
  45 {
  46         struct rcar_du_device *rcdu = rcrtc->group->dev;
  47
  48         rcar_du_write(rcdu, rcrtc->mmio_offset + reg,
  49                       rcar_du_read(rcdu, rcrtc->mmio_offset + reg) & ~clr);
  50 }
  51
  52 static void rcar_du_crtc_set(struct rcar_du_crtc *rcrtc, u32 reg, u32 set)
  53 {
  54         struct rcar_du_device *rcdu = rcrtc->group->dev;
  55
  56         rcar_du_write(rcdu, rcrtc->mmio_offset + reg,
  57                       rcar_du_read(rcdu, rcrtc->mmio_offset + reg) | set);
  58 }
  59
  60 static void rcar_du_crtc_clr_set(struct rcar_du_crtc *rcrtc, u32 reg,
  61                                  u32 clr, u32 set)
  62 {
  63         struct rcar_du_device *rcdu = rcrtc->group->dev;
  64         u32 value = rcar_du_read(rcdu, rcrtc->mmio_offset + reg);
  65
  66         rcar_du_write(rcdu, rcrtc->mmio_offset + reg, (value & ~clr) | set);
  67 }
  68
  69 /* -----------------------------------------------------------------------------
  70  * Hardware Setup
  71  */
  72
  73 struct dpll_info {
  74         unsigned int output;
  75         unsigned int fdpll;
  76         unsigned int n;
  77         unsigned int m;
  78 };
  79
  80 static void rcar_du_dpll_divider(struct rcar_du_crtc *rcrtc,
  81                                  struct dpll_info *dpll,
  82                                  unsigned long input,
  83                                  unsigned long target)
  84 {
  85         unsigned long best_diff = (unsigned long)-1;
  86         unsigned long diff;
  87         unsigned int fdpll;
  88         unsigned int m;
  89         unsigned int n;
  90
  91         /*
  92          *   fin                                 fvco        fout       fclkout
  93          * in --> [1/M] --> |PD| -> [LPF] -> [VCO] -> [1/P] -+-> [1/FDPLL] -> out
  94          *              +-> |  |                             |
  95          *              |                                    |
  96          *              +---------------- [1/N] <------------+
  97          *
  98          *      fclkout = fvco / P / FDPLL -- (1)
  99          *
 100          * fin/M = fvco/P/N
 101          *
 102          *      fvco = fin * P *  N / M -- (2)
 103          *
 104          * (1) + (2) indicates
 105          *
 106          *      fclkout = fin * N / M / FDPLL
 107          *
 108          * NOTES
 109          *      N       : (n + 1)
 110          *      M       : (m + 1)
 111          *      FDPLL   : (fdpll + 1)
 112          *      P       : 2
 113          *      2kHz < fvco < 4096MHz
 114          *
 115          * To minimize the jitter,
 116          * N : as large as possible
 117          * M : as small as possible
 118          */
 119         for (m = 0; m < 4; m++) {
 120                 for (n = 119; n > 38; n--) {
 121                         /*
 122                          * This code only runs on 64-bit architectures, the
 123                          * unsigned long type can thus be used for 64-bit
 124                          * computation. It will still compile without any
 125                          * warning on 32-bit architectures.
 126                          *
 127                          * To optimize calculations, use fout instead of fvco
 128                          * to verify the VCO frequency constraint.
 129                          */
 130                         unsigned long fout = input * (n + 1) / (m + 1);
 131
 132                         if (fout < 1000 || fout > 2048 * 1000 * 1000U)
 133                                 continue;
 134
 135                         for (fdpll = 1; fdpll < 32; fdpll++) {
 136                                 unsigned long output;
 137
 138                                 output = fout / (fdpll + 1);
 139                                 if (output >= 400 * 1000 * 1000)
 140                                         continue;
 141
 142                                 diff = abs((long)output - (long)target);
 143                                 if (best_diff > diff) {
 144                                         best_diff = diff;
 145                                         dpll->n = n;
 146                                         dpll->m = m;
 147                                         dpll->fdpll = fdpll;
 148                                         dpll->output = output;
 149                                 }
 150
 151                                 if (diff == 0)
 152                                         goto done;
 153                         }
 154                 }
 155         }
 156
 157 done:
 158         dev_dbg(rcrtc->group->dev->dev,
 159                 "output:%u, fdpll:%u, n:%u, m:%u, diff:%lu\n",
 160                  dpll->output, dpll->fdpll, dpll->n, dpll->m,
 161                  best_diff);
 162 }
 163
 164 struct du_clk_params {
 165         struct clk *clk;
 166         unsigned long rate;
 167         unsigned long diff;
 168         u32 escr;
 169 };
 170
 171 static void rcar_du_escr_divider(struct clk *clk, unsigned long target,
 172                                  u32 escr, struct du_clk_params *params)
 173 {
 174         unsigned long rate;
 175         unsigned long diff;
 176         u32 div;
 177
 178         /*
 179          * If the target rate has already been achieved perfectly we can't do
 180          * better.
 181          */
 182         if (params->diff == 0)
 183                 return;
 184
 185         /*
 186          * Compute the input clock rate and internal divisor values to obtain
 187          * the clock rate closest to the target frequency.
 188          */
 189         rate = clk_round_rate(clk, target);
 190         div = clamp(DIV_ROUND_CLOSEST(rate, target), 1UL, 64UL) - 1;
 191         diff = abs(rate / (div + 1) - target);
 192
 193         /*
 194          * Store the parameters if the resulting frequency is better than any
 195          * previously calculated value.
 196          */
 197         if (diff < params->diff) {
 198                 params->clk = clk;
 199                 params->rate = rate;
 200                 params->diff = diff;
 201                 params->escr = escr | div;
 202         }
 203 }
 204
 205 static const struct soc_device_attribute rcar_du_r8a7795_es1[] = {
 206         { .soc_id = "r8a7795", .revision = "ES1.*" },
 207         { /* sentinel */ }
 208 };
 209
 210 static void rcar_du_crtc_set_display_timing(struct rcar_du_crtc *rcrtc)
 211 {
 212         const struct drm_display_mode *mode = &rcrtc->crtc.state->adjusted_mode;
 213         struct rcar_du_device *rcdu = rcrtc->group->dev;
 214         unsigned long mode_clock = mode->clock * 1000;
 215         u32 dsmr;
 216         u32 escr;
 217
 218         if (rcdu->info->dpll_mask & (1 << rcrtc->index)) {
 219                 unsigned long target = mode_clock;
 220                 struct dpll_info dpll = { 0 };
 221                 unsigned long extclk;
 222                 u32 dpllcr;
 223                 u32 div = 0;
 224
 225                 /*
 226                  * DU channels that have a display PLL can't use the internal
 227                  * system clock, and have no internal clock divider.
 228                  */
 229
 230                 if (WARN_ON(!rcrtc->extclock))
 231                         return;
 232
 233                 /*
 234                  * The H3 ES1.x exhibits dot clock duty cycle stability issues.
 235                  * We can work around them by configuring the DPLL to twice the
 236                  * desired frequency, coupled with a /2 post-divider. Restrict
 237                  * the workaround to H3 ES1.x as ES2.0 and all other SoCs have
 238                  * no post-divider when a display PLL is present (as shown by
 239                  * the workaround breaking HDMI output on M3-W during testing).
 240                  */
 241                 if (soc_device_match(rcar_du_r8a7795_es1)) {
 242                         target *= 2;
 243                         div = 1;
 244                 }
 245
 246                 extclk = clk_get_rate(rcrtc->extclock);
 247                 rcar_du_dpll_divider(rcrtc, &dpll, extclk, target);
 248
 249                 dpllcr = DPLLCR_CODE | DPLLCR_CLKE
 250                        | DPLLCR_FDPLL(dpll.fdpll)
 251                        | DPLLCR_N(dpll.n) | DPLLCR_M(dpll.m)
 252                        | DPLLCR_STBY;
 253
 254                 if (rcrtc->index == 1)
 255                         dpllcr |= DPLLCR_PLCS1
 256                                |  DPLLCR_INCS_DOTCLKIN1;
 257                 else
 258                         dpllcr |= DPLLCR_PLCS0
 259                                |  DPLLCR_INCS_DOTCLKIN0;
 260
 261                 rcar_du_group_write(rcrtc->group, DPLLCR, dpllcr);
 262
 263                 escr = ESCR_DCLKSEL_DCLKIN | div;
 264         } else if (rcdu->info->lvds_clk_mask & BIT(rcrtc->index)) {
 265                 /*
 266                  * Use the LVDS PLL output as the dot clock when outputting to
 267                  * the LVDS encoder on an SoC that supports this clock routing
 268                  * option. We use the clock directly in that case, without any
 269                  * additional divider.
 270                  */
 271                 escr = ESCR_DCLKSEL_DCLKIN;
 272         } else {
 273                 struct du_clk_params params = { .diff = (unsigned long)-1 };
 274
 275                 rcar_du_escr_divider(rcrtc->clock, mode_clock,
 276                                      ESCR_DCLKSEL_CLKS, &params);
 277                 if (rcrtc->extclock)
 278                         rcar_du_escr_divider(rcrtc->extclock, mode_clock,
 279                                              ESCR_DCLKSEL_DCLKIN, &params);
 280
 281                 dev_dbg(rcrtc->group->dev->dev, "mode clock %lu %s rate %lu\n",
 282                         mode_clock, params.clk == rcrtc->clock ? "cpg" : "ext",
 283                         params.rate);
 284
 285                 clk_set_rate(params.clk, params.rate);
 286                 escr = params.escr;
 287         }
 288
 289         dev_dbg(rcrtc->group->dev->dev, "%s: ESCR 0x%08x\n", __func__, escr);
 290
 291         rcar_du_crtc_write(rcrtc, rcrtc->index % 2 ? ESCR13 : ESCR02, escr);
 292         rcar_du_crtc_write(rcrtc, rcrtc->index % 2 ? OTAR13 : OTAR02, 0);
 293
 294         /* Signal polarities */
 295         dsmr = ((mode->flags & DRM_MODE_FLAG_PVSYNC) ? DSMR_VSL : 0)
 296              | ((mode->flags & DRM_MODE_FLAG_PHSYNC) ? DSMR_HSL : 0)
 297              | ((mode->flags & DRM_MODE_FLAG_INTERLACE) ? DSMR_ODEV : 0)
 298              | DSMR_DIPM_DISP | DSMR_CSPM;
 299         rcar_du_crtc_write(rcrtc, DSMR, dsmr);
 300
 301         /* Display timings */
 302         rcar_du_crtc_write(rcrtc, HDSR, mode->htotal - mode->hsync_start - 19);
 303         rcar_du_crtc_write(rcrtc, HDER, mode->htotal - mode->hsync_start +
 304                                         mode->hdisplay - 19);
 305         rcar_du_crtc_write(rcrtc, HSWR, mode->hsync_end -
 306                                         mode->hsync_start - 1);
 307         rcar_du_crtc_write(rcrtc, HCR,  mode->htotal - 1);
 308
 309         rcar_du_crtc_write(rcrtc, VDSR, mode->crtc_vtotal -
 310                                         mode->crtc_vsync_end - 2);
 311         rcar_du_crtc_write(rcrtc, VDER, mode->crtc_vtotal -
 312                                         mode->crtc_vsync_end +
 313                                         mode->crtc_vdisplay - 2);
 314         rcar_du_crtc_write(rcrtc, VSPR, mode->crtc_vtotal -
 315                                         mode->crtc_vsync_end +
 316                                         mode->crtc_vsync_start - 1);
 317         rcar_du_crtc_write(rcrtc, VCR,  mode->crtc_vtotal - 1);
 318
 319         rcar_du_crtc_write(rcrtc, DESR,  mode->htotal - mode->hsync_start - 1);
 320         rcar_du_crtc_write(rcrtc, DEWR,  mode->hdisplay);
 321 }
 322
 323 void rcar_du_crtc_route_output(struct drm_crtc *crtc,
 324                                enum rcar_du_output output)
 325 {
 326         struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
 327         struct rcar_du_device *rcdu = rcrtc->group->dev;
 328
 329         /*
 330          * Store the route from the CRTC output to the DU output. The DU will be
 331          * configured when starting the CRTC.
 332          */
 333         rcrtc->outputs |= BIT(output);
 334
 335         /*
 336          * Store RGB routing to DPAD0, the hardware will be configured when
 337          * starting the CRTC.
 338          */
 339         if (output == RCAR_DU_OUTPUT_DPAD0)
 340                 rcdu->dpad0_source = rcrtc->index;
 341 }
 342
 343 static unsigned int plane_zpos(struct rcar_du_plane *plane)
 344 {
 345         return plane->plane.state->normalized_zpos;
 346 }
 347
 348 static const struct rcar_du_format_info *
 349 plane_format(struct rcar_du_plane *plane)
 350 {
 351         return to_rcar_plane_state(plane->plane.state)->format;
 352 }
 353
 354 static void rcar_du_crtc_update_planes(struct rcar_du_crtc *rcrtc)
 355 {
 356         struct rcar_du_plane *planes[RCAR_DU_NUM_HW_PLANES];
 357         struct rcar_du_device *rcdu = rcrtc->group->dev;
 358         unsigned int num_planes = 0;
 359         unsigned int dptsr_planes;
 360         unsigned int hwplanes = 0;
 361         unsigned int prio = 0;
 362         unsigned int i;
 363         u32 dspr = 0;
 364
 365         for (i = 0; i < rcrtc->group->num_planes; ++i) {
 366                 struct rcar_du_plane *plane = &rcrtc->group->planes[i];
 367                 unsigned int j;
 368
 369                 if (plane->plane.state->crtc != &rcrtc->crtc ||
 370                     !plane->plane.state->visible)
 371                         continue;
 372
 373                 /* Insert the plane in the sorted planes array. */
 374                 for (j = num_planes++; j > 0; --j) {
 375                         if (plane_zpos(planes[j-1]) <= plane_zpos(plane))
 376                                 break;
 377                         planes[j] = planes[j-1];
 378                 }
 379
 380                 planes[j] = plane;
 381                 prio += plane_format(plane)->planes * 4;
 382         }
 383
 384         for (i = 0; i < num_planes; ++i) {
 385                 struct rcar_du_plane *plane = planes[i];
 386                 struct drm_plane_state *state = plane->plane.state;
 387                 unsigned int index = to_rcar_plane_state(state)->hwindex;
 388
 389                 prio -= 4;
 390                 dspr |= (index + 1) << prio;
 391                 hwplanes |= 1 << index;
 392
 393                 if (plane_format(plane)->planes == 2) {
 394                         index = (index + 1) % 8;
 395
 396                         prio -= 4;
 397                         dspr |= (index + 1) << prio;
 398                         hwplanes |= 1 << index;
 399                 }
 400         }
 401
 402         /* If VSP+DU integration is enabled the plane assignment is fixed. */
 403         if (rcar_du_has(rcdu, RCAR_DU_FEATURE_VSP1_SOURCE)) {
 404                 if (rcdu->info->gen < 3) {
 405                         dspr = (rcrtc->index % 2) + 1;
 406                         hwplanes = 1 << (rcrtc->index % 2);
 407                 } else {
 408                         dspr = (rcrtc->index % 2) ? 3 : 1;
 409                         hwplanes = 1 << ((rcrtc->index % 2) ? 2 : 0);
 410                 }
 411         }
 412
 413         /*
 414          * Update the planes to display timing and dot clock generator
 415          * associations.
 416          *
 417          * Updating the DPTSR register requires restarting the CRTC group,
 418          * resulting in visible flicker. To mitigate the issue only update the
 419          * association if needed by enabled planes. Planes being disabled will
 420          * keep their current association.
 421          */
 422         mutex_lock(&rcrtc->group->lock);
 423
 424         dptsr_planes = rcrtc->index % 2 ? rcrtc->group->dptsr_planes | hwplanes
 425                      : rcrtc->group->dptsr_planes & ~hwplanes;
 426
 427         if (dptsr_planes != rcrtc->group->dptsr_planes) {
 428                 rcar_du_group_write(rcrtc->group, DPTSR,
 429                                     (dptsr_planes << 16) | dptsr_planes);
 430                 rcrtc->group->dptsr_planes = dptsr_planes;
 431
 432                 if (rcrtc->group->used_crtcs)
 433                         rcar_du_group_restart(rcrtc->group);
 434         }
 435
 436         /* Restart the group if plane sources have changed. */
 437         if (rcrtc->group->need_restart)
 438                 rcar_du_group_restart(rcrtc->group);
 439
 440         mutex_unlock(&rcrtc->group->lock);
 441
 442         rcar_du_group_write(rcrtc->group, rcrtc->index % 2 ? DS2PR : DS1PR,
 443                             dspr);
 444 }
 445
 446 /* -----------------------------------------------------------------------------
 447  * Page Flip
 448  */
 449
 450 void rcar_du_crtc_finish_page_flip(struct rcar_du_crtc *rcrtc)
 451 {
 452         struct drm_pending_vblank_event *event;
 453         struct drm_device *dev = rcrtc->crtc.dev;
 454         unsigned long flags;
 455
 456         spin_lock_irqsave(&dev->event_lock, flags);
 457         event = rcrtc->event;
 458         rcrtc->event = NULL;
 459         spin_unlock_irqrestore(&dev->event_lock, flags);
 460
 461         if (event == NULL)
 462                 return;
 463
 464         spin_lock_irqsave(&dev->event_lock, flags);
 465         drm_crtc_send_vblank_event(&rcrtc->crtc, event);
 466         wake_up(&rcrtc->flip_wait);
 467         spin_unlock_irqrestore(&dev->event_lock, flags);
 468
 469         drm_crtc_vblank_put(&rcrtc->crtc);
 470 }
 471
 472 static bool rcar_du_crtc_page_flip_pending(struct rcar_du_crtc *rcrtc)
 473 {
 474         struct drm_device *dev = rcrtc->crtc.dev;
 475         unsigned long flags;
 476         bool pending;
 477
 478         spin_lock_irqsave(&dev->event_lock, flags);
 479         pending = rcrtc->event != NULL;
 480         spin_unlock_irqrestore(&dev->event_lock, flags);
 481
 482         return pending;
 483 }
 484
 485 static void rcar_du_crtc_wait_page_flip(struct rcar_du_crtc *rcrtc)
 486 {
 487         struct rcar_du_device *rcdu = rcrtc->group->dev;
 488
 489         if (wait_event_timeout(rcrtc->flip_wait,
 490                                !rcar_du_crtc_page_flip_pending(rcrtc),
 491                                msecs_to_jiffies(50)))
 492                 return;
 493
 494         dev_warn(rcdu->dev, "page flip timeout\n");
 495
 496         rcar_du_crtc_finish_page_flip(rcrtc);
 497 }
 498
 499 /* -----------------------------------------------------------------------------
 500  * Start/Stop and Suspend/Resume
 501  */
 502
 503 static void rcar_du_crtc_setup(struct rcar_du_crtc *rcrtc)
 504 {
 505         /* Set display off and background to black */
 506         rcar_du_crtc_write(rcrtc, DOOR, DOOR_RGB(0, 0, 0));
 507         rcar_du_crtc_write(rcrtc, BPOR, BPOR_RGB(0, 0, 0));
 508
 509         /* Configure display timings and output routing */
 510         rcar_du_crtc_set_display_timing(rcrtc);
 511         rcar_du_group_set_routing(rcrtc->group);
 512
 513         /* Start with all planes disabled. */
 514         rcar_du_group_write(rcrtc->group, rcrtc->index % 2 ? DS2PR : DS1PR, 0);
 515
 516         /* Enable the VSP compositor. */
 517         if (rcar_du_has(rcrtc->group->dev, RCAR_DU_FEATURE_VSP1_SOURCE))
 518                 rcar_du_vsp_enable(rcrtc);
 519
 520         /* Turn vertical blanking interrupt reporting on. */
 521         drm_crtc_vblank_on(&rcrtc->crtc);
 522 }
 523
 524 static int rcar_du_crtc_get(struct rcar_du_crtc *rcrtc)
 525 {
 526         int ret;
 527
 528         /*
 529          * Guard against double-get, as the function is called from both the
 530          * .atomic_enable() and .atomic_begin() handlers.
 531          */
 532         if (rcrtc->initialized)
 533                 return 0;
 534
 535         ret = clk_prepare_enable(rcrtc->clock);
 536         if (ret < 0)
 537                 return ret;
 538
 539         ret = clk_prepare_enable(rcrtc->extclock);
 540         if (ret < 0)
 541                 goto error_clock;
 542
 543         ret = rcar_du_group_get(rcrtc->group);
 544         if (ret < 0)
 545                 goto error_group;
 546
 547         rcar_du_crtc_setup(rcrtc);
 548         rcrtc->initialized = true;
 549
 550         return 0;
 551
 552 error_group:
 553         clk_disable_unprepare(rcrtc->extclock);
 554 error_clock:
 555         clk_disable_unprepare(rcrtc->clock);
 556         return ret;
 557 }
 558
 559 static void rcar_du_crtc_put(struct rcar_du_crtc *rcrtc)
 560 {
 561         rcar_du_group_put(rcrtc->group);
 562
 563         clk_disable_unprepare(rcrtc->extclock);
 564         clk_disable_unprepare(rcrtc->clock);
 565
 566         rcrtc->initialized = false;
 567 }
 568
 569 static void rcar_du_crtc_start(struct rcar_du_crtc *rcrtc)
 570 {
 571         bool interlaced;
 572
 573         /*
 574          * Select master sync mode. This enables display operation in master
 575          * sync mode (with the HSYNC and VSYNC signals configured as outputs and
 576          * actively driven).
 577          */
 578         interlaced = rcrtc->crtc.mode.flags & DRM_MODE_FLAG_INTERLACE;
 579         rcar_du_crtc_clr_set(rcrtc, DSYSR, DSYSR_TVM_MASK | DSYSR_SCM_MASK,
 580                              (interlaced ? DSYSR_SCM_INT_VIDEO : 0) |
 581                              DSYSR_TVM_MASTER);
 582
 583         rcar_du_group_start_stop(rcrtc->group, true);
 584 }
 585
 586 static void rcar_du_crtc_disable_planes(struct rcar_du_crtc *rcrtc)
 587 {
 588         struct rcar_du_device *rcdu = rcrtc->group->dev;
 589         struct drm_crtc *crtc = &rcrtc->crtc;
 590         u32 status;
 591
 592         /* Make sure vblank interrupts are enabled. */
 593         drm_crtc_vblank_get(crtc);
 594
 595         /*
 596          * Disable planes and calculate how many vertical blanking interrupts we
 597          * have to wait for. If a vertical blanking interrupt has been triggered
 598          * but not processed yet, we don't know whether it occurred before or
 599          * after the planes got disabled. We thus have to wait for two vblank
 600          * interrupts in that case.
 601          */
 602         spin_lock_irq(&rcrtc->vblank_lock);
 603         rcar_du_group_write(rcrtc->group, rcrtc->index % 2 ? DS2PR : DS1PR, 0);
 604         status = rcar_du_crtc_read(rcrtc, DSSR);
 605         rcrtc->vblank_count = status & DSSR_VBK ? 2 : 1;
 606         spin_unlock_irq(&rcrtc->vblank_lock);
 607
 608         if (!wait_event_timeout(rcrtc->vblank_wait, rcrtc->vblank_count == 0,
 609                                 msecs_to_jiffies(100)))
 610                 dev_warn(rcdu->dev, "vertical blanking timeout\n");
 611
 612         drm_crtc_vblank_put(crtc);
 613 }
 614
 615 static void rcar_du_crtc_stop(struct rcar_du_crtc *rcrtc)
 616 {
 617         struct drm_crtc *crtc = &rcrtc->crtc;
 618
 619         /*
 620          * Disable all planes and wait for the change to take effect. This is
 621          * required as the plane enable registers are updated on vblank, and no
 622          * vblank will occur once the CRTC is stopped. Disabling planes when
 623          * starting the CRTC thus wouldn't be enough as it would start scanning
 624          * out immediately from old frame buffers until the next vblank.
 625          *
 626          * This increases the CRTC stop delay, especially when multiple CRTCs
 627          * are stopped in one operation as we now wait for one vblank per CRTC.
 628          * Whether this can be improved needs to be researched.
 629          */
 630         rcar_du_crtc_disable_planes(rcrtc);
 631
 632         /*
 633          * Disable vertical blanking interrupt reporting. We first need to wait
 634          * for page flip completion before stopping the CRTC as userspace
 635          * expects page flips to eventually complete.
 636          */
 637         rcar_du_crtc_wait_page_flip(rcrtc);
 638         drm_crtc_vblank_off(crtc);
 639
 640         /* Disable the VSP compositor. */
 641         if (rcar_du_has(rcrtc->group->dev, RCAR_DU_FEATURE_VSP1_SOURCE))
 642                 rcar_du_vsp_disable(rcrtc);
 643
 644         /*
 645          * Select switch sync mode. This stops display operation and configures
 646          * the HSYNC and VSYNC signals as inputs.
 647          */
 648         rcar_du_crtc_clr_set(rcrtc, DSYSR, DSYSR_TVM_MASK, DSYSR_TVM_SWITCH);
 649
 650         rcar_du_group_start_stop(rcrtc->group, false);
 651 }
 652
 653 /* -----------------------------------------------------------------------------
 654  * CRTC Functions
 655  */
 656
 657 static void rcar_du_crtc_atomic_enable(struct drm_crtc *crtc,
 658                                        struct drm_crtc_state *old_state)
 659 {
 660         struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
 661
 662         rcar_du_crtc_get(rcrtc);
 663         rcar_du_crtc_start(rcrtc);
 664 }
 665
 666 static void rcar_du_crtc_atomic_disable(struct drm_crtc *crtc,
 667                                         struct drm_crtc_state *old_state)
 668 {
 669         struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
 670
 671         rcar_du_crtc_stop(rcrtc);
 672         rcar_du_crtc_put(rcrtc);
 673
 674         spin_lock_irq(&crtc->dev->event_lock);
 675         if (crtc->state->event) {
 676                 drm_crtc_send_vblank_event(crtc, crtc->state->event);
 677                 crtc->state->event = NULL;
 678         }
 679         spin_unlock_irq(&crtc->dev->event_lock);
 680
 681         rcrtc->outputs = 0;
 682 }
 683
 684 static void rcar_du_crtc_atomic_begin(struct drm_crtc *crtc,
 685                                       struct drm_crtc_state *old_crtc_state)
 686 {
 687         struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
 688
 689         WARN_ON(!crtc->state->enable);
 690
 691         /*
 692          * If a mode set is in progress we can be called with the CRTC disabled.
 693          * We thus need to first get and setup the CRTC in order to configure
 694          * planes. We must *not* put the CRTC in .atomic_flush(), as it must be
 695          * kept awake until the .atomic_enable() call that will follow. The get
 696          * operation in .atomic_enable() will in that case be a no-op, and the
 697          * CRTC will be put later in .atomic_disable().
 698          *
 699          * If a mode set is not in progress the CRTC is enabled, and the
 700          * following get call will be a no-op. There is thus no need to belance
 701          * it in .atomic_flush() either.
 702          */
 703         rcar_du_crtc_get(rcrtc);
 704
 705         if (rcar_du_has(rcrtc->group->dev, RCAR_DU_FEATURE_VSP1_SOURCE))
 706                 rcar_du_vsp_atomic_begin(rcrtc);
 707 }
 708
 709 static void rcar_du_crtc_atomic_flush(struct drm_crtc *crtc,
 710                                       struct drm_crtc_state *old_crtc_state)
 711 {
 712         struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
 713         struct drm_device *dev = rcrtc->crtc.dev;
 714         unsigned long flags;
 715
 716         rcar_du_crtc_update_planes(rcrtc);
 717
 718         if (crtc->state->event) {
 719                 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
 720
 721                 spin_lock_irqsave(&dev->event_lock, flags);
 722                 rcrtc->event = crtc->state->event;
 723                 crtc->state->event = NULL;
 724                 spin_unlock_irqrestore(&dev->event_lock, flags);
 725         }
 726
 727         if (rcar_du_has(rcrtc->group->dev, RCAR_DU_FEATURE_VSP1_SOURCE))
 728                 rcar_du_vsp_atomic_flush(rcrtc);
 729 }
 730
 731 enum drm_mode_status rcar_du_crtc_mode_valid(struct drm_crtc *crtc,
 732                                    const struct drm_display_mode *mode)
 733 {
 734         struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
 735         struct rcar_du_device *rcdu = rcrtc->group->dev;
 736         bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
 737
 738         if (interlaced && !rcar_du_has(rcdu, RCAR_DU_FEATURE_INTERLACED))
 739                 return MODE_NO_INTERLACE;
 740
 741         return MODE_OK;
 742 }
 743
 744 static const struct drm_crtc_helper_funcs crtc_helper_funcs = {
 745         .atomic_begin = rcar_du_crtc_atomic_begin,
 746         .atomic_flush = rcar_du_crtc_atomic_flush,
 747         .atomic_enable = rcar_du_crtc_atomic_enable,
 748         .atomic_disable = rcar_du_crtc_atomic_disable,
 749         .mode_valid = rcar_du_crtc_mode_valid,
 750 };
 751
 752 static void rcar_du_crtc_crc_init(struct rcar_du_crtc *rcrtc)
 753 {
 754         struct rcar_du_device *rcdu = rcrtc->group->dev;
 755         const char **sources;
 756         unsigned int count;
 757         int i = -1;
 758
 759         /* CRC available only on Gen3 HW. */
 760         if (rcdu->info->gen < 3)
 761                 return;
 762
 763         /* Reserve 1 for "auto" source. */
 764         count = rcrtc->vsp->num_planes + 1;
 765
 766         sources = kmalloc_array(count, sizeof(*sources), GFP_KERNEL);
 767         if (!sources)
 768                 return;
 769
 770         sources[0] = kstrdup("auto", GFP_KERNEL);
 771         if (!sources[0])
 772                 goto error;
 773
 774         for (i = 0; i < rcrtc->vsp->num_planes; ++i) {
 775                 struct drm_plane *plane = &rcrtc->vsp->planes[i].plane;
 776                 char name[16];
 777
 778                 sprintf(name, "plane%u", plane->base.id);
 779                 sources[i + 1] = kstrdup(name, GFP_KERNEL);
 780                 if (!sources[i + 1])
 781                         goto error;
 782         }
 783
 784         rcrtc->sources = sources;
 785         rcrtc->sources_count = count;
 786         return;
 787
 788 error:
 789         while (i >= 0) {
 790                 kfree(sources[i]);
 791                 i--;
 792         }
 793         kfree(sources);
 794 }
 795
 796 static void rcar_du_crtc_crc_cleanup(struct rcar_du_crtc *rcrtc)
 797 {
 798         unsigned int i;
 799
 800         if (!rcrtc->sources)
 801                 return;
 802
 803         for (i = 0; i < rcrtc->sources_count; i++)
 804                 kfree(rcrtc->sources[i]);
 805         kfree(rcrtc->sources);
 806
 807         rcrtc->sources = NULL;
 808         rcrtc->sources_count = 0;
 809 }
 810
 811 static struct drm_crtc_state *
 812 rcar_du_crtc_atomic_duplicate_state(struct drm_crtc *crtc)
 813 {
 814         struct rcar_du_crtc_state *state;
 815         struct rcar_du_crtc_state *copy;
 816
 817         if (WARN_ON(!crtc->state))
 818                 return NULL;
 819
 820         state = to_rcar_crtc_state(crtc->state);
 821         copy = kmemdup(state, sizeof(*state), GFP_KERNEL);
 822         if (copy == NULL)
 823                 return NULL;
 824
 825         __drm_atomic_helper_crtc_duplicate_state(crtc, &copy->state);
 826
 827         return &copy->state;
 828 }
 829
 830 static void rcar_du_crtc_atomic_destroy_state(struct drm_crtc *crtc,
 831                                               struct drm_crtc_state *state)
 832 {
 833         __drm_atomic_helper_crtc_destroy_state(state);
 834         kfree(to_rcar_crtc_state(state));
 835 }
 836
 837 static void rcar_du_crtc_cleanup(struct drm_crtc *crtc)
 838 {
 839         struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
 840
 841         rcar_du_crtc_crc_cleanup(rcrtc);
 842
 843         return drm_crtc_cleanup(crtc);
 844 }
 845
 846 static void rcar_du_crtc_reset(struct drm_crtc *crtc)
 847 {
 848         struct rcar_du_crtc_state *state;
 849
 850         if (crtc->state) {
 851                 rcar_du_crtc_atomic_destroy_state(crtc, crtc->state);
 852                 crtc->state = NULL;
 853         }
 854
 855         state = kzalloc(sizeof(*state), GFP_KERNEL);
 856         if (state == NULL)
 857                 return;
 858
 859         state->crc.source = VSP1_DU_CRC_NONE;
 860         state->crc.index = 0;
 861
 862         crtc->state = &state->state;
 863         crtc->state->crtc = crtc;
 864 }
 865
 866 static int rcar_du_crtc_enable_vblank(struct drm_crtc *crtc)
 867 {
 868         struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
 869
 870         rcar_du_crtc_write(rcrtc, DSRCR, DSRCR_VBCL);
 871         rcar_du_crtc_set(rcrtc, DIER, DIER_VBE);
 872         rcrtc->vblank_enable = true;
 873
 874         return 0;
 875 }
 876
 877 static void rcar_du_crtc_disable_vblank(struct drm_crtc *crtc)
 878 {
 879         struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
 880
 881         rcar_du_crtc_clr(rcrtc, DIER, DIER_VBE);
 882         rcrtc->vblank_enable = false;
 883 }
 884
 885 static int rcar_du_crtc_parse_crc_source(struct rcar_du_crtc *rcrtc,
 886                                          const char *source_name,
 887                                          enum vsp1_du_crc_source *source)
 888 {
 889         unsigned int index;
 890         int ret;
 891
 892         /*
 893          * Parse the source name. Supported values are "plane%u" to compute the
 894          * CRC on an input plane (%u is the plane ID), and "auto" to compute the
 895          * CRC on the composer (VSP) output.
 896          */
 897
 898         if (!source_name) {
 899                 *source = VSP1_DU_CRC_NONE;
 900                 return 0;
 901         } else if (!strcmp(source_name, "auto")) {
 902                 *source = VSP1_DU_CRC_OUTPUT;
 903                 return 0;
 904         } else if (strstarts(source_name, "plane")) {
 905                 unsigned int i;
 906
 907                 *source = VSP1_DU_CRC_PLANE;
 908
 909                 ret = kstrtouint(source_name + strlen("plane"), 10, &index);
 910                 if (ret < 0)
 911                         return ret;
 912
 913                 for (i = 0; i < rcrtc->vsp->num_planes; ++i) {
 914                         if (index == rcrtc->vsp->planes[i].plane.base.id)
 915                                 return i;
 916                 }
 917         }
 918
 919         return -EINVAL;
 920 }
 921
 922 static int rcar_du_crtc_verify_crc_source(struct drm_crtc *crtc,
 923                                           const char *source_name,
 924                                           size_t *values_cnt)
 925 {
 926         struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
 927         enum vsp1_du_crc_source source;
 928
 929         if (rcar_du_crtc_parse_crc_source(rcrtc, source_name, &source) < 0) {
 930                 DRM_DEBUG_DRIVER("unknown source %s\n", source_name);
 931                 return -EINVAL;
 932         }
 933
 934         *values_cnt = 1;
 935         return 0;
 936 }
 937
 938 const char *const *rcar_du_crtc_get_crc_sources(struct drm_crtc *crtc,
 939                                                 size_t *count)
 940 {
 941         struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
 942
 943         *count = rcrtc->sources_count;
 944         return rcrtc->sources;
 945 }
 946
 947 static int rcar_du_crtc_set_crc_source(struct drm_crtc *crtc,
 948                                        const char *source_name)
 949 {
 950         struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
 951         struct drm_modeset_acquire_ctx ctx;
 952         struct drm_crtc_state *crtc_state;
 953         struct drm_atomic_state *state;
 954         enum vsp1_du_crc_source source;
 955         unsigned int index;
 956         int ret;
 957
 958         ret = rcar_du_crtc_parse_crc_source(rcrtc, source_name, &source);
 959         if (ret < 0)
 960                 return ret;
 961
 962         index = ret;
 963
 964         /* Perform an atomic commit to set the CRC source. */
 965         drm_modeset_acquire_init(&ctx, 0);
 966
 967         state = drm_atomic_state_alloc(crtc->dev);
 968         if (!state) {
 969                 ret = -ENOMEM;
 970                 goto unlock;
 971         }
 972
 973         state->acquire_ctx = &ctx;
 974
 975 retry:
 976         crtc_state = drm_atomic_get_crtc_state(state, crtc);
 977         if (!IS_ERR(crtc_state)) {
 978                 struct rcar_du_crtc_state *rcrtc_state;
 979
 980                 rcrtc_state = to_rcar_crtc_state(crtc_state);
 981                 rcrtc_state->crc.source = source;
 982                 rcrtc_state->crc.index = index;
 983
 984                 ret = drm_atomic_commit(state);
 985         } else {
 986                 ret = PTR_ERR(crtc_state);
 987         }
 988
 989         if (ret == -EDEADLK) {
 990                 drm_atomic_state_clear(state);
 991                 drm_modeset_backoff(&ctx);
 992                 goto retry;
 993         }
 994
 995         drm_atomic_state_put(state);
 996
 997 unlock:
 998         drm_modeset_drop_locks(&ctx);
 999         drm_modeset_acquire_fini(&ctx);
1000
1001         return 0;
1002 }
1003
1004 static const struct drm_crtc_funcs crtc_funcs_gen2 = {
1005         .reset = rcar_du_crtc_reset,
1006         .destroy = drm_crtc_cleanup,
1007         .set_config = drm_atomic_helper_set_config,
1008         .page_flip = drm_atomic_helper_page_flip,
1009         .atomic_duplicate_state = rcar_du_crtc_atomic_duplicate_state,
1010         .atomic_destroy_state = rcar_du_crtc_atomic_destroy_state,
1011         .enable_vblank = rcar_du_crtc_enable_vblank,
1012         .disable_vblank = rcar_du_crtc_disable_vblank,
1013 };
1014
1015 static const struct drm_crtc_funcs crtc_funcs_gen3 = {
1016         .reset = rcar_du_crtc_reset,
1017         .destroy = rcar_du_crtc_cleanup,
1018         .set_config = drm_atomic_helper_set_config,
1019         .page_flip = drm_atomic_helper_page_flip,
1020         .atomic_duplicate_state = rcar_du_crtc_atomic_duplicate_state,
1021         .atomic_destroy_state = rcar_du_crtc_atomic_destroy_state,
1022         .enable_vblank = rcar_du_crtc_enable_vblank,
1023         .disable_vblank = rcar_du_crtc_disable_vblank,
1024         .set_crc_source = rcar_du_crtc_set_crc_source,
1025         .verify_crc_source = rcar_du_crtc_verify_crc_source,
1026         .get_crc_sources = rcar_du_crtc_get_crc_sources,
1027 };
1028
1029 /* -----------------------------------------------------------------------------
1030  * Interrupt Handling
1031  */
1032
1033 static irqreturn_t rcar_du_crtc_irq(int irq, void *arg)
1034 {
1035         struct rcar_du_crtc *rcrtc = arg;
1036         struct rcar_du_device *rcdu = rcrtc->group->dev;
1037         irqreturn_t ret = IRQ_NONE;
1038         u32 status;
1039
1040         spin_lock(&rcrtc->vblank_lock);
1041
1042         status = rcar_du_crtc_read(rcrtc, DSSR);
1043         rcar_du_crtc_write(rcrtc, DSRCR, status & DSRCR_MASK);
1044
1045         if (status & DSSR_VBK) {
1046                 /*
1047                  * Wake up the vblank wait if the counter reaches 0. This must
1048                  * be protected by the vblank_lock to avoid races in
1049                  * rcar_du_crtc_disable_planes().
1050                  */
1051                 if (rcrtc->vblank_count) {
1052                         if (--rcrtc->vblank_count == 0)
1053                                 wake_up(&rcrtc->vblank_wait);
1054                 }
1055         }
1056
1057         spin_unlock(&rcrtc->vblank_lock);
1058
1059         if (status & DSSR_VBK) {
1060                 if (rcdu->info->gen < 3) {
1061                         drm_crtc_handle_vblank(&rcrtc->crtc);
1062                         rcar_du_crtc_finish_page_flip(rcrtc);
1063                 }
1064
1065                 ret = IRQ_HANDLED;
1066         }
1067
1068         return ret;
1069 }
1070
1071 /* -----------------------------------------------------------------------------
1072  * Initialization
1073  */
1074
1075 int rcar_du_crtc_create(struct rcar_du_group *rgrp, unsigned int swindex,
1076                         unsigned int hwindex)
1077 {
1078         static const unsigned int mmio_offsets[] = {
1079                 DU0_REG_OFFSET, DU1_REG_OFFSET, DU2_REG_OFFSET, DU3_REG_OFFSET
1080         };
1081
1082         struct rcar_du_device *rcdu = rgrp->dev;
1083         struct platform_device *pdev = to_platform_device(rcdu->dev);
1084         struct rcar_du_crtc *rcrtc = &rcdu->crtcs[swindex];
1085         struct drm_crtc *crtc = &rcrtc->crtc;
1086         struct drm_plane *primary;
1087         unsigned int irqflags;
1088         struct clk *clk;
1089         char clk_name[9];
1090         char *name;
1091         int irq;
1092         int ret;
1093
1094         /* Get the CRTC clock and the optional external clock. */
1095         if (rcar_du_has(rcdu, RCAR_DU_FEATURE_CRTC_IRQ_CLOCK)) {
1096                 sprintf(clk_name, "du.%u", hwindex);
1097                 name = clk_name;
1098         } else {
1099                 name = NULL;
1100         }
1101
1102         rcrtc->clock = devm_clk_get(rcdu->dev, name);
1103         if (IS_ERR(rcrtc->clock)) {
1104                 dev_err(rcdu->dev, "no clock for DU channel %u\n", hwindex);
1105                 return PTR_ERR(rcrtc->clock);
1106         }
1107
1108         sprintf(clk_name, "dclkin.%u", hwindex);
1109         clk = devm_clk_get(rcdu->dev, clk_name);
1110         if (!IS_ERR(clk)) {
1111                 rcrtc->extclock = clk;
1112         } else if (PTR_ERR(rcrtc->clock) == -EPROBE_DEFER) {
1113                 dev_info(rcdu->dev, "can't get external clock %u\n", hwindex);
1114                 return -EPROBE_DEFER;
1115         }
1116
1117         init_waitqueue_head(&rcrtc->flip_wait);
1118         init_waitqueue_head(&rcrtc->vblank_wait);
1119         spin_lock_init(&rcrtc->vblank_lock);
1120
1121         rcrtc->group = rgrp;
1122         rcrtc->mmio_offset = mmio_offsets[hwindex];
1123         rcrtc->index = hwindex;
1124
1125         if (rcar_du_has(rcdu, RCAR_DU_FEATURE_VSP1_SOURCE))
1126                 primary = &rcrtc->vsp->planes[rcrtc->vsp_pipe].plane;
1127         else
1128                 primary = &rgrp->planes[swindex % 2].plane;
1129
1130         ret = drm_crtc_init_with_planes(rcdu->ddev, crtc, primary, NULL,
1131                                         rcdu->info->gen <= 2 ?
1132                                         &crtc_funcs_gen2 : &crtc_funcs_gen3,
1133                                         NULL);
1134         if (ret < 0)
1135                 return ret;
1136
1137         drm_crtc_helper_add(crtc, &crtc_helper_funcs);
1138
1139         /* Start with vertical blanking interrupt reporting disabled. */
1140         drm_crtc_vblank_off(crtc);
1141
1142         /* Register the interrupt handler. */
1143         if (rcar_du_has(rcdu, RCAR_DU_FEATURE_CRTC_IRQ_CLOCK)) {
1144                 /* The IRQ's are associated with the CRTC (sw)index. */
1145                 irq = platform_get_irq(pdev, swindex);
1146                 irqflags = 0;
1147         } else {
1148                 irq = platform_get_irq(pdev, 0);
1149                 irqflags = IRQF_SHARED;
1150         }
1151
1152         if (irq < 0) {
1153                 dev_err(rcdu->dev, "no IRQ for CRTC %u\n", swindex);
1154                 return irq;
1155         }
1156
1157         ret = devm_request_irq(rcdu->dev, irq, rcar_du_crtc_irq, irqflags,
1158                                dev_name(rcdu->dev), rcrtc);
1159         if (ret < 0) {
1160                 dev_err(rcdu->dev,
1161                         "failed to register IRQ for CRTC %u\n", swindex);
1162                 return ret;
1163         }
1164
1165         rcar_du_crtc_crc_init(rcrtc);
1166
1167         return 0;
1168 }