drivers/gpu/drm/radeon/rs400.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28
  29 #include <linux/seq_file.h>
  30 #include <linux/slab.h>
  31
  32 #include <drm/drm_device.h>
  33 #include <drm/drm_file.h>
  34
  35 #include "radeon.h"
  36 #include "radeon_asic.h"
  37 #include "rs400d.h"
  38
  39 /* This files gather functions specifics to : rs400,rs480 */
  40 static void rs400_debugfs_pcie_gart_info_init(struct radeon_device *rdev);
  41
  42 void rs400_gart_adjust_size(struct radeon_device *rdev)
  43 {
  44         /* Check gart size */
  45         switch (rdev->mc.gtt_size/(1024*1024)) {
  46         case 32:
  47         case 64:
  48         case 128:
  49         case 256:
  50         case 512:
  51         case 1024:
  52         case 2048:
  53                 break;
  54         default:
  55                 DRM_ERROR("Unable to use IGP GART size %uM\n",
  56                           (unsigned)(rdev->mc.gtt_size >> 20));
  57                 DRM_ERROR("Valid GART size for IGP are 32M,64M,128M,256M,512M,1G,2G\n");
  58                 DRM_ERROR("Forcing to 32M GART size\n");
  59                 rdev->mc.gtt_size = 32 * 1024 * 1024;
  60                 return;
  61         }
  62 }
  63
  64 void rs400_gart_tlb_flush(struct radeon_device *rdev)
  65 {
  66         uint32_t tmp;
  67         unsigned int timeout = rdev->usec_timeout;
  68
  69         WREG32_MC(RS480_GART_CACHE_CNTRL, RS480_GART_CACHE_INVALIDATE);
  70         do {
  71                 tmp = RREG32_MC(RS480_GART_CACHE_CNTRL);
  72                 if ((tmp & RS480_GART_CACHE_INVALIDATE) == 0)
  73                         break;
  74                 udelay(1);
  75                 timeout--;
  76         } while (timeout > 0);
  77         WREG32_MC(RS480_GART_CACHE_CNTRL, 0);
  78 }
  79
  80 int rs400_gart_init(struct radeon_device *rdev)
  81 {
  82         int r;
  83
  84         if (rdev->gart.ptr) {
  85                 WARN(1, "RS400 GART already initialized\n");
  86                 return 0;
  87         }
  88         /* Check gart size */
  89         switch(rdev->mc.gtt_size / (1024 * 1024)) {
  90         case 32:
  91         case 64:
  92         case 128:
  93         case 256:
  94         case 512:
  95         case 1024:
  96         case 2048:
  97                 break;
  98         default:
  99                 return -EINVAL;
 100         }
 101         /* Initialize common gart structure */
 102         r = radeon_gart_init(rdev);
 103         if (r)
 104                 return r;
 105         rs400_debugfs_pcie_gart_info_init(rdev);
 106         rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
 107         return radeon_gart_table_ram_alloc(rdev);
 108 }
 109
 110 int rs400_gart_enable(struct radeon_device *rdev)
 111 {
 112         uint32_t size_reg;
 113         uint32_t tmp;
 114
 115         tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH);
 116         tmp |= RS690_DIS_OUT_OF_PCI_GART_ACCESS;
 117         WREG32_MC(RS690_AIC_CTRL_SCRATCH, tmp);
 118         /* Check gart size */
 119         switch(rdev->mc.gtt_size / (1024 * 1024)) {
 120         case 32:
 121                 size_reg = RS480_VA_SIZE_32MB;
 122                 break;
 123         case 64:
 124                 size_reg = RS480_VA_SIZE_64MB;
 125                 break;
 126         case 128:
 127                 size_reg = RS480_VA_SIZE_128MB;
 128                 break;
 129         case 256:
 130                 size_reg = RS480_VA_SIZE_256MB;
 131                 break;
 132         case 512:
 133                 size_reg = RS480_VA_SIZE_512MB;
 134                 break;
 135         case 1024:
 136                 size_reg = RS480_VA_SIZE_1GB;
 137                 break;
 138         case 2048:
 139                 size_reg = RS480_VA_SIZE_2GB;
 140                 break;
 141         default:
 142                 return -EINVAL;
 143         }
 144         /* It should be fine to program it to max value */
 145         if (rdev->family == CHIP_RS690 || (rdev->family == CHIP_RS740)) {
 146                 WREG32_MC(RS690_MCCFG_AGP_BASE, 0xFFFFFFFF);
 147                 WREG32_MC(RS690_MCCFG_AGP_BASE_2, 0);
 148         } else {
 149                 WREG32(RADEON_AGP_BASE, 0xFFFFFFFF);
 150                 WREG32(RS480_AGP_BASE_2, 0);
 151         }
 152         tmp = REG_SET(RS690_MC_AGP_TOP, rdev->mc.gtt_end >> 16);
 153         tmp |= REG_SET(RS690_MC_AGP_START, rdev->mc.gtt_start >> 16);
 154         if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740)) {
 155                 WREG32_MC(RS690_MCCFG_AGP_LOCATION, tmp);
 156                 tmp = RREG32(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS;
 157                 WREG32(RADEON_BUS_CNTL, tmp);
 158         } else {
 159                 WREG32(RADEON_MC_AGP_LOCATION, tmp);
 160                 tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
 161                 WREG32(RADEON_BUS_CNTL, tmp);
 162         }
 163         /* Table should be in 32bits address space so ignore bits above. */
 164         tmp = (u32)rdev->gart.table_addr & 0xfffff000;
 165         tmp |= (upper_32_bits(rdev->gart.table_addr) & 0xff) << 4;
 166
 167         WREG32_MC(RS480_GART_BASE, tmp);
 168         /* TODO: more tweaking here */
 169         WREG32_MC(RS480_GART_FEATURE_ID,
 170                   (RS480_TLB_ENABLE |
 171                    RS480_GTW_LAC_EN | RS480_1LEVEL_GART));
 172         /* Disable snooping */
 173         WREG32_MC(RS480_AGP_MODE_CNTL,
 174                   (1 << RS480_REQ_TYPE_SNOOP_SHIFT) | RS480_REQ_TYPE_SNOOP_DIS);
 175         /* Disable AGP mode */
 176         /* FIXME: according to doc we should set HIDE_MMCFG_BAR=0,
 177          * AGPMODE30=0 & AGP30ENHANCED=0 in NB_CNTL */
 178         if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740)) {
 179                 tmp = RREG32_MC(RS480_MC_MISC_CNTL);
 180                 tmp |= RS480_GART_INDEX_REG_EN | RS690_BLOCK_GFX_D3_EN;
 181                 WREG32_MC(RS480_MC_MISC_CNTL, tmp);
 182         } else {
 183                 tmp = RREG32_MC(RS480_MC_MISC_CNTL);
 184                 tmp |= RS480_GART_INDEX_REG_EN;
 185                 WREG32_MC(RS480_MC_MISC_CNTL, tmp);
 186         }
 187         /* Enable gart */
 188         WREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN | size_reg));
 189         rs400_gart_tlb_flush(rdev);
 190         DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
 191                  (unsigned)(rdev->mc.gtt_size >> 20),
 192                  (unsigned long long)rdev->gart.table_addr);
 193         rdev->gart.ready = true;
 194         return 0;
 195 }
 196
 197 void rs400_gart_disable(struct radeon_device *rdev)
 198 {
 199         uint32_t tmp;
 200
 201         tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH);
 202         tmp |= RS690_DIS_OUT_OF_PCI_GART_ACCESS;
 203         WREG32_MC(RS690_AIC_CTRL_SCRATCH, tmp);
 204         WREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE, 0);
 205 }
 206
 207 void rs400_gart_fini(struct radeon_device *rdev)
 208 {
 209         radeon_gart_fini(rdev);
 210         rs400_gart_disable(rdev);
 211         radeon_gart_table_ram_free(rdev);
 212 }
 213
 214 #define RS400_PTE_UNSNOOPED (1 << 0)
 215 #define RS400_PTE_WRITEABLE (1 << 2)
 216 #define RS400_PTE_READABLE  (1 << 3)
 217
 218 uint64_t rs400_gart_get_page_entry(uint64_t addr, uint32_t flags)
 219 {
 220         uint32_t entry;
 221
 222         entry = (lower_32_bits(addr) & PAGE_MASK) |
 223                 ((upper_32_bits(addr) & 0xff) << 4);
 224         if (flags & RADEON_GART_PAGE_READ)
 225                 entry |= RS400_PTE_READABLE;
 226         if (flags & RADEON_GART_PAGE_WRITE)
 227                 entry |= RS400_PTE_WRITEABLE;
 228         if (!(flags & RADEON_GART_PAGE_SNOOP))
 229                 entry |= RS400_PTE_UNSNOOPED;
 230         return entry;
 231 }
 232
 233 void rs400_gart_set_page(struct radeon_device *rdev, unsigned i,
 234                          uint64_t entry)
 235 {
 236         u32 *gtt = rdev->gart.ptr;
 237         gtt[i] = cpu_to_le32(lower_32_bits(entry));
 238 }
 239
 240 int rs400_mc_wait_for_idle(struct radeon_device *rdev)
 241 {
 242         unsigned i;
 243         uint32_t tmp;
 244
 245         for (i = 0; i < rdev->usec_timeout; i++) {
 246                 /* read MC_STATUS */
 247                 tmp = RREG32(RADEON_MC_STATUS);
 248                 if (tmp & RADEON_MC_IDLE) {
 249                         return 0;
 250                 }
 251                 udelay(1);
 252         }
 253         return -1;
 254 }
 255
 256 static void rs400_gpu_init(struct radeon_device *rdev)
 257 {
 258         /* FIXME: is this correct ? */
 259         r420_pipes_init(rdev);
 260         if (rs400_mc_wait_for_idle(rdev)) {
 261                 pr_warn("rs400: Failed to wait MC idle while programming pipes. Bad things might happen. %08x\n",
 262                         RREG32(RADEON_MC_STATUS));
 263         }
 264 }
 265
 266 static void rs400_mc_init(struct radeon_device *rdev)
 267 {
 268         u64 base;
 269
 270         rs400_gart_adjust_size(rdev);
 271         rdev->mc.igp_sideport_enabled = radeon_combios_sideport_present(rdev);
 272         /* DDR for all card after R300 & IGP */
 273         rdev->mc.vram_is_ddr = true;
 274         rdev->mc.vram_width = 128;
 275         r100_vram_init_sizes(rdev);
 276         base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
 277         radeon_vram_location(rdev, &rdev->mc, base);
 278         rdev->mc.gtt_base_align = rdev->mc.gtt_size - 1;
 279         radeon_gtt_location(rdev, &rdev->mc);
 280         radeon_update_bandwidth_info(rdev);
 281 }
 282
 283 uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg)
 284 {
 285         unsigned long flags;
 286         uint32_t r;
 287
 288         spin_lock_irqsave(&rdev->mc_idx_lock, flags);
 289         WREG32(RS480_NB_MC_INDEX, reg & 0xff);
 290         r = RREG32(RS480_NB_MC_DATA);
 291         WREG32(RS480_NB_MC_INDEX, 0xff);
 292         spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
 293         return r;
 294 }
 295
 296 void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
 297 {
 298         unsigned long flags;
 299
 300         spin_lock_irqsave(&rdev->mc_idx_lock, flags);
 301         WREG32(RS480_NB_MC_INDEX, ((reg) & 0xff) | RS480_NB_MC_IND_WR_EN);
 302         WREG32(RS480_NB_MC_DATA, (v));
 303         WREG32(RS480_NB_MC_INDEX, 0xff);
 304         spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
 305 }
 306
 307 #if defined(CONFIG_DEBUG_FS)
 308 static int rs400_debugfs_gart_info_show(struct seq_file *m, void *unused)
 309 {
 310         struct radeon_device *rdev = (struct radeon_device *)m->private;
 311         uint32_t tmp;
 312
 313         tmp = RREG32(RADEON_HOST_PATH_CNTL);
 314         seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp);
 315         tmp = RREG32(RADEON_BUS_CNTL);
 316         seq_printf(m, "BUS_CNTL 0x%08x\n", tmp);
 317         tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH);
 318         seq_printf(m, "AIC_CTRL_SCRATCH 0x%08x\n", tmp);
 319         if (rdev->family == CHIP_RS690 || (rdev->family == CHIP_RS740)) {
 320                 tmp = RREG32_MC(RS690_MCCFG_AGP_BASE);
 321                 seq_printf(m, "MCCFG_AGP_BASE 0x%08x\n", tmp);
 322                 tmp = RREG32_MC(RS690_MCCFG_AGP_BASE_2);
 323                 seq_printf(m, "MCCFG_AGP_BASE_2 0x%08x\n", tmp);
 324                 tmp = RREG32_MC(RS690_MCCFG_AGP_LOCATION);
 325                 seq_printf(m, "MCCFG_AGP_LOCATION 0x%08x\n", tmp);
 326                 tmp = RREG32_MC(RS690_MCCFG_FB_LOCATION);
 327                 seq_printf(m, "MCCFG_FB_LOCATION 0x%08x\n", tmp);
 328                 tmp = RREG32(RS690_HDP_FB_LOCATION);
 329                 seq_printf(m, "HDP_FB_LOCATION 0x%08x\n", tmp);
 330         } else {
 331                 tmp = RREG32(RADEON_AGP_BASE);
 332                 seq_printf(m, "AGP_BASE 0x%08x\n", tmp);
 333                 tmp = RREG32(RS480_AGP_BASE_2);
 334                 seq_printf(m, "AGP_BASE_2 0x%08x\n", tmp);
 335                 tmp = RREG32(RADEON_MC_AGP_LOCATION);
 336                 seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp);
 337         }
 338         tmp = RREG32_MC(RS480_GART_BASE);
 339         seq_printf(m, "GART_BASE 0x%08x\n", tmp);
 340         tmp = RREG32_MC(RS480_GART_FEATURE_ID);
 341         seq_printf(m, "GART_FEATURE_ID 0x%08x\n", tmp);
 342         tmp = RREG32_MC(RS480_AGP_MODE_CNTL);
 343         seq_printf(m, "AGP_MODE_CONTROL 0x%08x\n", tmp);
 344         tmp = RREG32_MC(RS480_MC_MISC_CNTL);
 345         seq_printf(m, "MC_MISC_CNTL 0x%08x\n", tmp);
 346         tmp = RREG32_MC(0x5F);
 347         seq_printf(m, "MC_MISC_UMA_CNTL 0x%08x\n", tmp);
 348         tmp = RREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE);
 349         seq_printf(m, "AGP_ADDRESS_SPACE_SIZE 0x%08x\n", tmp);
 350         tmp = RREG32_MC(RS480_GART_CACHE_CNTRL);
 351         seq_printf(m, "GART_CACHE_CNTRL 0x%08x\n", tmp);
 352         tmp = RREG32_MC(0x3B);
 353         seq_printf(m, "MC_GART_ERROR_ADDRESS 0x%08x\n", tmp);
 354         tmp = RREG32_MC(0x3C);
 355         seq_printf(m, "MC_GART_ERROR_ADDRESS_HI 0x%08x\n", tmp);
 356         tmp = RREG32_MC(0x30);
 357         seq_printf(m, "GART_ERROR_0 0x%08x\n", tmp);
 358         tmp = RREG32_MC(0x31);
 359         seq_printf(m, "GART_ERROR_1 0x%08x\n", tmp);
 360         tmp = RREG32_MC(0x32);
 361         seq_printf(m, "GART_ERROR_2 0x%08x\n", tmp);
 362         tmp = RREG32_MC(0x33);
 363         seq_printf(m, "GART_ERROR_3 0x%08x\n", tmp);
 364         tmp = RREG32_MC(0x34);
 365         seq_printf(m, "GART_ERROR_4 0x%08x\n", tmp);
 366         tmp = RREG32_MC(0x35);
 367         seq_printf(m, "GART_ERROR_5 0x%08x\n", tmp);
 368         tmp = RREG32_MC(0x36);
 369         seq_printf(m, "GART_ERROR_6 0x%08x\n", tmp);
 370         tmp = RREG32_MC(0x37);
 371         seq_printf(m, "GART_ERROR_7 0x%08x\n", tmp);
 372         return 0;
 373 }
 374
 375 DEFINE_SHOW_ATTRIBUTE(rs400_debugfs_gart_info);
 376 #endif
 377
 378 static void rs400_debugfs_pcie_gart_info_init(struct radeon_device *rdev)
 379 {
 380 #if defined(CONFIG_DEBUG_FS)
 381         struct dentry *root = rdev->ddev->primary->debugfs_root;
 382
 383         debugfs_create_file("rs400_gart_info", 0444, root, rdev,
 384                             &rs400_debugfs_gart_info_fops);
 385 #endif
 386 }
 387
 388 static void rs400_mc_program(struct radeon_device *rdev)
 389 {
 390         struct r100_mc_save save;
 391
 392         /* Stops all mc clients */
 393         r100_mc_stop(rdev, &save);
 394
 395         /* Wait for mc idle */
 396         if (rs400_mc_wait_for_idle(rdev))
 397                 dev_warn(rdev->dev, "rs400: Wait MC idle timeout before updating MC.\n");
 398         WREG32(R_000148_MC_FB_LOCATION,
 399                 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
 400                 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
 401
 402         r100_mc_resume(rdev, &save);
 403 }
 404
 405 static int rs400_startup(struct radeon_device *rdev)
 406 {
 407         int r;
 408
 409         r100_set_common_regs(rdev);
 410
 411         rs400_mc_program(rdev);
 412         /* Resume clock */
 413         r300_clock_startup(rdev);
 414         /* Initialize GPU configuration (# pipes, ...) */
 415         rs400_gpu_init(rdev);
 416         r100_enable_bm(rdev);
 417         /* Initialize GART (initialize after TTM so we can allocate
 418          * memory through TTM but finalize after TTM) */
 419         r = rs400_gart_enable(rdev);
 420         if (r)
 421                 return r;
 422
 423         /* allocate wb buffer */
 424         r = radeon_wb_init(rdev);
 425         if (r)
 426                 return r;
 427
 428         r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
 429         if (r) {
 430                 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
 431                 return r;
 432         }
 433
 434         /* Enable IRQ */
 435         if (!rdev->irq.installed) {
 436                 r = radeon_irq_kms_init(rdev);
 437                 if (r)
 438                         return r;
 439         }
 440
 441         r100_irq_set(rdev);
 442         rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
 443         /* 1M ring buffer */
 444         r = r100_cp_init(rdev, 1024 * 1024);
 445         if (r) {
 446                 dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
 447                 return r;
 448         }
 449
 450         r = radeon_ib_pool_init(rdev);
 451         if (r) {
 452                 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
 453                 return r;
 454         }
 455
 456         return 0;
 457 }
 458
 459 int rs400_resume(struct radeon_device *rdev)
 460 {
 461         int r;
 462
 463         /* Make sur GART are not working */
 464         rs400_gart_disable(rdev);
 465         /* Resume clock before doing reset */
 466         r300_clock_startup(rdev);
 467         /* setup MC before calling post tables */
 468         rs400_mc_program(rdev);
 469         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
 470         if (radeon_asic_reset(rdev)) {
 471                 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
 472                         RREG32(R_000E40_RBBM_STATUS),
 473                         RREG32(R_0007C0_CP_STAT));
 474         }
 475         /* post */
 476         radeon_combios_asic_init(rdev->ddev);
 477         /* Resume clock after posting */
 478         r300_clock_startup(rdev);
 479         /* Initialize surface registers */
 480         radeon_surface_init(rdev);
 481
 482         rdev->accel_working = true;
 483         r = rs400_startup(rdev);
 484         if (r) {
 485                 rdev->accel_working = false;
 486         }
 487         return r;
 488 }
 489
 490 int rs400_suspend(struct radeon_device *rdev)
 491 {
 492         radeon_pm_suspend(rdev);
 493         r100_cp_disable(rdev);
 494         radeon_wb_disable(rdev);
 495         r100_irq_disable(rdev);
 496         rs400_gart_disable(rdev);
 497         return 0;
 498 }
 499
 500 void rs400_fini(struct radeon_device *rdev)
 501 {
 502         radeon_pm_fini(rdev);
 503         r100_cp_fini(rdev);
 504         radeon_wb_fini(rdev);
 505         radeon_ib_pool_fini(rdev);
 506         radeon_gem_fini(rdev);
 507         rs400_gart_fini(rdev);
 508         radeon_irq_kms_fini(rdev);
 509         radeon_fence_driver_fini(rdev);
 510         radeon_bo_fini(rdev);
 511         radeon_atombios_fini(rdev);
 512         kfree(rdev->bios);
 513         rdev->bios = NULL;
 514 }
 515
 516 int rs400_init(struct radeon_device *rdev)
 517 {
 518         int r;
 519
 520         /* Disable VGA */
 521         r100_vga_render_disable(rdev);
 522         /* Initialize scratch registers */
 523         radeon_scratch_init(rdev);
 524         /* Initialize surface registers */
 525         radeon_surface_init(rdev);
 526         /* TODO: disable VGA need to use VGA request */
 527         /* restore some register to sane defaults */
 528         r100_restore_sanity(rdev);
 529         /* BIOS*/
 530         if (!radeon_get_bios(rdev)) {
 531                 if (ASIC_IS_AVIVO(rdev))
 532                         return -EINVAL;
 533         }
 534         if (rdev->is_atom_bios) {
 535                 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
 536                 return -EINVAL;
 537         } else {
 538                 r = radeon_combios_init(rdev);
 539                 if (r)
 540                         return r;
 541         }
 542         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
 543         if (radeon_asic_reset(rdev)) {
 544                 dev_warn(rdev->dev,
 545                         "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
 546                         RREG32(R_000E40_RBBM_STATUS),
 547                         RREG32(R_0007C0_CP_STAT));
 548         }
 549         /* check if cards are posted or not */
 550         if (radeon_boot_test_post_card(rdev) == false)
 551                 return -EINVAL;
 552
 553         /* Initialize clocks */
 554         radeon_get_clock_info(rdev->ddev);
 555         /* initialize memory controller */
 556         rs400_mc_init(rdev);
 557         /* Fence driver */
 558         radeon_fence_driver_init(rdev);
 559         /* Memory manager */
 560         r = radeon_bo_init(rdev);
 561         if (r)
 562                 return r;
 563         r = rs400_gart_init(rdev);
 564         if (r)
 565                 return r;
 566         r300_set_reg_safe(rdev);
 567
 568         /* Initialize power management */
 569         radeon_pm_init(rdev);
 570
 571         rdev->accel_working = true;
 572         r = rs400_startup(rdev);
 573         if (r) {
 574                 /* Somethings want wront with the accel init stop accel */
 575                 dev_err(rdev->dev, "Disabling GPU acceleration\n");
 576                 r100_cp_fini(rdev);
 577                 radeon_wb_fini(rdev);
 578                 radeon_ib_pool_fini(rdev);
 579                 rs400_gart_fini(rdev);
 580                 radeon_irq_kms_fini(rdev);
 581                 rdev->accel_working = false;
 582         }
 583         return 0;
 584 }