2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
30 #include <drm/radeon_drm.h>
31 #include "radeon_asic.h"
33 #include <linux/vga_switcheroo.h>
34 #include <linux/slab.h>
35 #include <linux/pm_runtime.h>
37 #if defined(CONFIG_VGA_SWITCHEROO)
38 bool radeon_has_atpx(void);
40 static inline bool radeon_has_atpx(void) { return false; }
44 * radeon_driver_unload_kms - Main unload function for KMS.
46 * @dev: drm dev pointer
48 * This is the main unload function for KMS (all asics).
49 * It calls radeon_modeset_fini() to tear down the
50 * displays, and radeon_device_fini() to tear down
51 * the rest of the device (CP, writeback, etc.).
52 * Returns 0 on success.
54 int radeon_driver_unload_kms(struct drm_device *dev)
56 struct radeon_device *rdev = dev->dev_private;
61 if (rdev->rmmio == NULL)
64 pm_runtime_get_sync(dev->dev);
66 radeon_acpi_fini(rdev);
68 radeon_modeset_fini(rdev);
69 radeon_device_fini(rdev);
73 dev->dev_private = NULL;
78 * radeon_driver_load_kms - Main load function for KMS.
80 * @dev: drm dev pointer
81 * @flags: device flags
83 * This is the main load function for KMS (all asics).
84 * It calls radeon_device_init() to set up the non-display
85 * parts of the chip (asic init, CP, writeback, etc.), and
86 * radeon_modeset_init() to set up the display parts
87 * (crtcs, encoders, hotplug detect, etc.).
88 * Returns 0 on success, error on failure.
90 int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags)
92 struct radeon_device *rdev;
95 rdev = kzalloc(sizeof(struct radeon_device), GFP_KERNEL);
99 dev->dev_private = (void *)rdev;
101 /* update BUS flag */
102 if (drm_pci_device_is_agp(dev)) {
103 flags |= RADEON_IS_AGP;
104 } else if (pci_is_pcie(dev->pdev)) {
105 flags |= RADEON_IS_PCIE;
107 flags |= RADEON_IS_PCI;
110 if ((radeon_runtime_pm != 0) &&
112 ((flags & RADEON_IS_IGP) == 0))
113 flags |= RADEON_IS_PX;
115 /* radeon_device_init should report only fatal error
116 * like memory allocation failure or iomapping failure,
117 * or memory manager initialization failure, it must
118 * properly initialize the GPU MC controller and permit
121 r = radeon_device_init(rdev, dev, dev->pdev, flags);
123 dev_err(&dev->pdev->dev, "Fatal error during GPU init\n");
127 /* Again modeset_init should fail only on fatal error
128 * otherwise it should provide enough functionalities
129 * for shadowfb to run
131 r = radeon_modeset_init(rdev);
133 dev_err(&dev->pdev->dev, "Fatal error during modeset init\n");
135 /* Call ACPI methods: require modeset init
136 * but failure is not fatal
139 acpi_status = radeon_acpi_init(rdev);
141 dev_dbg(&dev->pdev->dev,
142 "Error during ACPI methods call\n");
145 if (radeon_is_px(dev)) {
146 pm_runtime_use_autosuspend(dev->dev);
147 pm_runtime_set_autosuspend_delay(dev->dev, 5000);
148 pm_runtime_set_active(dev->dev);
149 pm_runtime_allow(dev->dev);
150 pm_runtime_mark_last_busy(dev->dev);
151 pm_runtime_put_autosuspend(dev->dev);
156 radeon_driver_unload_kms(dev);
163 * radeon_set_filp_rights - Set filp right.
165 * @dev: drm dev pointer
170 * Sets the filp rights for the device (all asics).
172 static void radeon_set_filp_rights(struct drm_device *dev,
173 struct drm_file **owner,
174 struct drm_file *applier,
177 mutex_lock(&dev->struct_mutex);
182 } else if (*value == 0) {
184 if (*owner == applier)
187 *value = *owner == applier ? 1 : 0;
188 mutex_unlock(&dev->struct_mutex);
192 * Userspace get information ioctl
195 * radeon_info_ioctl - answer a device specific request.
197 * @rdev: radeon device pointer
198 * @data: request object
201 * This function is used to pass device specific parameters to the userspace
202 * drivers. Examples include: pci device id, pipeline parms, tiling params,
204 * Returns 0 on success, -EINVAL on failure.
206 static int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
208 struct radeon_device *rdev = dev->dev_private;
209 struct drm_radeon_info *info = data;
210 struct radeon_mode_info *minfo = &rdev->mode_info;
211 uint32_t *value, value_tmp, *value_ptr, value_size;
213 struct drm_crtc *crtc;
216 value_ptr = (uint32_t *)((unsigned long)info->value);
218 value_size = sizeof(uint32_t);
220 switch (info->request) {
221 case RADEON_INFO_DEVICE_ID:
222 *value = dev->pdev->device;
224 case RADEON_INFO_NUM_GB_PIPES:
225 *value = rdev->num_gb_pipes;
227 case RADEON_INFO_NUM_Z_PIPES:
228 *value = rdev->num_z_pipes;
230 case RADEON_INFO_ACCEL_WORKING:
231 /* xf86-video-ati 6.13.0 relies on this being false for evergreen */
232 if ((rdev->family >= CHIP_CEDAR) && (rdev->family <= CHIP_HEMLOCK))
235 *value = rdev->accel_working;
237 case RADEON_INFO_CRTC_FROM_ID:
238 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {
239 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
242 for (i = 0, found = 0; i < rdev->num_crtc; i++) {
243 crtc = (struct drm_crtc *)minfo->crtcs[i];
244 if (crtc && crtc->base.id == *value) {
245 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
246 *value = radeon_crtc->crtc_id;
252 DRM_DEBUG_KMS("unknown crtc id %d\n", *value);
256 case RADEON_INFO_ACCEL_WORKING2:
257 *value = rdev->accel_working;
259 case RADEON_INFO_TILING_CONFIG:
260 if (rdev->family >= CHIP_BONAIRE)
261 *value = rdev->config.cik.tile_config;
262 else if (rdev->family >= CHIP_TAHITI)
263 *value = rdev->config.si.tile_config;
264 else if (rdev->family >= CHIP_CAYMAN)
265 *value = rdev->config.cayman.tile_config;
266 else if (rdev->family >= CHIP_CEDAR)
267 *value = rdev->config.evergreen.tile_config;
268 else if (rdev->family >= CHIP_RV770)
269 *value = rdev->config.rv770.tile_config;
270 else if (rdev->family >= CHIP_R600)
271 *value = rdev->config.r600.tile_config;
273 DRM_DEBUG_KMS("tiling config is r6xx+ only!\n");
277 case RADEON_INFO_WANT_HYPERZ:
278 /* The "value" here is both an input and output parameter.
279 * If the input value is 1, filp requests hyper-z access.
280 * If the input value is 0, filp revokes its hyper-z access.
282 * When returning, the value is 1 if filp owns hyper-z access,
284 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {
285 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
289 DRM_DEBUG_KMS("WANT_HYPERZ: invalid value %d\n", *value);
292 radeon_set_filp_rights(dev, &rdev->hyperz_filp, filp, value);
294 case RADEON_INFO_WANT_CMASK:
295 /* The same logic as Hyper-Z. */
296 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {
297 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
301 DRM_DEBUG_KMS("WANT_CMASK: invalid value %d\n", *value);
304 radeon_set_filp_rights(dev, &rdev->cmask_filp, filp, value);
306 case RADEON_INFO_CLOCK_CRYSTAL_FREQ:
307 /* return clock value in KHz */
308 if (rdev->asic->get_xclk)
309 *value = radeon_get_xclk(rdev) * 10;
311 *value = rdev->clock.spll.reference_freq * 10;
313 case RADEON_INFO_NUM_BACKENDS:
314 if (rdev->family >= CHIP_BONAIRE)
315 *value = rdev->config.cik.max_backends_per_se *
316 rdev->config.cik.max_shader_engines;
317 else if (rdev->family >= CHIP_TAHITI)
318 *value = rdev->config.si.max_backends_per_se *
319 rdev->config.si.max_shader_engines;
320 else if (rdev->family >= CHIP_CAYMAN)
321 *value = rdev->config.cayman.max_backends_per_se *
322 rdev->config.cayman.max_shader_engines;
323 else if (rdev->family >= CHIP_CEDAR)
324 *value = rdev->config.evergreen.max_backends;
325 else if (rdev->family >= CHIP_RV770)
326 *value = rdev->config.rv770.max_backends;
327 else if (rdev->family >= CHIP_R600)
328 *value = rdev->config.r600.max_backends;
333 case RADEON_INFO_NUM_TILE_PIPES:
334 if (rdev->family >= CHIP_BONAIRE)
335 *value = rdev->config.cik.max_tile_pipes;
336 else if (rdev->family >= CHIP_TAHITI)
337 *value = rdev->config.si.max_tile_pipes;
338 else if (rdev->family >= CHIP_CAYMAN)
339 *value = rdev->config.cayman.max_tile_pipes;
340 else if (rdev->family >= CHIP_CEDAR)
341 *value = rdev->config.evergreen.max_tile_pipes;
342 else if (rdev->family >= CHIP_RV770)
343 *value = rdev->config.rv770.max_tile_pipes;
344 else if (rdev->family >= CHIP_R600)
345 *value = rdev->config.r600.max_tile_pipes;
350 case RADEON_INFO_FUSION_GART_WORKING:
353 case RADEON_INFO_BACKEND_MAP:
354 if (rdev->family >= CHIP_BONAIRE)
355 *value = rdev->config.cik.backend_map;
356 else if (rdev->family >= CHIP_TAHITI)
357 *value = rdev->config.si.backend_map;
358 else if (rdev->family >= CHIP_CAYMAN)
359 *value = rdev->config.cayman.backend_map;
360 else if (rdev->family >= CHIP_CEDAR)
361 *value = rdev->config.evergreen.backend_map;
362 else if (rdev->family >= CHIP_RV770)
363 *value = rdev->config.rv770.backend_map;
364 else if (rdev->family >= CHIP_R600)
365 *value = rdev->config.r600.backend_map;
370 case RADEON_INFO_VA_START:
371 /* this is where we report if vm is supported or not */
372 if (rdev->family < CHIP_CAYMAN)
374 *value = RADEON_VA_RESERVED_SIZE;
376 case RADEON_INFO_IB_VM_MAX_SIZE:
377 /* this is where we report if vm is supported or not */
378 if (rdev->family < CHIP_CAYMAN)
380 *value = RADEON_IB_VM_MAX_SIZE;
382 case RADEON_INFO_MAX_PIPES:
383 if (rdev->family >= CHIP_BONAIRE)
384 *value = rdev->config.cik.max_cu_per_sh;
385 else if (rdev->family >= CHIP_TAHITI)
386 *value = rdev->config.si.max_cu_per_sh;
387 else if (rdev->family >= CHIP_CAYMAN)
388 *value = rdev->config.cayman.max_pipes_per_simd;
389 else if (rdev->family >= CHIP_CEDAR)
390 *value = rdev->config.evergreen.max_pipes;
391 else if (rdev->family >= CHIP_RV770)
392 *value = rdev->config.rv770.max_pipes;
393 else if (rdev->family >= CHIP_R600)
394 *value = rdev->config.r600.max_pipes;
399 case RADEON_INFO_TIMESTAMP:
400 if (rdev->family < CHIP_R600) {
401 DRM_DEBUG_KMS("timestamp is r6xx+ only!\n");
404 value = (uint32_t*)&value64;
405 value_size = sizeof(uint64_t);
406 value64 = radeon_get_gpu_clock_counter(rdev);
408 case RADEON_INFO_MAX_SE:
409 if (rdev->family >= CHIP_BONAIRE)
410 *value = rdev->config.cik.max_shader_engines;
411 else if (rdev->family >= CHIP_TAHITI)
412 *value = rdev->config.si.max_shader_engines;
413 else if (rdev->family >= CHIP_CAYMAN)
414 *value = rdev->config.cayman.max_shader_engines;
415 else if (rdev->family >= CHIP_CEDAR)
416 *value = rdev->config.evergreen.num_ses;
420 case RADEON_INFO_MAX_SH_PER_SE:
421 if (rdev->family >= CHIP_BONAIRE)
422 *value = rdev->config.cik.max_sh_per_se;
423 else if (rdev->family >= CHIP_TAHITI)
424 *value = rdev->config.si.max_sh_per_se;
428 case RADEON_INFO_FASTFB_WORKING:
429 *value = rdev->fastfb_working;
431 case RADEON_INFO_RING_WORKING:
432 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {
433 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
437 case RADEON_CS_RING_GFX:
438 case RADEON_CS_RING_COMPUTE:
439 *value = rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready;
441 case RADEON_CS_RING_DMA:
442 *value = rdev->ring[R600_RING_TYPE_DMA_INDEX].ready;
443 *value |= rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX].ready;
445 case RADEON_CS_RING_UVD:
446 *value = rdev->ring[R600_RING_TYPE_UVD_INDEX].ready;
452 case RADEON_INFO_SI_TILE_MODE_ARRAY:
453 if (rdev->family >= CHIP_BONAIRE) {
454 value = rdev->config.cik.tile_mode_array;
455 value_size = sizeof(uint32_t)*32;
456 } else if (rdev->family >= CHIP_TAHITI) {
457 value = rdev->config.si.tile_mode_array;
458 value_size = sizeof(uint32_t)*32;
460 DRM_DEBUG_KMS("tile mode array is si+ only!\n");
464 case RADEON_INFO_CIK_MACROTILE_MODE_ARRAY:
465 if (rdev->family >= CHIP_BONAIRE) {
466 value = rdev->config.cik.macrotile_mode_array;
467 value_size = sizeof(uint32_t)*16;
469 DRM_DEBUG_KMS("macrotile mode array is cik+ only!\n");
473 case RADEON_INFO_SI_CP_DMA_COMPUTE:
476 case RADEON_INFO_SI_BACKEND_ENABLED_MASK:
477 if (rdev->family >= CHIP_BONAIRE) {
478 *value = rdev->config.cik.backend_enable_mask;
479 } else if (rdev->family >= CHIP_TAHITI) {
480 *value = rdev->config.si.backend_enable_mask;
482 DRM_DEBUG_KMS("BACKEND_ENABLED_MASK is si+ only!\n");
485 case RADEON_INFO_MAX_SCLK:
486 if ((rdev->pm.pm_method == PM_METHOD_DPM) &&
487 rdev->pm.dpm_enabled)
488 *value = rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk * 10;
490 *value = rdev->pm.default_sclk * 10;
493 DRM_DEBUG_KMS("Invalid request %d\n", info->request);
496 if (copy_to_user(value_ptr, (char*)value, value_size)) {
497 DRM_ERROR("copy_to_user %s:%u\n", __func__, __LINE__);
505 * Outdated mess for old drm with Xorg being in charge (void function now).
508 * radeon_driver_firstopen_kms - drm callback for last close
510 * @dev: drm dev pointer
512 * Switch vga switcheroo state after last close (all asics).
514 void radeon_driver_lastclose_kms(struct drm_device *dev)
516 vga_switcheroo_process_delayed_switch();
520 * radeon_driver_open_kms - drm callback for open
522 * @dev: drm dev pointer
523 * @file_priv: drm file
525 * On device open, init vm on cayman+ (all asics).
526 * Returns 0 on success, error on failure.
528 int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv)
530 struct radeon_device *rdev = dev->dev_private;
533 file_priv->driver_priv = NULL;
535 r = pm_runtime_get_sync(dev->dev);
539 /* new gpu have virtual address space support */
540 if (rdev->family >= CHIP_CAYMAN) {
541 struct radeon_fpriv *fpriv;
542 struct radeon_bo_va *bo_va;
545 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
546 if (unlikely(!fpriv)) {
550 radeon_vm_init(rdev, &fpriv->vm);
552 r = radeon_bo_reserve(rdev->ring_tmp_bo.bo, false);
556 /* map the ib pool buffer read only into
557 * virtual address space */
558 bo_va = radeon_vm_bo_add(rdev, &fpriv->vm,
559 rdev->ring_tmp_bo.bo);
560 r = radeon_vm_bo_set_addr(rdev, bo_va, RADEON_VA_IB_OFFSET,
561 RADEON_VM_PAGE_READABLE |
562 RADEON_VM_PAGE_SNOOPED);
564 radeon_bo_unreserve(rdev->ring_tmp_bo.bo);
566 radeon_vm_fini(rdev, &fpriv->vm);
571 file_priv->driver_priv = fpriv;
574 pm_runtime_mark_last_busy(dev->dev);
575 pm_runtime_put_autosuspend(dev->dev);
580 * radeon_driver_postclose_kms - drm callback for post close
582 * @dev: drm dev pointer
583 * @file_priv: drm file
585 * On device post close, tear down vm on cayman+ (all asics).
587 void radeon_driver_postclose_kms(struct drm_device *dev,
588 struct drm_file *file_priv)
590 struct radeon_device *rdev = dev->dev_private;
592 /* new gpu have virtual address space support */
593 if (rdev->family >= CHIP_CAYMAN && file_priv->driver_priv) {
594 struct radeon_fpriv *fpriv = file_priv->driver_priv;
595 struct radeon_bo_va *bo_va;
598 r = radeon_bo_reserve(rdev->ring_tmp_bo.bo, false);
600 bo_va = radeon_vm_bo_find(&fpriv->vm,
601 rdev->ring_tmp_bo.bo);
603 radeon_vm_bo_rmv(rdev, bo_va);
604 radeon_bo_unreserve(rdev->ring_tmp_bo.bo);
607 radeon_vm_fini(rdev, &fpriv->vm);
609 file_priv->driver_priv = NULL;
614 * radeon_driver_preclose_kms - drm callback for pre close
616 * @dev: drm dev pointer
617 * @file_priv: drm file
619 * On device pre close, tear down hyperz and cmask filps on r1xx-r5xx
622 void radeon_driver_preclose_kms(struct drm_device *dev,
623 struct drm_file *file_priv)
625 struct radeon_device *rdev = dev->dev_private;
626 if (rdev->hyperz_filp == file_priv)
627 rdev->hyperz_filp = NULL;
628 if (rdev->cmask_filp == file_priv)
629 rdev->cmask_filp = NULL;
630 radeon_uvd_free_handles(rdev, file_priv);
634 * VBlank related functions.
637 * radeon_get_vblank_counter_kms - get frame count
639 * @dev: drm dev pointer
640 * @crtc: crtc to get the frame count from
642 * Gets the frame count on the requested crtc (all asics).
643 * Returns frame count on success, -EINVAL on failure.
645 u32 radeon_get_vblank_counter_kms(struct drm_device *dev, int crtc)
647 struct radeon_device *rdev = dev->dev_private;
649 if (crtc < 0 || crtc >= rdev->num_crtc) {
650 DRM_ERROR("Invalid crtc %d\n", crtc);
654 return radeon_get_vblank_counter(rdev, crtc);
658 * radeon_enable_vblank_kms - enable vblank interrupt
660 * @dev: drm dev pointer
661 * @crtc: crtc to enable vblank interrupt for
663 * Enable the interrupt on the requested crtc (all asics).
664 * Returns 0 on success, -EINVAL on failure.
666 int radeon_enable_vblank_kms(struct drm_device *dev, int crtc)
668 struct radeon_device *rdev = dev->dev_private;
669 unsigned long irqflags;
672 if (crtc < 0 || crtc >= rdev->num_crtc) {
673 DRM_ERROR("Invalid crtc %d\n", crtc);
677 spin_lock_irqsave(&rdev->irq.lock, irqflags);
678 rdev->irq.crtc_vblank_int[crtc] = true;
679 r = radeon_irq_set(rdev);
680 spin_unlock_irqrestore(&rdev->irq.lock, irqflags);
685 * radeon_disable_vblank_kms - disable vblank interrupt
687 * @dev: drm dev pointer
688 * @crtc: crtc to disable vblank interrupt for
690 * Disable the interrupt on the requested crtc (all asics).
692 void radeon_disable_vblank_kms(struct drm_device *dev, int crtc)
694 struct radeon_device *rdev = dev->dev_private;
695 unsigned long irqflags;
697 if (crtc < 0 || crtc >= rdev->num_crtc) {
698 DRM_ERROR("Invalid crtc %d\n", crtc);
702 spin_lock_irqsave(&rdev->irq.lock, irqflags);
703 rdev->irq.crtc_vblank_int[crtc] = false;
704 radeon_irq_set(rdev);
705 spin_unlock_irqrestore(&rdev->irq.lock, irqflags);
709 * radeon_get_vblank_timestamp_kms - get vblank timestamp
711 * @dev: drm dev pointer
712 * @crtc: crtc to get the timestamp for
713 * @max_error: max error
714 * @vblank_time: time value
715 * @flags: flags passed to the driver
717 * Gets the timestamp on the requested crtc based on the
718 * scanout position. (all asics).
719 * Returns postive status flags on success, negative error on failure.
721 int radeon_get_vblank_timestamp_kms(struct drm_device *dev, int crtc,
723 struct timeval *vblank_time,
726 struct drm_crtc *drmcrtc;
727 struct radeon_device *rdev = dev->dev_private;
729 if (crtc < 0 || crtc >= dev->num_crtcs) {
730 DRM_ERROR("Invalid crtc %d\n", crtc);
734 /* Get associated drm_crtc: */
735 drmcrtc = &rdev->mode_info.crtcs[crtc]->base;
737 /* Helper routine in DRM core does all the work: */
738 return drm_calc_vbltimestamp_from_scanoutpos(dev, crtc, max_error,
740 drmcrtc, &drmcrtc->hwmode);
743 #define KMS_INVALID_IOCTL(name) \
744 static int name(struct drm_device *dev, void *data, struct drm_file \
747 DRM_ERROR("invalid ioctl with kms %s\n", __func__); \
752 * All these ioctls are invalid in kms world.
754 KMS_INVALID_IOCTL(radeon_cp_init_kms)
755 KMS_INVALID_IOCTL(radeon_cp_start_kms)
756 KMS_INVALID_IOCTL(radeon_cp_stop_kms)
757 KMS_INVALID_IOCTL(radeon_cp_reset_kms)
758 KMS_INVALID_IOCTL(radeon_cp_idle_kms)
759 KMS_INVALID_IOCTL(radeon_cp_resume_kms)
760 KMS_INVALID_IOCTL(radeon_engine_reset_kms)
761 KMS_INVALID_IOCTL(radeon_fullscreen_kms)
762 KMS_INVALID_IOCTL(radeon_cp_swap_kms)
763 KMS_INVALID_IOCTL(radeon_cp_clear_kms)
764 KMS_INVALID_IOCTL(radeon_cp_vertex_kms)
765 KMS_INVALID_IOCTL(radeon_cp_indices_kms)
766 KMS_INVALID_IOCTL(radeon_cp_texture_kms)
767 KMS_INVALID_IOCTL(radeon_cp_stipple_kms)
768 KMS_INVALID_IOCTL(radeon_cp_indirect_kms)
769 KMS_INVALID_IOCTL(radeon_cp_vertex2_kms)
770 KMS_INVALID_IOCTL(radeon_cp_cmdbuf_kms)
771 KMS_INVALID_IOCTL(radeon_cp_getparam_kms)
772 KMS_INVALID_IOCTL(radeon_cp_flip_kms)
773 KMS_INVALID_IOCTL(radeon_mem_alloc_kms)
774 KMS_INVALID_IOCTL(radeon_mem_free_kms)
775 KMS_INVALID_IOCTL(radeon_mem_init_heap_kms)
776 KMS_INVALID_IOCTL(radeon_irq_emit_kms)
777 KMS_INVALID_IOCTL(radeon_irq_wait_kms)
778 KMS_INVALID_IOCTL(radeon_cp_setparam_kms)
779 KMS_INVALID_IOCTL(radeon_surface_alloc_kms)
780 KMS_INVALID_IOCTL(radeon_surface_free_kms)
783 const struct drm_ioctl_desc radeon_ioctls_kms[] = {
784 DRM_IOCTL_DEF_DRV(RADEON_CP_INIT, radeon_cp_init_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
785 DRM_IOCTL_DEF_DRV(RADEON_CP_START, radeon_cp_start_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
786 DRM_IOCTL_DEF_DRV(RADEON_CP_STOP, radeon_cp_stop_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
787 DRM_IOCTL_DEF_DRV(RADEON_CP_RESET, radeon_cp_reset_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
788 DRM_IOCTL_DEF_DRV(RADEON_CP_IDLE, radeon_cp_idle_kms, DRM_AUTH),
789 DRM_IOCTL_DEF_DRV(RADEON_CP_RESUME, radeon_cp_resume_kms, DRM_AUTH),
790 DRM_IOCTL_DEF_DRV(RADEON_RESET, radeon_engine_reset_kms, DRM_AUTH),
791 DRM_IOCTL_DEF_DRV(RADEON_FULLSCREEN, radeon_fullscreen_kms, DRM_AUTH),
792 DRM_IOCTL_DEF_DRV(RADEON_SWAP, radeon_cp_swap_kms, DRM_AUTH),
793 DRM_IOCTL_DEF_DRV(RADEON_CLEAR, radeon_cp_clear_kms, DRM_AUTH),
794 DRM_IOCTL_DEF_DRV(RADEON_VERTEX, radeon_cp_vertex_kms, DRM_AUTH),
795 DRM_IOCTL_DEF_DRV(RADEON_INDICES, radeon_cp_indices_kms, DRM_AUTH),
796 DRM_IOCTL_DEF_DRV(RADEON_TEXTURE, radeon_cp_texture_kms, DRM_AUTH),
797 DRM_IOCTL_DEF_DRV(RADEON_STIPPLE, radeon_cp_stipple_kms, DRM_AUTH),
798 DRM_IOCTL_DEF_DRV(RADEON_INDIRECT, radeon_cp_indirect_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
799 DRM_IOCTL_DEF_DRV(RADEON_VERTEX2, radeon_cp_vertex2_kms, DRM_AUTH),
800 DRM_IOCTL_DEF_DRV(RADEON_CMDBUF, radeon_cp_cmdbuf_kms, DRM_AUTH),
801 DRM_IOCTL_DEF_DRV(RADEON_GETPARAM, radeon_cp_getparam_kms, DRM_AUTH),
802 DRM_IOCTL_DEF_DRV(RADEON_FLIP, radeon_cp_flip_kms, DRM_AUTH),
803 DRM_IOCTL_DEF_DRV(RADEON_ALLOC, radeon_mem_alloc_kms, DRM_AUTH),
804 DRM_IOCTL_DEF_DRV(RADEON_FREE, radeon_mem_free_kms, DRM_AUTH),
805 DRM_IOCTL_DEF_DRV(RADEON_INIT_HEAP, radeon_mem_init_heap_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
806 DRM_IOCTL_DEF_DRV(RADEON_IRQ_EMIT, radeon_irq_emit_kms, DRM_AUTH),
807 DRM_IOCTL_DEF_DRV(RADEON_IRQ_WAIT, radeon_irq_wait_kms, DRM_AUTH),
808 DRM_IOCTL_DEF_DRV(RADEON_SETPARAM, radeon_cp_setparam_kms, DRM_AUTH),
809 DRM_IOCTL_DEF_DRV(RADEON_SURF_ALLOC, radeon_surface_alloc_kms, DRM_AUTH),
810 DRM_IOCTL_DEF_DRV(RADEON_SURF_FREE, radeon_surface_free_kms, DRM_AUTH),
812 DRM_IOCTL_DEF_DRV(RADEON_GEM_INFO, radeon_gem_info_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
813 DRM_IOCTL_DEF_DRV(RADEON_GEM_CREATE, radeon_gem_create_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
814 DRM_IOCTL_DEF_DRV(RADEON_GEM_MMAP, radeon_gem_mmap_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
815 DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_DOMAIN, radeon_gem_set_domain_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
816 DRM_IOCTL_DEF_DRV(RADEON_GEM_PREAD, radeon_gem_pread_ioctl, DRM_AUTH|DRM_UNLOCKED),
817 DRM_IOCTL_DEF_DRV(RADEON_GEM_PWRITE, radeon_gem_pwrite_ioctl, DRM_AUTH|DRM_UNLOCKED),
818 DRM_IOCTL_DEF_DRV(RADEON_GEM_WAIT_IDLE, radeon_gem_wait_idle_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
819 DRM_IOCTL_DEF_DRV(RADEON_CS, radeon_cs_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
820 DRM_IOCTL_DEF_DRV(RADEON_INFO, radeon_info_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
821 DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_TILING, radeon_gem_set_tiling_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
822 DRM_IOCTL_DEF_DRV(RADEON_GEM_GET_TILING, radeon_gem_get_tiling_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
823 DRM_IOCTL_DEF_DRV(RADEON_GEM_BUSY, radeon_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
824 DRM_IOCTL_DEF_DRV(RADEON_GEM_VA, radeon_gem_va_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
826 int radeon_max_kms_ioctl = DRM_ARRAY_SIZE(radeon_ioctls_kms);