2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
30 #include <drm/radeon_drm.h>
31 #include "radeon_asic.h"
33 #include <linux/vga_switcheroo.h>
34 #include <linux/slab.h>
35 #include <linux/pm_runtime.h>
37 * radeon_driver_unload_kms - Main unload function for KMS.
39 * @dev: drm dev pointer
41 * This is the main unload function for KMS (all asics).
42 * It calls radeon_modeset_fini() to tear down the
43 * displays, and radeon_device_fini() to tear down
44 * the rest of the device (CP, writeback, etc.).
45 * Returns 0 on success.
47 int radeon_driver_unload_kms(struct drm_device *dev)
49 struct radeon_device *rdev = dev->dev_private;
54 if (rdev->rmmio == NULL)
57 pm_runtime_get_sync(dev->dev);
59 radeon_acpi_fini(rdev);
61 radeon_modeset_fini(rdev);
62 radeon_device_fini(rdev);
66 dev->dev_private = NULL;
71 * radeon_driver_load_kms - Main load function for KMS.
73 * @dev: drm dev pointer
74 * @flags: device flags
76 * This is the main load function for KMS (all asics).
77 * It calls radeon_device_init() to set up the non-display
78 * parts of the chip (asic init, CP, writeback, etc.), and
79 * radeon_modeset_init() to set up the display parts
80 * (crtcs, encoders, hotplug detect, etc.).
81 * Returns 0 on success, error on failure.
83 int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags)
85 struct radeon_device *rdev;
88 rdev = kzalloc(sizeof(struct radeon_device), GFP_KERNEL);
92 dev->dev_private = (void *)rdev;
95 if (drm_pci_device_is_agp(dev)) {
96 flags |= RADEON_IS_AGP;
97 } else if (pci_is_pcie(dev->pdev)) {
98 flags |= RADEON_IS_PCIE;
100 flags |= RADEON_IS_PCI;
103 /* radeon_device_init should report only fatal error
104 * like memory allocation failure or iomapping failure,
105 * or memory manager initialization failure, it must
106 * properly initialize the GPU MC controller and permit
109 r = radeon_device_init(rdev, dev, dev->pdev, flags);
111 dev_err(&dev->pdev->dev, "Fatal error during GPU init\n");
115 /* Again modeset_init should fail only on fatal error
116 * otherwise it should provide enough functionalities
117 * for shadowfb to run
119 r = radeon_modeset_init(rdev);
121 dev_err(&dev->pdev->dev, "Fatal error during modeset init\n");
123 /* Call ACPI methods: require modeset init
124 * but failure is not fatal
127 acpi_status = radeon_acpi_init(rdev);
129 dev_dbg(&dev->pdev->dev,
130 "Error during ACPI methods call\n");
133 if (radeon_runtime_pm != 0) {
134 pm_runtime_use_autosuspend(dev->dev);
135 pm_runtime_set_autosuspend_delay(dev->dev, 5000);
136 pm_runtime_set_active(dev->dev);
137 pm_runtime_allow(dev->dev);
138 pm_runtime_mark_last_busy(dev->dev);
139 pm_runtime_put_autosuspend(dev->dev);
144 radeon_driver_unload_kms(dev);
151 * radeon_set_filp_rights - Set filp right.
153 * @dev: drm dev pointer
158 * Sets the filp rights for the device (all asics).
160 static void radeon_set_filp_rights(struct drm_device *dev,
161 struct drm_file **owner,
162 struct drm_file *applier,
165 mutex_lock(&dev->struct_mutex);
170 } else if (*value == 0) {
172 if (*owner == applier)
175 *value = *owner == applier ? 1 : 0;
176 mutex_unlock(&dev->struct_mutex);
180 * Userspace get information ioctl
183 * radeon_info_ioctl - answer a device specific request.
185 * @rdev: radeon device pointer
186 * @data: request object
189 * This function is used to pass device specific parameters to the userspace
190 * drivers. Examples include: pci device id, pipeline parms, tiling params,
192 * Returns 0 on success, -EINVAL on failure.
194 int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
196 struct radeon_device *rdev = dev->dev_private;
197 struct drm_radeon_info *info = data;
198 struct radeon_mode_info *minfo = &rdev->mode_info;
199 uint32_t *value, value_tmp, *value_ptr, value_size;
201 struct drm_crtc *crtc;
204 value_ptr = (uint32_t *)((unsigned long)info->value);
206 value_size = sizeof(uint32_t);
208 switch (info->request) {
209 case RADEON_INFO_DEVICE_ID:
210 *value = dev->pdev->device;
212 case RADEON_INFO_NUM_GB_PIPES:
213 *value = rdev->num_gb_pipes;
215 case RADEON_INFO_NUM_Z_PIPES:
216 *value = rdev->num_z_pipes;
218 case RADEON_INFO_ACCEL_WORKING:
219 /* xf86-video-ati 6.13.0 relies on this being false for evergreen */
220 if ((rdev->family >= CHIP_CEDAR) && (rdev->family <= CHIP_HEMLOCK))
223 *value = rdev->accel_working;
225 case RADEON_INFO_CRTC_FROM_ID:
226 if (DRM_COPY_FROM_USER(value, value_ptr, sizeof(uint32_t))) {
227 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
230 for (i = 0, found = 0; i < rdev->num_crtc; i++) {
231 crtc = (struct drm_crtc *)minfo->crtcs[i];
232 if (crtc && crtc->base.id == *value) {
233 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
234 *value = radeon_crtc->crtc_id;
240 DRM_DEBUG_KMS("unknown crtc id %d\n", *value);
244 case RADEON_INFO_ACCEL_WORKING2:
245 *value = rdev->accel_working;
247 case RADEON_INFO_TILING_CONFIG:
248 if (rdev->family >= CHIP_BONAIRE)
249 *value = rdev->config.cik.tile_config;
250 else if (rdev->family >= CHIP_TAHITI)
251 *value = rdev->config.si.tile_config;
252 else if (rdev->family >= CHIP_CAYMAN)
253 *value = rdev->config.cayman.tile_config;
254 else if (rdev->family >= CHIP_CEDAR)
255 *value = rdev->config.evergreen.tile_config;
256 else if (rdev->family >= CHIP_RV770)
257 *value = rdev->config.rv770.tile_config;
258 else if (rdev->family >= CHIP_R600)
259 *value = rdev->config.r600.tile_config;
261 DRM_DEBUG_KMS("tiling config is r6xx+ only!\n");
265 case RADEON_INFO_WANT_HYPERZ:
266 /* The "value" here is both an input and output parameter.
267 * If the input value is 1, filp requests hyper-z access.
268 * If the input value is 0, filp revokes its hyper-z access.
270 * When returning, the value is 1 if filp owns hyper-z access,
272 if (DRM_COPY_FROM_USER(value, value_ptr, sizeof(uint32_t))) {
273 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
277 DRM_DEBUG_KMS("WANT_HYPERZ: invalid value %d\n", *value);
280 radeon_set_filp_rights(dev, &rdev->hyperz_filp, filp, value);
282 case RADEON_INFO_WANT_CMASK:
283 /* The same logic as Hyper-Z. */
284 if (DRM_COPY_FROM_USER(value, value_ptr, sizeof(uint32_t))) {
285 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
289 DRM_DEBUG_KMS("WANT_CMASK: invalid value %d\n", *value);
292 radeon_set_filp_rights(dev, &rdev->cmask_filp, filp, value);
294 case RADEON_INFO_CLOCK_CRYSTAL_FREQ:
295 /* return clock value in KHz */
296 if (rdev->asic->get_xclk)
297 *value = radeon_get_xclk(rdev) * 10;
299 *value = rdev->clock.spll.reference_freq * 10;
301 case RADEON_INFO_NUM_BACKENDS:
302 if (rdev->family >= CHIP_BONAIRE)
303 *value = rdev->config.cik.max_backends_per_se *
304 rdev->config.cik.max_shader_engines;
305 else if (rdev->family >= CHIP_TAHITI)
306 *value = rdev->config.si.max_backends_per_se *
307 rdev->config.si.max_shader_engines;
308 else if (rdev->family >= CHIP_CAYMAN)
309 *value = rdev->config.cayman.max_backends_per_se *
310 rdev->config.cayman.max_shader_engines;
311 else if (rdev->family >= CHIP_CEDAR)
312 *value = rdev->config.evergreen.max_backends;
313 else if (rdev->family >= CHIP_RV770)
314 *value = rdev->config.rv770.max_backends;
315 else if (rdev->family >= CHIP_R600)
316 *value = rdev->config.r600.max_backends;
321 case RADEON_INFO_NUM_TILE_PIPES:
322 if (rdev->family >= CHIP_BONAIRE)
323 *value = rdev->config.cik.max_tile_pipes;
324 else if (rdev->family >= CHIP_TAHITI)
325 *value = rdev->config.si.max_tile_pipes;
326 else if (rdev->family >= CHIP_CAYMAN)
327 *value = rdev->config.cayman.max_tile_pipes;
328 else if (rdev->family >= CHIP_CEDAR)
329 *value = rdev->config.evergreen.max_tile_pipes;
330 else if (rdev->family >= CHIP_RV770)
331 *value = rdev->config.rv770.max_tile_pipes;
332 else if (rdev->family >= CHIP_R600)
333 *value = rdev->config.r600.max_tile_pipes;
338 case RADEON_INFO_FUSION_GART_WORKING:
341 case RADEON_INFO_BACKEND_MAP:
342 if (rdev->family >= CHIP_BONAIRE)
343 *value = rdev->config.cik.backend_map;
344 else if (rdev->family >= CHIP_TAHITI)
345 *value = rdev->config.si.backend_map;
346 else if (rdev->family >= CHIP_CAYMAN)
347 *value = rdev->config.cayman.backend_map;
348 else if (rdev->family >= CHIP_CEDAR)
349 *value = rdev->config.evergreen.backend_map;
350 else if (rdev->family >= CHIP_RV770)
351 *value = rdev->config.rv770.backend_map;
352 else if (rdev->family >= CHIP_R600)
353 *value = rdev->config.r600.backend_map;
358 case RADEON_INFO_VA_START:
359 /* this is where we report if vm is supported or not */
360 if (rdev->family < CHIP_CAYMAN)
362 *value = RADEON_VA_RESERVED_SIZE;
364 case RADEON_INFO_IB_VM_MAX_SIZE:
365 /* this is where we report if vm is supported or not */
366 if (rdev->family < CHIP_CAYMAN)
368 *value = RADEON_IB_VM_MAX_SIZE;
370 case RADEON_INFO_MAX_PIPES:
371 if (rdev->family >= CHIP_BONAIRE)
372 *value = rdev->config.cik.max_cu_per_sh;
373 else if (rdev->family >= CHIP_TAHITI)
374 *value = rdev->config.si.max_cu_per_sh;
375 else if (rdev->family >= CHIP_CAYMAN)
376 *value = rdev->config.cayman.max_pipes_per_simd;
377 else if (rdev->family >= CHIP_CEDAR)
378 *value = rdev->config.evergreen.max_pipes;
379 else if (rdev->family >= CHIP_RV770)
380 *value = rdev->config.rv770.max_pipes;
381 else if (rdev->family >= CHIP_R600)
382 *value = rdev->config.r600.max_pipes;
387 case RADEON_INFO_TIMESTAMP:
388 if (rdev->family < CHIP_R600) {
389 DRM_DEBUG_KMS("timestamp is r6xx+ only!\n");
392 value = (uint32_t*)&value64;
393 value_size = sizeof(uint64_t);
394 value64 = radeon_get_gpu_clock_counter(rdev);
396 case RADEON_INFO_MAX_SE:
397 if (rdev->family >= CHIP_BONAIRE)
398 *value = rdev->config.cik.max_shader_engines;
399 else if (rdev->family >= CHIP_TAHITI)
400 *value = rdev->config.si.max_shader_engines;
401 else if (rdev->family >= CHIP_CAYMAN)
402 *value = rdev->config.cayman.max_shader_engines;
403 else if (rdev->family >= CHIP_CEDAR)
404 *value = rdev->config.evergreen.num_ses;
408 case RADEON_INFO_MAX_SH_PER_SE:
409 if (rdev->family >= CHIP_BONAIRE)
410 *value = rdev->config.cik.max_sh_per_se;
411 else if (rdev->family >= CHIP_TAHITI)
412 *value = rdev->config.si.max_sh_per_se;
416 case RADEON_INFO_FASTFB_WORKING:
417 *value = rdev->fastfb_working;
419 case RADEON_INFO_RING_WORKING:
420 if (DRM_COPY_FROM_USER(value, value_ptr, sizeof(uint32_t))) {
421 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
425 case RADEON_CS_RING_GFX:
426 case RADEON_CS_RING_COMPUTE:
427 *value = rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready;
429 case RADEON_CS_RING_DMA:
430 *value = rdev->ring[R600_RING_TYPE_DMA_INDEX].ready;
431 *value |= rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX].ready;
433 case RADEON_CS_RING_UVD:
434 *value = rdev->ring[R600_RING_TYPE_UVD_INDEX].ready;
440 case RADEON_INFO_SI_TILE_MODE_ARRAY:
441 if (rdev->family >= CHIP_BONAIRE) {
442 value = rdev->config.cik.tile_mode_array;
443 value_size = sizeof(uint32_t)*32;
444 } else if (rdev->family >= CHIP_TAHITI) {
445 value = rdev->config.si.tile_mode_array;
446 value_size = sizeof(uint32_t)*32;
448 DRM_DEBUG_KMS("tile mode array is si+ only!\n");
452 case RADEON_INFO_SI_CP_DMA_COMPUTE:
456 DRM_DEBUG_KMS("Invalid request %d\n", info->request);
459 if (DRM_COPY_TO_USER(value_ptr, (char*)value, value_size)) {
460 DRM_ERROR("copy_to_user %s:%u\n", __func__, __LINE__);
468 * Outdated mess for old drm with Xorg being in charge (void function now).
471 * radeon_driver_firstopen_kms - drm callback for last close
473 * @dev: drm dev pointer
475 * Switch vga switcheroo state after last close (all asics).
477 void radeon_driver_lastclose_kms(struct drm_device *dev)
479 vga_switcheroo_process_delayed_switch();
483 * radeon_driver_open_kms - drm callback for open
485 * @dev: drm dev pointer
486 * @file_priv: drm file
488 * On device open, init vm on cayman+ (all asics).
489 * Returns 0 on success, error on failure.
491 int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv)
493 struct radeon_device *rdev = dev->dev_private;
496 file_priv->driver_priv = NULL;
498 r = pm_runtime_get_sync(dev->dev);
502 /* new gpu have virtual address space support */
503 if (rdev->family >= CHIP_CAYMAN) {
504 struct radeon_fpriv *fpriv;
505 struct radeon_bo_va *bo_va;
508 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
509 if (unlikely(!fpriv)) {
513 radeon_vm_init(rdev, &fpriv->vm);
515 /* map the ib pool buffer read only into
516 * virtual address space */
517 bo_va = radeon_vm_bo_add(rdev, &fpriv->vm,
518 rdev->ring_tmp_bo.bo);
519 r = radeon_vm_bo_set_addr(rdev, bo_va, RADEON_VA_IB_OFFSET,
520 RADEON_VM_PAGE_READABLE |
521 RADEON_VM_PAGE_SNOOPED);
523 radeon_vm_fini(rdev, &fpriv->vm);
528 file_priv->driver_priv = fpriv;
531 pm_runtime_mark_last_busy(dev->dev);
532 pm_runtime_put_autosuspend(dev->dev);
537 * radeon_driver_postclose_kms - drm callback for post close
539 * @dev: drm dev pointer
540 * @file_priv: drm file
542 * On device post close, tear down vm on cayman+ (all asics).
544 void radeon_driver_postclose_kms(struct drm_device *dev,
545 struct drm_file *file_priv)
547 struct radeon_device *rdev = dev->dev_private;
549 /* new gpu have virtual address space support */
550 if (rdev->family >= CHIP_CAYMAN && file_priv->driver_priv) {
551 struct radeon_fpriv *fpriv = file_priv->driver_priv;
552 struct radeon_bo_va *bo_va;
555 r = radeon_bo_reserve(rdev->ring_tmp_bo.bo, false);
557 bo_va = radeon_vm_bo_find(&fpriv->vm,
558 rdev->ring_tmp_bo.bo);
560 radeon_vm_bo_rmv(rdev, bo_va);
561 radeon_bo_unreserve(rdev->ring_tmp_bo.bo);
564 radeon_vm_fini(rdev, &fpriv->vm);
566 file_priv->driver_priv = NULL;
571 * radeon_driver_preclose_kms - drm callback for pre close
573 * @dev: drm dev pointer
574 * @file_priv: drm file
576 * On device pre close, tear down hyperz and cmask filps on r1xx-r5xx
579 void radeon_driver_preclose_kms(struct drm_device *dev,
580 struct drm_file *file_priv)
582 struct radeon_device *rdev = dev->dev_private;
583 if (rdev->hyperz_filp == file_priv)
584 rdev->hyperz_filp = NULL;
585 if (rdev->cmask_filp == file_priv)
586 rdev->cmask_filp = NULL;
587 radeon_uvd_free_handles(rdev, file_priv);
591 * VBlank related functions.
594 * radeon_get_vblank_counter_kms - get frame count
596 * @dev: drm dev pointer
597 * @crtc: crtc to get the frame count from
599 * Gets the frame count on the requested crtc (all asics).
600 * Returns frame count on success, -EINVAL on failure.
602 u32 radeon_get_vblank_counter_kms(struct drm_device *dev, int crtc)
604 struct radeon_device *rdev = dev->dev_private;
606 if (crtc < 0 || crtc >= rdev->num_crtc) {
607 DRM_ERROR("Invalid crtc %d\n", crtc);
611 return radeon_get_vblank_counter(rdev, crtc);
615 * radeon_enable_vblank_kms - enable vblank interrupt
617 * @dev: drm dev pointer
618 * @crtc: crtc to enable vblank interrupt for
620 * Enable the interrupt on the requested crtc (all asics).
621 * Returns 0 on success, -EINVAL on failure.
623 int radeon_enable_vblank_kms(struct drm_device *dev, int crtc)
625 struct radeon_device *rdev = dev->dev_private;
626 unsigned long irqflags;
629 if (crtc < 0 || crtc >= rdev->num_crtc) {
630 DRM_ERROR("Invalid crtc %d\n", crtc);
634 spin_lock_irqsave(&rdev->irq.lock, irqflags);
635 rdev->irq.crtc_vblank_int[crtc] = true;
636 r = radeon_irq_set(rdev);
637 spin_unlock_irqrestore(&rdev->irq.lock, irqflags);
642 * radeon_disable_vblank_kms - disable vblank interrupt
644 * @dev: drm dev pointer
645 * @crtc: crtc to disable vblank interrupt for
647 * Disable the interrupt on the requested crtc (all asics).
649 void radeon_disable_vblank_kms(struct drm_device *dev, int crtc)
651 struct radeon_device *rdev = dev->dev_private;
652 unsigned long irqflags;
654 if (crtc < 0 || crtc >= rdev->num_crtc) {
655 DRM_ERROR("Invalid crtc %d\n", crtc);
659 spin_lock_irqsave(&rdev->irq.lock, irqflags);
660 rdev->irq.crtc_vblank_int[crtc] = false;
661 radeon_irq_set(rdev);
662 spin_unlock_irqrestore(&rdev->irq.lock, irqflags);
666 * radeon_get_vblank_timestamp_kms - get vblank timestamp
668 * @dev: drm dev pointer
669 * @crtc: crtc to get the timestamp for
670 * @max_error: max error
671 * @vblank_time: time value
672 * @flags: flags passed to the driver
674 * Gets the timestamp on the requested crtc based on the
675 * scanout position. (all asics).
676 * Returns postive status flags on success, negative error on failure.
678 int radeon_get_vblank_timestamp_kms(struct drm_device *dev, int crtc,
680 struct timeval *vblank_time,
683 struct drm_crtc *drmcrtc;
684 struct radeon_device *rdev = dev->dev_private;
686 if (crtc < 0 || crtc >= dev->num_crtcs) {
687 DRM_ERROR("Invalid crtc %d\n", crtc);
691 /* Get associated drm_crtc: */
692 drmcrtc = &rdev->mode_info.crtcs[crtc]->base;
694 /* Helper routine in DRM core does all the work: */
695 return drm_calc_vbltimestamp_from_scanoutpos(dev, crtc, max_error,
700 #define KMS_INVALID_IOCTL(name) \
701 int name(struct drm_device *dev, void *data, struct drm_file *file_priv)\
703 DRM_ERROR("invalid ioctl with kms %s\n", __func__); \
708 * All these ioctls are invalid in kms world.
710 KMS_INVALID_IOCTL(radeon_cp_init_kms)
711 KMS_INVALID_IOCTL(radeon_cp_start_kms)
712 KMS_INVALID_IOCTL(radeon_cp_stop_kms)
713 KMS_INVALID_IOCTL(radeon_cp_reset_kms)
714 KMS_INVALID_IOCTL(radeon_cp_idle_kms)
715 KMS_INVALID_IOCTL(radeon_cp_resume_kms)
716 KMS_INVALID_IOCTL(radeon_engine_reset_kms)
717 KMS_INVALID_IOCTL(radeon_fullscreen_kms)
718 KMS_INVALID_IOCTL(radeon_cp_swap_kms)
719 KMS_INVALID_IOCTL(radeon_cp_clear_kms)
720 KMS_INVALID_IOCTL(radeon_cp_vertex_kms)
721 KMS_INVALID_IOCTL(radeon_cp_indices_kms)
722 KMS_INVALID_IOCTL(radeon_cp_texture_kms)
723 KMS_INVALID_IOCTL(radeon_cp_stipple_kms)
724 KMS_INVALID_IOCTL(radeon_cp_indirect_kms)
725 KMS_INVALID_IOCTL(radeon_cp_vertex2_kms)
726 KMS_INVALID_IOCTL(radeon_cp_cmdbuf_kms)
727 KMS_INVALID_IOCTL(radeon_cp_getparam_kms)
728 KMS_INVALID_IOCTL(radeon_cp_flip_kms)
729 KMS_INVALID_IOCTL(radeon_mem_alloc_kms)
730 KMS_INVALID_IOCTL(radeon_mem_free_kms)
731 KMS_INVALID_IOCTL(radeon_mem_init_heap_kms)
732 KMS_INVALID_IOCTL(radeon_irq_emit_kms)
733 KMS_INVALID_IOCTL(radeon_irq_wait_kms)
734 KMS_INVALID_IOCTL(radeon_cp_setparam_kms)
735 KMS_INVALID_IOCTL(radeon_surface_alloc_kms)
736 KMS_INVALID_IOCTL(radeon_surface_free_kms)
739 const struct drm_ioctl_desc radeon_ioctls_kms[] = {
740 DRM_IOCTL_DEF_DRV(RADEON_CP_INIT, radeon_cp_init_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
741 DRM_IOCTL_DEF_DRV(RADEON_CP_START, radeon_cp_start_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
742 DRM_IOCTL_DEF_DRV(RADEON_CP_STOP, radeon_cp_stop_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
743 DRM_IOCTL_DEF_DRV(RADEON_CP_RESET, radeon_cp_reset_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
744 DRM_IOCTL_DEF_DRV(RADEON_CP_IDLE, radeon_cp_idle_kms, DRM_AUTH),
745 DRM_IOCTL_DEF_DRV(RADEON_CP_RESUME, radeon_cp_resume_kms, DRM_AUTH),
746 DRM_IOCTL_DEF_DRV(RADEON_RESET, radeon_engine_reset_kms, DRM_AUTH),
747 DRM_IOCTL_DEF_DRV(RADEON_FULLSCREEN, radeon_fullscreen_kms, DRM_AUTH),
748 DRM_IOCTL_DEF_DRV(RADEON_SWAP, radeon_cp_swap_kms, DRM_AUTH),
749 DRM_IOCTL_DEF_DRV(RADEON_CLEAR, radeon_cp_clear_kms, DRM_AUTH),
750 DRM_IOCTL_DEF_DRV(RADEON_VERTEX, radeon_cp_vertex_kms, DRM_AUTH),
751 DRM_IOCTL_DEF_DRV(RADEON_INDICES, radeon_cp_indices_kms, DRM_AUTH),
752 DRM_IOCTL_DEF_DRV(RADEON_TEXTURE, radeon_cp_texture_kms, DRM_AUTH),
753 DRM_IOCTL_DEF_DRV(RADEON_STIPPLE, radeon_cp_stipple_kms, DRM_AUTH),
754 DRM_IOCTL_DEF_DRV(RADEON_INDIRECT, radeon_cp_indirect_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
755 DRM_IOCTL_DEF_DRV(RADEON_VERTEX2, radeon_cp_vertex2_kms, DRM_AUTH),
756 DRM_IOCTL_DEF_DRV(RADEON_CMDBUF, radeon_cp_cmdbuf_kms, DRM_AUTH),
757 DRM_IOCTL_DEF_DRV(RADEON_GETPARAM, radeon_cp_getparam_kms, DRM_AUTH),
758 DRM_IOCTL_DEF_DRV(RADEON_FLIP, radeon_cp_flip_kms, DRM_AUTH),
759 DRM_IOCTL_DEF_DRV(RADEON_ALLOC, radeon_mem_alloc_kms, DRM_AUTH),
760 DRM_IOCTL_DEF_DRV(RADEON_FREE, radeon_mem_free_kms, DRM_AUTH),
761 DRM_IOCTL_DEF_DRV(RADEON_INIT_HEAP, radeon_mem_init_heap_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
762 DRM_IOCTL_DEF_DRV(RADEON_IRQ_EMIT, radeon_irq_emit_kms, DRM_AUTH),
763 DRM_IOCTL_DEF_DRV(RADEON_IRQ_WAIT, radeon_irq_wait_kms, DRM_AUTH),
764 DRM_IOCTL_DEF_DRV(RADEON_SETPARAM, radeon_cp_setparam_kms, DRM_AUTH),
765 DRM_IOCTL_DEF_DRV(RADEON_SURF_ALLOC, radeon_surface_alloc_kms, DRM_AUTH),
766 DRM_IOCTL_DEF_DRV(RADEON_SURF_FREE, radeon_surface_free_kms, DRM_AUTH),
768 DRM_IOCTL_DEF_DRV(RADEON_GEM_INFO, radeon_gem_info_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
769 DRM_IOCTL_DEF_DRV(RADEON_GEM_CREATE, radeon_gem_create_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
770 DRM_IOCTL_DEF_DRV(RADEON_GEM_MMAP, radeon_gem_mmap_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
771 DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_DOMAIN, radeon_gem_set_domain_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
772 DRM_IOCTL_DEF_DRV(RADEON_GEM_PREAD, radeon_gem_pread_ioctl, DRM_AUTH|DRM_UNLOCKED),
773 DRM_IOCTL_DEF_DRV(RADEON_GEM_PWRITE, radeon_gem_pwrite_ioctl, DRM_AUTH|DRM_UNLOCKED),
774 DRM_IOCTL_DEF_DRV(RADEON_GEM_WAIT_IDLE, radeon_gem_wait_idle_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
775 DRM_IOCTL_DEF_DRV(RADEON_CS, radeon_cs_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
776 DRM_IOCTL_DEF_DRV(RADEON_INFO, radeon_info_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
777 DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_TILING, radeon_gem_set_tiling_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
778 DRM_IOCTL_DEF_DRV(RADEON_GEM_GET_TILING, radeon_gem_get_tiling_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
779 DRM_IOCTL_DEF_DRV(RADEON_GEM_BUSY, radeon_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
780 DRM_IOCTL_DEF_DRV(RADEON_GEM_VA, radeon_gem_va_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
782 int radeon_max_kms_ioctl = DRM_ARRAY_SIZE(radeon_ioctls_kms);