2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
23 * Authors: Dave Airlie
26 #include <linux/export.h>
29 #include "radeon_drm.h"
37 bool radeon_ddc_probe(struct radeon_connector *radeon_connector)
42 struct i2c_msg msgs[] = {
57 /* on hw with routers, select right port */
58 if (radeon_connector->router.ddc_valid)
59 radeon_router_select_ddc_port(radeon_connector);
61 ret = i2c_transfer(&radeon_connector->ddc_bus->adapter, msgs, 2);
63 /* Couldn't find an accessible DDC on this connector */
65 /* Probe also for valid EDID header
66 * EDID header starts with:
67 * 0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00.
68 * Only the first 6 bytes must be valid as
69 * drm_edid_block_valid() can fix the last 2 bytes */
70 if (drm_edid_header_is_valid(buf) < 6) {
71 /* Couldn't find an accessible EDID on this
80 static int pre_xfer(struct i2c_adapter *i2c_adap)
82 struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
83 struct radeon_device *rdev = i2c->dev->dev_private;
84 struct radeon_i2c_bus_rec *rec = &i2c->rec;
87 /* RV410 appears to have a bug where the hw i2c in reset
88 * holds the i2c port in a bad state - switch hw i2c away before
89 * doing DDC - do this for all r200s/r300s/r400s for safety sake
91 if (rec->hw_capable) {
92 if ((rdev->family >= CHIP_R200) && !ASIC_IS_AVIVO(rdev)) {
95 if (rdev->family >= CHIP_RV350)
96 reg = RADEON_GPIO_MONID;
97 else if ((rdev->family == CHIP_R300) ||
98 (rdev->family == CHIP_R350))
99 reg = RADEON_GPIO_DVI_DDC;
101 reg = RADEON_GPIO_CRT2_DDC;
103 mutex_lock(&rdev->dc_hw_i2c_mutex);
104 if (rec->a_clk_reg == reg) {
105 WREG32(RADEON_DVI_I2C_CNTL_0, (RADEON_I2C_SOFT_RST |
106 R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1)));
108 WREG32(RADEON_DVI_I2C_CNTL_0, (RADEON_I2C_SOFT_RST |
109 R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3)));
111 mutex_unlock(&rdev->dc_hw_i2c_mutex);
115 /* switch the pads to ddc mode */
116 if (ASIC_IS_DCE3(rdev) && rec->hw_capable) {
117 temp = RREG32(rec->mask_clk_reg);
119 WREG32(rec->mask_clk_reg, temp);
122 /* clear the output pin values */
123 temp = RREG32(rec->a_clk_reg) & ~rec->a_clk_mask;
124 WREG32(rec->a_clk_reg, temp);
126 temp = RREG32(rec->a_data_reg) & ~rec->a_data_mask;
127 WREG32(rec->a_data_reg, temp);
129 /* set the pins to input */
130 temp = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask;
131 WREG32(rec->en_clk_reg, temp);
133 temp = RREG32(rec->en_data_reg) & ~rec->en_data_mask;
134 WREG32(rec->en_data_reg, temp);
136 /* mask the gpio pins for software use */
137 temp = RREG32(rec->mask_clk_reg) | rec->mask_clk_mask;
138 WREG32(rec->mask_clk_reg, temp);
139 temp = RREG32(rec->mask_clk_reg);
141 temp = RREG32(rec->mask_data_reg) | rec->mask_data_mask;
142 WREG32(rec->mask_data_reg, temp);
143 temp = RREG32(rec->mask_data_reg);
148 static void post_xfer(struct i2c_adapter *i2c_adap)
150 struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
151 struct radeon_device *rdev = i2c->dev->dev_private;
152 struct radeon_i2c_bus_rec *rec = &i2c->rec;
155 /* unmask the gpio pins for software use */
156 temp = RREG32(rec->mask_clk_reg) & ~rec->mask_clk_mask;
157 WREG32(rec->mask_clk_reg, temp);
158 temp = RREG32(rec->mask_clk_reg);
160 temp = RREG32(rec->mask_data_reg) & ~rec->mask_data_mask;
161 WREG32(rec->mask_data_reg, temp);
162 temp = RREG32(rec->mask_data_reg);
165 static int get_clock(void *i2c_priv)
167 struct radeon_i2c_chan *i2c = i2c_priv;
168 struct radeon_device *rdev = i2c->dev->dev_private;
169 struct radeon_i2c_bus_rec *rec = &i2c->rec;
172 /* read the value off the pin */
173 val = RREG32(rec->y_clk_reg);
174 val &= rec->y_clk_mask;
180 static int get_data(void *i2c_priv)
182 struct radeon_i2c_chan *i2c = i2c_priv;
183 struct radeon_device *rdev = i2c->dev->dev_private;
184 struct radeon_i2c_bus_rec *rec = &i2c->rec;
187 /* read the value off the pin */
188 val = RREG32(rec->y_data_reg);
189 val &= rec->y_data_mask;
194 static void set_clock(void *i2c_priv, int clock)
196 struct radeon_i2c_chan *i2c = i2c_priv;
197 struct radeon_device *rdev = i2c->dev->dev_private;
198 struct radeon_i2c_bus_rec *rec = &i2c->rec;
201 /* set pin direction */
202 val = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask;
203 val |= clock ? 0 : rec->en_clk_mask;
204 WREG32(rec->en_clk_reg, val);
207 static void set_data(void *i2c_priv, int data)
209 struct radeon_i2c_chan *i2c = i2c_priv;
210 struct radeon_device *rdev = i2c->dev->dev_private;
211 struct radeon_i2c_bus_rec *rec = &i2c->rec;
214 /* set pin direction */
215 val = RREG32(rec->en_data_reg) & ~rec->en_data_mask;
216 val |= data ? 0 : rec->en_data_mask;
217 WREG32(rec->en_data_reg, val);
222 static u32 radeon_get_i2c_prescale(struct radeon_device *rdev)
224 u32 sclk = rdev->pm.current_sclk;
230 switch (rdev->family) {
244 nm = (sclk * 10) / (i2c_clock * 4);
245 for (loop = 1; loop < 255; loop++) {
246 if ((nm / loop) < loop)
251 prescale = m | (n << 8);
259 prescale = (((sclk * 10)/(4 * 128 * 100) + 1) << 8) + 128;
273 if (rdev->family == CHIP_R520)
274 prescale = (127 << 8) + ((sclk * 10) / (4 * 127 * i2c_clock));
276 prescale = (((sclk * 10)/(4 * 128 * 100) + 1) << 8) + 128;
302 DRM_ERROR("i2c: unhandled radeon chip\n");
309 /* hw i2c engine for r1xx-4xx hardware
310 * hw can buffer up to 15 bytes
312 static int r100_hw_i2c_xfer(struct i2c_adapter *i2c_adap,
313 struct i2c_msg *msgs, int num)
315 struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
316 struct radeon_device *rdev = i2c->dev->dev_private;
317 struct radeon_i2c_bus_rec *rec = &i2c->rec;
319 int i, j, k, ret = num;
321 u32 i2c_cntl_0, i2c_cntl_1, i2c_data;
324 mutex_lock(&rdev->dc_hw_i2c_mutex);
325 /* take the pm lock since we need a constant sclk */
326 mutex_lock(&rdev->pm.mutex);
328 prescale = radeon_get_i2c_prescale(rdev);
330 reg = ((prescale << RADEON_I2C_PRESCALE_SHIFT) |
331 RADEON_I2C_DRIVE_EN |
336 if (rdev->is_atom_bios) {
337 tmp = RREG32(RADEON_BIOS_6_SCRATCH);
338 WREG32(RADEON_BIOS_6_SCRATCH, tmp | ATOM_S6_HW_I2C_BUSY_STATE);
342 i2c_cntl_0 = RADEON_I2C_CNTL_0;
343 i2c_cntl_1 = RADEON_I2C_CNTL_1;
344 i2c_data = RADEON_I2C_DATA;
346 i2c_cntl_0 = RADEON_DVI_I2C_CNTL_0;
347 i2c_cntl_1 = RADEON_DVI_I2C_CNTL_1;
348 i2c_data = RADEON_DVI_I2C_DATA;
350 switch (rdev->family) {
357 switch (rec->mask_clk_reg) {
358 case RADEON_GPIO_DVI_DDC:
359 /* no gpio select bit */
362 DRM_ERROR("gpio not supported with hw i2c\n");
368 /* only bit 4 on r200 */
369 switch (rec->mask_clk_reg) {
370 case RADEON_GPIO_DVI_DDC:
371 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1);
373 case RADEON_GPIO_MONID:
374 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3);
377 DRM_ERROR("gpio not supported with hw i2c\n");
385 switch (rec->mask_clk_reg) {
386 case RADEON_GPIO_DVI_DDC:
387 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1);
389 case RADEON_GPIO_VGA_DDC:
390 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC2);
392 case RADEON_GPIO_CRT2_DDC:
393 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3);
396 DRM_ERROR("gpio not supported with hw i2c\n");
403 /* only bit 4 on r300/r350 */
404 switch (rec->mask_clk_reg) {
405 case RADEON_GPIO_VGA_DDC:
406 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1);
408 case RADEON_GPIO_DVI_DDC:
409 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3);
412 DRM_ERROR("gpio not supported with hw i2c\n");
425 switch (rec->mask_clk_reg) {
426 case RADEON_GPIO_VGA_DDC:
427 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1);
429 case RADEON_GPIO_DVI_DDC:
430 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC2);
432 case RADEON_GPIO_MONID:
433 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3);
436 DRM_ERROR("gpio not supported with hw i2c\n");
442 DRM_ERROR("unsupported asic\n");
449 /* check for bus probe */
451 if ((num == 1) && (p->len == 0)) {
452 WREG32(i2c_cntl_0, (RADEON_I2C_DONE |
455 RADEON_I2C_SOFT_RST));
456 WREG32(i2c_data, (p->addr << 1) & 0xff);
458 WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) |
459 (1 << RADEON_I2C_ADDR_COUNT_SHIFT) |
461 (48 << RADEON_I2C_TIME_LIMIT_SHIFT)));
462 WREG32(i2c_cntl_0, reg);
463 for (k = 0; k < 32; k++) {
465 tmp = RREG32(i2c_cntl_0);
466 if (tmp & RADEON_I2C_GO)
468 tmp = RREG32(i2c_cntl_0);
469 if (tmp & RADEON_I2C_DONE)
472 DRM_DEBUG("i2c write error 0x%08x\n", tmp);
473 WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT);
481 for (i = 0; i < num; i++) {
483 for (j = 0; j < p->len; j++) {
484 if (p->flags & I2C_M_RD) {
485 WREG32(i2c_cntl_0, (RADEON_I2C_DONE |
488 RADEON_I2C_SOFT_RST));
489 WREG32(i2c_data, ((p->addr << 1) & 0xff) | 0x1);
490 WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) |
491 (1 << RADEON_I2C_ADDR_COUNT_SHIFT) |
493 (48 << RADEON_I2C_TIME_LIMIT_SHIFT)));
494 WREG32(i2c_cntl_0, reg | RADEON_I2C_RECEIVE);
495 for (k = 0; k < 32; k++) {
497 tmp = RREG32(i2c_cntl_0);
498 if (tmp & RADEON_I2C_GO)
500 tmp = RREG32(i2c_cntl_0);
501 if (tmp & RADEON_I2C_DONE)
504 DRM_DEBUG("i2c read error 0x%08x\n", tmp);
505 WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT);
510 p->buf[j] = RREG32(i2c_data) & 0xff;
512 WREG32(i2c_cntl_0, (RADEON_I2C_DONE |
515 RADEON_I2C_SOFT_RST));
516 WREG32(i2c_data, (p->addr << 1) & 0xff);
517 WREG32(i2c_data, p->buf[j]);
518 WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) |
519 (1 << RADEON_I2C_ADDR_COUNT_SHIFT) |
521 (48 << RADEON_I2C_TIME_LIMIT_SHIFT)));
522 WREG32(i2c_cntl_0, reg);
523 for (k = 0; k < 32; k++) {
525 tmp = RREG32(i2c_cntl_0);
526 if (tmp & RADEON_I2C_GO)
528 tmp = RREG32(i2c_cntl_0);
529 if (tmp & RADEON_I2C_DONE)
532 DRM_DEBUG("i2c write error 0x%08x\n", tmp);
533 WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT);
543 WREG32(i2c_cntl_0, 0);
544 WREG32(i2c_cntl_1, 0);
545 WREG32(i2c_cntl_0, (RADEON_I2C_DONE |
548 RADEON_I2C_SOFT_RST));
550 if (rdev->is_atom_bios) {
551 tmp = RREG32(RADEON_BIOS_6_SCRATCH);
552 tmp &= ~ATOM_S6_HW_I2C_BUSY_STATE;
553 WREG32(RADEON_BIOS_6_SCRATCH, tmp);
556 mutex_unlock(&rdev->pm.mutex);
557 mutex_unlock(&rdev->dc_hw_i2c_mutex);
562 /* hw i2c engine for r5xx hardware
563 * hw can buffer up to 15 bytes
565 static int r500_hw_i2c_xfer(struct i2c_adapter *i2c_adap,
566 struct i2c_msg *msgs, int num)
568 struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
569 struct radeon_device *rdev = i2c->dev->dev_private;
570 struct radeon_i2c_bus_rec *rec = &i2c->rec;
572 int i, j, remaining, current_count, buffer_offset, ret = num;
577 mutex_lock(&rdev->dc_hw_i2c_mutex);
578 /* take the pm lock since we need a constant sclk */
579 mutex_lock(&rdev->pm.mutex);
581 prescale = radeon_get_i2c_prescale(rdev);
583 /* clear gpio mask bits */
584 tmp = RREG32(rec->mask_clk_reg);
585 tmp &= ~rec->mask_clk_mask;
586 WREG32(rec->mask_clk_reg, tmp);
587 tmp = RREG32(rec->mask_clk_reg);
589 tmp = RREG32(rec->mask_data_reg);
590 tmp &= ~rec->mask_data_mask;
591 WREG32(rec->mask_data_reg, tmp);
592 tmp = RREG32(rec->mask_data_reg);
594 /* clear pin values */
595 tmp = RREG32(rec->a_clk_reg);
596 tmp &= ~rec->a_clk_mask;
597 WREG32(rec->a_clk_reg, tmp);
598 tmp = RREG32(rec->a_clk_reg);
600 tmp = RREG32(rec->a_data_reg);
601 tmp &= ~rec->a_data_mask;
602 WREG32(rec->a_data_reg, tmp);
603 tmp = RREG32(rec->a_data_reg);
605 /* set the pins to input */
606 tmp = RREG32(rec->en_clk_reg);
607 tmp &= ~rec->en_clk_mask;
608 WREG32(rec->en_clk_reg, tmp);
609 tmp = RREG32(rec->en_clk_reg);
611 tmp = RREG32(rec->en_data_reg);
612 tmp &= ~rec->en_data_mask;
613 WREG32(rec->en_data_reg, tmp);
614 tmp = RREG32(rec->en_data_reg);
617 tmp = RREG32(RADEON_BIOS_6_SCRATCH);
618 WREG32(RADEON_BIOS_6_SCRATCH, tmp | ATOM_S6_HW_I2C_BUSY_STATE);
619 saved1 = RREG32(AVIVO_DC_I2C_CONTROL1);
620 saved2 = RREG32(0x494);
621 WREG32(0x494, saved2 | 0x1);
623 WREG32(AVIVO_DC_I2C_ARBITRATION, AVIVO_DC_I2C_SW_WANTS_TO_USE_I2C);
624 for (i = 0; i < 50; i++) {
626 if (RREG32(AVIVO_DC_I2C_ARBITRATION) & AVIVO_DC_I2C_SW_CAN_USE_I2C)
630 DRM_ERROR("failed to get i2c bus\n");
635 reg = AVIVO_DC_I2C_START | AVIVO_DC_I2C_STOP | AVIVO_DC_I2C_EN;
636 switch (rec->mask_clk_reg) {
637 case AVIVO_DC_GPIO_DDC1_MASK:
638 reg |= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC1);
640 case AVIVO_DC_GPIO_DDC2_MASK:
641 reg |= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC2);
643 case AVIVO_DC_GPIO_DDC3_MASK:
644 reg |= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC3);
647 DRM_ERROR("gpio not supported with hw i2c\n");
652 /* check for bus probe */
654 if ((num == 1) && (p->len == 0)) {
655 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE |
658 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET);
660 WREG32(AVIVO_DC_I2C_RESET, 0);
662 WREG32(AVIVO_DC_I2C_DATA, (p->addr << 1) & 0xff);
663 WREG32(AVIVO_DC_I2C_DATA, 0);
665 WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48));
666 WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) |
667 AVIVO_DC_I2C_DATA_COUNT(1) |
669 WREG32(AVIVO_DC_I2C_CONTROL1, reg);
670 WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO);
671 for (j = 0; j < 200; j++) {
673 tmp = RREG32(AVIVO_DC_I2C_STATUS1);
674 if (tmp & AVIVO_DC_I2C_GO)
676 tmp = RREG32(AVIVO_DC_I2C_STATUS1);
677 if (tmp & AVIVO_DC_I2C_DONE)
680 DRM_DEBUG("i2c write error 0x%08x\n", tmp);
681 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT);
689 for (i = 0; i < num; i++) {
693 if (p->flags & I2C_M_RD) {
698 current_count = remaining;
699 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE |
702 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET);
704 WREG32(AVIVO_DC_I2C_RESET, 0);
706 WREG32(AVIVO_DC_I2C_DATA, ((p->addr << 1) & 0xff) | 0x1);
707 WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48));
708 WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) |
709 AVIVO_DC_I2C_DATA_COUNT(current_count) |
711 WREG32(AVIVO_DC_I2C_CONTROL1, reg | AVIVO_DC_I2C_RECEIVE);
712 WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO);
713 for (j = 0; j < 200; j++) {
715 tmp = RREG32(AVIVO_DC_I2C_STATUS1);
716 if (tmp & AVIVO_DC_I2C_GO)
718 tmp = RREG32(AVIVO_DC_I2C_STATUS1);
719 if (tmp & AVIVO_DC_I2C_DONE)
722 DRM_DEBUG("i2c read error 0x%08x\n", tmp);
723 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT);
728 for (j = 0; j < current_count; j++)
729 p->buf[buffer_offset + j] = RREG32(AVIVO_DC_I2C_DATA) & 0xff;
730 remaining -= current_count;
731 buffer_offset += current_count;
738 current_count = remaining;
739 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE |
742 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET);
744 WREG32(AVIVO_DC_I2C_RESET, 0);
746 WREG32(AVIVO_DC_I2C_DATA, (p->addr << 1) & 0xff);
747 for (j = 0; j < current_count; j++)
748 WREG32(AVIVO_DC_I2C_DATA, p->buf[buffer_offset + j]);
750 WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48));
751 WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) |
752 AVIVO_DC_I2C_DATA_COUNT(current_count) |
754 WREG32(AVIVO_DC_I2C_CONTROL1, reg);
755 WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO);
756 for (j = 0; j < 200; j++) {
758 tmp = RREG32(AVIVO_DC_I2C_STATUS1);
759 if (tmp & AVIVO_DC_I2C_GO)
761 tmp = RREG32(AVIVO_DC_I2C_STATUS1);
762 if (tmp & AVIVO_DC_I2C_DONE)
765 DRM_DEBUG("i2c write error 0x%08x\n", tmp);
766 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT);
771 remaining -= current_count;
772 buffer_offset += current_count;
778 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE |
781 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET);
783 WREG32(AVIVO_DC_I2C_RESET, 0);
785 WREG32(AVIVO_DC_I2C_ARBITRATION, AVIVO_DC_I2C_SW_DONE_USING_I2C);
786 WREG32(AVIVO_DC_I2C_CONTROL1, saved1);
787 WREG32(0x494, saved2);
788 tmp = RREG32(RADEON_BIOS_6_SCRATCH);
789 tmp &= ~ATOM_S6_HW_I2C_BUSY_STATE;
790 WREG32(RADEON_BIOS_6_SCRATCH, tmp);
792 mutex_unlock(&rdev->pm.mutex);
793 mutex_unlock(&rdev->dc_hw_i2c_mutex);
798 static int radeon_hw_i2c_xfer(struct i2c_adapter *i2c_adap,
799 struct i2c_msg *msgs, int num)
801 struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
802 struct radeon_device *rdev = i2c->dev->dev_private;
803 struct radeon_i2c_bus_rec *rec = &i2c->rec;
806 switch (rdev->family) {
825 ret = r100_hw_i2c_xfer(i2c_adap, msgs, num);
830 /* XXX fill in hw i2c implementation */
839 ret = r100_hw_i2c_xfer(i2c_adap, msgs, num);
841 ret = r500_hw_i2c_xfer(i2c_adap, msgs, num);
847 /* XXX fill in hw i2c implementation */
857 /* XXX fill in hw i2c implementation */
864 /* XXX fill in hw i2c implementation */
867 DRM_ERROR("i2c: unhandled radeon chip\n");
875 static u32 radeon_hw_i2c_func(struct i2c_adapter *adap)
877 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
880 static const struct i2c_algorithm radeon_i2c_algo = {
881 .master_xfer = radeon_hw_i2c_xfer,
882 .functionality = radeon_hw_i2c_func,
885 struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev,
886 struct radeon_i2c_bus_rec *rec,
889 struct radeon_device *rdev = dev->dev_private;
890 struct radeon_i2c_chan *i2c;
893 i2c = kzalloc(sizeof(struct radeon_i2c_chan), GFP_KERNEL);
898 i2c->adapter.owner = THIS_MODULE;
899 i2c->adapter.class = I2C_CLASS_DDC;
900 i2c->adapter.dev.parent = &dev->pdev->dev;
902 i2c_set_adapdata(&i2c->adapter, i2c);
906 ((rdev->family <= CHIP_RS480) ||
907 ((rdev->family >= CHIP_RV515) && (rdev->family <= CHIP_R580))))) {
908 /* set the radeon hw i2c adapter */
909 snprintf(i2c->adapter.name, sizeof(i2c->adapter.name),
910 "Radeon i2c hw bus %s", name);
911 i2c->adapter.algo = &radeon_i2c_algo;
912 ret = i2c_add_adapter(&i2c->adapter);
914 DRM_ERROR("Failed to register hw i2c %s\n", name);
918 /* set the radeon bit adapter */
919 snprintf(i2c->adapter.name, sizeof(i2c->adapter.name),
920 "Radeon i2c bit bus %s", name);
921 i2c->adapter.algo_data = &i2c->algo.bit;
922 i2c->algo.bit.pre_xfer = pre_xfer;
923 i2c->algo.bit.post_xfer = post_xfer;
924 i2c->algo.bit.setsda = set_data;
925 i2c->algo.bit.setscl = set_clock;
926 i2c->algo.bit.getsda = get_data;
927 i2c->algo.bit.getscl = get_clock;
928 i2c->algo.bit.udelay = 20;
929 /* vesa says 2.2 ms is enough, 1 jiffy doesn't seem to always
930 * make this, 2 jiffies is a lot more reliable */
931 i2c->algo.bit.timeout = 2;
932 i2c->algo.bit.data = i2c;
933 ret = i2c_bit_add_bus(&i2c->adapter);
935 DRM_ERROR("Failed to register bit i2c %s\n", name);
947 struct radeon_i2c_chan *radeon_i2c_create_dp(struct drm_device *dev,
948 struct radeon_i2c_bus_rec *rec,
951 struct radeon_i2c_chan *i2c;
954 i2c = kzalloc(sizeof(struct radeon_i2c_chan), GFP_KERNEL);
959 i2c->adapter.owner = THIS_MODULE;
960 i2c->adapter.class = I2C_CLASS_DDC;
961 i2c->adapter.dev.parent = &dev->pdev->dev;
963 snprintf(i2c->adapter.name, sizeof(i2c->adapter.name),
964 "Radeon aux bus %s", name);
965 i2c_set_adapdata(&i2c->adapter, i2c);
966 i2c->adapter.algo_data = &i2c->algo.dp;
967 i2c->algo.dp.aux_ch = radeon_dp_i2c_aux_ch;
968 i2c->algo.dp.address = 0;
969 ret = i2c_dp_aux_add_bus(&i2c->adapter);
971 DRM_INFO("Failed to register i2c %s\n", name);
982 void radeon_i2c_destroy(struct radeon_i2c_chan *i2c)
986 i2c_del_adapter(&i2c->adapter);
990 /* Add the default buses */
991 void radeon_i2c_init(struct radeon_device *rdev)
993 if (rdev->is_atom_bios)
994 radeon_atombios_i2c_init(rdev);
996 radeon_combios_i2c_init(rdev);
999 /* remove all the buses */
1000 void radeon_i2c_fini(struct radeon_device *rdev)
1004 for (i = 0; i < RADEON_MAX_I2C_BUS; i++) {
1005 if (rdev->i2c_bus[i]) {
1006 radeon_i2c_destroy(rdev->i2c_bus[i]);
1007 rdev->i2c_bus[i] = NULL;
1012 /* Add additional buses */
1013 void radeon_i2c_add(struct radeon_device *rdev,
1014 struct radeon_i2c_bus_rec *rec,
1017 struct drm_device *dev = rdev->ddev;
1020 for (i = 0; i < RADEON_MAX_I2C_BUS; i++) {
1021 if (!rdev->i2c_bus[i]) {
1022 rdev->i2c_bus[i] = radeon_i2c_create(dev, rec, name);
1028 /* looks up bus based on id */
1029 struct radeon_i2c_chan *radeon_i2c_lookup(struct radeon_device *rdev,
1030 struct radeon_i2c_bus_rec *i2c_bus)
1034 for (i = 0; i < RADEON_MAX_I2C_BUS; i++) {
1035 if (rdev->i2c_bus[i] &&
1036 (rdev->i2c_bus[i]->rec.i2c_id == i2c_bus->i2c_id)) {
1037 return rdev->i2c_bus[i];
1043 struct drm_encoder *radeon_best_encoder(struct drm_connector *connector)
1048 void radeon_i2c_get_byte(struct radeon_i2c_chan *i2c_bus,
1055 struct i2c_msg msgs[] = {
1073 if (i2c_transfer(&i2c_bus->adapter, msgs, 2) == 2) {
1075 DRM_DEBUG("val = 0x%02x\n", *val);
1077 DRM_DEBUG("i2c 0x%02x 0x%02x read failed\n",
1082 void radeon_i2c_put_byte(struct radeon_i2c_chan *i2c_bus,
1088 struct i2c_msg msg = {
1098 if (i2c_transfer(&i2c_bus->adapter, &msg, 1) != 1)
1099 DRM_DEBUG("i2c 0x%02x 0x%02x write failed\n",
1103 /* ddc router switching */
1104 void radeon_router_select_ddc_port(struct radeon_connector *radeon_connector)
1108 if (!radeon_connector->router.ddc_valid)
1111 if (!radeon_connector->router_bus)
1114 radeon_i2c_get_byte(radeon_connector->router_bus,
1115 radeon_connector->router.i2c_addr,
1117 val &= ~radeon_connector->router.ddc_mux_control_pin;
1118 radeon_i2c_put_byte(radeon_connector->router_bus,
1119 radeon_connector->router.i2c_addr,
1121 radeon_i2c_get_byte(radeon_connector->router_bus,
1122 radeon_connector->router.i2c_addr,
1124 val &= ~radeon_connector->router.ddc_mux_control_pin;
1125 val |= radeon_connector->router.ddc_mux_state;
1126 radeon_i2c_put_byte(radeon_connector->router_bus,
1127 radeon_connector->router.i2c_addr,
1131 /* clock/data router switching */
1132 void radeon_router_select_cd_port(struct radeon_connector *radeon_connector)
1136 if (!radeon_connector->router.cd_valid)
1139 if (!radeon_connector->router_bus)
1142 radeon_i2c_get_byte(radeon_connector->router_bus,
1143 radeon_connector->router.i2c_addr,
1145 val &= ~radeon_connector->router.cd_mux_control_pin;
1146 radeon_i2c_put_byte(radeon_connector->router_bus,
1147 radeon_connector->router.i2c_addr,
1149 radeon_i2c_get_byte(radeon_connector->router_bus,
1150 radeon_connector->router.i2c_addr,
1152 val &= ~radeon_connector->router.cd_mux_control_pin;
1153 val |= radeon_connector->router.cd_mux_state;
1154 radeon_i2c_put_byte(radeon_connector->router_bus,
1155 radeon_connector->router.i2c_addr,