2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
23 * Authors: Dave Airlie
26 #include <linux/export.h>
30 #include "radeon_drm.h"
34 extern int radeon_atom_hw_i2c_xfer(struct i2c_adapter *i2c_adap,
35 struct i2c_msg *msgs, int num);
36 extern u32 radeon_atom_hw_i2c_func(struct i2c_adapter *adap);
42 bool radeon_ddc_probe(struct radeon_connector *radeon_connector)
47 struct i2c_msg msgs[] = {
62 /* on hw with routers, select right port */
63 if (radeon_connector->router.ddc_valid)
64 radeon_router_select_ddc_port(radeon_connector);
66 ret = i2c_transfer(&radeon_connector->ddc_bus->adapter, msgs, 2);
68 /* Couldn't find an accessible DDC on this connector */
70 /* Probe also for valid EDID header
71 * EDID header starts with:
72 * 0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00.
73 * Only the first 6 bytes must be valid as
74 * drm_edid_block_valid() can fix the last 2 bytes */
75 if (drm_edid_header_is_valid(buf) < 6) {
76 /* Couldn't find an accessible EDID on this
85 static int pre_xfer(struct i2c_adapter *i2c_adap)
87 struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
88 struct radeon_device *rdev = i2c->dev->dev_private;
89 struct radeon_i2c_bus_rec *rec = &i2c->rec;
92 /* RV410 appears to have a bug where the hw i2c in reset
93 * holds the i2c port in a bad state - switch hw i2c away before
94 * doing DDC - do this for all r200s/r300s/r400s for safety sake
96 if (rec->hw_capable) {
97 if ((rdev->family >= CHIP_R200) && !ASIC_IS_AVIVO(rdev)) {
100 if (rdev->family >= CHIP_RV350)
101 reg = RADEON_GPIO_MONID;
102 else if ((rdev->family == CHIP_R300) ||
103 (rdev->family == CHIP_R350))
104 reg = RADEON_GPIO_DVI_DDC;
106 reg = RADEON_GPIO_CRT2_DDC;
108 mutex_lock(&rdev->dc_hw_i2c_mutex);
109 if (rec->a_clk_reg == reg) {
110 WREG32(RADEON_DVI_I2C_CNTL_0, (RADEON_I2C_SOFT_RST |
111 R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1)));
113 WREG32(RADEON_DVI_I2C_CNTL_0, (RADEON_I2C_SOFT_RST |
114 R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3)));
116 mutex_unlock(&rdev->dc_hw_i2c_mutex);
120 /* switch the pads to ddc mode */
121 if (ASIC_IS_DCE3(rdev) && rec->hw_capable) {
122 temp = RREG32(rec->mask_clk_reg);
124 WREG32(rec->mask_clk_reg, temp);
127 /* clear the output pin values */
128 temp = RREG32(rec->a_clk_reg) & ~rec->a_clk_mask;
129 WREG32(rec->a_clk_reg, temp);
131 temp = RREG32(rec->a_data_reg) & ~rec->a_data_mask;
132 WREG32(rec->a_data_reg, temp);
134 /* set the pins to input */
135 temp = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask;
136 WREG32(rec->en_clk_reg, temp);
138 temp = RREG32(rec->en_data_reg) & ~rec->en_data_mask;
139 WREG32(rec->en_data_reg, temp);
141 /* mask the gpio pins for software use */
142 temp = RREG32(rec->mask_clk_reg) | rec->mask_clk_mask;
143 WREG32(rec->mask_clk_reg, temp);
144 temp = RREG32(rec->mask_clk_reg);
146 temp = RREG32(rec->mask_data_reg) | rec->mask_data_mask;
147 WREG32(rec->mask_data_reg, temp);
148 temp = RREG32(rec->mask_data_reg);
153 static void post_xfer(struct i2c_adapter *i2c_adap)
155 struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
156 struct radeon_device *rdev = i2c->dev->dev_private;
157 struct radeon_i2c_bus_rec *rec = &i2c->rec;
160 /* unmask the gpio pins for software use */
161 temp = RREG32(rec->mask_clk_reg) & ~rec->mask_clk_mask;
162 WREG32(rec->mask_clk_reg, temp);
163 temp = RREG32(rec->mask_clk_reg);
165 temp = RREG32(rec->mask_data_reg) & ~rec->mask_data_mask;
166 WREG32(rec->mask_data_reg, temp);
167 temp = RREG32(rec->mask_data_reg);
170 static int get_clock(void *i2c_priv)
172 struct radeon_i2c_chan *i2c = i2c_priv;
173 struct radeon_device *rdev = i2c->dev->dev_private;
174 struct radeon_i2c_bus_rec *rec = &i2c->rec;
177 /* read the value off the pin */
178 val = RREG32(rec->y_clk_reg);
179 val &= rec->y_clk_mask;
185 static int get_data(void *i2c_priv)
187 struct radeon_i2c_chan *i2c = i2c_priv;
188 struct radeon_device *rdev = i2c->dev->dev_private;
189 struct radeon_i2c_bus_rec *rec = &i2c->rec;
192 /* read the value off the pin */
193 val = RREG32(rec->y_data_reg);
194 val &= rec->y_data_mask;
199 static void set_clock(void *i2c_priv, int clock)
201 struct radeon_i2c_chan *i2c = i2c_priv;
202 struct radeon_device *rdev = i2c->dev->dev_private;
203 struct radeon_i2c_bus_rec *rec = &i2c->rec;
206 /* set pin direction */
207 val = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask;
208 val |= clock ? 0 : rec->en_clk_mask;
209 WREG32(rec->en_clk_reg, val);
212 static void set_data(void *i2c_priv, int data)
214 struct radeon_i2c_chan *i2c = i2c_priv;
215 struct radeon_device *rdev = i2c->dev->dev_private;
216 struct radeon_i2c_bus_rec *rec = &i2c->rec;
219 /* set pin direction */
220 val = RREG32(rec->en_data_reg) & ~rec->en_data_mask;
221 val |= data ? 0 : rec->en_data_mask;
222 WREG32(rec->en_data_reg, val);
227 static u32 radeon_get_i2c_prescale(struct radeon_device *rdev)
229 u32 sclk = rdev->pm.current_sclk;
235 switch (rdev->family) {
249 nm = (sclk * 10) / (i2c_clock * 4);
250 for (loop = 1; loop < 255; loop++) {
251 if ((nm / loop) < loop)
256 prescale = m | (n << 8);
264 prescale = (((sclk * 10)/(4 * 128 * 100) + 1) << 8) + 128;
278 if (rdev->family == CHIP_R520)
279 prescale = (127 << 8) + ((sclk * 10) / (4 * 127 * i2c_clock));
281 prescale = (((sclk * 10)/(4 * 128 * 100) + 1) << 8) + 128;
307 DRM_ERROR("i2c: unhandled radeon chip\n");
314 /* hw i2c engine for r1xx-4xx hardware
315 * hw can buffer up to 15 bytes
317 static int r100_hw_i2c_xfer(struct i2c_adapter *i2c_adap,
318 struct i2c_msg *msgs, int num)
320 struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
321 struct radeon_device *rdev = i2c->dev->dev_private;
322 struct radeon_i2c_bus_rec *rec = &i2c->rec;
324 int i, j, k, ret = num;
326 u32 i2c_cntl_0, i2c_cntl_1, i2c_data;
329 mutex_lock(&rdev->dc_hw_i2c_mutex);
330 /* take the pm lock since we need a constant sclk */
331 mutex_lock(&rdev->pm.mutex);
333 prescale = radeon_get_i2c_prescale(rdev);
335 reg = ((prescale << RADEON_I2C_PRESCALE_SHIFT) |
336 RADEON_I2C_DRIVE_EN |
341 if (rdev->is_atom_bios) {
342 tmp = RREG32(RADEON_BIOS_6_SCRATCH);
343 WREG32(RADEON_BIOS_6_SCRATCH, tmp | ATOM_S6_HW_I2C_BUSY_STATE);
347 i2c_cntl_0 = RADEON_I2C_CNTL_0;
348 i2c_cntl_1 = RADEON_I2C_CNTL_1;
349 i2c_data = RADEON_I2C_DATA;
351 i2c_cntl_0 = RADEON_DVI_I2C_CNTL_0;
352 i2c_cntl_1 = RADEON_DVI_I2C_CNTL_1;
353 i2c_data = RADEON_DVI_I2C_DATA;
355 switch (rdev->family) {
362 switch (rec->mask_clk_reg) {
363 case RADEON_GPIO_DVI_DDC:
364 /* no gpio select bit */
367 DRM_ERROR("gpio not supported with hw i2c\n");
373 /* only bit 4 on r200 */
374 switch (rec->mask_clk_reg) {
375 case RADEON_GPIO_DVI_DDC:
376 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1);
378 case RADEON_GPIO_MONID:
379 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3);
382 DRM_ERROR("gpio not supported with hw i2c\n");
390 switch (rec->mask_clk_reg) {
391 case RADEON_GPIO_DVI_DDC:
392 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1);
394 case RADEON_GPIO_VGA_DDC:
395 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC2);
397 case RADEON_GPIO_CRT2_DDC:
398 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3);
401 DRM_ERROR("gpio not supported with hw i2c\n");
408 /* only bit 4 on r300/r350 */
409 switch (rec->mask_clk_reg) {
410 case RADEON_GPIO_VGA_DDC:
411 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1);
413 case RADEON_GPIO_DVI_DDC:
414 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3);
417 DRM_ERROR("gpio not supported with hw i2c\n");
430 switch (rec->mask_clk_reg) {
431 case RADEON_GPIO_VGA_DDC:
432 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1);
434 case RADEON_GPIO_DVI_DDC:
435 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC2);
437 case RADEON_GPIO_MONID:
438 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3);
441 DRM_ERROR("gpio not supported with hw i2c\n");
447 DRM_ERROR("unsupported asic\n");
454 /* check for bus probe */
456 if ((num == 1) && (p->len == 0)) {
457 WREG32(i2c_cntl_0, (RADEON_I2C_DONE |
460 RADEON_I2C_SOFT_RST));
461 WREG32(i2c_data, (p->addr << 1) & 0xff);
463 WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) |
464 (1 << RADEON_I2C_ADDR_COUNT_SHIFT) |
466 (48 << RADEON_I2C_TIME_LIMIT_SHIFT)));
467 WREG32(i2c_cntl_0, reg);
468 for (k = 0; k < 32; k++) {
470 tmp = RREG32(i2c_cntl_0);
471 if (tmp & RADEON_I2C_GO)
473 tmp = RREG32(i2c_cntl_0);
474 if (tmp & RADEON_I2C_DONE)
477 DRM_DEBUG("i2c write error 0x%08x\n", tmp);
478 WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT);
486 for (i = 0; i < num; i++) {
488 for (j = 0; j < p->len; j++) {
489 if (p->flags & I2C_M_RD) {
490 WREG32(i2c_cntl_0, (RADEON_I2C_DONE |
493 RADEON_I2C_SOFT_RST));
494 WREG32(i2c_data, ((p->addr << 1) & 0xff) | 0x1);
495 WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) |
496 (1 << RADEON_I2C_ADDR_COUNT_SHIFT) |
498 (48 << RADEON_I2C_TIME_LIMIT_SHIFT)));
499 WREG32(i2c_cntl_0, reg | RADEON_I2C_RECEIVE);
500 for (k = 0; k < 32; k++) {
502 tmp = RREG32(i2c_cntl_0);
503 if (tmp & RADEON_I2C_GO)
505 tmp = RREG32(i2c_cntl_0);
506 if (tmp & RADEON_I2C_DONE)
509 DRM_DEBUG("i2c read error 0x%08x\n", tmp);
510 WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT);
515 p->buf[j] = RREG32(i2c_data) & 0xff;
517 WREG32(i2c_cntl_0, (RADEON_I2C_DONE |
520 RADEON_I2C_SOFT_RST));
521 WREG32(i2c_data, (p->addr << 1) & 0xff);
522 WREG32(i2c_data, p->buf[j]);
523 WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) |
524 (1 << RADEON_I2C_ADDR_COUNT_SHIFT) |
526 (48 << RADEON_I2C_TIME_LIMIT_SHIFT)));
527 WREG32(i2c_cntl_0, reg);
528 for (k = 0; k < 32; k++) {
530 tmp = RREG32(i2c_cntl_0);
531 if (tmp & RADEON_I2C_GO)
533 tmp = RREG32(i2c_cntl_0);
534 if (tmp & RADEON_I2C_DONE)
537 DRM_DEBUG("i2c write error 0x%08x\n", tmp);
538 WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT);
548 WREG32(i2c_cntl_0, 0);
549 WREG32(i2c_cntl_1, 0);
550 WREG32(i2c_cntl_0, (RADEON_I2C_DONE |
553 RADEON_I2C_SOFT_RST));
555 if (rdev->is_atom_bios) {
556 tmp = RREG32(RADEON_BIOS_6_SCRATCH);
557 tmp &= ~ATOM_S6_HW_I2C_BUSY_STATE;
558 WREG32(RADEON_BIOS_6_SCRATCH, tmp);
561 mutex_unlock(&rdev->pm.mutex);
562 mutex_unlock(&rdev->dc_hw_i2c_mutex);
567 /* hw i2c engine for r5xx hardware
568 * hw can buffer up to 15 bytes
570 static int r500_hw_i2c_xfer(struct i2c_adapter *i2c_adap,
571 struct i2c_msg *msgs, int num)
573 struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
574 struct radeon_device *rdev = i2c->dev->dev_private;
575 struct radeon_i2c_bus_rec *rec = &i2c->rec;
577 int i, j, remaining, current_count, buffer_offset, ret = num;
582 mutex_lock(&rdev->dc_hw_i2c_mutex);
583 /* take the pm lock since we need a constant sclk */
584 mutex_lock(&rdev->pm.mutex);
586 prescale = radeon_get_i2c_prescale(rdev);
588 /* clear gpio mask bits */
589 tmp = RREG32(rec->mask_clk_reg);
590 tmp &= ~rec->mask_clk_mask;
591 WREG32(rec->mask_clk_reg, tmp);
592 tmp = RREG32(rec->mask_clk_reg);
594 tmp = RREG32(rec->mask_data_reg);
595 tmp &= ~rec->mask_data_mask;
596 WREG32(rec->mask_data_reg, tmp);
597 tmp = RREG32(rec->mask_data_reg);
599 /* clear pin values */
600 tmp = RREG32(rec->a_clk_reg);
601 tmp &= ~rec->a_clk_mask;
602 WREG32(rec->a_clk_reg, tmp);
603 tmp = RREG32(rec->a_clk_reg);
605 tmp = RREG32(rec->a_data_reg);
606 tmp &= ~rec->a_data_mask;
607 WREG32(rec->a_data_reg, tmp);
608 tmp = RREG32(rec->a_data_reg);
610 /* set the pins to input */
611 tmp = RREG32(rec->en_clk_reg);
612 tmp &= ~rec->en_clk_mask;
613 WREG32(rec->en_clk_reg, tmp);
614 tmp = RREG32(rec->en_clk_reg);
616 tmp = RREG32(rec->en_data_reg);
617 tmp &= ~rec->en_data_mask;
618 WREG32(rec->en_data_reg, tmp);
619 tmp = RREG32(rec->en_data_reg);
622 tmp = RREG32(RADEON_BIOS_6_SCRATCH);
623 WREG32(RADEON_BIOS_6_SCRATCH, tmp | ATOM_S6_HW_I2C_BUSY_STATE);
624 saved1 = RREG32(AVIVO_DC_I2C_CONTROL1);
625 saved2 = RREG32(0x494);
626 WREG32(0x494, saved2 | 0x1);
628 WREG32(AVIVO_DC_I2C_ARBITRATION, AVIVO_DC_I2C_SW_WANTS_TO_USE_I2C);
629 for (i = 0; i < 50; i++) {
631 if (RREG32(AVIVO_DC_I2C_ARBITRATION) & AVIVO_DC_I2C_SW_CAN_USE_I2C)
635 DRM_ERROR("failed to get i2c bus\n");
640 reg = AVIVO_DC_I2C_START | AVIVO_DC_I2C_STOP | AVIVO_DC_I2C_EN;
641 switch (rec->mask_clk_reg) {
642 case AVIVO_DC_GPIO_DDC1_MASK:
643 reg |= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC1);
645 case AVIVO_DC_GPIO_DDC2_MASK:
646 reg |= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC2);
648 case AVIVO_DC_GPIO_DDC3_MASK:
649 reg |= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC3);
652 DRM_ERROR("gpio not supported with hw i2c\n");
657 /* check for bus probe */
659 if ((num == 1) && (p->len == 0)) {
660 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE |
663 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET);
665 WREG32(AVIVO_DC_I2C_RESET, 0);
667 WREG32(AVIVO_DC_I2C_DATA, (p->addr << 1) & 0xff);
668 WREG32(AVIVO_DC_I2C_DATA, 0);
670 WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48));
671 WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) |
672 AVIVO_DC_I2C_DATA_COUNT(1) |
674 WREG32(AVIVO_DC_I2C_CONTROL1, reg);
675 WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO);
676 for (j = 0; j < 200; j++) {
678 tmp = RREG32(AVIVO_DC_I2C_STATUS1);
679 if (tmp & AVIVO_DC_I2C_GO)
681 tmp = RREG32(AVIVO_DC_I2C_STATUS1);
682 if (tmp & AVIVO_DC_I2C_DONE)
685 DRM_DEBUG("i2c write error 0x%08x\n", tmp);
686 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT);
694 for (i = 0; i < num; i++) {
698 if (p->flags & I2C_M_RD) {
703 current_count = remaining;
704 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE |
707 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET);
709 WREG32(AVIVO_DC_I2C_RESET, 0);
711 WREG32(AVIVO_DC_I2C_DATA, ((p->addr << 1) & 0xff) | 0x1);
712 WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48));
713 WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) |
714 AVIVO_DC_I2C_DATA_COUNT(current_count) |
716 WREG32(AVIVO_DC_I2C_CONTROL1, reg | AVIVO_DC_I2C_RECEIVE);
717 WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO);
718 for (j = 0; j < 200; j++) {
720 tmp = RREG32(AVIVO_DC_I2C_STATUS1);
721 if (tmp & AVIVO_DC_I2C_GO)
723 tmp = RREG32(AVIVO_DC_I2C_STATUS1);
724 if (tmp & AVIVO_DC_I2C_DONE)
727 DRM_DEBUG("i2c read error 0x%08x\n", tmp);
728 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT);
733 for (j = 0; j < current_count; j++)
734 p->buf[buffer_offset + j] = RREG32(AVIVO_DC_I2C_DATA) & 0xff;
735 remaining -= current_count;
736 buffer_offset += current_count;
743 current_count = remaining;
744 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE |
747 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET);
749 WREG32(AVIVO_DC_I2C_RESET, 0);
751 WREG32(AVIVO_DC_I2C_DATA, (p->addr << 1) & 0xff);
752 for (j = 0; j < current_count; j++)
753 WREG32(AVIVO_DC_I2C_DATA, p->buf[buffer_offset + j]);
755 WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48));
756 WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) |
757 AVIVO_DC_I2C_DATA_COUNT(current_count) |
759 WREG32(AVIVO_DC_I2C_CONTROL1, reg);
760 WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO);
761 for (j = 0; j < 200; j++) {
763 tmp = RREG32(AVIVO_DC_I2C_STATUS1);
764 if (tmp & AVIVO_DC_I2C_GO)
766 tmp = RREG32(AVIVO_DC_I2C_STATUS1);
767 if (tmp & AVIVO_DC_I2C_DONE)
770 DRM_DEBUG("i2c write error 0x%08x\n", tmp);
771 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT);
776 remaining -= current_count;
777 buffer_offset += current_count;
783 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE |
786 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET);
788 WREG32(AVIVO_DC_I2C_RESET, 0);
790 WREG32(AVIVO_DC_I2C_ARBITRATION, AVIVO_DC_I2C_SW_DONE_USING_I2C);
791 WREG32(AVIVO_DC_I2C_CONTROL1, saved1);
792 WREG32(0x494, saved2);
793 tmp = RREG32(RADEON_BIOS_6_SCRATCH);
794 tmp &= ~ATOM_S6_HW_I2C_BUSY_STATE;
795 WREG32(RADEON_BIOS_6_SCRATCH, tmp);
797 mutex_unlock(&rdev->pm.mutex);
798 mutex_unlock(&rdev->dc_hw_i2c_mutex);
803 static int radeon_hw_i2c_xfer(struct i2c_adapter *i2c_adap,
804 struct i2c_msg *msgs, int num)
806 struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
807 struct radeon_device *rdev = i2c->dev->dev_private;
808 struct radeon_i2c_bus_rec *rec = &i2c->rec;
811 switch (rdev->family) {
830 ret = r100_hw_i2c_xfer(i2c_adap, msgs, num);
835 /* XXX fill in hw i2c implementation */
844 ret = r100_hw_i2c_xfer(i2c_adap, msgs, num);
846 ret = r500_hw_i2c_xfer(i2c_adap, msgs, num);
852 /* XXX fill in hw i2c implementation */
862 /* XXX fill in hw i2c implementation */
869 /* XXX fill in hw i2c implementation */
872 DRM_ERROR("i2c: unhandled radeon chip\n");
880 static u32 radeon_hw_i2c_func(struct i2c_adapter *adap)
882 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
885 static const struct i2c_algorithm radeon_i2c_algo = {
886 .master_xfer = radeon_hw_i2c_xfer,
887 .functionality = radeon_hw_i2c_func,
890 static const struct i2c_algorithm radeon_atom_i2c_algo = {
891 .master_xfer = radeon_atom_hw_i2c_xfer,
892 .functionality = radeon_atom_hw_i2c_func,
895 struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev,
896 struct radeon_i2c_bus_rec *rec,
899 struct radeon_device *rdev = dev->dev_private;
900 struct radeon_i2c_chan *i2c;
903 /* don't add the mm_i2c bus unless hw_i2c is enabled */
904 if (rec->mm_i2c && (radeon_hw_i2c == 0))
907 i2c = kzalloc(sizeof(struct radeon_i2c_chan), GFP_KERNEL);
912 i2c->adapter.owner = THIS_MODULE;
913 i2c->adapter.class = I2C_CLASS_DDC;
914 i2c->adapter.dev.parent = &dev->pdev->dev;
916 i2c_set_adapdata(&i2c->adapter, i2c);
920 ((rdev->family <= CHIP_RS480) ||
921 ((rdev->family >= CHIP_RV515) && (rdev->family <= CHIP_R580))))) {
922 /* set the radeon hw i2c adapter */
923 snprintf(i2c->adapter.name, sizeof(i2c->adapter.name),
924 "Radeon i2c hw bus %s", name);
925 i2c->adapter.algo = &radeon_i2c_algo;
926 ret = i2c_add_adapter(&i2c->adapter);
928 DRM_ERROR("Failed to register hw i2c %s\n", name);
931 } else if (rec->hw_capable &&
933 ASIC_IS_DCE3(rdev)) {
934 /* hw i2c using atom */
935 snprintf(i2c->adapter.name, sizeof(i2c->adapter.name),
936 "Radeon i2c hw bus %s", name);
937 i2c->adapter.algo = &radeon_atom_i2c_algo;
938 ret = i2c_add_adapter(&i2c->adapter);
940 DRM_ERROR("Failed to register hw i2c %s\n", name);
944 /* set the radeon bit adapter */
945 snprintf(i2c->adapter.name, sizeof(i2c->adapter.name),
946 "Radeon i2c bit bus %s", name);
947 i2c->adapter.algo_data = &i2c->algo.bit;
948 i2c->algo.bit.pre_xfer = pre_xfer;
949 i2c->algo.bit.post_xfer = post_xfer;
950 i2c->algo.bit.setsda = set_data;
951 i2c->algo.bit.setscl = set_clock;
952 i2c->algo.bit.getsda = get_data;
953 i2c->algo.bit.getscl = get_clock;
954 i2c->algo.bit.udelay = 10;
955 i2c->algo.bit.timeout = usecs_to_jiffies(2200); /* from VESA */
956 i2c->algo.bit.data = i2c;
957 ret = i2c_bit_add_bus(&i2c->adapter);
959 DRM_ERROR("Failed to register bit i2c %s\n", name);
971 struct radeon_i2c_chan *radeon_i2c_create_dp(struct drm_device *dev,
972 struct radeon_i2c_bus_rec *rec,
975 struct radeon_i2c_chan *i2c;
978 i2c = kzalloc(sizeof(struct radeon_i2c_chan), GFP_KERNEL);
983 i2c->adapter.owner = THIS_MODULE;
984 i2c->adapter.class = I2C_CLASS_DDC;
985 i2c->adapter.dev.parent = &dev->pdev->dev;
987 snprintf(i2c->adapter.name, sizeof(i2c->adapter.name),
988 "Radeon aux bus %s", name);
989 i2c_set_adapdata(&i2c->adapter, i2c);
990 i2c->adapter.algo_data = &i2c->algo.dp;
991 i2c->algo.dp.aux_ch = radeon_dp_i2c_aux_ch;
992 i2c->algo.dp.address = 0;
993 ret = i2c_dp_aux_add_bus(&i2c->adapter);
995 DRM_INFO("Failed to register i2c %s\n", name);
1006 void radeon_i2c_destroy(struct radeon_i2c_chan *i2c)
1010 i2c_del_adapter(&i2c->adapter);
1014 /* Add the default buses */
1015 void radeon_i2c_init(struct radeon_device *rdev)
1017 if (rdev->is_atom_bios)
1018 radeon_atombios_i2c_init(rdev);
1020 radeon_combios_i2c_init(rdev);
1023 /* remove all the buses */
1024 void radeon_i2c_fini(struct radeon_device *rdev)
1028 for (i = 0; i < RADEON_MAX_I2C_BUS; i++) {
1029 if (rdev->i2c_bus[i]) {
1030 radeon_i2c_destroy(rdev->i2c_bus[i]);
1031 rdev->i2c_bus[i] = NULL;
1036 /* Add additional buses */
1037 void radeon_i2c_add(struct radeon_device *rdev,
1038 struct radeon_i2c_bus_rec *rec,
1041 struct drm_device *dev = rdev->ddev;
1044 for (i = 0; i < RADEON_MAX_I2C_BUS; i++) {
1045 if (!rdev->i2c_bus[i]) {
1046 rdev->i2c_bus[i] = radeon_i2c_create(dev, rec, name);
1052 /* looks up bus based on id */
1053 struct radeon_i2c_chan *radeon_i2c_lookup(struct radeon_device *rdev,
1054 struct radeon_i2c_bus_rec *i2c_bus)
1058 for (i = 0; i < RADEON_MAX_I2C_BUS; i++) {
1059 if (rdev->i2c_bus[i] &&
1060 (rdev->i2c_bus[i]->rec.i2c_id == i2c_bus->i2c_id)) {
1061 return rdev->i2c_bus[i];
1067 struct drm_encoder *radeon_best_encoder(struct drm_connector *connector)
1072 void radeon_i2c_get_byte(struct radeon_i2c_chan *i2c_bus,
1079 struct i2c_msg msgs[] = {
1097 if (i2c_transfer(&i2c_bus->adapter, msgs, 2) == 2) {
1099 DRM_DEBUG("val = 0x%02x\n", *val);
1101 DRM_DEBUG("i2c 0x%02x 0x%02x read failed\n",
1106 void radeon_i2c_put_byte(struct radeon_i2c_chan *i2c_bus,
1112 struct i2c_msg msg = {
1122 if (i2c_transfer(&i2c_bus->adapter, &msg, 1) != 1)
1123 DRM_DEBUG("i2c 0x%02x 0x%02x write failed\n",
1127 /* ddc router switching */
1128 void radeon_router_select_ddc_port(struct radeon_connector *radeon_connector)
1132 if (!radeon_connector->router.ddc_valid)
1135 if (!radeon_connector->router_bus)
1138 radeon_i2c_get_byte(radeon_connector->router_bus,
1139 radeon_connector->router.i2c_addr,
1141 val &= ~radeon_connector->router.ddc_mux_control_pin;
1142 radeon_i2c_put_byte(radeon_connector->router_bus,
1143 radeon_connector->router.i2c_addr,
1145 radeon_i2c_get_byte(radeon_connector->router_bus,
1146 radeon_connector->router.i2c_addr,
1148 val &= ~radeon_connector->router.ddc_mux_control_pin;
1149 val |= radeon_connector->router.ddc_mux_state;
1150 radeon_i2c_put_byte(radeon_connector->router_bus,
1151 radeon_connector->router.i2c_addr,
1155 /* clock/data router switching */
1156 void radeon_router_select_cd_port(struct radeon_connector *radeon_connector)
1160 if (!radeon_connector->router.cd_valid)
1163 if (!radeon_connector->router_bus)
1166 radeon_i2c_get_byte(radeon_connector->router_bus,
1167 radeon_connector->router.i2c_addr,
1169 val &= ~radeon_connector->router.cd_mux_control_pin;
1170 radeon_i2c_put_byte(radeon_connector->router_bus,
1171 radeon_connector->router.i2c_addr,
1173 radeon_i2c_get_byte(radeon_connector->router_bus,
1174 radeon_connector->router.i2c_addr,
1176 val &= ~radeon_connector->router.cd_mux_control_pin;
1177 val |= radeon_connector->router.cd_mux_state;
1178 radeon_i2c_put_byte(radeon_connector->router_bus,
1179 radeon_connector->router.i2c_addr,