drivers/gpu/drm/radeon/radeon_display.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include <drm/drmP.h>
  27 #include <drm/radeon_drm.h>
  28 #include "radeon.h"
  29
  30 #include "atom.h"
  31 #include <asm/div64.h>
  32
  33 #include <linux/pm_runtime.h>
  34 #include <drm/drm_crtc_helper.h>
  35 #include <drm/drm_edid.h>
  36
  37 static void avivo_crtc_load_lut(struct drm_crtc *crtc)
  38 {
  39         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
  40         struct drm_device *dev = crtc->dev;
  41         struct radeon_device *rdev = dev->dev_private;
  42         int i;
  43
  44         DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
  45         WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0);
  46
  47         WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
  48         WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
  49         WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
  50
  51         WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
  52         WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
  53         WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
  54
  55         WREG32(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id);
  56         WREG32(AVIVO_DC_LUT_RW_MODE, 0);
  57         WREG32(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f);
  58
  59         WREG8(AVIVO_DC_LUT_RW_INDEX, 0);
  60         for (i = 0; i < 256; i++) {
  61                 WREG32(AVIVO_DC_LUT_30_COLOR,
  62                              (radeon_crtc->lut_r[i] << 20) |
  63                              (radeon_crtc->lut_g[i] << 10) |
  64                              (radeon_crtc->lut_b[i] << 0));
  65         }
  66
  67         WREG32(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id);
  68 }
  69
  70 static void dce4_crtc_load_lut(struct drm_crtc *crtc)
  71 {
  72         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
  73         struct drm_device *dev = crtc->dev;
  74         struct radeon_device *rdev = dev->dev_private;
  75         int i;
  76
  77         DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
  78         WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
  79
  80         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
  81         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
  82         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
  83
  84         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
  85         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
  86         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
  87
  88         WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
  89         WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);
  90
  91         WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);
  92         for (i = 0; i < 256; i++) {
  93                 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
  94                        (radeon_crtc->lut_r[i] << 20) |
  95                        (radeon_crtc->lut_g[i] << 10) |
  96                        (radeon_crtc->lut_b[i] << 0));
  97         }
  98 }
  99
 100 static void dce5_crtc_load_lut(struct drm_crtc *crtc)
 101 {
 102         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 103         struct drm_device *dev = crtc->dev;
 104         struct radeon_device *rdev = dev->dev_private;
 105         int i;
 106
 107         DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
 108
 109         WREG32(NI_INPUT_CSC_CONTROL + radeon_crtc->crtc_offset,
 110                (NI_INPUT_CSC_GRPH_MODE(NI_INPUT_CSC_BYPASS) |
 111                 NI_INPUT_CSC_OVL_MODE(NI_INPUT_CSC_BYPASS)));
 112         WREG32(NI_PRESCALE_GRPH_CONTROL + radeon_crtc->crtc_offset,
 113                NI_GRPH_PRESCALE_BYPASS);
 114         WREG32(NI_PRESCALE_OVL_CONTROL + radeon_crtc->crtc_offset,
 115                NI_OVL_PRESCALE_BYPASS);
 116         WREG32(NI_INPUT_GAMMA_CONTROL + radeon_crtc->crtc_offset,
 117                (NI_GRPH_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT) |
 118                 NI_OVL_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT)));
 119
 120         WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
 121
 122         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
 123         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
 124         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
 125
 126         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
 127         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
 128         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
 129
 130         WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
 131         WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);
 132
 133         WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);
 134         for (i = 0; i < 256; i++) {
 135                 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
 136                        (radeon_crtc->lut_r[i] << 20) |
 137                        (radeon_crtc->lut_g[i] << 10) |
 138                        (radeon_crtc->lut_b[i] << 0));
 139         }
 140
 141         WREG32(NI_DEGAMMA_CONTROL + radeon_crtc->crtc_offset,
 142                (NI_GRPH_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
 143                 NI_OVL_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
 144                 NI_ICON_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
 145                 NI_CURSOR_DEGAMMA_MODE(NI_DEGAMMA_BYPASS)));
 146         WREG32(NI_GAMUT_REMAP_CONTROL + radeon_crtc->crtc_offset,
 147                (NI_GRPH_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS) |
 148                 NI_OVL_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS)));
 149         WREG32(NI_REGAMMA_CONTROL + radeon_crtc->crtc_offset,
 150                (NI_GRPH_REGAMMA_MODE(NI_REGAMMA_BYPASS) |
 151                 NI_OVL_REGAMMA_MODE(NI_REGAMMA_BYPASS)));
 152         WREG32(NI_OUTPUT_CSC_CONTROL + radeon_crtc->crtc_offset,
 153                (NI_OUTPUT_CSC_GRPH_MODE(NI_OUTPUT_CSC_BYPASS) |
 154                 NI_OUTPUT_CSC_OVL_MODE(NI_OUTPUT_CSC_BYPASS)));
 155         /* XXX match this to the depth of the crtc fmt block, move to modeset? */
 156         WREG32(0x6940 + radeon_crtc->crtc_offset, 0);
 157         if (ASIC_IS_DCE8(rdev)) {
 158                 /* XXX this only needs to be programmed once per crtc at startup,
 159                  * not sure where the best place for it is
 160                  */
 161                 WREG32(CIK_ALPHA_CONTROL + radeon_crtc->crtc_offset,
 162                        CIK_CURSOR_ALPHA_BLND_ENA);
 163         }
 164 }
 165
 166 static void legacy_crtc_load_lut(struct drm_crtc *crtc)
 167 {
 168         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 169         struct drm_device *dev = crtc->dev;
 170         struct radeon_device *rdev = dev->dev_private;
 171         int i;
 172         uint32_t dac2_cntl;
 173
 174         dac2_cntl = RREG32(RADEON_DAC_CNTL2);
 175         if (radeon_crtc->crtc_id == 0)
 176                 dac2_cntl &= (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL;
 177         else
 178                 dac2_cntl |= RADEON_DAC2_PALETTE_ACC_CTL;
 179         WREG32(RADEON_DAC_CNTL2, dac2_cntl);
 180
 181         WREG8(RADEON_PALETTE_INDEX, 0);
 182         for (i = 0; i < 256; i++) {
 183                 WREG32(RADEON_PALETTE_30_DATA,
 184                              (radeon_crtc->lut_r[i] << 20) |
 185                              (radeon_crtc->lut_g[i] << 10) |
 186                              (radeon_crtc->lut_b[i] << 0));
 187         }
 188 }
 189
 190 void radeon_crtc_load_lut(struct drm_crtc *crtc)
 191 {
 192         struct drm_device *dev = crtc->dev;
 193         struct radeon_device *rdev = dev->dev_private;
 194
 195         if (!crtc->enabled)
 196                 return;
 197
 198         if (ASIC_IS_DCE5(rdev))
 199                 dce5_crtc_load_lut(crtc);
 200         else if (ASIC_IS_DCE4(rdev))
 201                 dce4_crtc_load_lut(crtc);
 202         else if (ASIC_IS_AVIVO(rdev))
 203                 avivo_crtc_load_lut(crtc);
 204         else
 205                 legacy_crtc_load_lut(crtc);
 206 }
 207
 208 /** Sets the color ramps on behalf of fbcon */
 209 void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
 210                               u16 blue, int regno)
 211 {
 212         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 213
 214         radeon_crtc->lut_r[regno] = red >> 6;
 215         radeon_crtc->lut_g[regno] = green >> 6;
 216         radeon_crtc->lut_b[regno] = blue >> 6;
 217 }
 218
 219 /** Gets the color ramps on behalf of fbcon */
 220 void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
 221                               u16 *blue, int regno)
 222 {
 223         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 224
 225         *red = radeon_crtc->lut_r[regno] << 6;
 226         *green = radeon_crtc->lut_g[regno] << 6;
 227         *blue = radeon_crtc->lut_b[regno] << 6;
 228 }
 229
 230 static void radeon_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
 231                                   u16 *blue, uint32_t start, uint32_t size)
 232 {
 233         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 234         int end = (start + size > 256) ? 256 : start + size, i;
 235
 236         /* userspace palettes are always correct as is */
 237         for (i = start; i < end; i++) {
 238                 radeon_crtc->lut_r[i] = red[i] >> 6;
 239                 radeon_crtc->lut_g[i] = green[i] >> 6;
 240                 radeon_crtc->lut_b[i] = blue[i] >> 6;
 241         }
 242         radeon_crtc_load_lut(crtc);
 243 }
 244
 245 static void radeon_crtc_destroy(struct drm_crtc *crtc)
 246 {
 247         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 248
 249         drm_crtc_cleanup(crtc);
 250         kfree(radeon_crtc);
 251 }
 252
 253 /*
 254  * Handle unpin events outside the interrupt handler proper.
 255  */
 256 static void radeon_unpin_work_func(struct work_struct *__work)
 257 {
 258         struct radeon_unpin_work *work =
 259                 container_of(__work, struct radeon_unpin_work, work);
 260         int r;
 261
 262         /* unpin of the old buffer */
 263         r = radeon_bo_reserve(work->old_rbo, false);
 264         if (likely(r == 0)) {
 265                 r = radeon_bo_unpin(work->old_rbo);
 266                 if (unlikely(r != 0)) {
 267                         DRM_ERROR("failed to unpin buffer after flip\n");
 268                 }
 269                 radeon_bo_unreserve(work->old_rbo);
 270         } else
 271                 DRM_ERROR("failed to reserve buffer after flip\n");
 272
 273         drm_gem_object_unreference_unlocked(&work->old_rbo->gem_base);
 274         kfree(work);
 275 }
 276
 277 void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id)
 278 {
 279         struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
 280         struct radeon_unpin_work *work;
 281         unsigned long flags;
 282         u32 update_pending;
 283         int vpos, hpos;
 284
 285         /* can happen during initialization */
 286         if (radeon_crtc == NULL)
 287                 return;
 288
 289         spin_lock_irqsave(&rdev->ddev->event_lock, flags);
 290         work = radeon_crtc->unpin_work;
 291         if (work == NULL ||
 292             (work->fence && !radeon_fence_signaled(work->fence))) {
 293                 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
 294                 return;
 295         }
 296         /* New pageflip, or just completion of a previous one? */
 297         if (!radeon_crtc->deferred_flip_completion) {
 298                 /* do the flip (mmio) */
 299                 update_pending = radeon_page_flip(rdev, crtc_id, work->new_crtc_base);
 300         } else {
 301                 /* This is just a completion of a flip queued in crtc
 302                  * at last invocation. Make sure we go directly to
 303                  * completion routine.
 304                  */
 305                 update_pending = 0;
 306                 radeon_crtc->deferred_flip_completion = 0;
 307         }
 308
 309         /* Has the pageflip already completed in crtc, or is it certain
 310          * to complete in this vblank?
 311          */
 312         if (update_pending &&
 313             (DRM_SCANOUTPOS_VALID & radeon_get_crtc_scanoutpos(rdev->ddev, crtc_id, 0,
 314                                                                &vpos, &hpos, NULL, NULL)) &&
 315             ((vpos >= (99 * rdev->mode_info.crtcs[crtc_id]->base.hwmode.crtc_vdisplay)/100) ||
 316              (vpos < 0 && !ASIC_IS_AVIVO(rdev)))) {
 317                 /* crtc didn't flip in this target vblank interval,
 318                  * but flip is pending in crtc. Based on the current
 319                  * scanout position we know that the current frame is
 320                  * (nearly) complete and the flip will (likely)
 321                  * complete before the start of the next frame.
 322                  */
 323                 update_pending = 0;
 324         }
 325         if (update_pending) {
 326                 /* crtc didn't flip in this target vblank interval,
 327                  * but flip is pending in crtc. It will complete it
 328                  * in next vblank interval, so complete the flip at
 329                  * next vblank irq.
 330                  */
 331                 radeon_crtc->deferred_flip_completion = 1;
 332                 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
 333                 return;
 334         }
 335
 336         /* Pageflip (will be) certainly completed in this vblank. Clean up. */
 337         radeon_crtc->unpin_work = NULL;
 338
 339         /* wakeup userspace */
 340         if (work->event)
 341                 drm_send_vblank_event(rdev->ddev, crtc_id, work->event);
 342
 343         spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
 344
 345         drm_vblank_put(rdev->ddev, radeon_crtc->crtc_id);
 346         radeon_fence_unref(&work->fence);
 347         radeon_post_page_flip(work->rdev, work->crtc_id);
 348         schedule_work(&work->work);
 349 }
 350
 351 static int radeon_crtc_page_flip(struct drm_crtc *crtc,
 352                                  struct drm_framebuffer *fb,
 353                                  struct drm_pending_vblank_event *event,
 354                                  uint32_t page_flip_flags)
 355 {
 356         struct drm_device *dev = crtc->dev;
 357         struct radeon_device *rdev = dev->dev_private;
 358         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 359         struct radeon_framebuffer *old_radeon_fb;
 360         struct radeon_framebuffer *new_radeon_fb;
 361         struct drm_gem_object *obj;
 362         struct radeon_bo *rbo;
 363         struct radeon_unpin_work *work;
 364         unsigned long flags;
 365         u32 tiling_flags, pitch_pixels;
 366         u64 base;
 367         int r;
 368
 369         work = kzalloc(sizeof *work, GFP_KERNEL);
 370         if (work == NULL)
 371                 return -ENOMEM;
 372
 373         work->event = event;
 374         work->rdev = rdev;
 375         work->crtc_id = radeon_crtc->crtc_id;
 376         old_radeon_fb = to_radeon_framebuffer(crtc->fb);
 377         new_radeon_fb = to_radeon_framebuffer(fb);
 378         /* schedule unpin of the old buffer */
 379         obj = old_radeon_fb->obj;
 380         /* take a reference to the old object */
 381         drm_gem_object_reference(obj);
 382         rbo = gem_to_radeon_bo(obj);
 383         work->old_rbo = rbo;
 384         obj = new_radeon_fb->obj;
 385         rbo = gem_to_radeon_bo(obj);
 386
 387         spin_lock(&rbo->tbo.bdev->fence_lock);
 388         if (rbo->tbo.sync_obj)
 389                 work->fence = radeon_fence_ref(rbo->tbo.sync_obj);
 390         spin_unlock(&rbo->tbo.bdev->fence_lock);
 391
 392         INIT_WORK(&work->work, radeon_unpin_work_func);
 393
 394         /* We borrow the event spin lock for protecting unpin_work */
 395         spin_lock_irqsave(&dev->event_lock, flags);
 396         if (radeon_crtc->unpin_work) {
 397                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
 398                 r = -EBUSY;
 399                 goto unlock_free;
 400         }
 401         radeon_crtc->unpin_work = work;
 402         radeon_crtc->deferred_flip_completion = 0;
 403         spin_unlock_irqrestore(&dev->event_lock, flags);
 404
 405         /* pin the new buffer */
 406         DRM_DEBUG_DRIVER("flip-ioctl() cur_fbo = %p, cur_bbo = %p\n",
 407                          work->old_rbo, rbo);
 408
 409         r = radeon_bo_reserve(rbo, false);
 410         if (unlikely(r != 0)) {
 411                 DRM_ERROR("failed to reserve new rbo buffer before flip\n");
 412                 goto pflip_cleanup;
 413         }
 414         /* Only 27 bit offset for legacy CRTC */
 415         r = radeon_bo_pin_restricted(rbo, RADEON_GEM_DOMAIN_VRAM,
 416                                      ASIC_IS_AVIVO(rdev) ? 0 : 1 << 27, &base);
 417         if (unlikely(r != 0)) {
 418                 radeon_bo_unreserve(rbo);
 419                 r = -EINVAL;
 420                 DRM_ERROR("failed to pin new rbo buffer before flip\n");
 421                 goto pflip_cleanup;
 422         }
 423         radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
 424         radeon_bo_unreserve(rbo);
 425
 426         if (!ASIC_IS_AVIVO(rdev)) {
 427                 /* crtc offset is from display base addr not FB location */
 428                 base -= radeon_crtc->legacy_display_base_addr;
 429                 pitch_pixels = fb->pitches[0] / (fb->bits_per_pixel / 8);
 430
 431                 if (tiling_flags & RADEON_TILING_MACRO) {
 432                         if (ASIC_IS_R300(rdev)) {
 433                                 base &= ~0x7ff;
 434                         } else {
 435                                 int byteshift = fb->bits_per_pixel >> 4;
 436                                 int tile_addr = (((crtc->y >> 3) * pitch_pixels +  crtc->x) >> (8 - byteshift)) << 11;
 437                                 base += tile_addr + ((crtc->x << byteshift) % 256) + ((crtc->y % 8) << 8);
 438                         }
 439                 } else {
 440                         int offset = crtc->y * pitch_pixels + crtc->x;
 441                         switch (fb->bits_per_pixel) {
 442                         case 8:
 443                         default:
 444                                 offset *= 1;
 445                                 break;
 446                         case 15:
 447                         case 16:
 448                                 offset *= 2;
 449                                 break;
 450                         case 24:
 451                                 offset *= 3;
 452                                 break;
 453                         case 32:
 454                                 offset *= 4;
 455                                 break;
 456                         }
 457                         base += offset;
 458                 }
 459                 base &= ~7;
 460         }
 461
 462         spin_lock_irqsave(&dev->event_lock, flags);
 463         work->new_crtc_base = base;
 464         spin_unlock_irqrestore(&dev->event_lock, flags);
 465
 466         /* update crtc fb */
 467         crtc->fb = fb;
 468
 469         r = drm_vblank_get(dev, radeon_crtc->crtc_id);
 470         if (r) {
 471                 DRM_ERROR("failed to get vblank before flip\n");
 472                 goto pflip_cleanup1;
 473         }
 474
 475         /* set the proper interrupt */
 476         radeon_pre_page_flip(rdev, radeon_crtc->crtc_id);
 477
 478         return 0;
 479
 480 pflip_cleanup1:
 481         if (unlikely(radeon_bo_reserve(rbo, false) != 0)) {
 482                 DRM_ERROR("failed to reserve new rbo in error path\n");
 483                 goto pflip_cleanup;
 484         }
 485         if (unlikely(radeon_bo_unpin(rbo) != 0)) {
 486                 DRM_ERROR("failed to unpin new rbo in error path\n");
 487         }
 488         radeon_bo_unreserve(rbo);
 489
 490 pflip_cleanup:
 491         spin_lock_irqsave(&dev->event_lock, flags);
 492         radeon_crtc->unpin_work = NULL;
 493 unlock_free:
 494         spin_unlock_irqrestore(&dev->event_lock, flags);
 495         drm_gem_object_unreference_unlocked(old_radeon_fb->obj);
 496         radeon_fence_unref(&work->fence);
 497         kfree(work);
 498
 499         return r;
 500 }
 501
 502 static int
 503 radeon_crtc_set_config(struct drm_mode_set *set)
 504 {
 505         struct drm_device *dev;
 506         struct radeon_device *rdev;
 507         struct drm_crtc *crtc;
 508         bool active = false;
 509         int ret;
 510
 511         if (!set || !set->crtc)
 512                 return -EINVAL;
 513
 514         dev = set->crtc->dev;
 515
 516         ret = pm_runtime_get_sync(dev->dev);
 517         if (ret < 0)
 518                 return ret;
 519
 520         ret = drm_crtc_helper_set_config(set);
 521
 522         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
 523                 if (crtc->enabled)
 524                         active = true;
 525
 526         pm_runtime_mark_last_busy(dev->dev);
 527
 528         rdev = dev->dev_private;
 529         /* if we have active crtcs and we don't have a power ref,
 530            take the current one */
 531         if (active && !rdev->have_disp_power_ref) {
 532                 rdev->have_disp_power_ref = true;
 533                 return ret;
 534         }
 535         /* if we have no active crtcs, then drop the power ref
 536            we got before */
 537         if (!active && rdev->have_disp_power_ref) {
 538                 pm_runtime_put_autosuspend(dev->dev);
 539                 rdev->have_disp_power_ref = false;
 540         }
 541
 542         /* drop the power reference we got coming in here */
 543         pm_runtime_put_autosuspend(dev->dev);
 544         return ret;
 545 }
 546 static const struct drm_crtc_funcs radeon_crtc_funcs = {
 547         .cursor_set = radeon_crtc_cursor_set,
 548         .cursor_move = radeon_crtc_cursor_move,
 549         .gamma_set = radeon_crtc_gamma_set,
 550         .set_config = radeon_crtc_set_config,
 551         .destroy = radeon_crtc_destroy,
 552         .page_flip = radeon_crtc_page_flip,
 553 };
 554
 555 static void radeon_crtc_init(struct drm_device *dev, int index)
 556 {
 557         struct radeon_device *rdev = dev->dev_private;
 558         struct radeon_crtc *radeon_crtc;
 559         int i;
 560
 561         radeon_crtc = kzalloc(sizeof(struct radeon_crtc) + (RADEONFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
 562         if (radeon_crtc == NULL)
 563                 return;
 564
 565         drm_crtc_init(dev, &radeon_crtc->base, &radeon_crtc_funcs);
 566
 567         drm_mode_crtc_set_gamma_size(&radeon_crtc->base, 256);
 568         radeon_crtc->crtc_id = index;
 569         rdev->mode_info.crtcs[index] = radeon_crtc;
 570
 571         if (rdev->family >= CHIP_BONAIRE) {
 572                 radeon_crtc->max_cursor_width = CIK_CURSOR_WIDTH;
 573                 radeon_crtc->max_cursor_height = CIK_CURSOR_HEIGHT;
 574         } else {
 575                 radeon_crtc->max_cursor_width = CURSOR_WIDTH;
 576                 radeon_crtc->max_cursor_height = CURSOR_HEIGHT;
 577         }
 578         dev->mode_config.cursor_width = radeon_crtc->max_cursor_width;
 579         dev->mode_config.cursor_height = radeon_crtc->max_cursor_height;
 580
 581 #if 0
 582         radeon_crtc->mode_set.crtc = &radeon_crtc->base;
 583         radeon_crtc->mode_set.connectors = (struct drm_connector **)(radeon_crtc + 1);
 584         radeon_crtc->mode_set.num_connectors = 0;
 585 #endif
 586
 587         for (i = 0; i < 256; i++) {
 588                 radeon_crtc->lut_r[i] = i << 2;
 589                 radeon_crtc->lut_g[i] = i << 2;
 590                 radeon_crtc->lut_b[i] = i << 2;
 591         }
 592
 593         if (rdev->is_atom_bios && (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom))
 594                 radeon_atombios_init_crtc(dev, radeon_crtc);
 595         else
 596                 radeon_legacy_init_crtc(dev, radeon_crtc);
 597 }
 598
 599 static const char *encoder_names[38] = {
 600         "NONE",
 601         "INTERNAL_LVDS",
 602         "INTERNAL_TMDS1",
 603         "INTERNAL_TMDS2",
 604         "INTERNAL_DAC1",
 605         "INTERNAL_DAC2",
 606         "INTERNAL_SDVOA",
 607         "INTERNAL_SDVOB",
 608         "SI170B",
 609         "CH7303",
 610         "CH7301",
 611         "INTERNAL_DVO1",
 612         "EXTERNAL_SDVOA",
 613         "EXTERNAL_SDVOB",
 614         "TITFP513",
 615         "INTERNAL_LVTM1",
 616         "VT1623",
 617         "HDMI_SI1930",
 618         "HDMI_INTERNAL",
 619         "INTERNAL_KLDSCP_TMDS1",
 620         "INTERNAL_KLDSCP_DVO1",
 621         "INTERNAL_KLDSCP_DAC1",
 622         "INTERNAL_KLDSCP_DAC2",
 623         "SI178",
 624         "MVPU_FPGA",
 625         "INTERNAL_DDI",
 626         "VT1625",
 627         "HDMI_SI1932",
 628         "DP_AN9801",
 629         "DP_DP501",
 630         "INTERNAL_UNIPHY",
 631         "INTERNAL_KLDSCP_LVTMA",
 632         "INTERNAL_UNIPHY1",
 633         "INTERNAL_UNIPHY2",
 634         "NUTMEG",
 635         "TRAVIS",
 636         "INTERNAL_VCE",
 637         "INTERNAL_UNIPHY3",
 638 };
 639
 640 static const char *hpd_names[6] = {
 641         "HPD1",
 642         "HPD2",
 643         "HPD3",
 644         "HPD4",
 645         "HPD5",
 646         "HPD6",
 647 };
 648
 649 static void radeon_print_display_setup(struct drm_device *dev)
 650 {
 651         struct drm_connector *connector;
 652         struct radeon_connector *radeon_connector;
 653         struct drm_encoder *encoder;
 654         struct radeon_encoder *radeon_encoder;
 655         uint32_t devices;
 656         int i = 0;
 657
 658         DRM_INFO("Radeon Display Connectors\n");
 659         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 660                 radeon_connector = to_radeon_connector(connector);
 661                 DRM_INFO("Connector %d:\n", i);
 662                 DRM_INFO("  %s\n", drm_get_connector_name(connector));
 663                 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE)
 664                         DRM_INFO("  %s\n", hpd_names[radeon_connector->hpd.hpd]);
 665                 if (radeon_connector->ddc_bus) {
 666                         DRM_INFO("  DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
 667                                  radeon_connector->ddc_bus->rec.mask_clk_reg,
 668                                  radeon_connector->ddc_bus->rec.mask_data_reg,
 669                                  radeon_connector->ddc_bus->rec.a_clk_reg,
 670                                  radeon_connector->ddc_bus->rec.a_data_reg,
 671                                  radeon_connector->ddc_bus->rec.en_clk_reg,
 672                                  radeon_connector->ddc_bus->rec.en_data_reg,
 673                                  radeon_connector->ddc_bus->rec.y_clk_reg,
 674                                  radeon_connector->ddc_bus->rec.y_data_reg);
 675                         if (radeon_connector->router.ddc_valid)
 676                                 DRM_INFO("  DDC Router 0x%x/0x%x\n",
 677                                          radeon_connector->router.ddc_mux_control_pin,
 678                                          radeon_connector->router.ddc_mux_state);
 679                         if (radeon_connector->router.cd_valid)
 680                                 DRM_INFO("  Clock/Data Router 0x%x/0x%x\n",
 681                                          radeon_connector->router.cd_mux_control_pin,
 682                                          radeon_connector->router.cd_mux_state);
 683                 } else {
 684                         if (connector->connector_type == DRM_MODE_CONNECTOR_VGA ||
 685                             connector->connector_type == DRM_MODE_CONNECTOR_DVII ||
 686                             connector->connector_type == DRM_MODE_CONNECTOR_DVID ||
 687                             connector->connector_type == DRM_MODE_CONNECTOR_DVIA ||
 688                             connector->connector_type == DRM_MODE_CONNECTOR_HDMIA ||
 689                             connector->connector_type == DRM_MODE_CONNECTOR_HDMIB)
 690                                 DRM_INFO("  DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n");
 691                 }
 692                 DRM_INFO("  Encoders:\n");
 693                 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 694                         radeon_encoder = to_radeon_encoder(encoder);
 695                         devices = radeon_encoder->devices & radeon_connector->devices;
 696                         if (devices) {
 697                                 if (devices & ATOM_DEVICE_CRT1_SUPPORT)
 698                                         DRM_INFO("    CRT1: %s\n", encoder_names[radeon_encoder->encoder_id]);
 699                                 if (devices & ATOM_DEVICE_CRT2_SUPPORT)
 700                                         DRM_INFO("    CRT2: %s\n", encoder_names[radeon_encoder->encoder_id]);
 701                                 if (devices & ATOM_DEVICE_LCD1_SUPPORT)
 702                                         DRM_INFO("    LCD1: %s\n", encoder_names[radeon_encoder->encoder_id]);
 703                                 if (devices & ATOM_DEVICE_DFP1_SUPPORT)
 704                                         DRM_INFO("    DFP1: %s\n", encoder_names[radeon_encoder->encoder_id]);
 705                                 if (devices & ATOM_DEVICE_DFP2_SUPPORT)
 706                                         DRM_INFO("    DFP2: %s\n", encoder_names[radeon_encoder->encoder_id]);
 707                                 if (devices & ATOM_DEVICE_DFP3_SUPPORT)
 708                                         DRM_INFO("    DFP3: %s\n", encoder_names[radeon_encoder->encoder_id]);
 709                                 if (devices & ATOM_DEVICE_DFP4_SUPPORT)
 710                                         DRM_INFO("    DFP4: %s\n", encoder_names[radeon_encoder->encoder_id]);
 711                                 if (devices & ATOM_DEVICE_DFP5_SUPPORT)
 712                                         DRM_INFO("    DFP5: %s\n", encoder_names[radeon_encoder->encoder_id]);
 713                                 if (devices & ATOM_DEVICE_DFP6_SUPPORT)
 714                                         DRM_INFO("    DFP6: %s\n", encoder_names[radeon_encoder->encoder_id]);
 715                                 if (devices & ATOM_DEVICE_TV1_SUPPORT)
 716                                         DRM_INFO("    TV1: %s\n", encoder_names[radeon_encoder->encoder_id]);
 717                                 if (devices & ATOM_DEVICE_CV_SUPPORT)
 718                                         DRM_INFO("    CV: %s\n", encoder_names[radeon_encoder->encoder_id]);
 719                         }
 720                 }
 721                 i++;
 722         }
 723 }
 724
 725 static bool radeon_setup_enc_conn(struct drm_device *dev)
 726 {
 727         struct radeon_device *rdev = dev->dev_private;
 728         bool ret = false;
 729
 730         if (rdev->bios) {
 731                 if (rdev->is_atom_bios) {
 732                         ret = radeon_get_atom_connector_info_from_supported_devices_table(dev);
 733                         if (ret == false)
 734                                 ret = radeon_get_atom_connector_info_from_object_table(dev);
 735                 } else {
 736                         ret = radeon_get_legacy_connector_info_from_bios(dev);
 737                         if (ret == false)
 738                                 ret = radeon_get_legacy_connector_info_from_table(dev);
 739                 }
 740         } else {
 741                 if (!ASIC_IS_AVIVO(rdev))
 742                         ret = radeon_get_legacy_connector_info_from_table(dev);
 743         }
 744         if (ret) {
 745                 radeon_setup_encoder_clones(dev);
 746                 radeon_print_display_setup(dev);
 747         }
 748
 749         return ret;
 750 }
 751
 752 int radeon_ddc_get_modes(struct radeon_connector *radeon_connector)
 753 {
 754         struct drm_device *dev = radeon_connector->base.dev;
 755         struct radeon_device *rdev = dev->dev_private;
 756         int ret = 0;
 757
 758         /* don't leak the edid if we already fetched it in detect() */
 759         if (radeon_connector->edid)
 760                 goto got_edid;
 761
 762         /* on hw with routers, select right port */
 763         if (radeon_connector->router.ddc_valid)
 764                 radeon_router_select_ddc_port(radeon_connector);
 765
 766         if (radeon_connector_encoder_get_dp_bridge_encoder_id(&radeon_connector->base) !=
 767             ENCODER_OBJECT_ID_NONE) {
 768                 struct radeon_connector_atom_dig *dig = radeon_connector->con_priv;
 769
 770                 if (dig->dp_i2c_bus)
 771                         radeon_connector->edid = drm_get_edid(&radeon_connector->base,
 772                                                               &dig->dp_i2c_bus->adapter);
 773         } else if ((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||
 774                    (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)) {
 775                 struct radeon_connector_atom_dig *dig = radeon_connector->con_priv;
 776
 777                 if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT ||
 778                      dig->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) && dig->dp_i2c_bus)
 779                         radeon_connector->edid = drm_get_edid(&radeon_connector->base,
 780                                                               &dig->dp_i2c_bus->adapter);
 781                 else if (radeon_connector->ddc_bus && !radeon_connector->edid)
 782                         radeon_connector->edid = drm_get_edid(&radeon_connector->base,
 783                                                               &radeon_connector->ddc_bus->adapter);
 784         } else {
 785                 if (radeon_connector->ddc_bus && !radeon_connector->edid)
 786                         radeon_connector->edid = drm_get_edid(&radeon_connector->base,
 787                                                               &radeon_connector->ddc_bus->adapter);
 788         }
 789
 790         if (!radeon_connector->edid) {
 791                 if (rdev->is_atom_bios) {
 792                         /* some laptops provide a hardcoded edid in rom for LCDs */
 793                         if (((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_LVDS) ||
 794                              (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)))
 795                                 radeon_connector->edid = radeon_bios_get_hardcoded_edid(rdev);
 796                 } else
 797                         /* some servers provide a hardcoded edid in rom for KVMs */
 798                         radeon_connector->edid = radeon_bios_get_hardcoded_edid(rdev);
 799         }
 800         if (radeon_connector->edid) {
 801 got_edid:
 802                 drm_mode_connector_update_edid_property(&radeon_connector->base, radeon_connector->edid);
 803                 ret = drm_add_edid_modes(&radeon_connector->base, radeon_connector->edid);
 804                 drm_edid_to_eld(&radeon_connector->base, radeon_connector->edid);
 805                 return ret;
 806         }
 807         drm_mode_connector_update_edid_property(&radeon_connector->base, NULL);
 808         return 0;
 809 }
 810
 811 /* avivo */
 812 static void avivo_get_fb_div(struct radeon_pll *pll,
 813                              u32 target_clock,
 814                              u32 post_div,
 815                              u32 ref_div,
 816                              u32 *fb_div,
 817                              u32 *frac_fb_div)
 818 {
 819         u32 tmp = post_div * ref_div;
 820
 821         tmp *= target_clock;
 822         *fb_div = tmp / pll->reference_freq;
 823         *frac_fb_div = tmp % pll->reference_freq;
 824
 825         if (*fb_div > pll->max_feedback_div)
 826                 *fb_div = pll->max_feedback_div;
 827         else if (*fb_div < pll->min_feedback_div)
 828                 *fb_div = pll->min_feedback_div;
 829 }
 830
 831 static u32 avivo_get_post_div(struct radeon_pll *pll,
 832                               u32 target_clock)
 833 {
 834         u32 vco, post_div, tmp;
 835
 836         if (pll->flags & RADEON_PLL_USE_POST_DIV)
 837                 return pll->post_div;
 838
 839         if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP) {
 840                 if (pll->flags & RADEON_PLL_IS_LCD)
 841                         vco = pll->lcd_pll_out_min;
 842                 else
 843                         vco = pll->pll_out_min;
 844         } else {
 845                 if (pll->flags & RADEON_PLL_IS_LCD)
 846                         vco = pll->lcd_pll_out_max;
 847                 else
 848                         vco = pll->pll_out_max;
 849         }
 850
 851         post_div = vco / target_clock;
 852         tmp = vco % target_clock;
 853
 854         if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP) {
 855                 if (tmp)
 856                         post_div++;
 857         } else {
 858                 if (!tmp)
 859                         post_div--;
 860         }
 861
 862         if (post_div > pll->max_post_div)
 863                 post_div = pll->max_post_div;
 864         else if (post_div < pll->min_post_div)
 865                 post_div = pll->min_post_div;
 866
 867         return post_div;
 868 }
 869
 870 #define MAX_TOLERANCE 10
 871
 872 void radeon_compute_pll_avivo(struct radeon_pll *pll,
 873                               u32 freq,
 874                               u32 *dot_clock_p,
 875                               u32 *fb_div_p,
 876                               u32 *frac_fb_div_p,
 877                               u32 *ref_div_p,
 878                               u32 *post_div_p)
 879 {
 880         u32 target_clock = freq / 10;
 881         u32 post_div = avivo_get_post_div(pll, target_clock);
 882         u32 ref_div = pll->min_ref_div;
 883         u32 fb_div = 0, frac_fb_div = 0, tmp;
 884
 885         if (pll->flags & RADEON_PLL_USE_REF_DIV)
 886                 ref_div = pll->reference_div;
 887
 888         if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
 889                 avivo_get_fb_div(pll, target_clock, post_div, ref_div, &fb_div, &frac_fb_div);
 890                 frac_fb_div = (100 * frac_fb_div) / pll->reference_freq;
 891                 if (frac_fb_div >= 5) {
 892                         frac_fb_div -= 5;
 893                         frac_fb_div = frac_fb_div / 10;
 894                         frac_fb_div++;
 895                 }
 896                 if (frac_fb_div >= 10) {
 897                         fb_div++;
 898                         frac_fb_div = 0;
 899                 }
 900         } else {
 901                 while (ref_div <= pll->max_ref_div) {
 902                         avivo_get_fb_div(pll, target_clock, post_div, ref_div,
 903                                          &fb_div, &frac_fb_div);
 904                         if (frac_fb_div >= (pll->reference_freq / 2))
 905                                 fb_div++;
 906                         frac_fb_div = 0;
 907                         tmp = (pll->reference_freq * fb_div) / (post_div * ref_div);
 908                         tmp = (tmp * 10000) / target_clock;
 909
 910                         if (tmp > (10000 + MAX_TOLERANCE))
 911                                 ref_div++;
 912                         else if (tmp >= (10000 - MAX_TOLERANCE))
 913                                 break;
 914                         else
 915                                 ref_div++;
 916                 }
 917         }
 918
 919         *dot_clock_p = ((pll->reference_freq * fb_div * 10) + (pll->reference_freq * frac_fb_div)) /
 920                 (ref_div * post_div * 10);
 921         *fb_div_p = fb_div;
 922         *frac_fb_div_p = frac_fb_div;
 923         *ref_div_p = ref_div;
 924         *post_div_p = post_div;
 925         DRM_DEBUG_KMS("%d, pll dividers - fb: %d.%d ref: %d, post %d\n",
 926                       *dot_clock_p, fb_div, frac_fb_div, ref_div, post_div);
 927 }
 928
 929 /* pre-avivo */
 930 static inline uint32_t radeon_div(uint64_t n, uint32_t d)
 931 {
 932         uint64_t mod;
 933
 934         n += d / 2;
 935
 936         mod = do_div(n, d);
 937         return n;
 938 }
 939
 940 void radeon_compute_pll_legacy(struct radeon_pll *pll,
 941                                uint64_t freq,
 942                                uint32_t *dot_clock_p,
 943                                uint32_t *fb_div_p,
 944                                uint32_t *frac_fb_div_p,
 945                                uint32_t *ref_div_p,
 946                                uint32_t *post_div_p)
 947 {
 948         uint32_t min_ref_div = pll->min_ref_div;
 949         uint32_t max_ref_div = pll->max_ref_div;
 950         uint32_t min_post_div = pll->min_post_div;
 951         uint32_t max_post_div = pll->max_post_div;
 952         uint32_t min_fractional_feed_div = 0;
 953         uint32_t max_fractional_feed_div = 0;
 954         uint32_t best_vco = pll->best_vco;
 955         uint32_t best_post_div = 1;
 956         uint32_t best_ref_div = 1;
 957         uint32_t best_feedback_div = 1;
 958         uint32_t best_frac_feedback_div = 0;
 959         uint32_t best_freq = -1;
 960         uint32_t best_error = 0xffffffff;
 961         uint32_t best_vco_diff = 1;
 962         uint32_t post_div;
 963         u32 pll_out_min, pll_out_max;
 964
 965         DRM_DEBUG_KMS("PLL freq %llu %u %u\n", freq, pll->min_ref_div, pll->max_ref_div);
 966         freq = freq * 1000;
 967
 968         if (pll->flags & RADEON_PLL_IS_LCD) {
 969                 pll_out_min = pll->lcd_pll_out_min;
 970                 pll_out_max = pll->lcd_pll_out_max;
 971         } else {
 972                 pll_out_min = pll->pll_out_min;
 973                 pll_out_max = pll->pll_out_max;
 974         }
 975
 976         if (pll_out_min > 64800)
 977                 pll_out_min = 64800;
 978
 979         if (pll->flags & RADEON_PLL_USE_REF_DIV)
 980                 min_ref_div = max_ref_div = pll->reference_div;
 981         else {
 982                 while (min_ref_div < max_ref_div-1) {
 983                         uint32_t mid = (min_ref_div + max_ref_div) / 2;
 984                         uint32_t pll_in = pll->reference_freq / mid;
 985                         if (pll_in < pll->pll_in_min)
 986                                 max_ref_div = mid;
 987                         else if (pll_in > pll->pll_in_max)
 988                                 min_ref_div = mid;
 989                         else
 990                                 break;
 991                 }
 992         }
 993
 994         if (pll->flags & RADEON_PLL_USE_POST_DIV)
 995                 min_post_div = max_post_div = pll->post_div;
 996
 997         if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
 998                 min_fractional_feed_div = pll->min_frac_feedback_div;
 999                 max_fractional_feed_div = pll->max_frac_feedback_div;
1000         }
1001
1002         for (post_div = max_post_div; post_div >= min_post_div; --post_div) {
1003                 uint32_t ref_div;
1004
1005                 if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1))
1006                         continue;
1007
1008                 /* legacy radeons only have a few post_divs */
1009                 if (pll->flags & RADEON_PLL_LEGACY) {
1010                         if ((post_div == 5) ||
1011                             (post_div == 7) ||
1012                             (post_div == 9) ||
1013                             (post_div == 10) ||
1014                             (post_div == 11) ||
1015                             (post_div == 13) ||
1016                             (post_div == 14) ||
1017                             (post_div == 15))
1018                                 continue;
1019                 }
1020
1021                 for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) {
1022                         uint32_t feedback_div, current_freq = 0, error, vco_diff;
1023                         uint32_t pll_in = pll->reference_freq / ref_div;
1024                         uint32_t min_feed_div = pll->min_feedback_div;
1025                         uint32_t max_feed_div = pll->max_feedback_div + 1;
1026
1027                         if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max)
1028                                 continue;
1029
1030                         while (min_feed_div < max_feed_div) {
1031                                 uint32_t vco;
1032                                 uint32_t min_frac_feed_div = min_fractional_feed_div;
1033                                 uint32_t max_frac_feed_div = max_fractional_feed_div + 1;
1034                                 uint32_t frac_feedback_div;
1035                                 uint64_t tmp;
1036
1037                                 feedback_div = (min_feed_div + max_feed_div) / 2;
1038
1039                                 tmp = (uint64_t)pll->reference_freq * feedback_div;
1040                                 vco = radeon_div(tmp, ref_div);
1041
1042                                 if (vco < pll_out_min) {
1043                                         min_feed_div = feedback_div + 1;
1044                                         continue;
1045                                 } else if (vco > pll_out_max) {
1046                                         max_feed_div = feedback_div;
1047                                         continue;
1048                                 }
1049
1050                                 while (min_frac_feed_div < max_frac_feed_div) {
1051                                         frac_feedback_div = (min_frac_feed_div + max_frac_feed_div) / 2;
1052                                         tmp = (uint64_t)pll->reference_freq * 10000 * feedback_div;
1053                                         tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div;
1054                                         current_freq = radeon_div(tmp, ref_div * post_div);
1055
1056                                         if (pll->flags & RADEON_PLL_PREFER_CLOSEST_LOWER) {
1057                                                 if (freq < current_freq)
1058                                                         error = 0xffffffff;
1059                                                 else
1060                                                         error = freq - current_freq;
1061                                         } else
1062                                                 error = abs(current_freq - freq);
1063                                         vco_diff = abs(vco - best_vco);
1064
1065                                         if ((best_vco == 0 && error < best_error) ||
1066                                             (best_vco != 0 &&
1067                                              ((best_error > 100 && error < best_error - 100) ||
1068                                               (abs(error - best_error) < 100 && vco_diff < best_vco_diff)))) {
1069                                                 best_post_div = post_div;
1070                                                 best_ref_div = ref_div;
1071                                                 best_feedback_div = feedback_div;
1072                                                 best_frac_feedback_div = frac_feedback_div;
1073                                                 best_freq = current_freq;
1074                                                 best_error = error;
1075                                                 best_vco_diff = vco_diff;
1076                                         } else if (current_freq == freq) {
1077                                                 if (best_freq == -1) {
1078                                                         best_post_div = post_div;
1079                                                         best_ref_div = ref_div;
1080                                                         best_feedback_div = feedback_div;
1081                                                         best_frac_feedback_div = frac_feedback_div;
1082                                                         best_freq = current_freq;
1083                                                         best_error = error;
1084                                                         best_vco_diff = vco_diff;
1085                                                 } else if (((pll->flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) ||
1086                                                            ((pll->flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) ||
1087                                                            ((pll->flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) ||
1088                                                            ((pll->flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) ||
1089                                                            ((pll->flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) ||
1090                                                            ((pll->flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) {
1091                                                         best_post_div = post_div;
1092                                                         best_ref_div = ref_div;
1093                                                         best_feedback_div = feedback_div;
1094                                                         best_frac_feedback_div = frac_feedback_div;
1095                                                         best_freq = current_freq;
1096                                                         best_error = error;
1097                                                         best_vco_diff = vco_diff;
1098                                                 }
1099                                         }
1100                                         if (current_freq < freq)
1101                                                 min_frac_feed_div = frac_feedback_div + 1;
1102                                         else
1103                                                 max_frac_feed_div = frac_feedback_div;
1104                                 }
1105                                 if (current_freq < freq)
1106                                         min_feed_div = feedback_div + 1;
1107                                 else
1108                                         max_feed_div = feedback_div;
1109                         }
1110                 }
1111         }
1112
1113         *dot_clock_p = best_freq / 10000;
1114         *fb_div_p = best_feedback_div;
1115         *frac_fb_div_p = best_frac_feedback_div;
1116         *ref_div_p = best_ref_div;
1117         *post_div_p = best_post_div;
1118         DRM_DEBUG_KMS("%lld %d, pll dividers - fb: %d.%d ref: %d, post %d\n",
1119                       (long long)freq,
1120                       best_freq / 1000, best_feedback_div, best_frac_feedback_div,
1121                       best_ref_div, best_post_div);
1122
1123 }
1124
1125 static void radeon_user_framebuffer_destroy(struct drm_framebuffer *fb)
1126 {
1127         struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
1128
1129         if (radeon_fb->obj) {
1130                 drm_gem_object_unreference_unlocked(radeon_fb->obj);
1131         }
1132         drm_framebuffer_cleanup(fb);
1133         kfree(radeon_fb);
1134 }
1135
1136 static int radeon_user_framebuffer_create_handle(struct drm_framebuffer *fb,
1137                                                   struct drm_file *file_priv,
1138                                                   unsigned int *handle)
1139 {
1140         struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
1141
1142         return drm_gem_handle_create(file_priv, radeon_fb->obj, handle);
1143 }
1144
1145 static const struct drm_framebuffer_funcs radeon_fb_funcs = {
1146         .destroy = radeon_user_framebuffer_destroy,
1147         .create_handle = radeon_user_framebuffer_create_handle,
1148 };
1149
1150 int
1151 radeon_framebuffer_init(struct drm_device *dev,
1152                         struct radeon_framebuffer *rfb,
1153                         struct drm_mode_fb_cmd2 *mode_cmd,
1154                         struct drm_gem_object *obj)
1155 {
1156         int ret;
1157         rfb->obj = obj;
1158         drm_helper_mode_fill_fb_struct(&rfb->base, mode_cmd);
1159         ret = drm_framebuffer_init(dev, &rfb->base, &radeon_fb_funcs);
1160         if (ret) {
1161                 rfb->obj = NULL;
1162                 return ret;
1163         }
1164         return 0;
1165 }
1166
1167 static struct drm_framebuffer *
1168 radeon_user_framebuffer_create(struct drm_device *dev,
1169                                struct drm_file *file_priv,
1170                                struct drm_mode_fb_cmd2 *mode_cmd)
1171 {
1172         struct drm_gem_object *obj;
1173         struct radeon_framebuffer *radeon_fb;
1174         int ret;
1175
1176         obj = drm_gem_object_lookup(dev, file_priv, mode_cmd->handles[0]);
1177         if (obj ==  NULL) {
1178                 dev_err(&dev->pdev->dev, "No GEM object associated to handle 0x%08X, "
1179                         "can't create framebuffer\n", mode_cmd->handles[0]);
1180                 return ERR_PTR(-ENOENT);
1181         }
1182
1183         radeon_fb = kzalloc(sizeof(*radeon_fb), GFP_KERNEL);
1184         if (radeon_fb == NULL) {
1185                 drm_gem_object_unreference_unlocked(obj);
1186                 return ERR_PTR(-ENOMEM);
1187         }
1188
1189         ret = radeon_framebuffer_init(dev, radeon_fb, mode_cmd, obj);
1190         if (ret) {
1191                 kfree(radeon_fb);
1192                 drm_gem_object_unreference_unlocked(obj);
1193                 return ERR_PTR(ret);
1194         }
1195
1196         return &radeon_fb->base;
1197 }
1198
1199 static void radeon_output_poll_changed(struct drm_device *dev)
1200 {
1201         struct radeon_device *rdev = dev->dev_private;
1202         radeon_fb_output_poll_changed(rdev);
1203 }
1204
1205 static const struct drm_mode_config_funcs radeon_mode_funcs = {
1206         .fb_create = radeon_user_framebuffer_create,
1207         .output_poll_changed = radeon_output_poll_changed
1208 };
1209
1210 static struct drm_prop_enum_list radeon_tmds_pll_enum_list[] =
1211 {       { 0, "driver" },
1212         { 1, "bios" },
1213 };
1214
1215 static struct drm_prop_enum_list radeon_tv_std_enum_list[] =
1216 {       { TV_STD_NTSC, "ntsc" },
1217         { TV_STD_PAL, "pal" },
1218         { TV_STD_PAL_M, "pal-m" },
1219         { TV_STD_PAL_60, "pal-60" },
1220         { TV_STD_NTSC_J, "ntsc-j" },
1221         { TV_STD_SCART_PAL, "scart-pal" },
1222         { TV_STD_PAL_CN, "pal-cn" },
1223         { TV_STD_SECAM, "secam" },
1224 };
1225
1226 static struct drm_prop_enum_list radeon_underscan_enum_list[] =
1227 {       { UNDERSCAN_OFF, "off" },
1228         { UNDERSCAN_ON, "on" },
1229         { UNDERSCAN_AUTO, "auto" },
1230 };
1231
1232 static struct drm_prop_enum_list radeon_audio_enum_list[] =
1233 {       { RADEON_AUDIO_DISABLE, "off" },
1234         { RADEON_AUDIO_ENABLE, "on" },
1235         { RADEON_AUDIO_AUTO, "auto" },
1236 };
1237
1238 /* XXX support different dither options? spatial, temporal, both, etc. */
1239 static struct drm_prop_enum_list radeon_dither_enum_list[] =
1240 {       { RADEON_FMT_DITHER_DISABLE, "off" },
1241         { RADEON_FMT_DITHER_ENABLE, "on" },
1242 };
1243
1244 static int radeon_modeset_create_props(struct radeon_device *rdev)
1245 {
1246         int sz;
1247
1248         if (rdev->is_atom_bios) {
1249                 rdev->mode_info.coherent_mode_property =
1250                         drm_property_create_range(rdev->ddev, 0 , "coherent", 0, 1);
1251                 if (!rdev->mode_info.coherent_mode_property)
1252                         return -ENOMEM;
1253         }
1254
1255         if (!ASIC_IS_AVIVO(rdev)) {
1256                 sz = ARRAY_SIZE(radeon_tmds_pll_enum_list);
1257                 rdev->mode_info.tmds_pll_property =
1258                         drm_property_create_enum(rdev->ddev, 0,
1259                                             "tmds_pll",
1260                                             radeon_tmds_pll_enum_list, sz);
1261         }
1262
1263         rdev->mode_info.load_detect_property =
1264                 drm_property_create_range(rdev->ddev, 0, "load detection", 0, 1);
1265         if (!rdev->mode_info.load_detect_property)
1266                 return -ENOMEM;
1267
1268         drm_mode_create_scaling_mode_property(rdev->ddev);
1269
1270         sz = ARRAY_SIZE(radeon_tv_std_enum_list);
1271         rdev->mode_info.tv_std_property =
1272                 drm_property_create_enum(rdev->ddev, 0,
1273                                     "tv standard",
1274                                     radeon_tv_std_enum_list, sz);
1275
1276         sz = ARRAY_SIZE(radeon_underscan_enum_list);
1277         rdev->mode_info.underscan_property =
1278                 drm_property_create_enum(rdev->ddev, 0,
1279                                     "underscan",
1280                                     radeon_underscan_enum_list, sz);
1281
1282         rdev->mode_info.underscan_hborder_property =
1283                 drm_property_create_range(rdev->ddev, 0,
1284                                         "underscan hborder", 0, 128);
1285         if (!rdev->mode_info.underscan_hborder_property)
1286                 return -ENOMEM;
1287
1288         rdev->mode_info.underscan_vborder_property =
1289                 drm_property_create_range(rdev->ddev, 0,
1290                                         "underscan vborder", 0, 128);
1291         if (!rdev->mode_info.underscan_vborder_property)
1292                 return -ENOMEM;
1293
1294         sz = ARRAY_SIZE(radeon_audio_enum_list);
1295         rdev->mode_info.audio_property =
1296                 drm_property_create_enum(rdev->ddev, 0,
1297                                          "audio",
1298                                          radeon_audio_enum_list, sz);
1299
1300         sz = ARRAY_SIZE(radeon_dither_enum_list);
1301         rdev->mode_info.dither_property =
1302                 drm_property_create_enum(rdev->ddev, 0,
1303                                          "dither",
1304                                          radeon_dither_enum_list, sz);
1305
1306         return 0;
1307 }
1308
1309 void radeon_update_display_priority(struct radeon_device *rdev)
1310 {
1311         /* adjustment options for the display watermarks */
1312         if ((radeon_disp_priority == 0) || (radeon_disp_priority > 2)) {
1313                 /* set display priority to high for r3xx, rv515 chips
1314                  * this avoids flickering due to underflow to the
1315                  * display controllers during heavy acceleration.
1316                  * Don't force high on rs4xx igp chips as it seems to
1317                  * affect the sound card.  See kernel bug 15982.
1318                  */
1319                 if ((ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV515)) &&
1320                     !(rdev->flags & RADEON_IS_IGP))
1321                         rdev->disp_priority = 2;
1322                 else
1323                         rdev->disp_priority = 0;
1324         } else
1325                 rdev->disp_priority = radeon_disp_priority;
1326
1327 }
1328
1329 /*
1330  * Allocate hdmi structs and determine register offsets
1331  */
1332 static void radeon_afmt_init(struct radeon_device *rdev)
1333 {
1334         int i;
1335
1336         for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++)
1337                 rdev->mode_info.afmt[i] = NULL;
1338
1339         if (ASIC_IS_NODCE(rdev)) {
1340                 /* nothing to do */
1341         } else if (ASIC_IS_DCE4(rdev)) {
1342                 static uint32_t eg_offsets[] = {
1343                         EVERGREEN_CRTC0_REGISTER_OFFSET,
1344                         EVERGREEN_CRTC1_REGISTER_OFFSET,
1345                         EVERGREEN_CRTC2_REGISTER_OFFSET,
1346                         EVERGREEN_CRTC3_REGISTER_OFFSET,
1347                         EVERGREEN_CRTC4_REGISTER_OFFSET,
1348                         EVERGREEN_CRTC5_REGISTER_OFFSET,
1349                         0x13830 - 0x7030,
1350                 };
1351                 int num_afmt;
1352
1353                 /* DCE8 has 7 audio blocks tied to DIG encoders */
1354                 /* DCE6 has 6 audio blocks tied to DIG encoders */
1355                 /* DCE4/5 has 6 audio blocks tied to DIG encoders */
1356                 /* DCE4.1 has 2 audio blocks tied to DIG encoders */
1357                 if (ASIC_IS_DCE8(rdev))
1358                         num_afmt = 7;
1359                 else if (ASIC_IS_DCE6(rdev))
1360                         num_afmt = 6;
1361                 else if (ASIC_IS_DCE5(rdev))
1362                         num_afmt = 6;
1363                 else if (ASIC_IS_DCE41(rdev))
1364                         num_afmt = 2;
1365                 else /* DCE4 */
1366                         num_afmt = 6;
1367
1368                 BUG_ON(num_afmt > ARRAY_SIZE(eg_offsets));
1369                 for (i = 0; i < num_afmt; i++) {
1370                         rdev->mode_info.afmt[i] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1371                         if (rdev->mode_info.afmt[i]) {
1372                                 rdev->mode_info.afmt[i]->offset = eg_offsets[i];
1373                                 rdev->mode_info.afmt[i]->id = i;
1374                         }
1375                 }
1376         } else if (ASIC_IS_DCE3(rdev)) {
1377                 /* DCE3.x has 2 audio blocks tied to DIG encoders */
1378                 rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1379                 if (rdev->mode_info.afmt[0]) {
1380                         rdev->mode_info.afmt[0]->offset = DCE3_HDMI_OFFSET0;
1381                         rdev->mode_info.afmt[0]->id = 0;
1382                 }
1383                 rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1384                 if (rdev->mode_info.afmt[1]) {
1385                         rdev->mode_info.afmt[1]->offset = DCE3_HDMI_OFFSET1;
1386                         rdev->mode_info.afmt[1]->id = 1;
1387                 }
1388         } else if (ASIC_IS_DCE2(rdev)) {
1389                 /* DCE2 has at least 1 routable audio block */
1390                 rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1391                 if (rdev->mode_info.afmt[0]) {
1392                         rdev->mode_info.afmt[0]->offset = DCE2_HDMI_OFFSET0;
1393                         rdev->mode_info.afmt[0]->id = 0;
1394                 }
1395                 /* r6xx has 2 routable audio blocks */
1396                 if (rdev->family >= CHIP_R600) {
1397                         rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1398                         if (rdev->mode_info.afmt[1]) {
1399                                 rdev->mode_info.afmt[1]->offset = DCE2_HDMI_OFFSET1;
1400                                 rdev->mode_info.afmt[1]->id = 1;
1401                         }
1402                 }
1403         }
1404 }
1405
1406 static void radeon_afmt_fini(struct radeon_device *rdev)
1407 {
1408         int i;
1409
1410         for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++) {
1411                 kfree(rdev->mode_info.afmt[i]);
1412                 rdev->mode_info.afmt[i] = NULL;
1413         }
1414 }
1415
1416 int radeon_modeset_init(struct radeon_device *rdev)
1417 {
1418         int i;
1419         int ret;
1420
1421         drm_mode_config_init(rdev->ddev);
1422         rdev->mode_info.mode_config_initialized = true;
1423
1424         rdev->ddev->mode_config.funcs = &radeon_mode_funcs;
1425
1426         if (ASIC_IS_DCE5(rdev)) {
1427                 rdev->ddev->mode_config.max_width = 16384;
1428                 rdev->ddev->mode_config.max_height = 16384;
1429         } else if (ASIC_IS_AVIVO(rdev)) {
1430                 rdev->ddev->mode_config.max_width = 8192;
1431                 rdev->ddev->mode_config.max_height = 8192;
1432         } else {
1433                 rdev->ddev->mode_config.max_width = 4096;
1434                 rdev->ddev->mode_config.max_height = 4096;
1435         }
1436
1437         rdev->ddev->mode_config.preferred_depth = 24;
1438         rdev->ddev->mode_config.prefer_shadow = 1;
1439
1440         rdev->ddev->mode_config.fb_base = rdev->mc.aper_base;
1441
1442         ret = radeon_modeset_create_props(rdev);
1443         if (ret) {
1444                 return ret;
1445         }
1446
1447         /* init i2c buses */
1448         radeon_i2c_init(rdev);
1449
1450         /* check combios for a valid hardcoded EDID - Sun servers */
1451         if (!rdev->is_atom_bios) {
1452                 /* check for hardcoded EDID in BIOS */
1453                 radeon_combios_check_hardcoded_edid(rdev);
1454         }
1455
1456         /* allocate crtcs */
1457         for (i = 0; i < rdev->num_crtc; i++) {
1458                 radeon_crtc_init(rdev->ddev, i);
1459         }
1460
1461         /* okay we should have all the bios connectors */
1462         ret = radeon_setup_enc_conn(rdev->ddev);
1463         if (!ret) {
1464                 return ret;
1465         }
1466
1467         /* init dig PHYs, disp eng pll */
1468         if (rdev->is_atom_bios) {
1469                 radeon_atom_encoder_init(rdev);
1470                 radeon_atom_disp_eng_pll_init(rdev);
1471         }
1472
1473         /* initialize hpd */
1474         radeon_hpd_init(rdev);
1475
1476         /* setup afmt */
1477         radeon_afmt_init(rdev);
1478
1479         radeon_fbdev_init(rdev);
1480         drm_kms_helper_poll_init(rdev->ddev);
1481
1482         if (rdev->pm.dpm_enabled) {
1483                 /* do dpm late init */
1484                 ret = radeon_pm_late_init(rdev);
1485                 if (ret) {
1486                         rdev->pm.dpm_enabled = false;
1487                         DRM_ERROR("radeon_pm_late_init failed, disabling dpm\n");
1488                 }
1489                 /* set the dpm state for PX since there won't be
1490                  * a modeset to call this.
1491                  */
1492                 radeon_pm_compute_clocks(rdev);
1493         }
1494
1495         return 0;
1496 }
1497
1498 void radeon_modeset_fini(struct radeon_device *rdev)
1499 {
1500         radeon_fbdev_fini(rdev);
1501         kfree(rdev->mode_info.bios_hardcoded_edid);
1502
1503         if (rdev->mode_info.mode_config_initialized) {
1504                 radeon_afmt_fini(rdev);
1505                 drm_kms_helper_poll_fini(rdev->ddev);
1506                 radeon_hpd_fini(rdev);
1507                 drm_mode_config_cleanup(rdev->ddev);
1508                 rdev->mode_info.mode_config_initialized = false;
1509         }
1510         /* free i2c buses */
1511         radeon_i2c_fini(rdev);
1512 }
1513
1514 static bool is_hdtv_mode(const struct drm_display_mode *mode)
1515 {
1516         /* try and guess if this is a tv or a monitor */
1517         if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */
1518             (mode->vdisplay == 576) || /* 576p */
1519             (mode->vdisplay == 720) || /* 720p */
1520             (mode->vdisplay == 1080)) /* 1080p */
1521                 return true;
1522         else
1523                 return false;
1524 }
1525
1526 bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
1527                                 const struct drm_display_mode *mode,
1528                                 struct drm_display_mode *adjusted_mode)
1529 {
1530         struct drm_device *dev = crtc->dev;
1531         struct radeon_device *rdev = dev->dev_private;
1532         struct drm_encoder *encoder;
1533         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1534         struct radeon_encoder *radeon_encoder;
1535         struct drm_connector *connector;
1536         struct radeon_connector *radeon_connector;
1537         bool first = true;
1538         u32 src_v = 1, dst_v = 1;
1539         u32 src_h = 1, dst_h = 1;
1540
1541         radeon_crtc->h_border = 0;
1542         radeon_crtc->v_border = 0;
1543
1544         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1545                 if (encoder->crtc != crtc)
1546                         continue;
1547                 radeon_encoder = to_radeon_encoder(encoder);
1548                 connector = radeon_get_connector_for_encoder(encoder);
1549                 radeon_connector = to_radeon_connector(connector);
1550
1551                 if (first) {
1552                         /* set scaling */
1553                         if (radeon_encoder->rmx_type == RMX_OFF)
1554                                 radeon_crtc->rmx_type = RMX_OFF;
1555                         else if (mode->hdisplay < radeon_encoder->native_mode.hdisplay ||
1556                                  mode->vdisplay < radeon_encoder->native_mode.vdisplay)
1557                                 radeon_crtc->rmx_type = radeon_encoder->rmx_type;
1558                         else
1559                                 radeon_crtc->rmx_type = RMX_OFF;
1560                         /* copy native mode */
1561                         memcpy(&radeon_crtc->native_mode,
1562                                &radeon_encoder->native_mode,
1563                                 sizeof(struct drm_display_mode));
1564                         src_v = crtc->mode.vdisplay;
1565                         dst_v = radeon_crtc->native_mode.vdisplay;
1566                         src_h = crtc->mode.hdisplay;
1567                         dst_h = radeon_crtc->native_mode.hdisplay;
1568
1569                         /* fix up for overscan on hdmi */
1570                         if (ASIC_IS_AVIVO(rdev) &&
1571                             (!(mode->flags & DRM_MODE_FLAG_INTERLACE)) &&
1572                             ((radeon_encoder->underscan_type == UNDERSCAN_ON) ||
1573                              ((radeon_encoder->underscan_type == UNDERSCAN_AUTO) &&
1574                               drm_detect_hdmi_monitor(radeon_connector->edid) &&
1575                               is_hdtv_mode(mode)))) {
1576                                 if (radeon_encoder->underscan_hborder != 0)
1577                                         radeon_crtc->h_border = radeon_encoder->underscan_hborder;
1578                                 else
1579                                         radeon_crtc->h_border = (mode->hdisplay >> 5) + 16;
1580                                 if (radeon_encoder->underscan_vborder != 0)
1581                                         radeon_crtc->v_border = radeon_encoder->underscan_vborder;
1582                                 else
1583                                         radeon_crtc->v_border = (mode->vdisplay >> 5) + 16;
1584                                 radeon_crtc->rmx_type = RMX_FULL;
1585                                 src_v = crtc->mode.vdisplay;
1586                                 dst_v = crtc->mode.vdisplay - (radeon_crtc->v_border * 2);
1587                                 src_h = crtc->mode.hdisplay;
1588                                 dst_h = crtc->mode.hdisplay - (radeon_crtc->h_border * 2);
1589                         }
1590                         first = false;
1591                 } else {
1592                         if (radeon_crtc->rmx_type != radeon_encoder->rmx_type) {
1593                                 /* WARNING: Right now this can't happen but
1594                                  * in the future we need to check that scaling
1595                                  * are consistent across different encoder
1596                                  * (ie all encoder can work with the same
1597                                  *  scaling).
1598                                  */
1599                                 DRM_ERROR("Scaling not consistent across encoder.\n");
1600                                 return false;
1601                         }
1602                 }
1603         }
1604         if (radeon_crtc->rmx_type != RMX_OFF) {
1605                 fixed20_12 a, b;
1606                 a.full = dfixed_const(src_v);
1607                 b.full = dfixed_const(dst_v);
1608                 radeon_crtc->vsc.full = dfixed_div(a, b);
1609                 a.full = dfixed_const(src_h);
1610                 b.full = dfixed_const(dst_h);
1611                 radeon_crtc->hsc.full = dfixed_div(a, b);
1612         } else {
1613                 radeon_crtc->vsc.full = dfixed_const(1);
1614                 radeon_crtc->hsc.full = dfixed_const(1);
1615         }
1616         return true;
1617 }
1618
1619 /*
1620  * Retrieve current video scanout position of crtc on a given gpu, and
1621  * an optional accurate timestamp of when query happened.
1622  *
1623  * \param dev Device to query.
1624  * \param crtc Crtc to query.
1625  * \param flags Flags from caller (DRM_CALLED_FROM_VBLIRQ or 0).
1626  * \param *vpos Location where vertical scanout position should be stored.
1627  * \param *hpos Location where horizontal scanout position should go.
1628  * \param *stime Target location for timestamp taken immediately before
1629  *               scanout position query. Can be NULL to skip timestamp.
1630  * \param *etime Target location for timestamp taken immediately after
1631  *               scanout position query. Can be NULL to skip timestamp.
1632  *
1633  * Returns vpos as a positive number while in active scanout area.
1634  * Returns vpos as a negative number inside vblank, counting the number
1635  * of scanlines to go until end of vblank, e.g., -1 means "one scanline
1636  * until start of active scanout / end of vblank."
1637  *
1638  * \return Flags, or'ed together as follows:
1639  *
1640  * DRM_SCANOUTPOS_VALID = Query successful.
1641  * DRM_SCANOUTPOS_INVBL = Inside vblank.
1642  * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of
1643  * this flag means that returned position may be offset by a constant but
1644  * unknown small number of scanlines wrt. real scanout position.
1645  *
1646  */
1647 int radeon_get_crtc_scanoutpos(struct drm_device *dev, int crtc, unsigned int flags,
1648                                int *vpos, int *hpos, ktime_t *stime, ktime_t *etime)
1649 {
1650         u32 stat_crtc = 0, vbl = 0, position = 0;
1651         int vbl_start, vbl_end, vtotal, ret = 0;
1652         bool in_vbl = true;
1653
1654         struct radeon_device *rdev = dev->dev_private;
1655
1656         /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
1657
1658         /* Get optional system timestamp before query. */
1659         if (stime)
1660                 *stime = ktime_get();
1661
1662         if (ASIC_IS_DCE4(rdev)) {
1663                 if (crtc == 0) {
1664                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1665                                      EVERGREEN_CRTC0_REGISTER_OFFSET);
1666                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1667                                           EVERGREEN_CRTC0_REGISTER_OFFSET);
1668                         ret |= DRM_SCANOUTPOS_VALID;
1669                 }
1670                 if (crtc == 1) {
1671                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1672                                      EVERGREEN_CRTC1_REGISTER_OFFSET);
1673                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1674                                           EVERGREEN_CRTC1_REGISTER_OFFSET);
1675                         ret |= DRM_SCANOUTPOS_VALID;
1676                 }
1677                 if (crtc == 2) {
1678                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1679                                      EVERGREEN_CRTC2_REGISTER_OFFSET);
1680                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1681                                           EVERGREEN_CRTC2_REGISTER_OFFSET);
1682                         ret |= DRM_SCANOUTPOS_VALID;
1683                 }
1684                 if (crtc == 3) {
1685                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1686                                      EVERGREEN_CRTC3_REGISTER_OFFSET);
1687                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1688                                           EVERGREEN_CRTC3_REGISTER_OFFSET);
1689                         ret |= DRM_SCANOUTPOS_VALID;
1690                 }
1691                 if (crtc == 4) {
1692                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1693                                      EVERGREEN_CRTC4_REGISTER_OFFSET);
1694                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1695                                           EVERGREEN_CRTC4_REGISTER_OFFSET);
1696                         ret |= DRM_SCANOUTPOS_VALID;
1697                 }
1698                 if (crtc == 5) {
1699                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1700                                      EVERGREEN_CRTC5_REGISTER_OFFSET);
1701                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1702                                           EVERGREEN_CRTC5_REGISTER_OFFSET);
1703                         ret |= DRM_SCANOUTPOS_VALID;
1704                 }
1705         } else if (ASIC_IS_AVIVO(rdev)) {
1706                 if (crtc == 0) {
1707                         vbl = RREG32(AVIVO_D1CRTC_V_BLANK_START_END);
1708                         position = RREG32(AVIVO_D1CRTC_STATUS_POSITION);
1709                         ret |= DRM_SCANOUTPOS_VALID;
1710                 }
1711                 if (crtc == 1) {
1712                         vbl = RREG32(AVIVO_D2CRTC_V_BLANK_START_END);
1713                         position = RREG32(AVIVO_D2CRTC_STATUS_POSITION);
1714                         ret |= DRM_SCANOUTPOS_VALID;
1715                 }
1716         } else {
1717                 /* Pre-AVIVO: Different encoding of scanout pos and vblank interval. */
1718                 if (crtc == 0) {
1719                         /* Assume vbl_end == 0, get vbl_start from
1720                          * upper 16 bits.
1721                          */
1722                         vbl = (RREG32(RADEON_CRTC_V_TOTAL_DISP) &
1723                                 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT;
1724                         /* Only retrieve vpos from upper 16 bits, set hpos == 0. */
1725                         position = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
1726                         stat_crtc = RREG32(RADEON_CRTC_STATUS);
1727                         if (!(stat_crtc & 1))
1728                                 in_vbl = false;
1729
1730                         ret |= DRM_SCANOUTPOS_VALID;
1731                 }
1732                 if (crtc == 1) {
1733                         vbl = (RREG32(RADEON_CRTC2_V_TOTAL_DISP) &
1734                                 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT;
1735                         position = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
1736                         stat_crtc = RREG32(RADEON_CRTC2_STATUS);
1737                         if (!(stat_crtc & 1))
1738                                 in_vbl = false;
1739
1740                         ret |= DRM_SCANOUTPOS_VALID;
1741                 }
1742         }
1743
1744         /* Get optional system timestamp after query. */
1745         if (etime)
1746                 *etime = ktime_get();
1747
1748         /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
1749
1750         /* Decode into vertical and horizontal scanout position. */
1751         *vpos = position & 0x1fff;
1752         *hpos = (position >> 16) & 0x1fff;
1753
1754         /* Valid vblank area boundaries from gpu retrieved? */
1755         if (vbl > 0) {
1756                 /* Yes: Decode. */
1757                 ret |= DRM_SCANOUTPOS_ACCURATE;
1758                 vbl_start = vbl & 0x1fff;
1759                 vbl_end = (vbl >> 16) & 0x1fff;
1760         }
1761         else {
1762                 /* No: Fake something reasonable which gives at least ok results. */
1763                 vbl_start = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vdisplay;
1764                 vbl_end = 0;
1765         }
1766
1767         /* Test scanout position against vblank region. */
1768         if ((*vpos < vbl_start) && (*vpos >= vbl_end))
1769                 in_vbl = false;
1770
1771         /* Check if inside vblank area and apply corrective offsets:
1772          * vpos will then be >=0 in video scanout area, but negative
1773          * within vblank area, counting down the number of lines until
1774          * start of scanout.
1775          */
1776
1777         /* Inside "upper part" of vblank area? Apply corrective offset if so: */
1778         if (in_vbl && (*vpos >= vbl_start)) {
1779                 vtotal = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vtotal;
1780                 *vpos = *vpos - vtotal;
1781         }
1782
1783         /* Correct for shifted end of vbl at vbl_end. */
1784         *vpos = *vpos - vbl_end;
1785
1786         /* In vblank? */
1787         if (in_vbl)
1788                 ret |= DRM_SCANOUTPOS_INVBL;
1789
1790         /* Is vpos outside nominal vblank area, but less than
1791          * 1/100 of a frame height away from start of vblank?
1792          * If so, assume this isn't a massively delayed vblank
1793          * interrupt, but a vblank interrupt that fired a few
1794          * microseconds before true start of vblank. Compensate
1795          * by adding a full frame duration to the final timestamp.
1796          * Happens, e.g., on ATI R500, R600.
1797          *
1798          * We only do this if DRM_CALLED_FROM_VBLIRQ.
1799          */
1800         if ((flags & DRM_CALLED_FROM_VBLIRQ) && !in_vbl) {
1801                 vbl_start = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vdisplay;
1802                 vtotal = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vtotal;
1803
1804                 if (vbl_start - *vpos < vtotal / 100) {
1805                         *vpos -= vtotal;
1806
1807                         /* Signal this correction as "applied". */
1808                         ret |= 0x8;
1809                 }
1810         }
1811
1812         return ret;
1813 }