2 * Copyright 2008 Jerome Glisse.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
25 * Jerome Glisse <glisse@freedesktop.org>
28 #include <drm/radeon_drm.h>
29 #include "radeon_reg.h"
31 #include "radeon_trace.h"
33 static int radeon_cs_parser_relocs(struct radeon_cs_parser *p)
35 struct drm_device *ddev = p->rdev->ddev;
36 struct radeon_cs_chunk *chunk;
40 if (p->chunk_relocs_idx == -1) {
43 chunk = &p->chunks[p->chunk_relocs_idx];
45 /* FIXME: we assume that each relocs use 4 dwords */
46 p->nrelocs = chunk->length_dw / 4;
47 p->relocs_ptr = kcalloc(p->nrelocs, sizeof(void *), GFP_KERNEL);
48 if (p->relocs_ptr == NULL) {
51 p->relocs = kcalloc(p->nrelocs, sizeof(struct radeon_cs_reloc), GFP_KERNEL);
52 if (p->relocs == NULL) {
55 for (i = 0; i < p->nrelocs; i++) {
56 struct drm_radeon_cs_reloc *r;
59 r = (struct drm_radeon_cs_reloc *)&chunk->kdata[i*4];
60 for (j = 0; j < i; j++) {
61 if (r->handle == p->relocs[j].handle) {
62 p->relocs_ptr[i] = &p->relocs[j];
68 p->relocs[i].handle = 0;
72 p->relocs[i].gobj = drm_gem_object_lookup(ddev, p->filp,
74 if (p->relocs[i].gobj == NULL) {
75 DRM_ERROR("gem object lookup failed 0x%x\n",
79 p->relocs_ptr[i] = &p->relocs[i];
80 p->relocs[i].robj = gem_to_radeon_bo(p->relocs[i].gobj);
81 p->relocs[i].lobj.bo = p->relocs[i].robj;
82 p->relocs[i].lobj.written = !!r->write_domain;
84 /* the first reloc of an UVD job is the msg and that must be in
85 VRAM, also but everything into VRAM on AGP cards to avoid
87 if (p->ring == R600_RING_TYPE_UVD_INDEX &&
88 p->rdev->family < CHIP_PALM &&
89 (i == 0 || drm_pci_device_is_agp(p->rdev->ddev))) {
91 p->relocs[i].lobj.domain =
92 RADEON_GEM_DOMAIN_VRAM;
94 p->relocs[i].lobj.alt_domain =
95 RADEON_GEM_DOMAIN_VRAM;
98 uint32_t domain = r->write_domain ?
99 r->write_domain : r->read_domains;
101 p->relocs[i].lobj.domain = domain;
102 if (domain == RADEON_GEM_DOMAIN_VRAM)
103 domain |= RADEON_GEM_DOMAIN_GTT;
104 p->relocs[i].lobj.alt_domain = domain;
107 p->relocs[i].lobj.tv.bo = &p->relocs[i].robj->tbo;
108 p->relocs[i].handle = r->handle;
110 radeon_bo_list_add_object(&p->relocs[i].lobj,
113 return radeon_bo_list_validate(&p->ticket, &p->validated, p->ring);
116 static int radeon_cs_get_ring(struct radeon_cs_parser *p, u32 ring, s32 priority)
118 p->priority = priority;
122 DRM_ERROR("unknown ring id: %d\n", ring);
124 case RADEON_CS_RING_GFX:
125 p->ring = RADEON_RING_TYPE_GFX_INDEX;
127 case RADEON_CS_RING_COMPUTE:
128 if (p->rdev->family >= CHIP_TAHITI) {
130 p->ring = CAYMAN_RING_TYPE_CP1_INDEX;
132 p->ring = CAYMAN_RING_TYPE_CP2_INDEX;
134 p->ring = RADEON_RING_TYPE_GFX_INDEX;
136 case RADEON_CS_RING_DMA:
137 if (p->rdev->family >= CHIP_CAYMAN) {
139 p->ring = R600_RING_TYPE_DMA_INDEX;
141 p->ring = CAYMAN_RING_TYPE_DMA1_INDEX;
142 } else if (p->rdev->family >= CHIP_R600) {
143 p->ring = R600_RING_TYPE_DMA_INDEX;
148 case RADEON_CS_RING_UVD:
149 p->ring = R600_RING_TYPE_UVD_INDEX;
155 static void radeon_cs_sync_rings(struct radeon_cs_parser *p)
159 for (i = 0; i < p->nrelocs; i++) {
160 if (!p->relocs[i].robj)
163 radeon_ib_sync_to(&p->ib, p->relocs[i].robj->tbo.sync_obj);
167 /* XXX: note that this is called from the legacy UMS CS ioctl as well */
168 int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data)
170 struct drm_radeon_cs *cs = data;
171 uint64_t *chunk_array_ptr;
173 u32 ring = RADEON_CS_RING_GFX;
176 if (!cs->num_chunks) {
180 INIT_LIST_HEAD(&p->validated);
183 p->ib.semaphore = NULL;
184 p->const_ib.sa_bo = NULL;
185 p->const_ib.semaphore = NULL;
186 p->chunk_ib_idx = -1;
187 p->chunk_relocs_idx = -1;
188 p->chunk_flags_idx = -1;
189 p->chunk_const_ib_idx = -1;
190 p->chunks_array = kcalloc(cs->num_chunks, sizeof(uint64_t), GFP_KERNEL);
191 if (p->chunks_array == NULL) {
194 chunk_array_ptr = (uint64_t *)(unsigned long)(cs->chunks);
195 if (DRM_COPY_FROM_USER(p->chunks_array, chunk_array_ptr,
196 sizeof(uint64_t)*cs->num_chunks)) {
200 p->nchunks = cs->num_chunks;
201 p->chunks = kcalloc(p->nchunks, sizeof(struct radeon_cs_chunk), GFP_KERNEL);
202 if (p->chunks == NULL) {
205 for (i = 0; i < p->nchunks; i++) {
206 struct drm_radeon_cs_chunk __user **chunk_ptr = NULL;
207 struct drm_radeon_cs_chunk user_chunk;
208 uint32_t __user *cdata;
210 chunk_ptr = (void __user*)(unsigned long)p->chunks_array[i];
211 if (DRM_COPY_FROM_USER(&user_chunk, chunk_ptr,
212 sizeof(struct drm_radeon_cs_chunk))) {
215 p->chunks[i].length_dw = user_chunk.length_dw;
216 p->chunks[i].kdata = NULL;
217 p->chunks[i].chunk_id = user_chunk.chunk_id;
218 p->chunks[i].user_ptr = (void __user *)(unsigned long)user_chunk.chunk_data;
219 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_RELOCS) {
220 p->chunk_relocs_idx = i;
222 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_IB) {
224 /* zero length IB isn't useful */
225 if (p->chunks[i].length_dw == 0)
228 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_CONST_IB) {
229 p->chunk_const_ib_idx = i;
230 /* zero length CONST IB isn't useful */
231 if (p->chunks[i].length_dw == 0)
234 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS) {
235 p->chunk_flags_idx = i;
236 /* zero length flags aren't useful */
237 if (p->chunks[i].length_dw == 0)
241 cdata = (uint32_t *)(unsigned long)user_chunk.chunk_data;
242 if ((p->chunks[i].chunk_id == RADEON_CHUNK_ID_RELOCS) ||
243 (p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS)) {
244 size = p->chunks[i].length_dw * sizeof(uint32_t);
245 p->chunks[i].kdata = kmalloc(size, GFP_KERNEL);
246 if (p->chunks[i].kdata == NULL) {
249 if (DRM_COPY_FROM_USER(p->chunks[i].kdata,
250 p->chunks[i].user_ptr, size)) {
253 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS) {
254 p->cs_flags = p->chunks[i].kdata[0];
255 if (p->chunks[i].length_dw > 1)
256 ring = p->chunks[i].kdata[1];
257 if (p->chunks[i].length_dw > 2)
258 priority = (s32)p->chunks[i].kdata[2];
263 /* these are KMS only */
265 if ((p->cs_flags & RADEON_CS_USE_VM) &&
266 !p->rdev->vm_manager.enabled) {
267 DRM_ERROR("VM not active on asic!\n");
271 if (radeon_cs_get_ring(p, ring, priority))
274 /* we only support VM on some SI+ rings */
275 if ((p->rdev->asic->ring[p->ring]->cs_parse == NULL) &&
276 ((p->cs_flags & RADEON_CS_USE_VM) == 0)) {
277 DRM_ERROR("Ring %d requires VM!\n", p->ring);
282 /* deal with non-vm */
283 if ((p->chunk_ib_idx != -1) &&
284 ((p->cs_flags & RADEON_CS_USE_VM) == 0) &&
285 (p->chunks[p->chunk_ib_idx].chunk_id == RADEON_CHUNK_ID_IB)) {
286 if (p->chunks[p->chunk_ib_idx].length_dw > (16 * 1024)) {
287 DRM_ERROR("cs IB too big: %d\n",
288 p->chunks[p->chunk_ib_idx].length_dw);
291 if (p->rdev && (p->rdev->flags & RADEON_IS_AGP)) {
292 p->chunks[p->chunk_ib_idx].kpage[0] = kmalloc(PAGE_SIZE, GFP_KERNEL);
293 p->chunks[p->chunk_ib_idx].kpage[1] = kmalloc(PAGE_SIZE, GFP_KERNEL);
294 if (p->chunks[p->chunk_ib_idx].kpage[0] == NULL ||
295 p->chunks[p->chunk_ib_idx].kpage[1] == NULL) {
296 kfree(p->chunks[p->chunk_ib_idx].kpage[0]);
297 kfree(p->chunks[p->chunk_ib_idx].kpage[1]);
298 p->chunks[p->chunk_ib_idx].kpage[0] = NULL;
299 p->chunks[p->chunk_ib_idx].kpage[1] = NULL;
303 p->chunks[p->chunk_ib_idx].kpage_idx[0] = -1;
304 p->chunks[p->chunk_ib_idx].kpage_idx[1] = -1;
305 p->chunks[p->chunk_ib_idx].last_copied_page = -1;
306 p->chunks[p->chunk_ib_idx].last_page_index =
307 ((p->chunks[p->chunk_ib_idx].length_dw * 4) - 1) / PAGE_SIZE;
314 * cs_parser_fini() - clean parser states
315 * @parser: parser structure holding parsing context.
316 * @error: error number
318 * If error is set than unvalidate buffer, otherwise just free memory
319 * used by parsing context.
321 static void radeon_cs_parser_fini(struct radeon_cs_parser *parser, int error, bool backoff)
326 ttm_eu_fence_buffer_objects(&parser->ticket,
329 } else if (backoff) {
330 ttm_eu_backoff_reservation(&parser->ticket,
334 if (parser->relocs != NULL) {
335 for (i = 0; i < parser->nrelocs; i++) {
336 if (parser->relocs[i].gobj)
337 drm_gem_object_unreference_unlocked(parser->relocs[i].gobj);
340 kfree(parser->track);
341 kfree(parser->relocs);
342 kfree(parser->relocs_ptr);
343 for (i = 0; i < parser->nchunks; i++) {
344 kfree(parser->chunks[i].kdata);
345 if ((parser->rdev->flags & RADEON_IS_AGP)) {
346 kfree(parser->chunks[i].kpage[0]);
347 kfree(parser->chunks[i].kpage[1]);
350 kfree(parser->chunks);
351 kfree(parser->chunks_array);
352 radeon_ib_free(parser->rdev, &parser->ib);
353 radeon_ib_free(parser->rdev, &parser->const_ib);
356 static int radeon_cs_ib_chunk(struct radeon_device *rdev,
357 struct radeon_cs_parser *parser)
359 struct radeon_cs_chunk *ib_chunk;
362 if (parser->chunk_ib_idx == -1)
365 if (parser->cs_flags & RADEON_CS_USE_VM)
368 ib_chunk = &parser->chunks[parser->chunk_ib_idx];
369 /* Copy the packet into the IB, the parser will read from the
370 * input memory (cached) and write to the IB (which can be
373 r = radeon_ib_get(rdev, parser->ring, &parser->ib,
374 NULL, ib_chunk->length_dw * 4);
376 DRM_ERROR("Failed to get ib !\n");
379 parser->ib.length_dw = ib_chunk->length_dw;
380 r = radeon_cs_parse(rdev, parser->ring, parser);
381 if (r || parser->parser_error) {
382 DRM_ERROR("Invalid command stream !\n");
385 r = radeon_cs_finish_pages(parser);
387 DRM_ERROR("Invalid command stream !\n");
391 if (parser->ring == R600_RING_TYPE_UVD_INDEX)
392 radeon_uvd_note_usage(rdev);
394 radeon_cs_sync_rings(parser);
395 r = radeon_ib_schedule(rdev, &parser->ib, NULL);
397 DRM_ERROR("Failed to schedule IB !\n");
402 static int radeon_bo_vm_update_pte(struct radeon_cs_parser *parser,
403 struct radeon_vm *vm)
405 struct radeon_device *rdev = parser->rdev;
406 struct radeon_bo_list *lobj;
407 struct radeon_bo *bo;
410 r = radeon_vm_bo_update_pte(rdev, vm, rdev->ring_tmp_bo.bo, &rdev->ring_tmp_bo.bo->tbo.mem);
414 list_for_each_entry(lobj, &parser->validated, tv.head) {
416 r = radeon_vm_bo_update_pte(parser->rdev, vm, bo, &bo->tbo.mem);
424 static int radeon_cs_ib_vm_chunk(struct radeon_device *rdev,
425 struct radeon_cs_parser *parser)
427 struct radeon_cs_chunk *ib_chunk;
428 struct radeon_fpriv *fpriv = parser->filp->driver_priv;
429 struct radeon_vm *vm = &fpriv->vm;
432 if (parser->chunk_ib_idx == -1)
434 if ((parser->cs_flags & RADEON_CS_USE_VM) == 0)
437 if ((rdev->family >= CHIP_TAHITI) &&
438 (parser->chunk_const_ib_idx != -1)) {
439 ib_chunk = &parser->chunks[parser->chunk_const_ib_idx];
440 if (ib_chunk->length_dw > RADEON_IB_VM_MAX_SIZE) {
441 DRM_ERROR("cs IB CONST too big: %d\n", ib_chunk->length_dw);
444 r = radeon_ib_get(rdev, parser->ring, &parser->const_ib,
445 vm, ib_chunk->length_dw * 4);
447 DRM_ERROR("Failed to get const ib !\n");
450 parser->const_ib.is_const_ib = true;
451 parser->const_ib.length_dw = ib_chunk->length_dw;
452 /* Copy the packet into the IB */
453 if (DRM_COPY_FROM_USER(parser->const_ib.ptr, ib_chunk->user_ptr,
454 ib_chunk->length_dw * 4)) {
457 r = radeon_ring_ib_parse(rdev, parser->ring, &parser->const_ib);
463 ib_chunk = &parser->chunks[parser->chunk_ib_idx];
464 if (ib_chunk->length_dw > RADEON_IB_VM_MAX_SIZE) {
465 DRM_ERROR("cs IB too big: %d\n", ib_chunk->length_dw);
468 r = radeon_ib_get(rdev, parser->ring, &parser->ib,
469 vm, ib_chunk->length_dw * 4);
471 DRM_ERROR("Failed to get ib !\n");
474 parser->ib.length_dw = ib_chunk->length_dw;
475 /* Copy the packet into the IB */
476 if (DRM_COPY_FROM_USER(parser->ib.ptr, ib_chunk->user_ptr,
477 ib_chunk->length_dw * 4)) {
480 r = radeon_ring_ib_parse(rdev, parser->ring, &parser->ib);
485 if (parser->ring == R600_RING_TYPE_UVD_INDEX)
486 radeon_uvd_note_usage(rdev);
488 mutex_lock(&rdev->vm_manager.lock);
489 mutex_lock(&vm->mutex);
490 r = radeon_vm_alloc_pt(rdev, vm);
494 r = radeon_bo_vm_update_pte(parser, vm);
498 radeon_cs_sync_rings(parser);
499 radeon_ib_sync_to(&parser->ib, vm->fence);
500 radeon_ib_sync_to(&parser->ib, radeon_vm_grab_id(
501 rdev, vm, parser->ring));
503 if ((rdev->family >= CHIP_TAHITI) &&
504 (parser->chunk_const_ib_idx != -1)) {
505 r = radeon_ib_schedule(rdev, &parser->ib, &parser->const_ib);
507 r = radeon_ib_schedule(rdev, &parser->ib, NULL);
511 radeon_vm_fence(rdev, vm, parser->ib.fence);
515 radeon_vm_add_to_lru(rdev, vm);
516 mutex_unlock(&vm->mutex);
517 mutex_unlock(&rdev->vm_manager.lock);
521 static int radeon_cs_handle_lockup(struct radeon_device *rdev, int r)
524 r = radeon_gpu_reset(rdev);
531 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
533 struct radeon_device *rdev = dev->dev_private;
534 struct radeon_cs_parser parser;
537 down_read(&rdev->exclusive_lock);
538 if (!rdev->accel_working) {
539 up_read(&rdev->exclusive_lock);
542 /* initialize parser */
543 memset(&parser, 0, sizeof(struct radeon_cs_parser));
546 parser.dev = rdev->dev;
547 parser.family = rdev->family;
548 r = radeon_cs_parser_init(&parser, data);
550 DRM_ERROR("Failed to initialize parser !\n");
551 radeon_cs_parser_fini(&parser, r, false);
552 up_read(&rdev->exclusive_lock);
553 r = radeon_cs_handle_lockup(rdev, r);
556 r = radeon_cs_parser_relocs(&parser);
558 if (r != -ERESTARTSYS)
559 DRM_ERROR("Failed to parse relocation %d!\n", r);
560 radeon_cs_parser_fini(&parser, r, false);
561 up_read(&rdev->exclusive_lock);
562 r = radeon_cs_handle_lockup(rdev, r);
566 trace_radeon_cs(&parser);
568 r = radeon_cs_ib_chunk(rdev, &parser);
572 r = radeon_cs_ib_vm_chunk(rdev, &parser);
577 radeon_cs_parser_fini(&parser, r, true);
578 up_read(&rdev->exclusive_lock);
579 r = radeon_cs_handle_lockup(rdev, r);
583 int radeon_cs_finish_pages(struct radeon_cs_parser *p)
585 struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
587 int size = PAGE_SIZE;
589 for (i = ibc->last_copied_page + 1; i <= ibc->last_page_index; i++) {
590 if (i == ibc->last_page_index) {
591 size = (ibc->length_dw * 4) % PAGE_SIZE;
596 if (DRM_COPY_FROM_USER(p->ib.ptr + (i * (PAGE_SIZE/4)),
597 ibc->user_ptr + (i * PAGE_SIZE),
604 static int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx)
607 struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
609 int size = PAGE_SIZE;
610 bool copy1 = (p->rdev && (p->rdev->flags & RADEON_IS_AGP)) ?
613 for (i = ibc->last_copied_page + 1; i < pg_idx; i++) {
614 if (DRM_COPY_FROM_USER(p->ib.ptr + (i * (PAGE_SIZE/4)),
615 ibc->user_ptr + (i * PAGE_SIZE),
617 p->parser_error = -EFAULT;
622 if (pg_idx == ibc->last_page_index) {
623 size = (ibc->length_dw * 4) % PAGE_SIZE;
628 new_page = ibc->kpage_idx[0] < ibc->kpage_idx[1] ? 0 : 1;
630 ibc->kpage[new_page] = p->ib.ptr + (pg_idx * (PAGE_SIZE / 4));
632 if (DRM_COPY_FROM_USER(ibc->kpage[new_page],
633 ibc->user_ptr + (pg_idx * PAGE_SIZE),
635 p->parser_error = -EFAULT;
639 /* copy to IB for non single case */
641 memcpy((void *)(p->ib.ptr+(pg_idx*(PAGE_SIZE/4))), ibc->kpage[new_page], size);
643 ibc->last_copied_page = pg_idx;
644 ibc->kpage_idx[new_page] = pg_idx;
649 u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
651 struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
652 u32 pg_idx, pg_offset;
656 pg_idx = (idx * 4) / PAGE_SIZE;
657 pg_offset = (idx * 4) % PAGE_SIZE;
659 if (ibc->kpage_idx[0] == pg_idx)
660 return ibc->kpage[0][pg_offset/4];
661 if (ibc->kpage_idx[1] == pg_idx)
662 return ibc->kpage[1][pg_offset/4];
664 new_page = radeon_cs_update_pages(p, pg_idx);
666 p->parser_error = new_page;
670 idx_value = ibc->kpage[new_page][pg_offset/4];
675 * radeon_cs_packet_parse() - parse cp packet and point ib index to next packet
676 * @parser: parser structure holding parsing context.
677 * @pkt: where to store packet information
679 * Assume that chunk_ib_index is properly set. Will return -EINVAL
680 * if packet is bigger than remaining ib size. or if packets is unknown.
682 int radeon_cs_packet_parse(struct radeon_cs_parser *p,
683 struct radeon_cs_packet *pkt,
686 struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
687 struct radeon_device *rdev = p->rdev;
690 if (idx >= ib_chunk->length_dw) {
691 DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
692 idx, ib_chunk->length_dw);
695 header = radeon_get_ib_value(p, idx);
697 pkt->type = RADEON_CP_PACKET_GET_TYPE(header);
698 pkt->count = RADEON_CP_PACKET_GET_COUNT(header);
701 case RADEON_PACKET_TYPE0:
702 if (rdev->family < CHIP_R600) {
703 pkt->reg = R100_CP_PACKET0_GET_REG(header);
705 RADEON_CP_PACKET0_GET_ONE_REG_WR(header);
707 pkt->reg = R600_CP_PACKET0_GET_REG(header);
709 case RADEON_PACKET_TYPE3:
710 pkt->opcode = RADEON_CP_PACKET3_GET_OPCODE(header);
712 case RADEON_PACKET_TYPE2:
716 DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx);
719 if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) {
720 DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
721 pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw);
728 * radeon_cs_packet_next_is_pkt3_nop() - test if the next packet is P3 NOP
729 * @p: structure holding the parser context.
731 * Check if the next packet is NOP relocation packet3.
733 bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p)
735 struct radeon_cs_packet p3reloc;
738 r = radeon_cs_packet_parse(p, &p3reloc, p->idx);
741 if (p3reloc.type != RADEON_PACKET_TYPE3)
743 if (p3reloc.opcode != RADEON_PACKET3_NOP)
749 * radeon_cs_dump_packet() - dump raw packet context
750 * @p: structure holding the parser context.
751 * @pkt: structure holding the packet.
753 * Used mostly for debugging and error reporting.
755 void radeon_cs_dump_packet(struct radeon_cs_parser *p,
756 struct radeon_cs_packet *pkt)
758 volatile uint32_t *ib;
764 for (i = 0; i <= (pkt->count + 1); i++, idx++)
765 DRM_INFO("ib[%d]=0x%08X\n", idx, ib[idx]);
769 * radeon_cs_packet_next_reloc() - parse next (should be reloc) packet
770 * @parser: parser structure holding parsing context.
771 * @data: pointer to relocation data
772 * @offset_start: starting offset
773 * @offset_mask: offset mask (to align start offset on)
774 * @reloc: reloc informations
776 * Check if next packet is relocation packet3, do bo validation and compute
777 * GPU offset using the provided start.
779 int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p,
780 struct radeon_cs_reloc **cs_reloc,
783 struct radeon_cs_chunk *relocs_chunk;
784 struct radeon_cs_packet p3reloc;
788 if (p->chunk_relocs_idx == -1) {
789 DRM_ERROR("No relocation chunk !\n");
793 relocs_chunk = &p->chunks[p->chunk_relocs_idx];
794 r = radeon_cs_packet_parse(p, &p3reloc, p->idx);
797 p->idx += p3reloc.count + 2;
798 if (p3reloc.type != RADEON_PACKET_TYPE3 ||
799 p3reloc.opcode != RADEON_PACKET3_NOP) {
800 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
802 radeon_cs_dump_packet(p, &p3reloc);
805 idx = radeon_get_ib_value(p, p3reloc.idx + 1);
806 if (idx >= relocs_chunk->length_dw) {
807 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
808 idx, relocs_chunk->length_dw);
809 radeon_cs_dump_packet(p, &p3reloc);
812 /* FIXME: we assume reloc size is 4 dwords */
814 *cs_reloc = p->relocs;
815 (*cs_reloc)->lobj.gpu_offset =
816 (u64)relocs_chunk->kdata[idx + 3] << 32;
817 (*cs_reloc)->lobj.gpu_offset |= relocs_chunk->kdata[idx + 0];
819 *cs_reloc = p->relocs_ptr[(idx / 4)];