drivers/gpu/drm/radeon/radeon_cp.c

   1 /* radeon_cp.c -- CP support for Radeon -*- linux-c -*- */
   2 /*
   3  * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
   4  * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
   5  * Copyright 2007 Advanced Micro Devices, Inc.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the "Software"),
  10  * to deal in the Software without restriction, including without limitation
  11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12  * and/or sell copies of the Software, and to permit persons to whom the
  13  * Software is furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the next
  16  * paragraph) shall be included in all copies or substantial portions of the
  17  * Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  22  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  23  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  24  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  25  * DEALINGS IN THE SOFTWARE.
  26  *
  27  * Authors:
  28  *    Kevin E. Martin <martin@valinux.com>
  29  *    Gareth Hughes <gareth@valinux.com>
  30  */
  31
  32 #include <linux/module.h>
  33
  34 #include <drm/drmP.h>
  35 #include <drm/radeon_drm.h>
  36 #include "radeon_drv.h"
  37 #include "r300_reg.h"
  38
  39 #define RADEON_FIFO_DEBUG       0
  40
  41 /* Firmware Names */
  42 #define FIRMWARE_R100           "radeon/R100_cp.bin"
  43 #define FIRMWARE_R200           "radeon/R200_cp.bin"
  44 #define FIRMWARE_R300           "radeon/R300_cp.bin"
  45 #define FIRMWARE_R420           "radeon/R420_cp.bin"
  46 #define FIRMWARE_RS690          "radeon/RS690_cp.bin"
  47 #define FIRMWARE_RS600          "radeon/RS600_cp.bin"
  48 #define FIRMWARE_R520           "radeon/R520_cp.bin"
  49
  50 MODULE_FIRMWARE(FIRMWARE_R100);
  51 MODULE_FIRMWARE(FIRMWARE_R200);
  52 MODULE_FIRMWARE(FIRMWARE_R300);
  53 MODULE_FIRMWARE(FIRMWARE_R420);
  54 MODULE_FIRMWARE(FIRMWARE_RS690);
  55 MODULE_FIRMWARE(FIRMWARE_RS600);
  56 MODULE_FIRMWARE(FIRMWARE_R520);
  57
  58 static int radeon_do_cleanup_cp(struct drm_device * dev);
  59 static void radeon_do_cp_start(drm_radeon_private_t * dev_priv);
  60
  61 u32 radeon_read_ring_rptr(drm_radeon_private_t *dev_priv, u32 off)
  62 {
  63         u32 val;
  64
  65         if (dev_priv->flags & RADEON_IS_AGP) {
  66                 val = DRM_READ32(dev_priv->ring_rptr, off);
  67         } else {
  68                 val = *(((volatile u32 *)
  69                          dev_priv->ring_rptr->handle) +
  70                         (off / sizeof(u32)));
  71                 val = le32_to_cpu(val);
  72         }
  73         return val;
  74 }
  75
  76 u32 radeon_get_ring_head(drm_radeon_private_t *dev_priv)
  77 {
  78         if (dev_priv->writeback_works)
  79                 return radeon_read_ring_rptr(dev_priv, 0);
  80         else {
  81                 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
  82                         return RADEON_READ(R600_CP_RB_RPTR);
  83                 else
  84                         return RADEON_READ(RADEON_CP_RB_RPTR);
  85         }
  86 }
  87
  88 void radeon_write_ring_rptr(drm_radeon_private_t *dev_priv, u32 off, u32 val)
  89 {
  90         if (dev_priv->flags & RADEON_IS_AGP)
  91                 DRM_WRITE32(dev_priv->ring_rptr, off, val);
  92         else
  93                 *(((volatile u32 *) dev_priv->ring_rptr->handle) +
  94                   (off / sizeof(u32))) = cpu_to_le32(val);
  95 }
  96
  97 void radeon_set_ring_head(drm_radeon_private_t *dev_priv, u32 val)
  98 {
  99         radeon_write_ring_rptr(dev_priv, 0, val);
 100 }
 101
 102 u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index)
 103 {
 104         if (dev_priv->writeback_works) {
 105                 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
 106                         return radeon_read_ring_rptr(dev_priv,
 107                                                      R600_SCRATCHOFF(index));
 108                 else
 109                         return radeon_read_ring_rptr(dev_priv,
 110                                                      RADEON_SCRATCHOFF(index));
 111         } else {
 112                 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
 113                         return RADEON_READ(R600_SCRATCH_REG0 + 4*index);
 114                 else
 115                         return RADEON_READ(RADEON_SCRATCH_REG0 + 4*index);
 116         }
 117 }
 118
 119 static u32 R500_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
 120 {
 121         u32 ret;
 122         RADEON_WRITE(R520_MC_IND_INDEX, 0x7f0000 | (addr & 0xff));
 123         ret = RADEON_READ(R520_MC_IND_DATA);
 124         RADEON_WRITE(R520_MC_IND_INDEX, 0);
 125         return ret;
 126 }
 127
 128 static u32 RS480_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
 129 {
 130         u32 ret;
 131         RADEON_WRITE(RS480_NB_MC_INDEX, addr & 0xff);
 132         ret = RADEON_READ(RS480_NB_MC_DATA);
 133         RADEON_WRITE(RS480_NB_MC_INDEX, 0xff);
 134         return ret;
 135 }
 136
 137 static u32 RS690_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
 138 {
 139         u32 ret;
 140         RADEON_WRITE(RS690_MC_INDEX, (addr & RS690_MC_INDEX_MASK));
 141         ret = RADEON_READ(RS690_MC_DATA);
 142         RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_MASK);
 143         return ret;
 144 }
 145
 146 static u32 RS600_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
 147 {
 148         u32 ret;
 149         RADEON_WRITE(RS600_MC_INDEX, ((addr & RS600_MC_ADDR_MASK) |
 150                                       RS600_MC_IND_CITF_ARB0));
 151         ret = RADEON_READ(RS600_MC_DATA);
 152         return ret;
 153 }
 154
 155 static u32 IGP_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
 156 {
 157         if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
 158             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
 159                 return RS690_READ_MCIND(dev_priv, addr);
 160         else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
 161                 return RS600_READ_MCIND(dev_priv, addr);
 162         else
 163                 return RS480_READ_MCIND(dev_priv, addr);
 164 }
 165
 166 u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv)
 167 {
 168
 169         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)
 170                 return RADEON_READ(R700_MC_VM_FB_LOCATION);
 171         else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
 172                 return RADEON_READ(R600_MC_VM_FB_LOCATION);
 173         else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
 174                 return R500_READ_MCIND(dev_priv, RV515_MC_FB_LOCATION);
 175         else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
 176                  ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
 177                 return RS690_READ_MCIND(dev_priv, RS690_MC_FB_LOCATION);
 178         else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
 179                 return RS600_READ_MCIND(dev_priv, RS600_MC_FB_LOCATION);
 180         else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
 181                 return R500_READ_MCIND(dev_priv, R520_MC_FB_LOCATION);
 182         else
 183                 return RADEON_READ(RADEON_MC_FB_LOCATION);
 184 }
 185
 186 static void radeon_write_fb_location(drm_radeon_private_t *dev_priv, u32 fb_loc)
 187 {
 188         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)
 189                 RADEON_WRITE(R700_MC_VM_FB_LOCATION, fb_loc);
 190         else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
 191                 RADEON_WRITE(R600_MC_VM_FB_LOCATION, fb_loc);
 192         else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
 193                 R500_WRITE_MCIND(RV515_MC_FB_LOCATION, fb_loc);
 194         else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
 195                  ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
 196                 RS690_WRITE_MCIND(RS690_MC_FB_LOCATION, fb_loc);
 197         else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
 198                 RS600_WRITE_MCIND(RS600_MC_FB_LOCATION, fb_loc);
 199         else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
 200                 R500_WRITE_MCIND(R520_MC_FB_LOCATION, fb_loc);
 201         else
 202                 RADEON_WRITE(RADEON_MC_FB_LOCATION, fb_loc);
 203 }
 204
 205 void radeon_write_agp_location(drm_radeon_private_t *dev_priv, u32 agp_loc)
 206 {
 207         /*R6xx/R7xx: AGP_TOP and BOT are actually 18 bits each */
 208         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770) {
 209                 RADEON_WRITE(R700_MC_VM_AGP_BOT, agp_loc & 0xffff); /* FIX ME */
 210                 RADEON_WRITE(R700_MC_VM_AGP_TOP, (agp_loc >> 16) & 0xffff);
 211         } else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) {
 212                 RADEON_WRITE(R600_MC_VM_AGP_BOT, agp_loc & 0xffff); /* FIX ME */
 213                 RADEON_WRITE(R600_MC_VM_AGP_TOP, (agp_loc >> 16) & 0xffff);
 214         } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
 215                 R500_WRITE_MCIND(RV515_MC_AGP_LOCATION, agp_loc);
 216         else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
 217                  ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
 218                 RS690_WRITE_MCIND(RS690_MC_AGP_LOCATION, agp_loc);
 219         else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
 220                 RS600_WRITE_MCIND(RS600_MC_AGP_LOCATION, agp_loc);
 221         else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
 222                 R500_WRITE_MCIND(R520_MC_AGP_LOCATION, agp_loc);
 223         else
 224                 RADEON_WRITE(RADEON_MC_AGP_LOCATION, agp_loc);
 225 }
 226
 227 void radeon_write_agp_base(drm_radeon_private_t *dev_priv, u64 agp_base)
 228 {
 229         u32 agp_base_hi = upper_32_bits(agp_base);
 230         u32 agp_base_lo = agp_base & 0xffffffff;
 231         u32 r6xx_agp_base = (agp_base >> 22) & 0x3ffff;
 232
 233         /* R6xx/R7xx must be aligned to a 4MB boundary */
 234         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)
 235                 RADEON_WRITE(R700_MC_VM_AGP_BASE, r6xx_agp_base);
 236         else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
 237                 RADEON_WRITE(R600_MC_VM_AGP_BASE, r6xx_agp_base);
 238         else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) {
 239                 R500_WRITE_MCIND(RV515_MC_AGP_BASE, agp_base_lo);
 240                 R500_WRITE_MCIND(RV515_MC_AGP_BASE_2, agp_base_hi);
 241         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
 242                  ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) {
 243                 RS690_WRITE_MCIND(RS690_MC_AGP_BASE, agp_base_lo);
 244                 RS690_WRITE_MCIND(RS690_MC_AGP_BASE_2, agp_base_hi);
 245         } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) {
 246                 RS600_WRITE_MCIND(RS600_AGP_BASE, agp_base_lo);
 247                 RS600_WRITE_MCIND(RS600_AGP_BASE_2, agp_base_hi);
 248         } else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) {
 249                 R500_WRITE_MCIND(R520_MC_AGP_BASE, agp_base_lo);
 250                 R500_WRITE_MCIND(R520_MC_AGP_BASE_2, agp_base_hi);
 251         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) ||
 252                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
 253                 RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo);
 254                 RADEON_WRITE(RS480_AGP_BASE_2, agp_base_hi);
 255         } else {
 256                 RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo);
 257                 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R200)
 258                         RADEON_WRITE(RADEON_AGP_BASE_2, agp_base_hi);
 259         }
 260 }
 261
 262 void radeon_enable_bm(struct drm_radeon_private *dev_priv)
 263 {
 264         u32 tmp;
 265         /* Turn on bus mastering */
 266         if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
 267             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) {
 268                 /* rs600/rs690/rs740 */
 269                 tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS;
 270                 RADEON_WRITE(RADEON_BUS_CNTL, tmp);
 271         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV350) ||
 272                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) ||
 273                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) ||
 274                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
 275                 /* r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
 276                 tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
 277                 RADEON_WRITE(RADEON_BUS_CNTL, tmp);
 278         } /* PCIE cards appears to not need this */
 279 }
 280
 281 static int RADEON_READ_PLL(struct drm_device * dev, int addr)
 282 {
 283         drm_radeon_private_t *dev_priv = dev->dev_private;
 284
 285         RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, addr & 0x1f);
 286         return RADEON_READ(RADEON_CLOCK_CNTL_DATA);
 287 }
 288
 289 static u32 RADEON_READ_PCIE(drm_radeon_private_t *dev_priv, int addr)
 290 {
 291         RADEON_WRITE8(RADEON_PCIE_INDEX, addr & 0xff);
 292         return RADEON_READ(RADEON_PCIE_DATA);
 293 }
 294
 295 #if RADEON_FIFO_DEBUG
 296 static void radeon_status(drm_radeon_private_t * dev_priv)
 297 {
 298         printk("%s:\n", __func__);
 299         printk("RBBM_STATUS = 0x%08x\n",
 300                (unsigned int)RADEON_READ(RADEON_RBBM_STATUS));
 301         printk("CP_RB_RTPR = 0x%08x\n",
 302                (unsigned int)RADEON_READ(RADEON_CP_RB_RPTR));
 303         printk("CP_RB_WTPR = 0x%08x\n",
 304                (unsigned int)RADEON_READ(RADEON_CP_RB_WPTR));
 305         printk("AIC_CNTL = 0x%08x\n",
 306                (unsigned int)RADEON_READ(RADEON_AIC_CNTL));
 307         printk("AIC_STAT = 0x%08x\n",
 308                (unsigned int)RADEON_READ(RADEON_AIC_STAT));
 309         printk("AIC_PT_BASE = 0x%08x\n",
 310                (unsigned int)RADEON_READ(RADEON_AIC_PT_BASE));
 311         printk("TLB_ADDR = 0x%08x\n",
 312                (unsigned int)RADEON_READ(RADEON_AIC_TLB_ADDR));
 313         printk("TLB_DATA = 0x%08x\n",
 314                (unsigned int)RADEON_READ(RADEON_AIC_TLB_DATA));
 315 }
 316 #endif
 317
 318 /* ================================================================
 319  * Engine, FIFO control
 320  */
 321
 322 static int radeon_do_pixcache_flush(drm_radeon_private_t * dev_priv)
 323 {
 324         u32 tmp;
 325         int i;
 326
 327         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
 328
 329         if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) {
 330                 tmp = RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT);
 331                 tmp |= RADEON_RB3D_DC_FLUSH_ALL;
 332                 RADEON_WRITE(RADEON_RB3D_DSTCACHE_CTLSTAT, tmp);
 333
 334                 for (i = 0; i < dev_priv->usec_timeout; i++) {
 335                         if (!(RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT)
 336                               & RADEON_RB3D_DC_BUSY)) {
 337                                 return 0;
 338                         }
 339                         DRM_UDELAY(1);
 340                 }
 341         } else {
 342                 /* don't flush or purge cache here or lockup */
 343                 return 0;
 344         }
 345
 346 #if RADEON_FIFO_DEBUG
 347         DRM_ERROR("failed!\n");
 348         radeon_status(dev_priv);
 349 #endif
 350         return -EBUSY;
 351 }
 352
 353 static int radeon_do_wait_for_fifo(drm_radeon_private_t * dev_priv, int entries)
 354 {
 355         int i;
 356
 357         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
 358
 359         for (i = 0; i < dev_priv->usec_timeout; i++) {
 360                 int slots = (RADEON_READ(RADEON_RBBM_STATUS)
 361                              & RADEON_RBBM_FIFOCNT_MASK);
 362                 if (slots >= entries)
 363                         return 0;
 364                 DRM_UDELAY(1);
 365         }
 366         DRM_DEBUG("wait for fifo failed status : 0x%08X 0x%08X\n",
 367                  RADEON_READ(RADEON_RBBM_STATUS),
 368                  RADEON_READ(R300_VAP_CNTL_STATUS));
 369
 370 #if RADEON_FIFO_DEBUG
 371         DRM_ERROR("failed!\n");
 372         radeon_status(dev_priv);
 373 #endif
 374         return -EBUSY;
 375 }
 376
 377 static int radeon_do_wait_for_idle(drm_radeon_private_t * dev_priv)
 378 {
 379         int i, ret;
 380
 381         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
 382
 383         ret = radeon_do_wait_for_fifo(dev_priv, 64);
 384         if (ret)
 385                 return ret;
 386
 387         for (i = 0; i < dev_priv->usec_timeout; i++) {
 388                 if (!(RADEON_READ(RADEON_RBBM_STATUS)
 389                       & RADEON_RBBM_ACTIVE)) {
 390                         radeon_do_pixcache_flush(dev_priv);
 391                         return 0;
 392                 }
 393                 DRM_UDELAY(1);
 394         }
 395         DRM_DEBUG("wait idle failed status : 0x%08X 0x%08X\n",
 396                  RADEON_READ(RADEON_RBBM_STATUS),
 397                  RADEON_READ(R300_VAP_CNTL_STATUS));
 398
 399 #if RADEON_FIFO_DEBUG
 400         DRM_ERROR("failed!\n");
 401         radeon_status(dev_priv);
 402 #endif
 403         return -EBUSY;
 404 }
 405
 406 static void radeon_init_pipes(struct drm_device *dev)
 407 {
 408         drm_radeon_private_t *dev_priv = dev->dev_private;
 409         uint32_t gb_tile_config, gb_pipe_sel = 0;
 410
 411         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV530) {
 412                 uint32_t z_pipe_sel = RADEON_READ(RV530_GB_PIPE_SELECT2);
 413                 if ((z_pipe_sel & 3) == 3)
 414                         dev_priv->num_z_pipes = 2;
 415                 else
 416                         dev_priv->num_z_pipes = 1;
 417         } else
 418                 dev_priv->num_z_pipes = 1;
 419
 420         /* RS4xx/RS6xx/R4xx/R5xx */
 421         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R420) {
 422                 gb_pipe_sel = RADEON_READ(R400_GB_PIPE_SELECT);
 423                 dev_priv->num_gb_pipes = ((gb_pipe_sel >> 12) & 0x3) + 1;
 424                 /* SE cards have 1 pipe */
 425                 if ((dev->pdev->device == 0x5e4c) ||
 426                     (dev->pdev->device == 0x5e4f))
 427                         dev_priv->num_gb_pipes = 1;
 428         } else {
 429                 /* R3xx */
 430                 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300 &&
 431                      dev->pdev->device != 0x4144) ||
 432                     ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350 &&
 433                      dev->pdev->device != 0x4148)) {
 434                         dev_priv->num_gb_pipes = 2;
 435                 } else {
 436                         /* RV3xx/R300 AD/R350 AH */
 437                         dev_priv->num_gb_pipes = 1;
 438                 }
 439         }
 440         DRM_INFO("Num pipes: %d\n", dev_priv->num_gb_pipes);
 441
 442         gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16 /*| R300_SUBPIXEL_1_16*/);
 443
 444         switch (dev_priv->num_gb_pipes) {
 445         case 2: gb_tile_config |= R300_PIPE_COUNT_R300; break;
 446         case 3: gb_tile_config |= R300_PIPE_COUNT_R420_3P; break;
 447         case 4: gb_tile_config |= R300_PIPE_COUNT_R420; break;
 448         default:
 449         case 1: gb_tile_config |= R300_PIPE_COUNT_RV350; break;
 450         }
 451
 452         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV515) {
 453                 RADEON_WRITE_PLL(R500_DYN_SCLK_PWMEM_PIPE, (1 | ((gb_pipe_sel >> 8) & 0xf) << 4));
 454                 RADEON_WRITE(R300_SU_REG_DEST, ((1 << dev_priv->num_gb_pipes) - 1));
 455         }
 456         RADEON_WRITE(R300_GB_TILE_CONFIG, gb_tile_config);
 457         radeon_do_wait_for_idle(dev_priv);
 458         RADEON_WRITE(R300_DST_PIPE_CONFIG, RADEON_READ(R300_DST_PIPE_CONFIG) | R300_PIPE_AUTO_CONFIG);
 459         RADEON_WRITE(R300_RB2D_DSTCACHE_MODE, (RADEON_READ(R300_RB2D_DSTCACHE_MODE) |
 460                                                R300_DC_AUTOFLUSH_ENABLE |
 461                                                R300_DC_DC_DISABLE_IGNORE_PE));
 462
 463
 464 }
 465
 466 /* ================================================================
 467  * CP control, initialization
 468  */
 469
 470 /* Load the microcode for the CP */
 471 static int radeon_cp_init_microcode(drm_radeon_private_t *dev_priv)
 472 {
 473         struct platform_device *pdev;
 474         const char *fw_name = NULL;
 475         int err;
 476
 477         DRM_DEBUG("\n");
 478
 479         pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
 480         err = IS_ERR(pdev);
 481         if (err) {
 482                 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
 483                 return -EINVAL;
 484         }
 485
 486         if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R100) ||
 487             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV100) ||
 488             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV200) ||
 489             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS100) ||
 490             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS200)) {
 491                 DRM_INFO("Loading R100 Microcode\n");
 492                 fw_name = FIRMWARE_R100;
 493         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R200) ||
 494                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV250) ||
 495                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV280) ||
 496                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS300)) {
 497                 DRM_INFO("Loading R200 Microcode\n");
 498                 fw_name = FIRMWARE_R200;
 499         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300) ||
 500                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350) ||
 501                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV350) ||
 502                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV380) ||
 503                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) ||
 504                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
 505                 DRM_INFO("Loading R300 Microcode\n");
 506                 fw_name = FIRMWARE_R300;
 507         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) ||
 508                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R423) ||
 509                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV410)) {
 510                 DRM_INFO("Loading R400 Microcode\n");
 511                 fw_name = FIRMWARE_R420;
 512         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
 513                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) {
 514                 DRM_INFO("Loading RS690/RS740 Microcode\n");
 515                 fw_name = FIRMWARE_RS690;
 516         } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) {
 517                 DRM_INFO("Loading RS600 Microcode\n");
 518                 fw_name = FIRMWARE_RS600;
 519         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) ||
 520                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R520) ||
 521                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV530) ||
 522                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R580) ||
 523                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV560) ||
 524                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV570)) {
 525                 DRM_INFO("Loading R500 Microcode\n");
 526                 fw_name = FIRMWARE_R520;
 527         }
 528
 529         err = request_firmware(&dev_priv->me_fw, fw_name, &pdev->dev);
 530         platform_device_unregister(pdev);
 531         if (err) {
 532                 printk(KERN_ERR "radeon_cp: Failed to load firmware \"%s\"\n",
 533                        fw_name);
 534         } else if (dev_priv->me_fw->size % 8) {
 535                 printk(KERN_ERR
 536                        "radeon_cp: Bogus length %zu in firmware \"%s\"\n",
 537                        dev_priv->me_fw->size, fw_name);
 538                 err = -EINVAL;
 539                 release_firmware(dev_priv->me_fw);
 540                 dev_priv->me_fw = NULL;
 541         }
 542         return err;
 543 }
 544
 545 static void radeon_cp_load_microcode(drm_radeon_private_t *dev_priv)
 546 {
 547         const __be32 *fw_data;
 548         int i, size;
 549
 550         radeon_do_wait_for_idle(dev_priv);
 551
 552         if (dev_priv->me_fw) {
 553                 size = dev_priv->me_fw->size / 4;
 554                 fw_data = (const __be32 *)&dev_priv->me_fw->data[0];
 555                 RADEON_WRITE(RADEON_CP_ME_RAM_ADDR, 0);
 556                 for (i = 0; i < size; i += 2) {
 557                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
 558                                      be32_to_cpup(&fw_data[i]));
 559                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
 560                                      be32_to_cpup(&fw_data[i + 1]));
 561                 }
 562         }
 563 }
 564
 565 /* Flush any pending commands to the CP.  This should only be used just
 566  * prior to a wait for idle, as it informs the engine that the command
 567  * stream is ending.
 568  */
 569 static void radeon_do_cp_flush(drm_radeon_private_t * dev_priv)
 570 {
 571         DRM_DEBUG("\n");
 572 #if 0
 573         u32 tmp;
 574
 575         tmp = RADEON_READ(RADEON_CP_RB_WPTR) | (1 << 31);
 576         RADEON_WRITE(RADEON_CP_RB_WPTR, tmp);
 577 #endif
 578 }
 579
 580 /* Wait for the CP to go idle.
 581  */
 582 int radeon_do_cp_idle(drm_radeon_private_t * dev_priv)
 583 {
 584         RING_LOCALS;
 585         DRM_DEBUG("\n");
 586
 587         BEGIN_RING(6);
 588
 589         RADEON_PURGE_CACHE();
 590         RADEON_PURGE_ZCACHE();
 591         RADEON_WAIT_UNTIL_IDLE();
 592
 593         ADVANCE_RING();
 594         COMMIT_RING();
 595
 596         return radeon_do_wait_for_idle(dev_priv);
 597 }
 598
 599 /* Start the Command Processor.
 600  */
 601 static void radeon_do_cp_start(drm_radeon_private_t * dev_priv)
 602 {
 603         RING_LOCALS;
 604         DRM_DEBUG("\n");
 605
 606         radeon_do_wait_for_idle(dev_priv);
 607
 608         RADEON_WRITE(RADEON_CP_CSQ_CNTL, dev_priv->cp_mode);
 609
 610         dev_priv->cp_running = 1;
 611
 612         /* on r420, any DMA from CP to system memory while 2D is active
 613          * can cause a hang.  workaround is to queue a CP RESYNC token
 614          */
 615         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) {
 616                 BEGIN_RING(3);
 617                 OUT_RING(CP_PACKET0(R300_CP_RESYNC_ADDR, 1));
 618                 OUT_RING(5); /* scratch reg 5 */
 619                 OUT_RING(0xdeadbeef);
 620                 ADVANCE_RING();
 621                 COMMIT_RING();
 622         }
 623
 624         BEGIN_RING(8);
 625         /* isync can only be written through cp on r5xx write it here */
 626         OUT_RING(CP_PACKET0(RADEON_ISYNC_CNTL, 0));
 627         OUT_RING(RADEON_ISYNC_ANY2D_IDLE3D |
 628                  RADEON_ISYNC_ANY3D_IDLE2D |
 629                  RADEON_ISYNC_WAIT_IDLEGUI |
 630                  RADEON_ISYNC_CPSCRATCH_IDLEGUI);
 631         RADEON_PURGE_CACHE();
 632         RADEON_PURGE_ZCACHE();
 633         RADEON_WAIT_UNTIL_IDLE();
 634         ADVANCE_RING();
 635         COMMIT_RING();
 636
 637         dev_priv->track_flush |= RADEON_FLUSH_EMITED | RADEON_PURGE_EMITED;
 638 }
 639
 640 /* Reset the Command Processor.  This will not flush any pending
 641  * commands, so you must wait for the CP command stream to complete
 642  * before calling this routine.
 643  */
 644 static void radeon_do_cp_reset(drm_radeon_private_t * dev_priv)
 645 {
 646         u32 cur_read_ptr;
 647         DRM_DEBUG("\n");
 648
 649         cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
 650         RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
 651         SET_RING_HEAD(dev_priv, cur_read_ptr);
 652         dev_priv->ring.tail = cur_read_ptr;
 653 }
 654
 655 /* Stop the Command Processor.  This will not flush any pending
 656  * commands, so you must flush the command stream and wait for the CP
 657  * to go idle before calling this routine.
 658  */
 659 static void radeon_do_cp_stop(drm_radeon_private_t * dev_priv)
 660 {
 661         RING_LOCALS;
 662         DRM_DEBUG("\n");
 663
 664         /* finish the pending CP_RESYNC token */
 665         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) {
 666                 BEGIN_RING(2);
 667                 OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
 668                 OUT_RING(R300_RB3D_DC_FINISH);
 669                 ADVANCE_RING();
 670                 COMMIT_RING();
 671                 radeon_do_wait_for_idle(dev_priv);
 672         }
 673
 674         RADEON_WRITE(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS);
 675
 676         dev_priv->cp_running = 0;
 677 }
 678
 679 /* Reset the engine.  This will stop the CP if it is running.
 680  */
 681 static int radeon_do_engine_reset(struct drm_device * dev)
 682 {
 683         drm_radeon_private_t *dev_priv = dev->dev_private;
 684         u32 clock_cntl_index = 0, mclk_cntl = 0, rbbm_soft_reset;
 685         DRM_DEBUG("\n");
 686
 687         radeon_do_pixcache_flush(dev_priv);
 688
 689         if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) {
 690                 /* may need something similar for newer chips */
 691                 clock_cntl_index = RADEON_READ(RADEON_CLOCK_CNTL_INDEX);
 692                 mclk_cntl = RADEON_READ_PLL(dev, RADEON_MCLK_CNTL);
 693
 694                 RADEON_WRITE_PLL(RADEON_MCLK_CNTL, (mclk_cntl |
 695                                                     RADEON_FORCEON_MCLKA |
 696                                                     RADEON_FORCEON_MCLKB |
 697                                                     RADEON_FORCEON_YCLKA |
 698                                                     RADEON_FORCEON_YCLKB |
 699                                                     RADEON_FORCEON_MC |
 700                                                     RADEON_FORCEON_AIC));
 701         }
 702
 703         rbbm_soft_reset = RADEON_READ(RADEON_RBBM_SOFT_RESET);
 704
 705         RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset |
 706                                               RADEON_SOFT_RESET_CP |
 707                                               RADEON_SOFT_RESET_HI |
 708                                               RADEON_SOFT_RESET_SE |
 709                                               RADEON_SOFT_RESET_RE |
 710                                               RADEON_SOFT_RESET_PP |
 711                                               RADEON_SOFT_RESET_E2 |
 712                                               RADEON_SOFT_RESET_RB));
 713         RADEON_READ(RADEON_RBBM_SOFT_RESET);
 714         RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset &
 715                                               ~(RADEON_SOFT_RESET_CP |
 716                                                 RADEON_SOFT_RESET_HI |
 717                                                 RADEON_SOFT_RESET_SE |
 718                                                 RADEON_SOFT_RESET_RE |
 719                                                 RADEON_SOFT_RESET_PP |
 720                                                 RADEON_SOFT_RESET_E2 |
 721                                                 RADEON_SOFT_RESET_RB)));
 722         RADEON_READ(RADEON_RBBM_SOFT_RESET);
 723
 724         if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) {
 725                 RADEON_WRITE_PLL(RADEON_MCLK_CNTL, mclk_cntl);
 726                 RADEON_WRITE(RADEON_CLOCK_CNTL_INDEX, clock_cntl_index);
 727                 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, rbbm_soft_reset);
 728         }
 729
 730         /* setup the raster pipes */
 731         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R300)
 732             radeon_init_pipes(dev);
 733
 734         /* Reset the CP ring */
 735         radeon_do_cp_reset(dev_priv);
 736
 737         /* The CP is no longer running after an engine reset */
 738         dev_priv->cp_running = 0;
 739
 740         /* Reset any pending vertex, indirect buffers */
 741         radeon_freelist_reset(dev);
 742
 743         return 0;
 744 }
 745
 746 static void radeon_cp_init_ring_buffer(struct drm_device * dev,
 747                                        drm_radeon_private_t *dev_priv,
 748                                        struct drm_file *file_priv)
 749 {
 750         struct drm_radeon_master_private *master_priv;
 751         u32 ring_start, cur_read_ptr;
 752
 753         /* Initialize the memory controller. With new memory map, the fb location
 754          * is not changed, it should have been properly initialized already. Part
 755          * of the problem is that the code below is bogus, assuming the GART is
 756          * always appended to the fb which is not necessarily the case
 757          */
 758         if (!dev_priv->new_memmap)
 759                 radeon_write_fb_location(dev_priv,
 760                              ((dev_priv->gart_vm_start - 1) & 0xffff0000)
 761                              | (dev_priv->fb_location >> 16));
 762
 763 #if __OS_HAS_AGP
 764         if (dev_priv->flags & RADEON_IS_AGP) {
 765                 radeon_write_agp_base(dev_priv, dev->agp->base);
 766
 767                 radeon_write_agp_location(dev_priv,
 768                              (((dev_priv->gart_vm_start - 1 +
 769                                 dev_priv->gart_size) & 0xffff0000) |
 770                               (dev_priv->gart_vm_start >> 16)));
 771
 772                 ring_start = (dev_priv->cp_ring->offset
 773                               - dev->agp->base
 774                               + dev_priv->gart_vm_start);
 775         } else
 776 #endif
 777                 ring_start = (dev_priv->cp_ring->offset
 778                               - (unsigned long)dev->sg->virtual
 779                               + dev_priv->gart_vm_start);
 780
 781         RADEON_WRITE(RADEON_CP_RB_BASE, ring_start);
 782
 783         /* Set the write pointer delay */
 784         RADEON_WRITE(RADEON_CP_RB_WPTR_DELAY, 0);
 785
 786         /* Initialize the ring buffer's read and write pointers */
 787         cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
 788         RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
 789         SET_RING_HEAD(dev_priv, cur_read_ptr);
 790         dev_priv->ring.tail = cur_read_ptr;
 791
 792 #if __OS_HAS_AGP
 793         if (dev_priv->flags & RADEON_IS_AGP) {
 794                 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR,
 795                              dev_priv->ring_rptr->offset
 796                              - dev->agp->base + dev_priv->gart_vm_start);
 797         } else
 798 #endif
 799         {
 800                 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR,
 801                              dev_priv->ring_rptr->offset
 802                              - ((unsigned long) dev->sg->virtual)
 803                              + dev_priv->gart_vm_start);
 804         }
 805
 806         /* Set ring buffer size */
 807 #ifdef __BIG_ENDIAN
 808         RADEON_WRITE(RADEON_CP_RB_CNTL,
 809                      RADEON_BUF_SWAP_32BIT |
 810                      (dev_priv->ring.fetch_size_l2ow << 18) |
 811                      (dev_priv->ring.rptr_update_l2qw << 8) |
 812                      dev_priv->ring.size_l2qw);
 813 #else
 814         RADEON_WRITE(RADEON_CP_RB_CNTL,
 815                      (dev_priv->ring.fetch_size_l2ow << 18) |
 816                      (dev_priv->ring.rptr_update_l2qw << 8) |
 817                      dev_priv->ring.size_l2qw);
 818 #endif
 819
 820
 821         /* Initialize the scratch register pointer.  This will cause
 822          * the scratch register values to be written out to memory
 823          * whenever they are updated.
 824          *
 825          * We simply put this behind the ring read pointer, this works
 826          * with PCI GART as well as (whatever kind of) AGP GART
 827          */
 828         RADEON_WRITE(RADEON_SCRATCH_ADDR, RADEON_READ(RADEON_CP_RB_RPTR_ADDR)
 829                      + RADEON_SCRATCH_REG_OFFSET);
 830
 831         RADEON_WRITE(RADEON_SCRATCH_UMSK, 0x7);
 832
 833         radeon_enable_bm(dev_priv);
 834
 835         radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(0), 0);
 836         RADEON_WRITE(RADEON_LAST_FRAME_REG, 0);
 837
 838         radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(1), 0);
 839         RADEON_WRITE(RADEON_LAST_DISPATCH_REG, 0);
 840
 841         radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(2), 0);
 842         RADEON_WRITE(RADEON_LAST_CLEAR_REG, 0);
 843
 844         /* reset sarea copies of these */
 845         master_priv = file_priv->master->driver_priv;
 846         if (master_priv->sarea_priv) {
 847                 master_priv->sarea_priv->last_frame = 0;
 848                 master_priv->sarea_priv->last_dispatch = 0;
 849                 master_priv->sarea_priv->last_clear = 0;
 850         }
 851
 852         radeon_do_wait_for_idle(dev_priv);
 853
 854         /* Sync everything up */
 855         RADEON_WRITE(RADEON_ISYNC_CNTL,
 856                      (RADEON_ISYNC_ANY2D_IDLE3D |
 857                       RADEON_ISYNC_ANY3D_IDLE2D |
 858                       RADEON_ISYNC_WAIT_IDLEGUI |
 859                       RADEON_ISYNC_CPSCRATCH_IDLEGUI));
 860
 861 }
 862
 863 static void radeon_test_writeback(drm_radeon_private_t * dev_priv)
 864 {
 865         u32 tmp;
 866
 867         /* Start with assuming that writeback doesn't work */
 868         dev_priv->writeback_works = 0;
 869
 870         /* Writeback doesn't seem to work everywhere, test it here and possibly
 871          * enable it if it appears to work
 872          */
 873         radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(1), 0);
 874
 875         RADEON_WRITE(RADEON_SCRATCH_REG1, 0xdeadbeef);
 876
 877         for (tmp = 0; tmp < dev_priv->usec_timeout; tmp++) {
 878                 u32 val;
 879
 880                 val = radeon_read_ring_rptr(dev_priv, RADEON_SCRATCHOFF(1));
 881                 if (val == 0xdeadbeef)
 882                         break;
 883                 DRM_UDELAY(1);
 884         }
 885
 886         if (tmp < dev_priv->usec_timeout) {
 887                 dev_priv->writeback_works = 1;
 888                 DRM_INFO("writeback test succeeded in %d usecs\n", tmp);
 889         } else {
 890                 dev_priv->writeback_works = 0;
 891                 DRM_INFO("writeback test failed\n");
 892         }
 893         if (radeon_no_wb == 1) {
 894                 dev_priv->writeback_works = 0;
 895                 DRM_INFO("writeback forced off\n");
 896         }
 897
 898         if (!dev_priv->writeback_works) {
 899                 /* Disable writeback to avoid unnecessary bus master transfer */
 900                 RADEON_WRITE(RADEON_CP_RB_CNTL, RADEON_READ(RADEON_CP_RB_CNTL) |
 901                              RADEON_RB_NO_UPDATE);
 902                 RADEON_WRITE(RADEON_SCRATCH_UMSK, 0);
 903         }
 904 }
 905
 906 /* Enable or disable IGP GART on the chip */
 907 static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on)
 908 {
 909         u32 temp;
 910
 911         if (on) {
 912                 DRM_DEBUG("programming igp gart %08X %08lX %08X\n",
 913                           dev_priv->gart_vm_start,
 914                           (long)dev_priv->gart_info.bus_addr,
 915                           dev_priv->gart_size);
 916
 917                 temp = IGP_READ_MCIND(dev_priv, RS480_MC_MISC_CNTL);
 918                 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
 919                     ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
 920                         IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, (RS480_GART_INDEX_REG_EN |
 921                                                              RS690_BLOCK_GFX_D3_EN));
 922                 else
 923                         IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, RS480_GART_INDEX_REG_EN);
 924
 925                 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN |
 926                                                                RS480_VA_SIZE_32MB));
 927
 928                 temp = IGP_READ_MCIND(dev_priv, RS480_GART_FEATURE_ID);
 929                 IGP_WRITE_MCIND(RS480_GART_FEATURE_ID, (RS480_HANG_EN |
 930                                                         RS480_TLB_ENABLE |
 931                                                         RS480_GTW_LAC_EN |
 932                                                         RS480_1LEVEL_GART));
 933
 934                 temp = dev_priv->gart_info.bus_addr & 0xfffff000;
 935                 temp |= (upper_32_bits(dev_priv->gart_info.bus_addr) & 0xff) << 4;
 936                 IGP_WRITE_MCIND(RS480_GART_BASE, temp);
 937
 938                 temp = IGP_READ_MCIND(dev_priv, RS480_AGP_MODE_CNTL);
 939                 IGP_WRITE_MCIND(RS480_AGP_MODE_CNTL, ((1 << RS480_REQ_TYPE_SNOOP_SHIFT) |
 940                                                       RS480_REQ_TYPE_SNOOP_DIS));
 941
 942                 radeon_write_agp_base(dev_priv, dev_priv->gart_vm_start);
 943
 944                 dev_priv->gart_size = 32*1024*1024;
 945                 temp = (((dev_priv->gart_vm_start - 1 + dev_priv->gart_size) &
 946                          0xffff0000) | (dev_priv->gart_vm_start >> 16));
 947
 948                 radeon_write_agp_location(dev_priv, temp);
 949
 950                 temp = IGP_READ_MCIND(dev_priv, RS480_AGP_ADDRESS_SPACE_SIZE);
 951                 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN |
 952                                                                RS480_VA_SIZE_32MB));
 953
 954                 do {
 955                         temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL);
 956                         if ((temp & RS480_GART_CACHE_INVALIDATE) == 0)
 957                                 break;
 958                         DRM_UDELAY(1);
 959                 } while (1);
 960
 961                 IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL,
 962                                 RS480_GART_CACHE_INVALIDATE);
 963
 964                 do {
 965                         temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL);
 966                         if ((temp & RS480_GART_CACHE_INVALIDATE) == 0)
 967                                 break;
 968                         DRM_UDELAY(1);
 969                 } while (1);
 970
 971                 IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL, 0);
 972         } else {
 973                 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, 0);
 974         }
 975 }
 976
 977 /* Enable or disable IGP GART on the chip */
 978 static void rs600_set_igpgart(drm_radeon_private_t *dev_priv, int on)
 979 {
 980         u32 temp;
 981         int i;
 982
 983         if (on) {
 984                 DRM_DEBUG("programming igp gart %08X %08lX %08X\n",
 985                          dev_priv->gart_vm_start,
 986                          (long)dev_priv->gart_info.bus_addr,
 987                          dev_priv->gart_size);
 988
 989                 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, (RS600_EFFECTIVE_L2_CACHE_SIZE(6) |
 990                                                     RS600_EFFECTIVE_L2_QUEUE_SIZE(6)));
 991
 992                 for (i = 0; i < 19; i++)
 993                         IGP_WRITE_MCIND(RS600_MC_PT0_CLIENT0_CNTL + i,
 994                                         (RS600_ENABLE_TRANSLATION_MODE_OVERRIDE |
 995                                          RS600_SYSTEM_ACCESS_MODE_IN_SYS |
 996                                          RS600_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASSTHROUGH |
 997                                          RS600_EFFECTIVE_L1_CACHE_SIZE(3) |
 998                                          RS600_ENABLE_FRAGMENT_PROCESSING |
 999                                          RS600_EFFECTIVE_L1_QUEUE_SIZE(3)));
1000
1001                 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_CNTL, (RS600_ENABLE_PAGE_TABLE |
1002                                                              RS600_PAGE_TABLE_TYPE_FLAT));
1003
1004                 /* disable all other contexts */
1005                 for (i = 1; i < 8; i++)
1006                         IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_CNTL + i, 0);
1007
1008                 /* setup the page table aperture */
1009                 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_FLAT_BASE_ADDR,
1010                                 dev_priv->gart_info.bus_addr);
1011                 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_FLAT_START_ADDR,
1012                                 dev_priv->gart_vm_start);
1013                 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_FLAT_END_ADDR,
1014                                 (dev_priv->gart_vm_start + dev_priv->gart_size - 1));
1015                 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR, 0);
1016
1017                 /* setup the system aperture */
1018                 IGP_WRITE_MCIND(RS600_MC_PT0_SYSTEM_APERTURE_LOW_ADDR,
1019                                 dev_priv->gart_vm_start);
1020                 IGP_WRITE_MCIND(RS600_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR,
1021                                 (dev_priv->gart_vm_start + dev_priv->gart_size - 1));
1022
1023                 /* enable page tables */
1024                 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
1025                 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, (temp | RS600_ENABLE_PT));
1026
1027                 temp = IGP_READ_MCIND(dev_priv, RS600_MC_CNTL1);
1028                 IGP_WRITE_MCIND(RS600_MC_CNTL1, (temp | RS600_ENABLE_PAGE_TABLES));
1029
1030                 /* invalidate the cache */
1031                 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
1032
1033                 temp &= ~(RS600_INVALIDATE_ALL_L1_TLBS | RS600_INVALIDATE_L2_CACHE);
1034                 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, temp);
1035                 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
1036
1037                 temp |= RS600_INVALIDATE_ALL_L1_TLBS | RS600_INVALIDATE_L2_CACHE;
1038                 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, temp);
1039                 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
1040
1041                 temp &= ~(RS600_INVALIDATE_ALL_L1_TLBS | RS600_INVALIDATE_L2_CACHE);
1042                 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, temp);
1043                 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
1044
1045         } else {
1046                 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, 0);
1047                 temp = IGP_READ_MCIND(dev_priv, RS600_MC_CNTL1);
1048                 temp &= ~RS600_ENABLE_PAGE_TABLES;
1049                 IGP_WRITE_MCIND(RS600_MC_CNTL1, temp);
1050         }
1051 }
1052
1053 static void radeon_set_pciegart(drm_radeon_private_t * dev_priv, int on)
1054 {
1055         u32 tmp = RADEON_READ_PCIE(dev_priv, RADEON_PCIE_TX_GART_CNTL);
1056         if (on) {
1057
1058                 DRM_DEBUG("programming pcie %08X %08lX %08X\n",
1059                           dev_priv->gart_vm_start,
1060                           (long)dev_priv->gart_info.bus_addr,
1061                           dev_priv->gart_size);
1062                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO,
1063                                   dev_priv->gart_vm_start);
1064                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_BASE,
1065                                   dev_priv->gart_info.bus_addr);
1066                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_START_LO,
1067                                   dev_priv->gart_vm_start);
1068                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_END_LO,
1069                                   dev_priv->gart_vm_start +
1070                                   dev_priv->gart_size - 1);
1071
1072                 radeon_write_agp_location(dev_priv, 0xffffffc0); /* ?? */
1073
1074                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
1075                                   RADEON_PCIE_TX_GART_EN);
1076         } else {
1077                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
1078                                   tmp & ~RADEON_PCIE_TX_GART_EN);
1079         }
1080 }
1081
1082 /* Enable or disable PCI GART on the chip */
1083 static void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on)
1084 {
1085         u32 tmp;
1086
1087         if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
1088             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740) ||
1089             (dev_priv->flags & RADEON_IS_IGPGART)) {
1090                 radeon_set_igpgart(dev_priv, on);
1091                 return;
1092         }
1093
1094         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) {
1095                 rs600_set_igpgart(dev_priv, on);
1096                 return;
1097         }
1098
1099         if (dev_priv->flags & RADEON_IS_PCIE) {
1100                 radeon_set_pciegart(dev_priv, on);
1101                 return;
1102         }
1103
1104         tmp = RADEON_READ(RADEON_AIC_CNTL);
1105
1106         if (on) {
1107                 RADEON_WRITE(RADEON_AIC_CNTL,
1108                              tmp | RADEON_PCIGART_TRANSLATE_EN);
1109
1110                 /* set PCI GART page-table base address
1111                  */
1112                 RADEON_WRITE(RADEON_AIC_PT_BASE, dev_priv->gart_info.bus_addr);
1113
1114                 /* set address range for PCI address translate
1115                  */
1116                 RADEON_WRITE(RADEON_AIC_LO_ADDR, dev_priv->gart_vm_start);
1117                 RADEON_WRITE(RADEON_AIC_HI_ADDR, dev_priv->gart_vm_start
1118                              + dev_priv->gart_size - 1);
1119
1120                 /* Turn off AGP aperture -- is this required for PCI GART?
1121                  */
1122                 radeon_write_agp_location(dev_priv, 0xffffffc0);
1123                 RADEON_WRITE(RADEON_AGP_COMMAND, 0);    /* clear AGP_COMMAND */
1124         } else {
1125                 RADEON_WRITE(RADEON_AIC_CNTL,
1126                              tmp & ~RADEON_PCIGART_TRANSLATE_EN);
1127         }
1128 }
1129
1130 static int radeon_setup_pcigart_surface(drm_radeon_private_t *dev_priv)
1131 {
1132         struct drm_ati_pcigart_info *gart_info = &dev_priv->gart_info;
1133         struct radeon_virt_surface *vp;
1134         int i;
1135
1136         for (i = 0; i < RADEON_MAX_SURFACES * 2; i++) {
1137                 if (!dev_priv->virt_surfaces[i].file_priv ||
1138                     dev_priv->virt_surfaces[i].file_priv == PCIGART_FILE_PRIV)
1139                         break;
1140         }
1141         if (i >= 2 * RADEON_MAX_SURFACES)
1142                 return -ENOMEM;
1143         vp = &dev_priv->virt_surfaces[i];
1144
1145         for (i = 0; i < RADEON_MAX_SURFACES; i++) {
1146                 struct radeon_surface *sp = &dev_priv->surfaces[i];
1147                 if (sp->refcount)
1148                         continue;
1149
1150                 vp->surface_index = i;
1151                 vp->lower = gart_info->bus_addr;
1152                 vp->upper = vp->lower + gart_info->table_size;
1153                 vp->flags = 0;
1154                 vp->file_priv = PCIGART_FILE_PRIV;
1155
1156                 sp->refcount = 1;
1157                 sp->lower = vp->lower;
1158                 sp->upper = vp->upper;
1159                 sp->flags = 0;
1160
1161                 RADEON_WRITE(RADEON_SURFACE0_INFO + 16 * i, sp->flags);
1162                 RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND + 16 * i, sp->lower);
1163                 RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND + 16 * i, sp->upper);
1164                 return 0;
1165         }
1166
1167         return -ENOMEM;
1168 }
1169
1170 static int radeon_do_init_cp(struct drm_device *dev, drm_radeon_init_t *init,
1171                              struct drm_file *file_priv)
1172 {
1173         drm_radeon_private_t *dev_priv = dev->dev_private;
1174         struct drm_radeon_master_private *master_priv = file_priv->master->driver_priv;
1175
1176         DRM_DEBUG("\n");
1177
1178         /* if we require new memory map but we don't have it fail */
1179         if ((dev_priv->flags & RADEON_NEW_MEMMAP) && !dev_priv->new_memmap) {
1180                 DRM_ERROR("Cannot initialise DRM on this card\nThis card requires a new X.org DDX for 3D\n");
1181                 radeon_do_cleanup_cp(dev);
1182                 return -EINVAL;
1183         }
1184
1185         if (init->is_pci && (dev_priv->flags & RADEON_IS_AGP)) {
1186                 DRM_DEBUG("Forcing AGP card to PCI mode\n");
1187                 dev_priv->flags &= ~RADEON_IS_AGP;
1188         } else if (!(dev_priv->flags & (RADEON_IS_AGP | RADEON_IS_PCI | RADEON_IS_PCIE))
1189                    && !init->is_pci) {
1190                 DRM_DEBUG("Restoring AGP flag\n");
1191                 dev_priv->flags |= RADEON_IS_AGP;
1192         }
1193
1194         if ((!(dev_priv->flags & RADEON_IS_AGP)) && !dev->sg) {
1195                 DRM_ERROR("PCI GART memory not allocated!\n");
1196                 radeon_do_cleanup_cp(dev);
1197                 return -EINVAL;
1198         }
1199
1200         dev_priv->usec_timeout = init->usec_timeout;
1201         if (dev_priv->usec_timeout < 1 ||
1202             dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT) {
1203                 DRM_DEBUG("TIMEOUT problem!\n");
1204                 radeon_do_cleanup_cp(dev);
1205                 return -EINVAL;
1206         }
1207
1208         /* Enable vblank on CRTC1 for older X servers
1209          */
1210         dev_priv->vblank_crtc = DRM_RADEON_VBLANK_CRTC1;
1211
1212         switch(init->func) {
1213         case RADEON_INIT_R200_CP:
1214                 dev_priv->microcode_version = UCODE_R200;
1215                 break;
1216         case RADEON_INIT_R300_CP:
1217                 dev_priv->microcode_version = UCODE_R300;
1218                 break;
1219         default:
1220                 dev_priv->microcode_version = UCODE_R100;
1221         }
1222
1223         dev_priv->do_boxes = 0;
1224         dev_priv->cp_mode = init->cp_mode;
1225
1226         /* We don't support anything other than bus-mastering ring mode,
1227          * but the ring can be in either AGP or PCI space for the ring
1228          * read pointer.
1229          */
1230         if ((init->cp_mode != RADEON_CSQ_PRIBM_INDDIS) &&
1231             (init->cp_mode != RADEON_CSQ_PRIBM_INDBM)) {
1232                 DRM_DEBUG("BAD cp_mode (%x)!\n", init->cp_mode);
1233                 radeon_do_cleanup_cp(dev);
1234                 return -EINVAL;
1235         }
1236
1237         switch (init->fb_bpp) {
1238         case 16:
1239                 dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565;
1240                 break;
1241         case 32:
1242         default:
1243                 dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888;
1244                 break;
1245         }
1246         dev_priv->front_offset = init->front_offset;
1247         dev_priv->front_pitch = init->front_pitch;
1248         dev_priv->back_offset = init->back_offset;
1249         dev_priv->back_pitch = init->back_pitch;
1250
1251         switch (init->depth_bpp) {
1252         case 16:
1253                 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z;
1254                 break;
1255         case 32:
1256         default:
1257                 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;
1258                 break;
1259         }
1260         dev_priv->depth_offset = init->depth_offset;
1261         dev_priv->depth_pitch = init->depth_pitch;
1262
1263         /* Hardware state for depth clears.  Remove this if/when we no
1264          * longer clear the depth buffer with a 3D rectangle.  Hard-code
1265          * all values to prevent unwanted 3D state from slipping through
1266          * and screwing with the clear operation.
1267          */
1268         dev_priv->depth_clear.rb3d_cntl = (RADEON_PLANE_MASK_ENABLE |
1269                                            (dev_priv->color_fmt << 10) |
1270                                            (dev_priv->microcode_version ==
1271                                             UCODE_R100 ? RADEON_ZBLOCK16 : 0));
1272
1273         dev_priv->depth_clear.rb3d_zstencilcntl =
1274             (dev_priv->depth_fmt |
1275              RADEON_Z_TEST_ALWAYS |
1276              RADEON_STENCIL_TEST_ALWAYS |
1277              RADEON_STENCIL_S_FAIL_REPLACE |
1278              RADEON_STENCIL_ZPASS_REPLACE |
1279              RADEON_STENCIL_ZFAIL_REPLACE | RADEON_Z_WRITE_ENABLE);
1280
1281         dev_priv->depth_clear.se_cntl = (RADEON_FFACE_CULL_CW |
1282                                          RADEON_BFACE_SOLID |
1283                                          RADEON_FFACE_SOLID |
1284                                          RADEON_FLAT_SHADE_VTX_LAST |
1285                                          RADEON_DIFFUSE_SHADE_FLAT |
1286                                          RADEON_ALPHA_SHADE_FLAT |
1287                                          RADEON_SPECULAR_SHADE_FLAT |
1288                                          RADEON_FOG_SHADE_FLAT |
1289                                          RADEON_VTX_PIX_CENTER_OGL |
1290                                          RADEON_ROUND_MODE_TRUNC |
1291                                          RADEON_ROUND_PREC_8TH_PIX);
1292
1293
1294         dev_priv->ring_offset = init->ring_offset;
1295         dev_priv->ring_rptr_offset = init->ring_rptr_offset;
1296         dev_priv->buffers_offset = init->buffers_offset;
1297         dev_priv->gart_textures_offset = init->gart_textures_offset;
1298
1299         master_priv->sarea = drm_getsarea(dev);
1300         if (!master_priv->sarea) {
1301                 DRM_ERROR("could not find sarea!\n");
1302                 radeon_do_cleanup_cp(dev);
1303                 return -EINVAL;
1304         }
1305
1306         dev_priv->cp_ring = drm_core_findmap(dev, init->ring_offset);
1307         if (!dev_priv->cp_ring) {
1308                 DRM_ERROR("could not find cp ring region!\n");
1309                 radeon_do_cleanup_cp(dev);
1310                 return -EINVAL;
1311         }
1312         dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset);
1313         if (!dev_priv->ring_rptr) {
1314                 DRM_ERROR("could not find ring read pointer!\n");
1315                 radeon_do_cleanup_cp(dev);
1316                 return -EINVAL;
1317         }
1318         dev->agp_buffer_token = init->buffers_offset;
1319         dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset);
1320         if (!dev->agp_buffer_map) {
1321                 DRM_ERROR("could not find dma buffer region!\n");
1322                 radeon_do_cleanup_cp(dev);
1323                 return -EINVAL;
1324         }
1325
1326         if (init->gart_textures_offset) {
1327                 dev_priv->gart_textures =
1328                     drm_core_findmap(dev, init->gart_textures_offset);
1329                 if (!dev_priv->gart_textures) {
1330                         DRM_ERROR("could not find GART texture region!\n");
1331                         radeon_do_cleanup_cp(dev);
1332                         return -EINVAL;
1333                 }
1334         }
1335
1336 #if __OS_HAS_AGP
1337         if (dev_priv->flags & RADEON_IS_AGP) {
1338                 drm_core_ioremap_wc(dev_priv->cp_ring, dev);
1339                 drm_core_ioremap_wc(dev_priv->ring_rptr, dev);
1340                 drm_core_ioremap_wc(dev->agp_buffer_map, dev);
1341                 if (!dev_priv->cp_ring->handle ||
1342                     !dev_priv->ring_rptr->handle ||
1343                     !dev->agp_buffer_map->handle) {
1344                         DRM_ERROR("could not find ioremap agp regions!\n");
1345                         radeon_do_cleanup_cp(dev);
1346                         return -EINVAL;
1347                 }
1348         } else
1349 #endif
1350         {
1351                 dev_priv->cp_ring->handle =
1352                         (void *)(unsigned long)dev_priv->cp_ring->offset;
1353                 dev_priv->ring_rptr->handle =
1354                         (void *)(unsigned long)dev_priv->ring_rptr->offset;
1355                 dev->agp_buffer_map->handle =
1356                         (void *)(unsigned long)dev->agp_buffer_map->offset;
1357
1358                 DRM_DEBUG("dev_priv->cp_ring->handle %p\n",
1359                           dev_priv->cp_ring->handle);
1360                 DRM_DEBUG("dev_priv->ring_rptr->handle %p\n",
1361                           dev_priv->ring_rptr->handle);
1362                 DRM_DEBUG("dev->agp_buffer_map->handle %p\n",
1363                           dev->agp_buffer_map->handle);
1364         }
1365
1366         dev_priv->fb_location = (radeon_read_fb_location(dev_priv) & 0xffff) << 16;
1367         dev_priv->fb_size =
1368                 ((radeon_read_fb_location(dev_priv) & 0xffff0000u) + 0x10000)
1369                 - dev_priv->fb_location;
1370
1371         dev_priv->front_pitch_offset = (((dev_priv->front_pitch / 64) << 22) |
1372                                         ((dev_priv->front_offset
1373                                           + dev_priv->fb_location) >> 10));
1374
1375         dev_priv->back_pitch_offset = (((dev_priv->back_pitch / 64) << 22) |
1376                                        ((dev_priv->back_offset
1377                                          + dev_priv->fb_location) >> 10));
1378
1379         dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch / 64) << 22) |
1380                                         ((dev_priv->depth_offset
1381                                           + dev_priv->fb_location) >> 10));
1382
1383         dev_priv->gart_size = init->gart_size;
1384
1385         /* New let's set the memory map ... */
1386         if (dev_priv->new_memmap) {
1387                 u32 base = 0;
1388
1389                 DRM_INFO("Setting GART location based on new memory map\n");
1390
1391                 /* If using AGP, try to locate the AGP aperture at the same
1392                  * location in the card and on the bus, though we have to
1393                  * align it down.
1394                  */
1395 #if __OS_HAS_AGP
1396                 if (dev_priv->flags & RADEON_IS_AGP) {
1397                         base = dev->agp->base;
1398                         /* Check if valid */
1399                         if ((base + dev_priv->gart_size - 1) >= dev_priv->fb_location &&
1400                             base < (dev_priv->fb_location + dev_priv->fb_size - 1)) {
1401                                 DRM_INFO("Can't use AGP base @0x%08lx, won't fit\n",
1402                                          dev->agp->base);
1403                                 base = 0;
1404                         }
1405                 }
1406 #endif
1407                 /* If not or if AGP is at 0 (Macs), try to put it elsewhere */
1408                 if (base == 0) {
1409                         base = dev_priv->fb_location + dev_priv->fb_size;
1410                         if (base < dev_priv->fb_location ||
1411                             ((base + dev_priv->gart_size) & 0xfffffffful) < base)
1412                                 base = dev_priv->fb_location
1413                                         - dev_priv->gart_size;
1414                 }
1415                 dev_priv->gart_vm_start = base & 0xffc00000u;
1416                 if (dev_priv->gart_vm_start != base)
1417                         DRM_INFO("GART aligned down from 0x%08x to 0x%08x\n",
1418                                  base, dev_priv->gart_vm_start);
1419         } else {
1420                 DRM_INFO("Setting GART location based on old memory map\n");
1421                 dev_priv->gart_vm_start = dev_priv->fb_location +
1422                         RADEON_READ(RADEON_CONFIG_APER_SIZE);
1423         }
1424
1425 #if __OS_HAS_AGP
1426         if (dev_priv->flags & RADEON_IS_AGP)
1427                 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1428                                                  - dev->agp->base
1429                                                  + dev_priv->gart_vm_start);
1430         else
1431 #endif
1432                 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1433                                         - (unsigned long)dev->sg->virtual
1434                                         + dev_priv->gart_vm_start);
1435
1436         DRM_DEBUG("dev_priv->gart_size %d\n", dev_priv->gart_size);
1437         DRM_DEBUG("dev_priv->gart_vm_start 0x%x\n", dev_priv->gart_vm_start);
1438         DRM_DEBUG("dev_priv->gart_buffers_offset 0x%lx\n",
1439                   dev_priv->gart_buffers_offset);
1440
1441         dev_priv->ring.start = (u32 *) dev_priv->cp_ring->handle;
1442         dev_priv->ring.end = ((u32 *) dev_priv->cp_ring->handle
1443                               + init->ring_size / sizeof(u32));
1444         dev_priv->ring.size = init->ring_size;
1445         dev_priv->ring.size_l2qw = drm_order(init->ring_size / 8);
1446
1447         dev_priv->ring.rptr_update = /* init->rptr_update */ 4096;
1448         dev_priv->ring.rptr_update_l2qw = drm_order( /* init->rptr_update */ 4096 / 8);
1449
1450         dev_priv->ring.fetch_size = /* init->fetch_size */ 32;
1451         dev_priv->ring.fetch_size_l2ow = drm_order( /* init->fetch_size */ 32 / 16);
1452         dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1;
1453
1454         dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK;
1455
1456 #if __OS_HAS_AGP
1457         if (dev_priv->flags & RADEON_IS_AGP) {
1458                 /* Turn off PCI GART */
1459                 radeon_set_pcigart(dev_priv, 0);
1460         } else
1461 #endif
1462         {
1463                 u32 sctrl;
1464                 int ret;
1465
1466                 dev_priv->gart_info.table_mask = DMA_BIT_MASK(32);
1467                 /* if we have an offset set from userspace */
1468                 if (dev_priv->pcigart_offset_set) {
1469                         dev_priv->gart_info.bus_addr =
1470                                 (resource_size_t)dev_priv->pcigart_offset + dev_priv->fb_location;
1471                         dev_priv->gart_info.mapping.offset =
1472                             dev_priv->pcigart_offset + dev_priv->fb_aper_offset;
1473                         dev_priv->gart_info.mapping.size =
1474                             dev_priv->gart_info.table_size;
1475
1476                         drm_core_ioremap_wc(&dev_priv->gart_info.mapping, dev);
1477                         dev_priv->gart_info.addr =
1478                             dev_priv->gart_info.mapping.handle;
1479
1480                         if (dev_priv->flags & RADEON_IS_PCIE)
1481                                 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCIE;
1482                         else
1483                                 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
1484                         dev_priv->gart_info.gart_table_location =
1485                             DRM_ATI_GART_FB;
1486
1487                         DRM_DEBUG("Setting phys_pci_gart to %p %08lX\n",
1488                                   dev_priv->gart_info.addr,
1489                                   dev_priv->pcigart_offset);
1490                 } else {
1491                         if (dev_priv->flags & RADEON_IS_IGPGART)
1492                                 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_IGP;
1493                         else
1494                                 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
1495                         dev_priv->gart_info.gart_table_location =
1496                             DRM_ATI_GART_MAIN;
1497                         dev_priv->gart_info.addr = NULL;
1498                         dev_priv->gart_info.bus_addr = 0;
1499                         if (dev_priv->flags & RADEON_IS_PCIE) {
1500                                 DRM_ERROR
1501                                     ("Cannot use PCI Express without GART in FB memory\n");
1502                                 radeon_do_cleanup_cp(dev);
1503                                 return -EINVAL;
1504                         }
1505                 }
1506
1507                 sctrl = RADEON_READ(RADEON_SURFACE_CNTL);
1508                 RADEON_WRITE(RADEON_SURFACE_CNTL, 0);
1509                 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
1510                         ret = r600_page_table_init(dev);
1511                 else
1512                         ret = drm_ati_pcigart_init(dev, &dev_priv->gart_info);
1513                 RADEON_WRITE(RADEON_SURFACE_CNTL, sctrl);
1514
1515                 if (!ret) {
1516                         DRM_ERROR("failed to init PCI GART!\n");
1517                         radeon_do_cleanup_cp(dev);
1518                         return -ENOMEM;
1519                 }
1520
1521                 ret = radeon_setup_pcigart_surface(dev_priv);
1522                 if (ret) {
1523                         DRM_ERROR("failed to setup GART surface!\n");
1524                         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
1525                                 r600_page_table_cleanup(dev, &dev_priv->gart_info);
1526                         else
1527                                 drm_ati_pcigart_cleanup(dev, &dev_priv->gart_info);
1528                         radeon_do_cleanup_cp(dev);
1529                         return ret;
1530                 }
1531
1532                 /* Turn on PCI GART */
1533                 radeon_set_pcigart(dev_priv, 1);
1534         }
1535
1536         if (!dev_priv->me_fw) {
1537                 int err = radeon_cp_init_microcode(dev_priv);
1538                 if (err) {
1539                         DRM_ERROR("Failed to load firmware!\n");
1540                         radeon_do_cleanup_cp(dev);
1541                         return err;
1542                 }
1543         }
1544         radeon_cp_load_microcode(dev_priv);
1545         radeon_cp_init_ring_buffer(dev, dev_priv, file_priv);
1546
1547         dev_priv->last_buf = 0;
1548
1549         radeon_do_engine_reset(dev);
1550         radeon_test_writeback(dev_priv);
1551
1552         return 0;
1553 }
1554
1555 static int radeon_do_cleanup_cp(struct drm_device * dev)
1556 {
1557         drm_radeon_private_t *dev_priv = dev->dev_private;
1558         DRM_DEBUG("\n");
1559
1560         /* Make sure interrupts are disabled here because the uninstall ioctl
1561          * may not have been called from userspace and after dev_private
1562          * is freed, it's too late.
1563          */
1564         if (dev->irq_enabled)
1565                 drm_irq_uninstall(dev);
1566
1567 #if __OS_HAS_AGP
1568         if (dev_priv->flags & RADEON_IS_AGP) {
1569                 if (dev_priv->cp_ring != NULL) {
1570                         drm_core_ioremapfree(dev_priv->cp_ring, dev);
1571                         dev_priv->cp_ring = NULL;
1572                 }
1573                 if (dev_priv->ring_rptr != NULL) {
1574                         drm_core_ioremapfree(dev_priv->ring_rptr, dev);
1575                         dev_priv->ring_rptr = NULL;
1576                 }
1577                 if (dev->agp_buffer_map != NULL) {
1578                         drm_core_ioremapfree(dev->agp_buffer_map, dev);
1579                         dev->agp_buffer_map = NULL;
1580                 }
1581         } else
1582 #endif
1583         {
1584
1585                 if (dev_priv->gart_info.bus_addr) {
1586                         /* Turn off PCI GART */
1587                         radeon_set_pcigart(dev_priv, 0);
1588                         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
1589                                 r600_page_table_cleanup(dev, &dev_priv->gart_info);
1590                         else {
1591                                 if (!drm_ati_pcigart_cleanup(dev, &dev_priv->gart_info))
1592                                         DRM_ERROR("failed to cleanup PCI GART!\n");
1593                         }
1594                 }
1595
1596                 if (dev_priv->gart_info.gart_table_location == DRM_ATI_GART_FB)
1597                 {
1598                         drm_core_ioremapfree(&dev_priv->gart_info.mapping, dev);
1599                         dev_priv->gart_info.addr = NULL;
1600                 }
1601         }
1602         /* only clear to the start of flags */
1603         memset(dev_priv, 0, offsetof(drm_radeon_private_t, flags));
1604
1605         return 0;
1606 }
1607
1608 /* This code will reinit the Radeon CP hardware after a resume from disc.
1609  * AFAIK, it would be very difficult to pickle the state at suspend time, so
1610  * here we make sure that all Radeon hardware initialisation is re-done without
1611  * affecting running applications.
1612  *
1613  * Charl P. Botha <http://cpbotha.net>
1614  */
1615 static int radeon_do_resume_cp(struct drm_device *dev, struct drm_file *file_priv)
1616 {
1617         drm_radeon_private_t *dev_priv = dev->dev_private;
1618
1619         if (!dev_priv) {
1620                 DRM_ERROR("Called with no initialization\n");
1621                 return -EINVAL;
1622         }
1623
1624         DRM_DEBUG("Starting radeon_do_resume_cp()\n");
1625
1626 #if __OS_HAS_AGP
1627         if (dev_priv->flags & RADEON_IS_AGP) {
1628                 /* Turn off PCI GART */
1629                 radeon_set_pcigart(dev_priv, 0);
1630         } else
1631 #endif
1632         {
1633                 /* Turn on PCI GART */
1634                 radeon_set_pcigart(dev_priv, 1);
1635         }
1636
1637         radeon_cp_load_microcode(dev_priv);
1638         radeon_cp_init_ring_buffer(dev, dev_priv, file_priv);
1639
1640         dev_priv->have_z_offset = 0;
1641         radeon_do_engine_reset(dev);
1642         radeon_irq_set_state(dev, RADEON_SW_INT_ENABLE, 1);
1643
1644         DRM_DEBUG("radeon_do_resume_cp() complete\n");
1645
1646         return 0;
1647 }
1648
1649 int radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_priv)
1650 {
1651         drm_radeon_private_t *dev_priv = dev->dev_private;
1652         drm_radeon_init_t *init = data;
1653
1654         LOCK_TEST_WITH_RETURN(dev, file_priv);
1655
1656         if (init->func == RADEON_INIT_R300_CP)
1657                 r300_init_reg_flags(dev);
1658
1659         switch (init->func) {
1660         case RADEON_INIT_CP:
1661         case RADEON_INIT_R200_CP:
1662         case RADEON_INIT_R300_CP:
1663                 return radeon_do_init_cp(dev, init, file_priv);
1664         case RADEON_INIT_R600_CP:
1665                 return r600_do_init_cp(dev, init, file_priv);
1666         case RADEON_CLEANUP_CP:
1667                 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1668                         return r600_do_cleanup_cp(dev);
1669                 else
1670                         return radeon_do_cleanup_cp(dev);
1671         }
1672
1673         return -EINVAL;
1674 }
1675
1676 int radeon_cp_start(struct drm_device *dev, void *data, struct drm_file *file_priv)
1677 {
1678         drm_radeon_private_t *dev_priv = dev->dev_private;
1679         DRM_DEBUG("\n");
1680
1681         LOCK_TEST_WITH_RETURN(dev, file_priv);
1682
1683         if (dev_priv->cp_running) {
1684                 DRM_DEBUG("while CP running\n");
1685                 return 0;
1686         }
1687         if (dev_priv->cp_mode == RADEON_CSQ_PRIDIS_INDDIS) {
1688                 DRM_DEBUG("called with bogus CP mode (%d)\n",
1689                           dev_priv->cp_mode);
1690                 return 0;
1691         }
1692
1693         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1694                 r600_do_cp_start(dev_priv);
1695         else
1696                 radeon_do_cp_start(dev_priv);
1697
1698         return 0;
1699 }
1700
1701 /* Stop the CP.  The engine must have been idled before calling this
1702  * routine.
1703  */
1704 int radeon_cp_stop(struct drm_device *dev, void *data, struct drm_file *file_priv)
1705 {
1706         drm_radeon_private_t *dev_priv = dev->dev_private;
1707         drm_radeon_cp_stop_t *stop = data;
1708         int ret;
1709         DRM_DEBUG("\n");
1710
1711         LOCK_TEST_WITH_RETURN(dev, file_priv);
1712
1713         if (!dev_priv->cp_running)
1714                 return 0;
1715
1716         /* Flush any pending CP commands.  This ensures any outstanding
1717          * commands are exectuted by the engine before we turn it off.
1718          */
1719         if (stop->flush) {
1720                 radeon_do_cp_flush(dev_priv);
1721         }
1722
1723         /* If we fail to make the engine go idle, we return an error
1724          * code so that the DRM ioctl wrapper can try again.
1725          */
1726         if (stop->idle) {
1727                 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1728                         ret = r600_do_cp_idle(dev_priv);
1729                 else
1730                         ret = radeon_do_cp_idle(dev_priv);
1731                 if (ret)
1732                         return ret;
1733         }
1734
1735         /* Finally, we can turn off the CP.  If the engine isn't idle,
1736          * we will get some dropped triangles as they won't be fully
1737          * rendered before the CP is shut down.
1738          */
1739         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1740                 r600_do_cp_stop(dev_priv);
1741         else
1742                 radeon_do_cp_stop(dev_priv);
1743
1744         /* Reset the engine */
1745         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1746                 r600_do_engine_reset(dev);
1747         else
1748                 radeon_do_engine_reset(dev);
1749
1750         return 0;
1751 }
1752
1753 void radeon_do_release(struct drm_device * dev)
1754 {
1755         drm_radeon_private_t *dev_priv = dev->dev_private;
1756         int i, ret;
1757
1758         if (dev_priv) {
1759                 if (dev_priv->cp_running) {
1760                         /* Stop the cp */
1761                         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) {
1762                                 while ((ret = r600_do_cp_idle(dev_priv)) != 0) {
1763                                         DRM_DEBUG("radeon_do_cp_idle %d\n", ret);
1764 #ifdef __linux__
1765                                         schedule();
1766 #else
1767                                         tsleep(&ret, PZERO, "rdnrel", 1);
1768 #endif
1769                                 }
1770                         } else {
1771                                 while ((ret = radeon_do_cp_idle(dev_priv)) != 0) {
1772                                         DRM_DEBUG("radeon_do_cp_idle %d\n", ret);
1773 #ifdef __linux__
1774                                         schedule();
1775 #else
1776                                         tsleep(&ret, PZERO, "rdnrel", 1);
1777 #endif
1778                                 }
1779                         }
1780                         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) {
1781                                 r600_do_cp_stop(dev_priv);
1782                                 r600_do_engine_reset(dev);
1783                         } else {
1784                                 radeon_do_cp_stop(dev_priv);
1785                                 radeon_do_engine_reset(dev);
1786                         }
1787                 }
1788
1789                 if ((dev_priv->flags & RADEON_FAMILY_MASK) < CHIP_R600) {
1790                         /* Disable *all* interrupts */
1791                         if (dev_priv->mmio)     /* remove this after permanent addmaps */
1792                                 RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
1793
1794                         if (dev_priv->mmio) {   /* remove all surfaces */
1795                                 for (i = 0; i < RADEON_MAX_SURFACES; i++) {
1796                                         RADEON_WRITE(RADEON_SURFACE0_INFO + 16 * i, 0);
1797                                         RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND +
1798                                                      16 * i, 0);
1799                                         RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND +
1800                                                      16 * i, 0);
1801                                 }
1802                         }
1803                 }
1804
1805                 /* Free memory heap structures */
1806                 radeon_mem_takedown(&(dev_priv->gart_heap));
1807                 radeon_mem_takedown(&(dev_priv->fb_heap));
1808
1809                 /* deallocate kernel resources */
1810                 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1811                         r600_do_cleanup_cp(dev);
1812                 else
1813                         radeon_do_cleanup_cp(dev);
1814                 release_firmware(dev_priv->me_fw);
1815                 dev_priv->me_fw = NULL;
1816                 release_firmware(dev_priv->pfp_fw);
1817                 dev_priv->pfp_fw = NULL;
1818         }
1819 }
1820
1821 /* Just reset the CP ring.  Called as part of an X Server engine reset.
1822  */
1823 int radeon_cp_reset(struct drm_device *dev, void *data, struct drm_file *file_priv)
1824 {
1825         drm_radeon_private_t *dev_priv = dev->dev_private;
1826         DRM_DEBUG("\n");
1827
1828         LOCK_TEST_WITH_RETURN(dev, file_priv);
1829
1830         if (!dev_priv) {
1831                 DRM_DEBUG("called before init done\n");
1832                 return -EINVAL;
1833         }
1834
1835         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1836                 r600_do_cp_reset(dev_priv);
1837         else
1838                 radeon_do_cp_reset(dev_priv);
1839
1840         /* The CP is no longer running after an engine reset */
1841         dev_priv->cp_running = 0;
1842
1843         return 0;
1844 }
1845
1846 int radeon_cp_idle(struct drm_device *dev, void *data, struct drm_file *file_priv)
1847 {
1848         drm_radeon_private_t *dev_priv = dev->dev_private;
1849         DRM_DEBUG("\n");
1850
1851         LOCK_TEST_WITH_RETURN(dev, file_priv);
1852
1853         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1854                 return r600_do_cp_idle(dev_priv);
1855         else
1856                 return radeon_do_cp_idle(dev_priv);
1857 }
1858
1859 /* Added by Charl P. Botha to call radeon_do_resume_cp().
1860  */
1861 int radeon_cp_resume(struct drm_device *dev, void *data, struct drm_file *file_priv)
1862 {
1863         drm_radeon_private_t *dev_priv = dev->dev_private;
1864         DRM_DEBUG("\n");
1865
1866         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1867                 return r600_do_resume_cp(dev, file_priv);
1868         else
1869                 return radeon_do_resume_cp(dev, file_priv);
1870 }
1871
1872 int radeon_engine_reset(struct drm_device *dev, void *data, struct drm_file *file_priv)
1873 {
1874         drm_radeon_private_t *dev_priv = dev->dev_private;
1875         DRM_DEBUG("\n");
1876
1877         LOCK_TEST_WITH_RETURN(dev, file_priv);
1878
1879         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1880                 return r600_do_engine_reset(dev);
1881         else
1882                 return radeon_do_engine_reset(dev);
1883 }
1884
1885 /* ================================================================
1886  * Fullscreen mode
1887  */
1888
1889 /* KW: Deprecated to say the least:
1890  */
1891 int radeon_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv)
1892 {
1893         return 0;
1894 }
1895
1896 /* ================================================================
1897  * Freelist management
1898  */
1899
1900 /* Original comment: FIXME: ROTATE_BUFS is a hack to cycle through
1901  *   bufs until freelist code is used.  Note this hides a problem with
1902  *   the scratch register * (used to keep track of last buffer
1903  *   completed) being written to before * the last buffer has actually
1904  *   completed rendering.
1905  *
1906  * KW:  It's also a good way to find free buffers quickly.
1907  *
1908  * KW: Ideally this loop wouldn't exist, and freelist_get wouldn't
1909  * sleep.  However, bugs in older versions of radeon_accel.c mean that
1910  * we essentially have to do this, else old clients will break.
1911  *
1912  * However, it does leave open a potential deadlock where all the
1913  * buffers are held by other clients, which can't release them because
1914  * they can't get the lock.
1915  */
1916
1917 struct drm_buf *radeon_freelist_get(struct drm_device * dev)
1918 {
1919         struct drm_device_dma *dma = dev->dma;
1920         drm_radeon_private_t *dev_priv = dev->dev_private;
1921         drm_radeon_buf_priv_t *buf_priv;
1922         struct drm_buf *buf;
1923         int i, t;
1924         int start;
1925
1926         if (++dev_priv->last_buf >= dma->buf_count)
1927                 dev_priv->last_buf = 0;
1928
1929         start = dev_priv->last_buf;
1930
1931         for (t = 0; t < dev_priv->usec_timeout; t++) {
1932                 u32 done_age = GET_SCRATCH(dev_priv, 1);
1933                 DRM_DEBUG("done_age = %d\n", done_age);
1934                 for (i = 0; i < dma->buf_count; i++) {
1935                         buf = dma->buflist[start];
1936                         buf_priv = buf->dev_private;
1937                         if (buf->file_priv == NULL || (buf->pending &&
1938                                                        buf_priv->age <=
1939                                                        done_age)) {
1940                                 dev_priv->stats.requested_bufs++;
1941                                 buf->pending = 0;
1942                                 return buf;
1943                         }
1944                         if (++start >= dma->buf_count)
1945                                 start = 0;
1946                 }
1947
1948                 if (t) {
1949                         DRM_UDELAY(1);
1950                         dev_priv->stats.freelist_loops++;
1951                 }
1952         }
1953
1954         return NULL;
1955 }
1956
1957 void radeon_freelist_reset(struct drm_device * dev)
1958 {
1959         struct drm_device_dma *dma = dev->dma;
1960         drm_radeon_private_t *dev_priv = dev->dev_private;
1961         int i;
1962
1963         dev_priv->last_buf = 0;
1964         for (i = 0; i < dma->buf_count; i++) {
1965                 struct drm_buf *buf = dma->buflist[i];
1966                 drm_radeon_buf_priv_t *buf_priv = buf->dev_private;
1967                 buf_priv->age = 0;
1968         }
1969 }
1970
1971 /* ================================================================
1972  * CP command submission
1973  */
1974
1975 int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n)
1976 {
1977         drm_radeon_ring_buffer_t *ring = &dev_priv->ring;
1978         int i;
1979         u32 last_head = GET_RING_HEAD(dev_priv);
1980
1981         for (i = 0; i < dev_priv->usec_timeout; i++) {
1982                 u32 head = GET_RING_HEAD(dev_priv);
1983
1984                 ring->space = (head - ring->tail) * sizeof(u32);
1985                 if (ring->space <= 0)
1986                         ring->space += ring->size;
1987                 if (ring->space > n)
1988                         return 0;
1989
1990                 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
1991
1992                 if (head != last_head)
1993                         i = 0;
1994                 last_head = head;
1995
1996                 DRM_UDELAY(1);
1997         }
1998
1999         /* FIXME: This return value is ignored in the BEGIN_RING macro! */
2000 #if RADEON_FIFO_DEBUG
2001         radeon_status(dev_priv);
2002         DRM_ERROR("failed!\n");
2003 #endif
2004         return -EBUSY;
2005 }
2006
2007 static int radeon_cp_get_buffers(struct drm_device *dev,
2008                                  struct drm_file *file_priv,
2009                                  struct drm_dma * d)
2010 {
2011         int i;
2012         struct drm_buf *buf;
2013
2014         for (i = d->granted_count; i < d->request_count; i++) {
2015                 buf = radeon_freelist_get(dev);
2016                 if (!buf)
2017                         return -EBUSY;  /* NOTE: broken client */
2018
2019                 buf->file_priv = file_priv;
2020
2021                 if (DRM_COPY_TO_USER(&d->request_indices[i], &buf->idx,
2022                                      sizeof(buf->idx)))
2023                         return -EFAULT;
2024                 if (DRM_COPY_TO_USER(&d->request_sizes[i], &buf->total,
2025                                      sizeof(buf->total)))
2026                         return -EFAULT;
2027
2028                 d->granted_count++;
2029         }
2030         return 0;
2031 }
2032
2033 int radeon_cp_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv)
2034 {
2035         struct drm_device_dma *dma = dev->dma;
2036         int ret = 0;
2037         struct drm_dma *d = data;
2038
2039         LOCK_TEST_WITH_RETURN(dev, file_priv);
2040
2041         /* Please don't send us buffers.
2042          */
2043         if (d->send_count != 0) {
2044                 DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n",
2045                           DRM_CURRENTPID, d->send_count);
2046                 return -EINVAL;
2047         }
2048
2049         /* We'll send you buffers.
2050          */
2051         if (d->request_count < 0 || d->request_count > dma->buf_count) {
2052                 DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n",
2053                           DRM_CURRENTPID, d->request_count, dma->buf_count);
2054                 return -EINVAL;
2055         }
2056
2057         d->granted_count = 0;
2058
2059         if (d->request_count) {
2060                 ret = radeon_cp_get_buffers(dev, file_priv, d);
2061         }
2062
2063         return ret;
2064 }
2065
2066 int radeon_driver_load(struct drm_device *dev, unsigned long flags)
2067 {
2068         drm_radeon_private_t *dev_priv;
2069         int ret = 0;
2070
2071         dev_priv = kzalloc(sizeof(drm_radeon_private_t), GFP_KERNEL);
2072         if (dev_priv == NULL)
2073                 return -ENOMEM;
2074
2075         dev->dev_private = (void *)dev_priv;
2076         dev_priv->flags = flags;
2077
2078         switch (flags & RADEON_FAMILY_MASK) {
2079         case CHIP_R100:
2080         case CHIP_RV200:
2081         case CHIP_R200:
2082         case CHIP_R300:
2083         case CHIP_R350:
2084         case CHIP_R420:
2085         case CHIP_R423:
2086         case CHIP_RV410:
2087         case CHIP_RV515:
2088         case CHIP_R520:
2089         case CHIP_RV570:
2090         case CHIP_R580:
2091                 dev_priv->flags |= RADEON_HAS_HIERZ;
2092                 break;
2093         default:
2094                 /* all other chips have no hierarchical z buffer */
2095                 break;
2096         }
2097
2098         pci_set_master(dev->pdev);
2099
2100         if (drm_pci_device_is_agp(dev))
2101                 dev_priv->flags |= RADEON_IS_AGP;
2102         else if (pci_is_pcie(dev->pdev))
2103                 dev_priv->flags |= RADEON_IS_PCIE;
2104         else
2105                 dev_priv->flags |= RADEON_IS_PCI;
2106
2107         ret = drm_addmap(dev, pci_resource_start(dev->pdev, 2),
2108                          pci_resource_len(dev->pdev, 2), _DRM_REGISTERS,
2109                          _DRM_READ_ONLY | _DRM_DRIVER, &dev_priv->mmio);
2110         if (ret != 0)
2111                 return ret;
2112
2113         ret = drm_vblank_init(dev, 2);
2114         if (ret) {
2115                 radeon_driver_unload(dev);
2116                 return ret;
2117         }
2118
2119         DRM_DEBUG("%s card detected\n",
2120                   ((dev_priv->flags & RADEON_IS_AGP) ? "AGP" : (((dev_priv->flags & RADEON_IS_PCIE) ? "PCIE" : "PCI"))));
2121         return ret;
2122 }
2123
2124 int radeon_master_create(struct drm_device *dev, struct drm_master *master)
2125 {
2126         struct drm_radeon_master_private *master_priv;
2127         unsigned long sareapage;
2128         int ret;
2129
2130         master_priv = kzalloc(sizeof(*master_priv), GFP_KERNEL);
2131         if (!master_priv)
2132                 return -ENOMEM;
2133
2134         /* prebuild the SAREA */
2135         sareapage = max_t(unsigned long, SAREA_MAX, PAGE_SIZE);
2136         ret = drm_addmap(dev, 0, sareapage, _DRM_SHM, _DRM_CONTAINS_LOCK,
2137                          &master_priv->sarea);
2138         if (ret) {
2139                 DRM_ERROR("SAREA setup failed\n");
2140                 kfree(master_priv);
2141                 return ret;
2142         }
2143         master_priv->sarea_priv = master_priv->sarea->handle + sizeof(struct drm_sarea);
2144         master_priv->sarea_priv->pfCurrentPage = 0;
2145
2146         master->driver_priv = master_priv;
2147         return 0;
2148 }
2149
2150 void radeon_master_destroy(struct drm_device *dev, struct drm_master *master)
2151 {
2152         struct drm_radeon_master_private *master_priv = master->driver_priv;
2153
2154         if (!master_priv)
2155                 return;
2156
2157         if (master_priv->sarea_priv &&
2158             master_priv->sarea_priv->pfCurrentPage != 0)
2159                 radeon_cp_dispatch_flip(dev, master);
2160
2161         master_priv->sarea_priv = NULL;
2162         if (master_priv->sarea)
2163                 drm_rmmap_locked(dev, master_priv->sarea);
2164
2165         kfree(master_priv);
2166
2167         master->driver_priv = NULL;
2168 }
2169
2170 /* Create mappings for registers and framebuffer so userland doesn't necessarily
2171  * have to find them.
2172  */
2173 int radeon_driver_firstopen(struct drm_device *dev)
2174 {
2175         int ret;
2176         drm_local_map_t *map;
2177         drm_radeon_private_t *dev_priv = dev->dev_private;
2178
2179         dev_priv->gart_info.table_size = RADEON_PCIGART_TABLE_SIZE;
2180
2181         dev_priv->fb_aper_offset = pci_resource_start(dev->pdev, 0);
2182         ret = drm_addmap(dev, dev_priv->fb_aper_offset,
2183                          pci_resource_len(dev->pdev, 0), _DRM_FRAME_BUFFER,
2184                          _DRM_WRITE_COMBINING, &map);
2185         if (ret != 0)
2186                 return ret;
2187
2188         return 0;
2189 }
2190
2191 int radeon_driver_unload(struct drm_device *dev)
2192 {
2193         drm_radeon_private_t *dev_priv = dev->dev_private;
2194
2195         DRM_DEBUG("\n");
2196
2197         drm_rmmap(dev, dev_priv->mmio);
2198
2199         kfree(dev_priv);
2200
2201         dev->dev_private = NULL;
2202         return 0;
2203 }
2204
2205 void radeon_commit_ring(drm_radeon_private_t *dev_priv)
2206 {
2207         int i;
2208         u32 *ring;
2209         int tail_aligned;
2210
2211         /* check if the ring is padded out to 16-dword alignment */
2212
2213         tail_aligned = dev_priv->ring.tail & (RADEON_RING_ALIGN-1);
2214         if (tail_aligned) {
2215                 int num_p2 = RADEON_RING_ALIGN - tail_aligned;
2216
2217                 ring = dev_priv->ring.start;
2218                 /* pad with some CP_PACKET2 */
2219                 for (i = 0; i < num_p2; i++)
2220                         ring[dev_priv->ring.tail + i] = CP_PACKET2();
2221
2222                 dev_priv->ring.tail += i;
2223
2224                 dev_priv->ring.space -= num_p2 * sizeof(u32);
2225         }
2226
2227         dev_priv->ring.tail &= dev_priv->ring.tail_mask;
2228
2229         DRM_MEMORYBARRIER();
2230         GET_RING_HEAD( dev_priv );
2231
2232         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) {
2233                 RADEON_WRITE(R600_CP_RB_WPTR, dev_priv->ring.tail);
2234                 /* read from PCI bus to ensure correct posting */
2235                 RADEON_READ(R600_CP_RB_RPTR);
2236         } else {
2237                 RADEON_WRITE(RADEON_CP_RB_WPTR, dev_priv->ring.tail);
2238                 /* read from PCI bus to ensure correct posting */
2239                 RADEON_READ(RADEON_CP_RB_RPTR);
2240         }
2241 }