drivers/gpu/drm/radeon/radeon_combios.c

   1 /*
   2  * Copyright 2004 ATI Technologies Inc., Markham, Ontario
   3  * Copyright 2007-8 Advanced Micro Devices, Inc.
   4  * Copyright 2008 Red Hat Inc.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  */
  27 #include "drmP.h"
  28 #include "radeon_drm.h"
  29 #include "radeon.h"
  30 #include "atom.h"
  31
  32 #ifdef CONFIG_PPC_PMAC
  33 /* not sure which of these are needed */
  34 #include <asm/machdep.h>
  35 #include <asm/pmac_feature.h>
  36 #include <asm/prom.h>
  37 #include <asm/pci-bridge.h>
  38 #endif /* CONFIG_PPC_PMAC */
  39
  40 /* from radeon_encoder.c */
  41 extern uint32_t
  42 radeon_get_encoder_id(struct drm_device *dev, uint32_t supported_device,
  43                       uint8_t dac);
  44 extern void radeon_link_encoder_connector(struct drm_device *dev);
  45
  46 /* from radeon_connector.c */
  47 extern void
  48 radeon_add_legacy_connector(struct drm_device *dev,
  49                             uint32_t connector_id,
  50                             uint32_t supported_device,
  51                             int connector_type,
  52                             struct radeon_i2c_bus_rec *i2c_bus,
  53                             uint16_t connector_object_id,
  54                             struct radeon_hpd *hpd);
  55
  56 /* from radeon_legacy_encoder.c */
  57 extern void
  58 radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_id,
  59                           uint32_t supported_device);
  60
  61 /* old legacy ATI BIOS routines */
  62
  63 /* COMBIOS table offsets */
  64 enum radeon_combios_table_offset {
  65         /* absolute offset tables */
  66         COMBIOS_ASIC_INIT_1_TABLE,
  67         COMBIOS_BIOS_SUPPORT_TABLE,
  68         COMBIOS_DAC_PROGRAMMING_TABLE,
  69         COMBIOS_MAX_COLOR_DEPTH_TABLE,
  70         COMBIOS_CRTC_INFO_TABLE,
  71         COMBIOS_PLL_INFO_TABLE,
  72         COMBIOS_TV_INFO_TABLE,
  73         COMBIOS_DFP_INFO_TABLE,
  74         COMBIOS_HW_CONFIG_INFO_TABLE,
  75         COMBIOS_MULTIMEDIA_INFO_TABLE,
  76         COMBIOS_TV_STD_PATCH_TABLE,
  77         COMBIOS_LCD_INFO_TABLE,
  78         COMBIOS_MOBILE_INFO_TABLE,
  79         COMBIOS_PLL_INIT_TABLE,
  80         COMBIOS_MEM_CONFIG_TABLE,
  81         COMBIOS_SAVE_MASK_TABLE,
  82         COMBIOS_HARDCODED_EDID_TABLE,
  83         COMBIOS_ASIC_INIT_2_TABLE,
  84         COMBIOS_CONNECTOR_INFO_TABLE,
  85         COMBIOS_DYN_CLK_1_TABLE,
  86         COMBIOS_RESERVED_MEM_TABLE,
  87         COMBIOS_EXT_TMDS_INFO_TABLE,
  88         COMBIOS_MEM_CLK_INFO_TABLE,
  89         COMBIOS_EXT_DAC_INFO_TABLE,
  90         COMBIOS_MISC_INFO_TABLE,
  91         COMBIOS_CRT_INFO_TABLE,
  92         COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE,
  93         COMBIOS_COMPONENT_VIDEO_INFO_TABLE,
  94         COMBIOS_FAN_SPEED_INFO_TABLE,
  95         COMBIOS_OVERDRIVE_INFO_TABLE,
  96         COMBIOS_OEM_INFO_TABLE,
  97         COMBIOS_DYN_CLK_2_TABLE,
  98         COMBIOS_POWER_CONNECTOR_INFO_TABLE,
  99         COMBIOS_I2C_INFO_TABLE,
 100         /* relative offset tables */
 101         COMBIOS_ASIC_INIT_3_TABLE,      /* offset from misc info */
 102         COMBIOS_ASIC_INIT_4_TABLE,      /* offset from misc info */
 103         COMBIOS_DETECTED_MEM_TABLE,     /* offset from misc info */
 104         COMBIOS_ASIC_INIT_5_TABLE,      /* offset from misc info */
 105         COMBIOS_RAM_RESET_TABLE,        /* offset from mem config */
 106         COMBIOS_POWERPLAY_INFO_TABLE,   /* offset from mobile info */
 107         COMBIOS_GPIO_INFO_TABLE,        /* offset from mobile info */
 108         COMBIOS_LCD_DDC_INFO_TABLE,     /* offset from mobile info */
 109         COMBIOS_TMDS_POWER_TABLE,       /* offset from mobile info */
 110         COMBIOS_TMDS_POWER_ON_TABLE,    /* offset from tmds power */
 111         COMBIOS_TMDS_POWER_OFF_TABLE,   /* offset from tmds power */
 112 };
 113
 114 enum radeon_combios_ddc {
 115         DDC_NONE_DETECTED,
 116         DDC_MONID,
 117         DDC_DVI,
 118         DDC_VGA,
 119         DDC_CRT2,
 120         DDC_LCD,
 121         DDC_GPIO,
 122 };
 123
 124 enum radeon_combios_connector {
 125         CONNECTOR_NONE_LEGACY,
 126         CONNECTOR_PROPRIETARY_LEGACY,
 127         CONNECTOR_CRT_LEGACY,
 128         CONNECTOR_DVI_I_LEGACY,
 129         CONNECTOR_DVI_D_LEGACY,
 130         CONNECTOR_CTV_LEGACY,
 131         CONNECTOR_STV_LEGACY,
 132         CONNECTOR_UNSUPPORTED_LEGACY
 133 };
 134
 135 const int legacy_connector_convert[] = {
 136         DRM_MODE_CONNECTOR_Unknown,
 137         DRM_MODE_CONNECTOR_DVID,
 138         DRM_MODE_CONNECTOR_VGA,
 139         DRM_MODE_CONNECTOR_DVII,
 140         DRM_MODE_CONNECTOR_DVID,
 141         DRM_MODE_CONNECTOR_Composite,
 142         DRM_MODE_CONNECTOR_SVIDEO,
 143         DRM_MODE_CONNECTOR_Unknown,
 144 };
 145
 146 static uint16_t combios_get_table_offset(struct drm_device *dev,
 147                                          enum radeon_combios_table_offset table)
 148 {
 149         struct radeon_device *rdev = dev->dev_private;
 150         int rev;
 151         uint16_t offset = 0, check_offset;
 152
 153         if (!rdev->bios)
 154                 return 0;
 155
 156         switch (table) {
 157                 /* absolute offset tables */
 158         case COMBIOS_ASIC_INIT_1_TABLE:
 159                 check_offset = RBIOS16(rdev->bios_header_start + 0xc);
 160                 if (check_offset)
 161                         offset = check_offset;
 162                 break;
 163         case COMBIOS_BIOS_SUPPORT_TABLE:
 164                 check_offset = RBIOS16(rdev->bios_header_start + 0x14);
 165                 if (check_offset)
 166                         offset = check_offset;
 167                 break;
 168         case COMBIOS_DAC_PROGRAMMING_TABLE:
 169                 check_offset = RBIOS16(rdev->bios_header_start + 0x2a);
 170                 if (check_offset)
 171                         offset = check_offset;
 172                 break;
 173         case COMBIOS_MAX_COLOR_DEPTH_TABLE:
 174                 check_offset = RBIOS16(rdev->bios_header_start + 0x2c);
 175                 if (check_offset)
 176                         offset = check_offset;
 177                 break;
 178         case COMBIOS_CRTC_INFO_TABLE:
 179                 check_offset = RBIOS16(rdev->bios_header_start + 0x2e);
 180                 if (check_offset)
 181                         offset = check_offset;
 182                 break;
 183         case COMBIOS_PLL_INFO_TABLE:
 184                 check_offset = RBIOS16(rdev->bios_header_start + 0x30);
 185                 if (check_offset)
 186                         offset = check_offset;
 187                 break;
 188         case COMBIOS_TV_INFO_TABLE:
 189                 check_offset = RBIOS16(rdev->bios_header_start + 0x32);
 190                 if (check_offset)
 191                         offset = check_offset;
 192                 break;
 193         case COMBIOS_DFP_INFO_TABLE:
 194                 check_offset = RBIOS16(rdev->bios_header_start + 0x34);
 195                 if (check_offset)
 196                         offset = check_offset;
 197                 break;
 198         case COMBIOS_HW_CONFIG_INFO_TABLE:
 199                 check_offset = RBIOS16(rdev->bios_header_start + 0x36);
 200                 if (check_offset)
 201                         offset = check_offset;
 202                 break;
 203         case COMBIOS_MULTIMEDIA_INFO_TABLE:
 204                 check_offset = RBIOS16(rdev->bios_header_start + 0x38);
 205                 if (check_offset)
 206                         offset = check_offset;
 207                 break;
 208         case COMBIOS_TV_STD_PATCH_TABLE:
 209                 check_offset = RBIOS16(rdev->bios_header_start + 0x3e);
 210                 if (check_offset)
 211                         offset = check_offset;
 212                 break;
 213         case COMBIOS_LCD_INFO_TABLE:
 214                 check_offset = RBIOS16(rdev->bios_header_start + 0x40);
 215                 if (check_offset)
 216                         offset = check_offset;
 217                 break;
 218         case COMBIOS_MOBILE_INFO_TABLE:
 219                 check_offset = RBIOS16(rdev->bios_header_start + 0x42);
 220                 if (check_offset)
 221                         offset = check_offset;
 222                 break;
 223         case COMBIOS_PLL_INIT_TABLE:
 224                 check_offset = RBIOS16(rdev->bios_header_start + 0x46);
 225                 if (check_offset)
 226                         offset = check_offset;
 227                 break;
 228         case COMBIOS_MEM_CONFIG_TABLE:
 229                 check_offset = RBIOS16(rdev->bios_header_start + 0x48);
 230                 if (check_offset)
 231                         offset = check_offset;
 232                 break;
 233         case COMBIOS_SAVE_MASK_TABLE:
 234                 check_offset = RBIOS16(rdev->bios_header_start + 0x4a);
 235                 if (check_offset)
 236                         offset = check_offset;
 237                 break;
 238         case COMBIOS_HARDCODED_EDID_TABLE:
 239                 check_offset = RBIOS16(rdev->bios_header_start + 0x4c);
 240                 if (check_offset)
 241                         offset = check_offset;
 242                 break;
 243         case COMBIOS_ASIC_INIT_2_TABLE:
 244                 check_offset = RBIOS16(rdev->bios_header_start + 0x4e);
 245                 if (check_offset)
 246                         offset = check_offset;
 247                 break;
 248         case COMBIOS_CONNECTOR_INFO_TABLE:
 249                 check_offset = RBIOS16(rdev->bios_header_start + 0x50);
 250                 if (check_offset)
 251                         offset = check_offset;
 252                 break;
 253         case COMBIOS_DYN_CLK_1_TABLE:
 254                 check_offset = RBIOS16(rdev->bios_header_start + 0x52);
 255                 if (check_offset)
 256                         offset = check_offset;
 257                 break;
 258         case COMBIOS_RESERVED_MEM_TABLE:
 259                 check_offset = RBIOS16(rdev->bios_header_start + 0x54);
 260                 if (check_offset)
 261                         offset = check_offset;
 262                 break;
 263         case COMBIOS_EXT_TMDS_INFO_TABLE:
 264                 check_offset = RBIOS16(rdev->bios_header_start + 0x58);
 265                 if (check_offset)
 266                         offset = check_offset;
 267                 break;
 268         case COMBIOS_MEM_CLK_INFO_TABLE:
 269                 check_offset = RBIOS16(rdev->bios_header_start + 0x5a);
 270                 if (check_offset)
 271                         offset = check_offset;
 272                 break;
 273         case COMBIOS_EXT_DAC_INFO_TABLE:
 274                 check_offset = RBIOS16(rdev->bios_header_start + 0x5c);
 275                 if (check_offset)
 276                         offset = check_offset;
 277                 break;
 278         case COMBIOS_MISC_INFO_TABLE:
 279                 check_offset = RBIOS16(rdev->bios_header_start + 0x5e);
 280                 if (check_offset)
 281                         offset = check_offset;
 282                 break;
 283         case COMBIOS_CRT_INFO_TABLE:
 284                 check_offset = RBIOS16(rdev->bios_header_start + 0x60);
 285                 if (check_offset)
 286                         offset = check_offset;
 287                 break;
 288         case COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE:
 289                 check_offset = RBIOS16(rdev->bios_header_start + 0x62);
 290                 if (check_offset)
 291                         offset = check_offset;
 292                 break;
 293         case COMBIOS_COMPONENT_VIDEO_INFO_TABLE:
 294                 check_offset = RBIOS16(rdev->bios_header_start + 0x64);
 295                 if (check_offset)
 296                         offset = check_offset;
 297                 break;
 298         case COMBIOS_FAN_SPEED_INFO_TABLE:
 299                 check_offset = RBIOS16(rdev->bios_header_start + 0x66);
 300                 if (check_offset)
 301                         offset = check_offset;
 302                 break;
 303         case COMBIOS_OVERDRIVE_INFO_TABLE:
 304                 check_offset = RBIOS16(rdev->bios_header_start + 0x68);
 305                 if (check_offset)
 306                         offset = check_offset;
 307                 break;
 308         case COMBIOS_OEM_INFO_TABLE:
 309                 check_offset = RBIOS16(rdev->bios_header_start + 0x6a);
 310                 if (check_offset)
 311                         offset = check_offset;
 312                 break;
 313         case COMBIOS_DYN_CLK_2_TABLE:
 314                 check_offset = RBIOS16(rdev->bios_header_start + 0x6c);
 315                 if (check_offset)
 316                         offset = check_offset;
 317                 break;
 318         case COMBIOS_POWER_CONNECTOR_INFO_TABLE:
 319                 check_offset = RBIOS16(rdev->bios_header_start + 0x6e);
 320                 if (check_offset)
 321                         offset = check_offset;
 322                 break;
 323         case COMBIOS_I2C_INFO_TABLE:
 324                 check_offset = RBIOS16(rdev->bios_header_start + 0x70);
 325                 if (check_offset)
 326                         offset = check_offset;
 327                 break;
 328                 /* relative offset tables */
 329         case COMBIOS_ASIC_INIT_3_TABLE: /* offset from misc info */
 330                 check_offset =
 331                     combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
 332                 if (check_offset) {
 333                         rev = RBIOS8(check_offset);
 334                         if (rev > 0) {
 335                                 check_offset = RBIOS16(check_offset + 0x3);
 336                                 if (check_offset)
 337                                         offset = check_offset;
 338                         }
 339                 }
 340                 break;
 341         case COMBIOS_ASIC_INIT_4_TABLE: /* offset from misc info */
 342                 check_offset =
 343                     combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
 344                 if (check_offset) {
 345                         rev = RBIOS8(check_offset);
 346                         if (rev > 0) {
 347                                 check_offset = RBIOS16(check_offset + 0x5);
 348                                 if (check_offset)
 349                                         offset = check_offset;
 350                         }
 351                 }
 352                 break;
 353         case COMBIOS_DETECTED_MEM_TABLE:        /* offset from misc info */
 354                 check_offset =
 355                     combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
 356                 if (check_offset) {
 357                         rev = RBIOS8(check_offset);
 358                         if (rev > 0) {
 359                                 check_offset = RBIOS16(check_offset + 0x7);
 360                                 if (check_offset)
 361                                         offset = check_offset;
 362                         }
 363                 }
 364                 break;
 365         case COMBIOS_ASIC_INIT_5_TABLE: /* offset from misc info */
 366                 check_offset =
 367                     combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
 368                 if (check_offset) {
 369                         rev = RBIOS8(check_offset);
 370                         if (rev == 2) {
 371                                 check_offset = RBIOS16(check_offset + 0x9);
 372                                 if (check_offset)
 373                                         offset = check_offset;
 374                         }
 375                 }
 376                 break;
 377         case COMBIOS_RAM_RESET_TABLE:   /* offset from mem config */
 378                 check_offset =
 379                     combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE);
 380                 if (check_offset) {
 381                         while (RBIOS8(check_offset++));
 382                         check_offset += 2;
 383                         if (check_offset)
 384                                 offset = check_offset;
 385                 }
 386                 break;
 387         case COMBIOS_POWERPLAY_INFO_TABLE:      /* offset from mobile info */
 388                 check_offset =
 389                     combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
 390                 if (check_offset) {
 391                         check_offset = RBIOS16(check_offset + 0x11);
 392                         if (check_offset)
 393                                 offset = check_offset;
 394                 }
 395                 break;
 396         case COMBIOS_GPIO_INFO_TABLE:   /* offset from mobile info */
 397                 check_offset =
 398                     combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
 399                 if (check_offset) {
 400                         check_offset = RBIOS16(check_offset + 0x13);
 401                         if (check_offset)
 402                                 offset = check_offset;
 403                 }
 404                 break;
 405         case COMBIOS_LCD_DDC_INFO_TABLE:        /* offset from mobile info */
 406                 check_offset =
 407                     combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
 408                 if (check_offset) {
 409                         check_offset = RBIOS16(check_offset + 0x15);
 410                         if (check_offset)
 411                                 offset = check_offset;
 412                 }
 413                 break;
 414         case COMBIOS_TMDS_POWER_TABLE:  /* offset from mobile info */
 415                 check_offset =
 416                     combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
 417                 if (check_offset) {
 418                         check_offset = RBIOS16(check_offset + 0x17);
 419                         if (check_offset)
 420                                 offset = check_offset;
 421                 }
 422                 break;
 423         case COMBIOS_TMDS_POWER_ON_TABLE:       /* offset from tmds power */
 424                 check_offset =
 425                     combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE);
 426                 if (check_offset) {
 427                         check_offset = RBIOS16(check_offset + 0x2);
 428                         if (check_offset)
 429                                 offset = check_offset;
 430                 }
 431                 break;
 432         case COMBIOS_TMDS_POWER_OFF_TABLE:      /* offset from tmds power */
 433                 check_offset =
 434                     combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE);
 435                 if (check_offset) {
 436                         check_offset = RBIOS16(check_offset + 0x4);
 437                         if (check_offset)
 438                                 offset = check_offset;
 439                 }
 440                 break;
 441         default:
 442                 break;
 443         }
 444
 445         return offset;
 446
 447 }
 448
 449 bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev)
 450 {
 451         int edid_info;
 452         struct edid *edid;
 453         unsigned char *raw;
 454         edid_info = combios_get_table_offset(rdev->ddev, COMBIOS_HARDCODED_EDID_TABLE);
 455         if (!edid_info)
 456                 return false;
 457
 458         raw = rdev->bios + edid_info;
 459         edid = kmalloc(EDID_LENGTH * (raw[0x7e] + 1), GFP_KERNEL);
 460         if (edid == NULL)
 461                 return false;
 462
 463         memcpy((unsigned char *)edid, raw, EDID_LENGTH * (raw[0x7e] + 1));
 464
 465         if (!drm_edid_is_valid(edid)) {
 466                 kfree(edid);
 467                 return false;
 468         }
 469
 470         rdev->mode_info.bios_hardcoded_edid = edid;
 471         return true;
 472 }
 473
 474 struct edid *
 475 radeon_combios_get_hardcoded_edid(struct radeon_device *rdev)
 476 {
 477         if (rdev->mode_info.bios_hardcoded_edid)
 478                 return rdev->mode_info.bios_hardcoded_edid;
 479         return NULL;
 480 }
 481
 482 static struct radeon_i2c_bus_rec combios_setup_i2c_bus(struct radeon_device *rdev,
 483                                                        int ddc_line)
 484 {
 485         struct radeon_i2c_bus_rec i2c;
 486
 487         if (ddc_line == RADEON_GPIOPAD_MASK) {
 488                 i2c.mask_clk_reg = RADEON_GPIOPAD_MASK;
 489                 i2c.mask_data_reg = RADEON_GPIOPAD_MASK;
 490                 i2c.a_clk_reg = RADEON_GPIOPAD_A;
 491                 i2c.a_data_reg = RADEON_GPIOPAD_A;
 492                 i2c.en_clk_reg = RADEON_GPIOPAD_EN;
 493                 i2c.en_data_reg = RADEON_GPIOPAD_EN;
 494                 i2c.y_clk_reg = RADEON_GPIOPAD_Y;
 495                 i2c.y_data_reg = RADEON_GPIOPAD_Y;
 496         } else if (ddc_line == RADEON_MDGPIO_MASK) {
 497                 i2c.mask_clk_reg = RADEON_MDGPIO_MASK;
 498                 i2c.mask_data_reg = RADEON_MDGPIO_MASK;
 499                 i2c.a_clk_reg = RADEON_MDGPIO_A;
 500                 i2c.a_data_reg = RADEON_MDGPIO_A;
 501                 i2c.en_clk_reg = RADEON_MDGPIO_EN;
 502                 i2c.en_data_reg = RADEON_MDGPIO_EN;
 503                 i2c.y_clk_reg = RADEON_MDGPIO_Y;
 504                 i2c.y_data_reg = RADEON_MDGPIO_Y;
 505         } else {
 506                 i2c.mask_clk_mask = RADEON_GPIO_EN_1;
 507                 i2c.mask_data_mask = RADEON_GPIO_EN_0;
 508                 i2c.a_clk_mask = RADEON_GPIO_A_1;
 509                 i2c.a_data_mask = RADEON_GPIO_A_0;
 510                 i2c.en_clk_mask = RADEON_GPIO_EN_1;
 511                 i2c.en_data_mask = RADEON_GPIO_EN_0;
 512                 i2c.y_clk_mask = RADEON_GPIO_Y_1;
 513                 i2c.y_data_mask = RADEON_GPIO_Y_0;
 514
 515                 i2c.mask_clk_reg = ddc_line;
 516                 i2c.mask_data_reg = ddc_line;
 517                 i2c.a_clk_reg = ddc_line;
 518                 i2c.a_data_reg = ddc_line;
 519                 i2c.en_clk_reg = ddc_line;
 520                 i2c.en_data_reg = ddc_line;
 521                 i2c.y_clk_reg = ddc_line;
 522                 i2c.y_data_reg = ddc_line;
 523         }
 524
 525         switch (rdev->family) {
 526         case CHIP_R100:
 527         case CHIP_RV100:
 528         case CHIP_RS100:
 529         case CHIP_RV200:
 530         case CHIP_RS200:
 531         case CHIP_RS300:
 532                 switch (ddc_line) {
 533                 case RADEON_GPIO_DVI_DDC:
 534                         i2c.hw_capable = true;
 535                         break;
 536                 default:
 537                         i2c.hw_capable = false;
 538                         break;
 539                 }
 540                 break;
 541         case CHIP_R200:
 542                 switch (ddc_line) {
 543                 case RADEON_GPIO_DVI_DDC:
 544                 case RADEON_GPIO_MONID:
 545                         i2c.hw_capable = true;
 546                         break;
 547                 default:
 548                         i2c.hw_capable = false;
 549                         break;
 550                 }
 551                 break;
 552         case CHIP_RV250:
 553         case CHIP_RV280:
 554                 switch (ddc_line) {
 555                 case RADEON_GPIO_VGA_DDC:
 556                 case RADEON_GPIO_DVI_DDC:
 557                 case RADEON_GPIO_CRT2_DDC:
 558                         i2c.hw_capable = true;
 559                         break;
 560                 default:
 561                         i2c.hw_capable = false;
 562                         break;
 563                 }
 564                 break;
 565         case CHIP_R300:
 566         case CHIP_R350:
 567                 switch (ddc_line) {
 568                 case RADEON_GPIO_VGA_DDC:
 569                 case RADEON_GPIO_DVI_DDC:
 570                         i2c.hw_capable = true;
 571                         break;
 572                 default:
 573                         i2c.hw_capable = false;
 574                         break;
 575                 }
 576                 break;
 577         case CHIP_RV350:
 578         case CHIP_RV380:
 579         case CHIP_RS400:
 580         case CHIP_RS480:
 581                 switch (ddc_line) {
 582                 case RADEON_GPIO_VGA_DDC:
 583                 case RADEON_GPIO_DVI_DDC:
 584                         i2c.hw_capable = true;
 585                         break;
 586                 case RADEON_GPIO_MONID:
 587                         /* hw i2c on RADEON_GPIO_MONID doesn't seem to work
 588                          * reliably on some pre-r4xx hardware; not sure why.
 589                          */
 590                         i2c.hw_capable = false;
 591                         break;
 592                 default:
 593                         i2c.hw_capable = false;
 594                         break;
 595                 }
 596                 break;
 597         default:
 598                 i2c.hw_capable = false;
 599                 break;
 600         }
 601         i2c.mm_i2c = false;
 602         i2c.i2c_id = 0;
 603         i2c.hpd = RADEON_HPD_NONE;
 604
 605         if (ddc_line)
 606                 i2c.valid = true;
 607         else
 608                 i2c.valid = false;
 609
 610         return i2c;
 611 }
 612
 613 bool radeon_combios_get_clock_info(struct drm_device *dev)
 614 {
 615         struct radeon_device *rdev = dev->dev_private;
 616         uint16_t pll_info;
 617         struct radeon_pll *p1pll = &rdev->clock.p1pll;
 618         struct radeon_pll *p2pll = &rdev->clock.p2pll;
 619         struct radeon_pll *spll = &rdev->clock.spll;
 620         struct radeon_pll *mpll = &rdev->clock.mpll;
 621         int8_t rev;
 622         uint16_t sclk, mclk;
 623
 624         pll_info = combios_get_table_offset(dev, COMBIOS_PLL_INFO_TABLE);
 625         if (pll_info) {
 626                 rev = RBIOS8(pll_info);
 627
 628                 /* pixel clocks */
 629                 p1pll->reference_freq = RBIOS16(pll_info + 0xe);
 630                 p1pll->reference_div = RBIOS16(pll_info + 0x10);
 631                 p1pll->pll_out_min = RBIOS32(pll_info + 0x12);
 632                 p1pll->pll_out_max = RBIOS32(pll_info + 0x16);
 633                 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
 634                 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
 635
 636                 if (rev > 9) {
 637                         p1pll->pll_in_min = RBIOS32(pll_info + 0x36);
 638                         p1pll->pll_in_max = RBIOS32(pll_info + 0x3a);
 639                 } else {
 640                         p1pll->pll_in_min = 40;
 641                         p1pll->pll_in_max = 500;
 642                 }
 643                 *p2pll = *p1pll;
 644
 645                 /* system clock */
 646                 spll->reference_freq = RBIOS16(pll_info + 0x1a);
 647                 spll->reference_div = RBIOS16(pll_info + 0x1c);
 648                 spll->pll_out_min = RBIOS32(pll_info + 0x1e);
 649                 spll->pll_out_max = RBIOS32(pll_info + 0x22);
 650
 651                 if (rev > 10) {
 652                         spll->pll_in_min = RBIOS32(pll_info + 0x48);
 653                         spll->pll_in_max = RBIOS32(pll_info + 0x4c);
 654                 } else {
 655                         /* ??? */
 656                         spll->pll_in_min = 40;
 657                         spll->pll_in_max = 500;
 658                 }
 659
 660                 /* memory clock */
 661                 mpll->reference_freq = RBIOS16(pll_info + 0x26);
 662                 mpll->reference_div = RBIOS16(pll_info + 0x28);
 663                 mpll->pll_out_min = RBIOS32(pll_info + 0x2a);
 664                 mpll->pll_out_max = RBIOS32(pll_info + 0x2e);
 665
 666                 if (rev > 10) {
 667                         mpll->pll_in_min = RBIOS32(pll_info + 0x5a);
 668                         mpll->pll_in_max = RBIOS32(pll_info + 0x5e);
 669                 } else {
 670                         /* ??? */
 671                         mpll->pll_in_min = 40;
 672                         mpll->pll_in_max = 500;
 673                 }
 674
 675                 /* default sclk/mclk */
 676                 sclk = RBIOS16(pll_info + 0xa);
 677                 mclk = RBIOS16(pll_info + 0x8);
 678                 if (sclk == 0)
 679                         sclk = 200 * 100;
 680                 if (mclk == 0)
 681                         mclk = 200 * 100;
 682
 683                 rdev->clock.default_sclk = sclk;
 684                 rdev->clock.default_mclk = mclk;
 685
 686                 return true;
 687         }
 688         return false;
 689 }
 690
 691 bool radeon_combios_sideport_present(struct radeon_device *rdev)
 692 {
 693         struct drm_device *dev = rdev->ddev;
 694         u16 igp_info;
 695
 696         igp_info = combios_get_table_offset(dev, COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE);
 697
 698         if (igp_info) {
 699                 if (RBIOS16(igp_info + 0x4))
 700                         return true;
 701         }
 702         return false;
 703 }
 704
 705 static const uint32_t default_primarydac_adj[CHIP_LAST] = {
 706         0x00000808,             /* r100  */
 707         0x00000808,             /* rv100 */
 708         0x00000808,             /* rs100 */
 709         0x00000808,             /* rv200 */
 710         0x00000808,             /* rs200 */
 711         0x00000808,             /* r200  */
 712         0x00000808,             /* rv250 */
 713         0x00000000,             /* rs300 */
 714         0x00000808,             /* rv280 */
 715         0x00000808,             /* r300  */
 716         0x00000808,             /* r350  */
 717         0x00000808,             /* rv350 */
 718         0x00000808,             /* rv380 */
 719         0x00000808,             /* r420  */
 720         0x00000808,             /* r423  */
 721         0x00000808,             /* rv410 */
 722         0x00000000,             /* rs400 */
 723         0x00000000,             /* rs480 */
 724 };
 725
 726 static void radeon_legacy_get_primary_dac_info_from_table(struct radeon_device *rdev,
 727                                                           struct radeon_encoder_primary_dac *p_dac)
 728 {
 729         p_dac->ps2_pdac_adj = default_primarydac_adj[rdev->family];
 730         return;
 731 }
 732
 733 struct radeon_encoder_primary_dac *radeon_combios_get_primary_dac_info(struct
 734                                                                        radeon_encoder
 735                                                                        *encoder)
 736 {
 737         struct drm_device *dev = encoder->base.dev;
 738         struct radeon_device *rdev = dev->dev_private;
 739         uint16_t dac_info;
 740         uint8_t rev, bg, dac;
 741         struct radeon_encoder_primary_dac *p_dac = NULL;
 742         int found = 0;
 743
 744         p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac),
 745                         GFP_KERNEL);
 746
 747         if (!p_dac)
 748                 return NULL;
 749
 750         /* check CRT table */
 751         dac_info = combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
 752         if (dac_info) {
 753                 rev = RBIOS8(dac_info) & 0x3;
 754                 if (rev < 2) {
 755                         bg = RBIOS8(dac_info + 0x2) & 0xf;
 756                         dac = (RBIOS8(dac_info + 0x2) >> 4) & 0xf;
 757                         p_dac->ps2_pdac_adj = (bg << 8) | (dac);
 758                 } else {
 759                         bg = RBIOS8(dac_info + 0x2) & 0xf;
 760                         dac = RBIOS8(dac_info + 0x3) & 0xf;
 761                         p_dac->ps2_pdac_adj = (bg << 8) | (dac);
 762                 }
 763                 /* if the values are all zeros, use the table */
 764                 if (p_dac->ps2_pdac_adj)
 765                         found = 1;
 766         }
 767
 768         if (!found) /* fallback to defaults */
 769                 radeon_legacy_get_primary_dac_info_from_table(rdev, p_dac);
 770
 771         return p_dac;
 772 }
 773
 774 enum radeon_tv_std
 775 radeon_combios_get_tv_info(struct radeon_device *rdev)
 776 {
 777         struct drm_device *dev = rdev->ddev;
 778         uint16_t tv_info;
 779         enum radeon_tv_std tv_std = TV_STD_NTSC;
 780
 781         tv_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
 782         if (tv_info) {
 783                 if (RBIOS8(tv_info + 6) == 'T') {
 784                         switch (RBIOS8(tv_info + 7) & 0xf) {
 785                         case 1:
 786                                 tv_std = TV_STD_NTSC;
 787                                 DRM_INFO("Default TV standard: NTSC\n");
 788                                 break;
 789                         case 2:
 790                                 tv_std = TV_STD_PAL;
 791                                 DRM_INFO("Default TV standard: PAL\n");
 792                                 break;
 793                         case 3:
 794                                 tv_std = TV_STD_PAL_M;
 795                                 DRM_INFO("Default TV standard: PAL-M\n");
 796                                 break;
 797                         case 4:
 798                                 tv_std = TV_STD_PAL_60;
 799                                 DRM_INFO("Default TV standard: PAL-60\n");
 800                                 break;
 801                         case 5:
 802                                 tv_std = TV_STD_NTSC_J;
 803                                 DRM_INFO("Default TV standard: NTSC-J\n");
 804                                 break;
 805                         case 6:
 806                                 tv_std = TV_STD_SCART_PAL;
 807                                 DRM_INFO("Default TV standard: SCART-PAL\n");
 808                                 break;
 809                         default:
 810                                 tv_std = TV_STD_NTSC;
 811                                 DRM_INFO
 812                                     ("Unknown TV standard; defaulting to NTSC\n");
 813                                 break;
 814                         }
 815
 816                         switch ((RBIOS8(tv_info + 9) >> 2) & 0x3) {
 817                         case 0:
 818                                 DRM_INFO("29.498928713 MHz TV ref clk\n");
 819                                 break;
 820                         case 1:
 821                                 DRM_INFO("28.636360000 MHz TV ref clk\n");
 822                                 break;
 823                         case 2:
 824                                 DRM_INFO("14.318180000 MHz TV ref clk\n");
 825                                 break;
 826                         case 3:
 827                                 DRM_INFO("27.000000000 MHz TV ref clk\n");
 828                                 break;
 829                         default:
 830                                 break;
 831                         }
 832                 }
 833         }
 834         return tv_std;
 835 }
 836
 837 static const uint32_t default_tvdac_adj[CHIP_LAST] = {
 838         0x00000000,             /* r100  */
 839         0x00280000,             /* rv100 */
 840         0x00000000,             /* rs100 */
 841         0x00880000,             /* rv200 */
 842         0x00000000,             /* rs200 */
 843         0x00000000,             /* r200  */
 844         0x00770000,             /* rv250 */
 845         0x00290000,             /* rs300 */
 846         0x00560000,             /* rv280 */
 847         0x00780000,             /* r300  */
 848         0x00770000,             /* r350  */
 849         0x00780000,             /* rv350 */
 850         0x00780000,             /* rv380 */
 851         0x01080000,             /* r420  */
 852         0x01080000,             /* r423  */
 853         0x01080000,             /* rv410 */
 854         0x00780000,             /* rs400 */
 855         0x00780000,             /* rs480 */
 856 };
 857
 858 static void radeon_legacy_get_tv_dac_info_from_table(struct radeon_device *rdev,
 859                                                      struct radeon_encoder_tv_dac *tv_dac)
 860 {
 861         tv_dac->ps2_tvdac_adj = default_tvdac_adj[rdev->family];
 862         if ((rdev->flags & RADEON_IS_MOBILITY) && (rdev->family == CHIP_RV250))
 863                 tv_dac->ps2_tvdac_adj = 0x00880000;
 864         tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
 865         tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
 866         return;
 867 }
 868
 869 struct radeon_encoder_tv_dac *radeon_combios_get_tv_dac_info(struct
 870                                                              radeon_encoder
 871                                                              *encoder)
 872 {
 873         struct drm_device *dev = encoder->base.dev;
 874         struct radeon_device *rdev = dev->dev_private;
 875         uint16_t dac_info;
 876         uint8_t rev, bg, dac;
 877         struct radeon_encoder_tv_dac *tv_dac = NULL;
 878         int found = 0;
 879
 880         tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
 881         if (!tv_dac)
 882                 return NULL;
 883
 884         /* first check TV table */
 885         dac_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
 886         if (dac_info) {
 887                 rev = RBIOS8(dac_info + 0x3);
 888                 if (rev > 4) {
 889                         bg = RBIOS8(dac_info + 0xc) & 0xf;
 890                         dac = RBIOS8(dac_info + 0xd) & 0xf;
 891                         tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
 892
 893                         bg = RBIOS8(dac_info + 0xe) & 0xf;
 894                         dac = RBIOS8(dac_info + 0xf) & 0xf;
 895                         tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
 896
 897                         bg = RBIOS8(dac_info + 0x10) & 0xf;
 898                         dac = RBIOS8(dac_info + 0x11) & 0xf;
 899                         tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
 900                         /* if the values are all zeros, use the table */
 901                         if (tv_dac->ps2_tvdac_adj)
 902                                 found = 1;
 903                 } else if (rev > 1) {
 904                         bg = RBIOS8(dac_info + 0xc) & 0xf;
 905                         dac = (RBIOS8(dac_info + 0xc) >> 4) & 0xf;
 906                         tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
 907
 908                         bg = RBIOS8(dac_info + 0xd) & 0xf;
 909                         dac = (RBIOS8(dac_info + 0xd) >> 4) & 0xf;
 910                         tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
 911
 912                         bg = RBIOS8(dac_info + 0xe) & 0xf;
 913                         dac = (RBIOS8(dac_info + 0xe) >> 4) & 0xf;
 914                         tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
 915                         /* if the values are all zeros, use the table */
 916                         if (tv_dac->ps2_tvdac_adj)
 917                                 found = 1;
 918                 }
 919                 tv_dac->tv_std = radeon_combios_get_tv_info(rdev);
 920         }
 921         if (!found) {
 922                 /* then check CRT table */
 923                 dac_info =
 924                     combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
 925                 if (dac_info) {
 926                         rev = RBIOS8(dac_info) & 0x3;
 927                         if (rev < 2) {
 928                                 bg = RBIOS8(dac_info + 0x3) & 0xf;
 929                                 dac = (RBIOS8(dac_info + 0x3) >> 4) & 0xf;
 930                                 tv_dac->ps2_tvdac_adj =
 931                                     (bg << 16) | (dac << 20);
 932                                 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
 933                                 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
 934                                 /* if the values are all zeros, use the table */
 935                                 if (tv_dac->ps2_tvdac_adj)
 936                                         found = 1;
 937                         } else {
 938                                 bg = RBIOS8(dac_info + 0x4) & 0xf;
 939                                 dac = RBIOS8(dac_info + 0x5) & 0xf;
 940                                 tv_dac->ps2_tvdac_adj =
 941                                     (bg << 16) | (dac << 20);
 942                                 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
 943                                 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
 944                                 /* if the values are all zeros, use the table */
 945                                 if (tv_dac->ps2_tvdac_adj)
 946                                         found = 1;
 947                         }
 948                 } else {
 949                         DRM_INFO("No TV DAC info found in BIOS\n");
 950                 }
 951         }
 952
 953         if (!found) /* fallback to defaults */
 954                 radeon_legacy_get_tv_dac_info_from_table(rdev, tv_dac);
 955
 956         return tv_dac;
 957 }
 958
 959 static struct radeon_encoder_lvds *radeon_legacy_get_lvds_info_from_regs(struct
 960                                                                          radeon_device
 961                                                                          *rdev)
 962 {
 963         struct radeon_encoder_lvds *lvds = NULL;
 964         uint32_t fp_vert_stretch, fp_horz_stretch;
 965         uint32_t ppll_div_sel, ppll_val;
 966         uint32_t lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL);
 967
 968         lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL);
 969
 970         if (!lvds)
 971                 return NULL;
 972
 973         fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH);
 974         fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH);
 975
 976         /* These should be fail-safe defaults, fingers crossed */
 977         lvds->panel_pwr_delay = 200;
 978         lvds->panel_vcc_delay = 2000;
 979
 980         lvds->lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
 981         lvds->panel_digon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) & 0xf;
 982         lvds->panel_blon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY2_SHIFT) & 0xf;
 983
 984         if (fp_vert_stretch & RADEON_VERT_STRETCH_ENABLE)
 985                 lvds->native_mode.vdisplay =
 986                     ((fp_vert_stretch & RADEON_VERT_PANEL_SIZE) >>
 987                      RADEON_VERT_PANEL_SHIFT) + 1;
 988         else
 989                 lvds->native_mode.vdisplay =
 990                     (RREG32(RADEON_CRTC_V_TOTAL_DISP) >> 16) + 1;
 991
 992         if (fp_horz_stretch & RADEON_HORZ_STRETCH_ENABLE)
 993                 lvds->native_mode.hdisplay =
 994                     (((fp_horz_stretch & RADEON_HORZ_PANEL_SIZE) >>
 995                       RADEON_HORZ_PANEL_SHIFT) + 1) * 8;
 996         else
 997                 lvds->native_mode.hdisplay =
 998                     ((RREG32(RADEON_CRTC_H_TOTAL_DISP) >> 16) + 1) * 8;
 999
1000         if ((lvds->native_mode.hdisplay < 640) ||
1001             (lvds->native_mode.vdisplay < 480)) {
1002                 lvds->native_mode.hdisplay = 640;
1003                 lvds->native_mode.vdisplay = 480;
1004         }
1005
1006         ppll_div_sel = RREG8(RADEON_CLOCK_CNTL_INDEX + 1) & 0x3;
1007         ppll_val = RREG32_PLL(RADEON_PPLL_DIV_0 + ppll_div_sel);
1008         if ((ppll_val & 0x000707ff) == 0x1bb)
1009                 lvds->use_bios_dividers = false;
1010         else {
1011                 lvds->panel_ref_divider =
1012                     RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff;
1013                 lvds->panel_post_divider = (ppll_val >> 16) & 0x7;
1014                 lvds->panel_fb_divider = ppll_val & 0x7ff;
1015
1016                 if ((lvds->panel_ref_divider != 0) &&
1017                     (lvds->panel_fb_divider > 3))
1018                         lvds->use_bios_dividers = true;
1019         }
1020         lvds->panel_vcc_delay = 200;
1021
1022         DRM_INFO("Panel info derived from registers\n");
1023         DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay,
1024                  lvds->native_mode.vdisplay);
1025
1026         return lvds;
1027 }
1028
1029 struct radeon_encoder_lvds *radeon_combios_get_lvds_info(struct radeon_encoder
1030                                                          *encoder)
1031 {
1032         struct drm_device *dev = encoder->base.dev;
1033         struct radeon_device *rdev = dev->dev_private;
1034         uint16_t lcd_info;
1035         uint32_t panel_setup;
1036         char stmp[30];
1037         int tmp, i;
1038         struct radeon_encoder_lvds *lvds = NULL;
1039
1040         lcd_info = combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);
1041
1042         if (lcd_info) {
1043                 lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL);
1044
1045                 if (!lvds)
1046                         return NULL;
1047
1048                 for (i = 0; i < 24; i++)
1049                         stmp[i] = RBIOS8(lcd_info + i + 1);
1050                 stmp[24] = 0;
1051
1052                 DRM_INFO("Panel ID String: %s\n", stmp);
1053
1054                 lvds->native_mode.hdisplay = RBIOS16(lcd_info + 0x19);
1055                 lvds->native_mode.vdisplay = RBIOS16(lcd_info + 0x1b);
1056
1057                 DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay,
1058                          lvds->native_mode.vdisplay);
1059
1060                 lvds->panel_vcc_delay = RBIOS16(lcd_info + 0x2c);
1061                 lvds->panel_vcc_delay = min_t(u16, lvds->panel_vcc_delay, 2000);
1062
1063                 lvds->panel_pwr_delay = RBIOS8(lcd_info + 0x24);
1064                 lvds->panel_digon_delay = RBIOS16(lcd_info + 0x38) & 0xf;
1065                 lvds->panel_blon_delay = (RBIOS16(lcd_info + 0x38) >> 4) & 0xf;
1066
1067                 lvds->panel_ref_divider = RBIOS16(lcd_info + 0x2e);
1068                 lvds->panel_post_divider = RBIOS8(lcd_info + 0x30);
1069                 lvds->panel_fb_divider = RBIOS16(lcd_info + 0x31);
1070                 if ((lvds->panel_ref_divider != 0) &&
1071                     (lvds->panel_fb_divider > 3))
1072                         lvds->use_bios_dividers = true;
1073
1074                 panel_setup = RBIOS32(lcd_info + 0x39);
1075                 lvds->lvds_gen_cntl = 0xff00;
1076                 if (panel_setup & 0x1)
1077                         lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_FORMAT;
1078
1079                 if ((panel_setup >> 4) & 0x1)
1080                         lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_TYPE;
1081
1082                 switch ((panel_setup >> 8) & 0x7) {
1083                 case 0:
1084                         lvds->lvds_gen_cntl |= RADEON_LVDS_NO_FM;
1085                         break;
1086                 case 1:
1087                         lvds->lvds_gen_cntl |= RADEON_LVDS_2_GREY;
1088                         break;
1089                 case 2:
1090                         lvds->lvds_gen_cntl |= RADEON_LVDS_4_GREY;
1091                         break;
1092                 default:
1093                         break;
1094                 }
1095
1096                 if ((panel_setup >> 16) & 0x1)
1097                         lvds->lvds_gen_cntl |= RADEON_LVDS_FP_POL_LOW;
1098
1099                 if ((panel_setup >> 17) & 0x1)
1100                         lvds->lvds_gen_cntl |= RADEON_LVDS_LP_POL_LOW;
1101
1102                 if ((panel_setup >> 18) & 0x1)
1103                         lvds->lvds_gen_cntl |= RADEON_LVDS_DTM_POL_LOW;
1104
1105                 if ((panel_setup >> 23) & 0x1)
1106                         lvds->lvds_gen_cntl |= RADEON_LVDS_BL_CLK_SEL;
1107
1108                 lvds->lvds_gen_cntl |= (panel_setup & 0xf0000000);
1109
1110                 for (i = 0; i < 32; i++) {
1111                         tmp = RBIOS16(lcd_info + 64 + i * 2);
1112                         if (tmp == 0)
1113                                 break;
1114
1115                         if ((RBIOS16(tmp) == lvds->native_mode.hdisplay) &&
1116                             (RBIOS16(tmp + 2) == lvds->native_mode.vdisplay)) {
1117                                 lvds->native_mode.htotal = lvds->native_mode.hdisplay +
1118                                         (RBIOS16(tmp + 17) - RBIOS16(tmp + 19)) * 8;
1119                                 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
1120                                         (RBIOS16(tmp + 21) - RBIOS16(tmp + 19) - 1) * 8;
1121                                 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
1122                                         (RBIOS8(tmp + 23) * 8);
1123
1124                                 lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
1125                                         (RBIOS16(tmp + 24) - RBIOS16(tmp + 26));
1126                                 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
1127                                         ((RBIOS16(tmp + 28) & 0x7ff) - RBIOS16(tmp + 26));
1128                                 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
1129                                         ((RBIOS16(tmp + 28) & 0xf800) >> 11);
1130
1131                                 lvds->native_mode.clock = RBIOS16(tmp + 9) * 10;
1132                                 lvds->native_mode.flags = 0;
1133                                 /* set crtc values */
1134                                 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
1135
1136                         }
1137                 }
1138         } else {
1139                 DRM_INFO("No panel info found in BIOS\n");
1140                 lvds = radeon_legacy_get_lvds_info_from_regs(rdev);
1141         }
1142
1143         if (lvds)
1144                 encoder->native_mode = lvds->native_mode;
1145         return lvds;
1146 }
1147
1148 static const struct radeon_tmds_pll default_tmds_pll[CHIP_LAST][4] = {
1149         {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}},  /* CHIP_R100  */
1150         {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}},  /* CHIP_RV100 */
1151         {{0, 0}, {0, 0}, {0, 0}, {0, 0}},       /* CHIP_RS100 */
1152         {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}},  /* CHIP_RV200 */
1153         {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}},  /* CHIP_RS200 */
1154         {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}},  /* CHIP_R200  */
1155         {{15500, 0x81b}, {0xffffffff, 0x83f}, {0, 0}, {0, 0}},  /* CHIP_RV250 */
1156         {{0, 0}, {0, 0}, {0, 0}, {0, 0}},       /* CHIP_RS300 */
1157         {{13000, 0x400f4}, {15000, 0x400f7}, {0xffffffff, 0x40111}, {0, 0}},    /* CHIP_RV280 */
1158         {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}},        /* CHIP_R300  */
1159         {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}},        /* CHIP_R350  */
1160         {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}},      /* CHIP_RV350 */
1161         {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}},      /* CHIP_RV380 */
1162         {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}},        /* CHIP_R420  */
1163         {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}},        /* CHIP_R423  */
1164         {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}},        /* CHIP_RV410 */
1165         { {0, 0}, {0, 0}, {0, 0}, {0, 0} },     /* CHIP_RS400 */
1166         { {0, 0}, {0, 0}, {0, 0}, {0, 0} },     /* CHIP_RS480 */
1167 };
1168
1169 bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder,
1170                                             struct radeon_encoder_int_tmds *tmds)
1171 {
1172         struct drm_device *dev = encoder->base.dev;
1173         struct radeon_device *rdev = dev->dev_private;
1174         int i;
1175
1176         for (i = 0; i < 4; i++) {
1177                 tmds->tmds_pll[i].value =
1178                         default_tmds_pll[rdev->family][i].value;
1179                 tmds->tmds_pll[i].freq = default_tmds_pll[rdev->family][i].freq;
1180         }
1181
1182         return true;
1183 }
1184
1185 bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder,
1186                                               struct radeon_encoder_int_tmds *tmds)
1187 {
1188         struct drm_device *dev = encoder->base.dev;
1189         struct radeon_device *rdev = dev->dev_private;
1190         uint16_t tmds_info;
1191         int i, n;
1192         uint8_t ver;
1193
1194         tmds_info = combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE);
1195
1196         if (tmds_info) {
1197                 ver = RBIOS8(tmds_info);
1198                 DRM_INFO("DFP table revision: %d\n", ver);
1199                 if (ver == 3) {
1200                         n = RBIOS8(tmds_info + 5) + 1;
1201                         if (n > 4)
1202                                 n = 4;
1203                         for (i = 0; i < n; i++) {
1204                                 tmds->tmds_pll[i].value =
1205                                     RBIOS32(tmds_info + i * 10 + 0x08);
1206                                 tmds->tmds_pll[i].freq =
1207                                     RBIOS16(tmds_info + i * 10 + 0x10);
1208                                 DRM_DEBUG("TMDS PLL From COMBIOS %u %x\n",
1209                                           tmds->tmds_pll[i].freq,
1210                                           tmds->tmds_pll[i].value);
1211                         }
1212                 } else if (ver == 4) {
1213                         int stride = 0;
1214                         n = RBIOS8(tmds_info + 5) + 1;
1215                         if (n > 4)
1216                                 n = 4;
1217                         for (i = 0; i < n; i++) {
1218                                 tmds->tmds_pll[i].value =
1219                                     RBIOS32(tmds_info + stride + 0x08);
1220                                 tmds->tmds_pll[i].freq =
1221                                     RBIOS16(tmds_info + stride + 0x10);
1222                                 if (i == 0)
1223                                         stride += 10;
1224                                 else
1225                                         stride += 6;
1226                                 DRM_DEBUG("TMDS PLL From COMBIOS %u %x\n",
1227                                           tmds->tmds_pll[i].freq,
1228                                           tmds->tmds_pll[i].value);
1229                         }
1230                 }
1231         } else {
1232                 DRM_INFO("No TMDS info found in BIOS\n");
1233                 return false;
1234         }
1235         return true;
1236 }
1237
1238 bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder,
1239                                                 struct radeon_encoder_ext_tmds *tmds)
1240 {
1241         struct drm_device *dev = encoder->base.dev;
1242         struct radeon_device *rdev = dev->dev_private;
1243         struct radeon_i2c_bus_rec i2c_bus;
1244
1245         /* default for macs */
1246         i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID);
1247         tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");
1248
1249         /* XXX some macs have duallink chips */
1250         switch (rdev->mode_info.connector_table) {
1251         case CT_POWERBOOK_EXTERNAL:
1252         case CT_MINI_EXTERNAL:
1253         default:
1254                 tmds->dvo_chip = DVO_SIL164;
1255                 tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */
1256                 break;
1257         }
1258
1259         return true;
1260 }
1261
1262 bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder,
1263                                                   struct radeon_encoder_ext_tmds *tmds)
1264 {
1265         struct drm_device *dev = encoder->base.dev;
1266         struct radeon_device *rdev = dev->dev_private;
1267         uint16_t offset;
1268         uint8_t ver, id, blocks, clk, data;
1269         int i;
1270         enum radeon_combios_ddc gpio;
1271         struct radeon_i2c_bus_rec i2c_bus;
1272
1273         tmds->i2c_bus = NULL;
1274         if (rdev->flags & RADEON_IS_IGP) {
1275                 offset = combios_get_table_offset(dev, COMBIOS_I2C_INFO_TABLE);
1276                 if (offset) {
1277                         ver = RBIOS8(offset);
1278                         DRM_INFO("GPIO Table revision: %d\n", ver);
1279                         blocks = RBIOS8(offset + 2);
1280                         for (i = 0; i < blocks; i++) {
1281                                 id = RBIOS8(offset + 3 + (i * 5) + 0);
1282                                 if (id == 136) {
1283                                         clk = RBIOS8(offset + 3 + (i * 5) + 3);
1284                                         data = RBIOS8(offset + 3 + (i * 5) + 4);
1285                                         i2c_bus.valid = true;
1286                                         i2c_bus.mask_clk_mask = (1 << clk);
1287                                         i2c_bus.mask_data_mask = (1 << data);
1288                                         i2c_bus.a_clk_mask = (1 << clk);
1289                                         i2c_bus.a_data_mask = (1 << data);
1290                                         i2c_bus.en_clk_mask = (1 << clk);
1291                                         i2c_bus.en_data_mask = (1 << data);
1292                                         i2c_bus.y_clk_mask = (1 << clk);
1293                                         i2c_bus.y_data_mask = (1 << data);
1294                                         i2c_bus.mask_clk_reg = RADEON_GPIOPAD_MASK;
1295                                         i2c_bus.mask_data_reg = RADEON_GPIOPAD_MASK;
1296                                         i2c_bus.a_clk_reg = RADEON_GPIOPAD_A;
1297                                         i2c_bus.a_data_reg = RADEON_GPIOPAD_A;
1298                                         i2c_bus.en_clk_reg = RADEON_GPIOPAD_EN;
1299                                         i2c_bus.en_data_reg = RADEON_GPIOPAD_EN;
1300                                         i2c_bus.y_clk_reg = RADEON_GPIOPAD_Y;
1301                                         i2c_bus.y_data_reg = RADEON_GPIOPAD_Y;
1302                                         tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");
1303                                         tmds->dvo_chip = DVO_SIL164;
1304                                         tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */
1305                                         break;
1306                                 }
1307                         }
1308                 }
1309         } else {
1310                 offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
1311                 if (offset) {
1312                         ver = RBIOS8(offset);
1313                         DRM_INFO("External TMDS Table revision: %d\n", ver);
1314                         tmds->slave_addr = RBIOS8(offset + 4 + 2);
1315                         tmds->slave_addr >>= 1; /* 7 bit addressing */
1316                         gpio = RBIOS8(offset + 4 + 3);
1317                         switch (gpio) {
1318                         case DDC_MONID:
1319                                 i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID);
1320                                 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");
1321                                 break;
1322                         case DDC_DVI:
1323                                 i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
1324                                 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");
1325                                 break;
1326                         case DDC_VGA:
1327                                 i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
1328                                 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");
1329                                 break;
1330                         case DDC_CRT2:
1331                                 /* R3xx+ chips don't have GPIO_CRT2_DDC gpio pad */
1332                                 if (rdev->family >= CHIP_R300)
1333                                         i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID);
1334                                 else
1335                                         i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC);
1336                                 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");
1337                                 break;
1338                         case DDC_LCD: /* MM i2c */
1339                                 i2c_bus.valid = true;
1340                                 i2c_bus.hw_capable = true;
1341                                 i2c_bus.mm_i2c = true;
1342                                 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");
1343                                 break;
1344                         default:
1345                                 DRM_ERROR("Unsupported gpio %d\n", gpio);
1346                                 break;
1347                         }
1348                 }
1349         }
1350
1351         if (!tmds->i2c_bus) {
1352                 DRM_INFO("No valid Ext TMDS info found in BIOS\n");
1353                 return false;
1354         }
1355
1356         return true;
1357 }
1358
1359 bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1360 {
1361         struct radeon_device *rdev = dev->dev_private;
1362         struct radeon_i2c_bus_rec ddc_i2c;
1363         struct radeon_hpd hpd;
1364
1365         rdev->mode_info.connector_table = radeon_connector_table;
1366         if (rdev->mode_info.connector_table == CT_NONE) {
1367 #ifdef CONFIG_PPC_PMAC
1368                 if (of_machine_is_compatible("PowerBook3,3")) {
1369                         /* powerbook with VGA */
1370                         rdev->mode_info.connector_table = CT_POWERBOOK_VGA;
1371                 } else if (of_machine_is_compatible("PowerBook3,4") ||
1372                            of_machine_is_compatible("PowerBook3,5")) {
1373                         /* powerbook with internal tmds */
1374                         rdev->mode_info.connector_table = CT_POWERBOOK_INTERNAL;
1375                 } else if (of_machine_is_compatible("PowerBook5,1") ||
1376                            of_machine_is_compatible("PowerBook5,2") ||
1377                            of_machine_is_compatible("PowerBook5,3") ||
1378                            of_machine_is_compatible("PowerBook5,4") ||
1379                            of_machine_is_compatible("PowerBook5,5")) {
1380                         /* powerbook with external single link tmds (sil164) */
1381                         rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1382                 } else if (of_machine_is_compatible("PowerBook5,6")) {
1383                         /* powerbook with external dual or single link tmds */
1384                         rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1385                 } else if (of_machine_is_compatible("PowerBook5,7") ||
1386                            of_machine_is_compatible("PowerBook5,8") ||
1387                            of_machine_is_compatible("PowerBook5,9")) {
1388                         /* PowerBook6,2 ? */
1389                         /* powerbook with external dual link tmds (sil1178?) */
1390                         rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1391                 } else if (of_machine_is_compatible("PowerBook4,1") ||
1392                            of_machine_is_compatible("PowerBook4,2") ||
1393                            of_machine_is_compatible("PowerBook4,3") ||
1394                            of_machine_is_compatible("PowerBook6,3") ||
1395                            of_machine_is_compatible("PowerBook6,5") ||
1396                            of_machine_is_compatible("PowerBook6,7")) {
1397                         /* ibook */
1398                         rdev->mode_info.connector_table = CT_IBOOK;
1399                 } else if (of_machine_is_compatible("PowerMac4,4")) {
1400                         /* emac */
1401                         rdev->mode_info.connector_table = CT_EMAC;
1402                 } else if (of_machine_is_compatible("PowerMac10,1")) {
1403                         /* mini with internal tmds */
1404                         rdev->mode_info.connector_table = CT_MINI_INTERNAL;
1405                 } else if (of_machine_is_compatible("PowerMac10,2")) {
1406                         /* mini with external tmds */
1407                         rdev->mode_info.connector_table = CT_MINI_EXTERNAL;
1408                 } else if (of_machine_is_compatible("PowerMac12,1")) {
1409                         /* PowerMac8,1 ? */
1410                         /* imac g5 isight */
1411                         rdev->mode_info.connector_table = CT_IMAC_G5_ISIGHT;
1412                 } else
1413 #endif /* CONFIG_PPC_PMAC */
1414                         rdev->mode_info.connector_table = CT_GENERIC;
1415         }
1416
1417         switch (rdev->mode_info.connector_table) {
1418         case CT_GENERIC:
1419                 DRM_INFO("Connector Table: %d (generic)\n",
1420                          rdev->mode_info.connector_table);
1421                 /* these are the most common settings */
1422                 if (rdev->flags & RADEON_SINGLE_CRTC) {
1423                         /* VGA - primary dac */
1424                         ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
1425                         hpd.hpd = RADEON_HPD_NONE;
1426                         radeon_add_legacy_encoder(dev,
1427                                                   radeon_get_encoder_id(dev,
1428                                                                         ATOM_DEVICE_CRT1_SUPPORT,
1429                                                                         1),
1430                                                   ATOM_DEVICE_CRT1_SUPPORT);
1431                         radeon_add_legacy_connector(dev, 0,
1432                                                     ATOM_DEVICE_CRT1_SUPPORT,
1433                                                     DRM_MODE_CONNECTOR_VGA,
1434                                                     &ddc_i2c,
1435                                                     CONNECTOR_OBJECT_ID_VGA,
1436                                                     &hpd);
1437                 } else if (rdev->flags & RADEON_IS_MOBILITY) {
1438                         /* LVDS */
1439                         ddc_i2c = combios_setup_i2c_bus(rdev, 0);
1440                         hpd.hpd = RADEON_HPD_NONE;
1441                         radeon_add_legacy_encoder(dev,
1442                                                   radeon_get_encoder_id(dev,
1443                                                                         ATOM_DEVICE_LCD1_SUPPORT,
1444                                                                         0),
1445                                                   ATOM_DEVICE_LCD1_SUPPORT);
1446                         radeon_add_legacy_connector(dev, 0,
1447                                                     ATOM_DEVICE_LCD1_SUPPORT,
1448                                                     DRM_MODE_CONNECTOR_LVDS,
1449                                                     &ddc_i2c,
1450                                                     CONNECTOR_OBJECT_ID_LVDS,
1451                                                     &hpd);
1452
1453                         /* VGA - primary dac */
1454                         ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
1455                         hpd.hpd = RADEON_HPD_NONE;
1456                         radeon_add_legacy_encoder(dev,
1457                                                   radeon_get_encoder_id(dev,
1458                                                                         ATOM_DEVICE_CRT1_SUPPORT,
1459                                                                         1),
1460                                                   ATOM_DEVICE_CRT1_SUPPORT);
1461                         radeon_add_legacy_connector(dev, 1,
1462                                                     ATOM_DEVICE_CRT1_SUPPORT,
1463                                                     DRM_MODE_CONNECTOR_VGA,
1464                                                     &ddc_i2c,
1465                                                     CONNECTOR_OBJECT_ID_VGA,
1466                                                     &hpd);
1467                 } else {
1468                         /* DVI-I - tv dac, int tmds */
1469                         ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
1470                         hpd.hpd = RADEON_HPD_1;
1471                         radeon_add_legacy_encoder(dev,
1472                                                   radeon_get_encoder_id(dev,
1473                                                                         ATOM_DEVICE_DFP1_SUPPORT,
1474                                                                         0),
1475                                                   ATOM_DEVICE_DFP1_SUPPORT);
1476                         radeon_add_legacy_encoder(dev,
1477                                                   radeon_get_encoder_id(dev,
1478                                                                         ATOM_DEVICE_CRT2_SUPPORT,
1479                                                                         2),
1480                                                   ATOM_DEVICE_CRT2_SUPPORT);
1481                         radeon_add_legacy_connector(dev, 0,
1482                                                     ATOM_DEVICE_DFP1_SUPPORT |
1483                                                     ATOM_DEVICE_CRT2_SUPPORT,
1484                                                     DRM_MODE_CONNECTOR_DVII,
1485                                                     &ddc_i2c,
1486                                                     CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1487                                                     &hpd);
1488
1489                         /* VGA - primary dac */
1490                         ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
1491                         hpd.hpd = RADEON_HPD_NONE;
1492                         radeon_add_legacy_encoder(dev,
1493                                                   radeon_get_encoder_id(dev,
1494                                                                         ATOM_DEVICE_CRT1_SUPPORT,
1495                                                                         1),
1496                                                   ATOM_DEVICE_CRT1_SUPPORT);
1497                         radeon_add_legacy_connector(dev, 1,
1498                                                     ATOM_DEVICE_CRT1_SUPPORT,
1499                                                     DRM_MODE_CONNECTOR_VGA,
1500                                                     &ddc_i2c,
1501                                                     CONNECTOR_OBJECT_ID_VGA,
1502                                                     &hpd);
1503                 }
1504
1505                 if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) {
1506                         /* TV - tv dac */
1507                         ddc_i2c.valid = false;
1508                         hpd.hpd = RADEON_HPD_NONE;
1509                         radeon_add_legacy_encoder(dev,
1510                                                   radeon_get_encoder_id(dev,
1511                                                                         ATOM_DEVICE_TV1_SUPPORT,
1512                                                                         2),
1513                                                   ATOM_DEVICE_TV1_SUPPORT);
1514                         radeon_add_legacy_connector(dev, 2,
1515                                                     ATOM_DEVICE_TV1_SUPPORT,
1516                                                     DRM_MODE_CONNECTOR_SVIDEO,
1517                                                     &ddc_i2c,
1518                                                     CONNECTOR_OBJECT_ID_SVIDEO,
1519                                                     &hpd);
1520                 }
1521                 break;
1522         case CT_IBOOK:
1523                 DRM_INFO("Connector Table: %d (ibook)\n",
1524                          rdev->mode_info.connector_table);
1525                 /* LVDS */
1526                 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
1527                 hpd.hpd = RADEON_HPD_NONE;
1528                 radeon_add_legacy_encoder(dev,
1529                                           radeon_get_encoder_id(dev,
1530                                                                 ATOM_DEVICE_LCD1_SUPPORT,
1531                                                                 0),
1532                                           ATOM_DEVICE_LCD1_SUPPORT);
1533                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1534                                             DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1535                                             CONNECTOR_OBJECT_ID_LVDS,
1536                                             &hpd);
1537                 /* VGA - TV DAC */
1538                 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
1539                 hpd.hpd = RADEON_HPD_NONE;
1540                 radeon_add_legacy_encoder(dev,
1541                                           radeon_get_encoder_id(dev,
1542                                                                 ATOM_DEVICE_CRT2_SUPPORT,
1543                                                                 2),
1544                                           ATOM_DEVICE_CRT2_SUPPORT);
1545                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1546                                             DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1547                                             CONNECTOR_OBJECT_ID_VGA,
1548                                             &hpd);
1549                 /* TV - TV DAC */
1550                 ddc_i2c.valid = false;
1551                 hpd.hpd = RADEON_HPD_NONE;
1552                 radeon_add_legacy_encoder(dev,
1553                                           radeon_get_encoder_id(dev,
1554                                                                 ATOM_DEVICE_TV1_SUPPORT,
1555                                                                 2),
1556                                           ATOM_DEVICE_TV1_SUPPORT);
1557                 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1558                                             DRM_MODE_CONNECTOR_SVIDEO,
1559                                             &ddc_i2c,
1560                                             CONNECTOR_OBJECT_ID_SVIDEO,
1561                                             &hpd);
1562                 break;
1563         case CT_POWERBOOK_EXTERNAL:
1564                 DRM_INFO("Connector Table: %d (powerbook external tmds)\n",
1565                          rdev->mode_info.connector_table);
1566                 /* LVDS */
1567                 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
1568                 hpd.hpd = RADEON_HPD_NONE;
1569                 radeon_add_legacy_encoder(dev,
1570                                           radeon_get_encoder_id(dev,
1571                                                                 ATOM_DEVICE_LCD1_SUPPORT,
1572                                                                 0),
1573                                           ATOM_DEVICE_LCD1_SUPPORT);
1574                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1575                                             DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1576                                             CONNECTOR_OBJECT_ID_LVDS,
1577                                             &hpd);
1578                 /* DVI-I - primary dac, ext tmds */
1579                 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
1580                 hpd.hpd = RADEON_HPD_2; /* ??? */
1581                 radeon_add_legacy_encoder(dev,
1582                                           radeon_get_encoder_id(dev,
1583                                                                 ATOM_DEVICE_DFP2_SUPPORT,
1584                                                                 0),
1585                                           ATOM_DEVICE_DFP2_SUPPORT);
1586                 radeon_add_legacy_encoder(dev,
1587                                           radeon_get_encoder_id(dev,
1588                                                                 ATOM_DEVICE_CRT1_SUPPORT,
1589                                                                 1),
1590                                           ATOM_DEVICE_CRT1_SUPPORT);
1591                 /* XXX some are SL */
1592                 radeon_add_legacy_connector(dev, 1,
1593                                             ATOM_DEVICE_DFP2_SUPPORT |
1594                                             ATOM_DEVICE_CRT1_SUPPORT,
1595                                             DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1596                                             CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I,
1597                                             &hpd);
1598                 /* TV - TV DAC */
1599                 ddc_i2c.valid = false;
1600                 hpd.hpd = RADEON_HPD_NONE;
1601                 radeon_add_legacy_encoder(dev,
1602                                           radeon_get_encoder_id(dev,
1603                                                                 ATOM_DEVICE_TV1_SUPPORT,
1604                                                                 2),
1605                                           ATOM_DEVICE_TV1_SUPPORT);
1606                 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1607                                             DRM_MODE_CONNECTOR_SVIDEO,
1608                                             &ddc_i2c,
1609                                             CONNECTOR_OBJECT_ID_SVIDEO,
1610                                             &hpd);
1611                 break;
1612         case CT_POWERBOOK_INTERNAL:
1613                 DRM_INFO("Connector Table: %d (powerbook internal tmds)\n",
1614                          rdev->mode_info.connector_table);
1615                 /* LVDS */
1616                 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
1617                 hpd.hpd = RADEON_HPD_NONE;
1618                 radeon_add_legacy_encoder(dev,
1619                                           radeon_get_encoder_id(dev,
1620                                                                 ATOM_DEVICE_LCD1_SUPPORT,
1621                                                                 0),
1622                                           ATOM_DEVICE_LCD1_SUPPORT);
1623                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1624                                             DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1625                                             CONNECTOR_OBJECT_ID_LVDS,
1626                                             &hpd);
1627                 /* DVI-I - primary dac, int tmds */
1628                 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
1629                 hpd.hpd = RADEON_HPD_1; /* ??? */
1630                 radeon_add_legacy_encoder(dev,
1631                                           radeon_get_encoder_id(dev,
1632                                                                 ATOM_DEVICE_DFP1_SUPPORT,
1633                                                                 0),
1634                                           ATOM_DEVICE_DFP1_SUPPORT);
1635                 radeon_add_legacy_encoder(dev,
1636                                           radeon_get_encoder_id(dev,
1637                                                                 ATOM_DEVICE_CRT1_SUPPORT,
1638                                                                 1),
1639                                           ATOM_DEVICE_CRT1_SUPPORT);
1640                 radeon_add_legacy_connector(dev, 1,
1641                                             ATOM_DEVICE_DFP1_SUPPORT |
1642                                             ATOM_DEVICE_CRT1_SUPPORT,
1643                                             DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1644                                             CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1645                                             &hpd);
1646                 /* TV - TV DAC */
1647                 ddc_i2c.valid = false;
1648                 hpd.hpd = RADEON_HPD_NONE;
1649                 radeon_add_legacy_encoder(dev,
1650                                           radeon_get_encoder_id(dev,
1651                                                                 ATOM_DEVICE_TV1_SUPPORT,
1652                                                                 2),
1653                                           ATOM_DEVICE_TV1_SUPPORT);
1654                 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1655                                             DRM_MODE_CONNECTOR_SVIDEO,
1656                                             &ddc_i2c,
1657                                             CONNECTOR_OBJECT_ID_SVIDEO,
1658                                             &hpd);
1659                 break;
1660         case CT_POWERBOOK_VGA:
1661                 DRM_INFO("Connector Table: %d (powerbook vga)\n",
1662                          rdev->mode_info.connector_table);
1663                 /* LVDS */
1664                 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
1665                 hpd.hpd = RADEON_HPD_NONE;
1666                 radeon_add_legacy_encoder(dev,
1667                                           radeon_get_encoder_id(dev,
1668                                                                 ATOM_DEVICE_LCD1_SUPPORT,
1669                                                                 0),
1670                                           ATOM_DEVICE_LCD1_SUPPORT);
1671                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1672                                             DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1673                                             CONNECTOR_OBJECT_ID_LVDS,
1674                                             &hpd);
1675                 /* VGA - primary dac */
1676                 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
1677                 hpd.hpd = RADEON_HPD_NONE;
1678                 radeon_add_legacy_encoder(dev,
1679                                           radeon_get_encoder_id(dev,
1680                                                                 ATOM_DEVICE_CRT1_SUPPORT,
1681                                                                 1),
1682                                           ATOM_DEVICE_CRT1_SUPPORT);
1683                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT1_SUPPORT,
1684                                             DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1685                                             CONNECTOR_OBJECT_ID_VGA,
1686                                             &hpd);
1687                 /* TV - TV DAC */
1688                 ddc_i2c.valid = false;
1689                 hpd.hpd = RADEON_HPD_NONE;
1690                 radeon_add_legacy_encoder(dev,
1691                                           radeon_get_encoder_id(dev,
1692                                                                 ATOM_DEVICE_TV1_SUPPORT,
1693                                                                 2),
1694                                           ATOM_DEVICE_TV1_SUPPORT);
1695                 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1696                                             DRM_MODE_CONNECTOR_SVIDEO,
1697                                             &ddc_i2c,
1698                                             CONNECTOR_OBJECT_ID_SVIDEO,
1699                                             &hpd);
1700                 break;
1701         case CT_MINI_EXTERNAL:
1702                 DRM_INFO("Connector Table: %d (mini external tmds)\n",
1703                          rdev->mode_info.connector_table);
1704                 /* DVI-I - tv dac, ext tmds */
1705                 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC);
1706                 hpd.hpd = RADEON_HPD_2; /* ??? */
1707                 radeon_add_legacy_encoder(dev,
1708                                           radeon_get_encoder_id(dev,
1709                                                                 ATOM_DEVICE_DFP2_SUPPORT,
1710                                                                 0),
1711                                           ATOM_DEVICE_DFP2_SUPPORT);
1712                 radeon_add_legacy_encoder(dev,
1713                                           radeon_get_encoder_id(dev,
1714                                                                 ATOM_DEVICE_CRT2_SUPPORT,
1715                                                                 2),
1716                                           ATOM_DEVICE_CRT2_SUPPORT);
1717                 /* XXX are any DL? */
1718                 radeon_add_legacy_connector(dev, 0,
1719                                             ATOM_DEVICE_DFP2_SUPPORT |
1720                                             ATOM_DEVICE_CRT2_SUPPORT,
1721                                             DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1722                                             CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1723                                             &hpd);
1724                 /* TV - TV DAC */
1725                 ddc_i2c.valid = false;
1726                 hpd.hpd = RADEON_HPD_NONE;
1727                 radeon_add_legacy_encoder(dev,
1728                                           radeon_get_encoder_id(dev,
1729                                                                 ATOM_DEVICE_TV1_SUPPORT,
1730                                                                 2),
1731                                           ATOM_DEVICE_TV1_SUPPORT);
1732                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT,
1733                                             DRM_MODE_CONNECTOR_SVIDEO,
1734                                             &ddc_i2c,
1735                                             CONNECTOR_OBJECT_ID_SVIDEO,
1736                                             &hpd);
1737                 break;
1738         case CT_MINI_INTERNAL:
1739                 DRM_INFO("Connector Table: %d (mini internal tmds)\n",
1740                          rdev->mode_info.connector_table);
1741                 /* DVI-I - tv dac, int tmds */
1742                 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC);
1743                 hpd.hpd = RADEON_HPD_1; /* ??? */
1744                 radeon_add_legacy_encoder(dev,
1745                                           radeon_get_encoder_id(dev,
1746                                                                 ATOM_DEVICE_DFP1_SUPPORT,
1747                                                                 0),
1748                                           ATOM_DEVICE_DFP1_SUPPORT);
1749                 radeon_add_legacy_encoder(dev,
1750                                           radeon_get_encoder_id(dev,
1751                                                                 ATOM_DEVICE_CRT2_SUPPORT,
1752                                                                 2),
1753                                           ATOM_DEVICE_CRT2_SUPPORT);
1754                 radeon_add_legacy_connector(dev, 0,
1755                                             ATOM_DEVICE_DFP1_SUPPORT |
1756                                             ATOM_DEVICE_CRT2_SUPPORT,
1757                                             DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1758                                             CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1759                                             &hpd);
1760                 /* TV - TV DAC */
1761                 ddc_i2c.valid = false;
1762                 hpd.hpd = RADEON_HPD_NONE;
1763                 radeon_add_legacy_encoder(dev,
1764                                           radeon_get_encoder_id(dev,
1765                                                                 ATOM_DEVICE_TV1_SUPPORT,
1766                                                                 2),
1767                                           ATOM_DEVICE_TV1_SUPPORT);
1768                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT,
1769                                             DRM_MODE_CONNECTOR_SVIDEO,
1770                                             &ddc_i2c,
1771                                             CONNECTOR_OBJECT_ID_SVIDEO,
1772                                             &hpd);
1773                 break;
1774         case CT_IMAC_G5_ISIGHT:
1775                 DRM_INFO("Connector Table: %d (imac g5 isight)\n",
1776                          rdev->mode_info.connector_table);
1777                 /* DVI-D - int tmds */
1778                 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID);
1779                 hpd.hpd = RADEON_HPD_1; /* ??? */
1780                 radeon_add_legacy_encoder(dev,
1781                                           radeon_get_encoder_id(dev,
1782                                                                 ATOM_DEVICE_DFP1_SUPPORT,
1783                                                                 0),
1784                                           ATOM_DEVICE_DFP1_SUPPORT);
1785                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_DFP1_SUPPORT,
1786                                             DRM_MODE_CONNECTOR_DVID, &ddc_i2c,
1787                                             CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D,
1788                                             &hpd);
1789                 /* VGA - tv dac */
1790                 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
1791                 hpd.hpd = RADEON_HPD_NONE;
1792                 radeon_add_legacy_encoder(dev,
1793                                           radeon_get_encoder_id(dev,
1794                                                                 ATOM_DEVICE_CRT2_SUPPORT,
1795                                                                 2),
1796                                           ATOM_DEVICE_CRT2_SUPPORT);
1797                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1798                                             DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1799                                             CONNECTOR_OBJECT_ID_VGA,
1800                                             &hpd);
1801                 /* TV - TV DAC */
1802                 ddc_i2c.valid = false;
1803                 hpd.hpd = RADEON_HPD_NONE;
1804                 radeon_add_legacy_encoder(dev,
1805                                           radeon_get_encoder_id(dev,
1806                                                                 ATOM_DEVICE_TV1_SUPPORT,
1807                                                                 2),
1808                                           ATOM_DEVICE_TV1_SUPPORT);
1809                 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1810                                             DRM_MODE_CONNECTOR_SVIDEO,
1811                                             &ddc_i2c,
1812                                             CONNECTOR_OBJECT_ID_SVIDEO,
1813                                             &hpd);
1814                 break;
1815         case CT_EMAC:
1816                 DRM_INFO("Connector Table: %d (emac)\n",
1817                          rdev->mode_info.connector_table);
1818                 /* VGA - primary dac */
1819                 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
1820                 hpd.hpd = RADEON_HPD_NONE;
1821                 radeon_add_legacy_encoder(dev,
1822                                           radeon_get_encoder_id(dev,
1823                                                                 ATOM_DEVICE_CRT1_SUPPORT,
1824                                                                 1),
1825                                           ATOM_DEVICE_CRT1_SUPPORT);
1826                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT,
1827                                             DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1828                                             CONNECTOR_OBJECT_ID_VGA,
1829                                             &hpd);
1830                 /* VGA - tv dac */
1831                 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC);
1832                 hpd.hpd = RADEON_HPD_NONE;
1833                 radeon_add_legacy_encoder(dev,
1834                                           radeon_get_encoder_id(dev,
1835                                                                 ATOM_DEVICE_CRT2_SUPPORT,
1836                                                                 2),
1837                                           ATOM_DEVICE_CRT2_SUPPORT);
1838                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1839                                             DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1840                                             CONNECTOR_OBJECT_ID_VGA,
1841                                             &hpd);
1842                 /* TV - TV DAC */
1843                 ddc_i2c.valid = false;
1844                 hpd.hpd = RADEON_HPD_NONE;
1845                 radeon_add_legacy_encoder(dev,
1846                                           radeon_get_encoder_id(dev,
1847                                                                 ATOM_DEVICE_TV1_SUPPORT,
1848                                                                 2),
1849                                           ATOM_DEVICE_TV1_SUPPORT);
1850                 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1851                                             DRM_MODE_CONNECTOR_SVIDEO,
1852                                             &ddc_i2c,
1853                                             CONNECTOR_OBJECT_ID_SVIDEO,
1854                                             &hpd);
1855                 break;
1856         default:
1857                 DRM_INFO("Connector table: %d (invalid)\n",
1858                          rdev->mode_info.connector_table);
1859                 return false;
1860         }
1861
1862         radeon_link_encoder_connector(dev);
1863
1864         return true;
1865 }
1866
1867 static bool radeon_apply_legacy_quirks(struct drm_device *dev,
1868                                        int bios_index,
1869                                        enum radeon_combios_connector
1870                                        *legacy_connector,
1871                                        struct radeon_i2c_bus_rec *ddc_i2c,
1872                                        struct radeon_hpd *hpd)
1873 {
1874         struct radeon_device *rdev = dev->dev_private;
1875
1876         /* XPRESS DDC quirks */
1877         if ((rdev->family == CHIP_RS400 ||
1878              rdev->family == CHIP_RS480) &&
1879             ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC)
1880                 *ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID);
1881         else if ((rdev->family == CHIP_RS400 ||
1882                   rdev->family == CHIP_RS480) &&
1883                  ddc_i2c->mask_clk_reg == RADEON_GPIO_MONID) {
1884                 *ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIOPAD_MASK);
1885                 ddc_i2c->mask_clk_mask = (0x20 << 8);
1886                 ddc_i2c->mask_data_mask = 0x80;
1887                 ddc_i2c->a_clk_mask = (0x20 << 8);
1888                 ddc_i2c->a_data_mask = 0x80;
1889                 ddc_i2c->en_clk_mask = (0x20 << 8);
1890                 ddc_i2c->en_data_mask = 0x80;
1891                 ddc_i2c->y_clk_mask = (0x20 << 8);
1892                 ddc_i2c->y_data_mask = 0x80;
1893         }
1894
1895         /* R3xx+ chips don't have GPIO_CRT2_DDC gpio pad */
1896         if ((rdev->family >= CHIP_R300) &&
1897             ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC)
1898                 *ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
1899
1900         /* Certain IBM chipset RN50s have a BIOS reporting two VGAs,
1901            one with VGA DDC and one with CRT2 DDC. - kill the CRT2 DDC one */
1902         if (dev->pdev->device == 0x515e &&
1903             dev->pdev->subsystem_vendor == 0x1014) {
1904                 if (*legacy_connector == CONNECTOR_CRT_LEGACY &&
1905                     ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC)
1906                         return false;
1907         }
1908
1909         /* Some RV100 cards with 2 VGA ports show up with DVI+VGA */
1910         if (dev->pdev->device == 0x5159 &&
1911             dev->pdev->subsystem_vendor == 0x1002 &&
1912             dev->pdev->subsystem_device == 0x013a) {
1913                 if (*legacy_connector == CONNECTOR_DVI_I_LEGACY)
1914                         *legacy_connector = CONNECTOR_CRT_LEGACY;
1915
1916         }
1917
1918         /* X300 card with extra non-existent DVI port */
1919         if (dev->pdev->device == 0x5B60 &&
1920             dev->pdev->subsystem_vendor == 0x17af &&
1921             dev->pdev->subsystem_device == 0x201e && bios_index == 2) {
1922                 if (*legacy_connector == CONNECTOR_DVI_I_LEGACY)
1923                         return false;
1924         }
1925
1926         return true;
1927 }
1928
1929 static bool radeon_apply_legacy_tv_quirks(struct drm_device *dev)
1930 {
1931         /* Acer 5102 has non-existent TV port */
1932         if (dev->pdev->device == 0x5975 &&
1933             dev->pdev->subsystem_vendor == 0x1025 &&
1934             dev->pdev->subsystem_device == 0x009f)
1935                 return false;
1936
1937         /* HP dc5750 has non-existent TV port */
1938         if (dev->pdev->device == 0x5974 &&
1939             dev->pdev->subsystem_vendor == 0x103c &&
1940             dev->pdev->subsystem_device == 0x280a)
1941                 return false;
1942
1943         /* MSI S270 has non-existent TV port */
1944         if (dev->pdev->device == 0x5955 &&
1945             dev->pdev->subsystem_vendor == 0x1462 &&
1946             dev->pdev->subsystem_device == 0x0131)
1947                 return false;
1948
1949         return true;
1950 }
1951
1952 static uint16_t combios_check_dl_dvi(struct drm_device *dev, int is_dvi_d)
1953 {
1954         struct radeon_device *rdev = dev->dev_private;
1955         uint32_t ext_tmds_info;
1956
1957         if (rdev->flags & RADEON_IS_IGP) {
1958                 if (is_dvi_d)
1959                         return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
1960                 else
1961                         return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
1962         }
1963         ext_tmds_info = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
1964         if (ext_tmds_info) {
1965                 uint8_t rev = RBIOS8(ext_tmds_info);
1966                 uint8_t flags = RBIOS8(ext_tmds_info + 4 + 5);
1967                 if (rev >= 3) {
1968                         if (is_dvi_d)
1969                                 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
1970                         else
1971                                 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
1972                 } else {
1973                         if (flags & 1) {
1974                                 if (is_dvi_d)
1975                                         return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
1976                                 else
1977                                         return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
1978                         }
1979                 }
1980         }
1981         if (is_dvi_d)
1982                 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
1983         else
1984                 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
1985 }
1986
1987 bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev)
1988 {
1989         struct radeon_device *rdev = dev->dev_private;
1990         uint32_t conn_info, entry, devices;
1991         uint16_t tmp, connector_object_id;
1992         enum radeon_combios_ddc ddc_type;
1993         enum radeon_combios_connector connector;
1994         int i = 0;
1995         struct radeon_i2c_bus_rec ddc_i2c;
1996         struct radeon_hpd hpd;
1997
1998         conn_info = combios_get_table_offset(dev, COMBIOS_CONNECTOR_INFO_TABLE);
1999         if (conn_info) {
2000                 for (i = 0; i < 4; i++) {
2001                         entry = conn_info + 2 + i * 2;
2002
2003                         if (!RBIOS16(entry))
2004                                 break;
2005
2006                         tmp = RBIOS16(entry);
2007
2008                         connector = (tmp >> 12) & 0xf;
2009
2010                         ddc_type = (tmp >> 8) & 0xf;
2011                         switch (ddc_type) {
2012                         case DDC_MONID:
2013                                 ddc_i2c =
2014                                         combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID);
2015                                 break;
2016                         case DDC_DVI:
2017                                 ddc_i2c =
2018                                         combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
2019                                 break;
2020                         case DDC_VGA:
2021                                 ddc_i2c =
2022                                         combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
2023                                 break;
2024                         case DDC_CRT2:
2025                                 ddc_i2c =
2026                                         combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC);
2027                                 break;
2028                         default:
2029                                 ddc_i2c.valid = false;
2030                                 break;
2031                         }
2032
2033                         switch (connector) {
2034                         case CONNECTOR_PROPRIETARY_LEGACY:
2035                         case CONNECTOR_DVI_I_LEGACY:
2036                         case CONNECTOR_DVI_D_LEGACY:
2037                                 if ((tmp >> 4) & 0x1)
2038                                         hpd.hpd = RADEON_HPD_2;
2039                                 else
2040                                         hpd.hpd = RADEON_HPD_1;
2041                                 break;
2042                         default:
2043                                 hpd.hpd = RADEON_HPD_NONE;
2044                                 break;
2045                         }
2046
2047                         if (!radeon_apply_legacy_quirks(dev, i, &connector,
2048                                                         &ddc_i2c, &hpd))
2049                                 continue;
2050
2051                         switch (connector) {
2052                         case CONNECTOR_PROPRIETARY_LEGACY:
2053                                 if ((tmp >> 4) & 0x1)
2054                                         devices = ATOM_DEVICE_DFP2_SUPPORT;
2055                                 else
2056                                         devices = ATOM_DEVICE_DFP1_SUPPORT;
2057                                 radeon_add_legacy_encoder(dev,
2058                                                           radeon_get_encoder_id
2059                                                           (dev, devices, 0),
2060                                                           devices);
2061                                 radeon_add_legacy_connector(dev, i, devices,
2062                                                             legacy_connector_convert
2063                                                             [connector],
2064                                                             &ddc_i2c,
2065                                                             CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D,
2066                                                             &hpd);
2067                                 break;
2068                         case CONNECTOR_CRT_LEGACY:
2069                                 if (tmp & 0x1) {
2070                                         devices = ATOM_DEVICE_CRT2_SUPPORT;
2071                                         radeon_add_legacy_encoder(dev,
2072                                                                   radeon_get_encoder_id
2073                                                                   (dev,
2074                                                                    ATOM_DEVICE_CRT2_SUPPORT,
2075                                                                    2),
2076                                                                   ATOM_DEVICE_CRT2_SUPPORT);
2077                                 } else {
2078                                         devices = ATOM_DEVICE_CRT1_SUPPORT;
2079                                         radeon_add_legacy_encoder(dev,
2080                                                                   radeon_get_encoder_id
2081                                                                   (dev,
2082                                                                    ATOM_DEVICE_CRT1_SUPPORT,
2083                                                                    1),
2084                                                                   ATOM_DEVICE_CRT1_SUPPORT);
2085                                 }
2086                                 radeon_add_legacy_connector(dev,
2087                                                             i,
2088                                                             devices,
2089                                                             legacy_connector_convert
2090                                                             [connector],
2091                                                             &ddc_i2c,
2092                                                             CONNECTOR_OBJECT_ID_VGA,
2093                                                             &hpd);
2094                                 break;
2095                         case CONNECTOR_DVI_I_LEGACY:
2096                                 devices = 0;
2097                                 if (tmp & 0x1) {
2098                                         devices |= ATOM_DEVICE_CRT2_SUPPORT;
2099                                         radeon_add_legacy_encoder(dev,
2100                                                                   radeon_get_encoder_id
2101                                                                   (dev,
2102                                                                    ATOM_DEVICE_CRT2_SUPPORT,
2103                                                                    2),
2104                                                                   ATOM_DEVICE_CRT2_SUPPORT);
2105                                 } else {
2106                                         devices |= ATOM_DEVICE_CRT1_SUPPORT;
2107                                         radeon_add_legacy_encoder(dev,
2108                                                                   radeon_get_encoder_id
2109                                                                   (dev,
2110                                                                    ATOM_DEVICE_CRT1_SUPPORT,
2111                                                                    1),
2112                                                                   ATOM_DEVICE_CRT1_SUPPORT);
2113                                 }
2114                                 if ((tmp >> 4) & 0x1) {
2115                                         devices |= ATOM_DEVICE_DFP2_SUPPORT;
2116                                         radeon_add_legacy_encoder(dev,
2117                                                                   radeon_get_encoder_id
2118                                                                   (dev,
2119                                                                    ATOM_DEVICE_DFP2_SUPPORT,
2120                                                                    0),
2121                                                                   ATOM_DEVICE_DFP2_SUPPORT);
2122                                         connector_object_id = combios_check_dl_dvi(dev, 0);
2123                                 } else {
2124                                         devices |= ATOM_DEVICE_DFP1_SUPPORT;
2125                                         radeon_add_legacy_encoder(dev,
2126                                                                   radeon_get_encoder_id
2127                                                                   (dev,
2128                                                                    ATOM_DEVICE_DFP1_SUPPORT,
2129                                                                    0),
2130                                                                   ATOM_DEVICE_DFP1_SUPPORT);
2131                                         connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2132                                 }
2133                                 radeon_add_legacy_connector(dev,
2134                                                             i,
2135                                                             devices,
2136                                                             legacy_connector_convert
2137                                                             [connector],
2138                                                             &ddc_i2c,
2139                                                             connector_object_id,
2140                                                             &hpd);
2141                                 break;
2142                         case CONNECTOR_DVI_D_LEGACY:
2143                                 if ((tmp >> 4) & 0x1) {
2144                                         devices = ATOM_DEVICE_DFP2_SUPPORT;
2145                                         connector_object_id = combios_check_dl_dvi(dev, 1);
2146                                 } else {
2147                                         devices = ATOM_DEVICE_DFP1_SUPPORT;
2148                                         connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2149                                 }
2150                                 radeon_add_legacy_encoder(dev,
2151                                                           radeon_get_encoder_id
2152                                                           (dev, devices, 0),
2153                                                           devices);
2154                                 radeon_add_legacy_connector(dev, i, devices,
2155                                                             legacy_connector_convert
2156                                                             [connector],
2157                                                             &ddc_i2c,
2158                                                             connector_object_id,
2159                                                             &hpd);
2160                                 break;
2161                         case CONNECTOR_CTV_LEGACY:
2162                         case CONNECTOR_STV_LEGACY:
2163                                 radeon_add_legacy_encoder(dev,
2164                                                           radeon_get_encoder_id
2165                                                           (dev,
2166                                                            ATOM_DEVICE_TV1_SUPPORT,
2167                                                            2),
2168                                                           ATOM_DEVICE_TV1_SUPPORT);
2169                                 radeon_add_legacy_connector(dev, i,
2170                                                             ATOM_DEVICE_TV1_SUPPORT,
2171                                                             legacy_connector_convert
2172                                                             [connector],
2173                                                             &ddc_i2c,
2174                                                             CONNECTOR_OBJECT_ID_SVIDEO,
2175                                                             &hpd);
2176                                 break;
2177                         default:
2178                                 DRM_ERROR("Unknown connector type: %d\n",
2179                                           connector);
2180                                 continue;
2181                         }
2182
2183                 }
2184         } else {
2185                 uint16_t tmds_info =
2186                     combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE);
2187                 if (tmds_info) {
2188                         DRM_DEBUG("Found DFP table, assuming DVI connector\n");
2189
2190                         radeon_add_legacy_encoder(dev,
2191                                                   radeon_get_encoder_id(dev,
2192                                                                         ATOM_DEVICE_CRT1_SUPPORT,
2193                                                                         1),
2194                                                   ATOM_DEVICE_CRT1_SUPPORT);
2195                         radeon_add_legacy_encoder(dev,
2196                                                   radeon_get_encoder_id(dev,
2197                                                                         ATOM_DEVICE_DFP1_SUPPORT,
2198                                                                         0),
2199                                                   ATOM_DEVICE_DFP1_SUPPORT);
2200
2201                         ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
2202                         hpd.hpd = RADEON_HPD_1;
2203                         radeon_add_legacy_connector(dev,
2204                                                     0,
2205                                                     ATOM_DEVICE_CRT1_SUPPORT |
2206                                                     ATOM_DEVICE_DFP1_SUPPORT,
2207                                                     DRM_MODE_CONNECTOR_DVII,
2208                                                     &ddc_i2c,
2209                                                     CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2210                                                     &hpd);
2211                 } else {
2212                         uint16_t crt_info =
2213                                 combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
2214                         DRM_DEBUG("Found CRT table, assuming VGA connector\n");
2215                         if (crt_info) {
2216                                 radeon_add_legacy_encoder(dev,
2217                                                           radeon_get_encoder_id(dev,
2218                                                                                 ATOM_DEVICE_CRT1_SUPPORT,
2219                                                                                 1),
2220                                                           ATOM_DEVICE_CRT1_SUPPORT);
2221                                 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
2222                                 hpd.hpd = RADEON_HPD_NONE;
2223                                 radeon_add_legacy_connector(dev,
2224                                                             0,
2225                                                             ATOM_DEVICE_CRT1_SUPPORT,
2226                                                             DRM_MODE_CONNECTOR_VGA,
2227                                                             &ddc_i2c,
2228                                                             CONNECTOR_OBJECT_ID_VGA,
2229                                                             &hpd);
2230                         } else {
2231                                 DRM_DEBUG("No connector info found\n");
2232                                 return false;
2233                         }
2234                 }
2235         }
2236
2237         if (rdev->flags & RADEON_IS_MOBILITY || rdev->flags & RADEON_IS_IGP) {
2238                 uint16_t lcd_info =
2239                     combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);
2240                 if (lcd_info) {
2241                         uint16_t lcd_ddc_info =
2242                             combios_get_table_offset(dev,
2243                                                      COMBIOS_LCD_DDC_INFO_TABLE);
2244
2245                         radeon_add_legacy_encoder(dev,
2246                                                   radeon_get_encoder_id(dev,
2247                                                                         ATOM_DEVICE_LCD1_SUPPORT,
2248                                                                         0),
2249                                                   ATOM_DEVICE_LCD1_SUPPORT);
2250
2251                         if (lcd_ddc_info) {
2252                                 ddc_type = RBIOS8(lcd_ddc_info + 2);
2253                                 switch (ddc_type) {
2254                                 case DDC_MONID:
2255                                         ddc_i2c =
2256                                             combios_setup_i2c_bus
2257                                                 (rdev, RADEON_GPIO_MONID);
2258                                         break;
2259                                 case DDC_DVI:
2260                                         ddc_i2c =
2261                                             combios_setup_i2c_bus
2262                                                 (rdev, RADEON_GPIO_DVI_DDC);
2263                                         break;
2264                                 case DDC_VGA:
2265                                         ddc_i2c =
2266                                             combios_setup_i2c_bus
2267                                                 (rdev, RADEON_GPIO_VGA_DDC);
2268                                         break;
2269                                 case DDC_CRT2:
2270                                         ddc_i2c =
2271                                             combios_setup_i2c_bus
2272                                                 (rdev, RADEON_GPIO_CRT2_DDC);
2273                                         break;
2274                                 case DDC_LCD:
2275                                         ddc_i2c =
2276                                             combios_setup_i2c_bus
2277                                                 (rdev, RADEON_GPIOPAD_MASK);
2278                                         ddc_i2c.mask_clk_mask =
2279                                             RBIOS32(lcd_ddc_info + 3);
2280                                         ddc_i2c.mask_data_mask =
2281                                             RBIOS32(lcd_ddc_info + 7);
2282                                         ddc_i2c.a_clk_mask =
2283                                             RBIOS32(lcd_ddc_info + 3);
2284                                         ddc_i2c.a_data_mask =
2285                                             RBIOS32(lcd_ddc_info + 7);
2286                                         ddc_i2c.en_clk_mask =
2287                                             RBIOS32(lcd_ddc_info + 3);
2288                                         ddc_i2c.en_data_mask =
2289                                             RBIOS32(lcd_ddc_info + 7);
2290                                         ddc_i2c.y_clk_mask =
2291                                             RBIOS32(lcd_ddc_info + 3);
2292                                         ddc_i2c.y_data_mask =
2293                                             RBIOS32(lcd_ddc_info + 7);
2294                                         break;
2295                                 case DDC_GPIO:
2296                                         ddc_i2c =
2297                                             combios_setup_i2c_bus
2298                                                 (rdev, RADEON_MDGPIO_MASK);
2299                                         ddc_i2c.mask_clk_mask =
2300                                             RBIOS32(lcd_ddc_info + 3);
2301                                         ddc_i2c.mask_data_mask =
2302                                             RBIOS32(lcd_ddc_info + 7);
2303                                         ddc_i2c.a_clk_mask =
2304                                             RBIOS32(lcd_ddc_info + 3);
2305                                         ddc_i2c.a_data_mask =
2306                                             RBIOS32(lcd_ddc_info + 7);
2307                                         ddc_i2c.en_clk_mask =
2308                                             RBIOS32(lcd_ddc_info + 3);
2309                                         ddc_i2c.en_data_mask =
2310                                             RBIOS32(lcd_ddc_info + 7);
2311                                         ddc_i2c.y_clk_mask =
2312                                             RBIOS32(lcd_ddc_info + 3);
2313                                         ddc_i2c.y_data_mask =
2314                                             RBIOS32(lcd_ddc_info + 7);
2315                                         break;
2316                                 default:
2317                                         ddc_i2c.valid = false;
2318                                         break;
2319                                 }
2320                                 DRM_DEBUG("LCD DDC Info Table found!\n");
2321                         } else
2322                                 ddc_i2c.valid = false;
2323
2324                         hpd.hpd = RADEON_HPD_NONE;
2325                         radeon_add_legacy_connector(dev,
2326                                                     5,
2327                                                     ATOM_DEVICE_LCD1_SUPPORT,
2328                                                     DRM_MODE_CONNECTOR_LVDS,
2329                                                     &ddc_i2c,
2330                                                     CONNECTOR_OBJECT_ID_LVDS,
2331                                                     &hpd);
2332                 }
2333         }
2334
2335         /* check TV table */
2336         if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) {
2337                 uint32_t tv_info =
2338                     combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
2339                 if (tv_info) {
2340                         if (RBIOS8(tv_info + 6) == 'T') {
2341                                 if (radeon_apply_legacy_tv_quirks(dev)) {
2342                                         hpd.hpd = RADEON_HPD_NONE;
2343                                         ddc_i2c.valid = false;
2344                                         radeon_add_legacy_encoder(dev,
2345                                                                   radeon_get_encoder_id
2346                                                                   (dev,
2347                                                                    ATOM_DEVICE_TV1_SUPPORT,
2348                                                                    2),
2349                                                                   ATOM_DEVICE_TV1_SUPPORT);
2350                                         radeon_add_legacy_connector(dev, 6,
2351                                                                     ATOM_DEVICE_TV1_SUPPORT,
2352                                                                     DRM_MODE_CONNECTOR_SVIDEO,
2353                                                                     &ddc_i2c,
2354                                                                     CONNECTOR_OBJECT_ID_SVIDEO,
2355                                                                     &hpd);
2356                                 }
2357                         }
2358                 }
2359         }
2360
2361         radeon_link_encoder_connector(dev);
2362
2363         return true;
2364 }
2365
2366 void radeon_combios_get_power_modes(struct radeon_device *rdev)
2367 {
2368         struct drm_device *dev = rdev->ddev;
2369         u16 offset, misc, misc2 = 0;
2370         u8 rev, blocks, tmp;
2371         int state_index = 0;
2372
2373         rdev->pm.default_power_state_index = -1;
2374
2375         if (rdev->flags & RADEON_IS_MOBILITY) {
2376                 offset = combios_get_table_offset(dev, COMBIOS_POWERPLAY_INFO_TABLE);
2377                 if (offset) {
2378                         rev = RBIOS8(offset);
2379                         blocks = RBIOS8(offset + 0x2);
2380                         /* power mode 0 tends to be the only valid one */
2381                         rdev->pm.power_state[state_index].num_clock_modes = 1;
2382                         rdev->pm.power_state[state_index].clock_info[0].mclk = RBIOS32(offset + 0x5 + 0x2);
2383                         rdev->pm.power_state[state_index].clock_info[0].sclk = RBIOS32(offset + 0x5 + 0x6);
2384                         if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2385                             (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2386                                 goto default_mode;
2387                         rdev->pm.power_state[state_index].type =
2388                                 POWER_STATE_TYPE_BATTERY;
2389                         misc = RBIOS16(offset + 0x5 + 0x0);
2390                         if (rev > 4)
2391                                 misc2 = RBIOS16(offset + 0x5 + 0xe);
2392                         rdev->pm.power_state[state_index].misc = misc;
2393                         rdev->pm.power_state[state_index].misc2 = misc2;
2394                         if (misc & 0x4) {
2395                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_GPIO;
2396                                 if (misc & 0x8)
2397                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2398                                                 true;
2399                                 else
2400                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2401                                                 false;
2402                                 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.valid = true;
2403                                 if (rev < 6) {
2404                                         rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.reg =
2405                                                 RBIOS16(offset + 0x5 + 0xb) * 4;
2406                                         tmp = RBIOS8(offset + 0x5 + 0xd);
2407                                         rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp);
2408                                 } else {
2409                                         u8 entries = RBIOS8(offset + 0x5 + 0xb);
2410                                         u16 voltage_table_offset = RBIOS16(offset + 0x5 + 0xc);
2411                                         if (entries && voltage_table_offset) {
2412                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.reg =
2413                                                         RBIOS16(voltage_table_offset) * 4;
2414                                                 tmp = RBIOS8(voltage_table_offset + 0x2);
2415                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp);
2416                                         } else
2417                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.valid = false;
2418                                 }
2419                                 switch ((misc2 & 0x700) >> 8) {
2420                                 case 0:
2421                                 default:
2422                                         rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 0;
2423                                         break;
2424                                 case 1:
2425                                         rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 33;
2426                                         break;
2427                                 case 2:
2428                                         rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 66;
2429                                         break;
2430                                 case 3:
2431                                         rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 99;
2432                                         break;
2433                                 case 4:
2434                                         rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 132;
2435                                         break;
2436                                 }
2437                         } else
2438                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2439                         if (rev > 6)
2440                                 rdev->pm.power_state[state_index].pcie_lanes =
2441                                         RBIOS8(offset + 0x5 + 0x10);
2442                         rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2443                         state_index++;
2444                 } else {
2445                         /* XXX figure out some good default low power mode for mobility cards w/out power tables */
2446                 }
2447         } else {
2448                 /* XXX figure out some good default low power mode for desktop cards */
2449         }
2450
2451 default_mode:
2452         /* add the default mode */
2453         rdev->pm.power_state[state_index].type =
2454                 POWER_STATE_TYPE_DEFAULT;
2455         rdev->pm.power_state[state_index].num_clock_modes = 1;
2456         rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
2457         rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
2458         rdev->pm.power_state[state_index].default_clock_mode = &rdev->pm.power_state[state_index].clock_info[0];
2459         if ((state_index > 0) &&
2460             (rdev->pm.power_state[0].clock_info[0].voltage.type == VOLTAGE_GPIO))
2461                 rdev->pm.power_state[state_index].clock_info[0].voltage =
2462                         rdev->pm.power_state[0].clock_info[0].voltage;
2463         else
2464                 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2465         rdev->pm.power_state[state_index].pcie_lanes = 16;
2466         rdev->pm.power_state[state_index].flags = 0;
2467         rdev->pm.default_power_state_index = state_index;
2468         rdev->pm.num_power_states = state_index + 1;
2469
2470         rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
2471         rdev->pm.current_clock_mode_index = 0;
2472 }
2473
2474 void radeon_external_tmds_setup(struct drm_encoder *encoder)
2475 {
2476         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2477         struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv;
2478
2479         if (!tmds)
2480                 return;
2481
2482         switch (tmds->dvo_chip) {
2483         case DVO_SIL164:
2484                 /* sil 164 */
2485                 radeon_i2c_put_byte(tmds->i2c_bus,
2486                                     tmds->slave_addr,
2487                                     0x08, 0x30);
2488                 radeon_i2c_put_byte(tmds->i2c_bus,
2489                                        tmds->slave_addr,
2490                                        0x09, 0x00);
2491                 radeon_i2c_put_byte(tmds->i2c_bus,
2492                                     tmds->slave_addr,
2493                                     0x0a, 0x90);
2494                 radeon_i2c_put_byte(tmds->i2c_bus,
2495                                     tmds->slave_addr,
2496                                     0x0c, 0x89);
2497                 radeon_i2c_put_byte(tmds->i2c_bus,
2498                                        tmds->slave_addr,
2499                                        0x08, 0x3b);
2500                 break;
2501         case DVO_SIL1178:
2502                 /* sil 1178 - untested */
2503                 /*
2504                  * 0x0f, 0x44
2505                  * 0x0f, 0x4c
2506                  * 0x0e, 0x01
2507                  * 0x0a, 0x80
2508                  * 0x09, 0x30
2509                  * 0x0c, 0xc9
2510                  * 0x0d, 0x70
2511                  * 0x08, 0x32
2512                  * 0x08, 0x33
2513                  */
2514                 break;
2515         default:
2516                 break;
2517         }
2518
2519 }
2520
2521 bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder)
2522 {
2523         struct drm_device *dev = encoder->dev;
2524         struct radeon_device *rdev = dev->dev_private;
2525         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2526         uint16_t offset;
2527         uint8_t blocks, slave_addr, rev;
2528         uint32_t index, id;
2529         uint32_t reg, val, and_mask, or_mask;
2530         struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv;
2531
2532         if (!tmds)
2533                 return false;
2534
2535         if (rdev->flags & RADEON_IS_IGP) {
2536                 offset = combios_get_table_offset(dev, COMBIOS_TMDS_POWER_ON_TABLE);
2537                 rev = RBIOS8(offset);
2538                 if (offset) {
2539                         rev = RBIOS8(offset);
2540                         if (rev > 1) {
2541                                 blocks = RBIOS8(offset + 3);
2542                                 index = offset + 4;
2543                                 while (blocks > 0) {
2544                                         id = RBIOS16(index);
2545                                         index += 2;
2546                                         switch (id >> 13) {
2547                                         case 0:
2548                                                 reg = (id & 0x1fff) * 4;
2549                                                 val = RBIOS32(index);
2550                                                 index += 4;
2551                                                 WREG32(reg, val);
2552                                                 break;
2553                                         case 2:
2554                                                 reg = (id & 0x1fff) * 4;
2555                                                 and_mask = RBIOS32(index);
2556                                                 index += 4;
2557                                                 or_mask = RBIOS32(index);
2558                                                 index += 4;
2559                                                 val = RREG32(reg);
2560                                                 val = (val & and_mask) | or_mask;
2561                                                 WREG32(reg, val);
2562                                                 break;
2563                                         case 3:
2564                                                 val = RBIOS16(index);
2565                                                 index += 2;
2566                                                 udelay(val);
2567                                                 break;
2568                                         case 4:
2569                                                 val = RBIOS16(index);
2570                                                 index += 2;
2571                                                 udelay(val * 1000);
2572                                                 break;
2573                                         case 6:
2574                                                 slave_addr = id & 0xff;
2575                                                 slave_addr >>= 1; /* 7 bit addressing */
2576                                                 index++;
2577                                                 reg = RBIOS8(index);
2578                                                 index++;
2579                                                 val = RBIOS8(index);
2580                                                 index++;
2581                                                 radeon_i2c_put_byte(tmds->i2c_bus,
2582                                                                     slave_addr,
2583                                                                     reg, val);
2584                                                 break;
2585                                         default:
2586                                                 DRM_ERROR("Unknown id %d\n", id >> 13);
2587                                                 break;
2588                                         }
2589                                         blocks--;
2590                                 }
2591                                 return true;
2592                         }
2593                 }
2594         } else {
2595                 offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
2596                 if (offset) {
2597                         index = offset + 10;
2598                         id = RBIOS16(index);
2599                         while (id != 0xffff) {
2600                                 index += 2;
2601                                 switch (id >> 13) {
2602                                 case 0:
2603                                         reg = (id & 0x1fff) * 4;
2604                                         val = RBIOS32(index);
2605                                         WREG32(reg, val);
2606                                         break;
2607                                 case 2:
2608                                         reg = (id & 0x1fff) * 4;
2609                                         and_mask = RBIOS32(index);
2610                                         index += 4;
2611                                         or_mask = RBIOS32(index);
2612                                         index += 4;
2613                                         val = RREG32(reg);
2614                                         val = (val & and_mask) | or_mask;
2615                                         WREG32(reg, val);
2616                                         break;
2617                                 case 4:
2618                                         val = RBIOS16(index);
2619                                         index += 2;
2620                                         udelay(val);
2621                                         break;
2622                                 case 5:
2623                                         reg = id & 0x1fff;
2624                                         and_mask = RBIOS32(index);
2625                                         index += 4;
2626                                         or_mask = RBIOS32(index);
2627                                         index += 4;
2628                                         val = RREG32_PLL(reg);
2629                                         val = (val & and_mask) | or_mask;
2630                                         WREG32_PLL(reg, val);
2631                                         break;
2632                                 case 6:
2633                                         reg = id & 0x1fff;
2634                                         val = RBIOS8(index);
2635                                         index += 1;
2636                                         radeon_i2c_put_byte(tmds->i2c_bus,
2637                                                             tmds->slave_addr,
2638                                                             reg, val);
2639                                         break;
2640                                 default:
2641                                         DRM_ERROR("Unknown id %d\n", id >> 13);
2642                                         break;
2643                                 }
2644                                 id = RBIOS16(index);
2645                         }
2646                         return true;
2647                 }
2648         }
2649         return false;
2650 }
2651
2652 static void combios_parse_mmio_table(struct drm_device *dev, uint16_t offset)
2653 {
2654         struct radeon_device *rdev = dev->dev_private;
2655
2656         if (offset) {
2657                 while (RBIOS16(offset)) {
2658                         uint16_t cmd = ((RBIOS16(offset) & 0xe000) >> 13);
2659                         uint32_t addr = (RBIOS16(offset) & 0x1fff);
2660                         uint32_t val, and_mask, or_mask;
2661                         uint32_t tmp;
2662
2663                         offset += 2;
2664                         switch (cmd) {
2665                         case 0:
2666                                 val = RBIOS32(offset);
2667                                 offset += 4;
2668                                 WREG32(addr, val);
2669                                 break;
2670                         case 1:
2671                                 val = RBIOS32(offset);
2672                                 offset += 4;
2673                                 WREG32(addr, val);
2674                                 break;
2675                         case 2:
2676                                 and_mask = RBIOS32(offset);
2677                                 offset += 4;
2678                                 or_mask = RBIOS32(offset);
2679                                 offset += 4;
2680                                 tmp = RREG32(addr);
2681                                 tmp &= and_mask;
2682                                 tmp |= or_mask;
2683                                 WREG32(addr, tmp);
2684                                 break;
2685                         case 3:
2686                                 and_mask = RBIOS32(offset);
2687                                 offset += 4;
2688                                 or_mask = RBIOS32(offset);
2689                                 offset += 4;
2690                                 tmp = RREG32(addr);
2691                                 tmp &= and_mask;
2692                                 tmp |= or_mask;
2693                                 WREG32(addr, tmp);
2694                                 break;
2695                         case 4:
2696                                 val = RBIOS16(offset);
2697                                 offset += 2;
2698                                 udelay(val);
2699                                 break;
2700                         case 5:
2701                                 val = RBIOS16(offset);
2702                                 offset += 2;
2703                                 switch (addr) {
2704                                 case 8:
2705                                         while (val--) {
2706                                                 if (!
2707                                                     (RREG32_PLL
2708                                                      (RADEON_CLK_PWRMGT_CNTL) &
2709                                                      RADEON_MC_BUSY))
2710                                                         break;
2711                                         }
2712                                         break;
2713                                 case 9:
2714                                         while (val--) {
2715                                                 if ((RREG32(RADEON_MC_STATUS) &
2716                                                      RADEON_MC_IDLE))
2717                                                         break;
2718                                         }
2719                                         break;
2720                                 default:
2721                                         break;
2722                                 }
2723                                 break;
2724                         default:
2725                                 break;
2726                         }
2727                 }
2728         }
2729 }
2730
2731 static void combios_parse_pll_table(struct drm_device *dev, uint16_t offset)
2732 {
2733         struct radeon_device *rdev = dev->dev_private;
2734
2735         if (offset) {
2736                 while (RBIOS8(offset)) {
2737                         uint8_t cmd = ((RBIOS8(offset) & 0xc0) >> 6);
2738                         uint8_t addr = (RBIOS8(offset) & 0x3f);
2739                         uint32_t val, shift, tmp;
2740                         uint32_t and_mask, or_mask;
2741
2742                         offset++;
2743                         switch (cmd) {
2744                         case 0:
2745                                 val = RBIOS32(offset);
2746                                 offset += 4;
2747                                 WREG32_PLL(addr, val);
2748                                 break;
2749                         case 1:
2750                                 shift = RBIOS8(offset) * 8;
2751                                 offset++;
2752                                 and_mask = RBIOS8(offset) << shift;
2753                                 and_mask |= ~(0xff << shift);
2754                                 offset++;
2755                                 or_mask = RBIOS8(offset) << shift;
2756                                 offset++;
2757                                 tmp = RREG32_PLL(addr);
2758                                 tmp &= and_mask;
2759                                 tmp |= or_mask;
2760                                 WREG32_PLL(addr, tmp);
2761                                 break;
2762                         case 2:
2763                         case 3:
2764                                 tmp = 1000;
2765                                 switch (addr) {
2766                                 case 1:
2767                                         udelay(150);
2768                                         break;
2769                                 case 2:
2770                                         udelay(1000);
2771                                         break;
2772                                 case 3:
2773                                         while (tmp--) {
2774                                                 if (!
2775                                                     (RREG32_PLL
2776                                                      (RADEON_CLK_PWRMGT_CNTL) &
2777                                                      RADEON_MC_BUSY))
2778                                                         break;
2779                                         }
2780                                         break;
2781                                 case 4:
2782                                         while (tmp--) {
2783                                                 if (RREG32_PLL
2784                                                     (RADEON_CLK_PWRMGT_CNTL) &
2785                                                     RADEON_DLL_READY)
2786                                                         break;
2787                                         }
2788                                         break;
2789                                 case 5:
2790                                         tmp =
2791                                             RREG32_PLL(RADEON_CLK_PWRMGT_CNTL);
2792                                         if (tmp & RADEON_CG_NO1_DEBUG_0) {
2793 #if 0
2794                                                 uint32_t mclk_cntl =
2795                                                     RREG32_PLL
2796                                                     (RADEON_MCLK_CNTL);
2797                                                 mclk_cntl &= 0xffff0000;
2798                                                 /*mclk_cntl |= 0x00001111;*//* ??? */
2799                                                 WREG32_PLL(RADEON_MCLK_CNTL,
2800                                                            mclk_cntl);
2801                                                 udelay(10000);
2802 #endif
2803                                                 WREG32_PLL
2804                                                     (RADEON_CLK_PWRMGT_CNTL,
2805                                                      tmp &
2806                                                      ~RADEON_CG_NO1_DEBUG_0);
2807                                                 udelay(10000);
2808                                         }
2809                                         break;
2810                                 default:
2811                                         break;
2812                                 }
2813                                 break;
2814                         default:
2815                                 break;
2816                         }
2817                 }
2818         }
2819 }
2820
2821 static void combios_parse_ram_reset_table(struct drm_device *dev,
2822                                           uint16_t offset)
2823 {
2824         struct radeon_device *rdev = dev->dev_private;
2825         uint32_t tmp;
2826
2827         if (offset) {
2828                 uint8_t val = RBIOS8(offset);
2829                 while (val != 0xff) {
2830                         offset++;
2831
2832                         if (val == 0x0f) {
2833                                 uint32_t channel_complete_mask;
2834
2835                                 if (ASIC_IS_R300(rdev))
2836                                         channel_complete_mask =
2837                                             R300_MEM_PWRUP_COMPLETE;
2838                                 else
2839                                         channel_complete_mask =
2840                                             RADEON_MEM_PWRUP_COMPLETE;
2841                                 tmp = 20000;
2842                                 while (tmp--) {
2843                                         if ((RREG32(RADEON_MEM_STR_CNTL) &
2844                                              channel_complete_mask) ==
2845                                             channel_complete_mask)
2846                                                 break;
2847                                 }
2848                         } else {
2849                                 uint32_t or_mask = RBIOS16(offset);
2850                                 offset += 2;
2851
2852                                 tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
2853                                 tmp &= RADEON_SDRAM_MODE_MASK;
2854                                 tmp |= or_mask;
2855                                 WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp);
2856
2857                                 or_mask = val << 24;
2858                                 tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
2859                                 tmp &= RADEON_B3MEM_RESET_MASK;
2860                                 tmp |= or_mask;
2861                                 WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp);
2862                         }
2863                         val = RBIOS8(offset);
2864                 }
2865         }
2866 }
2867
2868 static uint32_t combios_detect_ram(struct drm_device *dev, int ram,
2869                                    int mem_addr_mapping)
2870 {
2871         struct radeon_device *rdev = dev->dev_private;
2872         uint32_t mem_cntl;
2873         uint32_t mem_size;
2874         uint32_t addr = 0;
2875
2876         mem_cntl = RREG32(RADEON_MEM_CNTL);
2877         if (mem_cntl & RV100_HALF_MODE)
2878                 ram /= 2;
2879         mem_size = ram;
2880         mem_cntl &= ~(0xff << 8);
2881         mem_cntl |= (mem_addr_mapping & 0xff) << 8;
2882         WREG32(RADEON_MEM_CNTL, mem_cntl);
2883         RREG32(RADEON_MEM_CNTL);
2884
2885         /* sdram reset ? */
2886
2887         /* something like this????  */
2888         while (ram--) {
2889                 addr = ram * 1024 * 1024;
2890                 /* write to each page */
2891                 WREG32(RADEON_MM_INDEX, (addr) | RADEON_MM_APER);
2892                 WREG32(RADEON_MM_DATA, 0xdeadbeef);
2893                 /* read back and verify */
2894                 WREG32(RADEON_MM_INDEX, (addr) | RADEON_MM_APER);
2895                 if (RREG32(RADEON_MM_DATA) != 0xdeadbeef)
2896                         return 0;
2897         }
2898
2899         return mem_size;
2900 }
2901
2902 static void combios_write_ram_size(struct drm_device *dev)
2903 {
2904         struct radeon_device *rdev = dev->dev_private;
2905         uint8_t rev;
2906         uint16_t offset;
2907         uint32_t mem_size = 0;
2908         uint32_t mem_cntl = 0;
2909
2910         /* should do something smarter here I guess... */
2911         if (rdev->flags & RADEON_IS_IGP)
2912                 return;
2913
2914         /* first check detected mem table */
2915         offset = combios_get_table_offset(dev, COMBIOS_DETECTED_MEM_TABLE);
2916         if (offset) {
2917                 rev = RBIOS8(offset);
2918                 if (rev < 3) {
2919                         mem_cntl = RBIOS32(offset + 1);
2920                         mem_size = RBIOS16(offset + 5);
2921                         if (((rdev->flags & RADEON_FAMILY_MASK) < CHIP_R200) &&
2922                             ((dev->pdev->device != 0x515e)
2923                              && (dev->pdev->device != 0x5969)))
2924                                 WREG32(RADEON_MEM_CNTL, mem_cntl);
2925                 }
2926         }
2927
2928         if (!mem_size) {
2929                 offset =
2930                     combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE);
2931                 if (offset) {
2932                         rev = RBIOS8(offset - 1);
2933                         if (rev < 1) {
2934                                 if (((rdev->flags & RADEON_FAMILY_MASK) <
2935                                      CHIP_R200)
2936                                     && ((dev->pdev->device != 0x515e)
2937                                         && (dev->pdev->device != 0x5969))) {
2938                                         int ram = 0;
2939                                         int mem_addr_mapping = 0;
2940
2941                                         while (RBIOS8(offset)) {
2942                                                 ram = RBIOS8(offset);
2943                                                 mem_addr_mapping =
2944                                                     RBIOS8(offset + 1);
2945                                                 if (mem_addr_mapping != 0x25)
2946                                                         ram *= 2;
2947                                                 mem_size =
2948                                                     combios_detect_ram(dev, ram,
2949                                                                        mem_addr_mapping);
2950                                                 if (mem_size)
2951                                                         break;
2952                                                 offset += 2;
2953                                         }
2954                                 } else
2955                                         mem_size = RBIOS8(offset);
2956                         } else {
2957                                 mem_size = RBIOS8(offset);
2958                                 mem_size *= 2;  /* convert to MB */
2959                         }
2960                 }
2961         }
2962
2963         mem_size *= (1024 * 1024);      /* convert to bytes */
2964         WREG32(RADEON_CONFIG_MEMSIZE, mem_size);
2965 }
2966
2967 void radeon_combios_dyn_clk_setup(struct drm_device *dev, int enable)
2968 {
2969         uint16_t dyn_clk_info =
2970             combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE);
2971
2972         if (dyn_clk_info)
2973                 combios_parse_pll_table(dev, dyn_clk_info);
2974 }
2975
2976 void radeon_combios_asic_init(struct drm_device *dev)
2977 {
2978         struct radeon_device *rdev = dev->dev_private;
2979         uint16_t table;
2980
2981         /* port hardcoded mac stuff from radeonfb */
2982         if (rdev->bios == NULL)
2983                 return;
2984
2985         /* ASIC INIT 1 */
2986         table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_1_TABLE);
2987         if (table)
2988                 combios_parse_mmio_table(dev, table);
2989
2990         /* PLL INIT */
2991         table = combios_get_table_offset(dev, COMBIOS_PLL_INIT_TABLE);
2992         if (table)
2993                 combios_parse_pll_table(dev, table);
2994
2995         /* ASIC INIT 2 */
2996         table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_2_TABLE);
2997         if (table)
2998                 combios_parse_mmio_table(dev, table);
2999
3000         if (!(rdev->flags & RADEON_IS_IGP)) {
3001                 /* ASIC INIT 4 */
3002                 table =
3003                     combios_get_table_offset(dev, COMBIOS_ASIC_INIT_4_TABLE);
3004                 if (table)
3005                         combios_parse_mmio_table(dev, table);
3006
3007                 /* RAM RESET */
3008                 table = combios_get_table_offset(dev, COMBIOS_RAM_RESET_TABLE);
3009                 if (table)
3010                         combios_parse_ram_reset_table(dev, table);
3011
3012                 /* ASIC INIT 3 */
3013                 table =
3014                     combios_get_table_offset(dev, COMBIOS_ASIC_INIT_3_TABLE);
3015                 if (table)
3016                         combios_parse_mmio_table(dev, table);
3017
3018                 /* write CONFIG_MEMSIZE */
3019                 combios_write_ram_size(dev);
3020         }
3021
3022         /* DYN CLK 1 */
3023         table = combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE);
3024         if (table)
3025                 combios_parse_pll_table(dev, table);
3026
3027 }
3028
3029 void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev)
3030 {
3031         struct radeon_device *rdev = dev->dev_private;
3032         uint32_t bios_0_scratch, bios_6_scratch, bios_7_scratch;
3033
3034         bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
3035         bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3036         bios_7_scratch = RREG32(RADEON_BIOS_7_SCRATCH);
3037
3038         /* let the bios control the backlight */
3039         bios_0_scratch &= ~RADEON_DRIVER_BRIGHTNESS_EN;
3040
3041         /* tell the bios not to handle mode switching */
3042         bios_6_scratch |= (RADEON_DISPLAY_SWITCHING_DIS |
3043                            RADEON_ACC_MODE_CHANGE);
3044
3045         /* tell the bios a driver is loaded */
3046         bios_7_scratch |= RADEON_DRV_LOADED;
3047
3048         WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
3049         WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
3050         WREG32(RADEON_BIOS_7_SCRATCH, bios_7_scratch);
3051 }
3052
3053 void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock)
3054 {
3055         struct drm_device *dev = encoder->dev;
3056         struct radeon_device *rdev = dev->dev_private;
3057         uint32_t bios_6_scratch;
3058
3059         bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3060
3061         if (lock)
3062                 bios_6_scratch |= RADEON_DRIVER_CRITICAL;
3063         else
3064                 bios_6_scratch &= ~RADEON_DRIVER_CRITICAL;
3065
3066         WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
3067 }
3068
3069 void
3070 radeon_combios_connected_scratch_regs(struct drm_connector *connector,
3071                                       struct drm_encoder *encoder,
3072                                       bool connected)
3073 {
3074         struct drm_device *dev = connector->dev;
3075         struct radeon_device *rdev = dev->dev_private;
3076         struct radeon_connector *radeon_connector =
3077             to_radeon_connector(connector);
3078         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3079         uint32_t bios_4_scratch = RREG32(RADEON_BIOS_4_SCRATCH);
3080         uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH);
3081
3082         if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
3083             (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
3084                 if (connected) {
3085                         DRM_DEBUG("TV1 connected\n");
3086                         /* fix me */
3087                         bios_4_scratch |= RADEON_TV1_ATTACHED_SVIDEO;
3088                         /*save->bios_4_scratch |= RADEON_TV1_ATTACHED_COMP; */
3089                         bios_5_scratch |= RADEON_TV1_ON;
3090                         bios_5_scratch |= RADEON_ACC_REQ_TV1;
3091                 } else {
3092                         DRM_DEBUG("TV1 disconnected\n");
3093                         bios_4_scratch &= ~RADEON_TV1_ATTACHED_MASK;
3094                         bios_5_scratch &= ~RADEON_TV1_ON;
3095                         bios_5_scratch &= ~RADEON_ACC_REQ_TV1;
3096                 }
3097         }
3098         if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
3099             (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
3100                 if (connected) {
3101                         DRM_DEBUG("LCD1 connected\n");
3102                         bios_4_scratch |= RADEON_LCD1_ATTACHED;
3103                         bios_5_scratch |= RADEON_LCD1_ON;
3104                         bios_5_scratch |= RADEON_ACC_REQ_LCD1;
3105                 } else {
3106                         DRM_DEBUG("LCD1 disconnected\n");
3107                         bios_4_scratch &= ~RADEON_LCD1_ATTACHED;
3108                         bios_5_scratch &= ~RADEON_LCD1_ON;
3109                         bios_5_scratch &= ~RADEON_ACC_REQ_LCD1;
3110                 }
3111         }
3112         if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
3113             (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
3114                 if (connected) {
3115                         DRM_DEBUG("CRT1 connected\n");
3116                         bios_4_scratch |= RADEON_CRT1_ATTACHED_COLOR;
3117                         bios_5_scratch |= RADEON_CRT1_ON;
3118                         bios_5_scratch |= RADEON_ACC_REQ_CRT1;
3119                 } else {
3120                         DRM_DEBUG("CRT1 disconnected\n");
3121                         bios_4_scratch &= ~RADEON_CRT1_ATTACHED_MASK;
3122                         bios_5_scratch &= ~RADEON_CRT1_ON;
3123                         bios_5_scratch &= ~RADEON_ACC_REQ_CRT1;
3124                 }
3125         }
3126         if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
3127             (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
3128                 if (connected) {
3129                         DRM_DEBUG("CRT2 connected\n");
3130                         bios_4_scratch |= RADEON_CRT2_ATTACHED_COLOR;
3131                         bios_5_scratch |= RADEON_CRT2_ON;
3132                         bios_5_scratch |= RADEON_ACC_REQ_CRT2;
3133                 } else {
3134                         DRM_DEBUG("CRT2 disconnected\n");
3135                         bios_4_scratch &= ~RADEON_CRT2_ATTACHED_MASK;
3136                         bios_5_scratch &= ~RADEON_CRT2_ON;
3137                         bios_5_scratch &= ~RADEON_ACC_REQ_CRT2;
3138                 }
3139         }
3140         if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
3141             (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
3142                 if (connected) {
3143                         DRM_DEBUG("DFP1 connected\n");
3144                         bios_4_scratch |= RADEON_DFP1_ATTACHED;
3145                         bios_5_scratch |= RADEON_DFP1_ON;
3146                         bios_5_scratch |= RADEON_ACC_REQ_DFP1;
3147                 } else {
3148                         DRM_DEBUG("DFP1 disconnected\n");
3149                         bios_4_scratch &= ~RADEON_DFP1_ATTACHED;
3150                         bios_5_scratch &= ~RADEON_DFP1_ON;
3151                         bios_5_scratch &= ~RADEON_ACC_REQ_DFP1;
3152                 }
3153         }
3154         if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
3155             (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
3156                 if (connected) {
3157                         DRM_DEBUG("DFP2 connected\n");
3158                         bios_4_scratch |= RADEON_DFP2_ATTACHED;
3159                         bios_5_scratch |= RADEON_DFP2_ON;
3160                         bios_5_scratch |= RADEON_ACC_REQ_DFP2;
3161                 } else {
3162                         DRM_DEBUG("DFP2 disconnected\n");
3163                         bios_4_scratch &= ~RADEON_DFP2_ATTACHED;
3164                         bios_5_scratch &= ~RADEON_DFP2_ON;
3165                         bios_5_scratch &= ~RADEON_ACC_REQ_DFP2;
3166                 }
3167         }
3168         WREG32(RADEON_BIOS_4_SCRATCH, bios_4_scratch);
3169         WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
3170 }
3171
3172 void
3173 radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
3174 {
3175         struct drm_device *dev = encoder->dev;
3176         struct radeon_device *rdev = dev->dev_private;
3177         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3178         uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH);
3179
3180         if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
3181                 bios_5_scratch &= ~RADEON_TV1_CRTC_MASK;
3182                 bios_5_scratch |= (crtc << RADEON_TV1_CRTC_SHIFT);
3183         }
3184         if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
3185                 bios_5_scratch &= ~RADEON_CRT1_CRTC_MASK;
3186                 bios_5_scratch |= (crtc << RADEON_CRT1_CRTC_SHIFT);
3187         }
3188         if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
3189                 bios_5_scratch &= ~RADEON_CRT2_CRTC_MASK;
3190                 bios_5_scratch |= (crtc << RADEON_CRT2_CRTC_SHIFT);
3191         }
3192         if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
3193                 bios_5_scratch &= ~RADEON_LCD1_CRTC_MASK;
3194                 bios_5_scratch |= (crtc << RADEON_LCD1_CRTC_SHIFT);
3195         }
3196         if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
3197                 bios_5_scratch &= ~RADEON_DFP1_CRTC_MASK;
3198                 bios_5_scratch |= (crtc << RADEON_DFP1_CRTC_SHIFT);
3199         }
3200         if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
3201                 bios_5_scratch &= ~RADEON_DFP2_CRTC_MASK;
3202                 bios_5_scratch |= (crtc << RADEON_DFP2_CRTC_SHIFT);
3203         }
3204         WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
3205 }
3206
3207 void
3208 radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
3209 {
3210         struct drm_device *dev = encoder->dev;
3211         struct radeon_device *rdev = dev->dev_private;
3212         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3213         uint32_t bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3214
3215         if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) {
3216                 if (on)
3217                         bios_6_scratch |= RADEON_TV_DPMS_ON;
3218                 else
3219                         bios_6_scratch &= ~RADEON_TV_DPMS_ON;
3220         }
3221         if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
3222                 if (on)
3223                         bios_6_scratch |= RADEON_CRT_DPMS_ON;
3224                 else
3225                         bios_6_scratch &= ~RADEON_CRT_DPMS_ON;
3226         }
3227         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
3228                 if (on)
3229                         bios_6_scratch |= RADEON_LCD_DPMS_ON;
3230                 else
3231                         bios_6_scratch &= ~RADEON_LCD_DPMS_ON;
3232         }
3233         if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
3234                 if (on)
3235                         bios_6_scratch |= RADEON_DFP_DPMS_ON;
3236                 else
3237                         bios_6_scratch &= ~RADEON_DFP_DPMS_ON;
3238         }
3239         WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
3240 }