drivers/gpu/drm/radeon/radeon_atombios.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include "drmP.h"
  27 #include "radeon_drm.h"
  28 #include "radeon.h"
  29
  30 #include "atom.h"
  31 #include "atom-bits.h"
  32
  33 /* from radeon_encoder.c */
  34 extern uint32_t
  35 radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device,
  36                         uint8_t dac);
  37 extern void radeon_link_encoder_connector(struct drm_device *dev);
  38 extern void
  39 radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_enum,
  40                         uint32_t supported_device, u16 caps);
  41
  42 /* from radeon_connector.c */
  43 extern void
  44 radeon_add_atom_connector(struct drm_device *dev,
  45                           uint32_t connector_id,
  46                           uint32_t supported_device,
  47                           int connector_type,
  48                           struct radeon_i2c_bus_rec *i2c_bus,
  49                           uint32_t igp_lane_info,
  50                           uint16_t connector_object_id,
  51                           struct radeon_hpd *hpd,
  52                           struct radeon_router *router);
  53
  54 /* from radeon_legacy_encoder.c */
  55 extern void
  56 radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_enum,
  57                           uint32_t supported_device);
  58
  59 /* local */
  60 static int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
  61                                     u16 voltage_id, u16 *voltage);
  62
  63 union atom_supported_devices {
  64         struct _ATOM_SUPPORTED_DEVICES_INFO info;
  65         struct _ATOM_SUPPORTED_DEVICES_INFO_2 info_2;
  66         struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 info_2d1;
  67 };
  68
  69 static void radeon_lookup_i2c_gpio_quirks(struct radeon_device *rdev,
  70                                           ATOM_GPIO_I2C_ASSIGMENT *gpio,
  71                                           u8 index)
  72 {
  73         /* r4xx mask is technically not used by the hw, so patch in the legacy mask bits */
  74         if ((rdev->family == CHIP_R420) ||
  75             (rdev->family == CHIP_R423) ||
  76             (rdev->family == CHIP_RV410)) {
  77                 if ((le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x0018) ||
  78                     (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x0019) ||
  79                     (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x001a)) {
  80                         gpio->ucClkMaskShift = 0x19;
  81                         gpio->ucDataMaskShift = 0x18;
  82                 }
  83         }
  84
  85         /* some evergreen boards have bad data for this entry */
  86         if (ASIC_IS_DCE4(rdev)) {
  87                 if ((index == 7) &&
  88                     (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1936) &&
  89                     (gpio->sucI2cId.ucAccess == 0)) {
  90                         gpio->sucI2cId.ucAccess = 0x97;
  91                         gpio->ucDataMaskShift = 8;
  92                         gpio->ucDataEnShift = 8;
  93                         gpio->ucDataY_Shift = 8;
  94                         gpio->ucDataA_Shift = 8;
  95                 }
  96         }
  97
  98         /* some DCE3 boards have bad data for this entry */
  99         if (ASIC_IS_DCE3(rdev)) {
 100                 if ((index == 4) &&
 101                     (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1fda) &&
 102                     (gpio->sucI2cId.ucAccess == 0x94))
 103                         gpio->sucI2cId.ucAccess = 0x14;
 104         }
 105 }
 106
 107 static struct radeon_i2c_bus_rec radeon_get_bus_rec_for_i2c_gpio(ATOM_GPIO_I2C_ASSIGMENT *gpio)
 108 {
 109         struct radeon_i2c_bus_rec i2c;
 110
 111         memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
 112
 113         i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4;
 114         i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4;
 115         i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4;
 116         i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4;
 117         i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4;
 118         i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4;
 119         i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4;
 120         i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4;
 121         i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
 122         i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
 123         i2c.en_clk_mask = (1 << gpio->ucClkEnShift);
 124         i2c.en_data_mask = (1 << gpio->ucDataEnShift);
 125         i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);
 126         i2c.y_data_mask = (1 << gpio->ucDataY_Shift);
 127         i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
 128         i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
 129
 130         if (gpio->sucI2cId.sbfAccess.bfHW_Capable)
 131                 i2c.hw_capable = true;
 132         else
 133                 i2c.hw_capable = false;
 134
 135         if (gpio->sucI2cId.ucAccess == 0xa0)
 136                 i2c.mm_i2c = true;
 137         else
 138                 i2c.mm_i2c = false;
 139
 140         i2c.i2c_id = gpio->sucI2cId.ucAccess;
 141
 142         if (i2c.mask_clk_reg)
 143                 i2c.valid = true;
 144         else
 145                 i2c.valid = false;
 146
 147         return i2c;
 148 }
 149
 150 static struct radeon_i2c_bus_rec radeon_lookup_i2c_gpio(struct radeon_device *rdev,
 151                                                                uint8_t id)
 152 {
 153         struct atom_context *ctx = rdev->mode_info.atom_context;
 154         ATOM_GPIO_I2C_ASSIGMENT *gpio;
 155         struct radeon_i2c_bus_rec i2c;
 156         int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
 157         struct _ATOM_GPIO_I2C_INFO *i2c_info;
 158         uint16_t data_offset, size;
 159         int i, num_indices;
 160
 161         memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
 162         i2c.valid = false;
 163
 164         if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
 165                 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
 166
 167                 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
 168                         sizeof(ATOM_GPIO_I2C_ASSIGMENT);
 169
 170                 for (i = 0; i < num_indices; i++) {
 171                         gpio = &i2c_info->asGPIO_Info[i];
 172
 173                         radeon_lookup_i2c_gpio_quirks(rdev, gpio, i);
 174
 175                         if (gpio->sucI2cId.ucAccess == id) {
 176                                 i2c = radeon_get_bus_rec_for_i2c_gpio(gpio);
 177                                 break;
 178                         }
 179                 }
 180         }
 181
 182         return i2c;
 183 }
 184
 185 void radeon_atombios_i2c_init(struct radeon_device *rdev)
 186 {
 187         struct atom_context *ctx = rdev->mode_info.atom_context;
 188         ATOM_GPIO_I2C_ASSIGMENT *gpio;
 189         struct radeon_i2c_bus_rec i2c;
 190         int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
 191         struct _ATOM_GPIO_I2C_INFO *i2c_info;
 192         uint16_t data_offset, size;
 193         int i, num_indices;
 194         char stmp[32];
 195
 196         if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
 197                 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
 198
 199                 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
 200                         sizeof(ATOM_GPIO_I2C_ASSIGMENT);
 201
 202                 for (i = 0; i < num_indices; i++) {
 203                         gpio = &i2c_info->asGPIO_Info[i];
 204
 205                         radeon_lookup_i2c_gpio_quirks(rdev, gpio, i);
 206
 207                         i2c = radeon_get_bus_rec_for_i2c_gpio(gpio);
 208
 209                         if (i2c.valid) {
 210                                 sprintf(stmp, "0x%x", i2c.i2c_id);
 211                                 rdev->i2c_bus[i] = radeon_i2c_create(rdev->ddev, &i2c, stmp);
 212                         }
 213                 }
 214         }
 215 }
 216
 217 static struct radeon_gpio_rec radeon_lookup_gpio(struct radeon_device *rdev,
 218                                                         u8 id)
 219 {
 220         struct atom_context *ctx = rdev->mode_info.atom_context;
 221         struct radeon_gpio_rec gpio;
 222         int index = GetIndexIntoMasterTable(DATA, GPIO_Pin_LUT);
 223         struct _ATOM_GPIO_PIN_LUT *gpio_info;
 224         ATOM_GPIO_PIN_ASSIGNMENT *pin;
 225         u16 data_offset, size;
 226         int i, num_indices;
 227
 228         memset(&gpio, 0, sizeof(struct radeon_gpio_rec));
 229         gpio.valid = false;
 230
 231         if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
 232                 gpio_info = (struct _ATOM_GPIO_PIN_LUT *)(ctx->bios + data_offset);
 233
 234                 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
 235                         sizeof(ATOM_GPIO_PIN_ASSIGNMENT);
 236
 237                 for (i = 0; i < num_indices; i++) {
 238                         pin = &gpio_info->asGPIO_Pin[i];
 239                         if (id == pin->ucGPIO_ID) {
 240                                 gpio.id = pin->ucGPIO_ID;
 241                                 gpio.reg = le16_to_cpu(pin->usGpioPin_AIndex) * 4;
 242                                 gpio.mask = (1 << pin->ucGpioPinBitShift);
 243                                 gpio.valid = true;
 244                                 break;
 245                         }
 246                 }
 247         }
 248
 249         return gpio;
 250 }
 251
 252 static struct radeon_hpd radeon_atom_get_hpd_info_from_gpio(struct radeon_device *rdev,
 253                                                             struct radeon_gpio_rec *gpio)
 254 {
 255         struct radeon_hpd hpd;
 256         u32 reg;
 257
 258         memset(&hpd, 0, sizeof(struct radeon_hpd));
 259
 260         if (ASIC_IS_DCE6(rdev))
 261                 reg = SI_DC_GPIO_HPD_A;
 262         else if (ASIC_IS_DCE4(rdev))
 263                 reg = EVERGREEN_DC_GPIO_HPD_A;
 264         else
 265                 reg = AVIVO_DC_GPIO_HPD_A;
 266
 267         hpd.gpio = *gpio;
 268         if (gpio->reg == reg) {
 269                 switch(gpio->mask) {
 270                 case (1 << 0):
 271                         hpd.hpd = RADEON_HPD_1;
 272                         break;
 273                 case (1 << 8):
 274                         hpd.hpd = RADEON_HPD_2;
 275                         break;
 276                 case (1 << 16):
 277                         hpd.hpd = RADEON_HPD_3;
 278                         break;
 279                 case (1 << 24):
 280                         hpd.hpd = RADEON_HPD_4;
 281                         break;
 282                 case (1 << 26):
 283                         hpd.hpd = RADEON_HPD_5;
 284                         break;
 285                 case (1 << 28):
 286                         hpd.hpd = RADEON_HPD_6;
 287                         break;
 288                 default:
 289                         hpd.hpd = RADEON_HPD_NONE;
 290                         break;
 291                 }
 292         } else
 293                 hpd.hpd = RADEON_HPD_NONE;
 294         return hpd;
 295 }
 296
 297 static bool radeon_atom_apply_quirks(struct drm_device *dev,
 298                                      uint32_t supported_device,
 299                                      int *connector_type,
 300                                      struct radeon_i2c_bus_rec *i2c_bus,
 301                                      uint16_t *line_mux,
 302                                      struct radeon_hpd *hpd)
 303 {
 304
 305         /* Asus M2A-VM HDMI board lists the DVI port as HDMI */
 306         if ((dev->pdev->device == 0x791e) &&
 307             (dev->pdev->subsystem_vendor == 0x1043) &&
 308             (dev->pdev->subsystem_device == 0x826d)) {
 309                 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
 310                     (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
 311                         *connector_type = DRM_MODE_CONNECTOR_DVID;
 312         }
 313
 314         /* Asrock RS600 board lists the DVI port as HDMI */
 315         if ((dev->pdev->device == 0x7941) &&
 316             (dev->pdev->subsystem_vendor == 0x1849) &&
 317             (dev->pdev->subsystem_device == 0x7941)) {
 318                 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
 319                     (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
 320                         *connector_type = DRM_MODE_CONNECTOR_DVID;
 321         }
 322
 323         /* MSI K9A2GM V2/V3 board has no HDMI or DVI */
 324         if ((dev->pdev->device == 0x796e) &&
 325             (dev->pdev->subsystem_vendor == 0x1462) &&
 326             (dev->pdev->subsystem_device == 0x7302)) {
 327                 if ((supported_device == ATOM_DEVICE_DFP2_SUPPORT) ||
 328                     (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
 329                         return false;
 330         }
 331
 332         /* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */
 333         if ((dev->pdev->device == 0x7941) &&
 334             (dev->pdev->subsystem_vendor == 0x147b) &&
 335             (dev->pdev->subsystem_device == 0x2412)) {
 336                 if (*connector_type == DRM_MODE_CONNECTOR_DVII)
 337                         return false;
 338         }
 339
 340         /* Falcon NW laptop lists vga ddc line for LVDS */
 341         if ((dev->pdev->device == 0x5653) &&
 342             (dev->pdev->subsystem_vendor == 0x1462) &&
 343             (dev->pdev->subsystem_device == 0x0291)) {
 344                 if (*connector_type == DRM_MODE_CONNECTOR_LVDS) {
 345                         i2c_bus->valid = false;
 346                         *line_mux = 53;
 347                 }
 348         }
 349
 350         /* HIS X1300 is DVI+VGA, not DVI+DVI */
 351         if ((dev->pdev->device == 0x7146) &&
 352             (dev->pdev->subsystem_vendor == 0x17af) &&
 353             (dev->pdev->subsystem_device == 0x2058)) {
 354                 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
 355                         return false;
 356         }
 357
 358         /* Gigabyte X1300 is DVI+VGA, not DVI+DVI */
 359         if ((dev->pdev->device == 0x7142) &&
 360             (dev->pdev->subsystem_vendor == 0x1458) &&
 361             (dev->pdev->subsystem_device == 0x2134)) {
 362                 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
 363                         return false;
 364         }
 365
 366
 367         /* Funky macbooks */
 368         if ((dev->pdev->device == 0x71C5) &&
 369             (dev->pdev->subsystem_vendor == 0x106b) &&
 370             (dev->pdev->subsystem_device == 0x0080)) {
 371                 if ((supported_device == ATOM_DEVICE_CRT1_SUPPORT) ||
 372                     (supported_device == ATOM_DEVICE_DFP2_SUPPORT))
 373                         return false;
 374                 if (supported_device == ATOM_DEVICE_CRT2_SUPPORT)
 375                         *line_mux = 0x90;
 376         }
 377
 378         /* mac rv630, rv730, others */
 379         if ((supported_device == ATOM_DEVICE_TV1_SUPPORT) &&
 380             (*connector_type == DRM_MODE_CONNECTOR_DVII)) {
 381                 *connector_type = DRM_MODE_CONNECTOR_9PinDIN;
 382                 *line_mux = CONNECTOR_7PIN_DIN_ENUM_ID1;
 383         }
 384
 385         /* ASUS HD 3600 XT board lists the DVI port as HDMI */
 386         if ((dev->pdev->device == 0x9598) &&
 387             (dev->pdev->subsystem_vendor == 0x1043) &&
 388             (dev->pdev->subsystem_device == 0x01da)) {
 389                 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
 390                         *connector_type = DRM_MODE_CONNECTOR_DVII;
 391                 }
 392         }
 393
 394         /* ASUS HD 3600 board lists the DVI port as HDMI */
 395         if ((dev->pdev->device == 0x9598) &&
 396             (dev->pdev->subsystem_vendor == 0x1043) &&
 397             (dev->pdev->subsystem_device == 0x01e4)) {
 398                 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
 399                         *connector_type = DRM_MODE_CONNECTOR_DVII;
 400                 }
 401         }
 402
 403         /* ASUS HD 3450 board lists the DVI port as HDMI */
 404         if ((dev->pdev->device == 0x95C5) &&
 405             (dev->pdev->subsystem_vendor == 0x1043) &&
 406             (dev->pdev->subsystem_device == 0x01e2)) {
 407                 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
 408                         *connector_type = DRM_MODE_CONNECTOR_DVII;
 409                 }
 410         }
 411
 412         /* some BIOSes seem to report DAC on HDMI - usually this is a board with
 413          * HDMI + VGA reporting as HDMI
 414          */
 415         if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
 416                 if (supported_device & (ATOM_DEVICE_CRT_SUPPORT)) {
 417                         *connector_type = DRM_MODE_CONNECTOR_VGA;
 418                         *line_mux = 0;
 419                 }
 420         }
 421
 422         /* Acer laptop (Acer TravelMate 5730/5730G) has an HDMI port
 423          * on the laptop and a DVI port on the docking station and
 424          * both share the same encoder, hpd pin, and ddc line.
 425          * So while the bios table is technically correct,
 426          * we drop the DVI port here since xrandr has no concept of
 427          * encoders and will try and drive both connectors
 428          * with different crtcs which isn't possible on the hardware
 429          * side and leaves no crtcs for LVDS or VGA.
 430          */
 431         if (((dev->pdev->device == 0x95c4) || (dev->pdev->device == 0x9591)) &&
 432             (dev->pdev->subsystem_vendor == 0x1025) &&
 433             (dev->pdev->subsystem_device == 0x013c)) {
 434                 if ((*connector_type == DRM_MODE_CONNECTOR_DVII) &&
 435                     (supported_device == ATOM_DEVICE_DFP1_SUPPORT)) {
 436                         /* actually it's a DVI-D port not DVI-I */
 437                         *connector_type = DRM_MODE_CONNECTOR_DVID;
 438                         return false;
 439                 }
 440         }
 441
 442         /* XFX Pine Group device rv730 reports no VGA DDC lines
 443          * even though they are wired up to record 0x93
 444          */
 445         if ((dev->pdev->device == 0x9498) &&
 446             (dev->pdev->subsystem_vendor == 0x1682) &&
 447             (dev->pdev->subsystem_device == 0x2452) &&
 448             (i2c_bus->valid == false) &&
 449             !(supported_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))) {
 450                 struct radeon_device *rdev = dev->dev_private;
 451                 *i2c_bus = radeon_lookup_i2c_gpio(rdev, 0x93);
 452         }
 453
 454         /* Fujitsu D3003-S2 board lists DVI-I as DVI-D and VGA */
 455         if ((dev->pdev->device == 0x9802) &&
 456             (dev->pdev->subsystem_vendor == 0x1734) &&
 457             (dev->pdev->subsystem_device == 0x11bd)) {
 458                 if (*connector_type == DRM_MODE_CONNECTOR_VGA) {
 459                         *connector_type = DRM_MODE_CONNECTOR_DVII;
 460                         *line_mux = 0x3103;
 461                 } else if (*connector_type == DRM_MODE_CONNECTOR_DVID) {
 462                         *connector_type = DRM_MODE_CONNECTOR_DVII;
 463                 }
 464         }
 465
 466
 467         return true;
 468 }
 469
 470 const int supported_devices_connector_convert[] = {
 471         DRM_MODE_CONNECTOR_Unknown,
 472         DRM_MODE_CONNECTOR_VGA,
 473         DRM_MODE_CONNECTOR_DVII,
 474         DRM_MODE_CONNECTOR_DVID,
 475         DRM_MODE_CONNECTOR_DVIA,
 476         DRM_MODE_CONNECTOR_SVIDEO,
 477         DRM_MODE_CONNECTOR_Composite,
 478         DRM_MODE_CONNECTOR_LVDS,
 479         DRM_MODE_CONNECTOR_Unknown,
 480         DRM_MODE_CONNECTOR_Unknown,
 481         DRM_MODE_CONNECTOR_HDMIA,
 482         DRM_MODE_CONNECTOR_HDMIB,
 483         DRM_MODE_CONNECTOR_Unknown,
 484         DRM_MODE_CONNECTOR_Unknown,
 485         DRM_MODE_CONNECTOR_9PinDIN,
 486         DRM_MODE_CONNECTOR_DisplayPort
 487 };
 488
 489 const uint16_t supported_devices_connector_object_id_convert[] = {
 490         CONNECTOR_OBJECT_ID_NONE,
 491         CONNECTOR_OBJECT_ID_VGA,
 492         CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, /* not all boards support DL */
 493         CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D, /* not all boards support DL */
 494         CONNECTOR_OBJECT_ID_VGA, /* technically DVI-A */
 495         CONNECTOR_OBJECT_ID_COMPOSITE,
 496         CONNECTOR_OBJECT_ID_SVIDEO,
 497         CONNECTOR_OBJECT_ID_LVDS,
 498         CONNECTOR_OBJECT_ID_9PIN_DIN,
 499         CONNECTOR_OBJECT_ID_9PIN_DIN,
 500         CONNECTOR_OBJECT_ID_DISPLAYPORT,
 501         CONNECTOR_OBJECT_ID_HDMI_TYPE_A,
 502         CONNECTOR_OBJECT_ID_HDMI_TYPE_B,
 503         CONNECTOR_OBJECT_ID_SVIDEO
 504 };
 505
 506 const int object_connector_convert[] = {
 507         DRM_MODE_CONNECTOR_Unknown,
 508         DRM_MODE_CONNECTOR_DVII,
 509         DRM_MODE_CONNECTOR_DVII,
 510         DRM_MODE_CONNECTOR_DVID,
 511         DRM_MODE_CONNECTOR_DVID,
 512         DRM_MODE_CONNECTOR_VGA,
 513         DRM_MODE_CONNECTOR_Composite,
 514         DRM_MODE_CONNECTOR_SVIDEO,
 515         DRM_MODE_CONNECTOR_Unknown,
 516         DRM_MODE_CONNECTOR_Unknown,
 517         DRM_MODE_CONNECTOR_9PinDIN,
 518         DRM_MODE_CONNECTOR_Unknown,
 519         DRM_MODE_CONNECTOR_HDMIA,
 520         DRM_MODE_CONNECTOR_HDMIB,
 521         DRM_MODE_CONNECTOR_LVDS,
 522         DRM_MODE_CONNECTOR_9PinDIN,
 523         DRM_MODE_CONNECTOR_Unknown,
 524         DRM_MODE_CONNECTOR_Unknown,
 525         DRM_MODE_CONNECTOR_Unknown,
 526         DRM_MODE_CONNECTOR_DisplayPort,
 527         DRM_MODE_CONNECTOR_eDP,
 528         DRM_MODE_CONNECTOR_Unknown
 529 };
 530
 531 bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
 532 {
 533         struct radeon_device *rdev = dev->dev_private;
 534         struct radeon_mode_info *mode_info = &rdev->mode_info;
 535         struct atom_context *ctx = mode_info->atom_context;
 536         int index = GetIndexIntoMasterTable(DATA, Object_Header);
 537         u16 size, data_offset;
 538         u8 frev, crev;
 539         ATOM_CONNECTOR_OBJECT_TABLE *con_obj;
 540         ATOM_ENCODER_OBJECT_TABLE *enc_obj;
 541         ATOM_OBJECT_TABLE *router_obj;
 542         ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj;
 543         ATOM_OBJECT_HEADER *obj_header;
 544         int i, j, k, path_size, device_support;
 545         int connector_type;
 546         u16 igp_lane_info, conn_id, connector_object_id;
 547         struct radeon_i2c_bus_rec ddc_bus;
 548         struct radeon_router router;
 549         struct radeon_gpio_rec gpio;
 550         struct radeon_hpd hpd;
 551
 552         if (!atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset))
 553                 return false;
 554
 555         if (crev < 2)
 556                 return false;
 557
 558         obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset);
 559         path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *)
 560             (ctx->bios + data_offset +
 561              le16_to_cpu(obj_header->usDisplayPathTableOffset));
 562         con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *)
 563             (ctx->bios + data_offset +
 564              le16_to_cpu(obj_header->usConnectorObjectTableOffset));
 565         enc_obj = (ATOM_ENCODER_OBJECT_TABLE *)
 566             (ctx->bios + data_offset +
 567              le16_to_cpu(obj_header->usEncoderObjectTableOffset));
 568         router_obj = (ATOM_OBJECT_TABLE *)
 569                 (ctx->bios + data_offset +
 570                  le16_to_cpu(obj_header->usRouterObjectTableOffset));
 571         device_support = le16_to_cpu(obj_header->usDeviceSupport);
 572
 573         path_size = 0;
 574         for (i = 0; i < path_obj->ucNumOfDispPath; i++) {
 575                 uint8_t *addr = (uint8_t *) path_obj->asDispPath;
 576                 ATOM_DISPLAY_OBJECT_PATH *path;
 577                 addr += path_size;
 578                 path = (ATOM_DISPLAY_OBJECT_PATH *) addr;
 579                 path_size += le16_to_cpu(path->usSize);
 580
 581                 if (device_support & le16_to_cpu(path->usDeviceTag)) {
 582                         uint8_t con_obj_id, con_obj_num, con_obj_type;
 583
 584                         con_obj_id =
 585                             (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK)
 586                             >> OBJECT_ID_SHIFT;
 587                         con_obj_num =
 588                             (le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK)
 589                             >> ENUM_ID_SHIFT;
 590                         con_obj_type =
 591                             (le16_to_cpu(path->usConnObjectId) &
 592                              OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
 593
 594                         /* TODO CV support */
 595                         if (le16_to_cpu(path->usDeviceTag) ==
 596                                 ATOM_DEVICE_CV_SUPPORT)
 597                                 continue;
 598
 599                         /* IGP chips */
 600                         if ((rdev->flags & RADEON_IS_IGP) &&
 601                             (con_obj_id ==
 602                              CONNECTOR_OBJECT_ID_PCIE_CONNECTOR)) {
 603                                 uint16_t igp_offset = 0;
 604                                 ATOM_INTEGRATED_SYSTEM_INFO_V2 *igp_obj;
 605
 606                                 index =
 607                                     GetIndexIntoMasterTable(DATA,
 608                                                             IntegratedSystemInfo);
 609
 610                                 if (atom_parse_data_header(ctx, index, &size, &frev,
 611                                                            &crev, &igp_offset)) {
 612
 613                                         if (crev >= 2) {
 614                                                 igp_obj =
 615                                                         (ATOM_INTEGRATED_SYSTEM_INFO_V2
 616                                                          *) (ctx->bios + igp_offset);
 617
 618                                                 if (igp_obj) {
 619                                                         uint32_t slot_config, ct;
 620
 621                                                         if (con_obj_num == 1)
 622                                                                 slot_config =
 623                                                                         igp_obj->
 624                                                                         ulDDISlot1Config;
 625                                                         else
 626                                                                 slot_config =
 627                                                                         igp_obj->
 628                                                                         ulDDISlot2Config;
 629
 630                                                         ct = (slot_config >> 16) & 0xff;
 631                                                         connector_type =
 632                                                                 object_connector_convert
 633                                                                 [ct];
 634                                                         connector_object_id = ct;
 635                                                         igp_lane_info =
 636                                                                 slot_config & 0xffff;
 637                                                 } else
 638                                                         continue;
 639                                         } else
 640                                                 continue;
 641                                 } else {
 642                                         igp_lane_info = 0;
 643                                         connector_type =
 644                                                 object_connector_convert[con_obj_id];
 645                                         connector_object_id = con_obj_id;
 646                                 }
 647                         } else {
 648                                 igp_lane_info = 0;
 649                                 connector_type =
 650                                     object_connector_convert[con_obj_id];
 651                                 connector_object_id = con_obj_id;
 652                         }
 653
 654                         if (connector_type == DRM_MODE_CONNECTOR_Unknown)
 655                                 continue;
 656
 657                         router.ddc_valid = false;
 658                         router.cd_valid = false;
 659                         for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2); j++) {
 660                                 uint8_t grph_obj_id, grph_obj_num, grph_obj_type;
 661
 662                                 grph_obj_id =
 663                                     (le16_to_cpu(path->usGraphicObjIds[j]) &
 664                                      OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
 665                                 grph_obj_num =
 666                                     (le16_to_cpu(path->usGraphicObjIds[j]) &
 667                                      ENUM_ID_MASK) >> ENUM_ID_SHIFT;
 668                                 grph_obj_type =
 669                                     (le16_to_cpu(path->usGraphicObjIds[j]) &
 670                                      OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
 671
 672                                 if (grph_obj_type == GRAPH_OBJECT_TYPE_ENCODER) {
 673                                         for (k = 0; k < enc_obj->ucNumberOfObjects; k++) {
 674                                                 u16 encoder_obj = le16_to_cpu(enc_obj->asObjects[k].usObjectID);
 675                                                 if (le16_to_cpu(path->usGraphicObjIds[j]) == encoder_obj) {
 676                                                         ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
 677                                                                 (ctx->bios + data_offset +
 678                                                                  le16_to_cpu(enc_obj->asObjects[k].usRecordOffset));
 679                                                         ATOM_ENCODER_CAP_RECORD *cap_record;
 680                                                         u16 caps = 0;
 681
 682                                                         while (record->ucRecordSize > 0 &&
 683                                                                record->ucRecordType > 0 &&
 684                                                                record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
 685                                                                 switch (record->ucRecordType) {
 686                                                                 case ATOM_ENCODER_CAP_RECORD_TYPE:
 687                                                                         cap_record =(ATOM_ENCODER_CAP_RECORD *)
 688                                                                                 record;
 689                                                                         caps = le16_to_cpu(cap_record->usEncoderCap);
 690                                                                         break;
 691                                                                 }
 692                                                                 record = (ATOM_COMMON_RECORD_HEADER *)
 693                                                                         ((char *)record + record->ucRecordSize);
 694                                                         }
 695                                                         radeon_add_atom_encoder(dev,
 696                                                                                 encoder_obj,
 697                                                                                 le16_to_cpu
 698                                                                                 (path->
 699                                                                                  usDeviceTag),
 700                                                                                 caps);
 701                                                 }
 702                                         }
 703                                 } else if (grph_obj_type == GRAPH_OBJECT_TYPE_ROUTER) {
 704                                         for (k = 0; k < router_obj->ucNumberOfObjects; k++) {
 705                                                 u16 router_obj_id = le16_to_cpu(router_obj->asObjects[k].usObjectID);
 706                                                 if (le16_to_cpu(path->usGraphicObjIds[j]) == router_obj_id) {
 707                                                         ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
 708                                                                 (ctx->bios + data_offset +
 709                                                                  le16_to_cpu(router_obj->asObjects[k].usRecordOffset));
 710                                                         ATOM_I2C_RECORD *i2c_record;
 711                                                         ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
 712                                                         ATOM_ROUTER_DDC_PATH_SELECT_RECORD *ddc_path;
 713                                                         ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *cd_path;
 714                                                         ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *router_src_dst_table =
 715                                                                 (ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *)
 716                                                                 (ctx->bios + data_offset +
 717                                                                  le16_to_cpu(router_obj->asObjects[k].usSrcDstTableOffset));
 718                                                         int enum_id;
 719
 720                                                         router.router_id = router_obj_id;
 721                                                         for (enum_id = 0; enum_id < router_src_dst_table->ucNumberOfDst;
 722                                                              enum_id++) {
 723                                                                 if (le16_to_cpu(path->usConnObjectId) ==
 724                                                                     le16_to_cpu(router_src_dst_table->usDstObjectID[enum_id]))
 725                                                                         break;
 726                                                         }
 727
 728                                                         while (record->ucRecordSize > 0 &&
 729                                                                record->ucRecordType > 0 &&
 730                                                                record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
 731                                                                 switch (record->ucRecordType) {
 732                                                                 case ATOM_I2C_RECORD_TYPE:
 733                                                                         i2c_record =
 734                                                                                 (ATOM_I2C_RECORD *)
 735                                                                                 record;
 736                                                                         i2c_config =
 737                                                                                 (ATOM_I2C_ID_CONFIG_ACCESS *)
 738                                                                                 &i2c_record->sucI2cId;
 739                                                                         router.i2c_info =
 740                                                                                 radeon_lookup_i2c_gpio(rdev,
 741                                                                                                        i2c_config->
 742                                                                                                        ucAccess);
 743                                                                         router.i2c_addr = i2c_record->ucI2CAddr >> 1;
 744                                                                         break;
 745                                                                 case ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE:
 746                                                                         ddc_path = (ATOM_ROUTER_DDC_PATH_SELECT_RECORD *)
 747                                                                                 record;
 748                                                                         router.ddc_valid = true;
 749                                                                         router.ddc_mux_type = ddc_path->ucMuxType;
 750                                                                         router.ddc_mux_control_pin = ddc_path->ucMuxControlPin;
 751                                                                         router.ddc_mux_state = ddc_path->ucMuxState[enum_id];
 752                                                                         break;
 753                                                                 case ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE:
 754                                                                         cd_path = (ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *)
 755                                                                                 record;
 756                                                                         router.cd_valid = true;
 757                                                                         router.cd_mux_type = cd_path->ucMuxType;
 758                                                                         router.cd_mux_control_pin = cd_path->ucMuxControlPin;
 759                                                                         router.cd_mux_state = cd_path->ucMuxState[enum_id];
 760                                                                         break;
 761                                                                 }
 762                                                                 record = (ATOM_COMMON_RECORD_HEADER *)
 763                                                                         ((char *)record + record->ucRecordSize);
 764                                                         }
 765                                                 }
 766                                         }
 767                                 }
 768                         }
 769
 770                         /* look up gpio for ddc, hpd */
 771                         ddc_bus.valid = false;
 772                         hpd.hpd = RADEON_HPD_NONE;
 773                         if ((le16_to_cpu(path->usDeviceTag) &
 774                              (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) == 0) {
 775                                 for (j = 0; j < con_obj->ucNumberOfObjects; j++) {
 776                                         if (le16_to_cpu(path->usConnObjectId) ==
 777                                             le16_to_cpu(con_obj->asObjects[j].
 778                                                         usObjectID)) {
 779                                                 ATOM_COMMON_RECORD_HEADER
 780                                                     *record =
 781                                                     (ATOM_COMMON_RECORD_HEADER
 782                                                      *)
 783                                                     (ctx->bios + data_offset +
 784                                                      le16_to_cpu(con_obj->
 785                                                                  asObjects[j].
 786                                                                  usRecordOffset));
 787                                                 ATOM_I2C_RECORD *i2c_record;
 788                                                 ATOM_HPD_INT_RECORD *hpd_record;
 789                                                 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
 790
 791                                                 while (record->ucRecordSize > 0 &&
 792                                                        record->ucRecordType > 0 &&
 793                                                        record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
 794                                                         switch (record->ucRecordType) {
 795                                                         case ATOM_I2C_RECORD_TYPE:
 796                                                                 i2c_record =
 797                                                                     (ATOM_I2C_RECORD *)
 798                                                                         record;
 799                                                                 i2c_config =
 800                                                                         (ATOM_I2C_ID_CONFIG_ACCESS *)
 801                                                                         &i2c_record->sucI2cId;
 802                                                                 ddc_bus = radeon_lookup_i2c_gpio(rdev,
 803                                                                                                  i2c_config->
 804                                                                                                  ucAccess);
 805                                                                 break;
 806                                                         case ATOM_HPD_INT_RECORD_TYPE:
 807                                                                 hpd_record =
 808                                                                         (ATOM_HPD_INT_RECORD *)
 809                                                                         record;
 810                                                                 gpio = radeon_lookup_gpio(rdev,
 811                                                                                           hpd_record->ucHPDIntGPIOID);
 812                                                                 hpd = radeon_atom_get_hpd_info_from_gpio(rdev, &gpio);
 813                                                                 hpd.plugged_state = hpd_record->ucPlugged_PinState;
 814                                                                 break;
 815                                                         }
 816                                                         record =
 817                                                             (ATOM_COMMON_RECORD_HEADER
 818                                                              *) ((char *)record
 819                                                                  +
 820                                                                  record->
 821                                                                  ucRecordSize);
 822                                                 }
 823                                                 break;
 824                                         }
 825                                 }
 826                         }
 827
 828                         /* needed for aux chan transactions */
 829                         ddc_bus.hpd = hpd.hpd;
 830
 831                         conn_id = le16_to_cpu(path->usConnObjectId);
 832
 833                         if (!radeon_atom_apply_quirks
 834                             (dev, le16_to_cpu(path->usDeviceTag), &connector_type,
 835                              &ddc_bus, &conn_id, &hpd))
 836                                 continue;
 837
 838                         radeon_add_atom_connector(dev,
 839                                                   conn_id,
 840                                                   le16_to_cpu(path->
 841                                                               usDeviceTag),
 842                                                   connector_type, &ddc_bus,
 843                                                   igp_lane_info,
 844                                                   connector_object_id,
 845                                                   &hpd,
 846                                                   &router);
 847
 848                 }
 849         }
 850
 851         radeon_link_encoder_connector(dev);
 852
 853         return true;
 854 }
 855
 856 static uint16_t atombios_get_connector_object_id(struct drm_device *dev,
 857                                                  int connector_type,
 858                                                  uint16_t devices)
 859 {
 860         struct radeon_device *rdev = dev->dev_private;
 861
 862         if (rdev->flags & RADEON_IS_IGP) {
 863                 return supported_devices_connector_object_id_convert
 864                         [connector_type];
 865         } else if (((connector_type == DRM_MODE_CONNECTOR_DVII) ||
 866                     (connector_type == DRM_MODE_CONNECTOR_DVID)) &&
 867                    (devices & ATOM_DEVICE_DFP2_SUPPORT))  {
 868                 struct radeon_mode_info *mode_info = &rdev->mode_info;
 869                 struct atom_context *ctx = mode_info->atom_context;
 870                 int index = GetIndexIntoMasterTable(DATA, XTMDS_Info);
 871                 uint16_t size, data_offset;
 872                 uint8_t frev, crev;
 873                 ATOM_XTMDS_INFO *xtmds;
 874
 875                 if (atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset)) {
 876                         xtmds = (ATOM_XTMDS_INFO *)(ctx->bios + data_offset);
 877
 878                         if (xtmds->ucSupportedLink & ATOM_XTMDS_SUPPORTED_DUALLINK) {
 879                                 if (connector_type == DRM_MODE_CONNECTOR_DVII)
 880                                         return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
 881                                 else
 882                                         return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
 883                         } else {
 884                                 if (connector_type == DRM_MODE_CONNECTOR_DVII)
 885                                         return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
 886                                 else
 887                                         return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
 888                         }
 889                 } else
 890                         return supported_devices_connector_object_id_convert
 891                                 [connector_type];
 892         } else {
 893                 return supported_devices_connector_object_id_convert
 894                         [connector_type];
 895         }
 896 }
 897
 898 struct bios_connector {
 899         bool valid;
 900         uint16_t line_mux;
 901         uint16_t devices;
 902         int connector_type;
 903         struct radeon_i2c_bus_rec ddc_bus;
 904         struct radeon_hpd hpd;
 905 };
 906
 907 bool radeon_get_atom_connector_info_from_supported_devices_table(struct
 908                                                                  drm_device
 909                                                                  *dev)
 910 {
 911         struct radeon_device *rdev = dev->dev_private;
 912         struct radeon_mode_info *mode_info = &rdev->mode_info;
 913         struct atom_context *ctx = mode_info->atom_context;
 914         int index = GetIndexIntoMasterTable(DATA, SupportedDevicesInfo);
 915         uint16_t size, data_offset;
 916         uint8_t frev, crev;
 917         uint16_t device_support;
 918         uint8_t dac;
 919         union atom_supported_devices *supported_devices;
 920         int i, j, max_device;
 921         struct bios_connector *bios_connectors;
 922         size_t bc_size = sizeof(*bios_connectors) * ATOM_MAX_SUPPORTED_DEVICE;
 923         struct radeon_router router;
 924
 925         router.ddc_valid = false;
 926         router.cd_valid = false;
 927
 928         bios_connectors = kzalloc(bc_size, GFP_KERNEL);
 929         if (!bios_connectors)
 930                 return false;
 931
 932         if (!atom_parse_data_header(ctx, index, &size, &frev, &crev,
 933                                     &data_offset)) {
 934                 kfree(bios_connectors);
 935                 return false;
 936         }
 937
 938         supported_devices =
 939             (union atom_supported_devices *)(ctx->bios + data_offset);
 940
 941         device_support = le16_to_cpu(supported_devices->info.usDeviceSupport);
 942
 943         if (frev > 1)
 944                 max_device = ATOM_MAX_SUPPORTED_DEVICE;
 945         else
 946                 max_device = ATOM_MAX_SUPPORTED_DEVICE_INFO;
 947
 948         for (i = 0; i < max_device; i++) {
 949                 ATOM_CONNECTOR_INFO_I2C ci =
 950                     supported_devices->info.asConnInfo[i];
 951
 952                 bios_connectors[i].valid = false;
 953
 954                 if (!(device_support & (1 << i))) {
 955                         continue;
 956                 }
 957
 958                 if (i == ATOM_DEVICE_CV_INDEX) {
 959                         DRM_DEBUG_KMS("Skipping Component Video\n");
 960                         continue;
 961                 }
 962
 963                 bios_connectors[i].connector_type =
 964                     supported_devices_connector_convert[ci.sucConnectorInfo.
 965                                                         sbfAccess.
 966                                                         bfConnectorType];
 967
 968                 if (bios_connectors[i].connector_type ==
 969                     DRM_MODE_CONNECTOR_Unknown)
 970                         continue;
 971
 972                 dac = ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC;
 973
 974                 bios_connectors[i].line_mux =
 975                         ci.sucI2cId.ucAccess;
 976
 977                 /* give tv unique connector ids */
 978                 if (i == ATOM_DEVICE_TV1_INDEX) {
 979                         bios_connectors[i].ddc_bus.valid = false;
 980                         bios_connectors[i].line_mux = 50;
 981                 } else if (i == ATOM_DEVICE_TV2_INDEX) {
 982                         bios_connectors[i].ddc_bus.valid = false;
 983                         bios_connectors[i].line_mux = 51;
 984                 } else if (i == ATOM_DEVICE_CV_INDEX) {
 985                         bios_connectors[i].ddc_bus.valid = false;
 986                         bios_connectors[i].line_mux = 52;
 987                 } else
 988                         bios_connectors[i].ddc_bus =
 989                             radeon_lookup_i2c_gpio(rdev,
 990                                                    bios_connectors[i].line_mux);
 991
 992                 if ((crev > 1) && (frev > 1)) {
 993                         u8 isb = supported_devices->info_2d1.asIntSrcInfo[i].ucIntSrcBitmap;
 994                         switch (isb) {
 995                         case 0x4:
 996                                 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
 997                                 break;
 998                         case 0xa:
 999                                 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
1000                                 break;
1001                         default:
1002                                 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
1003                                 break;
1004                         }
1005                 } else {
1006                         if (i == ATOM_DEVICE_DFP1_INDEX)
1007                                 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
1008                         else if (i == ATOM_DEVICE_DFP2_INDEX)
1009                                 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
1010                         else
1011                                 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
1012                 }
1013
1014                 /* Always set the connector type to VGA for CRT1/CRT2. if they are
1015                  * shared with a DVI port, we'll pick up the DVI connector when we
1016                  * merge the outputs.  Some bioses incorrectly list VGA ports as DVI.
1017                  */
1018                 if (i == ATOM_DEVICE_CRT1_INDEX || i == ATOM_DEVICE_CRT2_INDEX)
1019                         bios_connectors[i].connector_type =
1020                             DRM_MODE_CONNECTOR_VGA;
1021
1022                 if (!radeon_atom_apply_quirks
1023                     (dev, (1 << i), &bios_connectors[i].connector_type,
1024                      &bios_connectors[i].ddc_bus, &bios_connectors[i].line_mux,
1025                      &bios_connectors[i].hpd))
1026                         continue;
1027
1028                 bios_connectors[i].valid = true;
1029                 bios_connectors[i].devices = (1 << i);
1030
1031                 if (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)
1032                         radeon_add_atom_encoder(dev,
1033                                                 radeon_get_encoder_enum(dev,
1034                                                                       (1 << i),
1035                                                                       dac),
1036                                                 (1 << i),
1037                                                 0);
1038                 else
1039                         radeon_add_legacy_encoder(dev,
1040                                                   radeon_get_encoder_enum(dev,
1041                                                                         (1 << i),
1042                                                                         dac),
1043                                                   (1 << i));
1044         }
1045
1046         /* combine shared connectors */
1047         for (i = 0; i < max_device; i++) {
1048                 if (bios_connectors[i].valid) {
1049                         for (j = 0; j < max_device; j++) {
1050                                 if (bios_connectors[j].valid && (i != j)) {
1051                                         if (bios_connectors[i].line_mux ==
1052                                             bios_connectors[j].line_mux) {
1053                                                 /* make sure not to combine LVDS */
1054                                                 if (bios_connectors[i].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1055                                                         bios_connectors[i].line_mux = 53;
1056                                                         bios_connectors[i].ddc_bus.valid = false;
1057                                                         continue;
1058                                                 }
1059                                                 if (bios_connectors[j].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1060                                                         bios_connectors[j].line_mux = 53;
1061                                                         bios_connectors[j].ddc_bus.valid = false;
1062                                                         continue;
1063                                                 }
1064                                                 /* combine analog and digital for DVI-I */
1065                                                 if (((bios_connectors[i].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
1066                                                      (bios_connectors[j].devices & (ATOM_DEVICE_CRT_SUPPORT))) ||
1067                                                     ((bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
1068                                                      (bios_connectors[i].devices & (ATOM_DEVICE_CRT_SUPPORT)))) {
1069                                                         bios_connectors[i].devices |=
1070                                                                 bios_connectors[j].devices;
1071                                                         bios_connectors[i].connector_type =
1072                                                                 DRM_MODE_CONNECTOR_DVII;
1073                                                         if (bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT))
1074                                                                 bios_connectors[i].hpd =
1075                                                                         bios_connectors[j].hpd;
1076                                                         bios_connectors[j].valid = false;
1077                                                 }
1078                                         }
1079                                 }
1080                         }
1081                 }
1082         }
1083
1084         /* add the connectors */
1085         for (i = 0; i < max_device; i++) {
1086                 if (bios_connectors[i].valid) {
1087                         uint16_t connector_object_id =
1088                                 atombios_get_connector_object_id(dev,
1089                                                       bios_connectors[i].connector_type,
1090                                                       bios_connectors[i].devices);
1091                         radeon_add_atom_connector(dev,
1092                                                   bios_connectors[i].line_mux,
1093                                                   bios_connectors[i].devices,
1094                                                   bios_connectors[i].
1095                                                   connector_type,
1096                                                   &bios_connectors[i].ddc_bus,
1097                                                   0,
1098                                                   connector_object_id,
1099                                                   &bios_connectors[i].hpd,
1100                                                   &router);
1101                 }
1102         }
1103
1104         radeon_link_encoder_connector(dev);
1105
1106         kfree(bios_connectors);
1107         return true;
1108 }
1109
1110 union firmware_info {
1111         ATOM_FIRMWARE_INFO info;
1112         ATOM_FIRMWARE_INFO_V1_2 info_12;
1113         ATOM_FIRMWARE_INFO_V1_3 info_13;
1114         ATOM_FIRMWARE_INFO_V1_4 info_14;
1115         ATOM_FIRMWARE_INFO_V2_1 info_21;
1116         ATOM_FIRMWARE_INFO_V2_2 info_22;
1117 };
1118
1119 bool radeon_atom_get_clock_info(struct drm_device *dev)
1120 {
1121         struct radeon_device *rdev = dev->dev_private;
1122         struct radeon_mode_info *mode_info = &rdev->mode_info;
1123         int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
1124         union firmware_info *firmware_info;
1125         uint8_t frev, crev;
1126         struct radeon_pll *p1pll = &rdev->clock.p1pll;
1127         struct radeon_pll *p2pll = &rdev->clock.p2pll;
1128         struct radeon_pll *dcpll = &rdev->clock.dcpll;
1129         struct radeon_pll *spll = &rdev->clock.spll;
1130         struct radeon_pll *mpll = &rdev->clock.mpll;
1131         uint16_t data_offset;
1132
1133         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1134                                    &frev, &crev, &data_offset)) {
1135                 firmware_info =
1136                         (union firmware_info *)(mode_info->atom_context->bios +
1137                                                 data_offset);
1138                 /* pixel clocks */
1139                 p1pll->reference_freq =
1140                     le16_to_cpu(firmware_info->info.usReferenceClock);
1141                 p1pll->reference_div = 0;
1142
1143                 if (crev < 2)
1144                         p1pll->pll_out_min =
1145                                 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Output);
1146                 else
1147                         p1pll->pll_out_min =
1148                                 le32_to_cpu(firmware_info->info_12.ulMinPixelClockPLL_Output);
1149                 p1pll->pll_out_max =
1150                     le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output);
1151
1152                 if (crev >= 4) {
1153                         p1pll->lcd_pll_out_min =
1154                                 le16_to_cpu(firmware_info->info_14.usLcdMinPixelClockPLL_Output) * 100;
1155                         if (p1pll->lcd_pll_out_min == 0)
1156                                 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
1157                         p1pll->lcd_pll_out_max =
1158                                 le16_to_cpu(firmware_info->info_14.usLcdMaxPixelClockPLL_Output) * 100;
1159                         if (p1pll->lcd_pll_out_max == 0)
1160                                 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
1161                 } else {
1162                         p1pll->lcd_pll_out_min = p1pll->pll_out_min;
1163                         p1pll->lcd_pll_out_max = p1pll->pll_out_max;
1164                 }
1165
1166                 if (p1pll->pll_out_min == 0) {
1167                         if (ASIC_IS_AVIVO(rdev))
1168                                 p1pll->pll_out_min = 64800;
1169                         else
1170                                 p1pll->pll_out_min = 20000;
1171                 }
1172
1173                 p1pll->pll_in_min =
1174                     le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input);
1175                 p1pll->pll_in_max =
1176                     le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input);
1177
1178                 *p2pll = *p1pll;
1179
1180                 /* system clock */
1181                 if (ASIC_IS_DCE4(rdev))
1182                         spll->reference_freq =
1183                                 le16_to_cpu(firmware_info->info_21.usCoreReferenceClock);
1184                 else
1185                         spll->reference_freq =
1186                                 le16_to_cpu(firmware_info->info.usReferenceClock);
1187                 spll->reference_div = 0;
1188
1189                 spll->pll_out_min =
1190                     le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output);
1191                 spll->pll_out_max =
1192                     le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output);
1193
1194                 /* ??? */
1195                 if (spll->pll_out_min == 0) {
1196                         if (ASIC_IS_AVIVO(rdev))
1197                                 spll->pll_out_min = 64800;
1198                         else
1199                                 spll->pll_out_min = 20000;
1200                 }
1201
1202                 spll->pll_in_min =
1203                     le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input);
1204                 spll->pll_in_max =
1205                     le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input);
1206
1207                 /* memory clock */
1208                 if (ASIC_IS_DCE4(rdev))
1209                         mpll->reference_freq =
1210                                 le16_to_cpu(firmware_info->info_21.usMemoryReferenceClock);
1211                 else
1212                         mpll->reference_freq =
1213                                 le16_to_cpu(firmware_info->info.usReferenceClock);
1214                 mpll->reference_div = 0;
1215
1216                 mpll->pll_out_min =
1217                     le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output);
1218                 mpll->pll_out_max =
1219                     le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output);
1220
1221                 /* ??? */
1222                 if (mpll->pll_out_min == 0) {
1223                         if (ASIC_IS_AVIVO(rdev))
1224                                 mpll->pll_out_min = 64800;
1225                         else
1226                                 mpll->pll_out_min = 20000;
1227                 }
1228
1229                 mpll->pll_in_min =
1230                     le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input);
1231                 mpll->pll_in_max =
1232                     le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input);
1233
1234                 rdev->clock.default_sclk =
1235                     le32_to_cpu(firmware_info->info.ulDefaultEngineClock);
1236                 rdev->clock.default_mclk =
1237                     le32_to_cpu(firmware_info->info.ulDefaultMemoryClock);
1238
1239                 if (ASIC_IS_DCE4(rdev)) {
1240                         rdev->clock.default_dispclk =
1241                                 le32_to_cpu(firmware_info->info_21.ulDefaultDispEngineClkFreq);
1242                         if (rdev->clock.default_dispclk == 0) {
1243                                 if (ASIC_IS_DCE5(rdev))
1244                                         rdev->clock.default_dispclk = 54000; /* 540 Mhz */
1245                                 else
1246                                         rdev->clock.default_dispclk = 60000; /* 600 Mhz */
1247                         }
1248                         rdev->clock.dp_extclk =
1249                                 le16_to_cpu(firmware_info->info_21.usUniphyDPModeExtClkFreq);
1250                 }
1251                 *dcpll = *p1pll;
1252
1253                 rdev->clock.max_pixel_clock = le16_to_cpu(firmware_info->info.usMaxPixelClock);
1254                 if (rdev->clock.max_pixel_clock == 0)
1255                         rdev->clock.max_pixel_clock = 40000;
1256
1257                 return true;
1258         }
1259
1260         return false;
1261 }
1262
1263 union igp_info {
1264         struct _ATOM_INTEGRATED_SYSTEM_INFO info;
1265         struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
1266         struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 info_6;
1267         struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7 info_7;
1268 };
1269
1270 bool radeon_atombios_sideport_present(struct radeon_device *rdev)
1271 {
1272         struct radeon_mode_info *mode_info = &rdev->mode_info;
1273         int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1274         union igp_info *igp_info;
1275         u8 frev, crev;
1276         u16 data_offset;
1277
1278         /* sideport is AMD only */
1279         if (rdev->family == CHIP_RS600)
1280                 return false;
1281
1282         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1283                                    &frev, &crev, &data_offset)) {
1284                 igp_info = (union igp_info *)(mode_info->atom_context->bios +
1285                                       data_offset);
1286                 switch (crev) {
1287                 case 1:
1288                         if (le32_to_cpu(igp_info->info.ulBootUpMemoryClock))
1289                                 return true;
1290                         break;
1291                 case 2:
1292                         if (le32_to_cpu(igp_info->info_2.ulBootUpSidePortClock))
1293                                 return true;
1294                         break;
1295                 default:
1296                         DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
1297                         break;
1298                 }
1299         }
1300         return false;
1301 }
1302
1303 bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
1304                                    struct radeon_encoder_int_tmds *tmds)
1305 {
1306         struct drm_device *dev = encoder->base.dev;
1307         struct radeon_device *rdev = dev->dev_private;
1308         struct radeon_mode_info *mode_info = &rdev->mode_info;
1309         int index = GetIndexIntoMasterTable(DATA, TMDS_Info);
1310         uint16_t data_offset;
1311         struct _ATOM_TMDS_INFO *tmds_info;
1312         uint8_t frev, crev;
1313         uint16_t maxfreq;
1314         int i;
1315
1316         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1317                                    &frev, &crev, &data_offset)) {
1318                 tmds_info =
1319                         (struct _ATOM_TMDS_INFO *)(mode_info->atom_context->bios +
1320                                                    data_offset);
1321
1322                 maxfreq = le16_to_cpu(tmds_info->usMaxFrequency);
1323                 for (i = 0; i < 4; i++) {
1324                         tmds->tmds_pll[i].freq =
1325                             le16_to_cpu(tmds_info->asMiscInfo[i].usFrequency);
1326                         tmds->tmds_pll[i].value =
1327                             tmds_info->asMiscInfo[i].ucPLL_ChargePump & 0x3f;
1328                         tmds->tmds_pll[i].value |=
1329                             (tmds_info->asMiscInfo[i].
1330                              ucPLL_VCO_Gain & 0x3f) << 6;
1331                         tmds->tmds_pll[i].value |=
1332                             (tmds_info->asMiscInfo[i].
1333                              ucPLL_DutyCycle & 0xf) << 12;
1334                         tmds->tmds_pll[i].value |=
1335                             (tmds_info->asMiscInfo[i].
1336                              ucPLL_VoltageSwing & 0xf) << 16;
1337
1338                         DRM_DEBUG_KMS("TMDS PLL From ATOMBIOS %u %x\n",
1339                                   tmds->tmds_pll[i].freq,
1340                                   tmds->tmds_pll[i].value);
1341
1342                         if (maxfreq == tmds->tmds_pll[i].freq) {
1343                                 tmds->tmds_pll[i].freq = 0xffffffff;
1344                                 break;
1345                         }
1346                 }
1347                 return true;
1348         }
1349         return false;
1350 }
1351
1352 bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev,
1353                                       struct radeon_atom_ss *ss,
1354                                       int id)
1355 {
1356         struct radeon_mode_info *mode_info = &rdev->mode_info;
1357         int index = GetIndexIntoMasterTable(DATA, PPLL_SS_Info);
1358         uint16_t data_offset, size;
1359         struct _ATOM_SPREAD_SPECTRUM_INFO *ss_info;
1360         uint8_t frev, crev;
1361         int i, num_indices;
1362
1363         memset(ss, 0, sizeof(struct radeon_atom_ss));
1364         if (atom_parse_data_header(mode_info->atom_context, index, &size,
1365                                    &frev, &crev, &data_offset)) {
1366                 ss_info =
1367                         (struct _ATOM_SPREAD_SPECTRUM_INFO *)(mode_info->atom_context->bios + data_offset);
1368
1369                 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1370                         sizeof(ATOM_SPREAD_SPECTRUM_ASSIGNMENT);
1371
1372                 for (i = 0; i < num_indices; i++) {
1373                         if (ss_info->asSS_Info[i].ucSS_Id == id) {
1374                                 ss->percentage =
1375                                         le16_to_cpu(ss_info->asSS_Info[i].usSpreadSpectrumPercentage);
1376                                 ss->type = ss_info->asSS_Info[i].ucSpreadSpectrumType;
1377                                 ss->step = ss_info->asSS_Info[i].ucSS_Step;
1378                                 ss->delay = ss_info->asSS_Info[i].ucSS_Delay;
1379                                 ss->range = ss_info->asSS_Info[i].ucSS_Range;
1380                                 ss->refdiv = ss_info->asSS_Info[i].ucRecommendedRef_Div;
1381                                 return true;
1382                         }
1383                 }
1384         }
1385         return false;
1386 }
1387
1388 static void radeon_atombios_get_igp_ss_overrides(struct radeon_device *rdev,
1389                                                  struct radeon_atom_ss *ss,
1390                                                  int id)
1391 {
1392         struct radeon_mode_info *mode_info = &rdev->mode_info;
1393         int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1394         u16 data_offset, size;
1395         union igp_info *igp_info;
1396         u8 frev, crev;
1397         u16 percentage = 0, rate = 0;
1398
1399         /* get any igp specific overrides */
1400         if (atom_parse_data_header(mode_info->atom_context, index, &size,
1401                                    &frev, &crev, &data_offset)) {
1402                 igp_info = (union igp_info *)
1403                         (mode_info->atom_context->bios + data_offset);
1404                 switch (crev) {
1405                 case 6:
1406                         switch (id) {
1407                         case ASIC_INTERNAL_SS_ON_TMDS:
1408                                 percentage = le16_to_cpu(igp_info->info_6.usDVISSPercentage);
1409                                 rate = le16_to_cpu(igp_info->info_6.usDVISSpreadRateIn10Hz);
1410                                 break;
1411                         case ASIC_INTERNAL_SS_ON_HDMI:
1412                                 percentage = le16_to_cpu(igp_info->info_6.usHDMISSPercentage);
1413                                 rate = le16_to_cpu(igp_info->info_6.usHDMISSpreadRateIn10Hz);
1414                                 break;
1415                         case ASIC_INTERNAL_SS_ON_LVDS:
1416                                 percentage = le16_to_cpu(igp_info->info_6.usLvdsSSPercentage);
1417                                 rate = le16_to_cpu(igp_info->info_6.usLvdsSSpreadRateIn10Hz);
1418                                 break;
1419                         }
1420                         break;
1421                 case 7:
1422                         switch (id) {
1423                         case ASIC_INTERNAL_SS_ON_TMDS:
1424                                 percentage = le16_to_cpu(igp_info->info_7.usDVISSPercentage);
1425                                 rate = le16_to_cpu(igp_info->info_7.usDVISSpreadRateIn10Hz);
1426                                 break;
1427                         case ASIC_INTERNAL_SS_ON_HDMI:
1428                                 percentage = le16_to_cpu(igp_info->info_7.usHDMISSPercentage);
1429                                 rate = le16_to_cpu(igp_info->info_7.usHDMISSpreadRateIn10Hz);
1430                                 break;
1431                         case ASIC_INTERNAL_SS_ON_LVDS:
1432                                 percentage = le16_to_cpu(igp_info->info_7.usLvdsSSPercentage);
1433                                 rate = le16_to_cpu(igp_info->info_7.usLvdsSSpreadRateIn10Hz);
1434                                 break;
1435                         }
1436                         break;
1437                 default:
1438                         DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
1439                         break;
1440                 }
1441                 if (percentage)
1442                         ss->percentage = percentage;
1443                 if (rate)
1444                         ss->rate = rate;
1445         }
1446 }
1447
1448 union asic_ss_info {
1449         struct _ATOM_ASIC_INTERNAL_SS_INFO info;
1450         struct _ATOM_ASIC_INTERNAL_SS_INFO_V2 info_2;
1451         struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 info_3;
1452 };
1453
1454 bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev,
1455                                       struct radeon_atom_ss *ss,
1456                                       int id, u32 clock)
1457 {
1458         struct radeon_mode_info *mode_info = &rdev->mode_info;
1459         int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info);
1460         uint16_t data_offset, size;
1461         union asic_ss_info *ss_info;
1462         uint8_t frev, crev;
1463         int i, num_indices;
1464
1465         memset(ss, 0, sizeof(struct radeon_atom_ss));
1466         if (atom_parse_data_header(mode_info->atom_context, index, &size,
1467                                    &frev, &crev, &data_offset)) {
1468
1469                 ss_info =
1470                         (union asic_ss_info *)(mode_info->atom_context->bios + data_offset);
1471
1472                 switch (frev) {
1473                 case 1:
1474                         num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1475                                 sizeof(ATOM_ASIC_SS_ASSIGNMENT);
1476
1477                         for (i = 0; i < num_indices; i++) {
1478                                 if ((ss_info->info.asSpreadSpectrum[i].ucClockIndication == id) &&
1479                                     (clock <= le32_to_cpu(ss_info->info.asSpreadSpectrum[i].ulTargetClockRange))) {
1480                                         ss->percentage =
1481                                                 le16_to_cpu(ss_info->info.asSpreadSpectrum[i].usSpreadSpectrumPercentage);
1482                                         ss->type = ss_info->info.asSpreadSpectrum[i].ucSpreadSpectrumMode;
1483                                         ss->rate = le16_to_cpu(ss_info->info.asSpreadSpectrum[i].usSpreadRateInKhz);
1484                                         return true;
1485                                 }
1486                         }
1487                         break;
1488                 case 2:
1489                         num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1490                                 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2);
1491                         for (i = 0; i < num_indices; i++) {
1492                                 if ((ss_info->info_2.asSpreadSpectrum[i].ucClockIndication == id) &&
1493                                     (clock <= le32_to_cpu(ss_info->info_2.asSpreadSpectrum[i].ulTargetClockRange))) {
1494                                         ss->percentage =
1495                                                 le16_to_cpu(ss_info->info_2.asSpreadSpectrum[i].usSpreadSpectrumPercentage);
1496                                         ss->type = ss_info->info_2.asSpreadSpectrum[i].ucSpreadSpectrumMode;
1497                                         ss->rate = le16_to_cpu(ss_info->info_2.asSpreadSpectrum[i].usSpreadRateIn10Hz);
1498                                         return true;
1499                                 }
1500                         }
1501                         break;
1502                 case 3:
1503                         num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1504                                 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3);
1505                         for (i = 0; i < num_indices; i++) {
1506                                 if ((ss_info->info_3.asSpreadSpectrum[i].ucClockIndication == id) &&
1507                                     (clock <= le32_to_cpu(ss_info->info_3.asSpreadSpectrum[i].ulTargetClockRange))) {
1508                                         ss->percentage =
1509                                                 le16_to_cpu(ss_info->info_3.asSpreadSpectrum[i].usSpreadSpectrumPercentage);
1510                                         ss->type = ss_info->info_3.asSpreadSpectrum[i].ucSpreadSpectrumMode;
1511                                         ss->rate = le16_to_cpu(ss_info->info_3.asSpreadSpectrum[i].usSpreadRateIn10Hz);
1512                                         if (rdev->flags & RADEON_IS_IGP)
1513                                                 radeon_atombios_get_igp_ss_overrides(rdev, ss, id);
1514                                         return true;
1515                                 }
1516                         }
1517                         break;
1518                 default:
1519                         DRM_ERROR("Unsupported ASIC_InternalSS_Info table: %d %d\n", frev, crev);
1520                         break;
1521                 }
1522
1523         }
1524         return false;
1525 }
1526
1527 union lvds_info {
1528         struct _ATOM_LVDS_INFO info;
1529         struct _ATOM_LVDS_INFO_V12 info_12;
1530 };
1531
1532 struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct
1533                                                               radeon_encoder
1534                                                               *encoder)
1535 {
1536         struct drm_device *dev = encoder->base.dev;
1537         struct radeon_device *rdev = dev->dev_private;
1538         struct radeon_mode_info *mode_info = &rdev->mode_info;
1539         int index = GetIndexIntoMasterTable(DATA, LVDS_Info);
1540         uint16_t data_offset, misc;
1541         union lvds_info *lvds_info;
1542         uint8_t frev, crev;
1543         struct radeon_encoder_atom_dig *lvds = NULL;
1544         int encoder_enum = (encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
1545
1546         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1547                                    &frev, &crev, &data_offset)) {
1548                 lvds_info =
1549                         (union lvds_info *)(mode_info->atom_context->bios + data_offset);
1550                 lvds =
1551                     kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
1552
1553                 if (!lvds)
1554                         return NULL;
1555
1556                 lvds->native_mode.clock =
1557                     le16_to_cpu(lvds_info->info.sLCDTiming.usPixClk) * 10;
1558                 lvds->native_mode.hdisplay =
1559                     le16_to_cpu(lvds_info->info.sLCDTiming.usHActive);
1560                 lvds->native_mode.vdisplay =
1561                     le16_to_cpu(lvds_info->info.sLCDTiming.usVActive);
1562                 lvds->native_mode.htotal = lvds->native_mode.hdisplay +
1563                         le16_to_cpu(lvds_info->info.sLCDTiming.usHBlanking_Time);
1564                 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
1565                         le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncOffset);
1566                 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
1567                         le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncWidth);
1568                 lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
1569                         le16_to_cpu(lvds_info->info.sLCDTiming.usVBlanking_Time);
1570                 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
1571                         le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncOffset);
1572                 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
1573                         le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth);
1574                 lvds->panel_pwr_delay =
1575                     le16_to_cpu(lvds_info->info.usOffDelayInMs);
1576                 lvds->lcd_misc = lvds_info->info.ucLVDS_Misc;
1577
1578                 misc = le16_to_cpu(lvds_info->info.sLCDTiming.susModeMiscInfo.usAccess);
1579                 if (misc & ATOM_VSYNC_POLARITY)
1580                         lvds->native_mode.flags |= DRM_MODE_FLAG_NVSYNC;
1581                 if (misc & ATOM_HSYNC_POLARITY)
1582                         lvds->native_mode.flags |= DRM_MODE_FLAG_NHSYNC;
1583                 if (misc & ATOM_COMPOSITESYNC)
1584                         lvds->native_mode.flags |= DRM_MODE_FLAG_CSYNC;
1585                 if (misc & ATOM_INTERLACE)
1586                         lvds->native_mode.flags |= DRM_MODE_FLAG_INTERLACE;
1587                 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1588                         lvds->native_mode.flags |= DRM_MODE_FLAG_DBLSCAN;
1589
1590                 lvds->native_mode.width_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageHSize);
1591                 lvds->native_mode.height_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageVSize);
1592
1593                 /* set crtc values */
1594                 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
1595
1596                 lvds->lcd_ss_id = lvds_info->info.ucSS_Id;
1597
1598                 encoder->native_mode = lvds->native_mode;
1599
1600                 if (encoder_enum == 2)
1601                         lvds->linkb = true;
1602                 else
1603                         lvds->linkb = false;
1604
1605                 /* parse the lcd record table */
1606                 if (le16_to_cpu(lvds_info->info.usModePatchTableOffset)) {
1607                         ATOM_FAKE_EDID_PATCH_RECORD *fake_edid_record;
1608                         ATOM_PANEL_RESOLUTION_PATCH_RECORD *panel_res_record;
1609                         bool bad_record = false;
1610                         u8 *record;
1611
1612                         if ((frev == 1) && (crev < 2))
1613                                 /* absolute */
1614                                 record = (u8 *)(mode_info->atom_context->bios +
1615                                                 le16_to_cpu(lvds_info->info.usModePatchTableOffset));
1616                         else
1617                                 /* relative */
1618                                 record = (u8 *)(mode_info->atom_context->bios +
1619                                                 data_offset +
1620                                                 le16_to_cpu(lvds_info->info.usModePatchTableOffset));
1621                         while (*record != ATOM_RECORD_END_TYPE) {
1622                                 switch (*record) {
1623                                 case LCD_MODE_PATCH_RECORD_MODE_TYPE:
1624                                         record += sizeof(ATOM_PATCH_RECORD_MODE);
1625                                         break;
1626                                 case LCD_RTS_RECORD_TYPE:
1627                                         record += sizeof(ATOM_LCD_RTS_RECORD);
1628                                         break;
1629                                 case LCD_CAP_RECORD_TYPE:
1630                                         record += sizeof(ATOM_LCD_MODE_CONTROL_CAP);
1631                                         break;
1632                                 case LCD_FAKE_EDID_PATCH_RECORD_TYPE:
1633                                         fake_edid_record = (ATOM_FAKE_EDID_PATCH_RECORD *)record;
1634                                         if (fake_edid_record->ucFakeEDIDLength) {
1635                                                 struct edid *edid;
1636                                                 int edid_size =
1637                                                         max((int)EDID_LENGTH, (int)fake_edid_record->ucFakeEDIDLength);
1638                                                 edid = kmalloc(edid_size, GFP_KERNEL);
1639                                                 if (edid) {
1640                                                         memcpy((u8 *)edid, (u8 *)&fake_edid_record->ucFakeEDIDString[0],
1641                                                                fake_edid_record->ucFakeEDIDLength);
1642
1643                                                         if (drm_edid_is_valid(edid)) {
1644                                                                 rdev->mode_info.bios_hardcoded_edid = edid;
1645                                                                 rdev->mode_info.bios_hardcoded_edid_size = edid_size;
1646                                                         } else
1647                                                                 kfree(edid);
1648                                                 }
1649                                         }
1650                                         record += sizeof(ATOM_FAKE_EDID_PATCH_RECORD);
1651                                         break;
1652                                 case LCD_PANEL_RESOLUTION_RECORD_TYPE:
1653                                         panel_res_record = (ATOM_PANEL_RESOLUTION_PATCH_RECORD *)record;
1654                                         lvds->native_mode.width_mm = panel_res_record->usHSize;
1655                                         lvds->native_mode.height_mm = panel_res_record->usVSize;
1656                                         record += sizeof(ATOM_PANEL_RESOLUTION_PATCH_RECORD);
1657                                         break;
1658                                 default:
1659                                         DRM_ERROR("Bad LCD record %d\n", *record);
1660                                         bad_record = true;
1661                                         break;
1662                                 }
1663                                 if (bad_record)
1664                                         break;
1665                         }
1666                 }
1667         }
1668         return lvds;
1669 }
1670
1671 struct radeon_encoder_primary_dac *
1672 radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder)
1673 {
1674         struct drm_device *dev = encoder->base.dev;
1675         struct radeon_device *rdev = dev->dev_private;
1676         struct radeon_mode_info *mode_info = &rdev->mode_info;
1677         int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1678         uint16_t data_offset;
1679         struct _COMPASSIONATE_DATA *dac_info;
1680         uint8_t frev, crev;
1681         uint8_t bg, dac;
1682         struct radeon_encoder_primary_dac *p_dac = NULL;
1683
1684         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1685                                    &frev, &crev, &data_offset)) {
1686                 dac_info = (struct _COMPASSIONATE_DATA *)
1687                         (mode_info->atom_context->bios + data_offset);
1688
1689                 p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac), GFP_KERNEL);
1690
1691                 if (!p_dac)
1692                         return NULL;
1693
1694                 bg = dac_info->ucDAC1_BG_Adjustment;
1695                 dac = dac_info->ucDAC1_DAC_Adjustment;
1696                 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
1697
1698         }
1699         return p_dac;
1700 }
1701
1702 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
1703                                 struct drm_display_mode *mode)
1704 {
1705         struct radeon_mode_info *mode_info = &rdev->mode_info;
1706         ATOM_ANALOG_TV_INFO *tv_info;
1707         ATOM_ANALOG_TV_INFO_V1_2 *tv_info_v1_2;
1708         ATOM_DTD_FORMAT *dtd_timings;
1709         int data_index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1710         u8 frev, crev;
1711         u16 data_offset, misc;
1712
1713         if (!atom_parse_data_header(mode_info->atom_context, data_index, NULL,
1714                                     &frev, &crev, &data_offset))
1715                 return false;
1716
1717         switch (crev) {
1718         case 1:
1719                 tv_info = (ATOM_ANALOG_TV_INFO *)(mode_info->atom_context->bios + data_offset);
1720                 if (index >= MAX_SUPPORTED_TV_TIMING)
1721                         return false;
1722
1723                 mode->crtc_htotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Total);
1724                 mode->crtc_hdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Disp);
1725                 mode->crtc_hsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart);
1726                 mode->crtc_hsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart) +
1727                         le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncWidth);
1728
1729                 mode->crtc_vtotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Total);
1730                 mode->crtc_vdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Disp);
1731                 mode->crtc_vsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart);
1732                 mode->crtc_vsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart) +
1733                         le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncWidth);
1734
1735                 mode->flags = 0;
1736                 misc = le16_to_cpu(tv_info->aModeTimings[index].susModeMiscInfo.usAccess);
1737                 if (misc & ATOM_VSYNC_POLARITY)
1738                         mode->flags |= DRM_MODE_FLAG_NVSYNC;
1739                 if (misc & ATOM_HSYNC_POLARITY)
1740                         mode->flags |= DRM_MODE_FLAG_NHSYNC;
1741                 if (misc & ATOM_COMPOSITESYNC)
1742                         mode->flags |= DRM_MODE_FLAG_CSYNC;
1743                 if (misc & ATOM_INTERLACE)
1744                         mode->flags |= DRM_MODE_FLAG_INTERLACE;
1745                 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1746                         mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1747
1748                 mode->clock = le16_to_cpu(tv_info->aModeTimings[index].usPixelClock) * 10;
1749
1750                 if (index == 1) {
1751                         /* PAL timings appear to have wrong values for totals */
1752                         mode->crtc_htotal -= 1;
1753                         mode->crtc_vtotal -= 1;
1754                 }
1755                 break;
1756         case 2:
1757                 tv_info_v1_2 = (ATOM_ANALOG_TV_INFO_V1_2 *)(mode_info->atom_context->bios + data_offset);
1758                 if (index >= MAX_SUPPORTED_TV_TIMING_V1_2)
1759                         return false;
1760
1761                 dtd_timings = &tv_info_v1_2->aModeTimings[index];
1762                 mode->crtc_htotal = le16_to_cpu(dtd_timings->usHActive) +
1763                         le16_to_cpu(dtd_timings->usHBlanking_Time);
1764                 mode->crtc_hdisplay = le16_to_cpu(dtd_timings->usHActive);
1765                 mode->crtc_hsync_start = le16_to_cpu(dtd_timings->usHActive) +
1766                         le16_to_cpu(dtd_timings->usHSyncOffset);
1767                 mode->crtc_hsync_end = mode->crtc_hsync_start +
1768                         le16_to_cpu(dtd_timings->usHSyncWidth);
1769
1770                 mode->crtc_vtotal = le16_to_cpu(dtd_timings->usVActive) +
1771                         le16_to_cpu(dtd_timings->usVBlanking_Time);
1772                 mode->crtc_vdisplay = le16_to_cpu(dtd_timings->usVActive);
1773                 mode->crtc_vsync_start = le16_to_cpu(dtd_timings->usVActive) +
1774                         le16_to_cpu(dtd_timings->usVSyncOffset);
1775                 mode->crtc_vsync_end = mode->crtc_vsync_start +
1776                         le16_to_cpu(dtd_timings->usVSyncWidth);
1777
1778                 mode->flags = 0;
1779                 misc = le16_to_cpu(dtd_timings->susModeMiscInfo.usAccess);
1780                 if (misc & ATOM_VSYNC_POLARITY)
1781                         mode->flags |= DRM_MODE_FLAG_NVSYNC;
1782                 if (misc & ATOM_HSYNC_POLARITY)
1783                         mode->flags |= DRM_MODE_FLAG_NHSYNC;
1784                 if (misc & ATOM_COMPOSITESYNC)
1785                         mode->flags |= DRM_MODE_FLAG_CSYNC;
1786                 if (misc & ATOM_INTERLACE)
1787                         mode->flags |= DRM_MODE_FLAG_INTERLACE;
1788                 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1789                         mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1790
1791                 mode->clock = le16_to_cpu(dtd_timings->usPixClk) * 10;
1792                 break;
1793         }
1794         return true;
1795 }
1796
1797 enum radeon_tv_std
1798 radeon_atombios_get_tv_info(struct radeon_device *rdev)
1799 {
1800         struct radeon_mode_info *mode_info = &rdev->mode_info;
1801         int index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1802         uint16_t data_offset;
1803         uint8_t frev, crev;
1804         struct _ATOM_ANALOG_TV_INFO *tv_info;
1805         enum radeon_tv_std tv_std = TV_STD_NTSC;
1806
1807         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1808                                    &frev, &crev, &data_offset)) {
1809
1810                 tv_info = (struct _ATOM_ANALOG_TV_INFO *)
1811                         (mode_info->atom_context->bios + data_offset);
1812
1813                 switch (tv_info->ucTV_BootUpDefaultStandard) {
1814                 case ATOM_TV_NTSC:
1815                         tv_std = TV_STD_NTSC;
1816                         DRM_DEBUG_KMS("Default TV standard: NTSC\n");
1817                         break;
1818                 case ATOM_TV_NTSCJ:
1819                         tv_std = TV_STD_NTSC_J;
1820                         DRM_DEBUG_KMS("Default TV standard: NTSC-J\n");
1821                         break;
1822                 case ATOM_TV_PAL:
1823                         tv_std = TV_STD_PAL;
1824                         DRM_DEBUG_KMS("Default TV standard: PAL\n");
1825                         break;
1826                 case ATOM_TV_PALM:
1827                         tv_std = TV_STD_PAL_M;
1828                         DRM_DEBUG_KMS("Default TV standard: PAL-M\n");
1829                         break;
1830                 case ATOM_TV_PALN:
1831                         tv_std = TV_STD_PAL_N;
1832                         DRM_DEBUG_KMS("Default TV standard: PAL-N\n");
1833                         break;
1834                 case ATOM_TV_PALCN:
1835                         tv_std = TV_STD_PAL_CN;
1836                         DRM_DEBUG_KMS("Default TV standard: PAL-CN\n");
1837                         break;
1838                 case ATOM_TV_PAL60:
1839                         tv_std = TV_STD_PAL_60;
1840                         DRM_DEBUG_KMS("Default TV standard: PAL-60\n");
1841                         break;
1842                 case ATOM_TV_SECAM:
1843                         tv_std = TV_STD_SECAM;
1844                         DRM_DEBUG_KMS("Default TV standard: SECAM\n");
1845                         break;
1846                 default:
1847                         tv_std = TV_STD_NTSC;
1848                         DRM_DEBUG_KMS("Unknown TV standard; defaulting to NTSC\n");
1849                         break;
1850                 }
1851         }
1852         return tv_std;
1853 }
1854
1855 struct radeon_encoder_tv_dac *
1856 radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder)
1857 {
1858         struct drm_device *dev = encoder->base.dev;
1859         struct radeon_device *rdev = dev->dev_private;
1860         struct radeon_mode_info *mode_info = &rdev->mode_info;
1861         int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1862         uint16_t data_offset;
1863         struct _COMPASSIONATE_DATA *dac_info;
1864         uint8_t frev, crev;
1865         uint8_t bg, dac;
1866         struct radeon_encoder_tv_dac *tv_dac = NULL;
1867
1868         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1869                                    &frev, &crev, &data_offset)) {
1870
1871                 dac_info = (struct _COMPASSIONATE_DATA *)
1872                         (mode_info->atom_context->bios + data_offset);
1873
1874                 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
1875
1876                 if (!tv_dac)
1877                         return NULL;
1878
1879                 bg = dac_info->ucDAC2_CRT2_BG_Adjustment;
1880                 dac = dac_info->ucDAC2_CRT2_DAC_Adjustment;
1881                 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1882
1883                 bg = dac_info->ucDAC2_PAL_BG_Adjustment;
1884                 dac = dac_info->ucDAC2_PAL_DAC_Adjustment;
1885                 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1886
1887                 bg = dac_info->ucDAC2_NTSC_BG_Adjustment;
1888                 dac = dac_info->ucDAC2_NTSC_DAC_Adjustment;
1889                 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1890
1891                 tv_dac->tv_std = radeon_atombios_get_tv_info(rdev);
1892         }
1893         return tv_dac;
1894 }
1895
1896 static const char *thermal_controller_names[] = {
1897         "NONE",
1898         "lm63",
1899         "adm1032",
1900         "adm1030",
1901         "max6649",
1902         "lm64",
1903         "f75375",
1904         "asc7xxx",
1905 };
1906
1907 static const char *pp_lib_thermal_controller_names[] = {
1908         "NONE",
1909         "lm63",
1910         "adm1032",
1911         "adm1030",
1912         "max6649",
1913         "lm64",
1914         "f75375",
1915         "RV6xx",
1916         "RV770",
1917         "adt7473",
1918         "NONE",
1919         "External GPIO",
1920         "Evergreen",
1921         "emc2103",
1922         "Sumo",
1923         "Northern Islands",
1924         "Southern Islands",
1925         "lm96163",
1926 };
1927
1928 union power_info {
1929         struct _ATOM_POWERPLAY_INFO info;
1930         struct _ATOM_POWERPLAY_INFO_V2 info_2;
1931         struct _ATOM_POWERPLAY_INFO_V3 info_3;
1932         struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
1933         struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
1934         struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
1935 };
1936
1937 union pplib_clock_info {
1938         struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
1939         struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
1940         struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
1941         struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
1942         struct _ATOM_PPLIB_SI_CLOCK_INFO si;
1943 };
1944
1945 union pplib_power_state {
1946         struct _ATOM_PPLIB_STATE v1;
1947         struct _ATOM_PPLIB_STATE_V2 v2;
1948 };
1949
1950 static void radeon_atombios_parse_misc_flags_1_3(struct radeon_device *rdev,
1951                                                  int state_index,
1952                                                  u32 misc, u32 misc2)
1953 {
1954         rdev->pm.power_state[state_index].misc = misc;
1955         rdev->pm.power_state[state_index].misc2 = misc2;
1956         /* order matters! */
1957         if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
1958                 rdev->pm.power_state[state_index].type =
1959                         POWER_STATE_TYPE_POWERSAVE;
1960         if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
1961                 rdev->pm.power_state[state_index].type =
1962                         POWER_STATE_TYPE_BATTERY;
1963         if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
1964                 rdev->pm.power_state[state_index].type =
1965                         POWER_STATE_TYPE_BATTERY;
1966         if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
1967                 rdev->pm.power_state[state_index].type =
1968                         POWER_STATE_TYPE_BALANCED;
1969         if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN) {
1970                 rdev->pm.power_state[state_index].type =
1971                         POWER_STATE_TYPE_PERFORMANCE;
1972                 rdev->pm.power_state[state_index].flags &=
1973                         ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1974         }
1975         if (misc2 & ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE)
1976                 rdev->pm.power_state[state_index].type =
1977                         POWER_STATE_TYPE_BALANCED;
1978         if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
1979                 rdev->pm.power_state[state_index].type =
1980                         POWER_STATE_TYPE_DEFAULT;
1981                 rdev->pm.default_power_state_index = state_index;
1982                 rdev->pm.power_state[state_index].default_clock_mode =
1983                         &rdev->pm.power_state[state_index].clock_info[0];
1984         } else if (state_index == 0) {
1985                 rdev->pm.power_state[state_index].clock_info[0].flags |=
1986                         RADEON_PM_MODE_NO_DISPLAY;
1987         }
1988 }
1989
1990 static int radeon_atombios_parse_power_table_1_3(struct radeon_device *rdev)
1991 {
1992         struct radeon_mode_info *mode_info = &rdev->mode_info;
1993         u32 misc, misc2 = 0;
1994         int num_modes = 0, i;
1995         int state_index = 0;
1996         struct radeon_i2c_bus_rec i2c_bus;
1997         union power_info *power_info;
1998         int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
1999         u16 data_offset;
2000         u8 frev, crev;
2001
2002         if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
2003                                    &frev, &crev, &data_offset))
2004                 return state_index;
2005         power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
2006
2007         /* add the i2c bus for thermal/fan chip */
2008         if (power_info->info.ucOverdriveThermalController > 0) {
2009                 DRM_INFO("Possible %s thermal controller at 0x%02x\n",
2010                          thermal_controller_names[power_info->info.ucOverdriveThermalController],
2011                          power_info->info.ucOverdriveControllerAddress >> 1);
2012                 i2c_bus = radeon_lookup_i2c_gpio(rdev, power_info->info.ucOverdriveI2cLine);
2013                 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
2014                 if (rdev->pm.i2c_bus) {
2015                         struct i2c_board_info info = { };
2016                         const char *name = thermal_controller_names[power_info->info.
2017                                                                     ucOverdriveThermalController];
2018                         info.addr = power_info->info.ucOverdriveControllerAddress >> 1;
2019                         strlcpy(info.type, name, sizeof(info.type));
2020                         i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
2021                 }
2022         }
2023         num_modes = power_info->info.ucNumOfPowerModeEntries;
2024         if (num_modes > ATOM_MAX_NUMBEROF_POWER_BLOCK)
2025                 num_modes = ATOM_MAX_NUMBEROF_POWER_BLOCK;
2026         rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) * num_modes, GFP_KERNEL);
2027         if (!rdev->pm.power_state)
2028                 return state_index;
2029         /* last mode is usually default, array is low to high */
2030         for (i = 0; i < num_modes; i++) {
2031                 rdev->pm.power_state[state_index].clock_info =
2032                         kzalloc(sizeof(struct radeon_pm_clock_info) * 1, GFP_KERNEL);
2033                 if (!rdev->pm.power_state[state_index].clock_info)
2034                         return state_index;
2035                 rdev->pm.power_state[state_index].num_clock_modes = 1;
2036                 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2037                 switch (frev) {
2038                 case 1:
2039                         rdev->pm.power_state[state_index].clock_info[0].mclk =
2040                                 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usMemoryClock);
2041                         rdev->pm.power_state[state_index].clock_info[0].sclk =
2042                                 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usEngineClock);
2043                         /* skip invalid modes */
2044                         if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2045                             (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2046                                 continue;
2047                         rdev->pm.power_state[state_index].pcie_lanes =
2048                                 power_info->info.asPowerPlayInfo[i].ucNumPciELanes;
2049                         misc = le32_to_cpu(power_info->info.asPowerPlayInfo[i].ulMiscInfo);
2050                         if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
2051                             (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
2052                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2053                                         VOLTAGE_GPIO;
2054                                 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2055                                         radeon_lookup_gpio(rdev,
2056                                                            power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex);
2057                                 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2058                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2059                                                 true;
2060                                 else
2061                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2062                                                 false;
2063                         } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2064                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2065                                         VOLTAGE_VDDC;
2066                                 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2067                                         power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex;
2068                         }
2069                         rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2070                         radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, 0);
2071                         state_index++;
2072                         break;
2073                 case 2:
2074                         rdev->pm.power_state[state_index].clock_info[0].mclk =
2075                                 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMemoryClock);
2076                         rdev->pm.power_state[state_index].clock_info[0].sclk =
2077                                 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulEngineClock);
2078                         /* skip invalid modes */
2079                         if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2080                             (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2081                                 continue;
2082                         rdev->pm.power_state[state_index].pcie_lanes =
2083                                 power_info->info_2.asPowerPlayInfo[i].ucNumPciELanes;
2084                         misc = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo);
2085                         misc2 = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo2);
2086                         if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
2087                             (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
2088                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2089                                         VOLTAGE_GPIO;
2090                                 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2091                                         radeon_lookup_gpio(rdev,
2092                                                            power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex);
2093                                 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2094                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2095                                                 true;
2096                                 else
2097                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2098                                                 false;
2099                         } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2100                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2101                                         VOLTAGE_VDDC;
2102                                 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2103                                         power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex;
2104                         }
2105                         rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2106                         radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2);
2107                         state_index++;
2108                         break;
2109                 case 3:
2110                         rdev->pm.power_state[state_index].clock_info[0].mclk =
2111                                 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMemoryClock);
2112                         rdev->pm.power_state[state_index].clock_info[0].sclk =
2113                                 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulEngineClock);
2114                         /* skip invalid modes */
2115                         if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2116                             (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2117                                 continue;
2118                         rdev->pm.power_state[state_index].pcie_lanes =
2119                                 power_info->info_3.asPowerPlayInfo[i].ucNumPciELanes;
2120                         misc = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo);
2121                         misc2 = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo2);
2122                         if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
2123                             (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
2124                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2125                                         VOLTAGE_GPIO;
2126                                 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2127                                         radeon_lookup_gpio(rdev,
2128                                                            power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex);
2129                                 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2130                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2131                                                 true;
2132                                 else
2133                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2134                                                 false;
2135                         } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2136                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2137                                         VOLTAGE_VDDC;
2138                                 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2139                                         power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex;
2140                                 if (misc2 & ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN) {
2141                                         rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_enabled =
2142                                                 true;
2143                                         rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_id =
2144                                                 power_info->info_3.asPowerPlayInfo[i].ucVDDCI_VoltageDropIndex;
2145                                 }
2146                         }
2147                         rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2148                         radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2);
2149                         state_index++;
2150                         break;
2151                 }
2152         }
2153         /* last mode is usually default */
2154         if (rdev->pm.default_power_state_index == -1) {
2155                 rdev->pm.power_state[state_index - 1].type =
2156                         POWER_STATE_TYPE_DEFAULT;
2157                 rdev->pm.default_power_state_index = state_index - 1;
2158                 rdev->pm.power_state[state_index - 1].default_clock_mode =
2159                         &rdev->pm.power_state[state_index - 1].clock_info[0];
2160                 rdev->pm.power_state[state_index].flags &=
2161                         ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2162                 rdev->pm.power_state[state_index].misc = 0;
2163                 rdev->pm.power_state[state_index].misc2 = 0;
2164         }
2165         return state_index;
2166 }
2167
2168 static void radeon_atombios_add_pplib_thermal_controller(struct radeon_device *rdev,
2169                                                          ATOM_PPLIB_THERMALCONTROLLER *controller)
2170 {
2171         struct radeon_i2c_bus_rec i2c_bus;
2172
2173         /* add the i2c bus for thermal/fan chip */
2174         if (controller->ucType > 0) {
2175                 if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV6xx) {
2176                         DRM_INFO("Internal thermal controller %s fan control\n",
2177                                  (controller->ucFanParameters &
2178                                   ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2179                         rdev->pm.int_thermal_type = THERMAL_TYPE_RV6XX;
2180                 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV770) {
2181                         DRM_INFO("Internal thermal controller %s fan control\n",
2182                                  (controller->ucFanParameters &
2183                                   ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2184                         rdev->pm.int_thermal_type = THERMAL_TYPE_RV770;
2185                 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_EVERGREEN) {
2186                         DRM_INFO("Internal thermal controller %s fan control\n",
2187                                  (controller->ucFanParameters &
2188                                   ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2189                         rdev->pm.int_thermal_type = THERMAL_TYPE_EVERGREEN;
2190                 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_SUMO) {
2191                         DRM_INFO("Internal thermal controller %s fan control\n",
2192                                  (controller->ucFanParameters &
2193                                   ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2194                         rdev->pm.int_thermal_type = THERMAL_TYPE_SUMO;
2195                 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_NISLANDS) {
2196                         DRM_INFO("Internal thermal controller %s fan control\n",
2197                                  (controller->ucFanParameters &
2198                                   ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2199                         rdev->pm.int_thermal_type = THERMAL_TYPE_NI;
2200                 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_SISLANDS) {
2201                         DRM_INFO("Internal thermal controller %s fan control\n",
2202                                  (controller->ucFanParameters &
2203                                   ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2204                         rdev->pm.int_thermal_type = THERMAL_TYPE_SI;
2205                 } else if ((controller->ucType ==
2206                             ATOM_PP_THERMALCONTROLLER_EXTERNAL_GPIO) ||
2207                            (controller->ucType ==
2208                             ATOM_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL) ||
2209                            (controller->ucType ==
2210                             ATOM_PP_THERMALCONTROLLER_EMC2103_WITH_INTERNAL)) {
2211                         DRM_INFO("Special thermal controller config\n");
2212                 } else {
2213                         DRM_INFO("Possible %s thermal controller at 0x%02x %s fan control\n",
2214                                  pp_lib_thermal_controller_names[controller->ucType],
2215                                  controller->ucI2cAddress >> 1,
2216                                  (controller->ucFanParameters &
2217                                   ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2218                         i2c_bus = radeon_lookup_i2c_gpio(rdev, controller->ucI2cLine);
2219                         rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
2220                         if (rdev->pm.i2c_bus) {
2221                                 struct i2c_board_info info = { };
2222                                 const char *name = pp_lib_thermal_controller_names[controller->ucType];
2223                                 info.addr = controller->ucI2cAddress >> 1;
2224                                 strlcpy(info.type, name, sizeof(info.type));
2225                                 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
2226                         }
2227                 }
2228         }
2229 }
2230
2231 static void radeon_atombios_get_default_voltages(struct radeon_device *rdev,
2232                                                  u16 *vddc, u16 *vddci)
2233 {
2234         struct radeon_mode_info *mode_info = &rdev->mode_info;
2235         int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
2236         u8 frev, crev;
2237         u16 data_offset;
2238         union firmware_info *firmware_info;
2239
2240         *vddc = 0;
2241         *vddci = 0;
2242
2243         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
2244                                    &frev, &crev, &data_offset)) {
2245                 firmware_info =
2246                         (union firmware_info *)(mode_info->atom_context->bios +
2247                                                 data_offset);
2248                 *vddc = le16_to_cpu(firmware_info->info_14.usBootUpVDDCVoltage);
2249                 if ((frev == 2) && (crev >= 2))
2250                         *vddci = le16_to_cpu(firmware_info->info_22.usBootUpVDDCIVoltage);
2251         }
2252 }
2253
2254 static void radeon_atombios_parse_pplib_non_clock_info(struct radeon_device *rdev,
2255                                                        int state_index, int mode_index,
2256                                                        struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info)
2257 {
2258         int j;
2259         u32 misc = le32_to_cpu(non_clock_info->ulCapsAndSettings);
2260         u32 misc2 = le16_to_cpu(non_clock_info->usClassification);
2261         u16 vddc, vddci;
2262
2263         radeon_atombios_get_default_voltages(rdev, &vddc, &vddci);
2264
2265         rdev->pm.power_state[state_index].misc = misc;
2266         rdev->pm.power_state[state_index].misc2 = misc2;
2267         rdev->pm.power_state[state_index].pcie_lanes =
2268                 ((misc & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >>
2269                  ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1;
2270         switch (misc2 & ATOM_PPLIB_CLASSIFICATION_UI_MASK) {
2271         case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY:
2272                 rdev->pm.power_state[state_index].type =
2273                         POWER_STATE_TYPE_BATTERY;
2274                 break;
2275         case ATOM_PPLIB_CLASSIFICATION_UI_BALANCED:
2276                 rdev->pm.power_state[state_index].type =
2277                         POWER_STATE_TYPE_BALANCED;
2278                 break;
2279         case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE:
2280                 rdev->pm.power_state[state_index].type =
2281                         POWER_STATE_TYPE_PERFORMANCE;
2282                 break;
2283         case ATOM_PPLIB_CLASSIFICATION_UI_NONE:
2284                 if (misc2 & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
2285                         rdev->pm.power_state[state_index].type =
2286                                 POWER_STATE_TYPE_PERFORMANCE;
2287                 break;
2288         }
2289         rdev->pm.power_state[state_index].flags = 0;
2290         if (misc & ATOM_PPLIB_SINGLE_DISPLAY_ONLY)
2291                 rdev->pm.power_state[state_index].flags |=
2292                         RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2293         if (misc2 & ATOM_PPLIB_CLASSIFICATION_BOOT) {
2294                 rdev->pm.power_state[state_index].type =
2295                         POWER_STATE_TYPE_DEFAULT;
2296                 rdev->pm.default_power_state_index = state_index;
2297                 rdev->pm.power_state[state_index].default_clock_mode =
2298                         &rdev->pm.power_state[state_index].clock_info[mode_index - 1];
2299                 if (ASIC_IS_DCE5(rdev) && !(rdev->flags & RADEON_IS_IGP)) {
2300                         /* NI chips post without MC ucode, so default clocks are strobe mode only */
2301                         rdev->pm.default_sclk = rdev->pm.power_state[state_index].clock_info[0].sclk;
2302                         rdev->pm.default_mclk = rdev->pm.power_state[state_index].clock_info[0].mclk;
2303                         rdev->pm.default_vddc = rdev->pm.power_state[state_index].clock_info[0].voltage.voltage;
2304                         rdev->pm.default_vddci = rdev->pm.power_state[state_index].clock_info[0].voltage.vddci;
2305                 } else {
2306                         /* patch the table values with the default slck/mclk from firmware info */
2307                         for (j = 0; j < mode_index; j++) {
2308                                 rdev->pm.power_state[state_index].clock_info[j].mclk =
2309                                         rdev->clock.default_mclk;
2310                                 rdev->pm.power_state[state_index].clock_info[j].sclk =
2311                                         rdev->clock.default_sclk;
2312                                 if (vddc)
2313                                         rdev->pm.power_state[state_index].clock_info[j].voltage.voltage =
2314                                                 vddc;
2315                         }
2316                 }
2317         }
2318 }
2319
2320 static bool radeon_atombios_parse_pplib_clock_info(struct radeon_device *rdev,
2321                                                    int state_index, int mode_index,
2322                                                    union pplib_clock_info *clock_info)
2323 {
2324         u32 sclk, mclk;
2325         u16 vddc;
2326
2327         if (rdev->flags & RADEON_IS_IGP) {
2328                 if (rdev->family >= CHIP_PALM) {
2329                         sclk = le16_to_cpu(clock_info->sumo.usEngineClockLow);
2330                         sclk |= clock_info->sumo.ucEngineClockHigh << 16;
2331                         rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2332                 } else {
2333                         sclk = le16_to_cpu(clock_info->rs780.usLowEngineClockLow);
2334                         sclk |= clock_info->rs780.ucLowEngineClockHigh << 16;
2335                         rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2336                 }
2337         } else if (ASIC_IS_DCE6(rdev)) {
2338                 sclk = le16_to_cpu(clock_info->si.usEngineClockLow);
2339                 sclk |= clock_info->si.ucEngineClockHigh << 16;
2340                 mclk = le16_to_cpu(clock_info->si.usMemoryClockLow);
2341                 mclk |= clock_info->si.ucMemoryClockHigh << 16;
2342                 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2343                 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2344                 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2345                         VOLTAGE_SW;
2346                 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2347                         le16_to_cpu(clock_info->si.usVDDC);
2348                 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.vddci =
2349                         le16_to_cpu(clock_info->si.usVDDCI);
2350         } else if (ASIC_IS_DCE4(rdev)) {
2351                 sclk = le16_to_cpu(clock_info->evergreen.usEngineClockLow);
2352                 sclk |= clock_info->evergreen.ucEngineClockHigh << 16;
2353                 mclk = le16_to_cpu(clock_info->evergreen.usMemoryClockLow);
2354                 mclk |= clock_info->evergreen.ucMemoryClockHigh << 16;
2355                 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2356                 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2357                 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2358                         VOLTAGE_SW;
2359                 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2360                         le16_to_cpu(clock_info->evergreen.usVDDC);
2361                 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.vddci =
2362                         le16_to_cpu(clock_info->evergreen.usVDDCI);
2363         } else {
2364                 sclk = le16_to_cpu(clock_info->r600.usEngineClockLow);
2365                 sclk |= clock_info->r600.ucEngineClockHigh << 16;
2366                 mclk = le16_to_cpu(clock_info->r600.usMemoryClockLow);
2367                 mclk |= clock_info->r600.ucMemoryClockHigh << 16;
2368                 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2369                 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2370                 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2371                         VOLTAGE_SW;
2372                 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2373                         le16_to_cpu(clock_info->r600.usVDDC);
2374         }
2375
2376         /* patch up vddc if necessary */
2377         switch (rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage) {
2378         case ATOM_VIRTUAL_VOLTAGE_ID0:
2379         case ATOM_VIRTUAL_VOLTAGE_ID1:
2380         case ATOM_VIRTUAL_VOLTAGE_ID2:
2381         case ATOM_VIRTUAL_VOLTAGE_ID3:
2382                 if (radeon_atom_get_max_vddc(rdev, VOLTAGE_TYPE_VDDC,
2383                                              rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage,
2384                                              &vddc) == 0)
2385                         rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage = vddc;
2386                 break;
2387         default:
2388                 break;
2389         }
2390
2391         if (rdev->flags & RADEON_IS_IGP) {
2392                 /* skip invalid modes */
2393                 if (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0)
2394                         return false;
2395         } else {
2396                 /* skip invalid modes */
2397                 if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk == 0) ||
2398                     (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0))
2399                         return false;
2400         }
2401         return true;
2402 }
2403
2404 static int radeon_atombios_parse_power_table_4_5(struct radeon_device *rdev)
2405 {
2406         struct radeon_mode_info *mode_info = &rdev->mode_info;
2407         struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
2408         union pplib_power_state *power_state;
2409         int i, j;
2410         int state_index = 0, mode_index = 0;
2411         union pplib_clock_info *clock_info;
2412         bool valid;
2413         union power_info *power_info;
2414         int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2415         u16 data_offset;
2416         u8 frev, crev;
2417
2418         if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
2419                                    &frev, &crev, &data_offset))
2420                 return state_index;
2421         power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
2422
2423         radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController);
2424         rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) *
2425                                        power_info->pplib.ucNumStates, GFP_KERNEL);
2426         if (!rdev->pm.power_state)
2427                 return state_index;
2428         /* first mode is usually default, followed by low to high */
2429         for (i = 0; i < power_info->pplib.ucNumStates; i++) {
2430                 mode_index = 0;
2431                 power_state = (union pplib_power_state *)
2432                         (mode_info->atom_context->bios + data_offset +
2433                          le16_to_cpu(power_info->pplib.usStateArrayOffset) +
2434                          i * power_info->pplib.ucStateEntrySize);
2435                 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
2436                         (mode_info->atom_context->bios + data_offset +
2437                          le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset) +
2438                          (power_state->v1.ucNonClockStateIndex *
2439                           power_info->pplib.ucNonClockSize));
2440                 rdev->pm.power_state[i].clock_info = kzalloc(sizeof(struct radeon_pm_clock_info) *
2441                                                              ((power_info->pplib.ucStateEntrySize - 1) ?
2442                                                               (power_info->pplib.ucStateEntrySize - 1) : 1),
2443                                                              GFP_KERNEL);
2444                 if (!rdev->pm.power_state[i].clock_info)
2445                         return state_index;
2446                 if (power_info->pplib.ucStateEntrySize - 1) {
2447                         for (j = 0; j < (power_info->pplib.ucStateEntrySize - 1); j++) {
2448                                 clock_info = (union pplib_clock_info *)
2449                                         (mode_info->atom_context->bios + data_offset +
2450                                          le16_to_cpu(power_info->pplib.usClockInfoArrayOffset) +
2451                                          (power_state->v1.ucClockStateIndices[j] *
2452                                           power_info->pplib.ucClockInfoSize));
2453                                 valid = radeon_atombios_parse_pplib_clock_info(rdev,
2454                                                                                state_index, mode_index,
2455                                                                                clock_info);
2456                                 if (valid)
2457                                         mode_index++;
2458                         }
2459                 } else {
2460                         rdev->pm.power_state[state_index].clock_info[0].mclk =
2461                                 rdev->clock.default_mclk;
2462                         rdev->pm.power_state[state_index].clock_info[0].sclk =
2463                                 rdev->clock.default_sclk;
2464                         mode_index++;
2465                 }
2466                 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
2467                 if (mode_index) {
2468                         radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index,
2469                                                                    non_clock_info);
2470                         state_index++;
2471                 }
2472         }
2473         /* if multiple clock modes, mark the lowest as no display */
2474         for (i = 0; i < state_index; i++) {
2475                 if (rdev->pm.power_state[i].num_clock_modes > 1)
2476                         rdev->pm.power_state[i].clock_info[0].flags |=
2477                                 RADEON_PM_MODE_NO_DISPLAY;
2478         }
2479         /* first mode is usually default */
2480         if (rdev->pm.default_power_state_index == -1) {
2481                 rdev->pm.power_state[0].type =
2482                         POWER_STATE_TYPE_DEFAULT;
2483                 rdev->pm.default_power_state_index = 0;
2484                 rdev->pm.power_state[0].default_clock_mode =
2485                         &rdev->pm.power_state[0].clock_info[0];
2486         }
2487         return state_index;
2488 }
2489
2490 static int radeon_atombios_parse_power_table_6(struct radeon_device *rdev)
2491 {
2492         struct radeon_mode_info *mode_info = &rdev->mode_info;
2493         struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
2494         union pplib_power_state *power_state;
2495         int i, j, non_clock_array_index, clock_array_index;
2496         int state_index = 0, mode_index = 0;
2497         union pplib_clock_info *clock_info;
2498         struct _StateArray *state_array;
2499         struct _ClockInfoArray *clock_info_array;
2500         struct _NonClockInfoArray *non_clock_info_array;
2501         bool valid;
2502         union power_info *power_info;
2503         int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2504         u16 data_offset;
2505         u8 frev, crev;
2506
2507         if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
2508                                    &frev, &crev, &data_offset))
2509                 return state_index;
2510         power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
2511
2512         radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController);
2513         state_array = (struct _StateArray *)
2514                 (mode_info->atom_context->bios + data_offset +
2515                  le16_to_cpu(power_info->pplib.usStateArrayOffset));
2516         clock_info_array = (struct _ClockInfoArray *)
2517                 (mode_info->atom_context->bios + data_offset +
2518                  le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
2519         non_clock_info_array = (struct _NonClockInfoArray *)
2520                 (mode_info->atom_context->bios + data_offset +
2521                  le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
2522         rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) *
2523                                        state_array->ucNumEntries, GFP_KERNEL);
2524         if (!rdev->pm.power_state)
2525                 return state_index;
2526         for (i = 0; i < state_array->ucNumEntries; i++) {
2527                 mode_index = 0;
2528                 power_state = (union pplib_power_state *)&state_array->states[i];
2529                 /* XXX this might be an inagua bug... */
2530                 non_clock_array_index = i; /* power_state->v2.nonClockInfoIndex */
2531                 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
2532                         &non_clock_info_array->nonClockInfo[non_clock_array_index];
2533                 rdev->pm.power_state[i].clock_info = kzalloc(sizeof(struct radeon_pm_clock_info) *
2534                                                              (power_state->v2.ucNumDPMLevels ?
2535                                                               power_state->v2.ucNumDPMLevels : 1),
2536                                                              GFP_KERNEL);
2537                 if (!rdev->pm.power_state[i].clock_info)
2538                         return state_index;
2539                 if (power_state->v2.ucNumDPMLevels) {
2540                         for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
2541                                 clock_array_index = power_state->v2.clockInfoIndex[j];
2542                                 /* XXX this might be an inagua bug... */
2543                                 if (clock_array_index >= clock_info_array->ucNumEntries)
2544                                         continue;
2545                                 clock_info = (union pplib_clock_info *)
2546                                         &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize];
2547                                 valid = radeon_atombios_parse_pplib_clock_info(rdev,
2548                                                                                state_index, mode_index,
2549                                                                                clock_info);
2550                                 if (valid)
2551                                         mode_index++;
2552                         }
2553                 } else {
2554                         rdev->pm.power_state[state_index].clock_info[0].mclk =
2555                                 rdev->clock.default_mclk;
2556                         rdev->pm.power_state[state_index].clock_info[0].sclk =
2557                                 rdev->clock.default_sclk;
2558                         mode_index++;
2559                 }
2560                 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
2561                 if (mode_index) {
2562                         radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index,
2563                                                                    non_clock_info);
2564                         state_index++;
2565                 }
2566         }
2567         /* if multiple clock modes, mark the lowest as no display */
2568         for (i = 0; i < state_index; i++) {
2569                 if (rdev->pm.power_state[i].num_clock_modes > 1)
2570                         rdev->pm.power_state[i].clock_info[0].flags |=
2571                                 RADEON_PM_MODE_NO_DISPLAY;
2572         }
2573         /* first mode is usually default */
2574         if (rdev->pm.default_power_state_index == -1) {
2575                 rdev->pm.power_state[0].type =
2576                         POWER_STATE_TYPE_DEFAULT;
2577                 rdev->pm.default_power_state_index = 0;
2578                 rdev->pm.power_state[0].default_clock_mode =
2579                         &rdev->pm.power_state[0].clock_info[0];
2580         }
2581         return state_index;
2582 }
2583
2584 void radeon_atombios_get_power_modes(struct radeon_device *rdev)
2585 {
2586         struct radeon_mode_info *mode_info = &rdev->mode_info;
2587         int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2588         u16 data_offset;
2589         u8 frev, crev;
2590         int state_index = 0;
2591
2592         rdev->pm.default_power_state_index = -1;
2593
2594         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
2595                                    &frev, &crev, &data_offset)) {
2596                 switch (frev) {
2597                 case 1:
2598                 case 2:
2599                 case 3:
2600                         state_index = radeon_atombios_parse_power_table_1_3(rdev);
2601                         break;
2602                 case 4:
2603                 case 5:
2604                         state_index = radeon_atombios_parse_power_table_4_5(rdev);
2605                         break;
2606                 case 6:
2607                         state_index = radeon_atombios_parse_power_table_6(rdev);
2608                         break;
2609                 default:
2610                         break;
2611                 }
2612         } else {
2613                 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state), GFP_KERNEL);
2614                 if (rdev->pm.power_state) {
2615                         rdev->pm.power_state[0].clock_info =
2616                                 kzalloc(sizeof(struct radeon_pm_clock_info) * 1, GFP_KERNEL);
2617                         if (rdev->pm.power_state[0].clock_info) {
2618                                 /* add the default mode */
2619                                 rdev->pm.power_state[state_index].type =
2620                                         POWER_STATE_TYPE_DEFAULT;
2621                                 rdev->pm.power_state[state_index].num_clock_modes = 1;
2622                                 rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
2623                                 rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
2624                                 rdev->pm.power_state[state_index].default_clock_mode =
2625                                         &rdev->pm.power_state[state_index].clock_info[0];
2626                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2627                                 rdev->pm.power_state[state_index].pcie_lanes = 16;
2628                                 rdev->pm.default_power_state_index = state_index;
2629                                 rdev->pm.power_state[state_index].flags = 0;
2630                                 state_index++;
2631                         }
2632                 }
2633         }
2634
2635         rdev->pm.num_power_states = state_index;
2636
2637         rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
2638         rdev->pm.current_clock_mode_index = 0;
2639         if (rdev->pm.default_power_state_index >= 0)
2640                 rdev->pm.current_vddc =
2641                         rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
2642         else
2643                 rdev->pm.current_vddc = 0;
2644 }
2645
2646 void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable)
2647 {
2648         DYNAMIC_CLOCK_GATING_PS_ALLOCATION args;
2649         int index = GetIndexIntoMasterTable(COMMAND, DynamicClockGating);
2650
2651         args.ucEnable = enable;
2652
2653         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2654 }
2655
2656 uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev)
2657 {
2658         GET_ENGINE_CLOCK_PS_ALLOCATION args;
2659         int index = GetIndexIntoMasterTable(COMMAND, GetEngineClock);
2660
2661         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2662         return le32_to_cpu(args.ulReturnEngineClock);
2663 }
2664
2665 uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev)
2666 {
2667         GET_MEMORY_CLOCK_PS_ALLOCATION args;
2668         int index = GetIndexIntoMasterTable(COMMAND, GetMemoryClock);
2669
2670         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2671         return le32_to_cpu(args.ulReturnMemoryClock);
2672 }
2673
2674 void radeon_atom_set_engine_clock(struct radeon_device *rdev,
2675                                   uint32_t eng_clock)
2676 {
2677         SET_ENGINE_CLOCK_PS_ALLOCATION args;
2678         int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock);
2679
2680         args.ulTargetEngineClock = cpu_to_le32(eng_clock);      /* 10 khz */
2681
2682         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2683 }
2684
2685 void radeon_atom_set_memory_clock(struct radeon_device *rdev,
2686                                   uint32_t mem_clock)
2687 {
2688         SET_MEMORY_CLOCK_PS_ALLOCATION args;
2689         int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock);
2690
2691         if (rdev->flags & RADEON_IS_IGP)
2692                 return;
2693
2694         args.ulTargetMemoryClock = cpu_to_le32(mem_clock);      /* 10 khz */
2695
2696         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2697 }
2698
2699 union set_voltage {
2700         struct _SET_VOLTAGE_PS_ALLOCATION alloc;
2701         struct _SET_VOLTAGE_PARAMETERS v1;
2702         struct _SET_VOLTAGE_PARAMETERS_V2 v2;
2703         struct _SET_VOLTAGE_PARAMETERS_V1_3 v3;
2704 };
2705
2706 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type)
2707 {
2708         union set_voltage args;
2709         int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
2710         u8 frev, crev, volt_index = voltage_level;
2711
2712         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2713                 return;
2714
2715         /* 0xff01 is a flag rather then an actual voltage */
2716         if (voltage_level == 0xff01)
2717                 return;
2718
2719         switch (crev) {
2720         case 1:
2721                 args.v1.ucVoltageType = voltage_type;
2722                 args.v1.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_ALL_SOURCE;
2723                 args.v1.ucVoltageIndex = volt_index;
2724                 break;
2725         case 2:
2726                 args.v2.ucVoltageType = voltage_type;
2727                 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE;
2728                 args.v2.usVoltageLevel = cpu_to_le16(voltage_level);
2729                 break;
2730         case 3:
2731                 args.v3.ucVoltageType = voltage_type;
2732                 args.v3.ucVoltageMode = ATOM_SET_VOLTAGE;
2733                 args.v3.usVoltageLevel = cpu_to_le16(voltage_level);
2734                 break;
2735         default:
2736                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
2737                 return;
2738         }
2739
2740         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2741 }
2742
2743 static int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
2744                                     u16 voltage_id, u16 *voltage)
2745 {
2746         union set_voltage args;
2747         int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
2748         u8 frev, crev;
2749
2750         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2751                 return -EINVAL;
2752
2753         switch (crev) {
2754         case 1:
2755                 return -EINVAL;
2756         case 2:
2757                 args.v2.ucVoltageType = SET_VOLTAGE_GET_MAX_VOLTAGE;
2758                 args.v2.ucVoltageMode = 0;
2759                 args.v2.usVoltageLevel = 0;
2760
2761                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2762
2763                 *voltage = le16_to_cpu(args.v2.usVoltageLevel);
2764                 break;
2765         case 3:
2766                 args.v3.ucVoltageType = voltage_type;
2767                 args.v3.ucVoltageMode = ATOM_GET_VOLTAGE_LEVEL;
2768                 args.v3.usVoltageLevel = cpu_to_le16(voltage_id);
2769
2770                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2771
2772                 *voltage = le16_to_cpu(args.v3.usVoltageLevel);
2773                 break;
2774         default:
2775                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
2776                 return -EINVAL;
2777         }
2778
2779         return 0;
2780 }
2781
2782 void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev)
2783 {
2784         struct radeon_device *rdev = dev->dev_private;
2785         uint32_t bios_2_scratch, bios_6_scratch;
2786
2787         if (rdev->family >= CHIP_R600) {
2788                 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
2789                 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
2790         } else {
2791                 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
2792                 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2793         }
2794
2795         /* let the bios control the backlight */
2796         bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE;
2797
2798         /* tell the bios not to handle mode switching */
2799         bios_6_scratch |= ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH;
2800
2801         if (rdev->family >= CHIP_R600) {
2802                 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
2803                 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
2804         } else {
2805                 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
2806                 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2807         }
2808
2809 }
2810
2811 void radeon_save_bios_scratch_regs(struct radeon_device *rdev)
2812 {
2813         uint32_t scratch_reg;
2814         int i;
2815
2816         if (rdev->family >= CHIP_R600)
2817                 scratch_reg = R600_BIOS_0_SCRATCH;
2818         else
2819                 scratch_reg = RADEON_BIOS_0_SCRATCH;
2820
2821         for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
2822                 rdev->bios_scratch[i] = RREG32(scratch_reg + (i * 4));
2823 }
2824
2825 void radeon_restore_bios_scratch_regs(struct radeon_device *rdev)
2826 {
2827         uint32_t scratch_reg;
2828         int i;
2829
2830         if (rdev->family >= CHIP_R600)
2831                 scratch_reg = R600_BIOS_0_SCRATCH;
2832         else
2833                 scratch_reg = RADEON_BIOS_0_SCRATCH;
2834
2835         for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
2836                 WREG32(scratch_reg + (i * 4), rdev->bios_scratch[i]);
2837 }
2838
2839 void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock)
2840 {
2841         struct drm_device *dev = encoder->dev;
2842         struct radeon_device *rdev = dev->dev_private;
2843         uint32_t bios_6_scratch;
2844
2845         if (rdev->family >= CHIP_R600)
2846                 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
2847         else
2848                 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2849
2850         if (lock) {
2851                 bios_6_scratch |= ATOM_S6_CRITICAL_STATE;
2852                 bios_6_scratch &= ~ATOM_S6_ACC_MODE;
2853         } else {
2854                 bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE;
2855                 bios_6_scratch |= ATOM_S6_ACC_MODE;
2856         }
2857
2858         if (rdev->family >= CHIP_R600)
2859                 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
2860         else
2861                 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2862 }
2863
2864 /* at some point we may want to break this out into individual functions */
2865 void
2866 radeon_atombios_connected_scratch_regs(struct drm_connector *connector,
2867                                        struct drm_encoder *encoder,
2868                                        bool connected)
2869 {
2870         struct drm_device *dev = connector->dev;
2871         struct radeon_device *rdev = dev->dev_private;
2872         struct radeon_connector *radeon_connector =
2873             to_radeon_connector(connector);
2874         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2875         uint32_t bios_0_scratch, bios_3_scratch, bios_6_scratch;
2876
2877         if (rdev->family >= CHIP_R600) {
2878                 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2879                 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
2880                 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
2881         } else {
2882                 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
2883                 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
2884                 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2885         }
2886
2887         if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
2888             (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
2889                 if (connected) {
2890                         DRM_DEBUG_KMS("TV1 connected\n");
2891                         bios_3_scratch |= ATOM_S3_TV1_ACTIVE;
2892                         bios_6_scratch |= ATOM_S6_ACC_REQ_TV1;
2893                 } else {
2894                         DRM_DEBUG_KMS("TV1 disconnected\n");
2895                         bios_0_scratch &= ~ATOM_S0_TV1_MASK;
2896                         bios_3_scratch &= ~ATOM_S3_TV1_ACTIVE;
2897                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_TV1;
2898                 }
2899         }
2900         if ((radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) &&
2901             (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT)) {
2902                 if (connected) {
2903                         DRM_DEBUG_KMS("CV connected\n");
2904                         bios_3_scratch |= ATOM_S3_CV_ACTIVE;
2905                         bios_6_scratch |= ATOM_S6_ACC_REQ_CV;
2906                 } else {
2907                         DRM_DEBUG_KMS("CV disconnected\n");
2908                         bios_0_scratch &= ~ATOM_S0_CV_MASK;
2909                         bios_3_scratch &= ~ATOM_S3_CV_ACTIVE;
2910                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_CV;
2911                 }
2912         }
2913         if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
2914             (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
2915                 if (connected) {
2916                         DRM_DEBUG_KMS("LCD1 connected\n");
2917                         bios_0_scratch |= ATOM_S0_LCD1;
2918                         bios_3_scratch |= ATOM_S3_LCD1_ACTIVE;
2919                         bios_6_scratch |= ATOM_S6_ACC_REQ_LCD1;
2920                 } else {
2921                         DRM_DEBUG_KMS("LCD1 disconnected\n");
2922                         bios_0_scratch &= ~ATOM_S0_LCD1;
2923                         bios_3_scratch &= ~ATOM_S3_LCD1_ACTIVE;
2924                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_LCD1;
2925                 }
2926         }
2927         if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
2928             (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
2929                 if (connected) {
2930                         DRM_DEBUG_KMS("CRT1 connected\n");
2931                         bios_0_scratch |= ATOM_S0_CRT1_COLOR;
2932                         bios_3_scratch |= ATOM_S3_CRT1_ACTIVE;
2933                         bios_6_scratch |= ATOM_S6_ACC_REQ_CRT1;
2934                 } else {
2935                         DRM_DEBUG_KMS("CRT1 disconnected\n");
2936                         bios_0_scratch &= ~ATOM_S0_CRT1_MASK;
2937                         bios_3_scratch &= ~ATOM_S3_CRT1_ACTIVE;
2938                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT1;
2939                 }
2940         }
2941         if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
2942             (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
2943                 if (connected) {
2944                         DRM_DEBUG_KMS("CRT2 connected\n");
2945                         bios_0_scratch |= ATOM_S0_CRT2_COLOR;
2946                         bios_3_scratch |= ATOM_S3_CRT2_ACTIVE;
2947                         bios_6_scratch |= ATOM_S6_ACC_REQ_CRT2;
2948                 } else {
2949                         DRM_DEBUG_KMS("CRT2 disconnected\n");
2950                         bios_0_scratch &= ~ATOM_S0_CRT2_MASK;
2951                         bios_3_scratch &= ~ATOM_S3_CRT2_ACTIVE;
2952                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT2;
2953                 }
2954         }
2955         if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
2956             (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
2957                 if (connected) {
2958                         DRM_DEBUG_KMS("DFP1 connected\n");
2959                         bios_0_scratch |= ATOM_S0_DFP1;
2960                         bios_3_scratch |= ATOM_S3_DFP1_ACTIVE;
2961                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP1;
2962                 } else {
2963                         DRM_DEBUG_KMS("DFP1 disconnected\n");
2964                         bios_0_scratch &= ~ATOM_S0_DFP1;
2965                         bios_3_scratch &= ~ATOM_S3_DFP1_ACTIVE;
2966                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP1;
2967                 }
2968         }
2969         if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
2970             (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
2971                 if (connected) {
2972                         DRM_DEBUG_KMS("DFP2 connected\n");
2973                         bios_0_scratch |= ATOM_S0_DFP2;
2974                         bios_3_scratch |= ATOM_S3_DFP2_ACTIVE;
2975                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP2;
2976                 } else {
2977                         DRM_DEBUG_KMS("DFP2 disconnected\n");
2978                         bios_0_scratch &= ~ATOM_S0_DFP2;
2979                         bios_3_scratch &= ~ATOM_S3_DFP2_ACTIVE;
2980                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP2;
2981                 }
2982         }
2983         if ((radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) &&
2984             (radeon_connector->devices & ATOM_DEVICE_DFP3_SUPPORT)) {
2985                 if (connected) {
2986                         DRM_DEBUG_KMS("DFP3 connected\n");
2987                         bios_0_scratch |= ATOM_S0_DFP3;
2988                         bios_3_scratch |= ATOM_S3_DFP3_ACTIVE;
2989                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP3;
2990                 } else {
2991                         DRM_DEBUG_KMS("DFP3 disconnected\n");
2992                         bios_0_scratch &= ~ATOM_S0_DFP3;
2993                         bios_3_scratch &= ~ATOM_S3_DFP3_ACTIVE;
2994                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP3;
2995                 }
2996         }
2997         if ((radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) &&
2998             (radeon_connector->devices & ATOM_DEVICE_DFP4_SUPPORT)) {
2999                 if (connected) {
3000                         DRM_DEBUG_KMS("DFP4 connected\n");
3001                         bios_0_scratch |= ATOM_S0_DFP4;
3002                         bios_3_scratch |= ATOM_S3_DFP4_ACTIVE;
3003                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP4;
3004                 } else {
3005                         DRM_DEBUG_KMS("DFP4 disconnected\n");
3006                         bios_0_scratch &= ~ATOM_S0_DFP4;
3007                         bios_3_scratch &= ~ATOM_S3_DFP4_ACTIVE;
3008                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP4;
3009                 }
3010         }
3011         if ((radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) &&
3012             (radeon_connector->devices & ATOM_DEVICE_DFP5_SUPPORT)) {
3013                 if (connected) {
3014                         DRM_DEBUG_KMS("DFP5 connected\n");
3015                         bios_0_scratch |= ATOM_S0_DFP5;
3016                         bios_3_scratch |= ATOM_S3_DFP5_ACTIVE;
3017                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP5;
3018                 } else {
3019                         DRM_DEBUG_KMS("DFP5 disconnected\n");
3020                         bios_0_scratch &= ~ATOM_S0_DFP5;
3021                         bios_3_scratch &= ~ATOM_S3_DFP5_ACTIVE;
3022                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP5;
3023                 }
3024         }
3025         if ((radeon_encoder->devices & ATOM_DEVICE_DFP6_SUPPORT) &&
3026             (radeon_connector->devices & ATOM_DEVICE_DFP6_SUPPORT)) {
3027                 if (connected) {
3028                         DRM_DEBUG_KMS("DFP6 connected\n");
3029                         bios_0_scratch |= ATOM_S0_DFP6;
3030                         bios_3_scratch |= ATOM_S3_DFP6_ACTIVE;
3031                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP6;
3032                 } else {
3033                         DRM_DEBUG_KMS("DFP6 disconnected\n");
3034                         bios_0_scratch &= ~ATOM_S0_DFP6;
3035                         bios_3_scratch &= ~ATOM_S3_DFP6_ACTIVE;
3036                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP6;
3037                 }
3038         }
3039
3040         if (rdev->family >= CHIP_R600) {
3041                 WREG32(R600_BIOS_0_SCRATCH, bios_0_scratch);
3042                 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
3043                 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
3044         } else {
3045                 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
3046                 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
3047                 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
3048         }
3049 }
3050
3051 void
3052 radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
3053 {
3054         struct drm_device *dev = encoder->dev;
3055         struct radeon_device *rdev = dev->dev_private;
3056         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3057         uint32_t bios_3_scratch;
3058
3059         if (ASIC_IS_DCE4(rdev))
3060                 return;
3061
3062         if (rdev->family >= CHIP_R600)
3063                 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
3064         else
3065                 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
3066
3067         if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
3068                 bios_3_scratch &= ~ATOM_S3_TV1_CRTC_ACTIVE;
3069                 bios_3_scratch |= (crtc << 18);
3070         }
3071         if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
3072                 bios_3_scratch &= ~ATOM_S3_CV_CRTC_ACTIVE;
3073                 bios_3_scratch |= (crtc << 24);
3074         }
3075         if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
3076                 bios_3_scratch &= ~ATOM_S3_CRT1_CRTC_ACTIVE;
3077                 bios_3_scratch |= (crtc << 16);
3078         }
3079         if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
3080                 bios_3_scratch &= ~ATOM_S3_CRT2_CRTC_ACTIVE;
3081                 bios_3_scratch |= (crtc << 20);
3082         }
3083         if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
3084                 bios_3_scratch &= ~ATOM_S3_LCD1_CRTC_ACTIVE;
3085                 bios_3_scratch |= (crtc << 17);
3086         }
3087         if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
3088                 bios_3_scratch &= ~ATOM_S3_DFP1_CRTC_ACTIVE;
3089                 bios_3_scratch |= (crtc << 19);
3090         }
3091         if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
3092                 bios_3_scratch &= ~ATOM_S3_DFP2_CRTC_ACTIVE;
3093                 bios_3_scratch |= (crtc << 23);
3094         }
3095         if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
3096                 bios_3_scratch &= ~ATOM_S3_DFP3_CRTC_ACTIVE;
3097                 bios_3_scratch |= (crtc << 25);
3098         }
3099
3100         if (rdev->family >= CHIP_R600)
3101                 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
3102         else
3103                 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
3104 }
3105
3106 void
3107 radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
3108 {
3109         struct drm_device *dev = encoder->dev;
3110         struct radeon_device *rdev = dev->dev_private;
3111         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3112         uint32_t bios_2_scratch;
3113
3114         if (ASIC_IS_DCE4(rdev))
3115                 return;
3116
3117         if (rdev->family >= CHIP_R600)
3118                 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
3119         else
3120                 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
3121
3122         if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
3123                 if (on)
3124                         bios_2_scratch &= ~ATOM_S2_TV1_DPMS_STATE;
3125                 else
3126                         bios_2_scratch |= ATOM_S2_TV1_DPMS_STATE;
3127         }
3128         if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
3129                 if (on)
3130                         bios_2_scratch &= ~ATOM_S2_CV_DPMS_STATE;
3131                 else
3132                         bios_2_scratch |= ATOM_S2_CV_DPMS_STATE;
3133         }
3134         if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
3135                 if (on)
3136                         bios_2_scratch &= ~ATOM_S2_CRT1_DPMS_STATE;
3137                 else
3138                         bios_2_scratch |= ATOM_S2_CRT1_DPMS_STATE;
3139         }
3140         if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
3141                 if (on)
3142                         bios_2_scratch &= ~ATOM_S2_CRT2_DPMS_STATE;
3143                 else
3144                         bios_2_scratch |= ATOM_S2_CRT2_DPMS_STATE;
3145         }
3146         if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
3147                 if (on)
3148                         bios_2_scratch &= ~ATOM_S2_LCD1_DPMS_STATE;
3149                 else
3150                         bios_2_scratch |= ATOM_S2_LCD1_DPMS_STATE;
3151         }
3152         if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
3153                 if (on)
3154                         bios_2_scratch &= ~ATOM_S2_DFP1_DPMS_STATE;
3155                 else
3156                         bios_2_scratch |= ATOM_S2_DFP1_DPMS_STATE;
3157         }
3158         if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
3159                 if (on)
3160                         bios_2_scratch &= ~ATOM_S2_DFP2_DPMS_STATE;
3161                 else
3162                         bios_2_scratch |= ATOM_S2_DFP2_DPMS_STATE;
3163         }
3164         if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
3165                 if (on)
3166                         bios_2_scratch &= ~ATOM_S2_DFP3_DPMS_STATE;
3167                 else
3168                         bios_2_scratch |= ATOM_S2_DFP3_DPMS_STATE;
3169         }
3170         if (radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) {
3171                 if (on)
3172                         bios_2_scratch &= ~ATOM_S2_DFP4_DPMS_STATE;
3173                 else
3174                         bios_2_scratch |= ATOM_S2_DFP4_DPMS_STATE;
3175         }
3176         if (radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) {
3177                 if (on)
3178                         bios_2_scratch &= ~ATOM_S2_DFP5_DPMS_STATE;
3179                 else
3180                         bios_2_scratch |= ATOM_S2_DFP5_DPMS_STATE;
3181         }
3182
3183         if (rdev->family >= CHIP_R600)
3184                 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
3185         else
3186                 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
3187 }