drivers/gpu/drm/radeon/radeon_asic.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28
  29 #include <linux/console.h>
  30 #include <drm/drmP.h>
  31 #include <drm/drm_crtc_helper.h>
  32 #include <drm/radeon_drm.h>
  33 #include <linux/vgaarb.h>
  34 #include <linux/vga_switcheroo.h>
  35 #include "radeon_reg.h"
  36 #include "radeon.h"
  37 #include "radeon_asic.h"
  38 #include "atom.h"
  39
  40 /*
  41  * Registers accessors functions.
  42  */
  43 /**
  44  * radeon_invalid_rreg - dummy reg read function
  45  *
  46  * @rdev: radeon device pointer
  47  * @reg: offset of register
  48  *
  49  * Dummy register read function.  Used for register blocks
  50  * that certain asics don't have (all asics).
  51  * Returns the value in the register.
  52  */
  53 static uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg)
  54 {
  55         DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
  56         BUG_ON(1);
  57         return 0;
  58 }
  59
  60 /**
  61  * radeon_invalid_wreg - dummy reg write function
  62  *
  63  * @rdev: radeon device pointer
  64  * @reg: offset of register
  65  * @v: value to write to the register
  66  *
  67  * Dummy register read function.  Used for register blocks
  68  * that certain asics don't have (all asics).
  69  */
  70 static void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
  71 {
  72         DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
  73                   reg, v);
  74         BUG_ON(1);
  75 }
  76
  77 /**
  78  * radeon_register_accessor_init - sets up the register accessor callbacks
  79  *
  80  * @rdev: radeon device pointer
  81  *
  82  * Sets up the register accessor callbacks for various register
  83  * apertures.  Not all asics have all apertures (all asics).
  84  */
  85 static void radeon_register_accessor_init(struct radeon_device *rdev)
  86 {
  87         rdev->mc_rreg = &radeon_invalid_rreg;
  88         rdev->mc_wreg = &radeon_invalid_wreg;
  89         rdev->pll_rreg = &radeon_invalid_rreg;
  90         rdev->pll_wreg = &radeon_invalid_wreg;
  91         rdev->pciep_rreg = &radeon_invalid_rreg;
  92         rdev->pciep_wreg = &radeon_invalid_wreg;
  93
  94         /* Don't change order as we are overridding accessor. */
  95         if (rdev->family < CHIP_RV515) {
  96                 rdev->pcie_reg_mask = 0xff;
  97         } else {
  98                 rdev->pcie_reg_mask = 0x7ff;
  99         }
 100         /* FIXME: not sure here */
 101         if (rdev->family <= CHIP_R580) {
 102                 rdev->pll_rreg = &r100_pll_rreg;
 103                 rdev->pll_wreg = &r100_pll_wreg;
 104         }
 105         if (rdev->family >= CHIP_R420) {
 106                 rdev->mc_rreg = &r420_mc_rreg;
 107                 rdev->mc_wreg = &r420_mc_wreg;
 108         }
 109         if (rdev->family >= CHIP_RV515) {
 110                 rdev->mc_rreg = &rv515_mc_rreg;
 111                 rdev->mc_wreg = &rv515_mc_wreg;
 112         }
 113         if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) {
 114                 rdev->mc_rreg = &rs400_mc_rreg;
 115                 rdev->mc_wreg = &rs400_mc_wreg;
 116         }
 117         if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) {
 118                 rdev->mc_rreg = &rs690_mc_rreg;
 119                 rdev->mc_wreg = &rs690_mc_wreg;
 120         }
 121         if (rdev->family == CHIP_RS600) {
 122                 rdev->mc_rreg = &rs600_mc_rreg;
 123                 rdev->mc_wreg = &rs600_mc_wreg;
 124         }
 125         if (rdev->family >= CHIP_R600) {
 126                 rdev->pciep_rreg = &r600_pciep_rreg;
 127                 rdev->pciep_wreg = &r600_pciep_wreg;
 128         }
 129 }
 130
 131
 132 /* helper to disable agp */
 133 /**
 134  * radeon_agp_disable - AGP disable helper function
 135  *
 136  * @rdev: radeon device pointer
 137  *
 138  * Removes AGP flags and changes the gart callbacks on AGP
 139  * cards when using the internal gart rather than AGP (all asics).
 140  */
 141 void radeon_agp_disable(struct radeon_device *rdev)
 142 {
 143         rdev->flags &= ~RADEON_IS_AGP;
 144         if (rdev->family >= CHIP_R600) {
 145                 DRM_INFO("Forcing AGP to PCIE mode\n");
 146                 rdev->flags |= RADEON_IS_PCIE;
 147         } else if (rdev->family >= CHIP_RV515 ||
 148                         rdev->family == CHIP_RV380 ||
 149                         rdev->family == CHIP_RV410 ||
 150                         rdev->family == CHIP_R423) {
 151                 DRM_INFO("Forcing AGP to PCIE mode\n");
 152                 rdev->flags |= RADEON_IS_PCIE;
 153                 rdev->asic->gart.tlb_flush = &rv370_pcie_gart_tlb_flush;
 154                 rdev->asic->gart.set_page = &rv370_pcie_gart_set_page;
 155         } else {
 156                 DRM_INFO("Forcing AGP to PCI mode\n");
 157                 rdev->flags |= RADEON_IS_PCI;
 158                 rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush;
 159                 rdev->asic->gart.set_page = &r100_pci_gart_set_page;
 160         }
 161         rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
 162 }
 163
 164 /*
 165  * ASIC
 166  */
 167 static struct radeon_asic r100_asic = {
 168         .init = &r100_init,
 169         .fini = &r100_fini,
 170         .suspend = &r100_suspend,
 171         .resume = &r100_resume,
 172         .vga_set_state = &r100_vga_set_state,
 173         .asic_reset = &r100_asic_reset,
 174         .ioctl_wait_idle = NULL,
 175         .gui_idle = &r100_gui_idle,
 176         .mc_wait_for_idle = &r100_mc_wait_for_idle,
 177         .gart = {
 178                 .tlb_flush = &r100_pci_gart_tlb_flush,
 179                 .set_page = &r100_pci_gart_set_page,
 180         },
 181         .ring = {
 182                 [RADEON_RING_TYPE_GFX_INDEX] = {
 183                         .ib_execute = &r100_ring_ib_execute,
 184                         .emit_fence = &r100_fence_ring_emit,
 185                         .emit_semaphore = &r100_semaphore_ring_emit,
 186                         .cs_parse = &r100_cs_parse,
 187                         .ring_start = &r100_ring_start,
 188                         .ring_test = &r100_ring_test,
 189                         .ib_test = &r100_ib_test,
 190                         .is_lockup = &r100_gpu_is_lockup,
 191                 }
 192         },
 193         .irq = {
 194                 .set = &r100_irq_set,
 195                 .process = &r100_irq_process,
 196         },
 197         .display = {
 198                 .bandwidth_update = &r100_bandwidth_update,
 199                 .get_vblank_counter = &r100_get_vblank_counter,
 200                 .wait_for_vblank = &r100_wait_for_vblank,
 201                 .set_backlight_level = &radeon_legacy_set_backlight_level,
 202                 .get_backlight_level = &radeon_legacy_get_backlight_level,
 203         },
 204         .copy = {
 205                 .blit = &r100_copy_blit,
 206                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 207                 .dma = NULL,
 208                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 209                 .copy = &r100_copy_blit,
 210                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 211         },
 212         .surface = {
 213                 .set_reg = r100_set_surface_reg,
 214                 .clear_reg = r100_clear_surface_reg,
 215         },
 216         .hpd = {
 217                 .init = &r100_hpd_init,
 218                 .fini = &r100_hpd_fini,
 219                 .sense = &r100_hpd_sense,
 220                 .set_polarity = &r100_hpd_set_polarity,
 221         },
 222         .pm = {
 223                 .misc = &r100_pm_misc,
 224                 .prepare = &r100_pm_prepare,
 225                 .finish = &r100_pm_finish,
 226                 .init_profile = &r100_pm_init_profile,
 227                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 228                 .get_engine_clock = &radeon_legacy_get_engine_clock,
 229                 .set_engine_clock = &radeon_legacy_set_engine_clock,
 230                 .get_memory_clock = &radeon_legacy_get_memory_clock,
 231                 .set_memory_clock = NULL,
 232                 .get_pcie_lanes = NULL,
 233                 .set_pcie_lanes = NULL,
 234                 .set_clock_gating = &radeon_legacy_set_clock_gating,
 235         },
 236         .pflip = {
 237                 .pre_page_flip = &r100_pre_page_flip,
 238                 .page_flip = &r100_page_flip,
 239                 .post_page_flip = &r100_post_page_flip,
 240         },
 241 };
 242
 243 static struct radeon_asic r200_asic = {
 244         .init = &r100_init,
 245         .fini = &r100_fini,
 246         .suspend = &r100_suspend,
 247         .resume = &r100_resume,
 248         .vga_set_state = &r100_vga_set_state,
 249         .asic_reset = &r100_asic_reset,
 250         .ioctl_wait_idle = NULL,
 251         .gui_idle = &r100_gui_idle,
 252         .mc_wait_for_idle = &r100_mc_wait_for_idle,
 253         .gart = {
 254                 .tlb_flush = &r100_pci_gart_tlb_flush,
 255                 .set_page = &r100_pci_gart_set_page,
 256         },
 257         .ring = {
 258                 [RADEON_RING_TYPE_GFX_INDEX] = {
 259                         .ib_execute = &r100_ring_ib_execute,
 260                         .emit_fence = &r100_fence_ring_emit,
 261                         .emit_semaphore = &r100_semaphore_ring_emit,
 262                         .cs_parse = &r100_cs_parse,
 263                         .ring_start = &r100_ring_start,
 264                         .ring_test = &r100_ring_test,
 265                         .ib_test = &r100_ib_test,
 266                         .is_lockup = &r100_gpu_is_lockup,
 267                 }
 268         },
 269         .irq = {
 270                 .set = &r100_irq_set,
 271                 .process = &r100_irq_process,
 272         },
 273         .display = {
 274                 .bandwidth_update = &r100_bandwidth_update,
 275                 .get_vblank_counter = &r100_get_vblank_counter,
 276                 .wait_for_vblank = &r100_wait_for_vblank,
 277                 .set_backlight_level = &radeon_legacy_set_backlight_level,
 278                 .get_backlight_level = &radeon_legacy_get_backlight_level,
 279         },
 280         .copy = {
 281                 .blit = &r100_copy_blit,
 282                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 283                 .dma = &r200_copy_dma,
 284                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 285                 .copy = &r100_copy_blit,
 286                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 287         },
 288         .surface = {
 289                 .set_reg = r100_set_surface_reg,
 290                 .clear_reg = r100_clear_surface_reg,
 291         },
 292         .hpd = {
 293                 .init = &r100_hpd_init,
 294                 .fini = &r100_hpd_fini,
 295                 .sense = &r100_hpd_sense,
 296                 .set_polarity = &r100_hpd_set_polarity,
 297         },
 298         .pm = {
 299                 .misc = &r100_pm_misc,
 300                 .prepare = &r100_pm_prepare,
 301                 .finish = &r100_pm_finish,
 302                 .init_profile = &r100_pm_init_profile,
 303                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 304                 .get_engine_clock = &radeon_legacy_get_engine_clock,
 305                 .set_engine_clock = &radeon_legacy_set_engine_clock,
 306                 .get_memory_clock = &radeon_legacy_get_memory_clock,
 307                 .set_memory_clock = NULL,
 308                 .get_pcie_lanes = NULL,
 309                 .set_pcie_lanes = NULL,
 310                 .set_clock_gating = &radeon_legacy_set_clock_gating,
 311         },
 312         .pflip = {
 313                 .pre_page_flip = &r100_pre_page_flip,
 314                 .page_flip = &r100_page_flip,
 315                 .post_page_flip = &r100_post_page_flip,
 316         },
 317 };
 318
 319 static struct radeon_asic r300_asic = {
 320         .init = &r300_init,
 321         .fini = &r300_fini,
 322         .suspend = &r300_suspend,
 323         .resume = &r300_resume,
 324         .vga_set_state = &r100_vga_set_state,
 325         .asic_reset = &r300_asic_reset,
 326         .ioctl_wait_idle = NULL,
 327         .gui_idle = &r100_gui_idle,
 328         .mc_wait_for_idle = &r300_mc_wait_for_idle,
 329         .gart = {
 330                 .tlb_flush = &r100_pci_gart_tlb_flush,
 331                 .set_page = &r100_pci_gart_set_page,
 332         },
 333         .ring = {
 334                 [RADEON_RING_TYPE_GFX_INDEX] = {
 335                         .ib_execute = &r100_ring_ib_execute,
 336                         .emit_fence = &r300_fence_ring_emit,
 337                         .emit_semaphore = &r100_semaphore_ring_emit,
 338                         .cs_parse = &r300_cs_parse,
 339                         .ring_start = &r300_ring_start,
 340                         .ring_test = &r100_ring_test,
 341                         .ib_test = &r100_ib_test,
 342                         .is_lockup = &r100_gpu_is_lockup,
 343                 }
 344         },
 345         .irq = {
 346                 .set = &r100_irq_set,
 347                 .process = &r100_irq_process,
 348         },
 349         .display = {
 350                 .bandwidth_update = &r100_bandwidth_update,
 351                 .get_vblank_counter = &r100_get_vblank_counter,
 352                 .wait_for_vblank = &r100_wait_for_vblank,
 353                 .set_backlight_level = &radeon_legacy_set_backlight_level,
 354                 .get_backlight_level = &radeon_legacy_get_backlight_level,
 355         },
 356         .copy = {
 357                 .blit = &r100_copy_blit,
 358                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 359                 .dma = &r200_copy_dma,
 360                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 361                 .copy = &r100_copy_blit,
 362                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 363         },
 364         .surface = {
 365                 .set_reg = r100_set_surface_reg,
 366                 .clear_reg = r100_clear_surface_reg,
 367         },
 368         .hpd = {
 369                 .init = &r100_hpd_init,
 370                 .fini = &r100_hpd_fini,
 371                 .sense = &r100_hpd_sense,
 372                 .set_polarity = &r100_hpd_set_polarity,
 373         },
 374         .pm = {
 375                 .misc = &r100_pm_misc,
 376                 .prepare = &r100_pm_prepare,
 377                 .finish = &r100_pm_finish,
 378                 .init_profile = &r100_pm_init_profile,
 379                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 380                 .get_engine_clock = &radeon_legacy_get_engine_clock,
 381                 .set_engine_clock = &radeon_legacy_set_engine_clock,
 382                 .get_memory_clock = &radeon_legacy_get_memory_clock,
 383                 .set_memory_clock = NULL,
 384                 .get_pcie_lanes = &rv370_get_pcie_lanes,
 385                 .set_pcie_lanes = &rv370_set_pcie_lanes,
 386                 .set_clock_gating = &radeon_legacy_set_clock_gating,
 387         },
 388         .pflip = {
 389                 .pre_page_flip = &r100_pre_page_flip,
 390                 .page_flip = &r100_page_flip,
 391                 .post_page_flip = &r100_post_page_flip,
 392         },
 393 };
 394
 395 static struct radeon_asic r300_asic_pcie = {
 396         .init = &r300_init,
 397         .fini = &r300_fini,
 398         .suspend = &r300_suspend,
 399         .resume = &r300_resume,
 400         .vga_set_state = &r100_vga_set_state,
 401         .asic_reset = &r300_asic_reset,
 402         .ioctl_wait_idle = NULL,
 403         .gui_idle = &r100_gui_idle,
 404         .mc_wait_for_idle = &r300_mc_wait_for_idle,
 405         .gart = {
 406                 .tlb_flush = &rv370_pcie_gart_tlb_flush,
 407                 .set_page = &rv370_pcie_gart_set_page,
 408         },
 409         .ring = {
 410                 [RADEON_RING_TYPE_GFX_INDEX] = {
 411                         .ib_execute = &r100_ring_ib_execute,
 412                         .emit_fence = &r300_fence_ring_emit,
 413                         .emit_semaphore = &r100_semaphore_ring_emit,
 414                         .cs_parse = &r300_cs_parse,
 415                         .ring_start = &r300_ring_start,
 416                         .ring_test = &r100_ring_test,
 417                         .ib_test = &r100_ib_test,
 418                         .is_lockup = &r100_gpu_is_lockup,
 419                 }
 420         },
 421         .irq = {
 422                 .set = &r100_irq_set,
 423                 .process = &r100_irq_process,
 424         },
 425         .display = {
 426                 .bandwidth_update = &r100_bandwidth_update,
 427                 .get_vblank_counter = &r100_get_vblank_counter,
 428                 .wait_for_vblank = &r100_wait_for_vblank,
 429                 .set_backlight_level = &radeon_legacy_set_backlight_level,
 430                 .get_backlight_level = &radeon_legacy_get_backlight_level,
 431         },
 432         .copy = {
 433                 .blit = &r100_copy_blit,
 434                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 435                 .dma = &r200_copy_dma,
 436                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 437                 .copy = &r100_copy_blit,
 438                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 439         },
 440         .surface = {
 441                 .set_reg = r100_set_surface_reg,
 442                 .clear_reg = r100_clear_surface_reg,
 443         },
 444         .hpd = {
 445                 .init = &r100_hpd_init,
 446                 .fini = &r100_hpd_fini,
 447                 .sense = &r100_hpd_sense,
 448                 .set_polarity = &r100_hpd_set_polarity,
 449         },
 450         .pm = {
 451                 .misc = &r100_pm_misc,
 452                 .prepare = &r100_pm_prepare,
 453                 .finish = &r100_pm_finish,
 454                 .init_profile = &r100_pm_init_profile,
 455                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 456                 .get_engine_clock = &radeon_legacy_get_engine_clock,
 457                 .set_engine_clock = &radeon_legacy_set_engine_clock,
 458                 .get_memory_clock = &radeon_legacy_get_memory_clock,
 459                 .set_memory_clock = NULL,
 460                 .get_pcie_lanes = &rv370_get_pcie_lanes,
 461                 .set_pcie_lanes = &rv370_set_pcie_lanes,
 462                 .set_clock_gating = &radeon_legacy_set_clock_gating,
 463         },
 464         .pflip = {
 465                 .pre_page_flip = &r100_pre_page_flip,
 466                 .page_flip = &r100_page_flip,
 467                 .post_page_flip = &r100_post_page_flip,
 468         },
 469 };
 470
 471 static struct radeon_asic r420_asic = {
 472         .init = &r420_init,
 473         .fini = &r420_fini,
 474         .suspend = &r420_suspend,
 475         .resume = &r420_resume,
 476         .vga_set_state = &r100_vga_set_state,
 477         .asic_reset = &r300_asic_reset,
 478         .ioctl_wait_idle = NULL,
 479         .gui_idle = &r100_gui_idle,
 480         .mc_wait_for_idle = &r300_mc_wait_for_idle,
 481         .gart = {
 482                 .tlb_flush = &rv370_pcie_gart_tlb_flush,
 483                 .set_page = &rv370_pcie_gart_set_page,
 484         },
 485         .ring = {
 486                 [RADEON_RING_TYPE_GFX_INDEX] = {
 487                         .ib_execute = &r100_ring_ib_execute,
 488                         .emit_fence = &r300_fence_ring_emit,
 489                         .emit_semaphore = &r100_semaphore_ring_emit,
 490                         .cs_parse = &r300_cs_parse,
 491                         .ring_start = &r300_ring_start,
 492                         .ring_test = &r100_ring_test,
 493                         .ib_test = &r100_ib_test,
 494                         .is_lockup = &r100_gpu_is_lockup,
 495                 }
 496         },
 497         .irq = {
 498                 .set = &r100_irq_set,
 499                 .process = &r100_irq_process,
 500         },
 501         .display = {
 502                 .bandwidth_update = &r100_bandwidth_update,
 503                 .get_vblank_counter = &r100_get_vblank_counter,
 504                 .wait_for_vblank = &r100_wait_for_vblank,
 505                 .set_backlight_level = &atombios_set_backlight_level,
 506                 .get_backlight_level = &atombios_get_backlight_level,
 507         },
 508         .copy = {
 509                 .blit = &r100_copy_blit,
 510                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 511                 .dma = &r200_copy_dma,
 512                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 513                 .copy = &r100_copy_blit,
 514                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 515         },
 516         .surface = {
 517                 .set_reg = r100_set_surface_reg,
 518                 .clear_reg = r100_clear_surface_reg,
 519         },
 520         .hpd = {
 521                 .init = &r100_hpd_init,
 522                 .fini = &r100_hpd_fini,
 523                 .sense = &r100_hpd_sense,
 524                 .set_polarity = &r100_hpd_set_polarity,
 525         },
 526         .pm = {
 527                 .misc = &r100_pm_misc,
 528                 .prepare = &r100_pm_prepare,
 529                 .finish = &r100_pm_finish,
 530                 .init_profile = &r420_pm_init_profile,
 531                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 532                 .get_engine_clock = &radeon_atom_get_engine_clock,
 533                 .set_engine_clock = &radeon_atom_set_engine_clock,
 534                 .get_memory_clock = &radeon_atom_get_memory_clock,
 535                 .set_memory_clock = &radeon_atom_set_memory_clock,
 536                 .get_pcie_lanes = &rv370_get_pcie_lanes,
 537                 .set_pcie_lanes = &rv370_set_pcie_lanes,
 538                 .set_clock_gating = &radeon_atom_set_clock_gating,
 539         },
 540         .pflip = {
 541                 .pre_page_flip = &r100_pre_page_flip,
 542                 .page_flip = &r100_page_flip,
 543                 .post_page_flip = &r100_post_page_flip,
 544         },
 545 };
 546
 547 static struct radeon_asic rs400_asic = {
 548         .init = &rs400_init,
 549         .fini = &rs400_fini,
 550         .suspend = &rs400_suspend,
 551         .resume = &rs400_resume,
 552         .vga_set_state = &r100_vga_set_state,
 553         .asic_reset = &r300_asic_reset,
 554         .ioctl_wait_idle = NULL,
 555         .gui_idle = &r100_gui_idle,
 556         .mc_wait_for_idle = &rs400_mc_wait_for_idle,
 557         .gart = {
 558                 .tlb_flush = &rs400_gart_tlb_flush,
 559                 .set_page = &rs400_gart_set_page,
 560         },
 561         .ring = {
 562                 [RADEON_RING_TYPE_GFX_INDEX] = {
 563                         .ib_execute = &r100_ring_ib_execute,
 564                         .emit_fence = &r300_fence_ring_emit,
 565                         .emit_semaphore = &r100_semaphore_ring_emit,
 566                         .cs_parse = &r300_cs_parse,
 567                         .ring_start = &r300_ring_start,
 568                         .ring_test = &r100_ring_test,
 569                         .ib_test = &r100_ib_test,
 570                         .is_lockup = &r100_gpu_is_lockup,
 571                 }
 572         },
 573         .irq = {
 574                 .set = &r100_irq_set,
 575                 .process = &r100_irq_process,
 576         },
 577         .display = {
 578                 .bandwidth_update = &r100_bandwidth_update,
 579                 .get_vblank_counter = &r100_get_vblank_counter,
 580                 .wait_for_vblank = &r100_wait_for_vblank,
 581                 .set_backlight_level = &radeon_legacy_set_backlight_level,
 582                 .get_backlight_level = &radeon_legacy_get_backlight_level,
 583         },
 584         .copy = {
 585                 .blit = &r100_copy_blit,
 586                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 587                 .dma = &r200_copy_dma,
 588                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 589                 .copy = &r100_copy_blit,
 590                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 591         },
 592         .surface = {
 593                 .set_reg = r100_set_surface_reg,
 594                 .clear_reg = r100_clear_surface_reg,
 595         },
 596         .hpd = {
 597                 .init = &r100_hpd_init,
 598                 .fini = &r100_hpd_fini,
 599                 .sense = &r100_hpd_sense,
 600                 .set_polarity = &r100_hpd_set_polarity,
 601         },
 602         .pm = {
 603                 .misc = &r100_pm_misc,
 604                 .prepare = &r100_pm_prepare,
 605                 .finish = &r100_pm_finish,
 606                 .init_profile = &r100_pm_init_profile,
 607                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 608                 .get_engine_clock = &radeon_legacy_get_engine_clock,
 609                 .set_engine_clock = &radeon_legacy_set_engine_clock,
 610                 .get_memory_clock = &radeon_legacy_get_memory_clock,
 611                 .set_memory_clock = NULL,
 612                 .get_pcie_lanes = NULL,
 613                 .set_pcie_lanes = NULL,
 614                 .set_clock_gating = &radeon_legacy_set_clock_gating,
 615         },
 616         .pflip = {
 617                 .pre_page_flip = &r100_pre_page_flip,
 618                 .page_flip = &r100_page_flip,
 619                 .post_page_flip = &r100_post_page_flip,
 620         },
 621 };
 622
 623 static struct radeon_asic rs600_asic = {
 624         .init = &rs600_init,
 625         .fini = &rs600_fini,
 626         .suspend = &rs600_suspend,
 627         .resume = &rs600_resume,
 628         .vga_set_state = &r100_vga_set_state,
 629         .asic_reset = &rs600_asic_reset,
 630         .ioctl_wait_idle = NULL,
 631         .gui_idle = &r100_gui_idle,
 632         .mc_wait_for_idle = &rs600_mc_wait_for_idle,
 633         .gart = {
 634                 .tlb_flush = &rs600_gart_tlb_flush,
 635                 .set_page = &rs600_gart_set_page,
 636         },
 637         .ring = {
 638                 [RADEON_RING_TYPE_GFX_INDEX] = {
 639                         .ib_execute = &r100_ring_ib_execute,
 640                         .emit_fence = &r300_fence_ring_emit,
 641                         .emit_semaphore = &r100_semaphore_ring_emit,
 642                         .cs_parse = &r300_cs_parse,
 643                         .ring_start = &r300_ring_start,
 644                         .ring_test = &r100_ring_test,
 645                         .ib_test = &r100_ib_test,
 646                         .is_lockup = &r100_gpu_is_lockup,
 647                 }
 648         },
 649         .irq = {
 650                 .set = &rs600_irq_set,
 651                 .process = &rs600_irq_process,
 652         },
 653         .display = {
 654                 .bandwidth_update = &rs600_bandwidth_update,
 655                 .get_vblank_counter = &rs600_get_vblank_counter,
 656                 .wait_for_vblank = &avivo_wait_for_vblank,
 657                 .set_backlight_level = &atombios_set_backlight_level,
 658                 .get_backlight_level = &atombios_get_backlight_level,
 659         },
 660         .copy = {
 661                 .blit = &r100_copy_blit,
 662                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 663                 .dma = &r200_copy_dma,
 664                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 665                 .copy = &r100_copy_blit,
 666                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 667         },
 668         .surface = {
 669                 .set_reg = r100_set_surface_reg,
 670                 .clear_reg = r100_clear_surface_reg,
 671         },
 672         .hpd = {
 673                 .init = &rs600_hpd_init,
 674                 .fini = &rs600_hpd_fini,
 675                 .sense = &rs600_hpd_sense,
 676                 .set_polarity = &rs600_hpd_set_polarity,
 677         },
 678         .pm = {
 679                 .misc = &rs600_pm_misc,
 680                 .prepare = &rs600_pm_prepare,
 681                 .finish = &rs600_pm_finish,
 682                 .init_profile = &r420_pm_init_profile,
 683                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 684                 .get_engine_clock = &radeon_atom_get_engine_clock,
 685                 .set_engine_clock = &radeon_atom_set_engine_clock,
 686                 .get_memory_clock = &radeon_atom_get_memory_clock,
 687                 .set_memory_clock = &radeon_atom_set_memory_clock,
 688                 .get_pcie_lanes = NULL,
 689                 .set_pcie_lanes = NULL,
 690                 .set_clock_gating = &radeon_atom_set_clock_gating,
 691         },
 692         .pflip = {
 693                 .pre_page_flip = &rs600_pre_page_flip,
 694                 .page_flip = &rs600_page_flip,
 695                 .post_page_flip = &rs600_post_page_flip,
 696         },
 697 };
 698
 699 static struct radeon_asic rs690_asic = {
 700         .init = &rs690_init,
 701         .fini = &rs690_fini,
 702         .suspend = &rs690_suspend,
 703         .resume = &rs690_resume,
 704         .vga_set_state = &r100_vga_set_state,
 705         .asic_reset = &rs600_asic_reset,
 706         .ioctl_wait_idle = NULL,
 707         .gui_idle = &r100_gui_idle,
 708         .mc_wait_for_idle = &rs690_mc_wait_for_idle,
 709         .gart = {
 710                 .tlb_flush = &rs400_gart_tlb_flush,
 711                 .set_page = &rs400_gart_set_page,
 712         },
 713         .ring = {
 714                 [RADEON_RING_TYPE_GFX_INDEX] = {
 715                         .ib_execute = &r100_ring_ib_execute,
 716                         .emit_fence = &r300_fence_ring_emit,
 717                         .emit_semaphore = &r100_semaphore_ring_emit,
 718                         .cs_parse = &r300_cs_parse,
 719                         .ring_start = &r300_ring_start,
 720                         .ring_test = &r100_ring_test,
 721                         .ib_test = &r100_ib_test,
 722                         .is_lockup = &r100_gpu_is_lockup,
 723                 }
 724         },
 725         .irq = {
 726                 .set = &rs600_irq_set,
 727                 .process = &rs600_irq_process,
 728         },
 729         .display = {
 730                 .get_vblank_counter = &rs600_get_vblank_counter,
 731                 .bandwidth_update = &rs690_bandwidth_update,
 732                 .wait_for_vblank = &avivo_wait_for_vblank,
 733                 .set_backlight_level = &atombios_set_backlight_level,
 734                 .get_backlight_level = &atombios_get_backlight_level,
 735         },
 736         .copy = {
 737                 .blit = &r100_copy_blit,
 738                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 739                 .dma = &r200_copy_dma,
 740                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 741                 .copy = &r200_copy_dma,
 742                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 743         },
 744         .surface = {
 745                 .set_reg = r100_set_surface_reg,
 746                 .clear_reg = r100_clear_surface_reg,
 747         },
 748         .hpd = {
 749                 .init = &rs600_hpd_init,
 750                 .fini = &rs600_hpd_fini,
 751                 .sense = &rs600_hpd_sense,
 752                 .set_polarity = &rs600_hpd_set_polarity,
 753         },
 754         .pm = {
 755                 .misc = &rs600_pm_misc,
 756                 .prepare = &rs600_pm_prepare,
 757                 .finish = &rs600_pm_finish,
 758                 .init_profile = &r420_pm_init_profile,
 759                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 760                 .get_engine_clock = &radeon_atom_get_engine_clock,
 761                 .set_engine_clock = &radeon_atom_set_engine_clock,
 762                 .get_memory_clock = &radeon_atom_get_memory_clock,
 763                 .set_memory_clock = &radeon_atom_set_memory_clock,
 764                 .get_pcie_lanes = NULL,
 765                 .set_pcie_lanes = NULL,
 766                 .set_clock_gating = &radeon_atom_set_clock_gating,
 767         },
 768         .pflip = {
 769                 .pre_page_flip = &rs600_pre_page_flip,
 770                 .page_flip = &rs600_page_flip,
 771                 .post_page_flip = &rs600_post_page_flip,
 772         },
 773 };
 774
 775 static struct radeon_asic rv515_asic = {
 776         .init = &rv515_init,
 777         .fini = &rv515_fini,
 778         .suspend = &rv515_suspend,
 779         .resume = &rv515_resume,
 780         .vga_set_state = &r100_vga_set_state,
 781         .asic_reset = &rs600_asic_reset,
 782         .ioctl_wait_idle = NULL,
 783         .gui_idle = &r100_gui_idle,
 784         .mc_wait_for_idle = &rv515_mc_wait_for_idle,
 785         .gart = {
 786                 .tlb_flush = &rv370_pcie_gart_tlb_flush,
 787                 .set_page = &rv370_pcie_gart_set_page,
 788         },
 789         .ring = {
 790                 [RADEON_RING_TYPE_GFX_INDEX] = {
 791                         .ib_execute = &r100_ring_ib_execute,
 792                         .emit_fence = &r300_fence_ring_emit,
 793                         .emit_semaphore = &r100_semaphore_ring_emit,
 794                         .cs_parse = &r300_cs_parse,
 795                         .ring_start = &rv515_ring_start,
 796                         .ring_test = &r100_ring_test,
 797                         .ib_test = &r100_ib_test,
 798                         .is_lockup = &r100_gpu_is_lockup,
 799                 }
 800         },
 801         .irq = {
 802                 .set = &rs600_irq_set,
 803                 .process = &rs600_irq_process,
 804         },
 805         .display = {
 806                 .get_vblank_counter = &rs600_get_vblank_counter,
 807                 .bandwidth_update = &rv515_bandwidth_update,
 808                 .wait_for_vblank = &avivo_wait_for_vblank,
 809                 .set_backlight_level = &atombios_set_backlight_level,
 810                 .get_backlight_level = &atombios_get_backlight_level,
 811         },
 812         .copy = {
 813                 .blit = &r100_copy_blit,
 814                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 815                 .dma = &r200_copy_dma,
 816                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 817                 .copy = &r100_copy_blit,
 818                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 819         },
 820         .surface = {
 821                 .set_reg = r100_set_surface_reg,
 822                 .clear_reg = r100_clear_surface_reg,
 823         },
 824         .hpd = {
 825                 .init = &rs600_hpd_init,
 826                 .fini = &rs600_hpd_fini,
 827                 .sense = &rs600_hpd_sense,
 828                 .set_polarity = &rs600_hpd_set_polarity,
 829         },
 830         .pm = {
 831                 .misc = &rs600_pm_misc,
 832                 .prepare = &rs600_pm_prepare,
 833                 .finish = &rs600_pm_finish,
 834                 .init_profile = &r420_pm_init_profile,
 835                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 836                 .get_engine_clock = &radeon_atom_get_engine_clock,
 837                 .set_engine_clock = &radeon_atom_set_engine_clock,
 838                 .get_memory_clock = &radeon_atom_get_memory_clock,
 839                 .set_memory_clock = &radeon_atom_set_memory_clock,
 840                 .get_pcie_lanes = &rv370_get_pcie_lanes,
 841                 .set_pcie_lanes = &rv370_set_pcie_lanes,
 842                 .set_clock_gating = &radeon_atom_set_clock_gating,
 843         },
 844         .pflip = {
 845                 .pre_page_flip = &rs600_pre_page_flip,
 846                 .page_flip = &rs600_page_flip,
 847                 .post_page_flip = &rs600_post_page_flip,
 848         },
 849 };
 850
 851 static struct radeon_asic r520_asic = {
 852         .init = &r520_init,
 853         .fini = &rv515_fini,
 854         .suspend = &rv515_suspend,
 855         .resume = &r520_resume,
 856         .vga_set_state = &r100_vga_set_state,
 857         .asic_reset = &rs600_asic_reset,
 858         .ioctl_wait_idle = NULL,
 859         .gui_idle = &r100_gui_idle,
 860         .mc_wait_for_idle = &r520_mc_wait_for_idle,
 861         .gart = {
 862                 .tlb_flush = &rv370_pcie_gart_tlb_flush,
 863                 .set_page = &rv370_pcie_gart_set_page,
 864         },
 865         .ring = {
 866                 [RADEON_RING_TYPE_GFX_INDEX] = {
 867                         .ib_execute = &r100_ring_ib_execute,
 868                         .emit_fence = &r300_fence_ring_emit,
 869                         .emit_semaphore = &r100_semaphore_ring_emit,
 870                         .cs_parse = &r300_cs_parse,
 871                         .ring_start = &rv515_ring_start,
 872                         .ring_test = &r100_ring_test,
 873                         .ib_test = &r100_ib_test,
 874                         .is_lockup = &r100_gpu_is_lockup,
 875                 }
 876         },
 877         .irq = {
 878                 .set = &rs600_irq_set,
 879                 .process = &rs600_irq_process,
 880         },
 881         .display = {
 882                 .bandwidth_update = &rv515_bandwidth_update,
 883                 .get_vblank_counter = &rs600_get_vblank_counter,
 884                 .wait_for_vblank = &avivo_wait_for_vblank,
 885                 .set_backlight_level = &atombios_set_backlight_level,
 886                 .get_backlight_level = &atombios_get_backlight_level,
 887         },
 888         .copy = {
 889                 .blit = &r100_copy_blit,
 890                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 891                 .dma = &r200_copy_dma,
 892                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 893                 .copy = &r100_copy_blit,
 894                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 895         },
 896         .surface = {
 897                 .set_reg = r100_set_surface_reg,
 898                 .clear_reg = r100_clear_surface_reg,
 899         },
 900         .hpd = {
 901                 .init = &rs600_hpd_init,
 902                 .fini = &rs600_hpd_fini,
 903                 .sense = &rs600_hpd_sense,
 904                 .set_polarity = &rs600_hpd_set_polarity,
 905         },
 906         .pm = {
 907                 .misc = &rs600_pm_misc,
 908                 .prepare = &rs600_pm_prepare,
 909                 .finish = &rs600_pm_finish,
 910                 .init_profile = &r420_pm_init_profile,
 911                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 912                 .get_engine_clock = &radeon_atom_get_engine_clock,
 913                 .set_engine_clock = &radeon_atom_set_engine_clock,
 914                 .get_memory_clock = &radeon_atom_get_memory_clock,
 915                 .set_memory_clock = &radeon_atom_set_memory_clock,
 916                 .get_pcie_lanes = &rv370_get_pcie_lanes,
 917                 .set_pcie_lanes = &rv370_set_pcie_lanes,
 918                 .set_clock_gating = &radeon_atom_set_clock_gating,
 919         },
 920         .pflip = {
 921                 .pre_page_flip = &rs600_pre_page_flip,
 922                 .page_flip = &rs600_page_flip,
 923                 .post_page_flip = &rs600_post_page_flip,
 924         },
 925 };
 926
 927 static struct radeon_asic r600_asic = {
 928         .init = &r600_init,
 929         .fini = &r600_fini,
 930         .suspend = &r600_suspend,
 931         .resume = &r600_resume,
 932         .vga_set_state = &r600_vga_set_state,
 933         .asic_reset = &r600_asic_reset,
 934         .ioctl_wait_idle = r600_ioctl_wait_idle,
 935         .gui_idle = &r600_gui_idle,
 936         .mc_wait_for_idle = &r600_mc_wait_for_idle,
 937         .gart = {
 938                 .tlb_flush = &r600_pcie_gart_tlb_flush,
 939                 .set_page = &rs600_gart_set_page,
 940         },
 941         .ring = {
 942                 [RADEON_RING_TYPE_GFX_INDEX] = {
 943                         .ib_execute = &r600_ring_ib_execute,
 944                         .emit_fence = &r600_fence_ring_emit,
 945                         .emit_semaphore = &r600_semaphore_ring_emit,
 946                         .cs_parse = &r600_cs_parse,
 947                         .ring_test = &r600_ring_test,
 948                         .ib_test = &r600_ib_test,
 949                         .is_lockup = &r600_gpu_is_lockup,
 950                 },
 951                 [R600_RING_TYPE_DMA_INDEX] = {
 952                         .ib_execute = &r600_dma_ring_ib_execute,
 953                         .emit_fence = &r600_dma_fence_ring_emit,
 954                         .emit_semaphore = &r600_dma_semaphore_ring_emit,
 955                         .cs_parse = NULL,
 956                         .ring_test = &r600_dma_ring_test,
 957                         .ib_test = &r600_dma_ib_test,
 958                         .is_lockup = &r600_dma_is_lockup,
 959                 }
 960         },
 961         .irq = {
 962                 .set = &r600_irq_set,
 963                 .process = &r600_irq_process,
 964         },
 965         .display = {
 966                 .bandwidth_update = &rv515_bandwidth_update,
 967                 .get_vblank_counter = &rs600_get_vblank_counter,
 968                 .wait_for_vblank = &avivo_wait_for_vblank,
 969                 .set_backlight_level = &atombios_set_backlight_level,
 970                 .get_backlight_level = &atombios_get_backlight_level,
 971         },
 972         .copy = {
 973                 .blit = &r600_copy_blit,
 974                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 975                 .dma = &r600_copy_dma,
 976                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
 977                 .copy = &r600_copy_blit,
 978                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 979         },
 980         .surface = {
 981                 .set_reg = r600_set_surface_reg,
 982                 .clear_reg = r600_clear_surface_reg,
 983         },
 984         .hpd = {
 985                 .init = &r600_hpd_init,
 986                 .fini = &r600_hpd_fini,
 987                 .sense = &r600_hpd_sense,
 988                 .set_polarity = &r600_hpd_set_polarity,
 989         },
 990         .pm = {
 991                 .misc = &r600_pm_misc,
 992                 .prepare = &rs600_pm_prepare,
 993                 .finish = &rs600_pm_finish,
 994                 .init_profile = &r600_pm_init_profile,
 995                 .get_dynpm_state = &r600_pm_get_dynpm_state,
 996                 .get_engine_clock = &radeon_atom_get_engine_clock,
 997                 .set_engine_clock = &radeon_atom_set_engine_clock,
 998                 .get_memory_clock = &radeon_atom_get_memory_clock,
 999                 .set_memory_clock = &radeon_atom_set_memory_clock,
1000                 .get_pcie_lanes = &r600_get_pcie_lanes,
1001                 .set_pcie_lanes = &r600_set_pcie_lanes,
1002                 .set_clock_gating = NULL,
1003         },
1004         .pflip = {
1005                 .pre_page_flip = &rs600_pre_page_flip,
1006                 .page_flip = &rs600_page_flip,
1007                 .post_page_flip = &rs600_post_page_flip,
1008         },
1009 };
1010
1011 static struct radeon_asic rs780_asic = {
1012         .init = &r600_init,
1013         .fini = &r600_fini,
1014         .suspend = &r600_suspend,
1015         .resume = &r600_resume,
1016         .vga_set_state = &r600_vga_set_state,
1017         .asic_reset = &r600_asic_reset,
1018         .ioctl_wait_idle = r600_ioctl_wait_idle,
1019         .gui_idle = &r600_gui_idle,
1020         .mc_wait_for_idle = &r600_mc_wait_for_idle,
1021         .gart = {
1022                 .tlb_flush = &r600_pcie_gart_tlb_flush,
1023                 .set_page = &rs600_gart_set_page,
1024         },
1025         .ring = {
1026                 [RADEON_RING_TYPE_GFX_INDEX] = {
1027                         .ib_execute = &r600_ring_ib_execute,
1028                         .emit_fence = &r600_fence_ring_emit,
1029                         .emit_semaphore = &r600_semaphore_ring_emit,
1030                         .cs_parse = &r600_cs_parse,
1031                         .ring_test = &r600_ring_test,
1032                         .ib_test = &r600_ib_test,
1033                         .is_lockup = &r600_gpu_is_lockup,
1034                 },
1035                 [R600_RING_TYPE_DMA_INDEX] = {
1036                         .ib_execute = &r600_dma_ring_ib_execute,
1037                         .emit_fence = &r600_dma_fence_ring_emit,
1038                         .emit_semaphore = &r600_dma_semaphore_ring_emit,
1039                         .cs_parse = NULL,
1040                         .ring_test = &r600_dma_ring_test,
1041                         .ib_test = &r600_dma_ib_test,
1042                         .is_lockup = &r600_dma_is_lockup,
1043                 }
1044         },
1045         .irq = {
1046                 .set = &r600_irq_set,
1047                 .process = &r600_irq_process,
1048         },
1049         .display = {
1050                 .bandwidth_update = &rs690_bandwidth_update,
1051                 .get_vblank_counter = &rs600_get_vblank_counter,
1052                 .wait_for_vblank = &avivo_wait_for_vblank,
1053                 .set_backlight_level = &atombios_set_backlight_level,
1054                 .get_backlight_level = &atombios_get_backlight_level,
1055         },
1056         .copy = {
1057                 .blit = &r600_copy_blit,
1058                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1059                 .dma = &r600_copy_dma,
1060                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1061                 .copy = &r600_copy_blit,
1062                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1063         },
1064         .surface = {
1065                 .set_reg = r600_set_surface_reg,
1066                 .clear_reg = r600_clear_surface_reg,
1067         },
1068         .hpd = {
1069                 .init = &r600_hpd_init,
1070                 .fini = &r600_hpd_fini,
1071                 .sense = &r600_hpd_sense,
1072                 .set_polarity = &r600_hpd_set_polarity,
1073         },
1074         .pm = {
1075                 .misc = &r600_pm_misc,
1076                 .prepare = &rs600_pm_prepare,
1077                 .finish = &rs600_pm_finish,
1078                 .init_profile = &rs780_pm_init_profile,
1079                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1080                 .get_engine_clock = &radeon_atom_get_engine_clock,
1081                 .set_engine_clock = &radeon_atom_set_engine_clock,
1082                 .get_memory_clock = NULL,
1083                 .set_memory_clock = NULL,
1084                 .get_pcie_lanes = NULL,
1085                 .set_pcie_lanes = NULL,
1086                 .set_clock_gating = NULL,
1087         },
1088         .pflip = {
1089                 .pre_page_flip = &rs600_pre_page_flip,
1090                 .page_flip = &rs600_page_flip,
1091                 .post_page_flip = &rs600_post_page_flip,
1092         },
1093 };
1094
1095 static struct radeon_asic rv770_asic = {
1096         .init = &rv770_init,
1097         .fini = &rv770_fini,
1098         .suspend = &rv770_suspend,
1099         .resume = &rv770_resume,
1100         .asic_reset = &r600_asic_reset,
1101         .vga_set_state = &r600_vga_set_state,
1102         .ioctl_wait_idle = r600_ioctl_wait_idle,
1103         .gui_idle = &r600_gui_idle,
1104         .mc_wait_for_idle = &r600_mc_wait_for_idle,
1105         .gart = {
1106                 .tlb_flush = &r600_pcie_gart_tlb_flush,
1107                 .set_page = &rs600_gart_set_page,
1108         },
1109         .ring = {
1110                 [RADEON_RING_TYPE_GFX_INDEX] = {
1111                         .ib_execute = &r600_ring_ib_execute,
1112                         .emit_fence = &r600_fence_ring_emit,
1113                         .emit_semaphore = &r600_semaphore_ring_emit,
1114                         .cs_parse = &r600_cs_parse,
1115                         .ring_test = &r600_ring_test,
1116                         .ib_test = &r600_ib_test,
1117                         .is_lockup = &r600_gpu_is_lockup,
1118                 },
1119                 [R600_RING_TYPE_DMA_INDEX] = {
1120                         .ib_execute = &r600_dma_ring_ib_execute,
1121                         .emit_fence = &r600_dma_fence_ring_emit,
1122                         .emit_semaphore = &r600_dma_semaphore_ring_emit,
1123                         .cs_parse = NULL,
1124                         .ring_test = &r600_dma_ring_test,
1125                         .ib_test = &r600_dma_ib_test,
1126                         .is_lockup = &r600_dma_is_lockup,
1127                 }
1128         },
1129         .irq = {
1130                 .set = &r600_irq_set,
1131                 .process = &r600_irq_process,
1132         },
1133         .display = {
1134                 .bandwidth_update = &rv515_bandwidth_update,
1135                 .get_vblank_counter = &rs600_get_vblank_counter,
1136                 .wait_for_vblank = &avivo_wait_for_vblank,
1137                 .set_backlight_level = &atombios_set_backlight_level,
1138                 .get_backlight_level = &atombios_get_backlight_level,
1139         },
1140         .copy = {
1141                 .blit = &r600_copy_blit,
1142                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1143                 .dma = &r600_copy_dma,
1144                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1145                 .copy = &r600_copy_blit,
1146                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1147         },
1148         .surface = {
1149                 .set_reg = r600_set_surface_reg,
1150                 .clear_reg = r600_clear_surface_reg,
1151         },
1152         .hpd = {
1153                 .init = &r600_hpd_init,
1154                 .fini = &r600_hpd_fini,
1155                 .sense = &r600_hpd_sense,
1156                 .set_polarity = &r600_hpd_set_polarity,
1157         },
1158         .pm = {
1159                 .misc = &rv770_pm_misc,
1160                 .prepare = &rs600_pm_prepare,
1161                 .finish = &rs600_pm_finish,
1162                 .init_profile = &r600_pm_init_profile,
1163                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1164                 .get_engine_clock = &radeon_atom_get_engine_clock,
1165                 .set_engine_clock = &radeon_atom_set_engine_clock,
1166                 .get_memory_clock = &radeon_atom_get_memory_clock,
1167                 .set_memory_clock = &radeon_atom_set_memory_clock,
1168                 .get_pcie_lanes = &r600_get_pcie_lanes,
1169                 .set_pcie_lanes = &r600_set_pcie_lanes,
1170                 .set_clock_gating = &radeon_atom_set_clock_gating,
1171         },
1172         .pflip = {
1173                 .pre_page_flip = &rs600_pre_page_flip,
1174                 .page_flip = &rv770_page_flip,
1175                 .post_page_flip = &rs600_post_page_flip,
1176         },
1177 };
1178
1179 static struct radeon_asic evergreen_asic = {
1180         .init = &evergreen_init,
1181         .fini = &evergreen_fini,
1182         .suspend = &evergreen_suspend,
1183         .resume = &evergreen_resume,
1184         .asic_reset = &evergreen_asic_reset,
1185         .vga_set_state = &r600_vga_set_state,
1186         .ioctl_wait_idle = r600_ioctl_wait_idle,
1187         .gui_idle = &r600_gui_idle,
1188         .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1189         .gart = {
1190                 .tlb_flush = &evergreen_pcie_gart_tlb_flush,
1191                 .set_page = &rs600_gart_set_page,
1192         },
1193         .ring = {
1194                 [RADEON_RING_TYPE_GFX_INDEX] = {
1195                         .ib_execute = &evergreen_ring_ib_execute,
1196                         .emit_fence = &r600_fence_ring_emit,
1197                         .emit_semaphore = &r600_semaphore_ring_emit,
1198                         .cs_parse = &evergreen_cs_parse,
1199                         .ring_test = &r600_ring_test,
1200                         .ib_test = &r600_ib_test,
1201                         .is_lockup = &evergreen_gpu_is_lockup,
1202                 }
1203         },
1204         .irq = {
1205                 .set = &evergreen_irq_set,
1206                 .process = &evergreen_irq_process,
1207         },
1208         .display = {
1209                 .bandwidth_update = &evergreen_bandwidth_update,
1210                 .get_vblank_counter = &evergreen_get_vblank_counter,
1211                 .wait_for_vblank = &dce4_wait_for_vblank,
1212                 .set_backlight_level = &atombios_set_backlight_level,
1213                 .get_backlight_level = &atombios_get_backlight_level,
1214         },
1215         .copy = {
1216                 .blit = &r600_copy_blit,
1217                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1218                 .dma = NULL,
1219                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1220                 .copy = &r600_copy_blit,
1221                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1222         },
1223         .surface = {
1224                 .set_reg = r600_set_surface_reg,
1225                 .clear_reg = r600_clear_surface_reg,
1226         },
1227         .hpd = {
1228                 .init = &evergreen_hpd_init,
1229                 .fini = &evergreen_hpd_fini,
1230                 .sense = &evergreen_hpd_sense,
1231                 .set_polarity = &evergreen_hpd_set_polarity,
1232         },
1233         .pm = {
1234                 .misc = &evergreen_pm_misc,
1235                 .prepare = &evergreen_pm_prepare,
1236                 .finish = &evergreen_pm_finish,
1237                 .init_profile = &r600_pm_init_profile,
1238                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1239                 .get_engine_clock = &radeon_atom_get_engine_clock,
1240                 .set_engine_clock = &radeon_atom_set_engine_clock,
1241                 .get_memory_clock = &radeon_atom_get_memory_clock,
1242                 .set_memory_clock = &radeon_atom_set_memory_clock,
1243                 .get_pcie_lanes = &r600_get_pcie_lanes,
1244                 .set_pcie_lanes = &r600_set_pcie_lanes,
1245                 .set_clock_gating = NULL,
1246         },
1247         .pflip = {
1248                 .pre_page_flip = &evergreen_pre_page_flip,
1249                 .page_flip = &evergreen_page_flip,
1250                 .post_page_flip = &evergreen_post_page_flip,
1251         },
1252 };
1253
1254 static struct radeon_asic sumo_asic = {
1255         .init = &evergreen_init,
1256         .fini = &evergreen_fini,
1257         .suspend = &evergreen_suspend,
1258         .resume = &evergreen_resume,
1259         .asic_reset = &evergreen_asic_reset,
1260         .vga_set_state = &r600_vga_set_state,
1261         .ioctl_wait_idle = r600_ioctl_wait_idle,
1262         .gui_idle = &r600_gui_idle,
1263         .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1264         .gart = {
1265                 .tlb_flush = &evergreen_pcie_gart_tlb_flush,
1266                 .set_page = &rs600_gart_set_page,
1267         },
1268         .ring = {
1269                 [RADEON_RING_TYPE_GFX_INDEX] = {
1270                         .ib_execute = &evergreen_ring_ib_execute,
1271                         .emit_fence = &r600_fence_ring_emit,
1272                         .emit_semaphore = &r600_semaphore_ring_emit,
1273                         .cs_parse = &evergreen_cs_parse,
1274                         .ring_test = &r600_ring_test,
1275                         .ib_test = &r600_ib_test,
1276                         .is_lockup = &evergreen_gpu_is_lockup,
1277                 },
1278         },
1279         .irq = {
1280                 .set = &evergreen_irq_set,
1281                 .process = &evergreen_irq_process,
1282         },
1283         .display = {
1284                 .bandwidth_update = &evergreen_bandwidth_update,
1285                 .get_vblank_counter = &evergreen_get_vblank_counter,
1286                 .wait_for_vblank = &dce4_wait_for_vblank,
1287                 .set_backlight_level = &atombios_set_backlight_level,
1288                 .get_backlight_level = &atombios_get_backlight_level,
1289         },
1290         .copy = {
1291                 .blit = &r600_copy_blit,
1292                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1293                 .dma = NULL,
1294                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1295                 .copy = &r600_copy_blit,
1296                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1297         },
1298         .surface = {
1299                 .set_reg = r600_set_surface_reg,
1300                 .clear_reg = r600_clear_surface_reg,
1301         },
1302         .hpd = {
1303                 .init = &evergreen_hpd_init,
1304                 .fini = &evergreen_hpd_fini,
1305                 .sense = &evergreen_hpd_sense,
1306                 .set_polarity = &evergreen_hpd_set_polarity,
1307         },
1308         .pm = {
1309                 .misc = &evergreen_pm_misc,
1310                 .prepare = &evergreen_pm_prepare,
1311                 .finish = &evergreen_pm_finish,
1312                 .init_profile = &sumo_pm_init_profile,
1313                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1314                 .get_engine_clock = &radeon_atom_get_engine_clock,
1315                 .set_engine_clock = &radeon_atom_set_engine_clock,
1316                 .get_memory_clock = NULL,
1317                 .set_memory_clock = NULL,
1318                 .get_pcie_lanes = NULL,
1319                 .set_pcie_lanes = NULL,
1320                 .set_clock_gating = NULL,
1321         },
1322         .pflip = {
1323                 .pre_page_flip = &evergreen_pre_page_flip,
1324                 .page_flip = &evergreen_page_flip,
1325                 .post_page_flip = &evergreen_post_page_flip,
1326         },
1327 };
1328
1329 static struct radeon_asic btc_asic = {
1330         .init = &evergreen_init,
1331         .fini = &evergreen_fini,
1332         .suspend = &evergreen_suspend,
1333         .resume = &evergreen_resume,
1334         .asic_reset = &evergreen_asic_reset,
1335         .vga_set_state = &r600_vga_set_state,
1336         .ioctl_wait_idle = r600_ioctl_wait_idle,
1337         .gui_idle = &r600_gui_idle,
1338         .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1339         .gart = {
1340                 .tlb_flush = &evergreen_pcie_gart_tlb_flush,
1341                 .set_page = &rs600_gart_set_page,
1342         },
1343         .ring = {
1344                 [RADEON_RING_TYPE_GFX_INDEX] = {
1345                         .ib_execute = &evergreen_ring_ib_execute,
1346                         .emit_fence = &r600_fence_ring_emit,
1347                         .emit_semaphore = &r600_semaphore_ring_emit,
1348                         .cs_parse = &evergreen_cs_parse,
1349                         .ring_test = &r600_ring_test,
1350                         .ib_test = &r600_ib_test,
1351                         .is_lockup = &evergreen_gpu_is_lockup,
1352                 }
1353         },
1354         .irq = {
1355                 .set = &evergreen_irq_set,
1356                 .process = &evergreen_irq_process,
1357         },
1358         .display = {
1359                 .bandwidth_update = &evergreen_bandwidth_update,
1360                 .get_vblank_counter = &evergreen_get_vblank_counter,
1361                 .wait_for_vblank = &dce4_wait_for_vblank,
1362                 .set_backlight_level = &atombios_set_backlight_level,
1363                 .get_backlight_level = &atombios_get_backlight_level,
1364         },
1365         .copy = {
1366                 .blit = &r600_copy_blit,
1367                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1368                 .dma = NULL,
1369                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1370                 .copy = &r600_copy_blit,
1371                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1372         },
1373         .surface = {
1374                 .set_reg = r600_set_surface_reg,
1375                 .clear_reg = r600_clear_surface_reg,
1376         },
1377         .hpd = {
1378                 .init = &evergreen_hpd_init,
1379                 .fini = &evergreen_hpd_fini,
1380                 .sense = &evergreen_hpd_sense,
1381                 .set_polarity = &evergreen_hpd_set_polarity,
1382         },
1383         .pm = {
1384                 .misc = &evergreen_pm_misc,
1385                 .prepare = &evergreen_pm_prepare,
1386                 .finish = &evergreen_pm_finish,
1387                 .init_profile = &btc_pm_init_profile,
1388                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1389                 .get_engine_clock = &radeon_atom_get_engine_clock,
1390                 .set_engine_clock = &radeon_atom_set_engine_clock,
1391                 .get_memory_clock = &radeon_atom_get_memory_clock,
1392                 .set_memory_clock = &radeon_atom_set_memory_clock,
1393                 .get_pcie_lanes = NULL,
1394                 .set_pcie_lanes = NULL,
1395                 .set_clock_gating = NULL,
1396         },
1397         .pflip = {
1398                 .pre_page_flip = &evergreen_pre_page_flip,
1399                 .page_flip = &evergreen_page_flip,
1400                 .post_page_flip = &evergreen_post_page_flip,
1401         },
1402 };
1403
1404 static struct radeon_asic cayman_asic = {
1405         .init = &cayman_init,
1406         .fini = &cayman_fini,
1407         .suspend = &cayman_suspend,
1408         .resume = &cayman_resume,
1409         .asic_reset = &cayman_asic_reset,
1410         .vga_set_state = &r600_vga_set_state,
1411         .ioctl_wait_idle = r600_ioctl_wait_idle,
1412         .gui_idle = &r600_gui_idle,
1413         .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1414         .gart = {
1415                 .tlb_flush = &cayman_pcie_gart_tlb_flush,
1416                 .set_page = &rs600_gart_set_page,
1417         },
1418         .vm = {
1419                 .init = &cayman_vm_init,
1420                 .fini = &cayman_vm_fini,
1421                 .pt_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1422                 .set_page = &cayman_vm_set_page,
1423         },
1424         .ring = {
1425                 [RADEON_RING_TYPE_GFX_INDEX] = {
1426                         .ib_execute = &cayman_ring_ib_execute,
1427                         .ib_parse = &evergreen_ib_parse,
1428                         .emit_fence = &cayman_fence_ring_emit,
1429                         .emit_semaphore = &r600_semaphore_ring_emit,
1430                         .cs_parse = &evergreen_cs_parse,
1431                         .ring_test = &r600_ring_test,
1432                         .ib_test = &r600_ib_test,
1433                         .is_lockup = &evergreen_gpu_is_lockup,
1434                         .vm_flush = &cayman_vm_flush,
1435                 },
1436                 [CAYMAN_RING_TYPE_CP1_INDEX] = {
1437                         .ib_execute = &cayman_ring_ib_execute,
1438                         .ib_parse = &evergreen_ib_parse,
1439                         .emit_fence = &cayman_fence_ring_emit,
1440                         .emit_semaphore = &r600_semaphore_ring_emit,
1441                         .cs_parse = &evergreen_cs_parse,
1442                         .ring_test = &r600_ring_test,
1443                         .ib_test = &r600_ib_test,
1444                         .is_lockup = &evergreen_gpu_is_lockup,
1445                         .vm_flush = &cayman_vm_flush,
1446                 },
1447                 [CAYMAN_RING_TYPE_CP2_INDEX] = {
1448                         .ib_execute = &cayman_ring_ib_execute,
1449                         .ib_parse = &evergreen_ib_parse,
1450                         .emit_fence = &cayman_fence_ring_emit,
1451                         .emit_semaphore = &r600_semaphore_ring_emit,
1452                         .cs_parse = &evergreen_cs_parse,
1453                         .ring_test = &r600_ring_test,
1454                         .ib_test = &r600_ib_test,
1455                         .is_lockup = &evergreen_gpu_is_lockup,
1456                         .vm_flush = &cayman_vm_flush,
1457                 }
1458         },
1459         .irq = {
1460                 .set = &evergreen_irq_set,
1461                 .process = &evergreen_irq_process,
1462         },
1463         .display = {
1464                 .bandwidth_update = &evergreen_bandwidth_update,
1465                 .get_vblank_counter = &evergreen_get_vblank_counter,
1466                 .wait_for_vblank = &dce4_wait_for_vblank,
1467                 .set_backlight_level = &atombios_set_backlight_level,
1468                 .get_backlight_level = &atombios_get_backlight_level,
1469         },
1470         .copy = {
1471                 .blit = &r600_copy_blit,
1472                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1473                 .dma = NULL,
1474                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1475                 .copy = &r600_copy_blit,
1476                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1477         },
1478         .surface = {
1479                 .set_reg = r600_set_surface_reg,
1480                 .clear_reg = r600_clear_surface_reg,
1481         },
1482         .hpd = {
1483                 .init = &evergreen_hpd_init,
1484                 .fini = &evergreen_hpd_fini,
1485                 .sense = &evergreen_hpd_sense,
1486                 .set_polarity = &evergreen_hpd_set_polarity,
1487         },
1488         .pm = {
1489                 .misc = &evergreen_pm_misc,
1490                 .prepare = &evergreen_pm_prepare,
1491                 .finish = &evergreen_pm_finish,
1492                 .init_profile = &btc_pm_init_profile,
1493                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1494                 .get_engine_clock = &radeon_atom_get_engine_clock,
1495                 .set_engine_clock = &radeon_atom_set_engine_clock,
1496                 .get_memory_clock = &radeon_atom_get_memory_clock,
1497                 .set_memory_clock = &radeon_atom_set_memory_clock,
1498                 .get_pcie_lanes = NULL,
1499                 .set_pcie_lanes = NULL,
1500                 .set_clock_gating = NULL,
1501         },
1502         .pflip = {
1503                 .pre_page_flip = &evergreen_pre_page_flip,
1504                 .page_flip = &evergreen_page_flip,
1505                 .post_page_flip = &evergreen_post_page_flip,
1506         },
1507 };
1508
1509 static struct radeon_asic trinity_asic = {
1510         .init = &cayman_init,
1511         .fini = &cayman_fini,
1512         .suspend = &cayman_suspend,
1513         .resume = &cayman_resume,
1514         .asic_reset = &cayman_asic_reset,
1515         .vga_set_state = &r600_vga_set_state,
1516         .ioctl_wait_idle = r600_ioctl_wait_idle,
1517         .gui_idle = &r600_gui_idle,
1518         .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1519         .gart = {
1520                 .tlb_flush = &cayman_pcie_gart_tlb_flush,
1521                 .set_page = &rs600_gart_set_page,
1522         },
1523         .vm = {
1524                 .init = &cayman_vm_init,
1525                 .fini = &cayman_vm_fini,
1526                 .pt_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1527                 .set_page = &cayman_vm_set_page,
1528         },
1529         .ring = {
1530                 [RADEON_RING_TYPE_GFX_INDEX] = {
1531                         .ib_execute = &cayman_ring_ib_execute,
1532                         .ib_parse = &evergreen_ib_parse,
1533                         .emit_fence = &cayman_fence_ring_emit,
1534                         .emit_semaphore = &r600_semaphore_ring_emit,
1535                         .cs_parse = &evergreen_cs_parse,
1536                         .ring_test = &r600_ring_test,
1537                         .ib_test = &r600_ib_test,
1538                         .is_lockup = &evergreen_gpu_is_lockup,
1539                         .vm_flush = &cayman_vm_flush,
1540                 },
1541                 [CAYMAN_RING_TYPE_CP1_INDEX] = {
1542                         .ib_execute = &cayman_ring_ib_execute,
1543                         .ib_parse = &evergreen_ib_parse,
1544                         .emit_fence = &cayman_fence_ring_emit,
1545                         .emit_semaphore = &r600_semaphore_ring_emit,
1546                         .cs_parse = &evergreen_cs_parse,
1547                         .ring_test = &r600_ring_test,
1548                         .ib_test = &r600_ib_test,
1549                         .is_lockup = &evergreen_gpu_is_lockup,
1550                         .vm_flush = &cayman_vm_flush,
1551                 },
1552                 [CAYMAN_RING_TYPE_CP2_INDEX] = {
1553                         .ib_execute = &cayman_ring_ib_execute,
1554                         .ib_parse = &evergreen_ib_parse,
1555                         .emit_fence = &cayman_fence_ring_emit,
1556                         .emit_semaphore = &r600_semaphore_ring_emit,
1557                         .cs_parse = &evergreen_cs_parse,
1558                         .ring_test = &r600_ring_test,
1559                         .ib_test = &r600_ib_test,
1560                         .is_lockup = &evergreen_gpu_is_lockup,
1561                         .vm_flush = &cayman_vm_flush,
1562                 }
1563         },
1564         .irq = {
1565                 .set = &evergreen_irq_set,
1566                 .process = &evergreen_irq_process,
1567         },
1568         .display = {
1569                 .bandwidth_update = &dce6_bandwidth_update,
1570                 .get_vblank_counter = &evergreen_get_vblank_counter,
1571                 .wait_for_vblank = &dce4_wait_for_vblank,
1572                 .set_backlight_level = &atombios_set_backlight_level,
1573                 .get_backlight_level = &atombios_get_backlight_level,
1574         },
1575         .copy = {
1576                 .blit = &r600_copy_blit,
1577                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1578                 .dma = NULL,
1579                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1580                 .copy = &r600_copy_blit,
1581                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1582         },
1583         .surface = {
1584                 .set_reg = r600_set_surface_reg,
1585                 .clear_reg = r600_clear_surface_reg,
1586         },
1587         .hpd = {
1588                 .init = &evergreen_hpd_init,
1589                 .fini = &evergreen_hpd_fini,
1590                 .sense = &evergreen_hpd_sense,
1591                 .set_polarity = &evergreen_hpd_set_polarity,
1592         },
1593         .pm = {
1594                 .misc = &evergreen_pm_misc,
1595                 .prepare = &evergreen_pm_prepare,
1596                 .finish = &evergreen_pm_finish,
1597                 .init_profile = &sumo_pm_init_profile,
1598                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1599                 .get_engine_clock = &radeon_atom_get_engine_clock,
1600                 .set_engine_clock = &radeon_atom_set_engine_clock,
1601                 .get_memory_clock = NULL,
1602                 .set_memory_clock = NULL,
1603                 .get_pcie_lanes = NULL,
1604                 .set_pcie_lanes = NULL,
1605                 .set_clock_gating = NULL,
1606         },
1607         .pflip = {
1608                 .pre_page_flip = &evergreen_pre_page_flip,
1609                 .page_flip = &evergreen_page_flip,
1610                 .post_page_flip = &evergreen_post_page_flip,
1611         },
1612 };
1613
1614 static struct radeon_asic si_asic = {
1615         .init = &si_init,
1616         .fini = &si_fini,
1617         .suspend = &si_suspend,
1618         .resume = &si_resume,
1619         .asic_reset = &si_asic_reset,
1620         .vga_set_state = &r600_vga_set_state,
1621         .ioctl_wait_idle = r600_ioctl_wait_idle,
1622         .gui_idle = &r600_gui_idle,
1623         .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1624         .gart = {
1625                 .tlb_flush = &si_pcie_gart_tlb_flush,
1626                 .set_page = &rs600_gart_set_page,
1627         },
1628         .vm = {
1629                 .init = &si_vm_init,
1630                 .fini = &si_vm_fini,
1631                 .pt_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1632                 .set_page = &si_vm_set_page,
1633         },
1634         .ring = {
1635                 [RADEON_RING_TYPE_GFX_INDEX] = {
1636                         .ib_execute = &si_ring_ib_execute,
1637                         .ib_parse = &si_ib_parse,
1638                         .emit_fence = &si_fence_ring_emit,
1639                         .emit_semaphore = &r600_semaphore_ring_emit,
1640                         .cs_parse = NULL,
1641                         .ring_test = &r600_ring_test,
1642                         .ib_test = &r600_ib_test,
1643                         .is_lockup = &si_gpu_is_lockup,
1644                         .vm_flush = &si_vm_flush,
1645                 },
1646                 [CAYMAN_RING_TYPE_CP1_INDEX] = {
1647                         .ib_execute = &si_ring_ib_execute,
1648                         .ib_parse = &si_ib_parse,
1649                         .emit_fence = &si_fence_ring_emit,
1650                         .emit_semaphore = &r600_semaphore_ring_emit,
1651                         .cs_parse = NULL,
1652                         .ring_test = &r600_ring_test,
1653                         .ib_test = &r600_ib_test,
1654                         .is_lockup = &si_gpu_is_lockup,
1655                         .vm_flush = &si_vm_flush,
1656                 },
1657                 [CAYMAN_RING_TYPE_CP2_INDEX] = {
1658                         .ib_execute = &si_ring_ib_execute,
1659                         .ib_parse = &si_ib_parse,
1660                         .emit_fence = &si_fence_ring_emit,
1661                         .emit_semaphore = &r600_semaphore_ring_emit,
1662                         .cs_parse = NULL,
1663                         .ring_test = &r600_ring_test,
1664                         .ib_test = &r600_ib_test,
1665                         .is_lockup = &si_gpu_is_lockup,
1666                         .vm_flush = &si_vm_flush,
1667                 }
1668         },
1669         .irq = {
1670                 .set = &si_irq_set,
1671                 .process = &si_irq_process,
1672         },
1673         .display = {
1674                 .bandwidth_update = &dce6_bandwidth_update,
1675                 .get_vblank_counter = &evergreen_get_vblank_counter,
1676                 .wait_for_vblank = &dce4_wait_for_vblank,
1677                 .set_backlight_level = &atombios_set_backlight_level,
1678                 .get_backlight_level = &atombios_get_backlight_level,
1679         },
1680         .copy = {
1681                 .blit = NULL,
1682                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1683                 .dma = NULL,
1684                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1685                 .copy = NULL,
1686                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1687         },
1688         .surface = {
1689                 .set_reg = r600_set_surface_reg,
1690                 .clear_reg = r600_clear_surface_reg,
1691         },
1692         .hpd = {
1693                 .init = &evergreen_hpd_init,
1694                 .fini = &evergreen_hpd_fini,
1695                 .sense = &evergreen_hpd_sense,
1696                 .set_polarity = &evergreen_hpd_set_polarity,
1697         },
1698         .pm = {
1699                 .misc = &evergreen_pm_misc,
1700                 .prepare = &evergreen_pm_prepare,
1701                 .finish = &evergreen_pm_finish,
1702                 .init_profile = &sumo_pm_init_profile,
1703                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1704                 .get_engine_clock = &radeon_atom_get_engine_clock,
1705                 .set_engine_clock = &radeon_atom_set_engine_clock,
1706                 .get_memory_clock = &radeon_atom_get_memory_clock,
1707                 .set_memory_clock = &radeon_atom_set_memory_clock,
1708                 .get_pcie_lanes = NULL,
1709                 .set_pcie_lanes = NULL,
1710                 .set_clock_gating = NULL,
1711         },
1712         .pflip = {
1713                 .pre_page_flip = &evergreen_pre_page_flip,
1714                 .page_flip = &evergreen_page_flip,
1715                 .post_page_flip = &evergreen_post_page_flip,
1716         },
1717 };
1718
1719 /**
1720  * radeon_asic_init - register asic specific callbacks
1721  *
1722  * @rdev: radeon device pointer
1723  *
1724  * Registers the appropriate asic specific callbacks for each
1725  * chip family.  Also sets other asics specific info like the number
1726  * of crtcs and the register aperture accessors (all asics).
1727  * Returns 0 for success.
1728  */
1729 int radeon_asic_init(struct radeon_device *rdev)
1730 {
1731         radeon_register_accessor_init(rdev);
1732
1733         /* set the number of crtcs */
1734         if (rdev->flags & RADEON_SINGLE_CRTC)
1735                 rdev->num_crtc = 1;
1736         else
1737                 rdev->num_crtc = 2;
1738
1739         switch (rdev->family) {
1740         case CHIP_R100:
1741         case CHIP_RV100:
1742         case CHIP_RS100:
1743         case CHIP_RV200:
1744         case CHIP_RS200:
1745                 rdev->asic = &r100_asic;
1746                 break;
1747         case CHIP_R200:
1748         case CHIP_RV250:
1749         case CHIP_RS300:
1750         case CHIP_RV280:
1751                 rdev->asic = &r200_asic;
1752                 break;
1753         case CHIP_R300:
1754         case CHIP_R350:
1755         case CHIP_RV350:
1756         case CHIP_RV380:
1757                 if (rdev->flags & RADEON_IS_PCIE)
1758                         rdev->asic = &r300_asic_pcie;
1759                 else
1760                         rdev->asic = &r300_asic;
1761                 break;
1762         case CHIP_R420:
1763         case CHIP_R423:
1764         case CHIP_RV410:
1765                 rdev->asic = &r420_asic;
1766                 /* handle macs */
1767                 if (rdev->bios == NULL) {
1768                         rdev->asic->pm.get_engine_clock = &radeon_legacy_get_engine_clock;
1769                         rdev->asic->pm.set_engine_clock = &radeon_legacy_set_engine_clock;
1770                         rdev->asic->pm.get_memory_clock = &radeon_legacy_get_memory_clock;
1771                         rdev->asic->pm.set_memory_clock = NULL;
1772                         rdev->asic->display.set_backlight_level = &radeon_legacy_set_backlight_level;
1773                 }
1774                 break;
1775         case CHIP_RS400:
1776         case CHIP_RS480:
1777                 rdev->asic = &rs400_asic;
1778                 break;
1779         case CHIP_RS600:
1780                 rdev->asic = &rs600_asic;
1781                 break;
1782         case CHIP_RS690:
1783         case CHIP_RS740:
1784                 rdev->asic = &rs690_asic;
1785                 break;
1786         case CHIP_RV515:
1787                 rdev->asic = &rv515_asic;
1788                 break;
1789         case CHIP_R520:
1790         case CHIP_RV530:
1791         case CHIP_RV560:
1792         case CHIP_RV570:
1793         case CHIP_R580:
1794                 rdev->asic = &r520_asic;
1795                 break;
1796         case CHIP_R600:
1797         case CHIP_RV610:
1798         case CHIP_RV630:
1799         case CHIP_RV620:
1800         case CHIP_RV635:
1801         case CHIP_RV670:
1802                 rdev->asic = &r600_asic;
1803                 break;
1804         case CHIP_RS780:
1805         case CHIP_RS880:
1806                 rdev->asic = &rs780_asic;
1807                 break;
1808         case CHIP_RV770:
1809         case CHIP_RV730:
1810         case CHIP_RV710:
1811         case CHIP_RV740:
1812                 rdev->asic = &rv770_asic;
1813                 break;
1814         case CHIP_CEDAR:
1815         case CHIP_REDWOOD:
1816         case CHIP_JUNIPER:
1817         case CHIP_CYPRESS:
1818         case CHIP_HEMLOCK:
1819                 /* set num crtcs */
1820                 if (rdev->family == CHIP_CEDAR)
1821                         rdev->num_crtc = 4;
1822                 else
1823                         rdev->num_crtc = 6;
1824                 rdev->asic = &evergreen_asic;
1825                 break;
1826         case CHIP_PALM:
1827         case CHIP_SUMO:
1828         case CHIP_SUMO2:
1829                 rdev->asic = &sumo_asic;
1830                 break;
1831         case CHIP_BARTS:
1832         case CHIP_TURKS:
1833         case CHIP_CAICOS:
1834                 /* set num crtcs */
1835                 if (rdev->family == CHIP_CAICOS)
1836                         rdev->num_crtc = 4;
1837                 else
1838                         rdev->num_crtc = 6;
1839                 rdev->asic = &btc_asic;
1840                 break;
1841         case CHIP_CAYMAN:
1842                 rdev->asic = &cayman_asic;
1843                 /* set num crtcs */
1844                 rdev->num_crtc = 6;
1845                 break;
1846         case CHIP_ARUBA:
1847                 rdev->asic = &trinity_asic;
1848                 /* set num crtcs */
1849                 rdev->num_crtc = 4;
1850                 break;
1851         case CHIP_TAHITI:
1852         case CHIP_PITCAIRN:
1853         case CHIP_VERDE:
1854                 rdev->asic = &si_asic;
1855                 /* set num crtcs */
1856                 rdev->num_crtc = 6;
1857                 break;
1858         default:
1859                 /* FIXME: not supported yet */
1860                 return -EINVAL;
1861         }
1862
1863         if (rdev->flags & RADEON_IS_IGP) {
1864                 rdev->asic->pm.get_memory_clock = NULL;
1865                 rdev->asic->pm.set_memory_clock = NULL;
1866         }
1867
1868         return 0;
1869 }
1870