2 * Copyright 2009 Advanced Micro Devices, Inc.
3 * Copyright 2009 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
23 * Authors: Dave Airlie
30 #define CP_PACKET2 0x80000000
31 #define PACKET2_PAD_SHIFT 0
32 #define PACKET2_PAD_MASK (0x3fffffff << 0)
34 #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
36 #define R6XX_MAX_SH_GPRS 256
37 #define R6XX_MAX_TEMP_GPRS 16
38 #define R6XX_MAX_SH_THREADS 256
39 #define R6XX_MAX_SH_STACK_ENTRIES 4096
40 #define R6XX_MAX_BACKENDS 8
41 #define R6XX_MAX_BACKENDS_MASK 0xff
42 #define R6XX_MAX_SIMDS 8
43 #define R6XX_MAX_SIMDS_MASK 0xff
44 #define R6XX_MAX_PIPES 8
45 #define R6XX_MAX_PIPES_MASK 0xff
48 #define PTE_VALID (1 << 0)
49 #define PTE_SYSTEM (1 << 1)
50 #define PTE_SNOOPED (1 << 2)
51 #define PTE_READABLE (1 << 5)
52 #define PTE_WRITEABLE (1 << 6)
55 #define ARRAY_LINEAR_GENERAL 0x00000000
56 #define ARRAY_LINEAR_ALIGNED 0x00000001
57 #define ARRAY_1D_TILED_THIN1 0x00000002
58 #define ARRAY_2D_TILED_THIN1 0x00000004
61 #define ARB_POP 0x2418
62 #define ENABLE_TC128 (1 << 30)
63 #define ARB_GDEC_RD_CNTL 0x246C
65 #define CC_GC_SHADER_PIPE_CONFIG 0x8950
66 #define CC_RB_BACKEND_DISABLE 0x98F4
67 #define BACKEND_DISABLE(x) ((x) << 16)
69 #define R_028808_CB_COLOR_CONTROL 0x28808
70 #define S_028808_SPECIAL_OP(x) (((x) & 0x7) << 4)
71 #define G_028808_SPECIAL_OP(x) (((x) >> 4) & 0x7)
72 #define C_028808_SPECIAL_OP 0xFFFFFF8F
73 #define V_028808_SPECIAL_NORMAL 0x00
74 #define V_028808_SPECIAL_DISABLE 0x01
75 #define V_028808_SPECIAL_RESOLVE_BOX 0x07
77 #define CB_COLOR0_BASE 0x28040
78 #define CB_COLOR1_BASE 0x28044
79 #define CB_COLOR2_BASE 0x28048
80 #define CB_COLOR3_BASE 0x2804C
81 #define CB_COLOR4_BASE 0x28050
82 #define CB_COLOR5_BASE 0x28054
83 #define CB_COLOR6_BASE 0x28058
84 #define CB_COLOR7_BASE 0x2805C
85 #define CB_COLOR7_FRAG 0x280FC
87 #define CB_COLOR0_SIZE 0x28060
88 #define CB_COLOR0_VIEW 0x28080
89 #define R_028080_CB_COLOR0_VIEW 0x028080
90 #define S_028080_SLICE_START(x) (((x) & 0x7FF) << 0)
91 #define G_028080_SLICE_START(x) (((x) >> 0) & 0x7FF)
92 #define C_028080_SLICE_START 0xFFFFF800
93 #define S_028080_SLICE_MAX(x) (((x) & 0x7FF) << 13)
94 #define G_028080_SLICE_MAX(x) (((x) >> 13) & 0x7FF)
95 #define C_028080_SLICE_MAX 0xFF001FFF
96 #define R_028084_CB_COLOR1_VIEW 0x028084
97 #define R_028088_CB_COLOR2_VIEW 0x028088
98 #define R_02808C_CB_COLOR3_VIEW 0x02808C
99 #define R_028090_CB_COLOR4_VIEW 0x028090
100 #define R_028094_CB_COLOR5_VIEW 0x028094
101 #define R_028098_CB_COLOR6_VIEW 0x028098
102 #define R_02809C_CB_COLOR7_VIEW 0x02809C
103 #define R_028100_CB_COLOR0_MASK 0x028100
104 #define S_028100_CMASK_BLOCK_MAX(x) (((x) & 0xFFF) << 0)
105 #define G_028100_CMASK_BLOCK_MAX(x) (((x) >> 0) & 0xFFF)
106 #define C_028100_CMASK_BLOCK_MAX 0xFFFFF000
107 #define S_028100_FMASK_TILE_MAX(x) (((x) & 0xFFFFF) << 12)
108 #define G_028100_FMASK_TILE_MAX(x) (((x) >> 12) & 0xFFFFF)
109 #define C_028100_FMASK_TILE_MAX 0x00000FFF
110 #define R_028104_CB_COLOR1_MASK 0x028104
111 #define R_028108_CB_COLOR2_MASK 0x028108
112 #define R_02810C_CB_COLOR3_MASK 0x02810C
113 #define R_028110_CB_COLOR4_MASK 0x028110
114 #define R_028114_CB_COLOR5_MASK 0x028114
115 #define R_028118_CB_COLOR6_MASK 0x028118
116 #define R_02811C_CB_COLOR7_MASK 0x02811C
117 #define CB_COLOR0_INFO 0x280a0
118 # define CB_FORMAT(x) ((x) << 2)
119 # define CB_ARRAY_MODE(x) ((x) << 8)
120 # define CB_SOURCE_FORMAT(x) ((x) << 27)
121 # define CB_SF_EXPORT_FULL 0
122 # define CB_SF_EXPORT_NORM 1
123 #define CB_COLOR0_TILE 0x280c0
124 #define CB_COLOR0_FRAG 0x280e0
125 #define CB_COLOR0_MASK 0x28100
127 #define SQ_ALU_CONST_CACHE_PS_0 0x28940
128 #define SQ_ALU_CONST_CACHE_PS_1 0x28944
129 #define SQ_ALU_CONST_CACHE_PS_2 0x28948
130 #define SQ_ALU_CONST_CACHE_PS_3 0x2894c
131 #define SQ_ALU_CONST_CACHE_PS_4 0x28950
132 #define SQ_ALU_CONST_CACHE_PS_5 0x28954
133 #define SQ_ALU_CONST_CACHE_PS_6 0x28958
134 #define SQ_ALU_CONST_CACHE_PS_7 0x2895c
135 #define SQ_ALU_CONST_CACHE_PS_8 0x28960
136 #define SQ_ALU_CONST_CACHE_PS_9 0x28964
137 #define SQ_ALU_CONST_CACHE_PS_10 0x28968
138 #define SQ_ALU_CONST_CACHE_PS_11 0x2896c
139 #define SQ_ALU_CONST_CACHE_PS_12 0x28970
140 #define SQ_ALU_CONST_CACHE_PS_13 0x28974
141 #define SQ_ALU_CONST_CACHE_PS_14 0x28978
142 #define SQ_ALU_CONST_CACHE_PS_15 0x2897c
143 #define SQ_ALU_CONST_CACHE_VS_0 0x28980
144 #define SQ_ALU_CONST_CACHE_VS_1 0x28984
145 #define SQ_ALU_CONST_CACHE_VS_2 0x28988
146 #define SQ_ALU_CONST_CACHE_VS_3 0x2898c
147 #define SQ_ALU_CONST_CACHE_VS_4 0x28990
148 #define SQ_ALU_CONST_CACHE_VS_5 0x28994
149 #define SQ_ALU_CONST_CACHE_VS_6 0x28998
150 #define SQ_ALU_CONST_CACHE_VS_7 0x2899c
151 #define SQ_ALU_CONST_CACHE_VS_8 0x289a0
152 #define SQ_ALU_CONST_CACHE_VS_9 0x289a4
153 #define SQ_ALU_CONST_CACHE_VS_10 0x289a8
154 #define SQ_ALU_CONST_CACHE_VS_11 0x289ac
155 #define SQ_ALU_CONST_CACHE_VS_12 0x289b0
156 #define SQ_ALU_CONST_CACHE_VS_13 0x289b4
157 #define SQ_ALU_CONST_CACHE_VS_14 0x289b8
158 #define SQ_ALU_CONST_CACHE_VS_15 0x289bc
159 #define SQ_ALU_CONST_CACHE_GS_0 0x289c0
160 #define SQ_ALU_CONST_CACHE_GS_1 0x289c4
161 #define SQ_ALU_CONST_CACHE_GS_2 0x289c8
162 #define SQ_ALU_CONST_CACHE_GS_3 0x289cc
163 #define SQ_ALU_CONST_CACHE_GS_4 0x289d0
164 #define SQ_ALU_CONST_CACHE_GS_5 0x289d4
165 #define SQ_ALU_CONST_CACHE_GS_6 0x289d8
166 #define SQ_ALU_CONST_CACHE_GS_7 0x289dc
167 #define SQ_ALU_CONST_CACHE_GS_8 0x289e0
168 #define SQ_ALU_CONST_CACHE_GS_9 0x289e4
169 #define SQ_ALU_CONST_CACHE_GS_10 0x289e8
170 #define SQ_ALU_CONST_CACHE_GS_11 0x289ec
171 #define SQ_ALU_CONST_CACHE_GS_12 0x289f0
172 #define SQ_ALU_CONST_CACHE_GS_13 0x289f4
173 #define SQ_ALU_CONST_CACHE_GS_14 0x289f8
174 #define SQ_ALU_CONST_CACHE_GS_15 0x289fc
176 #define CONFIG_MEMSIZE 0x5428
177 #define CONFIG_CNTL 0x5424
178 #define CP_STALLED_STAT1 0x8674
179 #define CP_STALLED_STAT2 0x8678
180 #define CP_BUSY_STAT 0x867C
181 #define CP_STAT 0x8680
182 #define CP_COHER_BASE 0x85F8
183 #define CP_DEBUG 0xC1FC
184 #define R_0086D8_CP_ME_CNTL 0x86D8
185 #define S_0086D8_CP_PFP_HALT(x) (((x) & 1)<<26)
186 #define C_0086D8_CP_PFP_HALT(x) ((x) & 0xFBFFFFFF)
187 #define S_0086D8_CP_ME_HALT(x) (((x) & 1)<<28)
188 #define C_0086D8_CP_ME_HALT(x) ((x) & 0xEFFFFFFF)
189 #define CP_ME_RAM_DATA 0xC160
190 #define CP_ME_RAM_RADDR 0xC158
191 #define CP_ME_RAM_WADDR 0xC15C
192 #define CP_MEQ_THRESHOLDS 0x8764
193 #define MEQ_END(x) ((x) << 16)
194 #define ROQ_END(x) ((x) << 24)
195 #define CP_PERFMON_CNTL 0x87FC
196 #define CP_PFP_UCODE_ADDR 0xC150
197 #define CP_PFP_UCODE_DATA 0xC154
198 #define CP_QUEUE_THRESHOLDS 0x8760
199 #define ROQ_IB1_START(x) ((x) << 0)
200 #define ROQ_IB2_START(x) ((x) << 8)
201 #define CP_RB_BASE 0xC100
202 #define CP_RB_CNTL 0xC104
203 #define RB_BUFSZ(x) ((x) << 0)
204 #define RB_BLKSZ(x) ((x) << 8)
205 #define RB_NO_UPDATE (1 << 27)
206 #define RB_RPTR_WR_ENA (1 << 31)
207 #define BUF_SWAP_32BIT (2 << 16)
208 #define CP_RB_RPTR 0x8700
209 #define CP_RB_RPTR_ADDR 0xC10C
210 #define RB_RPTR_SWAP(x) ((x) << 0)
211 #define CP_RB_RPTR_ADDR_HI 0xC110
212 #define CP_RB_RPTR_WR 0xC108
213 #define CP_RB_WPTR 0xC114
214 #define CP_RB_WPTR_ADDR 0xC118
215 #define CP_RB_WPTR_ADDR_HI 0xC11C
216 #define CP_RB_WPTR_DELAY 0x8704
217 #define CP_ROQ_IB1_STAT 0x8784
218 #define CP_ROQ_IB2_STAT 0x8788
219 #define CP_SEM_WAIT_TIMER 0x85BC
221 #define DB_DEBUG 0x9830
222 #define PREZ_MUST_WAIT_FOR_POSTZ_DONE (1 << 31)
223 #define DB_DEPTH_BASE 0x2800C
224 #define DB_HTILE_DATA_BASE 0x28014
225 #define DB_HTILE_SURFACE 0x28D24
226 #define S_028D24_HTILE_WIDTH(x) (((x) & 0x1) << 0)
227 #define G_028D24_HTILE_WIDTH(x) (((x) >> 0) & 0x1)
228 #define C_028D24_HTILE_WIDTH 0xFFFFFFFE
229 #define S_028D24_HTILE_HEIGHT(x) (((x) & 0x1) << 1)
230 #define G_028D24_HTILE_HEIGHT(x) (((x) >> 1) & 0x1)
231 #define C_028D24_HTILE_HEIGHT 0xFFFFFFFD
232 #define G_028D24_LINEAR(x) (((x) >> 2) & 0x1)
233 #define DB_WATERMARKS 0x9838
234 #define DEPTH_FREE(x) ((x) << 0)
235 #define DEPTH_FLUSH(x) ((x) << 5)
236 #define DEPTH_PENDING_FREE(x) ((x) << 15)
237 #define DEPTH_CACHELINE_FREE(x) ((x) << 20)
239 #define DCP_TILING_CONFIG 0x6CA0
240 #define PIPE_TILING(x) ((x) << 1)
241 #define BANK_TILING(x) ((x) << 4)
242 #define GROUP_SIZE(x) ((x) << 6)
243 #define ROW_TILING(x) ((x) << 8)
244 #define BANK_SWAPS(x) ((x) << 11)
245 #define SAMPLE_SPLIT(x) ((x) << 14)
246 #define BACKEND_MAP(x) ((x) << 16)
248 #define GB_TILING_CONFIG 0x98F0
249 #define PIPE_TILING__SHIFT 1
250 #define PIPE_TILING__MASK 0x0000000e
252 #define GC_USER_SHADER_PIPE_CONFIG 0x8954
253 #define INACTIVE_QD_PIPES(x) ((x) << 8)
254 #define INACTIVE_QD_PIPES_MASK 0x0000FF00
255 #define INACTIVE_SIMDS(x) ((x) << 16)
256 #define INACTIVE_SIMDS_MASK 0x00FF0000
258 #define SQ_CONFIG 0x8c00
259 # define VC_ENABLE (1 << 0)
260 # define EXPORT_SRC_C (1 << 1)
261 # define DX9_CONSTS (1 << 2)
262 # define ALU_INST_PREFER_VECTOR (1 << 3)
263 # define DX10_CLAMP (1 << 4)
264 # define CLAUSE_SEQ_PRIO(x) ((x) << 8)
265 # define PS_PRIO(x) ((x) << 24)
266 # define VS_PRIO(x) ((x) << 26)
267 # define GS_PRIO(x) ((x) << 28)
268 # define ES_PRIO(x) ((x) << 30)
269 #define SQ_GPR_RESOURCE_MGMT_1 0x8c04
270 # define NUM_PS_GPRS(x) ((x) << 0)
271 # define NUM_VS_GPRS(x) ((x) << 16)
272 # define NUM_CLAUSE_TEMP_GPRS(x) ((x) << 28)
273 #define SQ_GPR_RESOURCE_MGMT_2 0x8c08
274 # define NUM_GS_GPRS(x) ((x) << 0)
275 # define NUM_ES_GPRS(x) ((x) << 16)
276 #define SQ_THREAD_RESOURCE_MGMT 0x8c0c
277 # define NUM_PS_THREADS(x) ((x) << 0)
278 # define NUM_VS_THREADS(x) ((x) << 8)
279 # define NUM_GS_THREADS(x) ((x) << 16)
280 # define NUM_ES_THREADS(x) ((x) << 24)
281 #define SQ_STACK_RESOURCE_MGMT_1 0x8c10
282 # define NUM_PS_STACK_ENTRIES(x) ((x) << 0)
283 # define NUM_VS_STACK_ENTRIES(x) ((x) << 16)
284 #define SQ_STACK_RESOURCE_MGMT_2 0x8c14
285 # define NUM_GS_STACK_ENTRIES(x) ((x) << 0)
286 # define NUM_ES_STACK_ENTRIES(x) ((x) << 16)
287 #define SQ_ESGS_RING_BASE 0x8c40
288 #define SQ_GSVS_RING_BASE 0x8c48
289 #define SQ_ESTMP_RING_BASE 0x8c50
290 #define SQ_GSTMP_RING_BASE 0x8c58
291 #define SQ_VSTMP_RING_BASE 0x8c60
292 #define SQ_PSTMP_RING_BASE 0x8c68
293 #define SQ_FBUF_RING_BASE 0x8c70
294 #define SQ_REDUC_RING_BASE 0x8c78
296 #define GRBM_CNTL 0x8000
297 # define GRBM_READ_TIMEOUT(x) ((x) << 0)
298 #define GRBM_STATUS 0x8010
299 #define CMDFIFO_AVAIL_MASK 0x0000001F
300 #define GUI_ACTIVE (1<<31)
301 #define GRBM_STATUS2 0x8014
302 #define GRBM_SOFT_RESET 0x8020
303 #define SOFT_RESET_CP (1<<0)
305 #define CG_THERMAL_CTRL 0x7F0
306 #define DIG_THERM_DPM(x) ((x) << 12)
307 #define DIG_THERM_DPM_MASK 0x000FF000
308 #define DIG_THERM_DPM_SHIFT 12
309 #define CG_THERMAL_STATUS 0x7F4
310 #define ASIC_T(x) ((x) << 0)
311 #define ASIC_T_MASK 0x1FF
312 #define ASIC_T_SHIFT 0
313 #define CG_THERMAL_INT 0x7F8
314 #define DIG_THERM_INTH(x) ((x) << 8)
315 #define DIG_THERM_INTH_MASK 0x0000FF00
316 #define DIG_THERM_INTH_SHIFT 8
317 #define DIG_THERM_INTL(x) ((x) << 16)
318 #define DIG_THERM_INTL_MASK 0x00FF0000
319 #define DIG_THERM_INTL_SHIFT 16
320 #define THERM_INT_MASK_HIGH (1 << 24)
321 #define THERM_INT_MASK_LOW (1 << 25)
323 #define RV770_CG_THERMAL_INT 0x734
325 #define HDP_HOST_PATH_CNTL 0x2C00
326 #define HDP_NONSURFACE_BASE 0x2C04
327 #define HDP_NONSURFACE_INFO 0x2C08
328 #define HDP_NONSURFACE_SIZE 0x2C0C
329 #define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0
330 #define HDP_TILING_CONFIG 0x2F3C
331 #define HDP_DEBUG1 0x2F34
333 #define MC_CONFIG 0x2000
334 #define MC_VM_AGP_TOP 0x2184
335 #define MC_VM_AGP_BOT 0x2188
336 #define MC_VM_AGP_BASE 0x218C
337 #define MC_VM_FB_LOCATION 0x2180
338 #define MC_VM_L1_TLB_MCB_RD_UVD_CNTL 0x2124
339 #define ENABLE_L1_TLB (1 << 0)
340 #define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1)
341 #define ENABLE_L1_STRICT_ORDERING (1 << 2)
342 #define SYSTEM_ACCESS_MODE_MASK 0x000000C0
343 #define SYSTEM_ACCESS_MODE_SHIFT 6
344 #define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 6)
345 #define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 6)
346 #define SYSTEM_ACCESS_MODE_IN_SYS (2 << 6)
347 #define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 6)
348 #define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 8)
349 #define SYSTEM_APERTURE_UNMAPPED_ACCESS_DEFAULT_PAGE (1 << 8)
350 #define ENABLE_SEMAPHORE_MODE (1 << 10)
351 #define ENABLE_WAIT_L2_QUERY (1 << 11)
352 #define EFFECTIVE_L1_TLB_SIZE(x) (((x) & 7) << 12)
353 #define EFFECTIVE_L1_TLB_SIZE_MASK 0x00007000
354 #define EFFECTIVE_L1_TLB_SIZE_SHIFT 12
355 #define EFFECTIVE_L1_QUEUE_SIZE(x) (((x) & 7) << 15)
356 #define EFFECTIVE_L1_QUEUE_SIZE_MASK 0x00038000
357 #define EFFECTIVE_L1_QUEUE_SIZE_SHIFT 15
358 #define MC_VM_L1_TLB_MCD_RD_A_CNTL 0x219C
359 #define MC_VM_L1_TLB_MCD_RD_B_CNTL 0x21A0
360 #define MC_VM_L1_TLB_MCB_RD_GFX_CNTL 0x21FC
361 #define MC_VM_L1_TLB_MCB_RD_HDP_CNTL 0x2204
362 #define MC_VM_L1_TLB_MCB_RD_PDMA_CNTL 0x2208
363 #define MC_VM_L1_TLB_MCB_RD_SEM_CNTL 0x220C
364 #define MC_VM_L1_TLB_MCB_RD_SYS_CNTL 0x2200
365 #define MC_VM_L1_TLB_MCB_WR_UVD_CNTL 0x212c
366 #define MC_VM_L1_TLB_MCD_WR_A_CNTL 0x21A4
367 #define MC_VM_L1_TLB_MCD_WR_B_CNTL 0x21A8
368 #define MC_VM_L1_TLB_MCB_WR_GFX_CNTL 0x2210
369 #define MC_VM_L1_TLB_MCB_WR_HDP_CNTL 0x2218
370 #define MC_VM_L1_TLB_MCB_WR_PDMA_CNTL 0x221C
371 #define MC_VM_L1_TLB_MCB_WR_SEM_CNTL 0x2220
372 #define MC_VM_L1_TLB_MCB_WR_SYS_CNTL 0x2214
373 #define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2190
374 #define LOGICAL_PAGE_NUMBER_MASK 0x000FFFFF
375 #define LOGICAL_PAGE_NUMBER_SHIFT 0
376 #define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2194
377 #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x2198
379 #define RS_DQ_RD_RET_CONF 0x2348
381 #define PA_CL_ENHANCE 0x8A14
382 #define CLIP_VTX_REORDER_ENA (1 << 0)
383 #define NUM_CLIP_SEQ(x) ((x) << 1)
384 #define PA_SC_AA_CONFIG 0x28C04
385 #define PA_SC_AA_SAMPLE_LOCS_2S 0x8B40
386 #define PA_SC_AA_SAMPLE_LOCS_4S 0x8B44
387 #define PA_SC_AA_SAMPLE_LOCS_8S_WD0 0x8B48
388 #define PA_SC_AA_SAMPLE_LOCS_8S_WD1 0x8B4C
389 #define S0_X(x) ((x) << 0)
390 #define S0_Y(x) ((x) << 4)
391 #define S1_X(x) ((x) << 8)
392 #define S1_Y(x) ((x) << 12)
393 #define S2_X(x) ((x) << 16)
394 #define S2_Y(x) ((x) << 20)
395 #define S3_X(x) ((x) << 24)
396 #define S3_Y(x) ((x) << 28)
397 #define S4_X(x) ((x) << 0)
398 #define S4_Y(x) ((x) << 4)
399 #define S5_X(x) ((x) << 8)
400 #define S5_Y(x) ((x) << 12)
401 #define S6_X(x) ((x) << 16)
402 #define S6_Y(x) ((x) << 20)
403 #define S7_X(x) ((x) << 24)
404 #define S7_Y(x) ((x) << 28)
405 #define PA_SC_CLIPRECT_RULE 0x2820c
406 #define PA_SC_ENHANCE 0x8BF0
407 #define FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0)
408 #define FORCE_EOV_MAX_TILE_CNT(x) ((x) << 12)
409 #define PA_SC_LINE_STIPPLE 0x28A0C
410 #define PA_SC_LINE_STIPPLE_STATE 0x8B10
411 #define PA_SC_MODE_CNTL 0x28A4C
412 #define PA_SC_MULTI_CHIP_CNTL 0x8B20
414 #define PA_SC_SCREEN_SCISSOR_TL 0x28030
415 #define PA_SC_GENERIC_SCISSOR_TL 0x28240
416 #define PA_SC_WINDOW_SCISSOR_TL 0x28204
418 #define PCIE_PORT_INDEX 0x0038
419 #define PCIE_PORT_DATA 0x003C
422 #define NOOFCHAN_SHIFT 12
423 #define NOOFCHAN_MASK 0x00003000
425 #define RAMCFG 0x2408
426 #define NOOFBANK_SHIFT 0
427 #define NOOFBANK_MASK 0x00000001
428 #define NOOFRANK_SHIFT 1
429 #define NOOFRANK_MASK 0x00000002
430 #define NOOFROWS_SHIFT 2
431 #define NOOFROWS_MASK 0x0000001C
432 #define NOOFCOLS_SHIFT 5
433 #define NOOFCOLS_MASK 0x00000060
434 #define CHANSIZE_SHIFT 7
435 #define CHANSIZE_MASK 0x00000080
436 #define BURSTLENGTH_SHIFT 8
437 #define BURSTLENGTH_MASK 0x00000100
438 #define CHANSIZE_OVERRIDE (1 << 10)
440 #define SCRATCH_REG0 0x8500
441 #define SCRATCH_REG1 0x8504
442 #define SCRATCH_REG2 0x8508
443 #define SCRATCH_REG3 0x850C
444 #define SCRATCH_REG4 0x8510
445 #define SCRATCH_REG5 0x8514
446 #define SCRATCH_REG6 0x8518
447 #define SCRATCH_REG7 0x851C
448 #define SCRATCH_UMSK 0x8540
449 #define SCRATCH_ADDR 0x8544
451 #define SPI_CONFIG_CNTL 0x9100
452 #define GPR_WRITE_PRIORITY(x) ((x) << 0)
453 #define DISABLE_INTERP_1 (1 << 5)
454 #define SPI_CONFIG_CNTL_1 0x913C
455 #define VTX_DONE_DELAY(x) ((x) << 0)
456 #define INTERP_ONE_PRIM_PER_ROW (1 << 4)
457 #define SPI_INPUT_Z 0x286D8
458 #define SPI_PS_IN_CONTROL_0 0x286CC
459 #define NUM_INTERP(x) ((x)<<0)
460 #define POSITION_ENA (1<<8)
461 #define POSITION_CENTROID (1<<9)
462 #define POSITION_ADDR(x) ((x)<<10)
463 #define PARAM_GEN(x) ((x)<<15)
464 #define PARAM_GEN_ADDR(x) ((x)<<19)
465 #define BARYC_SAMPLE_CNTL(x) ((x)<<26)
466 #define PERSP_GRADIENT_ENA (1<<28)
467 #define LINEAR_GRADIENT_ENA (1<<29)
468 #define POSITION_SAMPLE (1<<30)
469 #define BARYC_AT_SAMPLE_ENA (1<<31)
470 #define SPI_PS_IN_CONTROL_1 0x286D0
471 #define GEN_INDEX_PIX (1<<0)
472 #define GEN_INDEX_PIX_ADDR(x) ((x)<<1)
473 #define FRONT_FACE_ENA (1<<8)
474 #define FRONT_FACE_CHAN(x) ((x)<<9)
475 #define FRONT_FACE_ALL_BITS (1<<11)
476 #define FRONT_FACE_ADDR(x) ((x)<<12)
477 #define FOG_ADDR(x) ((x)<<17)
478 #define FIXED_PT_POSITION_ENA (1<<24)
479 #define FIXED_PT_POSITION_ADDR(x) ((x)<<25)
481 #define SQ_MS_FIFO_SIZES 0x8CF0
482 #define CACHE_FIFO_SIZE(x) ((x) << 0)
483 #define FETCH_FIFO_HIWATER(x) ((x) << 8)
484 #define DONE_FIFO_HIWATER(x) ((x) << 16)
485 #define ALU_UPDATE_FIFO_HIWATER(x) ((x) << 24)
486 #define SQ_PGM_START_ES 0x28880
487 #define SQ_PGM_START_FS 0x28894
488 #define SQ_PGM_START_GS 0x2886C
489 #define SQ_PGM_START_PS 0x28840
490 #define SQ_PGM_RESOURCES_PS 0x28850
491 #define SQ_PGM_EXPORTS_PS 0x28854
492 #define SQ_PGM_CF_OFFSET_PS 0x288cc
493 #define SQ_PGM_START_VS 0x28858
494 #define SQ_PGM_RESOURCES_VS 0x28868
495 #define SQ_PGM_CF_OFFSET_VS 0x288d0
497 #define SQ_VTX_CONSTANT_WORD0_0 0x30000
498 #define SQ_VTX_CONSTANT_WORD1_0 0x30004
499 #define SQ_VTX_CONSTANT_WORD2_0 0x30008
500 # define SQ_VTXC_BASE_ADDR_HI(x) ((x) << 0)
501 # define SQ_VTXC_STRIDE(x) ((x) << 8)
502 # define SQ_VTXC_ENDIAN_SWAP(x) ((x) << 30)
503 # define SQ_ENDIAN_NONE 0
504 # define SQ_ENDIAN_8IN16 1
505 # define SQ_ENDIAN_8IN32 2
506 #define SQ_VTX_CONSTANT_WORD3_0 0x3000c
507 #define SQ_VTX_CONSTANT_WORD6_0 0x38018
508 #define S__SQ_VTX_CONSTANT_TYPE(x) (((x) & 3) << 30)
509 #define G__SQ_VTX_CONSTANT_TYPE(x) (((x) >> 30) & 3)
510 #define SQ_TEX_VTX_INVALID_TEXTURE 0x0
511 #define SQ_TEX_VTX_INVALID_BUFFER 0x1
512 #define SQ_TEX_VTX_VALID_TEXTURE 0x2
513 #define SQ_TEX_VTX_VALID_BUFFER 0x3
516 #define SX_MISC 0x28350
517 #define SX_MEMORY_EXPORT_BASE 0x9010
518 #define SX_DEBUG_1 0x9054
519 #define SMX_EVENT_RELEASE (1 << 0)
520 #define ENABLE_NEW_SMX_ADDRESS (1 << 16)
522 #define TA_CNTL_AUX 0x9508
523 #define DISABLE_CUBE_WRAP (1 << 0)
524 #define DISABLE_CUBE_ANISO (1 << 1)
525 #define SYNC_GRADIENT (1 << 24)
526 #define SYNC_WALKER (1 << 25)
527 #define SYNC_ALIGNER (1 << 26)
528 #define BILINEAR_PRECISION_6_BIT (0 << 31)
529 #define BILINEAR_PRECISION_8_BIT (1 << 31)
531 #define TC_CNTL 0x9608
532 #define TC_L2_SIZE(x) ((x)<<5)
533 #define L2_DISABLE_LATE_HIT (1<<9)
535 #define VC_ENHANCE 0x9714
537 #define VGT_CACHE_INVALIDATION 0x88C4
538 #define CACHE_INVALIDATION(x) ((x)<<0)
542 #define VGT_DMA_BASE 0x287E8
543 #define VGT_DMA_BASE_HI 0x287E4
544 #define VGT_ES_PER_GS 0x88CC
545 #define VGT_GS_PER_ES 0x88C8
546 #define VGT_GS_PER_VS 0x88E8
547 #define VGT_GS_VERTEX_REUSE 0x88D4
548 #define VGT_PRIMITIVE_TYPE 0x8958
549 #define VGT_NUM_INSTANCES 0x8974
550 #define VGT_OUT_DEALLOC_CNTL 0x28C5C
551 #define DEALLOC_DIST_MASK 0x0000007F
552 #define VGT_STRMOUT_BASE_OFFSET_0 0x28B10
553 #define VGT_STRMOUT_BASE_OFFSET_1 0x28B14
554 #define VGT_STRMOUT_BASE_OFFSET_2 0x28B18
555 #define VGT_STRMOUT_BASE_OFFSET_3 0x28B1c
556 #define VGT_STRMOUT_BASE_OFFSET_HI_0 0x28B44
557 #define VGT_STRMOUT_BASE_OFFSET_HI_1 0x28B48
558 #define VGT_STRMOUT_BASE_OFFSET_HI_2 0x28B4c
559 #define VGT_STRMOUT_BASE_OFFSET_HI_3 0x28B50
560 #define VGT_STRMOUT_BUFFER_BASE_0 0x28AD8
561 #define VGT_STRMOUT_BUFFER_BASE_1 0x28AE8
562 #define VGT_STRMOUT_BUFFER_BASE_2 0x28AF8
563 #define VGT_STRMOUT_BUFFER_BASE_3 0x28B08
564 #define VGT_STRMOUT_BUFFER_OFFSET_0 0x28ADC
565 #define VGT_STRMOUT_BUFFER_OFFSET_1 0x28AEC
566 #define VGT_STRMOUT_BUFFER_OFFSET_2 0x28AFC
567 #define VGT_STRMOUT_BUFFER_OFFSET_3 0x28B0C
568 #define VGT_STRMOUT_BUFFER_SIZE_0 0x28AD0
569 #define VGT_STRMOUT_BUFFER_SIZE_1 0x28AE0
570 #define VGT_STRMOUT_BUFFER_SIZE_2 0x28AF0
571 #define VGT_STRMOUT_BUFFER_SIZE_3 0x28B00
573 #define VGT_STRMOUT_EN 0x28AB0
574 #define VGT_VERTEX_REUSE_BLOCK_CNTL 0x28C58
575 #define VTX_REUSE_DEPTH_MASK 0x000000FF
576 #define VGT_EVENT_INITIATOR 0x28a90
577 # define CACHE_FLUSH_AND_INV_EVENT_TS (0x14 << 0)
578 # define CACHE_FLUSH_AND_INV_EVENT (0x16 << 0)
580 #define VM_CONTEXT0_CNTL 0x1410
581 #define ENABLE_CONTEXT (1 << 0)
582 #define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1)
583 #define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4)
584 #define VM_CONTEXT0_INVALIDATION_LOW_ADDR 0x1490
585 #define VM_CONTEXT0_INVALIDATION_HIGH_ADDR 0x14B0
586 #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x1574
587 #define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x1594
588 #define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x15B4
589 #define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1554
590 #define VM_CONTEXT0_REQUEST_RESPONSE 0x1470
591 #define REQUEST_TYPE(x) (((x) & 0xf) << 0)
592 #define RESPONSE_TYPE_MASK 0x000000F0
593 #define RESPONSE_TYPE_SHIFT 4
594 #define VM_L2_CNTL 0x1400
595 #define ENABLE_L2_CACHE (1 << 0)
596 #define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1)
597 #define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9)
598 #define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 13)
599 #define VM_L2_CNTL2 0x1404
600 #define INVALIDATE_ALL_L1_TLBS (1 << 0)
601 #define INVALIDATE_L2_CACHE (1 << 1)
602 #define VM_L2_CNTL3 0x1408
603 #define BANK_SELECT_0(x) (((x) & 0x1f) << 0)
604 #define BANK_SELECT_1(x) (((x) & 0x1f) << 5)
605 #define L2_CACHE_UPDATE_MODE(x) (((x) & 3) << 10)
606 #define VM_L2_STATUS 0x140C
607 #define L2_BUSY (1 << 0)
609 #define WAIT_UNTIL 0x8040
610 #define WAIT_CP_DMA_IDLE_bit (1 << 8)
611 #define WAIT_2D_IDLE_bit (1 << 14)
612 #define WAIT_3D_IDLE_bit (1 << 15)
613 #define WAIT_2D_IDLECLEAN_bit (1 << 16)
614 #define WAIT_3D_IDLECLEAN_bit (1 << 17)
617 #define DMA_TILING_CONFIG 0x3ec4
618 #define DMA_CONFIG 0x3e4c
620 #define DMA_RB_CNTL 0xd000
621 # define DMA_RB_ENABLE (1 << 0)
622 # define DMA_RB_SIZE(x) ((x) << 1) /* log2 */
623 # define DMA_RB_SWAP_ENABLE (1 << 9) /* 8IN32 */
624 # define DMA_RPTR_WRITEBACK_ENABLE (1 << 12)
625 # define DMA_RPTR_WRITEBACK_SWAP_ENABLE (1 << 13) /* 8IN32 */
626 # define DMA_RPTR_WRITEBACK_TIMER(x) ((x) << 16) /* log2 */
627 #define DMA_RB_BASE 0xd004
628 #define DMA_RB_RPTR 0xd008
629 #define DMA_RB_WPTR 0xd00c
631 #define DMA_RB_RPTR_ADDR_HI 0xd01c
632 #define DMA_RB_RPTR_ADDR_LO 0xd020
634 #define DMA_IB_CNTL 0xd024
635 # define DMA_IB_ENABLE (1 << 0)
636 # define DMA_IB_SWAP_ENABLE (1 << 4)
637 #define DMA_IB_RPTR 0xd028
638 #define DMA_CNTL 0xd02c
639 # define TRAP_ENABLE (1 << 0)
640 # define SEM_INCOMPLETE_INT_ENABLE (1 << 1)
641 # define SEM_WAIT_INT_ENABLE (1 << 2)
642 # define DATA_SWAP_ENABLE (1 << 3)
643 # define FENCE_SWAP_ENABLE (1 << 4)
644 # define CTXEMPTY_INT_ENABLE (1 << 28)
645 #define DMA_STATUS_REG 0xd034
646 # define DMA_IDLE (1 << 0)
647 #define DMA_SEM_INCOMPLETE_TIMER_CNTL 0xd044
648 #define DMA_SEM_WAIT_FAIL_TIMER_CNTL 0xd048
649 #define DMA_MODE 0xd0bc
651 /* async DMA packets */
652 #define DMA_PACKET(cmd, t, s, n) ((((cmd) & 0xF) << 28) | \
653 (((t) & 0x1) << 23) | \
654 (((s) & 0x1) << 22) | \
655 (((n) & 0xFFFF) << 0))
656 /* async DMA Packet types */
657 #define DMA_PACKET_WRITE 0x2
658 #define DMA_PACKET_COPY 0x3
659 #define DMA_PACKET_INDIRECT_BUFFER 0x4
660 #define DMA_PACKET_SEMAPHORE 0x5
661 #define DMA_PACKET_FENCE 0x6
662 #define DMA_PACKET_TRAP 0x7
663 #define DMA_PACKET_CONSTANT_FILL 0xd /* 7xx only */
664 #define DMA_PACKET_NOP 0xf
666 #define IH_RB_CNTL 0x3e00
667 # define IH_RB_ENABLE (1 << 0)
668 # define IH_RB_SIZE(x) ((x) << 1) /* log2 */
669 # define IH_RB_FULL_DRAIN_ENABLE (1 << 6)
670 # define IH_WPTR_WRITEBACK_ENABLE (1 << 8)
671 # define IH_WPTR_WRITEBACK_TIMER(x) ((x) << 9) /* log2 */
672 # define IH_WPTR_OVERFLOW_ENABLE (1 << 16)
673 # define IH_WPTR_OVERFLOW_CLEAR (1 << 31)
674 #define IH_RB_BASE 0x3e04
675 #define IH_RB_RPTR 0x3e08
676 #define IH_RB_WPTR 0x3e0c
677 # define RB_OVERFLOW (1 << 0)
678 # define WPTR_OFFSET_MASK 0x3fffc
679 #define IH_RB_WPTR_ADDR_HI 0x3e10
680 #define IH_RB_WPTR_ADDR_LO 0x3e14
681 #define IH_CNTL 0x3e18
682 # define ENABLE_INTR (1 << 0)
683 # define IH_MC_SWAP(x) ((x) << 1)
684 # define IH_MC_SWAP_NONE 0
685 # define IH_MC_SWAP_16BIT 1
686 # define IH_MC_SWAP_32BIT 2
687 # define IH_MC_SWAP_64BIT 3
688 # define RPTR_REARM (1 << 4)
689 # define MC_WRREQ_CREDIT(x) ((x) << 15)
690 # define MC_WR_CLEAN_CNT(x) ((x) << 20)
692 #define RLC_CNTL 0x3f00
693 # define RLC_ENABLE (1 << 0)
694 #define RLC_HB_BASE 0x3f10
695 #define RLC_HB_CNTL 0x3f0c
696 #define RLC_HB_RPTR 0x3f20
697 #define RLC_HB_WPTR 0x3f1c
698 #define RLC_HB_WPTR_LSB_ADDR 0x3f14
699 #define RLC_HB_WPTR_MSB_ADDR 0x3f18
700 #define RLC_GPU_CLOCK_COUNT_LSB 0x3f38
701 #define RLC_GPU_CLOCK_COUNT_MSB 0x3f3c
702 #define RLC_CAPTURE_GPU_CLOCK_COUNT 0x3f40
703 #define RLC_MC_CNTL 0x3f44
704 #define RLC_UCODE_CNTL 0x3f48
705 #define RLC_UCODE_ADDR 0x3f2c
706 #define RLC_UCODE_DATA 0x3f30
708 #define SRBM_SOFT_RESET 0xe60
709 # define SOFT_RESET_BIF (1 << 1)
710 # define SOFT_RESET_DMA (1 << 12)
711 # define SOFT_RESET_RLC (1 << 13)
712 # define SOFT_RESET_UVD (1 << 18)
713 # define RV770_SOFT_RESET_DMA (1 << 20)
715 #define BIF_SCRATCH0 0x5438
717 #define BUS_CNTL 0x5420
718 # define BIOS_ROM_DIS (1 << 1)
719 # define VGA_COHE_SPEC_TIMER_DIS (1 << 9)
721 #define CP_INT_CNTL 0xc124
722 # define CNTX_BUSY_INT_ENABLE (1 << 19)
723 # define CNTX_EMPTY_INT_ENABLE (1 << 20)
724 # define SCRATCH_INT_ENABLE (1 << 25)
725 # define TIME_STAMP_INT_ENABLE (1 << 26)
726 # define IB2_INT_ENABLE (1 << 29)
727 # define IB1_INT_ENABLE (1 << 30)
728 # define RB_INT_ENABLE (1 << 31)
729 #define CP_INT_STATUS 0xc128
730 # define SCRATCH_INT_STAT (1 << 25)
731 # define TIME_STAMP_INT_STAT (1 << 26)
732 # define IB2_INT_STAT (1 << 29)
733 # define IB1_INT_STAT (1 << 30)
734 # define RB_INT_STAT (1 << 31)
736 #define GRBM_INT_CNTL 0x8060
737 # define RDERR_INT_ENABLE (1 << 0)
738 # define WAIT_COUNT_TIMEOUT_INT_ENABLE (1 << 1)
739 # define GUI_IDLE_INT_ENABLE (1 << 19)
741 #define INTERRUPT_CNTL 0x5468
742 # define IH_DUMMY_RD_OVERRIDE (1 << 0)
743 # define IH_DUMMY_RD_EN (1 << 1)
744 # define IH_REQ_NONSNOOP_EN (1 << 3)
745 # define GEN_IH_INT_EN (1 << 8)
746 #define INTERRUPT_CNTL2 0x546c
748 #define D1MODE_VBLANK_STATUS 0x6534
749 #define D2MODE_VBLANK_STATUS 0x6d34
750 # define DxMODE_VBLANK_OCCURRED (1 << 0)
751 # define DxMODE_VBLANK_ACK (1 << 4)
752 # define DxMODE_VBLANK_STAT (1 << 12)
753 # define DxMODE_VBLANK_INTERRUPT (1 << 16)
754 # define DxMODE_VBLANK_INTERRUPT_TYPE (1 << 17)
755 #define D1MODE_VLINE_STATUS 0x653c
756 #define D2MODE_VLINE_STATUS 0x6d3c
757 # define DxMODE_VLINE_OCCURRED (1 << 0)
758 # define DxMODE_VLINE_ACK (1 << 4)
759 # define DxMODE_VLINE_STAT (1 << 12)
760 # define DxMODE_VLINE_INTERRUPT (1 << 16)
761 # define DxMODE_VLINE_INTERRUPT_TYPE (1 << 17)
762 #define DxMODE_INT_MASK 0x6540
763 # define D1MODE_VBLANK_INT_MASK (1 << 0)
764 # define D1MODE_VLINE_INT_MASK (1 << 4)
765 # define D2MODE_VBLANK_INT_MASK (1 << 8)
766 # define D2MODE_VLINE_INT_MASK (1 << 12)
767 #define DCE3_DISP_INTERRUPT_STATUS 0x7ddc
768 # define DC_HPD1_INTERRUPT (1 << 18)
769 # define DC_HPD2_INTERRUPT (1 << 19)
770 #define DISP_INTERRUPT_STATUS 0x7edc
771 # define LB_D1_VLINE_INTERRUPT (1 << 2)
772 # define LB_D2_VLINE_INTERRUPT (1 << 3)
773 # define LB_D1_VBLANK_INTERRUPT (1 << 4)
774 # define LB_D2_VBLANK_INTERRUPT (1 << 5)
775 # define DACA_AUTODETECT_INTERRUPT (1 << 16)
776 # define DACB_AUTODETECT_INTERRUPT (1 << 17)
777 # define DC_HOT_PLUG_DETECT1_INTERRUPT (1 << 18)
778 # define DC_HOT_PLUG_DETECT2_INTERRUPT (1 << 19)
779 # define DC_I2C_SW_DONE_INTERRUPT (1 << 20)
780 # define DC_I2C_HW_DONE_INTERRUPT (1 << 21)
781 #define DISP_INTERRUPT_STATUS_CONTINUE 0x7ee8
782 #define DCE3_DISP_INTERRUPT_STATUS_CONTINUE 0x7de8
783 # define DC_HPD4_INTERRUPT (1 << 14)
784 # define DC_HPD4_RX_INTERRUPT (1 << 15)
785 # define DC_HPD3_INTERRUPT (1 << 28)
786 # define DC_HPD1_RX_INTERRUPT (1 << 29)
787 # define DC_HPD2_RX_INTERRUPT (1 << 30)
788 #define DCE3_DISP_INTERRUPT_STATUS_CONTINUE2 0x7dec
789 # define DC_HPD3_RX_INTERRUPT (1 << 0)
790 # define DIGA_DP_VID_STREAM_DISABLE_INTERRUPT (1 << 1)
791 # define DIGA_DP_STEER_FIFO_OVERFLOW_INTERRUPT (1 << 2)
792 # define DIGB_DP_VID_STREAM_DISABLE_INTERRUPT (1 << 3)
793 # define DIGB_DP_STEER_FIFO_OVERFLOW_INTERRUPT (1 << 4)
794 # define AUX1_SW_DONE_INTERRUPT (1 << 5)
795 # define AUX1_LS_DONE_INTERRUPT (1 << 6)
796 # define AUX2_SW_DONE_INTERRUPT (1 << 7)
797 # define AUX2_LS_DONE_INTERRUPT (1 << 8)
798 # define AUX3_SW_DONE_INTERRUPT (1 << 9)
799 # define AUX3_LS_DONE_INTERRUPT (1 << 10)
800 # define AUX4_SW_DONE_INTERRUPT (1 << 11)
801 # define AUX4_LS_DONE_INTERRUPT (1 << 12)
802 # define DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT (1 << 13)
803 # define DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT (1 << 14)
805 # define AUX5_SW_DONE_INTERRUPT (1 << 15)
806 # define AUX5_LS_DONE_INTERRUPT (1 << 16)
807 # define AUX6_SW_DONE_INTERRUPT (1 << 17)
808 # define AUX6_LS_DONE_INTERRUPT (1 << 18)
809 # define DC_HPD5_INTERRUPT (1 << 19)
810 # define DC_HPD5_RX_INTERRUPT (1 << 20)
811 # define DC_HPD6_INTERRUPT (1 << 21)
812 # define DC_HPD6_RX_INTERRUPT (1 << 22)
814 #define DACA_AUTO_DETECT_CONTROL 0x7828
815 #define DACB_AUTO_DETECT_CONTROL 0x7a28
816 #define DCE3_DACA_AUTO_DETECT_CONTROL 0x7028
817 #define DCE3_DACB_AUTO_DETECT_CONTROL 0x7128
818 # define DACx_AUTODETECT_MODE(x) ((x) << 0)
819 # define DACx_AUTODETECT_MODE_NONE 0
820 # define DACx_AUTODETECT_MODE_CONNECT 1
821 # define DACx_AUTODETECT_MODE_DISCONNECT 2
822 # define DACx_AUTODETECT_FRAME_TIME_COUNTER(x) ((x) << 8)
823 /* bit 18 = R/C, 17 = G/Y, 16 = B/Comp */
824 # define DACx_AUTODETECT_CHECK_MASK(x) ((x) << 16)
826 #define DCE3_DACA_AUTODETECT_INT_CONTROL 0x7038
827 #define DCE3_DACB_AUTODETECT_INT_CONTROL 0x7138
828 #define DACA_AUTODETECT_INT_CONTROL 0x7838
829 #define DACB_AUTODETECT_INT_CONTROL 0x7a38
830 # define DACx_AUTODETECT_ACK (1 << 0)
831 # define DACx_AUTODETECT_INT_ENABLE (1 << 16)
833 #define DC_HOT_PLUG_DETECT1_CONTROL 0x7d00
834 #define DC_HOT_PLUG_DETECT2_CONTROL 0x7d10
835 #define DC_HOT_PLUG_DETECT3_CONTROL 0x7d24
836 # define DC_HOT_PLUG_DETECTx_EN (1 << 0)
838 #define DC_HOT_PLUG_DETECT1_INT_STATUS 0x7d04
839 #define DC_HOT_PLUG_DETECT2_INT_STATUS 0x7d14
840 #define DC_HOT_PLUG_DETECT3_INT_STATUS 0x7d28
841 # define DC_HOT_PLUG_DETECTx_INT_STATUS (1 << 0)
842 # define DC_HOT_PLUG_DETECTx_SENSE (1 << 1)
845 #define DC_HPD1_INT_STATUS 0x7d00
846 #define DC_HPD2_INT_STATUS 0x7d0c
847 #define DC_HPD3_INT_STATUS 0x7d18
848 #define DC_HPD4_INT_STATUS 0x7d24
850 #define DC_HPD5_INT_STATUS 0x7dc0
851 #define DC_HPD6_INT_STATUS 0x7df4
852 # define DC_HPDx_INT_STATUS (1 << 0)
853 # define DC_HPDx_SENSE (1 << 1)
854 # define DC_HPDx_RX_INT_STATUS (1 << 8)
856 #define DC_HOT_PLUG_DETECT1_INT_CONTROL 0x7d08
857 #define DC_HOT_PLUG_DETECT2_INT_CONTROL 0x7d18
858 #define DC_HOT_PLUG_DETECT3_INT_CONTROL 0x7d2c
859 # define DC_HOT_PLUG_DETECTx_INT_ACK (1 << 0)
860 # define DC_HOT_PLUG_DETECTx_INT_POLARITY (1 << 8)
861 # define DC_HOT_PLUG_DETECTx_INT_EN (1 << 16)
863 #define DC_HPD1_INT_CONTROL 0x7d04
864 #define DC_HPD2_INT_CONTROL 0x7d10
865 #define DC_HPD3_INT_CONTROL 0x7d1c
866 #define DC_HPD4_INT_CONTROL 0x7d28
868 #define DC_HPD5_INT_CONTROL 0x7dc4
869 #define DC_HPD6_INT_CONTROL 0x7df8
870 # define DC_HPDx_INT_ACK (1 << 0)
871 # define DC_HPDx_INT_POLARITY (1 << 8)
872 # define DC_HPDx_INT_EN (1 << 16)
873 # define DC_HPDx_RX_INT_ACK (1 << 20)
874 # define DC_HPDx_RX_INT_EN (1 << 24)
877 #define DC_HPD1_CONTROL 0x7d08
878 #define DC_HPD2_CONTROL 0x7d14
879 #define DC_HPD3_CONTROL 0x7d20
880 #define DC_HPD4_CONTROL 0x7d2c
882 #define DC_HPD5_CONTROL 0x7dc8
883 #define DC_HPD6_CONTROL 0x7dfc
884 # define DC_HPDx_CONNECTION_TIMER(x) ((x) << 0)
885 # define DC_HPDx_RX_INT_TIMER(x) ((x) << 16)
887 # define DC_HPDx_EN (1 << 28)
889 #define D1GRPH_INTERRUPT_STATUS 0x6158
890 #define D2GRPH_INTERRUPT_STATUS 0x6958
891 # define DxGRPH_PFLIP_INT_OCCURRED (1 << 0)
892 # define DxGRPH_PFLIP_INT_CLEAR (1 << 8)
893 #define D1GRPH_INTERRUPT_CONTROL 0x615c
894 #define D2GRPH_INTERRUPT_CONTROL 0x695c
895 # define DxGRPH_PFLIP_INT_MASK (1 << 0)
896 # define DxGRPH_PFLIP_INT_TYPE (1 << 8)
898 /* PCIE link stuff */
899 #define PCIE_LC_TRAINING_CNTL 0xa1 /* PCIE_P */
900 # define LC_POINT_7_PLUS_EN (1 << 6)
901 #define PCIE_LC_LINK_WIDTH_CNTL 0xa2 /* PCIE_P */
902 # define LC_LINK_WIDTH_SHIFT 0
903 # define LC_LINK_WIDTH_MASK 0x7
904 # define LC_LINK_WIDTH_X0 0
905 # define LC_LINK_WIDTH_X1 1
906 # define LC_LINK_WIDTH_X2 2
907 # define LC_LINK_WIDTH_X4 3
908 # define LC_LINK_WIDTH_X8 4
909 # define LC_LINK_WIDTH_X16 6
910 # define LC_LINK_WIDTH_RD_SHIFT 4
911 # define LC_LINK_WIDTH_RD_MASK 0x70
912 # define LC_RECONFIG_ARC_MISSING_ESCAPE (1 << 7)
913 # define LC_RECONFIG_NOW (1 << 8)
914 # define LC_RENEGOTIATION_SUPPORT (1 << 9)
915 # define LC_RENEGOTIATE_EN (1 << 10)
916 # define LC_SHORT_RECONFIG_EN (1 << 11)
917 # define LC_UPCONFIGURE_SUPPORT (1 << 12)
918 # define LC_UPCONFIGURE_DIS (1 << 13)
919 #define PCIE_LC_SPEED_CNTL 0xa4 /* PCIE_P */
920 # define LC_GEN2_EN_STRAP (1 << 0)
921 # define LC_TARGET_LINK_SPEED_OVERRIDE_EN (1 << 1)
922 # define LC_FORCE_EN_HW_SPEED_CHANGE (1 << 5)
923 # define LC_FORCE_DIS_HW_SPEED_CHANGE (1 << 6)
924 # define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK (0x3 << 8)
925 # define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT 3
926 # define LC_CURRENT_DATA_RATE (1 << 11)
927 # define LC_VOLTAGE_TIMER_SEL_MASK (0xf << 14)
928 # define LC_CLR_FAILED_SPD_CHANGE_CNT (1 << 21)
929 # define LC_OTHER_SIDE_EVER_SENT_GEN2 (1 << 23)
930 # define LC_OTHER_SIDE_SUPPORTS_GEN2 (1 << 24)
931 #define MM_CFGREGS_CNTL 0x544c
932 # define MM_WR_TO_CFG_EN (1 << 3)
933 #define LINK_CNTL2 0x88 /* F0 */
934 # define TARGET_LINK_SPEED_MASK (0xf << 0)
935 # define SELECTABLE_DEEMPHASIS (1 << 6)
938 #define AZ_HOT_PLUG_CONTROL 0x7300
939 # define AZ_FORCE_CODEC_WAKE (1 << 0)
940 # define JACK_DETECTION_ENABLE (1 << 4)
941 # define UNSOLICITED_RESPONSE_ENABLE (1 << 8)
942 # define CODEC_HOT_PLUG_ENABLE (1 << 12)
943 # define AUDIO_ENABLED (1 << 31)
945 # define PIN0_JACK_DETECTION_ENABLE (1 << 4)
946 # define PIN1_JACK_DETECTION_ENABLE (1 << 5)
947 # define PIN2_JACK_DETECTION_ENABLE (1 << 6)
948 # define PIN3_JACK_DETECTION_ENABLE (1 << 7)
949 # define PIN0_AUDIO_ENABLED (1 << 24)
950 # define PIN1_AUDIO_ENABLED (1 << 25)
951 # define PIN2_AUDIO_ENABLED (1 << 26)
952 # define PIN3_AUDIO_ENABLED (1 << 27)
954 /* Audio clocks DCE 2.0/3.0 */
955 #define AUDIO_DTO 0x7340
956 # define AUDIO_DTO_PHASE(x) (((x) & 0xffff) << 0)
957 # define AUDIO_DTO_MODULE(x) (((x) & 0xffff) << 16)
959 /* Audio clocks DCE 3.2 */
960 #define DCCG_AUDIO_DTO0_PHASE 0x0514
961 #define DCCG_AUDIO_DTO0_MODULE 0x0518
962 #define DCCG_AUDIO_DTO0_LOAD 0x051c
963 # define DTO_LOAD (1 << 31)
964 #define DCCG_AUDIO_DTO0_CNTL 0x0520
965 # define DCCG_AUDIO_DTO_WALLCLOCK_RATIO(x) (((x) & 7) << 0)
966 # define DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK 7
967 # define DCCG_AUDIO_DTO_WALLCLOCK_RATIO_SHIFT 0
969 #define DCCG_AUDIO_DTO1_PHASE 0x0524
970 #define DCCG_AUDIO_DTO1_MODULE 0x0528
971 #define DCCG_AUDIO_DTO1_LOAD 0x052c
972 #define DCCG_AUDIO_DTO1_CNTL 0x0530
974 #define DCCG_AUDIO_DTO_SELECT 0x0534
977 #define TMDSA_CNTL 0x7880
978 # define TMDSA_HDMI_EN (1 << 2)
979 #define LVTMA_CNTL 0x7a80
980 # define LVTMA_HDMI_EN (1 << 2)
981 #define DDIA_CNTL 0x7200
982 # define DDIA_HDMI_EN (1 << 2)
983 #define DIG0_CNTL 0x75a0
984 # define DIG_MODE(x) (((x) & 7) << 8)
985 # define DIG_MODE_DP 0
986 # define DIG_MODE_LVDS 1
987 # define DIG_MODE_TMDS_DVI 2
988 # define DIG_MODE_TMDS_HDMI 3
989 # define DIG_MODE_SDVO 4
990 #define DIG1_CNTL 0x79a0
992 #define AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER 0x71bc
993 #define SPEAKER_ALLOCATION(x) (((x) & 0x7f) << 0)
994 #define SPEAKER_ALLOCATION_MASK (0x7f << 0)
995 #define SPEAKER_ALLOCATION_SHIFT 0
996 #define HDMI_CONNECTION (1 << 16)
997 #define DP_CONNECTION (1 << 17)
999 #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR0 0x71c8 /* LPCM */
1000 #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR1 0x71cc /* AC3 */
1001 #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR2 0x71d0 /* MPEG1 */
1002 #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR3 0x71d4 /* MP3 */
1003 #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR4 0x71d8 /* MPEG2 */
1004 #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR5 0x71dc /* AAC */
1005 #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR6 0x71e0 /* DTS */
1006 #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR7 0x71e4 /* ATRAC */
1007 #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR8 0x71e8 /* one bit audio - leave at 0 (default) */
1008 #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR9 0x71ec /* Dolby Digital */
1009 #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR10 0x71f0 /* DTS-HD */
1010 #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR11 0x71f4 /* MAT-MLP */
1011 #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR12 0x71f8 /* DTS */
1012 #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR13 0x71fc /* WMA Pro */
1013 # define MAX_CHANNELS(x) (((x) & 0x7) << 0)
1014 /* max channels minus one. 7 = 8 channels */
1015 # define SUPPORTED_FREQUENCIES(x) (((x) & 0xff) << 8)
1016 # define DESCRIPTOR_BYTE_2(x) (((x) & 0xff) << 16)
1017 # define SUPPORTED_FREQUENCIES_STEREO(x) (((x) & 0xff) << 24) /* LPCM only */
1018 /* SUPPORTED_FREQUENCIES, SUPPORTED_FREQUENCIES_STEREO
1028 /* rs6xx/rs740 and r6xx share the same HDMI blocks, however, rs6xx has only one
1029 * instance of the blocks while r6xx has 2. DCE 3.0 cards are slightly
1030 * different due to the new DIG blocks, but also have 2 instances.
1031 * DCE 3.0 HDMI blocks are part of each DIG encoder.
1034 /* rs6xx/rs740/r6xx/dce3 */
1035 #define HDMI0_CONTROL 0x7400
1036 /* rs6xx/rs740/r6xx */
1037 # define HDMI0_ENABLE (1 << 0)
1038 # define HDMI0_STREAM(x) (((x) & 3) << 2)
1039 # define HDMI0_STREAM_TMDSA 0
1040 # define HDMI0_STREAM_LVTMA 1
1041 # define HDMI0_STREAM_DVOA 2
1042 # define HDMI0_STREAM_DDIA 3
1043 /* rs6xx/r6xx/dce3 */
1044 # define HDMI0_ERROR_ACK (1 << 8)
1045 # define HDMI0_ERROR_MASK (1 << 9)
1046 #define HDMI0_STATUS 0x7404
1047 # define HDMI0_ACTIVE_AVMUTE (1 << 0)
1048 # define HDMI0_AUDIO_ENABLE (1 << 4)
1049 # define HDMI0_AZ_FORMAT_WTRIG (1 << 28)
1050 # define HDMI0_AZ_FORMAT_WTRIG_INT (1 << 29)
1051 #define HDMI0_AUDIO_PACKET_CONTROL 0x7408
1052 # define HDMI0_AUDIO_SAMPLE_SEND (1 << 0)
1053 # define HDMI0_AUDIO_DELAY_EN(x) (((x) & 3) << 4)
1054 # define HDMI0_AUDIO_DELAY_EN_MASK (3 << 4)
1055 # define HDMI0_AUDIO_SEND_MAX_PACKETS (1 << 8)
1056 # define HDMI0_AUDIO_TEST_EN (1 << 12)
1057 # define HDMI0_AUDIO_PACKETS_PER_LINE(x) (((x) & 0x1f) << 16)
1058 # define HDMI0_AUDIO_PACKETS_PER_LINE_MASK (0x1f << 16)
1059 # define HDMI0_AUDIO_CHANNEL_SWAP (1 << 24)
1060 # define HDMI0_60958_CS_UPDATE (1 << 26)
1061 # define HDMI0_AZ_FORMAT_WTRIG_MASK (1 << 28)
1062 # define HDMI0_AZ_FORMAT_WTRIG_ACK (1 << 29)
1063 #define HDMI0_AUDIO_CRC_CONTROL 0x740c
1064 # define HDMI0_AUDIO_CRC_EN (1 << 0)
1065 #define DCE3_HDMI0_ACR_PACKET_CONTROL 0x740c
1066 #define HDMI0_VBI_PACKET_CONTROL 0x7410
1067 # define HDMI0_NULL_SEND (1 << 0)
1068 # define HDMI0_GC_SEND (1 << 4)
1069 # define HDMI0_GC_CONT (1 << 5) /* 0 - once; 1 - every frame */
1070 #define HDMI0_INFOFRAME_CONTROL0 0x7414
1071 # define HDMI0_AVI_INFO_SEND (1 << 0)
1072 # define HDMI0_AVI_INFO_CONT (1 << 1)
1073 # define HDMI0_AUDIO_INFO_SEND (1 << 4)
1074 # define HDMI0_AUDIO_INFO_CONT (1 << 5)
1075 # define HDMI0_AUDIO_INFO_SOURCE (1 << 6) /* 0 - sound block; 1 - hdmi regs */
1076 # define HDMI0_AUDIO_INFO_UPDATE (1 << 7)
1077 # define HDMI0_MPEG_INFO_SEND (1 << 8)
1078 # define HDMI0_MPEG_INFO_CONT (1 << 9)
1079 # define HDMI0_MPEG_INFO_UPDATE (1 << 10)
1080 #define HDMI0_INFOFRAME_CONTROL1 0x7418
1081 # define HDMI0_AVI_INFO_LINE(x) (((x) & 0x3f) << 0)
1082 # define HDMI0_AVI_INFO_LINE_MASK (0x3f << 0)
1083 # define HDMI0_AUDIO_INFO_LINE(x) (((x) & 0x3f) << 8)
1084 # define HDMI0_AUDIO_INFO_LINE_MASK (0x3f << 8)
1085 # define HDMI0_MPEG_INFO_LINE(x) (((x) & 0x3f) << 16)
1086 #define HDMI0_GENERIC_PACKET_CONTROL 0x741c
1087 # define HDMI0_GENERIC0_SEND (1 << 0)
1088 # define HDMI0_GENERIC0_CONT (1 << 1)
1089 # define HDMI0_GENERIC0_UPDATE (1 << 2)
1090 # define HDMI0_GENERIC1_SEND (1 << 4)
1091 # define HDMI0_GENERIC1_CONT (1 << 5)
1092 # define HDMI0_GENERIC0_LINE(x) (((x) & 0x3f) << 16)
1093 # define HDMI0_GENERIC0_LINE_MASK (0x3f << 16)
1094 # define HDMI0_GENERIC1_LINE(x) (((x) & 0x3f) << 24)
1095 # define HDMI0_GENERIC1_LINE_MASK (0x3f << 24)
1096 #define HDMI0_GC 0x7428
1097 # define HDMI0_GC_AVMUTE (1 << 0)
1098 #define HDMI0_AVI_INFO0 0x7454
1099 # define HDMI0_AVI_INFO_CHECKSUM(x) (((x) & 0xff) << 0)
1100 # define HDMI0_AVI_INFO_S(x) (((x) & 3) << 8)
1101 # define HDMI0_AVI_INFO_B(x) (((x) & 3) << 10)
1102 # define HDMI0_AVI_INFO_A(x) (((x) & 1) << 12)
1103 # define HDMI0_AVI_INFO_Y(x) (((x) & 3) << 13)
1104 # define HDMI0_AVI_INFO_Y_RGB 0
1105 # define HDMI0_AVI_INFO_Y_YCBCR422 1
1106 # define HDMI0_AVI_INFO_Y_YCBCR444 2
1107 # define HDMI0_AVI_INFO_Y_A_B_S(x) (((x) & 0xff) << 8)
1108 # define HDMI0_AVI_INFO_R(x) (((x) & 0xf) << 16)
1109 # define HDMI0_AVI_INFO_M(x) (((x) & 0x3) << 20)
1110 # define HDMI0_AVI_INFO_C(x) (((x) & 0x3) << 22)
1111 # define HDMI0_AVI_INFO_C_M_R(x) (((x) & 0xff) << 16)
1112 # define HDMI0_AVI_INFO_SC(x) (((x) & 0x3) << 24)
1113 # define HDMI0_AVI_INFO_ITC_EC_Q_SC(x) (((x) & 0xff) << 24)
1114 #define HDMI0_AVI_INFO1 0x7458
1115 # define HDMI0_AVI_INFO_VIC(x) (((x) & 0x7f) << 0) /* don't use avi infoframe v1 */
1116 # define HDMI0_AVI_INFO_PR(x) (((x) & 0xf) << 8) /* don't use avi infoframe v1 */
1117 # define HDMI0_AVI_INFO_TOP(x) (((x) & 0xffff) << 16)
1118 #define HDMI0_AVI_INFO2 0x745c
1119 # define HDMI0_AVI_INFO_BOTTOM(x) (((x) & 0xffff) << 0)
1120 # define HDMI0_AVI_INFO_LEFT(x) (((x) & 0xffff) << 16)
1121 #define HDMI0_AVI_INFO3 0x7460
1122 # define HDMI0_AVI_INFO_RIGHT(x) (((x) & 0xffff) << 0)
1123 # define HDMI0_AVI_INFO_VERSION(x) (((x) & 3) << 24)
1124 #define HDMI0_MPEG_INFO0 0x7464
1125 # define HDMI0_MPEG_INFO_CHECKSUM(x) (((x) & 0xff) << 0)
1126 # define HDMI0_MPEG_INFO_MB0(x) (((x) & 0xff) << 8)
1127 # define HDMI0_MPEG_INFO_MB1(x) (((x) & 0xff) << 16)
1128 # define HDMI0_MPEG_INFO_MB2(x) (((x) & 0xff) << 24)
1129 #define HDMI0_MPEG_INFO1 0x7468
1130 # define HDMI0_MPEG_INFO_MB3(x) (((x) & 0xff) << 0)
1131 # define HDMI0_MPEG_INFO_MF(x) (((x) & 3) << 8)
1132 # define HDMI0_MPEG_INFO_FR(x) (((x) & 1) << 12)
1133 #define HDMI0_GENERIC0_HDR 0x746c
1134 #define HDMI0_GENERIC0_0 0x7470
1135 #define HDMI0_GENERIC0_1 0x7474
1136 #define HDMI0_GENERIC0_2 0x7478
1137 #define HDMI0_GENERIC0_3 0x747c
1138 #define HDMI0_GENERIC0_4 0x7480
1139 #define HDMI0_GENERIC0_5 0x7484
1140 #define HDMI0_GENERIC0_6 0x7488
1141 #define HDMI0_GENERIC1_HDR 0x748c
1142 #define HDMI0_GENERIC1_0 0x7490
1143 #define HDMI0_GENERIC1_1 0x7494
1144 #define HDMI0_GENERIC1_2 0x7498
1145 #define HDMI0_GENERIC1_3 0x749c
1146 #define HDMI0_GENERIC1_4 0x74a0
1147 #define HDMI0_GENERIC1_5 0x74a4
1148 #define HDMI0_GENERIC1_6 0x74a8
1149 #define HDMI0_ACR_32_0 0x74ac
1150 # define HDMI0_ACR_CTS_32(x) (((x) & 0xfffff) << 12)
1151 # define HDMI0_ACR_CTS_32_MASK (0xfffff << 12)
1152 #define HDMI0_ACR_32_1 0x74b0
1153 # define HDMI0_ACR_N_32(x) (((x) & 0xfffff) << 0)
1154 # define HDMI0_ACR_N_32_MASK (0xfffff << 0)
1155 #define HDMI0_ACR_44_0 0x74b4
1156 # define HDMI0_ACR_CTS_44(x) (((x) & 0xfffff) << 12)
1157 # define HDMI0_ACR_CTS_44_MASK (0xfffff << 12)
1158 #define HDMI0_ACR_44_1 0x74b8
1159 # define HDMI0_ACR_N_44(x) (((x) & 0xfffff) << 0)
1160 # define HDMI0_ACR_N_44_MASK (0xfffff << 0)
1161 #define HDMI0_ACR_48_0 0x74bc
1162 # define HDMI0_ACR_CTS_48(x) (((x) & 0xfffff) << 12)
1163 # define HDMI0_ACR_CTS_48_MASK (0xfffff << 12)
1164 #define HDMI0_ACR_48_1 0x74c0
1165 # define HDMI0_ACR_N_48(x) (((x) & 0xfffff) << 0)
1166 # define HDMI0_ACR_N_48_MASK (0xfffff << 0)
1167 #define HDMI0_ACR_STATUS_0 0x74c4
1168 #define HDMI0_ACR_STATUS_1 0x74c8
1169 #define HDMI0_AUDIO_INFO0 0x74cc
1170 # define HDMI0_AUDIO_INFO_CHECKSUM(x) (((x) & 0xff) << 0)
1171 # define HDMI0_AUDIO_INFO_CC(x) (((x) & 7) << 8)
1172 #define HDMI0_AUDIO_INFO1 0x74d0
1173 # define HDMI0_AUDIO_INFO_CA(x) (((x) & 0xff) << 0)
1174 # define HDMI0_AUDIO_INFO_LSV(x) (((x) & 0xf) << 11)
1175 # define HDMI0_AUDIO_INFO_DM_INH(x) (((x) & 1) << 15)
1176 # define HDMI0_AUDIO_INFO_DM_INH_LSV(x) (((x) & 0xff) << 8)
1177 #define HDMI0_60958_0 0x74d4
1178 # define HDMI0_60958_CS_A(x) (((x) & 1) << 0)
1179 # define HDMI0_60958_CS_B(x) (((x) & 1) << 1)
1180 # define HDMI0_60958_CS_C(x) (((x) & 1) << 2)
1181 # define HDMI0_60958_CS_D(x) (((x) & 3) << 3)
1182 # define HDMI0_60958_CS_MODE(x) (((x) & 3) << 6)
1183 # define HDMI0_60958_CS_CATEGORY_CODE(x) (((x) & 0xff) << 8)
1184 # define HDMI0_60958_CS_SOURCE_NUMBER(x) (((x) & 0xf) << 16)
1185 # define HDMI0_60958_CS_CHANNEL_NUMBER_L(x) (((x) & 0xf) << 20)
1186 # define HDMI0_60958_CS_CHANNEL_NUMBER_L_MASK (0xf << 20)
1187 # define HDMI0_60958_CS_SAMPLING_FREQUENCY(x) (((x) & 0xf) << 24)
1188 # define HDMI0_60958_CS_CLOCK_ACCURACY(x) (((x) & 3) << 28)
1189 # define HDMI0_60958_CS_CLOCK_ACCURACY_MASK (3 << 28)
1190 #define HDMI0_60958_1 0x74d8
1191 # define HDMI0_60958_CS_WORD_LENGTH(x) (((x) & 0xf) << 0)
1192 # define HDMI0_60958_CS_ORIGINAL_SAMPLING_FREQUENCY(x) (((x) & 0xf) << 4)
1193 # define HDMI0_60958_CS_VALID_L(x) (((x) & 1) << 16)
1194 # define HDMI0_60958_CS_VALID_R(x) (((x) & 1) << 18)
1195 # define HDMI0_60958_CS_CHANNEL_NUMBER_R(x) (((x) & 0xf) << 20)
1196 # define HDMI0_60958_CS_CHANNEL_NUMBER_R_MASK (0xf << 20)
1197 #define HDMI0_ACR_PACKET_CONTROL 0x74dc
1198 # define HDMI0_ACR_SEND (1 << 0)
1199 # define HDMI0_ACR_CONT (1 << 1)
1200 # define HDMI0_ACR_SELECT(x) (((x) & 3) << 4)
1201 # define HDMI0_ACR_HW 0
1202 # define HDMI0_ACR_32 1
1203 # define HDMI0_ACR_44 2
1204 # define HDMI0_ACR_48 3
1205 # define HDMI0_ACR_SOURCE (1 << 8) /* 0 - hw; 1 - cts value */
1206 # define HDMI0_ACR_AUTO_SEND (1 << 12)
1207 #define DCE3_HDMI0_AUDIO_CRC_CONTROL 0x74dc
1208 #define HDMI0_RAMP_CONTROL0 0x74e0
1209 # define HDMI0_RAMP_MAX_COUNT(x) (((x) & 0xffffff) << 0)
1210 #define HDMI0_RAMP_CONTROL1 0x74e4
1211 # define HDMI0_RAMP_MIN_COUNT(x) (((x) & 0xffffff) << 0)
1212 #define HDMI0_RAMP_CONTROL2 0x74e8
1213 # define HDMI0_RAMP_INC_COUNT(x) (((x) & 0xffffff) << 0)
1214 #define HDMI0_RAMP_CONTROL3 0x74ec
1215 # define HDMI0_RAMP_DEC_COUNT(x) (((x) & 0xffffff) << 0)
1216 /* HDMI0_60958_2 is r7xx only */
1217 #define HDMI0_60958_2 0x74f0
1218 # define HDMI0_60958_CS_CHANNEL_NUMBER_2(x) (((x) & 0xf) << 0)
1219 # define HDMI0_60958_CS_CHANNEL_NUMBER_3(x) (((x) & 0xf) << 4)
1220 # define HDMI0_60958_CS_CHANNEL_NUMBER_4(x) (((x) & 0xf) << 8)
1221 # define HDMI0_60958_CS_CHANNEL_NUMBER_5(x) (((x) & 0xf) << 12)
1222 # define HDMI0_60958_CS_CHANNEL_NUMBER_6(x) (((x) & 0xf) << 16)
1223 # define HDMI0_60958_CS_CHANNEL_NUMBER_7(x) (((x) & 0xf) << 20)
1224 /* r6xx only; second instance starts at 0x7700 */
1225 #define HDMI1_CONTROL 0x7700
1226 #define HDMI1_STATUS 0x7704
1227 #define HDMI1_AUDIO_PACKET_CONTROL 0x7708
1228 /* DCE3; second instance starts at 0x7800 NOT 0x7700 */
1229 #define DCE3_HDMI1_CONTROL 0x7800
1230 #define DCE3_HDMI1_STATUS 0x7804
1231 #define DCE3_HDMI1_AUDIO_PACKET_CONTROL 0x7808
1232 /* DCE3.2 (for interrupts) */
1233 #define AFMT_STATUS 0x7600
1234 # define AFMT_AUDIO_ENABLE (1 << 4)
1235 # define AFMT_AZ_FORMAT_WTRIG (1 << 28)
1236 # define AFMT_AZ_FORMAT_WTRIG_INT (1 << 29)
1237 # define AFMT_AZ_AUDIO_ENABLE_CHG (1 << 30)
1238 #define AFMT_AUDIO_PACKET_CONTROL 0x7604
1239 # define AFMT_AUDIO_SAMPLE_SEND (1 << 0)
1240 # define AFMT_AUDIO_TEST_EN (1 << 12)
1241 # define AFMT_AUDIO_CHANNEL_SWAP (1 << 24)
1242 # define AFMT_60958_CS_UPDATE (1 << 26)
1243 # define AFMT_AZ_AUDIO_ENABLE_CHG_MASK (1 << 27)
1244 # define AFMT_AZ_FORMAT_WTRIG_MASK (1 << 28)
1245 # define AFMT_AZ_FORMAT_WTRIG_ACK (1 << 29)
1246 # define AFMT_AZ_AUDIO_ENABLE_CHG_ACK (1 << 30)
1248 /* DCE3 FMT blocks */
1249 #define FMT_CONTROL 0x6700
1250 # define FMT_PIXEL_ENCODING (1 << 16)
1251 /* 0 = RGB 4:4:4 or YCbCr 4:4:4, 1 = YCbCr 4:2:2 */
1252 #define FMT_BIT_DEPTH_CONTROL 0x6710
1253 # define FMT_TRUNCATE_EN (1 << 0)
1254 # define FMT_TRUNCATE_DEPTH (1 << 4)
1255 # define FMT_SPATIAL_DITHER_EN (1 << 8)
1256 # define FMT_SPATIAL_DITHER_MODE(x) ((x) << 9)
1257 # define FMT_SPATIAL_DITHER_DEPTH (1 << 12)
1258 # define FMT_FRAME_RANDOM_ENABLE (1 << 13)
1259 # define FMT_RGB_RANDOM_ENABLE (1 << 14)
1260 # define FMT_HIGHPASS_RANDOM_ENABLE (1 << 15)
1261 # define FMT_TEMPORAL_DITHER_EN (1 << 16)
1262 # define FMT_TEMPORAL_DITHER_DEPTH (1 << 20)
1263 # define FMT_TEMPORAL_DITHER_OFFSET(x) ((x) << 21)
1264 # define FMT_TEMPORAL_LEVEL (1 << 24)
1265 # define FMT_TEMPORAL_DITHER_RESET (1 << 25)
1266 # define FMT_25FRC_SEL(x) ((x) << 26)
1267 # define FMT_50FRC_SEL(x) ((x) << 28)
1268 # define FMT_75FRC_SEL(x) ((x) << 30)
1269 #define FMT_CLAMP_CONTROL 0x672c
1270 # define FMT_CLAMP_DATA_EN (1 << 0)
1271 # define FMT_CLAMP_COLOR_FORMAT(x) ((x) << 16)
1272 # define FMT_CLAMP_6BPC 0
1273 # define FMT_CLAMP_8BPC 1
1274 # define FMT_CLAMP_10BPC 2
1276 /* Power management */
1277 #define CG_SPLL_FUNC_CNTL 0x600
1278 # define SPLL_RESET (1 << 0)
1279 # define SPLL_SLEEP (1 << 1)
1280 # define SPLL_REF_DIV(x) ((x) << 2)
1281 # define SPLL_REF_DIV_MASK (7 << 2)
1282 # define SPLL_FB_DIV(x) ((x) << 5)
1283 # define SPLL_FB_DIV_MASK (0xff << 5)
1284 # define SPLL_PULSEEN (1 << 13)
1285 # define SPLL_PULSENUM(x) ((x) << 14)
1286 # define SPLL_PULSENUM_MASK (3 << 14)
1287 # define SPLL_SW_HILEN(x) ((x) << 16)
1288 # define SPLL_SW_HILEN_MASK (0xf << 16)
1289 # define SPLL_SW_LOLEN(x) ((x) << 20)
1290 # define SPLL_SW_LOLEN_MASK (0xf << 20)
1291 # define SPLL_DIVEN (1 << 24)
1292 # define SPLL_BYPASS_EN (1 << 25)
1293 # define SPLL_CHG_STATUS (1 << 29)
1294 # define SPLL_CTLREQ (1 << 30)
1295 # define SPLL_CTLACK (1 << 31)
1297 #define GENERAL_PWRMGT 0x618
1298 # define GLOBAL_PWRMGT_EN (1 << 0)
1299 # define STATIC_PM_EN (1 << 1)
1300 # define MOBILE_SU (1 << 2)
1301 # define THERMAL_PROTECTION_DIS (1 << 3)
1302 # define THERMAL_PROTECTION_TYPE (1 << 4)
1303 # define ENABLE_GEN2PCIE (1 << 5)
1304 # define SW_GPIO_INDEX(x) ((x) << 6)
1305 # define SW_GPIO_INDEX_MASK (3 << 6)
1306 # define LOW_VOLT_D2_ACPI (1 << 8)
1307 # define LOW_VOLT_D3_ACPI (1 << 9)
1308 # define VOLT_PWRMGT_EN (1 << 10)
1309 #define CG_TPC 0x61c
1310 # define TPCC(x) ((x) << 0)
1311 # define TPCC_MASK (0x7fffff << 0)
1312 # define TPU(x) ((x) << 23)
1313 # define TPU_MASK (0x1f << 23)
1314 #define SCLK_PWRMGT_CNTL 0x620
1315 # define SCLK_PWRMGT_OFF (1 << 0)
1316 # define SCLK_TURNOFF (1 << 1)
1317 # define SPLL_TURNOFF (1 << 2)
1318 # define SU_SCLK_USE_BCLK (1 << 3)
1319 # define DYNAMIC_GFX_ISLAND_PWR_DOWN (1 << 4)
1320 # define DYNAMIC_GFX_ISLAND_PWR_LP (1 << 5)
1321 # define CLK_TURN_ON_STAGGER (1 << 6)
1322 # define CLK_TURN_OFF_STAGGER (1 << 7)
1323 # define FIR_FORCE_TREND_SEL (1 << 8)
1324 # define FIR_TREND_MODE (1 << 9)
1325 # define DYN_GFX_CLK_OFF_EN (1 << 10)
1326 # define VDDC3D_TURNOFF_D1 (1 << 11)
1327 # define VDDC3D_TURNOFF_D2 (1 << 12)
1328 # define VDDC3D_TURNOFF_D3 (1 << 13)
1329 # define SPLL_TURNOFF_D2 (1 << 14)
1330 # define SCLK_LOW_D1 (1 << 15)
1331 # define DYN_GFX_CLK_OFF_MC_EN (1 << 16)
1332 #define MCLK_PWRMGT_CNTL 0x624
1333 # define MPLL_PWRMGT_OFF (1 << 0)
1334 # define YCLK_TURNOFF (1 << 1)
1335 # define MPLL_TURNOFF (1 << 2)
1336 # define SU_MCLK_USE_BCLK (1 << 3)
1337 # define DLL_READY (1 << 4)
1338 # define MC_BUSY (1 << 5)
1339 # define MC_INT_CNTL (1 << 7)
1340 # define MRDCKA_SLEEP (1 << 8)
1341 # define MRDCKB_SLEEP (1 << 9)
1342 # define MRDCKC_SLEEP (1 << 10)
1343 # define MRDCKD_SLEEP (1 << 11)
1344 # define MRDCKE_SLEEP (1 << 12)
1345 # define MRDCKF_SLEEP (1 << 13)
1346 # define MRDCKG_SLEEP (1 << 14)
1347 # define MRDCKH_SLEEP (1 << 15)
1348 # define MRDCKA_RESET (1 << 16)
1349 # define MRDCKB_RESET (1 << 17)
1350 # define MRDCKC_RESET (1 << 18)
1351 # define MRDCKD_RESET (1 << 19)
1352 # define MRDCKE_RESET (1 << 20)
1353 # define MRDCKF_RESET (1 << 21)
1354 # define MRDCKG_RESET (1 << 22)
1355 # define MRDCKH_RESET (1 << 23)
1356 # define DLL_READY_READ (1 << 24)
1357 # define USE_DISPLAY_GAP (1 << 25)
1358 # define USE_DISPLAY_URGENT_NORMAL (1 << 26)
1359 # define USE_DISPLAY_GAP_CTXSW (1 << 27)
1360 # define MPLL_TURNOFF_D2 (1 << 28)
1361 # define USE_DISPLAY_URGENT_CTXSW (1 << 29)
1363 #define MPLL_TIME 0x634
1364 # define MPLL_LOCK_TIME(x) ((x) << 0)
1365 # define MPLL_LOCK_TIME_MASK (0xffff << 0)
1366 # define MPLL_RESET_TIME(x) ((x) << 16)
1367 # define MPLL_RESET_TIME_MASK (0xffff << 16)
1369 #define SCLK_FREQ_SETTING_STEP_0_PART1 0x648
1370 # define STEP_0_SPLL_POST_DIV(x) ((x) << 0)
1371 # define STEP_0_SPLL_POST_DIV_MASK (0xff << 0)
1372 # define STEP_0_SPLL_FB_DIV(x) ((x) << 8)
1373 # define STEP_0_SPLL_FB_DIV_MASK (0xff << 8)
1374 # define STEP_0_SPLL_REF_DIV(x) ((x) << 16)
1375 # define STEP_0_SPLL_REF_DIV_MASK (7 << 16)
1376 # define STEP_0_SPLL_STEP_TIME(x) ((x) << 19)
1377 # define STEP_0_SPLL_STEP_TIME_MASK (0x1fff << 19)
1378 #define SCLK_FREQ_SETTING_STEP_0_PART2 0x64c
1379 # define STEP_0_PULSE_HIGH_CNT(x) ((x) << 0)
1380 # define STEP_0_PULSE_HIGH_CNT_MASK (0x1ff << 0)
1381 # define STEP_0_POST_DIV_EN (1 << 9)
1382 # define STEP_0_SPLL_STEP_ENABLE (1 << 30)
1383 # define STEP_0_SPLL_ENTRY_VALID (1 << 31)
1385 #define VID_RT 0x6f8
1386 # define VID_CRT(x) ((x) << 0)
1387 # define VID_CRT_MASK (0x1fff << 0)
1388 # define VID_CRTU(x) ((x) << 13)
1389 # define VID_CRTU_MASK (7 << 13)
1390 # define SSTU(x) ((x) << 16)
1391 # define SSTU_MASK (7 << 16)
1392 #define CTXSW_PROFILE_INDEX 0x6fc
1393 # define CTXSW_FREQ_VIDS_CFG_INDEX(x) ((x) << 0)
1394 # define CTXSW_FREQ_VIDS_CFG_INDEX_MASK (3 << 0)
1395 # define CTXSW_FREQ_VIDS_CFG_INDEX_SHIFT 0
1396 # define CTXSW_FREQ_MCLK_CFG_INDEX(x) ((x) << 2)
1397 # define CTXSW_FREQ_MCLK_CFG_INDEX_MASK (3 << 2)
1398 # define CTXSW_FREQ_MCLK_CFG_INDEX_SHIFT 2
1399 # define CTXSW_FREQ_SCLK_CFG_INDEX(x) ((x) << 4)
1400 # define CTXSW_FREQ_SCLK_CFG_INDEX_MASK (0x1f << 4)
1401 # define CTXSW_FREQ_SCLK_CFG_INDEX_SHIFT 4
1402 # define CTXSW_FREQ_STATE_SPLL_RESET_EN (1 << 9)
1403 # define CTXSW_FREQ_STATE_ENABLE (1 << 10)
1404 # define CTXSW_FREQ_DISPLAY_WATERMARK (1 << 11)
1405 # define CTXSW_FREQ_GEN2PCIE_VOLT (1 << 12)
1407 #define TARGET_AND_CURRENT_PROFILE_INDEX 0x70c
1408 # define TARGET_PROFILE_INDEX_MASK (3 << 0)
1409 # define TARGET_PROFILE_INDEX_SHIFT 0
1410 # define CURRENT_PROFILE_INDEX_MASK (3 << 2)
1411 # define CURRENT_PROFILE_INDEX_SHIFT 2
1412 # define DYN_PWR_ENTER_INDEX(x) ((x) << 4)
1413 # define DYN_PWR_ENTER_INDEX_MASK (3 << 4)
1414 # define DYN_PWR_ENTER_INDEX_SHIFT 4
1415 # define CURR_MCLK_INDEX_MASK (3 << 6)
1416 # define CURR_MCLK_INDEX_SHIFT 6
1417 # define CURR_SCLK_INDEX_MASK (0x1f << 8)
1418 # define CURR_SCLK_INDEX_SHIFT 8
1419 # define CURR_VID_INDEX_MASK (3 << 13)
1420 # define CURR_VID_INDEX_SHIFT 13
1422 #define LOWER_GPIO_ENABLE 0x710
1423 #define UPPER_GPIO_ENABLE 0x714
1424 #define CTXSW_VID_LOWER_GPIO_CNTL 0x718
1426 #define VID_UPPER_GPIO_CNTL 0x740
1427 #define CG_CTX_CGTT3D_R 0x744
1428 # define PHC(x) ((x) << 0)
1429 # define PHC_MASK (0x1ff << 0)
1430 # define SDC(x) ((x) << 9)
1431 # define SDC_MASK (0x3fff << 9)
1432 #define CG_VDDC3D_OOR 0x748
1433 # define SU(x) ((x) << 23)
1434 # define SU_MASK (0xf << 23)
1435 #define CG_FTV 0x74c
1436 #define CG_FFCT_0 0x750
1437 # define UTC_0(x) ((x) << 0)
1438 # define UTC_0_MASK (0x3ff << 0)
1439 # define DTC_0(x) ((x) << 10)
1440 # define DTC_0_MASK (0x3ff << 10)
1442 #define CG_BSP 0x78c
1443 # define BSP(x) ((x) << 0)
1444 # define BSP_MASK (0xffff << 0)
1445 # define BSU(x) ((x) << 16)
1446 # define BSU_MASK (0xf << 16)
1448 # define FLS(x) ((x) << 0)
1449 # define FLS_MASK (0xffff << 0)
1450 # define FMS(x) ((x) << 16)
1451 # define FMS_MASK (0xffff << 16)
1453 # define FHS(x) ((x) << 0)
1454 # define FHS_MASK (0xffff << 0)
1455 #define CG_GIT 0x798
1456 # define CG_GICST(x) ((x) << 0)
1457 # define CG_GICST_MASK (0xffff << 0)
1458 # define CG_GIPOT(x) ((x) << 16)
1459 # define CG_GIPOT_MASK (0xffff << 16)
1461 #define CG_SSP 0x7a8
1462 # define CG_SST(x) ((x) << 0)
1463 # define CG_SST_MASK (0xffff << 0)
1464 # define CG_SSTU(x) ((x) << 16)
1465 # define CG_SSTU_MASK (0xf << 16)
1467 #define CG_RLC_REQ_AND_RSP 0x7c4
1468 # define RLC_CG_REQ_TYPE_MASK 0xf
1469 # define RLC_CG_REQ_TYPE_SHIFT 0
1470 # define CG_RLC_RSP_TYPE_MASK 0xf0
1471 # define CG_RLC_RSP_TYPE_SHIFT 4
1473 #define CG_FC_T 0x7cc
1474 # define FC_T(x) ((x) << 0)
1475 # define FC_T_MASK (0xffff << 0)
1476 # define FC_TU(x) ((x) << 16)
1477 # define FC_TU_MASK (0x1f << 16)
1479 #define GPIOPAD_MASK 0x1798
1480 #define GPIOPAD_A 0x179c
1481 #define GPIOPAD_EN 0x17a0
1483 #define GRBM_PWR_CNTL 0x800c
1484 # define REQ_TYPE_MASK 0xf
1485 # define REQ_TYPE_SHIFT 0
1486 # define RSP_TYPE_MASK 0xf0
1487 # define RSP_TYPE_SHIFT 4
1492 #define UVD_SEMA_ADDR_LOW 0xef00
1493 #define UVD_SEMA_ADDR_HIGH 0xef04
1494 #define UVD_SEMA_CMD 0xef08
1496 #define UVD_GPCOM_VCPU_CMD 0xef0c
1497 #define UVD_GPCOM_VCPU_DATA0 0xef10
1498 #define UVD_GPCOM_VCPU_DATA1 0xef14
1499 #define UVD_ENGINE_CNTL 0xef18
1501 #define UVD_SEMA_CNTL 0xf400
1502 #define UVD_RB_ARB_CTRL 0xf480
1504 #define UVD_LMI_EXT40_ADDR 0xf498
1505 #define UVD_CGC_GATE 0xf4a8
1506 #define UVD_LMI_CTRL2 0xf4f4
1507 #define UVD_MASTINT_EN 0xf500
1508 #define UVD_FW_START 0xf51C
1509 #define UVD_LMI_ADDR_EXT 0xf594
1510 #define UVD_LMI_CTRL 0xf598
1511 #define UVD_LMI_SWAP_CNTL 0xf5b4
1512 #define UVD_MP_SWAP_CNTL 0xf5bC
1513 #define UVD_MPC_CNTL 0xf5dC
1514 #define UVD_MPC_SET_MUXA0 0xf5e4
1515 #define UVD_MPC_SET_MUXA1 0xf5e8
1516 #define UVD_MPC_SET_MUXB0 0xf5eC
1517 #define UVD_MPC_SET_MUXB1 0xf5f0
1518 #define UVD_MPC_SET_MUX 0xf5f4
1519 #define UVD_MPC_SET_ALU 0xf5f8
1521 #define UVD_VCPU_CACHE_OFFSET0 0xf608
1522 #define UVD_VCPU_CACHE_SIZE0 0xf60c
1523 #define UVD_VCPU_CACHE_OFFSET1 0xf610
1524 #define UVD_VCPU_CACHE_SIZE1 0xf614
1525 #define UVD_VCPU_CACHE_OFFSET2 0xf618
1526 #define UVD_VCPU_CACHE_SIZE2 0xf61c
1528 #define UVD_VCPU_CNTL 0xf660
1529 #define UVD_SOFT_RESET 0xf680
1530 #define RBC_SOFT_RESET (1<<0)
1531 #define LBSI_SOFT_RESET (1<<1)
1532 #define LMI_SOFT_RESET (1<<2)
1533 #define VCPU_SOFT_RESET (1<<3)
1534 #define CSM_SOFT_RESET (1<<5)
1535 #define CXW_SOFT_RESET (1<<6)
1536 #define TAP_SOFT_RESET (1<<7)
1537 #define LMI_UMC_SOFT_RESET (1<<13)
1538 #define UVD_RBC_IB_BASE 0xf684
1539 #define UVD_RBC_IB_SIZE 0xf688
1540 #define UVD_RBC_RB_BASE 0xf68c
1541 #define UVD_RBC_RB_RPTR 0xf690
1542 #define UVD_RBC_RB_WPTR 0xf694
1543 #define UVD_RBC_RB_WPTR_CNTL 0xf698
1545 #define UVD_STATUS 0xf6bc
1547 #define UVD_SEMA_TIMEOUT_STATUS 0xf6c0
1548 #define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL 0xf6c4
1549 #define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL 0xf6c8
1550 #define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL 0xf6cc
1552 #define UVD_RBC_RB_CNTL 0xf6a4
1553 #define UVD_RBC_RB_RPTR_ADDR 0xf6a8
1555 #define UVD_CONTEXT_ID 0xf6f4
1558 #define GFX_MACRO_BYPASS_CNTL 0x30c0
1559 #define SPLL_BYPASS_CNTL (1 << 0)
1560 #define UPLL_BYPASS_CNTL (1 << 1)
1562 #define CG_UPLL_FUNC_CNTL 0x7e0
1563 # define UPLL_RESET_MASK 0x00000001
1564 # define UPLL_SLEEP_MASK 0x00000002
1565 # define UPLL_BYPASS_EN_MASK 0x00000004
1566 # define UPLL_CTLREQ_MASK 0x00000008
1567 # define UPLL_FB_DIV(x) ((x) << 4)
1568 # define UPLL_FB_DIV_MASK 0x0000FFF0
1569 # define UPLL_REF_DIV(x) ((x) << 16)
1570 # define UPLL_REF_DIV_MASK 0x003F0000
1571 # define UPLL_REFCLK_SRC_SEL_MASK 0x20000000
1572 # define UPLL_CTLACK_MASK 0x40000000
1573 # define UPLL_CTLACK2_MASK 0x80000000
1574 #define CG_UPLL_FUNC_CNTL_2 0x7e4
1575 # define UPLL_SW_HILEN(x) ((x) << 0)
1576 # define UPLL_SW_LOLEN(x) ((x) << 4)
1577 # define UPLL_SW_HILEN2(x) ((x) << 8)
1578 # define UPLL_SW_LOLEN2(x) ((x) << 12)
1579 # define UPLL_DIVEN_MASK 0x00010000
1580 # define UPLL_DIVEN2_MASK 0x00020000
1581 # define UPLL_SW_MASK 0x0003FFFF
1582 # define VCLK_SRC_SEL(x) ((x) << 20)
1583 # define VCLK_SRC_SEL_MASK 0x01F00000
1584 # define DCLK_SRC_SEL(x) ((x) << 25)
1585 # define DCLK_SRC_SEL_MASK 0x3E000000
1590 #define PACKET0(reg, n) ((RADEON_PACKET_TYPE0 << 30) | \
1591 (((reg) >> 2) & 0xFFFF) | \
1592 ((n) & 0x3FFF) << 16)
1593 #define PACKET3(op, n) ((RADEON_PACKET_TYPE3 << 30) | \
1594 (((op) & 0xFF) << 8) | \
1595 ((n) & 0x3FFF) << 16)
1597 /* Packet 3 types */
1598 #define PACKET3_NOP 0x10
1599 #define PACKET3_INDIRECT_BUFFER_END 0x17
1600 #define PACKET3_SET_PREDICATION 0x20
1601 #define PACKET3_REG_RMW 0x21
1602 #define PACKET3_COND_EXEC 0x22
1603 #define PACKET3_PRED_EXEC 0x23
1604 #define PACKET3_START_3D_CMDBUF 0x24
1605 #define PACKET3_DRAW_INDEX_2 0x27
1606 #define PACKET3_CONTEXT_CONTROL 0x28
1607 #define PACKET3_DRAW_INDEX_IMMD_BE 0x29
1608 #define PACKET3_INDEX_TYPE 0x2A
1609 #define PACKET3_DRAW_INDEX 0x2B
1610 #define PACKET3_DRAW_INDEX_AUTO 0x2D
1611 #define PACKET3_DRAW_INDEX_IMMD 0x2E
1612 #define PACKET3_NUM_INSTANCES 0x2F
1613 #define PACKET3_STRMOUT_BUFFER_UPDATE 0x34
1614 #define PACKET3_INDIRECT_BUFFER_MP 0x38
1615 #define PACKET3_MEM_SEMAPHORE 0x39
1616 # define PACKET3_SEM_WAIT_ON_SIGNAL (0x1 << 12)
1617 # define PACKET3_SEM_SEL_SIGNAL (0x6 << 29)
1618 # define PACKET3_SEM_SEL_WAIT (0x7 << 29)
1619 #define PACKET3_MPEG_INDEX 0x3A
1620 #define PACKET3_COPY_DW 0x3B
1621 #define PACKET3_WAIT_REG_MEM 0x3C
1622 #define PACKET3_MEM_WRITE 0x3D
1623 #define PACKET3_INDIRECT_BUFFER 0x32
1624 #define PACKET3_CP_DMA 0x41
1626 * 2. SRC_ADDR_LO [31:0]
1627 * 3. CP_SYNC [31] | SRC_ADDR_HI [7:0]
1628 * 4. DST_ADDR_LO [31:0]
1629 * 5. DST_ADDR_HI [7:0]
1630 * 6. COMMAND [29:22] | BYTE_COUNT [20:0]
1632 # define PACKET3_CP_DMA_CP_SYNC (1 << 31)
1634 # define PACKET3_CP_DMA_CMD_SRC_SWAP(x) ((x) << 22)
1640 # define PACKET3_CP_DMA_CMD_DST_SWAP(x) ((x) << 24)
1646 # define PACKET3_CP_DMA_CMD_SAS (1 << 26)
1650 # define PACKET3_CP_DMA_CMD_DAS (1 << 27)
1654 # define PACKET3_CP_DMA_CMD_SAIC (1 << 28)
1655 # define PACKET3_CP_DMA_CMD_DAIC (1 << 29)
1656 #define PACKET3_PFP_SYNC_ME 0x42 /* r7xx+ only */
1657 #define PACKET3_SURFACE_SYNC 0x43
1658 # define PACKET3_CB0_DEST_BASE_ENA (1 << 6)
1659 # define PACKET3_FULL_CACHE_ENA (1 << 20) /* r7xx+ only */
1660 # define PACKET3_TC_ACTION_ENA (1 << 23)
1661 # define PACKET3_VC_ACTION_ENA (1 << 24)
1662 # define PACKET3_CB_ACTION_ENA (1 << 25)
1663 # define PACKET3_DB_ACTION_ENA (1 << 26)
1664 # define PACKET3_SH_ACTION_ENA (1 << 27)
1665 # define PACKET3_SMX_ACTION_ENA (1 << 28)
1666 #define PACKET3_ME_INITIALIZE 0x44
1667 #define PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16)
1668 #define PACKET3_COND_WRITE 0x45
1669 #define PACKET3_EVENT_WRITE 0x46
1670 #define EVENT_TYPE(x) ((x) << 0)
1671 #define EVENT_INDEX(x) ((x) << 8)
1672 /* 0 - any non-TS event
1674 * 2 - SAMPLE_PIPELINESTAT
1675 * 3 - SAMPLE_STREAMOUTSTAT*
1676 * 4 - *S_PARTIAL_FLUSH
1679 #define PACKET3_EVENT_WRITE_EOP 0x47
1680 #define DATA_SEL(x) ((x) << 29)
1682 * 1 - send low 32bit data
1683 * 2 - send 64bit data
1684 * 3 - send 64bit counter value
1686 #define INT_SEL(x) ((x) << 24)
1688 * 1 - interrupt only (DATA_SEL = 0)
1689 * 2 - interrupt when data write is confirmed
1691 #define PACKET3_ONE_REG_WRITE 0x57
1692 #define PACKET3_SET_CONFIG_REG 0x68
1693 #define PACKET3_SET_CONFIG_REG_OFFSET 0x00008000
1694 #define PACKET3_SET_CONFIG_REG_END 0x0000ac00
1695 #define PACKET3_SET_CONTEXT_REG 0x69
1696 #define PACKET3_SET_CONTEXT_REG_OFFSET 0x00028000
1697 #define PACKET3_SET_CONTEXT_REG_END 0x00029000
1698 #define PACKET3_SET_ALU_CONST 0x6A
1699 #define PACKET3_SET_ALU_CONST_OFFSET 0x00030000
1700 #define PACKET3_SET_ALU_CONST_END 0x00032000
1701 #define PACKET3_SET_BOOL_CONST 0x6B
1702 #define PACKET3_SET_BOOL_CONST_OFFSET 0x0003e380
1703 #define PACKET3_SET_BOOL_CONST_END 0x00040000
1704 #define PACKET3_SET_LOOP_CONST 0x6C
1705 #define PACKET3_SET_LOOP_CONST_OFFSET 0x0003e200
1706 #define PACKET3_SET_LOOP_CONST_END 0x0003e380
1707 #define PACKET3_SET_RESOURCE 0x6D
1708 #define PACKET3_SET_RESOURCE_OFFSET 0x00038000
1709 #define PACKET3_SET_RESOURCE_END 0x0003c000
1710 #define PACKET3_SET_SAMPLER 0x6E
1711 #define PACKET3_SET_SAMPLER_OFFSET 0x0003c000
1712 #define PACKET3_SET_SAMPLER_END 0x0003cff0
1713 #define PACKET3_SET_CTL_CONST 0x6F
1714 #define PACKET3_SET_CTL_CONST_OFFSET 0x0003cff0
1715 #define PACKET3_SET_CTL_CONST_END 0x0003e200
1716 #define PACKET3_STRMOUT_BASE_UPDATE 0x72 /* r7xx */
1717 #define PACKET3_SURFACE_BASE_UPDATE 0x73
1719 #define R_000011_K8_FB_LOCATION 0x11
1720 #define R_000012_MC_MISC_UMA_CNTL 0x12
1721 #define G_000012_K8_ADDR_EXT(x) (((x) >> 0) & 0xFF)
1722 #define R_0028F8_MC_INDEX 0x28F8
1723 #define S_0028F8_MC_IND_ADDR(x) (((x) & 0x1FF) << 0)
1724 #define C_0028F8_MC_IND_ADDR 0xFFFFFE00
1725 #define S_0028F8_MC_IND_WR_EN(x) (((x) & 0x1) << 9)
1726 #define R_0028FC_MC_DATA 0x28FC
1728 #define R_008020_GRBM_SOFT_RESET 0x8020
1729 #define S_008020_SOFT_RESET_CP(x) (((x) & 1) << 0)
1730 #define S_008020_SOFT_RESET_CB(x) (((x) & 1) << 1)
1731 #define S_008020_SOFT_RESET_CR(x) (((x) & 1) << 2)
1732 #define S_008020_SOFT_RESET_DB(x) (((x) & 1) << 3)
1733 #define S_008020_SOFT_RESET_PA(x) (((x) & 1) << 5)
1734 #define S_008020_SOFT_RESET_SC(x) (((x) & 1) << 6)
1735 #define S_008020_SOFT_RESET_SMX(x) (((x) & 1) << 7)
1736 #define S_008020_SOFT_RESET_SPI(x) (((x) & 1) << 8)
1737 #define S_008020_SOFT_RESET_SH(x) (((x) & 1) << 9)
1738 #define S_008020_SOFT_RESET_SX(x) (((x) & 1) << 10)
1739 #define S_008020_SOFT_RESET_TC(x) (((x) & 1) << 11)
1740 #define S_008020_SOFT_RESET_TA(x) (((x) & 1) << 12)
1741 #define S_008020_SOFT_RESET_VC(x) (((x) & 1) << 13)
1742 #define S_008020_SOFT_RESET_VGT(x) (((x) & 1) << 14)
1743 #define R_008010_GRBM_STATUS 0x8010
1744 #define S_008010_CMDFIFO_AVAIL(x) (((x) & 0x1F) << 0)
1745 #define S_008010_CP_RQ_PENDING(x) (((x) & 1) << 6)
1746 #define S_008010_CF_RQ_PENDING(x) (((x) & 1) << 7)
1747 #define S_008010_PF_RQ_PENDING(x) (((x) & 1) << 8)
1748 #define S_008010_GRBM_EE_BUSY(x) (((x) & 1) << 10)
1749 #define S_008010_VC_BUSY(x) (((x) & 1) << 11)
1750 #define S_008010_DB03_CLEAN(x) (((x) & 1) << 12)
1751 #define S_008010_CB03_CLEAN(x) (((x) & 1) << 13)
1752 #define S_008010_VGT_BUSY_NO_DMA(x) (((x) & 1) << 16)
1753 #define S_008010_VGT_BUSY(x) (((x) & 1) << 17)
1754 #define S_008010_TA03_BUSY(x) (((x) & 1) << 18)
1755 #define S_008010_TC_BUSY(x) (((x) & 1) << 19)
1756 #define S_008010_SX_BUSY(x) (((x) & 1) << 20)
1757 #define S_008010_SH_BUSY(x) (((x) & 1) << 21)
1758 #define S_008010_SPI03_BUSY(x) (((x) & 1) << 22)
1759 #define S_008010_SMX_BUSY(x) (((x) & 1) << 23)
1760 #define S_008010_SC_BUSY(x) (((x) & 1) << 24)
1761 #define S_008010_PA_BUSY(x) (((x) & 1) << 25)
1762 #define S_008010_DB03_BUSY(x) (((x) & 1) << 26)
1763 #define S_008010_CR_BUSY(x) (((x) & 1) << 27)
1764 #define S_008010_CP_COHERENCY_BUSY(x) (((x) & 1) << 28)
1765 #define S_008010_CP_BUSY(x) (((x) & 1) << 29)
1766 #define S_008010_CB03_BUSY(x) (((x) & 1) << 30)
1767 #define S_008010_GUI_ACTIVE(x) (((x) & 1) << 31)
1768 #define G_008010_CMDFIFO_AVAIL(x) (((x) >> 0) & 0x1F)
1769 #define G_008010_CP_RQ_PENDING(x) (((x) >> 6) & 1)
1770 #define G_008010_CF_RQ_PENDING(x) (((x) >> 7) & 1)
1771 #define G_008010_PF_RQ_PENDING(x) (((x) >> 8) & 1)
1772 #define G_008010_GRBM_EE_BUSY(x) (((x) >> 10) & 1)
1773 #define G_008010_VC_BUSY(x) (((x) >> 11) & 1)
1774 #define G_008010_DB03_CLEAN(x) (((x) >> 12) & 1)
1775 #define G_008010_CB03_CLEAN(x) (((x) >> 13) & 1)
1776 #define G_008010_TA_BUSY(x) (((x) >> 14) & 1)
1777 #define G_008010_VGT_BUSY_NO_DMA(x) (((x) >> 16) & 1)
1778 #define G_008010_VGT_BUSY(x) (((x) >> 17) & 1)
1779 #define G_008010_TA03_BUSY(x) (((x) >> 18) & 1)
1780 #define G_008010_TC_BUSY(x) (((x) >> 19) & 1)
1781 #define G_008010_SX_BUSY(x) (((x) >> 20) & 1)
1782 #define G_008010_SH_BUSY(x) (((x) >> 21) & 1)
1783 #define G_008010_SPI03_BUSY(x) (((x) >> 22) & 1)
1784 #define G_008010_SMX_BUSY(x) (((x) >> 23) & 1)
1785 #define G_008010_SC_BUSY(x) (((x) >> 24) & 1)
1786 #define G_008010_PA_BUSY(x) (((x) >> 25) & 1)
1787 #define G_008010_DB03_BUSY(x) (((x) >> 26) & 1)
1788 #define G_008010_CR_BUSY(x) (((x) >> 27) & 1)
1789 #define G_008010_CP_COHERENCY_BUSY(x) (((x) >> 28) & 1)
1790 #define G_008010_CP_BUSY(x) (((x) >> 29) & 1)
1791 #define G_008010_CB03_BUSY(x) (((x) >> 30) & 1)
1792 #define G_008010_GUI_ACTIVE(x) (((x) >> 31) & 1)
1793 #define R_008014_GRBM_STATUS2 0x8014
1794 #define S_008014_CR_CLEAN(x) (((x) & 1) << 0)
1795 #define S_008014_SMX_CLEAN(x) (((x) & 1) << 1)
1796 #define S_008014_SPI0_BUSY(x) (((x) & 1) << 8)
1797 #define S_008014_SPI1_BUSY(x) (((x) & 1) << 9)
1798 #define S_008014_SPI2_BUSY(x) (((x) & 1) << 10)
1799 #define S_008014_SPI3_BUSY(x) (((x) & 1) << 11)
1800 #define S_008014_TA0_BUSY(x) (((x) & 1) << 12)
1801 #define S_008014_TA1_BUSY(x) (((x) & 1) << 13)
1802 #define S_008014_TA2_BUSY(x) (((x) & 1) << 14)
1803 #define S_008014_TA3_BUSY(x) (((x) & 1) << 15)
1804 #define S_008014_DB0_BUSY(x) (((x) & 1) << 16)
1805 #define S_008014_DB1_BUSY(x) (((x) & 1) << 17)
1806 #define S_008014_DB2_BUSY(x) (((x) & 1) << 18)
1807 #define S_008014_DB3_BUSY(x) (((x) & 1) << 19)
1808 #define S_008014_CB0_BUSY(x) (((x) & 1) << 20)
1809 #define S_008014_CB1_BUSY(x) (((x) & 1) << 21)
1810 #define S_008014_CB2_BUSY(x) (((x) & 1) << 22)
1811 #define S_008014_CB3_BUSY(x) (((x) & 1) << 23)
1812 #define G_008014_CR_CLEAN(x) (((x) >> 0) & 1)
1813 #define G_008014_SMX_CLEAN(x) (((x) >> 1) & 1)
1814 #define G_008014_SPI0_BUSY(x) (((x) >> 8) & 1)
1815 #define G_008014_SPI1_BUSY(x) (((x) >> 9) & 1)
1816 #define G_008014_SPI2_BUSY(x) (((x) >> 10) & 1)
1817 #define G_008014_SPI3_BUSY(x) (((x) >> 11) & 1)
1818 #define G_008014_TA0_BUSY(x) (((x) >> 12) & 1)
1819 #define G_008014_TA1_BUSY(x) (((x) >> 13) & 1)
1820 #define G_008014_TA2_BUSY(x) (((x) >> 14) & 1)
1821 #define G_008014_TA3_BUSY(x) (((x) >> 15) & 1)
1822 #define G_008014_DB0_BUSY(x) (((x) >> 16) & 1)
1823 #define G_008014_DB1_BUSY(x) (((x) >> 17) & 1)
1824 #define G_008014_DB2_BUSY(x) (((x) >> 18) & 1)
1825 #define G_008014_DB3_BUSY(x) (((x) >> 19) & 1)
1826 #define G_008014_CB0_BUSY(x) (((x) >> 20) & 1)
1827 #define G_008014_CB1_BUSY(x) (((x) >> 21) & 1)
1828 #define G_008014_CB2_BUSY(x) (((x) >> 22) & 1)
1829 #define G_008014_CB3_BUSY(x) (((x) >> 23) & 1)
1830 #define R_000E50_SRBM_STATUS 0x0E50
1831 #define G_000E50_RLC_RQ_PENDING(x) (((x) >> 3) & 1)
1832 #define G_000E50_RCU_RQ_PENDING(x) (((x) >> 4) & 1)
1833 #define G_000E50_GRBM_RQ_PENDING(x) (((x) >> 5) & 1)
1834 #define G_000E50_HI_RQ_PENDING(x) (((x) >> 6) & 1)
1835 #define G_000E50_IO_EXTERN_SIGNAL(x) (((x) >> 7) & 1)
1836 #define G_000E50_VMC_BUSY(x) (((x) >> 8) & 1)
1837 #define G_000E50_MCB_BUSY(x) (((x) >> 9) & 1)
1838 #define G_000E50_MCDZ_BUSY(x) (((x) >> 10) & 1)
1839 #define G_000E50_MCDY_BUSY(x) (((x) >> 11) & 1)
1840 #define G_000E50_MCDX_BUSY(x) (((x) >> 12) & 1)
1841 #define G_000E50_MCDW_BUSY(x) (((x) >> 13) & 1)
1842 #define G_000E50_SEM_BUSY(x) (((x) >> 14) & 1)
1843 #define G_000E50_RLC_BUSY(x) (((x) >> 15) & 1)
1844 #define G_000E50_IH_BUSY(x) (((x) >> 17) & 1)
1845 #define G_000E50_BIF_BUSY(x) (((x) >> 29) & 1)
1846 #define R_000E60_SRBM_SOFT_RESET 0x0E60
1847 #define S_000E60_SOFT_RESET_BIF(x) (((x) & 1) << 1)
1848 #define S_000E60_SOFT_RESET_CG(x) (((x) & 1) << 2)
1849 #define S_000E60_SOFT_RESET_CMC(x) (((x) & 1) << 3)
1850 #define S_000E60_SOFT_RESET_CSC(x) (((x) & 1) << 4)
1851 #define S_000E60_SOFT_RESET_DC(x) (((x) & 1) << 5)
1852 #define S_000E60_SOFT_RESET_GRBM(x) (((x) & 1) << 8)
1853 #define S_000E60_SOFT_RESET_HDP(x) (((x) & 1) << 9)
1854 #define S_000E60_SOFT_RESET_IH(x) (((x) & 1) << 10)
1855 #define S_000E60_SOFT_RESET_MC(x) (((x) & 1) << 11)
1856 #define S_000E60_SOFT_RESET_RLC(x) (((x) & 1) << 13)
1857 #define S_000E60_SOFT_RESET_ROM(x) (((x) & 1) << 14)
1858 #define S_000E60_SOFT_RESET_SEM(x) (((x) & 1) << 15)
1859 #define S_000E60_SOFT_RESET_TSC(x) (((x) & 1) << 16)
1860 #define S_000E60_SOFT_RESET_VMC(x) (((x) & 1) << 17)
1862 #define R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL 0x5480
1864 #define R_028C04_PA_SC_AA_CONFIG 0x028C04
1865 #define S_028C04_MSAA_NUM_SAMPLES(x) (((x) & 0x3) << 0)
1866 #define G_028C04_MSAA_NUM_SAMPLES(x) (((x) >> 0) & 0x3)
1867 #define C_028C04_MSAA_NUM_SAMPLES 0xFFFFFFFC
1868 #define S_028C04_AA_MASK_CENTROID_DTMN(x) (((x) & 0x1) << 4)
1869 #define G_028C04_AA_MASK_CENTROID_DTMN(x) (((x) >> 4) & 0x1)
1870 #define C_028C04_AA_MASK_CENTROID_DTMN 0xFFFFFFEF
1871 #define S_028C04_MAX_SAMPLE_DIST(x) (((x) & 0xF) << 13)
1872 #define G_028C04_MAX_SAMPLE_DIST(x) (((x) >> 13) & 0xF)
1873 #define C_028C04_MAX_SAMPLE_DIST 0xFFFE1FFF
1874 #define R_0280E0_CB_COLOR0_FRAG 0x0280E0
1875 #define S_0280E0_BASE_256B(x) (((x) & 0xFFFFFFFF) << 0)
1876 #define G_0280E0_BASE_256B(x) (((x) >> 0) & 0xFFFFFFFF)
1877 #define C_0280E0_BASE_256B 0x00000000
1878 #define R_0280E4_CB_COLOR1_FRAG 0x0280E4
1879 #define R_0280E8_CB_COLOR2_FRAG 0x0280E8
1880 #define R_0280EC_CB_COLOR3_FRAG 0x0280EC
1881 #define R_0280F0_CB_COLOR4_FRAG 0x0280F0
1882 #define R_0280F4_CB_COLOR5_FRAG 0x0280F4
1883 #define R_0280F8_CB_COLOR6_FRAG 0x0280F8
1884 #define R_0280FC_CB_COLOR7_FRAG 0x0280FC
1885 #define R_0280C0_CB_COLOR0_TILE 0x0280C0
1886 #define S_0280C0_BASE_256B(x) (((x) & 0xFFFFFFFF) << 0)
1887 #define G_0280C0_BASE_256B(x) (((x) >> 0) & 0xFFFFFFFF)
1888 #define C_0280C0_BASE_256B 0x00000000
1889 #define R_0280C4_CB_COLOR1_TILE 0x0280C4
1890 #define R_0280C8_CB_COLOR2_TILE 0x0280C8
1891 #define R_0280CC_CB_COLOR3_TILE 0x0280CC
1892 #define R_0280D0_CB_COLOR4_TILE 0x0280D0
1893 #define R_0280D4_CB_COLOR5_TILE 0x0280D4
1894 #define R_0280D8_CB_COLOR6_TILE 0x0280D8
1895 #define R_0280DC_CB_COLOR7_TILE 0x0280DC
1896 #define R_0280A0_CB_COLOR0_INFO 0x0280A0
1897 #define S_0280A0_ENDIAN(x) (((x) & 0x3) << 0)
1898 #define G_0280A0_ENDIAN(x) (((x) >> 0) & 0x3)
1899 #define C_0280A0_ENDIAN 0xFFFFFFFC
1900 #define S_0280A0_FORMAT(x) (((x) & 0x3F) << 2)
1901 #define G_0280A0_FORMAT(x) (((x) >> 2) & 0x3F)
1902 #define C_0280A0_FORMAT 0xFFFFFF03
1903 #define V_0280A0_COLOR_INVALID 0x00000000
1904 #define V_0280A0_COLOR_8 0x00000001
1905 #define V_0280A0_COLOR_4_4 0x00000002
1906 #define V_0280A0_COLOR_3_3_2 0x00000003
1907 #define V_0280A0_COLOR_16 0x00000005
1908 #define V_0280A0_COLOR_16_FLOAT 0x00000006
1909 #define V_0280A0_COLOR_8_8 0x00000007
1910 #define V_0280A0_COLOR_5_6_5 0x00000008
1911 #define V_0280A0_COLOR_6_5_5 0x00000009
1912 #define V_0280A0_COLOR_1_5_5_5 0x0000000A
1913 #define V_0280A0_COLOR_4_4_4_4 0x0000000B
1914 #define V_0280A0_COLOR_5_5_5_1 0x0000000C
1915 #define V_0280A0_COLOR_32 0x0000000D
1916 #define V_0280A0_COLOR_32_FLOAT 0x0000000E
1917 #define V_0280A0_COLOR_16_16 0x0000000F
1918 #define V_0280A0_COLOR_16_16_FLOAT 0x00000010
1919 #define V_0280A0_COLOR_8_24 0x00000011
1920 #define V_0280A0_COLOR_8_24_FLOAT 0x00000012
1921 #define V_0280A0_COLOR_24_8 0x00000013
1922 #define V_0280A0_COLOR_24_8_FLOAT 0x00000014
1923 #define V_0280A0_COLOR_10_11_11 0x00000015
1924 #define V_0280A0_COLOR_10_11_11_FLOAT 0x00000016
1925 #define V_0280A0_COLOR_11_11_10 0x00000017
1926 #define V_0280A0_COLOR_11_11_10_FLOAT 0x00000018
1927 #define V_0280A0_COLOR_2_10_10_10 0x00000019
1928 #define V_0280A0_COLOR_8_8_8_8 0x0000001A
1929 #define V_0280A0_COLOR_10_10_10_2 0x0000001B
1930 #define V_0280A0_COLOR_X24_8_32_FLOAT 0x0000001C
1931 #define V_0280A0_COLOR_32_32 0x0000001D
1932 #define V_0280A0_COLOR_32_32_FLOAT 0x0000001E
1933 #define V_0280A0_COLOR_16_16_16_16 0x0000001F
1934 #define V_0280A0_COLOR_16_16_16_16_FLOAT 0x00000020
1935 #define V_0280A0_COLOR_32_32_32_32 0x00000022
1936 #define V_0280A0_COLOR_32_32_32_32_FLOAT 0x00000023
1937 #define S_0280A0_ARRAY_MODE(x) (((x) & 0xF) << 8)
1938 #define G_0280A0_ARRAY_MODE(x) (((x) >> 8) & 0xF)
1939 #define C_0280A0_ARRAY_MODE 0xFFFFF0FF
1940 #define V_0280A0_ARRAY_LINEAR_GENERAL 0x00000000
1941 #define V_0280A0_ARRAY_LINEAR_ALIGNED 0x00000001
1942 #define V_0280A0_ARRAY_1D_TILED_THIN1 0x00000002
1943 #define V_0280A0_ARRAY_2D_TILED_THIN1 0x00000004
1944 #define S_0280A0_NUMBER_TYPE(x) (((x) & 0x7) << 12)
1945 #define G_0280A0_NUMBER_TYPE(x) (((x) >> 12) & 0x7)
1946 #define C_0280A0_NUMBER_TYPE 0xFFFF8FFF
1947 #define S_0280A0_READ_SIZE(x) (((x) & 0x1) << 15)
1948 #define G_0280A0_READ_SIZE(x) (((x) >> 15) & 0x1)
1949 #define C_0280A0_READ_SIZE 0xFFFF7FFF
1950 #define S_0280A0_COMP_SWAP(x) (((x) & 0x3) << 16)
1951 #define G_0280A0_COMP_SWAP(x) (((x) >> 16) & 0x3)
1952 #define C_0280A0_COMP_SWAP 0xFFFCFFFF
1953 #define S_0280A0_TILE_MODE(x) (((x) & 0x3) << 18)
1954 #define G_0280A0_TILE_MODE(x) (((x) >> 18) & 0x3)
1955 #define C_0280A0_TILE_MODE 0xFFF3FFFF
1956 #define V_0280A0_TILE_DISABLE 0
1957 #define V_0280A0_CLEAR_ENABLE 1
1958 #define V_0280A0_FRAG_ENABLE 2
1959 #define S_0280A0_BLEND_CLAMP(x) (((x) & 0x1) << 20)
1960 #define G_0280A0_BLEND_CLAMP(x) (((x) >> 20) & 0x1)
1961 #define C_0280A0_BLEND_CLAMP 0xFFEFFFFF
1962 #define S_0280A0_CLEAR_COLOR(x) (((x) & 0x1) << 21)
1963 #define G_0280A0_CLEAR_COLOR(x) (((x) >> 21) & 0x1)
1964 #define C_0280A0_CLEAR_COLOR 0xFFDFFFFF
1965 #define S_0280A0_BLEND_BYPASS(x) (((x) & 0x1) << 22)
1966 #define G_0280A0_BLEND_BYPASS(x) (((x) >> 22) & 0x1)
1967 #define C_0280A0_BLEND_BYPASS 0xFFBFFFFF
1968 #define S_0280A0_BLEND_FLOAT32(x) (((x) & 0x1) << 23)
1969 #define G_0280A0_BLEND_FLOAT32(x) (((x) >> 23) & 0x1)
1970 #define C_0280A0_BLEND_FLOAT32 0xFF7FFFFF
1971 #define S_0280A0_SIMPLE_FLOAT(x) (((x) & 0x1) << 24)
1972 #define G_0280A0_SIMPLE_FLOAT(x) (((x) >> 24) & 0x1)
1973 #define C_0280A0_SIMPLE_FLOAT 0xFEFFFFFF
1974 #define S_0280A0_ROUND_MODE(x) (((x) & 0x1) << 25)
1975 #define G_0280A0_ROUND_MODE(x) (((x) >> 25) & 0x1)
1976 #define C_0280A0_ROUND_MODE 0xFDFFFFFF
1977 #define S_0280A0_TILE_COMPACT(x) (((x) & 0x1) << 26)
1978 #define G_0280A0_TILE_COMPACT(x) (((x) >> 26) & 0x1)
1979 #define C_0280A0_TILE_COMPACT 0xFBFFFFFF
1980 #define S_0280A0_SOURCE_FORMAT(x) (((x) & 0x1) << 27)
1981 #define G_0280A0_SOURCE_FORMAT(x) (((x) >> 27) & 0x1)
1982 #define C_0280A0_SOURCE_FORMAT 0xF7FFFFFF
1983 #define R_0280A4_CB_COLOR1_INFO 0x0280A4
1984 #define R_0280A8_CB_COLOR2_INFO 0x0280A8
1985 #define R_0280AC_CB_COLOR3_INFO 0x0280AC
1986 #define R_0280B0_CB_COLOR4_INFO 0x0280B0
1987 #define R_0280B4_CB_COLOR5_INFO 0x0280B4
1988 #define R_0280B8_CB_COLOR6_INFO 0x0280B8
1989 #define R_0280BC_CB_COLOR7_INFO 0x0280BC
1990 #define R_028060_CB_COLOR0_SIZE 0x028060
1991 #define S_028060_PITCH_TILE_MAX(x) (((x) & 0x3FF) << 0)
1992 #define G_028060_PITCH_TILE_MAX(x) (((x) >> 0) & 0x3FF)
1993 #define C_028060_PITCH_TILE_MAX 0xFFFFFC00
1994 #define S_028060_SLICE_TILE_MAX(x) (((x) & 0xFFFFF) << 10)
1995 #define G_028060_SLICE_TILE_MAX(x) (((x) >> 10) & 0xFFFFF)
1996 #define C_028060_SLICE_TILE_MAX 0xC00003FF
1997 #define R_028064_CB_COLOR1_SIZE 0x028064
1998 #define R_028068_CB_COLOR2_SIZE 0x028068
1999 #define R_02806C_CB_COLOR3_SIZE 0x02806C
2000 #define R_028070_CB_COLOR4_SIZE 0x028070
2001 #define R_028074_CB_COLOR5_SIZE 0x028074
2002 #define R_028078_CB_COLOR6_SIZE 0x028078
2003 #define R_02807C_CB_COLOR7_SIZE 0x02807C
2004 #define R_028238_CB_TARGET_MASK 0x028238
2005 #define S_028238_TARGET0_ENABLE(x) (((x) & 0xF) << 0)
2006 #define G_028238_TARGET0_ENABLE(x) (((x) >> 0) & 0xF)
2007 #define C_028238_TARGET0_ENABLE 0xFFFFFFF0
2008 #define S_028238_TARGET1_ENABLE(x) (((x) & 0xF) << 4)
2009 #define G_028238_TARGET1_ENABLE(x) (((x) >> 4) & 0xF)
2010 #define C_028238_TARGET1_ENABLE 0xFFFFFF0F
2011 #define S_028238_TARGET2_ENABLE(x) (((x) & 0xF) << 8)
2012 #define G_028238_TARGET2_ENABLE(x) (((x) >> 8) & 0xF)
2013 #define C_028238_TARGET2_ENABLE 0xFFFFF0FF
2014 #define S_028238_TARGET3_ENABLE(x) (((x) & 0xF) << 12)
2015 #define G_028238_TARGET3_ENABLE(x) (((x) >> 12) & 0xF)
2016 #define C_028238_TARGET3_ENABLE 0xFFFF0FFF
2017 #define S_028238_TARGET4_ENABLE(x) (((x) & 0xF) << 16)
2018 #define G_028238_TARGET4_ENABLE(x) (((x) >> 16) & 0xF)
2019 #define C_028238_TARGET4_ENABLE 0xFFF0FFFF
2020 #define S_028238_TARGET5_ENABLE(x) (((x) & 0xF) << 20)
2021 #define G_028238_TARGET5_ENABLE(x) (((x) >> 20) & 0xF)
2022 #define C_028238_TARGET5_ENABLE 0xFF0FFFFF
2023 #define S_028238_TARGET6_ENABLE(x) (((x) & 0xF) << 24)
2024 #define G_028238_TARGET6_ENABLE(x) (((x) >> 24) & 0xF)
2025 #define C_028238_TARGET6_ENABLE 0xF0FFFFFF
2026 #define S_028238_TARGET7_ENABLE(x) (((x) & 0xF) << 28)
2027 #define G_028238_TARGET7_ENABLE(x) (((x) >> 28) & 0xF)
2028 #define C_028238_TARGET7_ENABLE 0x0FFFFFFF
2029 #define R_02823C_CB_SHADER_MASK 0x02823C
2030 #define S_02823C_OUTPUT0_ENABLE(x) (((x) & 0xF) << 0)
2031 #define G_02823C_OUTPUT0_ENABLE(x) (((x) >> 0) & 0xF)
2032 #define C_02823C_OUTPUT0_ENABLE 0xFFFFFFF0
2033 #define S_02823C_OUTPUT1_ENABLE(x) (((x) & 0xF) << 4)
2034 #define G_02823C_OUTPUT1_ENABLE(x) (((x) >> 4) & 0xF)
2035 #define C_02823C_OUTPUT1_ENABLE 0xFFFFFF0F
2036 #define S_02823C_OUTPUT2_ENABLE(x) (((x) & 0xF) << 8)
2037 #define G_02823C_OUTPUT2_ENABLE(x) (((x) >> 8) & 0xF)
2038 #define C_02823C_OUTPUT2_ENABLE 0xFFFFF0FF
2039 #define S_02823C_OUTPUT3_ENABLE(x) (((x) & 0xF) << 12)
2040 #define G_02823C_OUTPUT3_ENABLE(x) (((x) >> 12) & 0xF)
2041 #define C_02823C_OUTPUT3_ENABLE 0xFFFF0FFF
2042 #define S_02823C_OUTPUT4_ENABLE(x) (((x) & 0xF) << 16)
2043 #define G_02823C_OUTPUT4_ENABLE(x) (((x) >> 16) & 0xF)
2044 #define C_02823C_OUTPUT4_ENABLE 0xFFF0FFFF
2045 #define S_02823C_OUTPUT5_ENABLE(x) (((x) & 0xF) << 20)
2046 #define G_02823C_OUTPUT5_ENABLE(x) (((x) >> 20) & 0xF)
2047 #define C_02823C_OUTPUT5_ENABLE 0xFF0FFFFF
2048 #define S_02823C_OUTPUT6_ENABLE(x) (((x) & 0xF) << 24)
2049 #define G_02823C_OUTPUT6_ENABLE(x) (((x) >> 24) & 0xF)
2050 #define C_02823C_OUTPUT6_ENABLE 0xF0FFFFFF
2051 #define S_02823C_OUTPUT7_ENABLE(x) (((x) & 0xF) << 28)
2052 #define G_02823C_OUTPUT7_ENABLE(x) (((x) >> 28) & 0xF)
2053 #define C_02823C_OUTPUT7_ENABLE 0x0FFFFFFF
2054 #define R_028AB0_VGT_STRMOUT_EN 0x028AB0
2055 #define S_028AB0_STREAMOUT(x) (((x) & 0x1) << 0)
2056 #define G_028AB0_STREAMOUT(x) (((x) >> 0) & 0x1)
2057 #define C_028AB0_STREAMOUT 0xFFFFFFFE
2058 #define R_028B20_VGT_STRMOUT_BUFFER_EN 0x028B20
2059 #define S_028B20_BUFFER_0_EN(x) (((x) & 0x1) << 0)
2060 #define G_028B20_BUFFER_0_EN(x) (((x) >> 0) & 0x1)
2061 #define C_028B20_BUFFER_0_EN 0xFFFFFFFE
2062 #define S_028B20_BUFFER_1_EN(x) (((x) & 0x1) << 1)
2063 #define G_028B20_BUFFER_1_EN(x) (((x) >> 1) & 0x1)
2064 #define C_028B20_BUFFER_1_EN 0xFFFFFFFD
2065 #define S_028B20_BUFFER_2_EN(x) (((x) & 0x1) << 2)
2066 #define G_028B20_BUFFER_2_EN(x) (((x) >> 2) & 0x1)
2067 #define C_028B20_BUFFER_2_EN 0xFFFFFFFB
2068 #define S_028B20_BUFFER_3_EN(x) (((x) & 0x1) << 3)
2069 #define G_028B20_BUFFER_3_EN(x) (((x) >> 3) & 0x1)
2070 #define C_028B20_BUFFER_3_EN 0xFFFFFFF7
2071 #define S_028B20_SIZE(x) (((x) & 0xFFFFFFFF) << 0)
2072 #define G_028B20_SIZE(x) (((x) >> 0) & 0xFFFFFFFF)
2073 #define C_028B20_SIZE 0x00000000
2074 #define R_038000_SQ_TEX_RESOURCE_WORD0_0 0x038000
2075 #define S_038000_DIM(x) (((x) & 0x7) << 0)
2076 #define G_038000_DIM(x) (((x) >> 0) & 0x7)
2077 #define C_038000_DIM 0xFFFFFFF8
2078 #define V_038000_SQ_TEX_DIM_1D 0x00000000
2079 #define V_038000_SQ_TEX_DIM_2D 0x00000001
2080 #define V_038000_SQ_TEX_DIM_3D 0x00000002
2081 #define V_038000_SQ_TEX_DIM_CUBEMAP 0x00000003
2082 #define V_038000_SQ_TEX_DIM_1D_ARRAY 0x00000004
2083 #define V_038000_SQ_TEX_DIM_2D_ARRAY 0x00000005
2084 #define V_038000_SQ_TEX_DIM_2D_MSAA 0x00000006
2085 #define V_038000_SQ_TEX_DIM_2D_ARRAY_MSAA 0x00000007
2086 #define S_038000_TILE_MODE(x) (((x) & 0xF) << 3)
2087 #define G_038000_TILE_MODE(x) (((x) >> 3) & 0xF)
2088 #define C_038000_TILE_MODE 0xFFFFFF87
2089 #define V_038000_ARRAY_LINEAR_GENERAL 0x00000000
2090 #define V_038000_ARRAY_LINEAR_ALIGNED 0x00000001
2091 #define V_038000_ARRAY_1D_TILED_THIN1 0x00000002
2092 #define V_038000_ARRAY_2D_TILED_THIN1 0x00000004
2093 #define S_038000_TILE_TYPE(x) (((x) & 0x1) << 7)
2094 #define G_038000_TILE_TYPE(x) (((x) >> 7) & 0x1)
2095 #define C_038000_TILE_TYPE 0xFFFFFF7F
2096 #define S_038000_PITCH(x) (((x) & 0x7FF) << 8)
2097 #define G_038000_PITCH(x) (((x) >> 8) & 0x7FF)
2098 #define C_038000_PITCH 0xFFF800FF
2099 #define S_038000_TEX_WIDTH(x) (((x) & 0x1FFF) << 19)
2100 #define G_038000_TEX_WIDTH(x) (((x) >> 19) & 0x1FFF)
2101 #define C_038000_TEX_WIDTH 0x0007FFFF
2102 #define R_038004_SQ_TEX_RESOURCE_WORD1_0 0x038004
2103 #define S_038004_TEX_HEIGHT(x) (((x) & 0x1FFF) << 0)
2104 #define G_038004_TEX_HEIGHT(x) (((x) >> 0) & 0x1FFF)
2105 #define C_038004_TEX_HEIGHT 0xFFFFE000
2106 #define S_038004_TEX_DEPTH(x) (((x) & 0x1FFF) << 13)
2107 #define G_038004_TEX_DEPTH(x) (((x) >> 13) & 0x1FFF)
2108 #define C_038004_TEX_DEPTH 0xFC001FFF
2109 #define S_038004_DATA_FORMAT(x) (((x) & 0x3F) << 26)
2110 #define G_038004_DATA_FORMAT(x) (((x) >> 26) & 0x3F)
2111 #define C_038004_DATA_FORMAT 0x03FFFFFF
2112 #define V_038004_COLOR_INVALID 0x00000000
2113 #define V_038004_COLOR_8 0x00000001
2114 #define V_038004_COLOR_4_4 0x00000002
2115 #define V_038004_COLOR_3_3_2 0x00000003
2116 #define V_038004_COLOR_16 0x00000005
2117 #define V_038004_COLOR_16_FLOAT 0x00000006
2118 #define V_038004_COLOR_8_8 0x00000007
2119 #define V_038004_COLOR_5_6_5 0x00000008
2120 #define V_038004_COLOR_6_5_5 0x00000009
2121 #define V_038004_COLOR_1_5_5_5 0x0000000A
2122 #define V_038004_COLOR_4_4_4_4 0x0000000B
2123 #define V_038004_COLOR_5_5_5_1 0x0000000C
2124 #define V_038004_COLOR_32 0x0000000D
2125 #define V_038004_COLOR_32_FLOAT 0x0000000E
2126 #define V_038004_COLOR_16_16 0x0000000F
2127 #define V_038004_COLOR_16_16_FLOAT 0x00000010
2128 #define V_038004_COLOR_8_24 0x00000011
2129 #define V_038004_COLOR_8_24_FLOAT 0x00000012
2130 #define V_038004_COLOR_24_8 0x00000013
2131 #define V_038004_COLOR_24_8_FLOAT 0x00000014
2132 #define V_038004_COLOR_10_11_11 0x00000015
2133 #define V_038004_COLOR_10_11_11_FLOAT 0x00000016
2134 #define V_038004_COLOR_11_11_10 0x00000017
2135 #define V_038004_COLOR_11_11_10_FLOAT 0x00000018
2136 #define V_038004_COLOR_2_10_10_10 0x00000019
2137 #define V_038004_COLOR_8_8_8_8 0x0000001A
2138 #define V_038004_COLOR_10_10_10_2 0x0000001B
2139 #define V_038004_COLOR_X24_8_32_FLOAT 0x0000001C
2140 #define V_038004_COLOR_32_32 0x0000001D
2141 #define V_038004_COLOR_32_32_FLOAT 0x0000001E
2142 #define V_038004_COLOR_16_16_16_16 0x0000001F
2143 #define V_038004_COLOR_16_16_16_16_FLOAT 0x00000020
2144 #define V_038004_COLOR_32_32_32_32 0x00000022
2145 #define V_038004_COLOR_32_32_32_32_FLOAT 0x00000023
2146 #define V_038004_FMT_1 0x00000025
2147 #define V_038004_FMT_GB_GR 0x00000027
2148 #define V_038004_FMT_BG_RG 0x00000028
2149 #define V_038004_FMT_32_AS_8 0x00000029
2150 #define V_038004_FMT_32_AS_8_8 0x0000002A
2151 #define V_038004_FMT_5_9_9_9_SHAREDEXP 0x0000002B
2152 #define V_038004_FMT_8_8_8 0x0000002C
2153 #define V_038004_FMT_16_16_16 0x0000002D
2154 #define V_038004_FMT_16_16_16_FLOAT 0x0000002E
2155 #define V_038004_FMT_32_32_32 0x0000002F
2156 #define V_038004_FMT_32_32_32_FLOAT 0x00000030
2157 #define V_038004_FMT_BC1 0x00000031
2158 #define V_038004_FMT_BC2 0x00000032
2159 #define V_038004_FMT_BC3 0x00000033
2160 #define V_038004_FMT_BC4 0x00000034
2161 #define V_038004_FMT_BC5 0x00000035
2162 #define V_038004_FMT_BC6 0x00000036
2163 #define V_038004_FMT_BC7 0x00000037
2164 #define V_038004_FMT_32_AS_32_32_32_32 0x00000038
2165 #define R_038010_SQ_TEX_RESOURCE_WORD4_0 0x038010
2166 #define S_038010_FORMAT_COMP_X(x) (((x) & 0x3) << 0)
2167 #define G_038010_FORMAT_COMP_X(x) (((x) >> 0) & 0x3)
2168 #define C_038010_FORMAT_COMP_X 0xFFFFFFFC
2169 #define S_038010_FORMAT_COMP_Y(x) (((x) & 0x3) << 2)
2170 #define G_038010_FORMAT_COMP_Y(x) (((x) >> 2) & 0x3)
2171 #define C_038010_FORMAT_COMP_Y 0xFFFFFFF3
2172 #define S_038010_FORMAT_COMP_Z(x) (((x) & 0x3) << 4)
2173 #define G_038010_FORMAT_COMP_Z(x) (((x) >> 4) & 0x3)
2174 #define C_038010_FORMAT_COMP_Z 0xFFFFFFCF
2175 #define S_038010_FORMAT_COMP_W(x) (((x) & 0x3) << 6)
2176 #define G_038010_FORMAT_COMP_W(x) (((x) >> 6) & 0x3)
2177 #define C_038010_FORMAT_COMP_W 0xFFFFFF3F
2178 #define S_038010_NUM_FORMAT_ALL(x) (((x) & 0x3) << 8)
2179 #define G_038010_NUM_FORMAT_ALL(x) (((x) >> 8) & 0x3)
2180 #define C_038010_NUM_FORMAT_ALL 0xFFFFFCFF
2181 #define S_038010_SRF_MODE_ALL(x) (((x) & 0x1) << 10)
2182 #define G_038010_SRF_MODE_ALL(x) (((x) >> 10) & 0x1)
2183 #define C_038010_SRF_MODE_ALL 0xFFFFFBFF
2184 #define S_038010_FORCE_DEGAMMA(x) (((x) & 0x1) << 11)
2185 #define G_038010_FORCE_DEGAMMA(x) (((x) >> 11) & 0x1)
2186 #define C_038010_FORCE_DEGAMMA 0xFFFFF7FF
2187 #define S_038010_ENDIAN_SWAP(x) (((x) & 0x3) << 12)
2188 #define G_038010_ENDIAN_SWAP(x) (((x) >> 12) & 0x3)
2189 #define C_038010_ENDIAN_SWAP 0xFFFFCFFF
2190 #define S_038010_REQUEST_SIZE(x) (((x) & 0x3) << 14)
2191 #define G_038010_REQUEST_SIZE(x) (((x) >> 14) & 0x3)
2192 #define C_038010_REQUEST_SIZE 0xFFFF3FFF
2193 #define S_038010_DST_SEL_X(x) (((x) & 0x7) << 16)
2194 #define G_038010_DST_SEL_X(x) (((x) >> 16) & 0x7)
2195 #define C_038010_DST_SEL_X 0xFFF8FFFF
2196 #define S_038010_DST_SEL_Y(x) (((x) & 0x7) << 19)
2197 #define G_038010_DST_SEL_Y(x) (((x) >> 19) & 0x7)
2198 #define C_038010_DST_SEL_Y 0xFFC7FFFF
2199 #define S_038010_DST_SEL_Z(x) (((x) & 0x7) << 22)
2200 #define G_038010_DST_SEL_Z(x) (((x) >> 22) & 0x7)
2201 #define C_038010_DST_SEL_Z 0xFE3FFFFF
2202 #define S_038010_DST_SEL_W(x) (((x) & 0x7) << 25)
2203 #define G_038010_DST_SEL_W(x) (((x) >> 25) & 0x7)
2204 #define C_038010_DST_SEL_W 0xF1FFFFFF
2211 #define S_038010_BASE_LEVEL(x) (((x) & 0xF) << 28)
2212 #define G_038010_BASE_LEVEL(x) (((x) >> 28) & 0xF)
2213 #define C_038010_BASE_LEVEL 0x0FFFFFFF
2214 #define R_038014_SQ_TEX_RESOURCE_WORD5_0 0x038014
2215 #define S_038014_LAST_LEVEL(x) (((x) & 0xF) << 0)
2216 #define G_038014_LAST_LEVEL(x) (((x) >> 0) & 0xF)
2217 #define C_038014_LAST_LEVEL 0xFFFFFFF0
2218 #define S_038014_BASE_ARRAY(x) (((x) & 0x1FFF) << 4)
2219 #define G_038014_BASE_ARRAY(x) (((x) >> 4) & 0x1FFF)
2220 #define C_038014_BASE_ARRAY 0xFFFE000F
2221 #define S_038014_LAST_ARRAY(x) (((x) & 0x1FFF) << 17)
2222 #define G_038014_LAST_ARRAY(x) (((x) >> 17) & 0x1FFF)
2223 #define C_038014_LAST_ARRAY 0xC001FFFF
2224 #define R_0288A8_SQ_ESGS_RING_ITEMSIZE 0x0288A8
2225 #define S_0288A8_ITEMSIZE(x) (((x) & 0x7FFF) << 0)
2226 #define G_0288A8_ITEMSIZE(x) (((x) >> 0) & 0x7FFF)
2227 #define C_0288A8_ITEMSIZE 0xFFFF8000
2228 #define R_008C44_SQ_ESGS_RING_SIZE 0x008C44
2229 #define S_008C44_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0)
2230 #define G_008C44_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF)
2231 #define C_008C44_MEM_SIZE 0x00000000
2232 #define R_0288B0_SQ_ESTMP_RING_ITEMSIZE 0x0288B0
2233 #define S_0288B0_ITEMSIZE(x) (((x) & 0x7FFF) << 0)
2234 #define G_0288B0_ITEMSIZE(x) (((x) >> 0) & 0x7FFF)
2235 #define C_0288B0_ITEMSIZE 0xFFFF8000
2236 #define R_008C54_SQ_ESTMP_RING_SIZE 0x008C54
2237 #define S_008C54_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0)
2238 #define G_008C54_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF)
2239 #define C_008C54_MEM_SIZE 0x00000000
2240 #define R_0288C0_SQ_FBUF_RING_ITEMSIZE 0x0288C0
2241 #define S_0288C0_ITEMSIZE(x) (((x) & 0x7FFF) << 0)
2242 #define G_0288C0_ITEMSIZE(x) (((x) >> 0) & 0x7FFF)
2243 #define C_0288C0_ITEMSIZE 0xFFFF8000
2244 #define R_008C74_SQ_FBUF_RING_SIZE 0x008C74
2245 #define S_008C74_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0)
2246 #define G_008C74_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF)
2247 #define C_008C74_MEM_SIZE 0x00000000
2248 #define R_0288B4_SQ_GSTMP_RING_ITEMSIZE 0x0288B4
2249 #define S_0288B4_ITEMSIZE(x) (((x) & 0x7FFF) << 0)
2250 #define G_0288B4_ITEMSIZE(x) (((x) >> 0) & 0x7FFF)
2251 #define C_0288B4_ITEMSIZE 0xFFFF8000
2252 #define R_008C5C_SQ_GSTMP_RING_SIZE 0x008C5C
2253 #define S_008C5C_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0)
2254 #define G_008C5C_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF)
2255 #define C_008C5C_MEM_SIZE 0x00000000
2256 #define R_0288AC_SQ_GSVS_RING_ITEMSIZE 0x0288AC
2257 #define S_0288AC_ITEMSIZE(x) (((x) & 0x7FFF) << 0)
2258 #define G_0288AC_ITEMSIZE(x) (((x) >> 0) & 0x7FFF)
2259 #define C_0288AC_ITEMSIZE 0xFFFF8000
2260 #define R_008C4C_SQ_GSVS_RING_SIZE 0x008C4C
2261 #define S_008C4C_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0)
2262 #define G_008C4C_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF)
2263 #define C_008C4C_MEM_SIZE 0x00000000
2264 #define R_0288BC_SQ_PSTMP_RING_ITEMSIZE 0x0288BC
2265 #define S_0288BC_ITEMSIZE(x) (((x) & 0x7FFF) << 0)
2266 #define G_0288BC_ITEMSIZE(x) (((x) >> 0) & 0x7FFF)
2267 #define C_0288BC_ITEMSIZE 0xFFFF8000
2268 #define R_008C6C_SQ_PSTMP_RING_SIZE 0x008C6C
2269 #define S_008C6C_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0)
2270 #define G_008C6C_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF)
2271 #define C_008C6C_MEM_SIZE 0x00000000
2272 #define R_0288C4_SQ_REDUC_RING_ITEMSIZE 0x0288C4
2273 #define S_0288C4_ITEMSIZE(x) (((x) & 0x7FFF) << 0)
2274 #define G_0288C4_ITEMSIZE(x) (((x) >> 0) & 0x7FFF)
2275 #define C_0288C4_ITEMSIZE 0xFFFF8000
2276 #define R_008C7C_SQ_REDUC_RING_SIZE 0x008C7C
2277 #define S_008C7C_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0)
2278 #define G_008C7C_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF)
2279 #define C_008C7C_MEM_SIZE 0x00000000
2280 #define R_0288B8_SQ_VSTMP_RING_ITEMSIZE 0x0288B8
2281 #define S_0288B8_ITEMSIZE(x) (((x) & 0x7FFF) << 0)
2282 #define G_0288B8_ITEMSIZE(x) (((x) >> 0) & 0x7FFF)
2283 #define C_0288B8_ITEMSIZE 0xFFFF8000
2284 #define R_008C64_SQ_VSTMP_RING_SIZE 0x008C64
2285 #define S_008C64_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0)
2286 #define G_008C64_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF)
2287 #define C_008C64_MEM_SIZE 0x00000000
2288 #define R_0288C8_SQ_GS_VERT_ITEMSIZE 0x0288C8
2289 #define S_0288C8_ITEMSIZE(x) (((x) & 0x7FFF) << 0)
2290 #define G_0288C8_ITEMSIZE(x) (((x) >> 0) & 0x7FFF)
2291 #define C_0288C8_ITEMSIZE 0xFFFF8000
2292 #define R_028010_DB_DEPTH_INFO 0x028010
2293 #define S_028010_FORMAT(x) (((x) & 0x7) << 0)
2294 #define G_028010_FORMAT(x) (((x) >> 0) & 0x7)
2295 #define C_028010_FORMAT 0xFFFFFFF8
2296 #define V_028010_DEPTH_INVALID 0x00000000
2297 #define V_028010_DEPTH_16 0x00000001
2298 #define V_028010_DEPTH_X8_24 0x00000002
2299 #define V_028010_DEPTH_8_24 0x00000003
2300 #define V_028010_DEPTH_X8_24_FLOAT 0x00000004
2301 #define V_028010_DEPTH_8_24_FLOAT 0x00000005
2302 #define V_028010_DEPTH_32_FLOAT 0x00000006
2303 #define V_028010_DEPTH_X24_8_32_FLOAT 0x00000007
2304 #define S_028010_READ_SIZE(x) (((x) & 0x1) << 3)
2305 #define G_028010_READ_SIZE(x) (((x) >> 3) & 0x1)
2306 #define C_028010_READ_SIZE 0xFFFFFFF7
2307 #define S_028010_ARRAY_MODE(x) (((x) & 0xF) << 15)
2308 #define G_028010_ARRAY_MODE(x) (((x) >> 15) & 0xF)
2309 #define C_028010_ARRAY_MODE 0xFFF87FFF
2310 #define V_028010_ARRAY_1D_TILED_THIN1 0x00000002
2311 #define V_028010_ARRAY_2D_TILED_THIN1 0x00000004
2312 #define S_028010_TILE_SURFACE_ENABLE(x) (((x) & 0x1) << 25)
2313 #define G_028010_TILE_SURFACE_ENABLE(x) (((x) >> 25) & 0x1)
2314 #define C_028010_TILE_SURFACE_ENABLE 0xFDFFFFFF
2315 #define S_028010_TILE_COMPACT(x) (((x) & 0x1) << 26)
2316 #define G_028010_TILE_COMPACT(x) (((x) >> 26) & 0x1)
2317 #define C_028010_TILE_COMPACT 0xFBFFFFFF
2318 #define S_028010_ZRANGE_PRECISION(x) (((x) & 0x1) << 31)
2319 #define G_028010_ZRANGE_PRECISION(x) (((x) >> 31) & 0x1)
2320 #define C_028010_ZRANGE_PRECISION 0x7FFFFFFF
2321 #define R_028000_DB_DEPTH_SIZE 0x028000
2322 #define S_028000_PITCH_TILE_MAX(x) (((x) & 0x3FF) << 0)
2323 #define G_028000_PITCH_TILE_MAX(x) (((x) >> 0) & 0x3FF)
2324 #define C_028000_PITCH_TILE_MAX 0xFFFFFC00
2325 #define S_028000_SLICE_TILE_MAX(x) (((x) & 0xFFFFF) << 10)
2326 #define G_028000_SLICE_TILE_MAX(x) (((x) >> 10) & 0xFFFFF)
2327 #define C_028000_SLICE_TILE_MAX 0xC00003FF
2328 #define R_028004_DB_DEPTH_VIEW 0x028004
2329 #define S_028004_SLICE_START(x) (((x) & 0x7FF) << 0)
2330 #define G_028004_SLICE_START(x) (((x) >> 0) & 0x7FF)
2331 #define C_028004_SLICE_START 0xFFFFF800
2332 #define S_028004_SLICE_MAX(x) (((x) & 0x7FF) << 13)
2333 #define G_028004_SLICE_MAX(x) (((x) >> 13) & 0x7FF)
2334 #define C_028004_SLICE_MAX 0xFF001FFF
2335 #define R_028800_DB_DEPTH_CONTROL 0x028800
2336 #define S_028800_STENCIL_ENABLE(x) (((x) & 0x1) << 0)
2337 #define G_028800_STENCIL_ENABLE(x) (((x) >> 0) & 0x1)
2338 #define C_028800_STENCIL_ENABLE 0xFFFFFFFE
2339 #define S_028800_Z_ENABLE(x) (((x) & 0x1) << 1)
2340 #define G_028800_Z_ENABLE(x) (((x) >> 1) & 0x1)
2341 #define C_028800_Z_ENABLE 0xFFFFFFFD
2342 #define S_028800_Z_WRITE_ENABLE(x) (((x) & 0x1) << 2)
2343 #define G_028800_Z_WRITE_ENABLE(x) (((x) >> 2) & 0x1)
2344 #define C_028800_Z_WRITE_ENABLE 0xFFFFFFFB
2345 #define S_028800_ZFUNC(x) (((x) & 0x7) << 4)
2346 #define G_028800_ZFUNC(x) (((x) >> 4) & 0x7)
2347 #define C_028800_ZFUNC 0xFFFFFF8F
2348 #define S_028800_BACKFACE_ENABLE(x) (((x) & 0x1) << 7)
2349 #define G_028800_BACKFACE_ENABLE(x) (((x) >> 7) & 0x1)
2350 #define C_028800_BACKFACE_ENABLE 0xFFFFFF7F
2351 #define S_028800_STENCILFUNC(x) (((x) & 0x7) << 8)
2352 #define G_028800_STENCILFUNC(x) (((x) >> 8) & 0x7)
2353 #define C_028800_STENCILFUNC 0xFFFFF8FF
2354 #define S_028800_STENCILFAIL(x) (((x) & 0x7) << 11)
2355 #define G_028800_STENCILFAIL(x) (((x) >> 11) & 0x7)
2356 #define C_028800_STENCILFAIL 0xFFFFC7FF
2357 #define S_028800_STENCILZPASS(x) (((x) & 0x7) << 14)
2358 #define G_028800_STENCILZPASS(x) (((x) >> 14) & 0x7)
2359 #define C_028800_STENCILZPASS 0xFFFE3FFF
2360 #define S_028800_STENCILZFAIL(x) (((x) & 0x7) << 17)
2361 #define G_028800_STENCILZFAIL(x) (((x) >> 17) & 0x7)
2362 #define C_028800_STENCILZFAIL 0xFFF1FFFF
2363 #define S_028800_STENCILFUNC_BF(x) (((x) & 0x7) << 20)
2364 #define G_028800_STENCILFUNC_BF(x) (((x) >> 20) & 0x7)
2365 #define C_028800_STENCILFUNC_BF 0xFF8FFFFF
2366 #define S_028800_STENCILFAIL_BF(x) (((x) & 0x7) << 23)
2367 #define G_028800_STENCILFAIL_BF(x) (((x) >> 23) & 0x7)
2368 #define C_028800_STENCILFAIL_BF 0xFC7FFFFF
2369 #define S_028800_STENCILZPASS_BF(x) (((x) & 0x7) << 26)
2370 #define G_028800_STENCILZPASS_BF(x) (((x) >> 26) & 0x7)
2371 #define C_028800_STENCILZPASS_BF 0xE3FFFFFF
2372 #define S_028800_STENCILZFAIL_BF(x) (((x) & 0x7) << 29)
2373 #define G_028800_STENCILZFAIL_BF(x) (((x) >> 29) & 0x7)
2374 #define C_028800_STENCILZFAIL_BF 0x1FFFFFFF