2 * Copyright 2009 Advanced Micro Devices, Inc.
3 * Copyright 2009 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
23 * Authors: Dave Airlie
30 #define CP_PACKET2 0x80000000
31 #define PACKET2_PAD_SHIFT 0
32 #define PACKET2_PAD_MASK (0x3fffffff << 0)
34 #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
36 #define R6XX_MAX_SH_GPRS 256
37 #define R6XX_MAX_TEMP_GPRS 16
38 #define R6XX_MAX_SH_THREADS 256
39 #define R6XX_MAX_SH_STACK_ENTRIES 4096
40 #define R6XX_MAX_BACKENDS 8
41 #define R6XX_MAX_BACKENDS_MASK 0xff
42 #define R6XX_MAX_SIMDS 8
43 #define R6XX_MAX_SIMDS_MASK 0xff
44 #define R6XX_MAX_PIPES 8
45 #define R6XX_MAX_PIPES_MASK 0xff
48 #define PTE_VALID (1 << 0)
49 #define PTE_SYSTEM (1 << 1)
50 #define PTE_SNOOPED (1 << 2)
51 #define PTE_READABLE (1 << 5)
52 #define PTE_WRITEABLE (1 << 6)
55 #define ARRAY_LINEAR_GENERAL 0x00000000
56 #define ARRAY_LINEAR_ALIGNED 0x00000001
57 #define ARRAY_1D_TILED_THIN1 0x00000002
58 #define ARRAY_2D_TILED_THIN1 0x00000004
61 #define ARB_POP 0x2418
62 #define ENABLE_TC128 (1 << 30)
63 #define ARB_GDEC_RD_CNTL 0x246C
65 #define CC_GC_SHADER_PIPE_CONFIG 0x8950
66 #define CC_RB_BACKEND_DISABLE 0x98F4
67 #define BACKEND_DISABLE(x) ((x) << 16)
69 #define R_028808_CB_COLOR_CONTROL 0x28808
70 #define S_028808_SPECIAL_OP(x) (((x) & 0x7) << 4)
71 #define G_028808_SPECIAL_OP(x) (((x) >> 4) & 0x7)
72 #define C_028808_SPECIAL_OP 0xFFFFFF8F
73 #define V_028808_SPECIAL_NORMAL 0x00
74 #define V_028808_SPECIAL_DISABLE 0x01
75 #define V_028808_SPECIAL_RESOLVE_BOX 0x07
77 #define CB_COLOR0_BASE 0x28040
78 #define CB_COLOR1_BASE 0x28044
79 #define CB_COLOR2_BASE 0x28048
80 #define CB_COLOR3_BASE 0x2804C
81 #define CB_COLOR4_BASE 0x28050
82 #define CB_COLOR5_BASE 0x28054
83 #define CB_COLOR6_BASE 0x28058
84 #define CB_COLOR7_BASE 0x2805C
85 #define CB_COLOR7_FRAG 0x280FC
87 #define CB_COLOR0_SIZE 0x28060
88 #define CB_COLOR0_VIEW 0x28080
89 #define R_028080_CB_COLOR0_VIEW 0x028080
90 #define S_028080_SLICE_START(x) (((x) & 0x7FF) << 0)
91 #define G_028080_SLICE_START(x) (((x) >> 0) & 0x7FF)
92 #define C_028080_SLICE_START 0xFFFFF800
93 #define S_028080_SLICE_MAX(x) (((x) & 0x7FF) << 13)
94 #define G_028080_SLICE_MAX(x) (((x) >> 13) & 0x7FF)
95 #define C_028080_SLICE_MAX 0xFF001FFF
96 #define R_028084_CB_COLOR1_VIEW 0x028084
97 #define R_028088_CB_COLOR2_VIEW 0x028088
98 #define R_02808C_CB_COLOR3_VIEW 0x02808C
99 #define R_028090_CB_COLOR4_VIEW 0x028090
100 #define R_028094_CB_COLOR5_VIEW 0x028094
101 #define R_028098_CB_COLOR6_VIEW 0x028098
102 #define R_02809C_CB_COLOR7_VIEW 0x02809C
103 #define R_028100_CB_COLOR0_MASK 0x028100
104 #define S_028100_CMASK_BLOCK_MAX(x) (((x) & 0xFFF) << 0)
105 #define G_028100_CMASK_BLOCK_MAX(x) (((x) >> 0) & 0xFFF)
106 #define C_028100_CMASK_BLOCK_MAX 0xFFFFF000
107 #define S_028100_FMASK_TILE_MAX(x) (((x) & 0xFFFFF) << 12)
108 #define G_028100_FMASK_TILE_MAX(x) (((x) >> 12) & 0xFFFFF)
109 #define C_028100_FMASK_TILE_MAX 0x00000FFF
110 #define R_028104_CB_COLOR1_MASK 0x028104
111 #define R_028108_CB_COLOR2_MASK 0x028108
112 #define R_02810C_CB_COLOR3_MASK 0x02810C
113 #define R_028110_CB_COLOR4_MASK 0x028110
114 #define R_028114_CB_COLOR5_MASK 0x028114
115 #define R_028118_CB_COLOR6_MASK 0x028118
116 #define R_02811C_CB_COLOR7_MASK 0x02811C
117 #define CB_COLOR0_INFO 0x280a0
118 # define CB_FORMAT(x) ((x) << 2)
119 # define CB_ARRAY_MODE(x) ((x) << 8)
120 # define CB_SOURCE_FORMAT(x) ((x) << 27)
121 # define CB_SF_EXPORT_FULL 0
122 # define CB_SF_EXPORT_NORM 1
123 #define CB_COLOR0_TILE 0x280c0
124 #define CB_COLOR0_FRAG 0x280e0
125 #define CB_COLOR0_MASK 0x28100
127 #define SQ_ALU_CONST_CACHE_PS_0 0x28940
128 #define SQ_ALU_CONST_CACHE_PS_1 0x28944
129 #define SQ_ALU_CONST_CACHE_PS_2 0x28948
130 #define SQ_ALU_CONST_CACHE_PS_3 0x2894c
131 #define SQ_ALU_CONST_CACHE_PS_4 0x28950
132 #define SQ_ALU_CONST_CACHE_PS_5 0x28954
133 #define SQ_ALU_CONST_CACHE_PS_6 0x28958
134 #define SQ_ALU_CONST_CACHE_PS_7 0x2895c
135 #define SQ_ALU_CONST_CACHE_PS_8 0x28960
136 #define SQ_ALU_CONST_CACHE_PS_9 0x28964
137 #define SQ_ALU_CONST_CACHE_PS_10 0x28968
138 #define SQ_ALU_CONST_CACHE_PS_11 0x2896c
139 #define SQ_ALU_CONST_CACHE_PS_12 0x28970
140 #define SQ_ALU_CONST_CACHE_PS_13 0x28974
141 #define SQ_ALU_CONST_CACHE_PS_14 0x28978
142 #define SQ_ALU_CONST_CACHE_PS_15 0x2897c
143 #define SQ_ALU_CONST_CACHE_VS_0 0x28980
144 #define SQ_ALU_CONST_CACHE_VS_1 0x28984
145 #define SQ_ALU_CONST_CACHE_VS_2 0x28988
146 #define SQ_ALU_CONST_CACHE_VS_3 0x2898c
147 #define SQ_ALU_CONST_CACHE_VS_4 0x28990
148 #define SQ_ALU_CONST_CACHE_VS_5 0x28994
149 #define SQ_ALU_CONST_CACHE_VS_6 0x28998
150 #define SQ_ALU_CONST_CACHE_VS_7 0x2899c
151 #define SQ_ALU_CONST_CACHE_VS_8 0x289a0
152 #define SQ_ALU_CONST_CACHE_VS_9 0x289a4
153 #define SQ_ALU_CONST_CACHE_VS_10 0x289a8
154 #define SQ_ALU_CONST_CACHE_VS_11 0x289ac
155 #define SQ_ALU_CONST_CACHE_VS_12 0x289b0
156 #define SQ_ALU_CONST_CACHE_VS_13 0x289b4
157 #define SQ_ALU_CONST_CACHE_VS_14 0x289b8
158 #define SQ_ALU_CONST_CACHE_VS_15 0x289bc
159 #define SQ_ALU_CONST_CACHE_GS_0 0x289c0
160 #define SQ_ALU_CONST_CACHE_GS_1 0x289c4
161 #define SQ_ALU_CONST_CACHE_GS_2 0x289c8
162 #define SQ_ALU_CONST_CACHE_GS_3 0x289cc
163 #define SQ_ALU_CONST_CACHE_GS_4 0x289d0
164 #define SQ_ALU_CONST_CACHE_GS_5 0x289d4
165 #define SQ_ALU_CONST_CACHE_GS_6 0x289d8
166 #define SQ_ALU_CONST_CACHE_GS_7 0x289dc
167 #define SQ_ALU_CONST_CACHE_GS_8 0x289e0
168 #define SQ_ALU_CONST_CACHE_GS_9 0x289e4
169 #define SQ_ALU_CONST_CACHE_GS_10 0x289e8
170 #define SQ_ALU_CONST_CACHE_GS_11 0x289ec
171 #define SQ_ALU_CONST_CACHE_GS_12 0x289f0
172 #define SQ_ALU_CONST_CACHE_GS_13 0x289f4
173 #define SQ_ALU_CONST_CACHE_GS_14 0x289f8
174 #define SQ_ALU_CONST_CACHE_GS_15 0x289fc
176 #define CONFIG_MEMSIZE 0x5428
177 #define CONFIG_CNTL 0x5424
178 #define CP_STALLED_STAT1 0x8674
179 #define CP_STALLED_STAT2 0x8678
180 #define CP_BUSY_STAT 0x867C
181 #define CP_STAT 0x8680
182 #define CP_COHER_BASE 0x85F8
183 #define CP_DEBUG 0xC1FC
184 #define R_0086D8_CP_ME_CNTL 0x86D8
185 #define S_0086D8_CP_ME_HALT(x) (((x) & 1)<<28)
186 #define C_0086D8_CP_ME_HALT(x) ((x) & 0xEFFFFFFF)
187 #define CP_ME_RAM_DATA 0xC160
188 #define CP_ME_RAM_RADDR 0xC158
189 #define CP_ME_RAM_WADDR 0xC15C
190 #define CP_MEQ_THRESHOLDS 0x8764
191 #define MEQ_END(x) ((x) << 16)
192 #define ROQ_END(x) ((x) << 24)
193 #define CP_PERFMON_CNTL 0x87FC
194 #define CP_PFP_UCODE_ADDR 0xC150
195 #define CP_PFP_UCODE_DATA 0xC154
196 #define CP_QUEUE_THRESHOLDS 0x8760
197 #define ROQ_IB1_START(x) ((x) << 0)
198 #define ROQ_IB2_START(x) ((x) << 8)
199 #define CP_RB_BASE 0xC100
200 #define CP_RB_CNTL 0xC104
201 #define RB_BUFSZ(x) ((x) << 0)
202 #define RB_BLKSZ(x) ((x) << 8)
203 #define RB_NO_UPDATE (1 << 27)
204 #define RB_RPTR_WR_ENA (1 << 31)
205 #define BUF_SWAP_32BIT (2 << 16)
206 #define CP_RB_RPTR 0x8700
207 #define CP_RB_RPTR_ADDR 0xC10C
208 #define RB_RPTR_SWAP(x) ((x) << 0)
209 #define CP_RB_RPTR_ADDR_HI 0xC110
210 #define CP_RB_RPTR_WR 0xC108
211 #define CP_RB_WPTR 0xC114
212 #define CP_RB_WPTR_ADDR 0xC118
213 #define CP_RB_WPTR_ADDR_HI 0xC11C
214 #define CP_RB_WPTR_DELAY 0x8704
215 #define CP_ROQ_IB1_STAT 0x8784
216 #define CP_ROQ_IB2_STAT 0x8788
217 #define CP_SEM_WAIT_TIMER 0x85BC
219 #define DB_DEBUG 0x9830
220 #define PREZ_MUST_WAIT_FOR_POSTZ_DONE (1 << 31)
221 #define DB_DEPTH_BASE 0x2800C
222 #define DB_HTILE_DATA_BASE 0x28014
223 #define DB_HTILE_SURFACE 0x28D24
224 #define S_028D24_HTILE_WIDTH(x) (((x) & 0x1) << 0)
225 #define G_028D24_HTILE_WIDTH(x) (((x) >> 0) & 0x1)
226 #define C_028D24_HTILE_WIDTH 0xFFFFFFFE
227 #define S_028D24_HTILE_HEIGHT(x) (((x) & 0x1) << 1)
228 #define G_028D24_HTILE_HEIGHT(x) (((x) >> 1) & 0x1)
229 #define C_028D24_HTILE_HEIGHT 0xFFFFFFFD
230 #define G_028D24_LINEAR(x) (((x) >> 2) & 0x1)
231 #define DB_WATERMARKS 0x9838
232 #define DEPTH_FREE(x) ((x) << 0)
233 #define DEPTH_FLUSH(x) ((x) << 5)
234 #define DEPTH_PENDING_FREE(x) ((x) << 15)
235 #define DEPTH_CACHELINE_FREE(x) ((x) << 20)
237 #define DCP_TILING_CONFIG 0x6CA0
238 #define PIPE_TILING(x) ((x) << 1)
239 #define BANK_TILING(x) ((x) << 4)
240 #define GROUP_SIZE(x) ((x) << 6)
241 #define ROW_TILING(x) ((x) << 8)
242 #define BANK_SWAPS(x) ((x) << 11)
243 #define SAMPLE_SPLIT(x) ((x) << 14)
244 #define BACKEND_MAP(x) ((x) << 16)
246 #define GB_TILING_CONFIG 0x98F0
247 #define PIPE_TILING__SHIFT 1
248 #define PIPE_TILING__MASK 0x0000000e
250 #define GC_USER_SHADER_PIPE_CONFIG 0x8954
251 #define INACTIVE_QD_PIPES(x) ((x) << 8)
252 #define INACTIVE_QD_PIPES_MASK 0x0000FF00
253 #define INACTIVE_SIMDS(x) ((x) << 16)
254 #define INACTIVE_SIMDS_MASK 0x00FF0000
256 #define SQ_CONFIG 0x8c00
257 # define VC_ENABLE (1 << 0)
258 # define EXPORT_SRC_C (1 << 1)
259 # define DX9_CONSTS (1 << 2)
260 # define ALU_INST_PREFER_VECTOR (1 << 3)
261 # define DX10_CLAMP (1 << 4)
262 # define CLAUSE_SEQ_PRIO(x) ((x) << 8)
263 # define PS_PRIO(x) ((x) << 24)
264 # define VS_PRIO(x) ((x) << 26)
265 # define GS_PRIO(x) ((x) << 28)
266 # define ES_PRIO(x) ((x) << 30)
267 #define SQ_GPR_RESOURCE_MGMT_1 0x8c04
268 # define NUM_PS_GPRS(x) ((x) << 0)
269 # define NUM_VS_GPRS(x) ((x) << 16)
270 # define NUM_CLAUSE_TEMP_GPRS(x) ((x) << 28)
271 #define SQ_GPR_RESOURCE_MGMT_2 0x8c08
272 # define NUM_GS_GPRS(x) ((x) << 0)
273 # define NUM_ES_GPRS(x) ((x) << 16)
274 #define SQ_THREAD_RESOURCE_MGMT 0x8c0c
275 # define NUM_PS_THREADS(x) ((x) << 0)
276 # define NUM_VS_THREADS(x) ((x) << 8)
277 # define NUM_GS_THREADS(x) ((x) << 16)
278 # define NUM_ES_THREADS(x) ((x) << 24)
279 #define SQ_STACK_RESOURCE_MGMT_1 0x8c10
280 # define NUM_PS_STACK_ENTRIES(x) ((x) << 0)
281 # define NUM_VS_STACK_ENTRIES(x) ((x) << 16)
282 #define SQ_STACK_RESOURCE_MGMT_2 0x8c14
283 # define NUM_GS_STACK_ENTRIES(x) ((x) << 0)
284 # define NUM_ES_STACK_ENTRIES(x) ((x) << 16)
285 #define SQ_ESGS_RING_BASE 0x8c40
286 #define SQ_GSVS_RING_BASE 0x8c48
287 #define SQ_ESTMP_RING_BASE 0x8c50
288 #define SQ_GSTMP_RING_BASE 0x8c58
289 #define SQ_VSTMP_RING_BASE 0x8c60
290 #define SQ_PSTMP_RING_BASE 0x8c68
291 #define SQ_FBUF_RING_BASE 0x8c70
292 #define SQ_REDUC_RING_BASE 0x8c78
294 #define GRBM_CNTL 0x8000
295 # define GRBM_READ_TIMEOUT(x) ((x) << 0)
296 #define GRBM_STATUS 0x8010
297 #define CMDFIFO_AVAIL_MASK 0x0000001F
298 #define GUI_ACTIVE (1<<31)
299 #define GRBM_STATUS2 0x8014
300 #define GRBM_SOFT_RESET 0x8020
301 #define SOFT_RESET_CP (1<<0)
303 #define CG_THERMAL_STATUS 0x7F4
304 #define ASIC_T(x) ((x) << 0)
305 #define ASIC_T_MASK 0x1FF
306 #define ASIC_T_SHIFT 0
308 #define HDP_HOST_PATH_CNTL 0x2C00
309 #define HDP_NONSURFACE_BASE 0x2C04
310 #define HDP_NONSURFACE_INFO 0x2C08
311 #define HDP_NONSURFACE_SIZE 0x2C0C
312 #define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0
313 #define HDP_TILING_CONFIG 0x2F3C
314 #define HDP_DEBUG1 0x2F34
316 #define MC_VM_AGP_TOP 0x2184
317 #define MC_VM_AGP_BOT 0x2188
318 #define MC_VM_AGP_BASE 0x218C
319 #define MC_VM_FB_LOCATION 0x2180
320 #define MC_VM_L1_TLB_MCD_RD_A_CNTL 0x219C
321 #define ENABLE_L1_TLB (1 << 0)
322 #define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1)
323 #define ENABLE_L1_STRICT_ORDERING (1 << 2)
324 #define SYSTEM_ACCESS_MODE_MASK 0x000000C0
325 #define SYSTEM_ACCESS_MODE_SHIFT 6
326 #define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 6)
327 #define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 6)
328 #define SYSTEM_ACCESS_MODE_IN_SYS (2 << 6)
329 #define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 6)
330 #define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 8)
331 #define SYSTEM_APERTURE_UNMAPPED_ACCESS_DEFAULT_PAGE (1 << 8)
332 #define ENABLE_SEMAPHORE_MODE (1 << 10)
333 #define ENABLE_WAIT_L2_QUERY (1 << 11)
334 #define EFFECTIVE_L1_TLB_SIZE(x) (((x) & 7) << 12)
335 #define EFFECTIVE_L1_TLB_SIZE_MASK 0x00007000
336 #define EFFECTIVE_L1_TLB_SIZE_SHIFT 12
337 #define EFFECTIVE_L1_QUEUE_SIZE(x) (((x) & 7) << 15)
338 #define EFFECTIVE_L1_QUEUE_SIZE_MASK 0x00038000
339 #define EFFECTIVE_L1_QUEUE_SIZE_SHIFT 15
340 #define MC_VM_L1_TLB_MCD_RD_B_CNTL 0x21A0
341 #define MC_VM_L1_TLB_MCB_RD_GFX_CNTL 0x21FC
342 #define MC_VM_L1_TLB_MCB_RD_HDP_CNTL 0x2204
343 #define MC_VM_L1_TLB_MCB_RD_PDMA_CNTL 0x2208
344 #define MC_VM_L1_TLB_MCB_RD_SEM_CNTL 0x220C
345 #define MC_VM_L1_TLB_MCB_RD_SYS_CNTL 0x2200
346 #define MC_VM_L1_TLB_MCD_WR_A_CNTL 0x21A4
347 #define MC_VM_L1_TLB_MCD_WR_B_CNTL 0x21A8
348 #define MC_VM_L1_TLB_MCB_WR_GFX_CNTL 0x2210
349 #define MC_VM_L1_TLB_MCB_WR_HDP_CNTL 0x2218
350 #define MC_VM_L1_TLB_MCB_WR_PDMA_CNTL 0x221C
351 #define MC_VM_L1_TLB_MCB_WR_SEM_CNTL 0x2220
352 #define MC_VM_L1_TLB_MCB_WR_SYS_CNTL 0x2214
353 #define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2190
354 #define LOGICAL_PAGE_NUMBER_MASK 0x000FFFFF
355 #define LOGICAL_PAGE_NUMBER_SHIFT 0
356 #define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2194
357 #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x2198
359 #define PA_CL_ENHANCE 0x8A14
360 #define CLIP_VTX_REORDER_ENA (1 << 0)
361 #define NUM_CLIP_SEQ(x) ((x) << 1)
362 #define PA_SC_AA_CONFIG 0x28C04
363 #define PA_SC_AA_SAMPLE_LOCS_2S 0x8B40
364 #define PA_SC_AA_SAMPLE_LOCS_4S 0x8B44
365 #define PA_SC_AA_SAMPLE_LOCS_8S_WD0 0x8B48
366 #define PA_SC_AA_SAMPLE_LOCS_8S_WD1 0x8B4C
367 #define S0_X(x) ((x) << 0)
368 #define S0_Y(x) ((x) << 4)
369 #define S1_X(x) ((x) << 8)
370 #define S1_Y(x) ((x) << 12)
371 #define S2_X(x) ((x) << 16)
372 #define S2_Y(x) ((x) << 20)
373 #define S3_X(x) ((x) << 24)
374 #define S3_Y(x) ((x) << 28)
375 #define S4_X(x) ((x) << 0)
376 #define S4_Y(x) ((x) << 4)
377 #define S5_X(x) ((x) << 8)
378 #define S5_Y(x) ((x) << 12)
379 #define S6_X(x) ((x) << 16)
380 #define S6_Y(x) ((x) << 20)
381 #define S7_X(x) ((x) << 24)
382 #define S7_Y(x) ((x) << 28)
383 #define PA_SC_CLIPRECT_RULE 0x2820c
384 #define PA_SC_ENHANCE 0x8BF0
385 #define FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0)
386 #define FORCE_EOV_MAX_TILE_CNT(x) ((x) << 12)
387 #define PA_SC_LINE_STIPPLE 0x28A0C
388 #define PA_SC_LINE_STIPPLE_STATE 0x8B10
389 #define PA_SC_MODE_CNTL 0x28A4C
390 #define PA_SC_MULTI_CHIP_CNTL 0x8B20
392 #define PA_SC_SCREEN_SCISSOR_TL 0x28030
393 #define PA_SC_GENERIC_SCISSOR_TL 0x28240
394 #define PA_SC_WINDOW_SCISSOR_TL 0x28204
396 #define PCIE_PORT_INDEX 0x0038
397 #define PCIE_PORT_DATA 0x003C
400 #define NOOFCHAN_SHIFT 12
401 #define NOOFCHAN_MASK 0x00003000
403 #define RAMCFG 0x2408
404 #define NOOFBANK_SHIFT 0
405 #define NOOFBANK_MASK 0x00000001
406 #define NOOFRANK_SHIFT 1
407 #define NOOFRANK_MASK 0x00000002
408 #define NOOFROWS_SHIFT 2
409 #define NOOFROWS_MASK 0x0000001C
410 #define NOOFCOLS_SHIFT 5
411 #define NOOFCOLS_MASK 0x00000060
412 #define CHANSIZE_SHIFT 7
413 #define CHANSIZE_MASK 0x00000080
414 #define BURSTLENGTH_SHIFT 8
415 #define BURSTLENGTH_MASK 0x00000100
416 #define CHANSIZE_OVERRIDE (1 << 10)
418 #define SCRATCH_REG0 0x8500
419 #define SCRATCH_REG1 0x8504
420 #define SCRATCH_REG2 0x8508
421 #define SCRATCH_REG3 0x850C
422 #define SCRATCH_REG4 0x8510
423 #define SCRATCH_REG5 0x8514
424 #define SCRATCH_REG6 0x8518
425 #define SCRATCH_REG7 0x851C
426 #define SCRATCH_UMSK 0x8540
427 #define SCRATCH_ADDR 0x8544
429 #define SPI_CONFIG_CNTL 0x9100
430 #define GPR_WRITE_PRIORITY(x) ((x) << 0)
431 #define DISABLE_INTERP_1 (1 << 5)
432 #define SPI_CONFIG_CNTL_1 0x913C
433 #define VTX_DONE_DELAY(x) ((x) << 0)
434 #define INTERP_ONE_PRIM_PER_ROW (1 << 4)
435 #define SPI_INPUT_Z 0x286D8
436 #define SPI_PS_IN_CONTROL_0 0x286CC
437 #define NUM_INTERP(x) ((x)<<0)
438 #define POSITION_ENA (1<<8)
439 #define POSITION_CENTROID (1<<9)
440 #define POSITION_ADDR(x) ((x)<<10)
441 #define PARAM_GEN(x) ((x)<<15)
442 #define PARAM_GEN_ADDR(x) ((x)<<19)
443 #define BARYC_SAMPLE_CNTL(x) ((x)<<26)
444 #define PERSP_GRADIENT_ENA (1<<28)
445 #define LINEAR_GRADIENT_ENA (1<<29)
446 #define POSITION_SAMPLE (1<<30)
447 #define BARYC_AT_SAMPLE_ENA (1<<31)
448 #define SPI_PS_IN_CONTROL_1 0x286D0
449 #define GEN_INDEX_PIX (1<<0)
450 #define GEN_INDEX_PIX_ADDR(x) ((x)<<1)
451 #define FRONT_FACE_ENA (1<<8)
452 #define FRONT_FACE_CHAN(x) ((x)<<9)
453 #define FRONT_FACE_ALL_BITS (1<<11)
454 #define FRONT_FACE_ADDR(x) ((x)<<12)
455 #define FOG_ADDR(x) ((x)<<17)
456 #define FIXED_PT_POSITION_ENA (1<<24)
457 #define FIXED_PT_POSITION_ADDR(x) ((x)<<25)
459 #define SQ_MS_FIFO_SIZES 0x8CF0
460 #define CACHE_FIFO_SIZE(x) ((x) << 0)
461 #define FETCH_FIFO_HIWATER(x) ((x) << 8)
462 #define DONE_FIFO_HIWATER(x) ((x) << 16)
463 #define ALU_UPDATE_FIFO_HIWATER(x) ((x) << 24)
464 #define SQ_PGM_START_ES 0x28880
465 #define SQ_PGM_START_FS 0x28894
466 #define SQ_PGM_START_GS 0x2886C
467 #define SQ_PGM_START_PS 0x28840
468 #define SQ_PGM_RESOURCES_PS 0x28850
469 #define SQ_PGM_EXPORTS_PS 0x28854
470 #define SQ_PGM_CF_OFFSET_PS 0x288cc
471 #define SQ_PGM_START_VS 0x28858
472 #define SQ_PGM_RESOURCES_VS 0x28868
473 #define SQ_PGM_CF_OFFSET_VS 0x288d0
475 #define SQ_VTX_CONSTANT_WORD0_0 0x30000
476 #define SQ_VTX_CONSTANT_WORD1_0 0x30004
477 #define SQ_VTX_CONSTANT_WORD2_0 0x30008
478 # define SQ_VTXC_BASE_ADDR_HI(x) ((x) << 0)
479 # define SQ_VTXC_STRIDE(x) ((x) << 8)
480 # define SQ_VTXC_ENDIAN_SWAP(x) ((x) << 30)
481 # define SQ_ENDIAN_NONE 0
482 # define SQ_ENDIAN_8IN16 1
483 # define SQ_ENDIAN_8IN32 2
484 #define SQ_VTX_CONSTANT_WORD3_0 0x3000c
485 #define SQ_VTX_CONSTANT_WORD6_0 0x38018
486 #define S__SQ_VTX_CONSTANT_TYPE(x) (((x) & 3) << 30)
487 #define G__SQ_VTX_CONSTANT_TYPE(x) (((x) >> 30) & 3)
488 #define SQ_TEX_VTX_INVALID_TEXTURE 0x0
489 #define SQ_TEX_VTX_INVALID_BUFFER 0x1
490 #define SQ_TEX_VTX_VALID_TEXTURE 0x2
491 #define SQ_TEX_VTX_VALID_BUFFER 0x3
494 #define SX_MISC 0x28350
495 #define SX_MEMORY_EXPORT_BASE 0x9010
496 #define SX_DEBUG_1 0x9054
497 #define SMX_EVENT_RELEASE (1 << 0)
498 #define ENABLE_NEW_SMX_ADDRESS (1 << 16)
500 #define TA_CNTL_AUX 0x9508
501 #define DISABLE_CUBE_WRAP (1 << 0)
502 #define DISABLE_CUBE_ANISO (1 << 1)
503 #define SYNC_GRADIENT (1 << 24)
504 #define SYNC_WALKER (1 << 25)
505 #define SYNC_ALIGNER (1 << 26)
506 #define BILINEAR_PRECISION_6_BIT (0 << 31)
507 #define BILINEAR_PRECISION_8_BIT (1 << 31)
509 #define TC_CNTL 0x9608
510 #define TC_L2_SIZE(x) ((x)<<5)
511 #define L2_DISABLE_LATE_HIT (1<<9)
513 #define VC_ENHANCE 0x9714
515 #define VGT_CACHE_INVALIDATION 0x88C4
516 #define CACHE_INVALIDATION(x) ((x)<<0)
520 #define VGT_DMA_BASE 0x287E8
521 #define VGT_DMA_BASE_HI 0x287E4
522 #define VGT_ES_PER_GS 0x88CC
523 #define VGT_GS_PER_ES 0x88C8
524 #define VGT_GS_PER_VS 0x88E8
525 #define VGT_GS_VERTEX_REUSE 0x88D4
526 #define VGT_PRIMITIVE_TYPE 0x8958
527 #define VGT_NUM_INSTANCES 0x8974
528 #define VGT_OUT_DEALLOC_CNTL 0x28C5C
529 #define DEALLOC_DIST_MASK 0x0000007F
530 #define VGT_STRMOUT_BASE_OFFSET_0 0x28B10
531 #define VGT_STRMOUT_BASE_OFFSET_1 0x28B14
532 #define VGT_STRMOUT_BASE_OFFSET_2 0x28B18
533 #define VGT_STRMOUT_BASE_OFFSET_3 0x28B1c
534 #define VGT_STRMOUT_BASE_OFFSET_HI_0 0x28B44
535 #define VGT_STRMOUT_BASE_OFFSET_HI_1 0x28B48
536 #define VGT_STRMOUT_BASE_OFFSET_HI_2 0x28B4c
537 #define VGT_STRMOUT_BASE_OFFSET_HI_3 0x28B50
538 #define VGT_STRMOUT_BUFFER_BASE_0 0x28AD8
539 #define VGT_STRMOUT_BUFFER_BASE_1 0x28AE8
540 #define VGT_STRMOUT_BUFFER_BASE_2 0x28AF8
541 #define VGT_STRMOUT_BUFFER_BASE_3 0x28B08
542 #define VGT_STRMOUT_BUFFER_OFFSET_0 0x28ADC
543 #define VGT_STRMOUT_BUFFER_OFFSET_1 0x28AEC
544 #define VGT_STRMOUT_BUFFER_OFFSET_2 0x28AFC
545 #define VGT_STRMOUT_BUFFER_OFFSET_3 0x28B0C
546 #define VGT_STRMOUT_BUFFER_SIZE_0 0x28AD0
547 #define VGT_STRMOUT_BUFFER_SIZE_1 0x28AE0
548 #define VGT_STRMOUT_BUFFER_SIZE_2 0x28AF0
549 #define VGT_STRMOUT_BUFFER_SIZE_3 0x28B00
551 #define VGT_STRMOUT_EN 0x28AB0
552 #define VGT_VERTEX_REUSE_BLOCK_CNTL 0x28C58
553 #define VTX_REUSE_DEPTH_MASK 0x000000FF
554 #define VGT_EVENT_INITIATOR 0x28a90
555 # define CACHE_FLUSH_AND_INV_EVENT_TS (0x14 << 0)
556 # define CACHE_FLUSH_AND_INV_EVENT (0x16 << 0)
558 #define VM_CONTEXT0_CNTL 0x1410
559 #define ENABLE_CONTEXT (1 << 0)
560 #define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1)
561 #define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4)
562 #define VM_CONTEXT0_INVALIDATION_LOW_ADDR 0x1490
563 #define VM_CONTEXT0_INVALIDATION_HIGH_ADDR 0x14B0
564 #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x1574
565 #define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x1594
566 #define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x15B4
567 #define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1554
568 #define VM_CONTEXT0_REQUEST_RESPONSE 0x1470
569 #define REQUEST_TYPE(x) (((x) & 0xf) << 0)
570 #define RESPONSE_TYPE_MASK 0x000000F0
571 #define RESPONSE_TYPE_SHIFT 4
572 #define VM_L2_CNTL 0x1400
573 #define ENABLE_L2_CACHE (1 << 0)
574 #define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1)
575 #define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9)
576 #define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 13)
577 #define VM_L2_CNTL2 0x1404
578 #define INVALIDATE_ALL_L1_TLBS (1 << 0)
579 #define INVALIDATE_L2_CACHE (1 << 1)
580 #define VM_L2_CNTL3 0x1408
581 #define BANK_SELECT_0(x) (((x) & 0x1f) << 0)
582 #define BANK_SELECT_1(x) (((x) & 0x1f) << 5)
583 #define L2_CACHE_UPDATE_MODE(x) (((x) & 3) << 10)
584 #define VM_L2_STATUS 0x140C
585 #define L2_BUSY (1 << 0)
587 #define WAIT_UNTIL 0x8040
588 #define WAIT_2D_IDLE_bit (1 << 14)
589 #define WAIT_3D_IDLE_bit (1 << 15)
590 #define WAIT_2D_IDLECLEAN_bit (1 << 16)
591 #define WAIT_3D_IDLECLEAN_bit (1 << 17)
594 #define DMA_TILING_CONFIG 0x3ec4
595 #define DMA_CONFIG 0x3e4c
597 #define DMA_RB_CNTL 0xd000
598 # define DMA_RB_ENABLE (1 << 0)
599 # define DMA_RB_SIZE(x) ((x) << 1) /* log2 */
600 # define DMA_RB_SWAP_ENABLE (1 << 9) /* 8IN32 */
601 # define DMA_RPTR_WRITEBACK_ENABLE (1 << 12)
602 # define DMA_RPTR_WRITEBACK_SWAP_ENABLE (1 << 13) /* 8IN32 */
603 # define DMA_RPTR_WRITEBACK_TIMER(x) ((x) << 16) /* log2 */
604 #define DMA_RB_BASE 0xd004
605 #define DMA_RB_RPTR 0xd008
606 #define DMA_RB_WPTR 0xd00c
608 #define DMA_RB_RPTR_ADDR_HI 0xd01c
609 #define DMA_RB_RPTR_ADDR_LO 0xd020
611 #define DMA_IB_CNTL 0xd024
612 # define DMA_IB_ENABLE (1 << 0)
613 # define DMA_IB_SWAP_ENABLE (1 << 4)
614 #define DMA_IB_RPTR 0xd028
615 #define DMA_CNTL 0xd02c
616 # define TRAP_ENABLE (1 << 0)
617 # define SEM_INCOMPLETE_INT_ENABLE (1 << 1)
618 # define SEM_WAIT_INT_ENABLE (1 << 2)
619 # define DATA_SWAP_ENABLE (1 << 3)
620 # define FENCE_SWAP_ENABLE (1 << 4)
621 # define CTXEMPTY_INT_ENABLE (1 << 28)
622 #define DMA_STATUS_REG 0xd034
623 # define DMA_IDLE (1 << 0)
624 #define DMA_SEM_INCOMPLETE_TIMER_CNTL 0xd044
625 #define DMA_SEM_WAIT_FAIL_TIMER_CNTL 0xd048
626 #define DMA_MODE 0xd0bc
628 /* async DMA packets */
629 #define DMA_PACKET(cmd, t, s, n) ((((cmd) & 0xF) << 28) | \
630 (((t) & 0x1) << 23) | \
631 (((s) & 0x1) << 22) | \
632 (((n) & 0xFFFF) << 0))
633 /* async DMA Packet types */
634 #define DMA_PACKET_WRITE 0x2
635 #define DMA_PACKET_COPY 0x3
636 #define DMA_PACKET_INDIRECT_BUFFER 0x4
637 #define DMA_PACKET_SEMAPHORE 0x5
638 #define DMA_PACKET_FENCE 0x6
639 #define DMA_PACKET_TRAP 0x7
640 #define DMA_PACKET_CONSTANT_FILL 0xd /* 7xx only */
641 #define DMA_PACKET_NOP 0xf
643 #define IH_RB_CNTL 0x3e00
644 # define IH_RB_ENABLE (1 << 0)
645 # define IH_RB_SIZE(x) ((x) << 1) /* log2 */
646 # define IH_RB_FULL_DRAIN_ENABLE (1 << 6)
647 # define IH_WPTR_WRITEBACK_ENABLE (1 << 8)
648 # define IH_WPTR_WRITEBACK_TIMER(x) ((x) << 9) /* log2 */
649 # define IH_WPTR_OVERFLOW_ENABLE (1 << 16)
650 # define IH_WPTR_OVERFLOW_CLEAR (1 << 31)
651 #define IH_RB_BASE 0x3e04
652 #define IH_RB_RPTR 0x3e08
653 #define IH_RB_WPTR 0x3e0c
654 # define RB_OVERFLOW (1 << 0)
655 # define WPTR_OFFSET_MASK 0x3fffc
656 #define IH_RB_WPTR_ADDR_HI 0x3e10
657 #define IH_RB_WPTR_ADDR_LO 0x3e14
658 #define IH_CNTL 0x3e18
659 # define ENABLE_INTR (1 << 0)
660 # define IH_MC_SWAP(x) ((x) << 1)
661 # define IH_MC_SWAP_NONE 0
662 # define IH_MC_SWAP_16BIT 1
663 # define IH_MC_SWAP_32BIT 2
664 # define IH_MC_SWAP_64BIT 3
665 # define RPTR_REARM (1 << 4)
666 # define MC_WRREQ_CREDIT(x) ((x) << 15)
667 # define MC_WR_CLEAN_CNT(x) ((x) << 20)
669 #define RLC_CNTL 0x3f00
670 # define RLC_ENABLE (1 << 0)
671 #define RLC_HB_BASE 0x3f10
672 #define RLC_HB_CNTL 0x3f0c
673 #define RLC_HB_RPTR 0x3f20
674 #define RLC_HB_WPTR 0x3f1c
675 #define RLC_HB_WPTR_LSB_ADDR 0x3f14
676 #define RLC_HB_WPTR_MSB_ADDR 0x3f18
677 #define RLC_GPU_CLOCK_COUNT_LSB 0x3f38
678 #define RLC_GPU_CLOCK_COUNT_MSB 0x3f3c
679 #define RLC_CAPTURE_GPU_CLOCK_COUNT 0x3f40
680 #define RLC_MC_CNTL 0x3f44
681 #define RLC_UCODE_CNTL 0x3f48
682 #define RLC_UCODE_ADDR 0x3f2c
683 #define RLC_UCODE_DATA 0x3f30
686 #define TN_RLC_SAVE_AND_RESTORE_BASE 0x3f10
687 #define TN_RLC_CLEAR_STATE_RESTORE_BASE 0x3f20
689 #define SRBM_SOFT_RESET 0xe60
690 # define SOFT_RESET_DMA (1 << 12)
691 # define SOFT_RESET_RLC (1 << 13)
692 # define RV770_SOFT_RESET_DMA (1 << 20)
694 #define CP_INT_CNTL 0xc124
695 # define CNTX_BUSY_INT_ENABLE (1 << 19)
696 # define CNTX_EMPTY_INT_ENABLE (1 << 20)
697 # define SCRATCH_INT_ENABLE (1 << 25)
698 # define TIME_STAMP_INT_ENABLE (1 << 26)
699 # define IB2_INT_ENABLE (1 << 29)
700 # define IB1_INT_ENABLE (1 << 30)
701 # define RB_INT_ENABLE (1 << 31)
702 #define CP_INT_STATUS 0xc128
703 # define SCRATCH_INT_STAT (1 << 25)
704 # define TIME_STAMP_INT_STAT (1 << 26)
705 # define IB2_INT_STAT (1 << 29)
706 # define IB1_INT_STAT (1 << 30)
707 # define RB_INT_STAT (1 << 31)
709 #define GRBM_INT_CNTL 0x8060
710 # define RDERR_INT_ENABLE (1 << 0)
711 # define WAIT_COUNT_TIMEOUT_INT_ENABLE (1 << 1)
712 # define GUI_IDLE_INT_ENABLE (1 << 19)
714 #define INTERRUPT_CNTL 0x5468
715 # define IH_DUMMY_RD_OVERRIDE (1 << 0)
716 # define IH_DUMMY_RD_EN (1 << 1)
717 # define IH_REQ_NONSNOOP_EN (1 << 3)
718 # define GEN_IH_INT_EN (1 << 8)
719 #define INTERRUPT_CNTL2 0x546c
721 #define D1MODE_VBLANK_STATUS 0x6534
722 #define D2MODE_VBLANK_STATUS 0x6d34
723 # define DxMODE_VBLANK_OCCURRED (1 << 0)
724 # define DxMODE_VBLANK_ACK (1 << 4)
725 # define DxMODE_VBLANK_STAT (1 << 12)
726 # define DxMODE_VBLANK_INTERRUPT (1 << 16)
727 # define DxMODE_VBLANK_INTERRUPT_TYPE (1 << 17)
728 #define D1MODE_VLINE_STATUS 0x653c
729 #define D2MODE_VLINE_STATUS 0x6d3c
730 # define DxMODE_VLINE_OCCURRED (1 << 0)
731 # define DxMODE_VLINE_ACK (1 << 4)
732 # define DxMODE_VLINE_STAT (1 << 12)
733 # define DxMODE_VLINE_INTERRUPT (1 << 16)
734 # define DxMODE_VLINE_INTERRUPT_TYPE (1 << 17)
735 #define DxMODE_INT_MASK 0x6540
736 # define D1MODE_VBLANK_INT_MASK (1 << 0)
737 # define D1MODE_VLINE_INT_MASK (1 << 4)
738 # define D2MODE_VBLANK_INT_MASK (1 << 8)
739 # define D2MODE_VLINE_INT_MASK (1 << 12)
740 #define DCE3_DISP_INTERRUPT_STATUS 0x7ddc
741 # define DC_HPD1_INTERRUPT (1 << 18)
742 # define DC_HPD2_INTERRUPT (1 << 19)
743 #define DISP_INTERRUPT_STATUS 0x7edc
744 # define LB_D1_VLINE_INTERRUPT (1 << 2)
745 # define LB_D2_VLINE_INTERRUPT (1 << 3)
746 # define LB_D1_VBLANK_INTERRUPT (1 << 4)
747 # define LB_D2_VBLANK_INTERRUPT (1 << 5)
748 # define DACA_AUTODETECT_INTERRUPT (1 << 16)
749 # define DACB_AUTODETECT_INTERRUPT (1 << 17)
750 # define DC_HOT_PLUG_DETECT1_INTERRUPT (1 << 18)
751 # define DC_HOT_PLUG_DETECT2_INTERRUPT (1 << 19)
752 # define DC_I2C_SW_DONE_INTERRUPT (1 << 20)
753 # define DC_I2C_HW_DONE_INTERRUPT (1 << 21)
754 #define DISP_INTERRUPT_STATUS_CONTINUE 0x7ee8
755 #define DCE3_DISP_INTERRUPT_STATUS_CONTINUE 0x7de8
756 # define DC_HPD4_INTERRUPT (1 << 14)
757 # define DC_HPD4_RX_INTERRUPT (1 << 15)
758 # define DC_HPD3_INTERRUPT (1 << 28)
759 # define DC_HPD1_RX_INTERRUPT (1 << 29)
760 # define DC_HPD2_RX_INTERRUPT (1 << 30)
761 #define DCE3_DISP_INTERRUPT_STATUS_CONTINUE2 0x7dec
762 # define DC_HPD3_RX_INTERRUPT (1 << 0)
763 # define DIGA_DP_VID_STREAM_DISABLE_INTERRUPT (1 << 1)
764 # define DIGA_DP_STEER_FIFO_OVERFLOW_INTERRUPT (1 << 2)
765 # define DIGB_DP_VID_STREAM_DISABLE_INTERRUPT (1 << 3)
766 # define DIGB_DP_STEER_FIFO_OVERFLOW_INTERRUPT (1 << 4)
767 # define AUX1_SW_DONE_INTERRUPT (1 << 5)
768 # define AUX1_LS_DONE_INTERRUPT (1 << 6)
769 # define AUX2_SW_DONE_INTERRUPT (1 << 7)
770 # define AUX2_LS_DONE_INTERRUPT (1 << 8)
771 # define AUX3_SW_DONE_INTERRUPT (1 << 9)
772 # define AUX3_LS_DONE_INTERRUPT (1 << 10)
773 # define AUX4_SW_DONE_INTERRUPT (1 << 11)
774 # define AUX4_LS_DONE_INTERRUPT (1 << 12)
775 # define DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT (1 << 13)
776 # define DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT (1 << 14)
778 # define AUX5_SW_DONE_INTERRUPT (1 << 15)
779 # define AUX5_LS_DONE_INTERRUPT (1 << 16)
780 # define AUX6_SW_DONE_INTERRUPT (1 << 17)
781 # define AUX6_LS_DONE_INTERRUPT (1 << 18)
782 # define DC_HPD5_INTERRUPT (1 << 19)
783 # define DC_HPD5_RX_INTERRUPT (1 << 20)
784 # define DC_HPD6_INTERRUPT (1 << 21)
785 # define DC_HPD6_RX_INTERRUPT (1 << 22)
787 #define DACA_AUTO_DETECT_CONTROL 0x7828
788 #define DACB_AUTO_DETECT_CONTROL 0x7a28
789 #define DCE3_DACA_AUTO_DETECT_CONTROL 0x7028
790 #define DCE3_DACB_AUTO_DETECT_CONTROL 0x7128
791 # define DACx_AUTODETECT_MODE(x) ((x) << 0)
792 # define DACx_AUTODETECT_MODE_NONE 0
793 # define DACx_AUTODETECT_MODE_CONNECT 1
794 # define DACx_AUTODETECT_MODE_DISCONNECT 2
795 # define DACx_AUTODETECT_FRAME_TIME_COUNTER(x) ((x) << 8)
796 /* bit 18 = R/C, 17 = G/Y, 16 = B/Comp */
797 # define DACx_AUTODETECT_CHECK_MASK(x) ((x) << 16)
799 #define DCE3_DACA_AUTODETECT_INT_CONTROL 0x7038
800 #define DCE3_DACB_AUTODETECT_INT_CONTROL 0x7138
801 #define DACA_AUTODETECT_INT_CONTROL 0x7838
802 #define DACB_AUTODETECT_INT_CONTROL 0x7a38
803 # define DACx_AUTODETECT_ACK (1 << 0)
804 # define DACx_AUTODETECT_INT_ENABLE (1 << 16)
806 #define DC_HOT_PLUG_DETECT1_CONTROL 0x7d00
807 #define DC_HOT_PLUG_DETECT2_CONTROL 0x7d10
808 #define DC_HOT_PLUG_DETECT3_CONTROL 0x7d24
809 # define DC_HOT_PLUG_DETECTx_EN (1 << 0)
811 #define DC_HOT_PLUG_DETECT1_INT_STATUS 0x7d04
812 #define DC_HOT_PLUG_DETECT2_INT_STATUS 0x7d14
813 #define DC_HOT_PLUG_DETECT3_INT_STATUS 0x7d28
814 # define DC_HOT_PLUG_DETECTx_INT_STATUS (1 << 0)
815 # define DC_HOT_PLUG_DETECTx_SENSE (1 << 1)
818 #define DC_HPD1_INT_STATUS 0x7d00
819 #define DC_HPD2_INT_STATUS 0x7d0c
820 #define DC_HPD3_INT_STATUS 0x7d18
821 #define DC_HPD4_INT_STATUS 0x7d24
823 #define DC_HPD5_INT_STATUS 0x7dc0
824 #define DC_HPD6_INT_STATUS 0x7df4
825 # define DC_HPDx_INT_STATUS (1 << 0)
826 # define DC_HPDx_SENSE (1 << 1)
827 # define DC_HPDx_RX_INT_STATUS (1 << 8)
829 #define DC_HOT_PLUG_DETECT1_INT_CONTROL 0x7d08
830 #define DC_HOT_PLUG_DETECT2_INT_CONTROL 0x7d18
831 #define DC_HOT_PLUG_DETECT3_INT_CONTROL 0x7d2c
832 # define DC_HOT_PLUG_DETECTx_INT_ACK (1 << 0)
833 # define DC_HOT_PLUG_DETECTx_INT_POLARITY (1 << 8)
834 # define DC_HOT_PLUG_DETECTx_INT_EN (1 << 16)
836 #define DC_HPD1_INT_CONTROL 0x7d04
837 #define DC_HPD2_INT_CONTROL 0x7d10
838 #define DC_HPD3_INT_CONTROL 0x7d1c
839 #define DC_HPD4_INT_CONTROL 0x7d28
841 #define DC_HPD5_INT_CONTROL 0x7dc4
842 #define DC_HPD6_INT_CONTROL 0x7df8
843 # define DC_HPDx_INT_ACK (1 << 0)
844 # define DC_HPDx_INT_POLARITY (1 << 8)
845 # define DC_HPDx_INT_EN (1 << 16)
846 # define DC_HPDx_RX_INT_ACK (1 << 20)
847 # define DC_HPDx_RX_INT_EN (1 << 24)
850 #define DC_HPD1_CONTROL 0x7d08
851 #define DC_HPD2_CONTROL 0x7d14
852 #define DC_HPD3_CONTROL 0x7d20
853 #define DC_HPD4_CONTROL 0x7d2c
855 #define DC_HPD5_CONTROL 0x7dc8
856 #define DC_HPD6_CONTROL 0x7dfc
857 # define DC_HPDx_CONNECTION_TIMER(x) ((x) << 0)
858 # define DC_HPDx_RX_INT_TIMER(x) ((x) << 16)
860 # define DC_HPDx_EN (1 << 28)
862 #define D1GRPH_INTERRUPT_STATUS 0x6158
863 #define D2GRPH_INTERRUPT_STATUS 0x6958
864 # define DxGRPH_PFLIP_INT_OCCURRED (1 << 0)
865 # define DxGRPH_PFLIP_INT_CLEAR (1 << 8)
866 #define D1GRPH_INTERRUPT_CONTROL 0x615c
867 #define D2GRPH_INTERRUPT_CONTROL 0x695c
868 # define DxGRPH_PFLIP_INT_MASK (1 << 0)
869 # define DxGRPH_PFLIP_INT_TYPE (1 << 8)
871 /* PCIE link stuff */
872 #define PCIE_LC_TRAINING_CNTL 0xa1 /* PCIE_P */
873 # define LC_POINT_7_PLUS_EN (1 << 6)
874 #define PCIE_LC_LINK_WIDTH_CNTL 0xa2 /* PCIE_P */
875 # define LC_LINK_WIDTH_SHIFT 0
876 # define LC_LINK_WIDTH_MASK 0x7
877 # define LC_LINK_WIDTH_X0 0
878 # define LC_LINK_WIDTH_X1 1
879 # define LC_LINK_WIDTH_X2 2
880 # define LC_LINK_WIDTH_X4 3
881 # define LC_LINK_WIDTH_X8 4
882 # define LC_LINK_WIDTH_X16 6
883 # define LC_LINK_WIDTH_RD_SHIFT 4
884 # define LC_LINK_WIDTH_RD_MASK 0x70
885 # define LC_RECONFIG_ARC_MISSING_ESCAPE (1 << 7)
886 # define LC_RECONFIG_NOW (1 << 8)
887 # define LC_RENEGOTIATION_SUPPORT (1 << 9)
888 # define LC_RENEGOTIATE_EN (1 << 10)
889 # define LC_SHORT_RECONFIG_EN (1 << 11)
890 # define LC_UPCONFIGURE_SUPPORT (1 << 12)
891 # define LC_UPCONFIGURE_DIS (1 << 13)
892 #define PCIE_LC_SPEED_CNTL 0xa4 /* PCIE_P */
893 # define LC_GEN2_EN_STRAP (1 << 0)
894 # define LC_TARGET_LINK_SPEED_OVERRIDE_EN (1 << 1)
895 # define LC_FORCE_EN_HW_SPEED_CHANGE (1 << 5)
896 # define LC_FORCE_DIS_HW_SPEED_CHANGE (1 << 6)
897 # define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK (0x3 << 8)
898 # define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT 3
899 # define LC_CURRENT_DATA_RATE (1 << 11)
900 # define LC_VOLTAGE_TIMER_SEL_MASK (0xf << 14)
901 # define LC_CLR_FAILED_SPD_CHANGE_CNT (1 << 21)
902 # define LC_OTHER_SIDE_EVER_SENT_GEN2 (1 << 23)
903 # define LC_OTHER_SIDE_SUPPORTS_GEN2 (1 << 24)
904 #define MM_CFGREGS_CNTL 0x544c
905 # define MM_WR_TO_CFG_EN (1 << 3)
906 #define LINK_CNTL2 0x88 /* F0 */
907 # define TARGET_LINK_SPEED_MASK (0xf << 0)
908 # define SELECTABLE_DEEMPHASIS (1 << 6)
911 #define DCCG_AUDIO_DTO0_PHASE 0x0514
912 #define DCCG_AUDIO_DTO0_MODULE 0x0518
913 #define DCCG_AUDIO_DTO0_LOAD 0x051c
914 # define DTO_LOAD (1 << 31)
915 #define DCCG_AUDIO_DTO0_CNTL 0x0520
917 #define DCCG_AUDIO_DTO1_PHASE 0x0524
918 #define DCCG_AUDIO_DTO1_MODULE 0x0528
919 #define DCCG_AUDIO_DTO1_LOAD 0x052c
920 #define DCCG_AUDIO_DTO1_CNTL 0x0530
922 #define DCCG_AUDIO_DTO_SELECT 0x0534
925 #define TMDSA_CNTL 0x7880
926 # define TMDSA_HDMI_EN (1 << 2)
927 #define LVTMA_CNTL 0x7a80
928 # define LVTMA_HDMI_EN (1 << 2)
929 #define DDIA_CNTL 0x7200
930 # define DDIA_HDMI_EN (1 << 2)
931 #define DIG0_CNTL 0x75a0
932 # define DIG_MODE(x) (((x) & 7) << 8)
933 # define DIG_MODE_DP 0
934 # define DIG_MODE_LVDS 1
935 # define DIG_MODE_TMDS_DVI 2
936 # define DIG_MODE_TMDS_HDMI 3
937 # define DIG_MODE_SDVO 4
938 #define DIG1_CNTL 0x79a0
940 /* rs6xx/rs740 and r6xx share the same HDMI blocks, however, rs6xx has only one
941 * instance of the blocks while r6xx has 2. DCE 3.0 cards are slightly
942 * different due to the new DIG blocks, but also have 2 instances.
943 * DCE 3.0 HDMI blocks are part of each DIG encoder.
946 /* rs6xx/rs740/r6xx/dce3 */
947 #define HDMI0_CONTROL 0x7400
948 /* rs6xx/rs740/r6xx */
949 # define HDMI0_ENABLE (1 << 0)
950 # define HDMI0_STREAM(x) (((x) & 3) << 2)
951 # define HDMI0_STREAM_TMDSA 0
952 # define HDMI0_STREAM_LVTMA 1
953 # define HDMI0_STREAM_DVOA 2
954 # define HDMI0_STREAM_DDIA 3
955 /* rs6xx/r6xx/dce3 */
956 # define HDMI0_ERROR_ACK (1 << 8)
957 # define HDMI0_ERROR_MASK (1 << 9)
958 #define HDMI0_STATUS 0x7404
959 # define HDMI0_ACTIVE_AVMUTE (1 << 0)
960 # define HDMI0_AUDIO_ENABLE (1 << 4)
961 # define HDMI0_AZ_FORMAT_WTRIG (1 << 28)
962 # define HDMI0_AZ_FORMAT_WTRIG_INT (1 << 29)
963 #define HDMI0_AUDIO_PACKET_CONTROL 0x7408
964 # define HDMI0_AUDIO_SAMPLE_SEND (1 << 0)
965 # define HDMI0_AUDIO_DELAY_EN(x) (((x) & 3) << 4)
966 # define HDMI0_AUDIO_SEND_MAX_PACKETS (1 << 8)
967 # define HDMI0_AUDIO_TEST_EN (1 << 12)
968 # define HDMI0_AUDIO_PACKETS_PER_LINE(x) (((x) & 0x1f) << 16)
969 # define HDMI0_AUDIO_CHANNEL_SWAP (1 << 24)
970 # define HDMI0_60958_CS_UPDATE (1 << 26)
971 # define HDMI0_AZ_FORMAT_WTRIG_MASK (1 << 28)
972 # define HDMI0_AZ_FORMAT_WTRIG_ACK (1 << 29)
973 #define HDMI0_AUDIO_CRC_CONTROL 0x740c
974 # define HDMI0_AUDIO_CRC_EN (1 << 0)
975 #define HDMI0_VBI_PACKET_CONTROL 0x7410
976 # define HDMI0_NULL_SEND (1 << 0)
977 # define HDMI0_GC_SEND (1 << 4)
978 # define HDMI0_GC_CONT (1 << 5) /* 0 - once; 1 - every frame */
979 #define HDMI0_INFOFRAME_CONTROL0 0x7414
980 # define HDMI0_AVI_INFO_SEND (1 << 0)
981 # define HDMI0_AVI_INFO_CONT (1 << 1)
982 # define HDMI0_AUDIO_INFO_SEND (1 << 4)
983 # define HDMI0_AUDIO_INFO_CONT (1 << 5)
984 # define HDMI0_AUDIO_INFO_SOURCE (1 << 6) /* 0 - sound block; 1 - hmdi regs */
985 # define HDMI0_AUDIO_INFO_UPDATE (1 << 7)
986 # define HDMI0_MPEG_INFO_SEND (1 << 8)
987 # define HDMI0_MPEG_INFO_CONT (1 << 9)
988 # define HDMI0_MPEG_INFO_UPDATE (1 << 10)
989 #define HDMI0_INFOFRAME_CONTROL1 0x7418
990 # define HDMI0_AVI_INFO_LINE(x) (((x) & 0x3f) << 0)
991 # define HDMI0_AUDIO_INFO_LINE(x) (((x) & 0x3f) << 8)
992 # define HDMI0_MPEG_INFO_LINE(x) (((x) & 0x3f) << 16)
993 #define HDMI0_GENERIC_PACKET_CONTROL 0x741c
994 # define HDMI0_GENERIC0_SEND (1 << 0)
995 # define HDMI0_GENERIC0_CONT (1 << 1)
996 # define HDMI0_GENERIC0_UPDATE (1 << 2)
997 # define HDMI0_GENERIC1_SEND (1 << 4)
998 # define HDMI0_GENERIC1_CONT (1 << 5)
999 # define HDMI0_GENERIC0_LINE(x) (((x) & 0x3f) << 16)
1000 # define HDMI0_GENERIC1_LINE(x) (((x) & 0x3f) << 24)
1001 #define HDMI0_GC 0x7428
1002 # define HDMI0_GC_AVMUTE (1 << 0)
1003 #define HDMI0_AVI_INFO0 0x7454
1004 # define HDMI0_AVI_INFO_CHECKSUM(x) (((x) & 0xff) << 0)
1005 # define HDMI0_AVI_INFO_S(x) (((x) & 3) << 8)
1006 # define HDMI0_AVI_INFO_B(x) (((x) & 3) << 10)
1007 # define HDMI0_AVI_INFO_A(x) (((x) & 1) << 12)
1008 # define HDMI0_AVI_INFO_Y(x) (((x) & 3) << 13)
1009 # define HDMI0_AVI_INFO_Y_RGB 0
1010 # define HDMI0_AVI_INFO_Y_YCBCR422 1
1011 # define HDMI0_AVI_INFO_Y_YCBCR444 2
1012 # define HDMI0_AVI_INFO_Y_A_B_S(x) (((x) & 0xff) << 8)
1013 # define HDMI0_AVI_INFO_R(x) (((x) & 0xf) << 16)
1014 # define HDMI0_AVI_INFO_M(x) (((x) & 0x3) << 20)
1015 # define HDMI0_AVI_INFO_C(x) (((x) & 0x3) << 22)
1016 # define HDMI0_AVI_INFO_C_M_R(x) (((x) & 0xff) << 16)
1017 # define HDMI0_AVI_INFO_SC(x) (((x) & 0x3) << 24)
1018 # define HDMI0_AVI_INFO_ITC_EC_Q_SC(x) (((x) & 0xff) << 24)
1019 #define HDMI0_AVI_INFO1 0x7458
1020 # define HDMI0_AVI_INFO_VIC(x) (((x) & 0x7f) << 0) /* don't use avi infoframe v1 */
1021 # define HDMI0_AVI_INFO_PR(x) (((x) & 0xf) << 8) /* don't use avi infoframe v1 */
1022 # define HDMI0_AVI_INFO_TOP(x) (((x) & 0xffff) << 16)
1023 #define HDMI0_AVI_INFO2 0x745c
1024 # define HDMI0_AVI_INFO_BOTTOM(x) (((x) & 0xffff) << 0)
1025 # define HDMI0_AVI_INFO_LEFT(x) (((x) & 0xffff) << 16)
1026 #define HDMI0_AVI_INFO3 0x7460
1027 # define HDMI0_AVI_INFO_RIGHT(x) (((x) & 0xffff) << 0)
1028 # define HDMI0_AVI_INFO_VERSION(x) (((x) & 3) << 24)
1029 #define HDMI0_MPEG_INFO0 0x7464
1030 # define HDMI0_MPEG_INFO_CHECKSUM(x) (((x) & 0xff) << 0)
1031 # define HDMI0_MPEG_INFO_MB0(x) (((x) & 0xff) << 8)
1032 # define HDMI0_MPEG_INFO_MB1(x) (((x) & 0xff) << 16)
1033 # define HDMI0_MPEG_INFO_MB2(x) (((x) & 0xff) << 24)
1034 #define HDMI0_MPEG_INFO1 0x7468
1035 # define HDMI0_MPEG_INFO_MB3(x) (((x) & 0xff) << 0)
1036 # define HDMI0_MPEG_INFO_MF(x) (((x) & 3) << 8)
1037 # define HDMI0_MPEG_INFO_FR(x) (((x) & 1) << 12)
1038 #define HDMI0_GENERIC0_HDR 0x746c
1039 #define HDMI0_GENERIC0_0 0x7470
1040 #define HDMI0_GENERIC0_1 0x7474
1041 #define HDMI0_GENERIC0_2 0x7478
1042 #define HDMI0_GENERIC0_3 0x747c
1043 #define HDMI0_GENERIC0_4 0x7480
1044 #define HDMI0_GENERIC0_5 0x7484
1045 #define HDMI0_GENERIC0_6 0x7488
1046 #define HDMI0_GENERIC1_HDR 0x748c
1047 #define HDMI0_GENERIC1_0 0x7490
1048 #define HDMI0_GENERIC1_1 0x7494
1049 #define HDMI0_GENERIC1_2 0x7498
1050 #define HDMI0_GENERIC1_3 0x749c
1051 #define HDMI0_GENERIC1_4 0x74a0
1052 #define HDMI0_GENERIC1_5 0x74a4
1053 #define HDMI0_GENERIC1_6 0x74a8
1054 #define HDMI0_ACR_32_0 0x74ac
1055 # define HDMI0_ACR_CTS_32(x) (((x) & 0xfffff) << 12)
1056 #define HDMI0_ACR_32_1 0x74b0
1057 # define HDMI0_ACR_N_32(x) (((x) & 0xfffff) << 0)
1058 #define HDMI0_ACR_44_0 0x74b4
1059 # define HDMI0_ACR_CTS_44(x) (((x) & 0xfffff) << 12)
1060 #define HDMI0_ACR_44_1 0x74b8
1061 # define HDMI0_ACR_N_44(x) (((x) & 0xfffff) << 0)
1062 #define HDMI0_ACR_48_0 0x74bc
1063 # define HDMI0_ACR_CTS_48(x) (((x) & 0xfffff) << 12)
1064 #define HDMI0_ACR_48_1 0x74c0
1065 # define HDMI0_ACR_N_48(x) (((x) & 0xfffff) << 0)
1066 #define HDMI0_ACR_STATUS_0 0x74c4
1067 #define HDMI0_ACR_STATUS_1 0x74c8
1068 #define HDMI0_AUDIO_INFO0 0x74cc
1069 # define HDMI0_AUDIO_INFO_CHECKSUM(x) (((x) & 0xff) << 0)
1070 # define HDMI0_AUDIO_INFO_CC(x) (((x) & 7) << 8)
1071 #define HDMI0_AUDIO_INFO1 0x74d0
1072 # define HDMI0_AUDIO_INFO_CA(x) (((x) & 0xff) << 0)
1073 # define HDMI0_AUDIO_INFO_LSV(x) (((x) & 0xf) << 11)
1074 # define HDMI0_AUDIO_INFO_DM_INH(x) (((x) & 1) << 15)
1075 # define HDMI0_AUDIO_INFO_DM_INH_LSV(x) (((x) & 0xff) << 8)
1076 #define HDMI0_60958_0 0x74d4
1077 # define HDMI0_60958_CS_A(x) (((x) & 1) << 0)
1078 # define HDMI0_60958_CS_B(x) (((x) & 1) << 1)
1079 # define HDMI0_60958_CS_C(x) (((x) & 1) << 2)
1080 # define HDMI0_60958_CS_D(x) (((x) & 3) << 3)
1081 # define HDMI0_60958_CS_MODE(x) (((x) & 3) << 6)
1082 # define HDMI0_60958_CS_CATEGORY_CODE(x) (((x) & 0xff) << 8)
1083 # define HDMI0_60958_CS_SOURCE_NUMBER(x) (((x) & 0xf) << 16)
1084 # define HDMI0_60958_CS_CHANNEL_NUMBER_L(x) (((x) & 0xf) << 20)
1085 # define HDMI0_60958_CS_SAMPLING_FREQUENCY(x) (((x) & 0xf) << 24)
1086 # define HDMI0_60958_CS_CLOCK_ACCURACY(x) (((x) & 3) << 28)
1087 #define HDMI0_60958_1 0x74d8
1088 # define HDMI0_60958_CS_WORD_LENGTH(x) (((x) & 0xf) << 0)
1089 # define HDMI0_60958_CS_ORIGINAL_SAMPLING_FREQUENCY(x) (((x) & 0xf) << 4)
1090 # define HDMI0_60958_CS_VALID_L(x) (((x) & 1) << 16)
1091 # define HDMI0_60958_CS_VALID_R(x) (((x) & 1) << 18)
1092 # define HDMI0_60958_CS_CHANNEL_NUMBER_R(x) (((x) & 0xf) << 20)
1093 #define HDMI0_ACR_PACKET_CONTROL 0x74dc
1094 # define HDMI0_ACR_SEND (1 << 0)
1095 # define HDMI0_ACR_CONT (1 << 1)
1096 # define HDMI0_ACR_SELECT(x) (((x) & 3) << 4)
1097 # define HDMI0_ACR_HW 0
1098 # define HDMI0_ACR_32 1
1099 # define HDMI0_ACR_44 2
1100 # define HDMI0_ACR_48 3
1101 # define HDMI0_ACR_SOURCE (1 << 8) /* 0 - hw; 1 - cts value */
1102 # define HDMI0_ACR_AUTO_SEND (1 << 12)
1103 #define HDMI0_RAMP_CONTROL0 0x74e0
1104 # define HDMI0_RAMP_MAX_COUNT(x) (((x) & 0xffffff) << 0)
1105 #define HDMI0_RAMP_CONTROL1 0x74e4
1106 # define HDMI0_RAMP_MIN_COUNT(x) (((x) & 0xffffff) << 0)
1107 #define HDMI0_RAMP_CONTROL2 0x74e8
1108 # define HDMI0_RAMP_INC_COUNT(x) (((x) & 0xffffff) << 0)
1109 #define HDMI0_RAMP_CONTROL3 0x74ec
1110 # define HDMI0_RAMP_DEC_COUNT(x) (((x) & 0xffffff) << 0)
1111 /* HDMI0_60958_2 is r7xx only */
1112 #define HDMI0_60958_2 0x74f0
1113 # define HDMI0_60958_CS_CHANNEL_NUMBER_2(x) (((x) & 0xf) << 0)
1114 # define HDMI0_60958_CS_CHANNEL_NUMBER_3(x) (((x) & 0xf) << 4)
1115 # define HDMI0_60958_CS_CHANNEL_NUMBER_4(x) (((x) & 0xf) << 8)
1116 # define HDMI0_60958_CS_CHANNEL_NUMBER_5(x) (((x) & 0xf) << 12)
1117 # define HDMI0_60958_CS_CHANNEL_NUMBER_6(x) (((x) & 0xf) << 16)
1118 # define HDMI0_60958_CS_CHANNEL_NUMBER_7(x) (((x) & 0xf) << 20)
1119 /* r6xx only; second instance starts at 0x7700 */
1120 #define HDMI1_CONTROL 0x7700
1121 #define HDMI1_STATUS 0x7704
1122 #define HDMI1_AUDIO_PACKET_CONTROL 0x7708
1123 /* DCE3; second instance starts at 0x7800 NOT 0x7700 */
1124 #define DCE3_HDMI1_CONTROL 0x7800
1125 #define DCE3_HDMI1_STATUS 0x7804
1126 #define DCE3_HDMI1_AUDIO_PACKET_CONTROL 0x7808
1127 /* DCE3.2 (for interrupts) */
1128 #define AFMT_STATUS 0x7600
1129 # define AFMT_AUDIO_ENABLE (1 << 4)
1130 # define AFMT_AZ_FORMAT_WTRIG (1 << 28)
1131 # define AFMT_AZ_FORMAT_WTRIG_INT (1 << 29)
1132 # define AFMT_AZ_AUDIO_ENABLE_CHG (1 << 30)
1133 #define AFMT_AUDIO_PACKET_CONTROL 0x7604
1134 # define AFMT_AUDIO_SAMPLE_SEND (1 << 0)
1135 # define AFMT_AUDIO_TEST_EN (1 << 12)
1136 # define AFMT_AUDIO_CHANNEL_SWAP (1 << 24)
1137 # define AFMT_60958_CS_UPDATE (1 << 26)
1138 # define AFMT_AZ_AUDIO_ENABLE_CHG_MASK (1 << 27)
1139 # define AFMT_AZ_FORMAT_WTRIG_MASK (1 << 28)
1140 # define AFMT_AZ_FORMAT_WTRIG_ACK (1 << 29)
1141 # define AFMT_AZ_AUDIO_ENABLE_CHG_ACK (1 << 30)
1146 #define PACKET_TYPE0 0
1147 #define PACKET_TYPE1 1
1148 #define PACKET_TYPE2 2
1149 #define PACKET_TYPE3 3
1151 #define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3)
1152 #define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF)
1153 #define CP_PACKET0_GET_REG(h) (((h) & 0xFFFF) << 2)
1154 #define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF)
1155 #define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \
1156 (((reg) >> 2) & 0xFFFF) | \
1157 ((n) & 0x3FFF) << 16)
1158 #define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \
1159 (((op) & 0xFF) << 8) | \
1160 ((n) & 0x3FFF) << 16)
1162 /* Packet 3 types */
1163 #define PACKET3_NOP 0x10
1164 #define PACKET3_INDIRECT_BUFFER_END 0x17
1165 #define PACKET3_SET_PREDICATION 0x20
1166 #define PACKET3_REG_RMW 0x21
1167 #define PACKET3_COND_EXEC 0x22
1168 #define PACKET3_PRED_EXEC 0x23
1169 #define PACKET3_START_3D_CMDBUF 0x24
1170 #define PACKET3_DRAW_INDEX_2 0x27
1171 #define PACKET3_CONTEXT_CONTROL 0x28
1172 #define PACKET3_DRAW_INDEX_IMMD_BE 0x29
1173 #define PACKET3_INDEX_TYPE 0x2A
1174 #define PACKET3_DRAW_INDEX 0x2B
1175 #define PACKET3_DRAW_INDEX_AUTO 0x2D
1176 #define PACKET3_DRAW_INDEX_IMMD 0x2E
1177 #define PACKET3_NUM_INSTANCES 0x2F
1178 #define PACKET3_STRMOUT_BUFFER_UPDATE 0x34
1179 #define PACKET3_INDIRECT_BUFFER_MP 0x38
1180 #define PACKET3_MEM_SEMAPHORE 0x39
1181 # define PACKET3_SEM_WAIT_ON_SIGNAL (0x1 << 12)
1182 # define PACKET3_SEM_SEL_SIGNAL (0x6 << 29)
1183 # define PACKET3_SEM_SEL_WAIT (0x7 << 29)
1184 #define PACKET3_MPEG_INDEX 0x3A
1185 #define PACKET3_COPY_DW 0x3B
1186 #define PACKET3_WAIT_REG_MEM 0x3C
1187 #define PACKET3_MEM_WRITE 0x3D
1188 #define PACKET3_INDIRECT_BUFFER 0x32
1189 #define PACKET3_CP_DMA 0x41
1191 * 2. SRC_ADDR_LO [31:0]
1192 * 3. CP_SYNC [31] | SRC_ADDR_HI [7:0]
1193 * 4. DST_ADDR_LO [31:0]
1194 * 5. DST_ADDR_HI [7:0]
1195 * 6. COMMAND [29:22] | BYTE_COUNT [20:0]
1197 # define PACKET3_CP_DMA_CP_SYNC (1 << 31)
1199 # define PACKET3_CP_DMA_CMD_SRC_SWAP(x) ((x) << 23)
1205 # define PACKET3_CP_DMA_CMD_DST_SWAP(x) ((x) << 24)
1211 # define PACKET3_CP_DMA_CMD_SAS (1 << 26)
1215 # define PACKET3_CP_DMA_CMD_DAS (1 << 27)
1219 # define PACKET3_CP_DMA_CMD_SAIC (1 << 28)
1220 # define PACKET3_CP_DMA_CMD_DAIC (1 << 29)
1221 #define PACKET3_SURFACE_SYNC 0x43
1222 # define PACKET3_CB0_DEST_BASE_ENA (1 << 6)
1223 # define PACKET3_TC_ACTION_ENA (1 << 23)
1224 # define PACKET3_VC_ACTION_ENA (1 << 24)
1225 # define PACKET3_CB_ACTION_ENA (1 << 25)
1226 # define PACKET3_DB_ACTION_ENA (1 << 26)
1227 # define PACKET3_SH_ACTION_ENA (1 << 27)
1228 # define PACKET3_SMX_ACTION_ENA (1 << 28)
1229 #define PACKET3_ME_INITIALIZE 0x44
1230 #define PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16)
1231 #define PACKET3_COND_WRITE 0x45
1232 #define PACKET3_EVENT_WRITE 0x46
1233 #define EVENT_TYPE(x) ((x) << 0)
1234 #define EVENT_INDEX(x) ((x) << 8)
1235 /* 0 - any non-TS event
1237 * 2 - SAMPLE_PIPELINESTAT
1238 * 3 - SAMPLE_STREAMOUTSTAT*
1239 * 4 - *S_PARTIAL_FLUSH
1242 #define PACKET3_EVENT_WRITE_EOP 0x47
1243 #define DATA_SEL(x) ((x) << 29)
1245 * 1 - send low 32bit data
1246 * 2 - send 64bit data
1247 * 3 - send 64bit counter value
1249 #define INT_SEL(x) ((x) << 24)
1251 * 1 - interrupt only (DATA_SEL = 0)
1252 * 2 - interrupt when data write is confirmed
1254 #define PACKET3_ONE_REG_WRITE 0x57
1255 #define PACKET3_SET_CONFIG_REG 0x68
1256 #define PACKET3_SET_CONFIG_REG_OFFSET 0x00008000
1257 #define PACKET3_SET_CONFIG_REG_END 0x0000ac00
1258 #define PACKET3_SET_CONTEXT_REG 0x69
1259 #define PACKET3_SET_CONTEXT_REG_OFFSET 0x00028000
1260 #define PACKET3_SET_CONTEXT_REG_END 0x00029000
1261 #define PACKET3_SET_ALU_CONST 0x6A
1262 #define PACKET3_SET_ALU_CONST_OFFSET 0x00030000
1263 #define PACKET3_SET_ALU_CONST_END 0x00032000
1264 #define PACKET3_SET_BOOL_CONST 0x6B
1265 #define PACKET3_SET_BOOL_CONST_OFFSET 0x0003e380
1266 #define PACKET3_SET_BOOL_CONST_END 0x00040000
1267 #define PACKET3_SET_LOOP_CONST 0x6C
1268 #define PACKET3_SET_LOOP_CONST_OFFSET 0x0003e200
1269 #define PACKET3_SET_LOOP_CONST_END 0x0003e380
1270 #define PACKET3_SET_RESOURCE 0x6D
1271 #define PACKET3_SET_RESOURCE_OFFSET 0x00038000
1272 #define PACKET3_SET_RESOURCE_END 0x0003c000
1273 #define PACKET3_SET_SAMPLER 0x6E
1274 #define PACKET3_SET_SAMPLER_OFFSET 0x0003c000
1275 #define PACKET3_SET_SAMPLER_END 0x0003cff0
1276 #define PACKET3_SET_CTL_CONST 0x6F
1277 #define PACKET3_SET_CTL_CONST_OFFSET 0x0003cff0
1278 #define PACKET3_SET_CTL_CONST_END 0x0003e200
1279 #define PACKET3_STRMOUT_BASE_UPDATE 0x72 /* r7xx */
1280 #define PACKET3_SURFACE_BASE_UPDATE 0x73
1283 #define R_008020_GRBM_SOFT_RESET 0x8020
1284 #define S_008020_SOFT_RESET_CP(x) (((x) & 1) << 0)
1285 #define S_008020_SOFT_RESET_CB(x) (((x) & 1) << 1)
1286 #define S_008020_SOFT_RESET_CR(x) (((x) & 1) << 2)
1287 #define S_008020_SOFT_RESET_DB(x) (((x) & 1) << 3)
1288 #define S_008020_SOFT_RESET_PA(x) (((x) & 1) << 5)
1289 #define S_008020_SOFT_RESET_SC(x) (((x) & 1) << 6)
1290 #define S_008020_SOFT_RESET_SMX(x) (((x) & 1) << 7)
1291 #define S_008020_SOFT_RESET_SPI(x) (((x) & 1) << 8)
1292 #define S_008020_SOFT_RESET_SH(x) (((x) & 1) << 9)
1293 #define S_008020_SOFT_RESET_SX(x) (((x) & 1) << 10)
1294 #define S_008020_SOFT_RESET_TC(x) (((x) & 1) << 11)
1295 #define S_008020_SOFT_RESET_TA(x) (((x) & 1) << 12)
1296 #define S_008020_SOFT_RESET_VC(x) (((x) & 1) << 13)
1297 #define S_008020_SOFT_RESET_VGT(x) (((x) & 1) << 14)
1298 #define R_008010_GRBM_STATUS 0x8010
1299 #define S_008010_CMDFIFO_AVAIL(x) (((x) & 0x1F) << 0)
1300 #define S_008010_CP_RQ_PENDING(x) (((x) & 1) << 6)
1301 #define S_008010_CF_RQ_PENDING(x) (((x) & 1) << 7)
1302 #define S_008010_PF_RQ_PENDING(x) (((x) & 1) << 8)
1303 #define S_008010_GRBM_EE_BUSY(x) (((x) & 1) << 10)
1304 #define S_008010_VC_BUSY(x) (((x) & 1) << 11)
1305 #define S_008010_DB03_CLEAN(x) (((x) & 1) << 12)
1306 #define S_008010_CB03_CLEAN(x) (((x) & 1) << 13)
1307 #define S_008010_VGT_BUSY_NO_DMA(x) (((x) & 1) << 16)
1308 #define S_008010_VGT_BUSY(x) (((x) & 1) << 17)
1309 #define S_008010_TA03_BUSY(x) (((x) & 1) << 18)
1310 #define S_008010_TC_BUSY(x) (((x) & 1) << 19)
1311 #define S_008010_SX_BUSY(x) (((x) & 1) << 20)
1312 #define S_008010_SH_BUSY(x) (((x) & 1) << 21)
1313 #define S_008010_SPI03_BUSY(x) (((x) & 1) << 22)
1314 #define S_008010_SMX_BUSY(x) (((x) & 1) << 23)
1315 #define S_008010_SC_BUSY(x) (((x) & 1) << 24)
1316 #define S_008010_PA_BUSY(x) (((x) & 1) << 25)
1317 #define S_008010_DB03_BUSY(x) (((x) & 1) << 26)
1318 #define S_008010_CR_BUSY(x) (((x) & 1) << 27)
1319 #define S_008010_CP_COHERENCY_BUSY(x) (((x) & 1) << 28)
1320 #define S_008010_CP_BUSY(x) (((x) & 1) << 29)
1321 #define S_008010_CB03_BUSY(x) (((x) & 1) << 30)
1322 #define S_008010_GUI_ACTIVE(x) (((x) & 1) << 31)
1323 #define G_008010_CMDFIFO_AVAIL(x) (((x) >> 0) & 0x1F)
1324 #define G_008010_CP_RQ_PENDING(x) (((x) >> 6) & 1)
1325 #define G_008010_CF_RQ_PENDING(x) (((x) >> 7) & 1)
1326 #define G_008010_PF_RQ_PENDING(x) (((x) >> 8) & 1)
1327 #define G_008010_GRBM_EE_BUSY(x) (((x) >> 10) & 1)
1328 #define G_008010_VC_BUSY(x) (((x) >> 11) & 1)
1329 #define G_008010_DB03_CLEAN(x) (((x) >> 12) & 1)
1330 #define G_008010_CB03_CLEAN(x) (((x) >> 13) & 1)
1331 #define G_008010_VGT_BUSY_NO_DMA(x) (((x) >> 16) & 1)
1332 #define G_008010_VGT_BUSY(x) (((x) >> 17) & 1)
1333 #define G_008010_TA03_BUSY(x) (((x) >> 18) & 1)
1334 #define G_008010_TC_BUSY(x) (((x) >> 19) & 1)
1335 #define G_008010_SX_BUSY(x) (((x) >> 20) & 1)
1336 #define G_008010_SH_BUSY(x) (((x) >> 21) & 1)
1337 #define G_008010_SPI03_BUSY(x) (((x) >> 22) & 1)
1338 #define G_008010_SMX_BUSY(x) (((x) >> 23) & 1)
1339 #define G_008010_SC_BUSY(x) (((x) >> 24) & 1)
1340 #define G_008010_PA_BUSY(x) (((x) >> 25) & 1)
1341 #define G_008010_DB03_BUSY(x) (((x) >> 26) & 1)
1342 #define G_008010_CR_BUSY(x) (((x) >> 27) & 1)
1343 #define G_008010_CP_COHERENCY_BUSY(x) (((x) >> 28) & 1)
1344 #define G_008010_CP_BUSY(x) (((x) >> 29) & 1)
1345 #define G_008010_CB03_BUSY(x) (((x) >> 30) & 1)
1346 #define G_008010_GUI_ACTIVE(x) (((x) >> 31) & 1)
1347 #define R_008014_GRBM_STATUS2 0x8014
1348 #define S_008014_CR_CLEAN(x) (((x) & 1) << 0)
1349 #define S_008014_SMX_CLEAN(x) (((x) & 1) << 1)
1350 #define S_008014_SPI0_BUSY(x) (((x) & 1) << 8)
1351 #define S_008014_SPI1_BUSY(x) (((x) & 1) << 9)
1352 #define S_008014_SPI2_BUSY(x) (((x) & 1) << 10)
1353 #define S_008014_SPI3_BUSY(x) (((x) & 1) << 11)
1354 #define S_008014_TA0_BUSY(x) (((x) & 1) << 12)
1355 #define S_008014_TA1_BUSY(x) (((x) & 1) << 13)
1356 #define S_008014_TA2_BUSY(x) (((x) & 1) << 14)
1357 #define S_008014_TA3_BUSY(x) (((x) & 1) << 15)
1358 #define S_008014_DB0_BUSY(x) (((x) & 1) << 16)
1359 #define S_008014_DB1_BUSY(x) (((x) & 1) << 17)
1360 #define S_008014_DB2_BUSY(x) (((x) & 1) << 18)
1361 #define S_008014_DB3_BUSY(x) (((x) & 1) << 19)
1362 #define S_008014_CB0_BUSY(x) (((x) & 1) << 20)
1363 #define S_008014_CB1_BUSY(x) (((x) & 1) << 21)
1364 #define S_008014_CB2_BUSY(x) (((x) & 1) << 22)
1365 #define S_008014_CB3_BUSY(x) (((x) & 1) << 23)
1366 #define G_008014_CR_CLEAN(x) (((x) >> 0) & 1)
1367 #define G_008014_SMX_CLEAN(x) (((x) >> 1) & 1)
1368 #define G_008014_SPI0_BUSY(x) (((x) >> 8) & 1)
1369 #define G_008014_SPI1_BUSY(x) (((x) >> 9) & 1)
1370 #define G_008014_SPI2_BUSY(x) (((x) >> 10) & 1)
1371 #define G_008014_SPI3_BUSY(x) (((x) >> 11) & 1)
1372 #define G_008014_TA0_BUSY(x) (((x) >> 12) & 1)
1373 #define G_008014_TA1_BUSY(x) (((x) >> 13) & 1)
1374 #define G_008014_TA2_BUSY(x) (((x) >> 14) & 1)
1375 #define G_008014_TA3_BUSY(x) (((x) >> 15) & 1)
1376 #define G_008014_DB0_BUSY(x) (((x) >> 16) & 1)
1377 #define G_008014_DB1_BUSY(x) (((x) >> 17) & 1)
1378 #define G_008014_DB2_BUSY(x) (((x) >> 18) & 1)
1379 #define G_008014_DB3_BUSY(x) (((x) >> 19) & 1)
1380 #define G_008014_CB0_BUSY(x) (((x) >> 20) & 1)
1381 #define G_008014_CB1_BUSY(x) (((x) >> 21) & 1)
1382 #define G_008014_CB2_BUSY(x) (((x) >> 22) & 1)
1383 #define G_008014_CB3_BUSY(x) (((x) >> 23) & 1)
1384 #define R_000E50_SRBM_STATUS 0x0E50
1385 #define G_000E50_RLC_RQ_PENDING(x) (((x) >> 3) & 1)
1386 #define G_000E50_RCU_RQ_PENDING(x) (((x) >> 4) & 1)
1387 #define G_000E50_GRBM_RQ_PENDING(x) (((x) >> 5) & 1)
1388 #define G_000E50_HI_RQ_PENDING(x) (((x) >> 6) & 1)
1389 #define G_000E50_IO_EXTERN_SIGNAL(x) (((x) >> 7) & 1)
1390 #define G_000E50_VMC_BUSY(x) (((x) >> 8) & 1)
1391 #define G_000E50_MCB_BUSY(x) (((x) >> 9) & 1)
1392 #define G_000E50_MCDZ_BUSY(x) (((x) >> 10) & 1)
1393 #define G_000E50_MCDY_BUSY(x) (((x) >> 11) & 1)
1394 #define G_000E50_MCDX_BUSY(x) (((x) >> 12) & 1)
1395 #define G_000E50_MCDW_BUSY(x) (((x) >> 13) & 1)
1396 #define G_000E50_SEM_BUSY(x) (((x) >> 14) & 1)
1397 #define G_000E50_RLC_BUSY(x) (((x) >> 15) & 1)
1398 #define G_000E50_BIF_BUSY(x) (((x) >> 29) & 1)
1399 #define R_000E60_SRBM_SOFT_RESET 0x0E60
1400 #define S_000E60_SOFT_RESET_BIF(x) (((x) & 1) << 1)
1401 #define S_000E60_SOFT_RESET_CG(x) (((x) & 1) << 2)
1402 #define S_000E60_SOFT_RESET_CMC(x) (((x) & 1) << 3)
1403 #define S_000E60_SOFT_RESET_CSC(x) (((x) & 1) << 4)
1404 #define S_000E60_SOFT_RESET_DC(x) (((x) & 1) << 5)
1405 #define S_000E60_SOFT_RESET_GRBM(x) (((x) & 1) << 8)
1406 #define S_000E60_SOFT_RESET_HDP(x) (((x) & 1) << 9)
1407 #define S_000E60_SOFT_RESET_IH(x) (((x) & 1) << 10)
1408 #define S_000E60_SOFT_RESET_MC(x) (((x) & 1) << 11)
1409 #define S_000E60_SOFT_RESET_RLC(x) (((x) & 1) << 13)
1410 #define S_000E60_SOFT_RESET_ROM(x) (((x) & 1) << 14)
1411 #define S_000E60_SOFT_RESET_SEM(x) (((x) & 1) << 15)
1412 #define S_000E60_SOFT_RESET_TSC(x) (((x) & 1) << 16)
1413 #define S_000E60_SOFT_RESET_VMC(x) (((x) & 1) << 17)
1415 #define R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL 0x5480
1417 #define R_028C04_PA_SC_AA_CONFIG 0x028C04
1418 #define S_028C04_MSAA_NUM_SAMPLES(x) (((x) & 0x3) << 0)
1419 #define G_028C04_MSAA_NUM_SAMPLES(x) (((x) >> 0) & 0x3)
1420 #define C_028C04_MSAA_NUM_SAMPLES 0xFFFFFFFC
1421 #define S_028C04_AA_MASK_CENTROID_DTMN(x) (((x) & 0x1) << 4)
1422 #define G_028C04_AA_MASK_CENTROID_DTMN(x) (((x) >> 4) & 0x1)
1423 #define C_028C04_AA_MASK_CENTROID_DTMN 0xFFFFFFEF
1424 #define S_028C04_MAX_SAMPLE_DIST(x) (((x) & 0xF) << 13)
1425 #define G_028C04_MAX_SAMPLE_DIST(x) (((x) >> 13) & 0xF)
1426 #define C_028C04_MAX_SAMPLE_DIST 0xFFFE1FFF
1427 #define R_0280E0_CB_COLOR0_FRAG 0x0280E0
1428 #define S_0280E0_BASE_256B(x) (((x) & 0xFFFFFFFF) << 0)
1429 #define G_0280E0_BASE_256B(x) (((x) >> 0) & 0xFFFFFFFF)
1430 #define C_0280E0_BASE_256B 0x00000000
1431 #define R_0280E4_CB_COLOR1_FRAG 0x0280E4
1432 #define R_0280E8_CB_COLOR2_FRAG 0x0280E8
1433 #define R_0280EC_CB_COLOR3_FRAG 0x0280EC
1434 #define R_0280F0_CB_COLOR4_FRAG 0x0280F0
1435 #define R_0280F4_CB_COLOR5_FRAG 0x0280F4
1436 #define R_0280F8_CB_COLOR6_FRAG 0x0280F8
1437 #define R_0280FC_CB_COLOR7_FRAG 0x0280FC
1438 #define R_0280C0_CB_COLOR0_TILE 0x0280C0
1439 #define S_0280C0_BASE_256B(x) (((x) & 0xFFFFFFFF) << 0)
1440 #define G_0280C0_BASE_256B(x) (((x) >> 0) & 0xFFFFFFFF)
1441 #define C_0280C0_BASE_256B 0x00000000
1442 #define R_0280C4_CB_COLOR1_TILE 0x0280C4
1443 #define R_0280C8_CB_COLOR2_TILE 0x0280C8
1444 #define R_0280CC_CB_COLOR3_TILE 0x0280CC
1445 #define R_0280D0_CB_COLOR4_TILE 0x0280D0
1446 #define R_0280D4_CB_COLOR5_TILE 0x0280D4
1447 #define R_0280D8_CB_COLOR6_TILE 0x0280D8
1448 #define R_0280DC_CB_COLOR7_TILE 0x0280DC
1449 #define R_0280A0_CB_COLOR0_INFO 0x0280A0
1450 #define S_0280A0_ENDIAN(x) (((x) & 0x3) << 0)
1451 #define G_0280A0_ENDIAN(x) (((x) >> 0) & 0x3)
1452 #define C_0280A0_ENDIAN 0xFFFFFFFC
1453 #define S_0280A0_FORMAT(x) (((x) & 0x3F) << 2)
1454 #define G_0280A0_FORMAT(x) (((x) >> 2) & 0x3F)
1455 #define C_0280A0_FORMAT 0xFFFFFF03
1456 #define V_0280A0_COLOR_INVALID 0x00000000
1457 #define V_0280A0_COLOR_8 0x00000001
1458 #define V_0280A0_COLOR_4_4 0x00000002
1459 #define V_0280A0_COLOR_3_3_2 0x00000003
1460 #define V_0280A0_COLOR_16 0x00000005
1461 #define V_0280A0_COLOR_16_FLOAT 0x00000006
1462 #define V_0280A0_COLOR_8_8 0x00000007
1463 #define V_0280A0_COLOR_5_6_5 0x00000008
1464 #define V_0280A0_COLOR_6_5_5 0x00000009
1465 #define V_0280A0_COLOR_1_5_5_5 0x0000000A
1466 #define V_0280A0_COLOR_4_4_4_4 0x0000000B
1467 #define V_0280A0_COLOR_5_5_5_1 0x0000000C
1468 #define V_0280A0_COLOR_32 0x0000000D
1469 #define V_0280A0_COLOR_32_FLOAT 0x0000000E
1470 #define V_0280A0_COLOR_16_16 0x0000000F
1471 #define V_0280A0_COLOR_16_16_FLOAT 0x00000010
1472 #define V_0280A0_COLOR_8_24 0x00000011
1473 #define V_0280A0_COLOR_8_24_FLOAT 0x00000012
1474 #define V_0280A0_COLOR_24_8 0x00000013
1475 #define V_0280A0_COLOR_24_8_FLOAT 0x00000014
1476 #define V_0280A0_COLOR_10_11_11 0x00000015
1477 #define V_0280A0_COLOR_10_11_11_FLOAT 0x00000016
1478 #define V_0280A0_COLOR_11_11_10 0x00000017
1479 #define V_0280A0_COLOR_11_11_10_FLOAT 0x00000018
1480 #define V_0280A0_COLOR_2_10_10_10 0x00000019
1481 #define V_0280A0_COLOR_8_8_8_8 0x0000001A
1482 #define V_0280A0_COLOR_10_10_10_2 0x0000001B
1483 #define V_0280A0_COLOR_X24_8_32_FLOAT 0x0000001C
1484 #define V_0280A0_COLOR_32_32 0x0000001D
1485 #define V_0280A0_COLOR_32_32_FLOAT 0x0000001E
1486 #define V_0280A0_COLOR_16_16_16_16 0x0000001F
1487 #define V_0280A0_COLOR_16_16_16_16_FLOAT 0x00000020
1488 #define V_0280A0_COLOR_32_32_32_32 0x00000022
1489 #define V_0280A0_COLOR_32_32_32_32_FLOAT 0x00000023
1490 #define S_0280A0_ARRAY_MODE(x) (((x) & 0xF) << 8)
1491 #define G_0280A0_ARRAY_MODE(x) (((x) >> 8) & 0xF)
1492 #define C_0280A0_ARRAY_MODE 0xFFFFF0FF
1493 #define V_0280A0_ARRAY_LINEAR_GENERAL 0x00000000
1494 #define V_0280A0_ARRAY_LINEAR_ALIGNED 0x00000001
1495 #define V_0280A0_ARRAY_1D_TILED_THIN1 0x00000002
1496 #define V_0280A0_ARRAY_2D_TILED_THIN1 0x00000004
1497 #define S_0280A0_NUMBER_TYPE(x) (((x) & 0x7) << 12)
1498 #define G_0280A0_NUMBER_TYPE(x) (((x) >> 12) & 0x7)
1499 #define C_0280A0_NUMBER_TYPE 0xFFFF8FFF
1500 #define S_0280A0_READ_SIZE(x) (((x) & 0x1) << 15)
1501 #define G_0280A0_READ_SIZE(x) (((x) >> 15) & 0x1)
1502 #define C_0280A0_READ_SIZE 0xFFFF7FFF
1503 #define S_0280A0_COMP_SWAP(x) (((x) & 0x3) << 16)
1504 #define G_0280A0_COMP_SWAP(x) (((x) >> 16) & 0x3)
1505 #define C_0280A0_COMP_SWAP 0xFFFCFFFF
1506 #define S_0280A0_TILE_MODE(x) (((x) & 0x3) << 18)
1507 #define G_0280A0_TILE_MODE(x) (((x) >> 18) & 0x3)
1508 #define C_0280A0_TILE_MODE 0xFFF3FFFF
1509 #define V_0280A0_TILE_DISABLE 0
1510 #define V_0280A0_CLEAR_ENABLE 1
1511 #define V_0280A0_FRAG_ENABLE 2
1512 #define S_0280A0_BLEND_CLAMP(x) (((x) & 0x1) << 20)
1513 #define G_0280A0_BLEND_CLAMP(x) (((x) >> 20) & 0x1)
1514 #define C_0280A0_BLEND_CLAMP 0xFFEFFFFF
1515 #define S_0280A0_CLEAR_COLOR(x) (((x) & 0x1) << 21)
1516 #define G_0280A0_CLEAR_COLOR(x) (((x) >> 21) & 0x1)
1517 #define C_0280A0_CLEAR_COLOR 0xFFDFFFFF
1518 #define S_0280A0_BLEND_BYPASS(x) (((x) & 0x1) << 22)
1519 #define G_0280A0_BLEND_BYPASS(x) (((x) >> 22) & 0x1)
1520 #define C_0280A0_BLEND_BYPASS 0xFFBFFFFF
1521 #define S_0280A0_BLEND_FLOAT32(x) (((x) & 0x1) << 23)
1522 #define G_0280A0_BLEND_FLOAT32(x) (((x) >> 23) & 0x1)
1523 #define C_0280A0_BLEND_FLOAT32 0xFF7FFFFF
1524 #define S_0280A0_SIMPLE_FLOAT(x) (((x) & 0x1) << 24)
1525 #define G_0280A0_SIMPLE_FLOAT(x) (((x) >> 24) & 0x1)
1526 #define C_0280A0_SIMPLE_FLOAT 0xFEFFFFFF
1527 #define S_0280A0_ROUND_MODE(x) (((x) & 0x1) << 25)
1528 #define G_0280A0_ROUND_MODE(x) (((x) >> 25) & 0x1)
1529 #define C_0280A0_ROUND_MODE 0xFDFFFFFF
1530 #define S_0280A0_TILE_COMPACT(x) (((x) & 0x1) << 26)
1531 #define G_0280A0_TILE_COMPACT(x) (((x) >> 26) & 0x1)
1532 #define C_0280A0_TILE_COMPACT 0xFBFFFFFF
1533 #define S_0280A0_SOURCE_FORMAT(x) (((x) & 0x1) << 27)
1534 #define G_0280A0_SOURCE_FORMAT(x) (((x) >> 27) & 0x1)
1535 #define C_0280A0_SOURCE_FORMAT 0xF7FFFFFF
1536 #define R_0280A4_CB_COLOR1_INFO 0x0280A4
1537 #define R_0280A8_CB_COLOR2_INFO 0x0280A8
1538 #define R_0280AC_CB_COLOR3_INFO 0x0280AC
1539 #define R_0280B0_CB_COLOR4_INFO 0x0280B0
1540 #define R_0280B4_CB_COLOR5_INFO 0x0280B4
1541 #define R_0280B8_CB_COLOR6_INFO 0x0280B8
1542 #define R_0280BC_CB_COLOR7_INFO 0x0280BC
1543 #define R_028060_CB_COLOR0_SIZE 0x028060
1544 #define S_028060_PITCH_TILE_MAX(x) (((x) & 0x3FF) << 0)
1545 #define G_028060_PITCH_TILE_MAX(x) (((x) >> 0) & 0x3FF)
1546 #define C_028060_PITCH_TILE_MAX 0xFFFFFC00
1547 #define S_028060_SLICE_TILE_MAX(x) (((x) & 0xFFFFF) << 10)
1548 #define G_028060_SLICE_TILE_MAX(x) (((x) >> 10) & 0xFFFFF)
1549 #define C_028060_SLICE_TILE_MAX 0xC00003FF
1550 #define R_028064_CB_COLOR1_SIZE 0x028064
1551 #define R_028068_CB_COLOR2_SIZE 0x028068
1552 #define R_02806C_CB_COLOR3_SIZE 0x02806C
1553 #define R_028070_CB_COLOR4_SIZE 0x028070
1554 #define R_028074_CB_COLOR5_SIZE 0x028074
1555 #define R_028078_CB_COLOR6_SIZE 0x028078
1556 #define R_02807C_CB_COLOR7_SIZE 0x02807C
1557 #define R_028238_CB_TARGET_MASK 0x028238
1558 #define S_028238_TARGET0_ENABLE(x) (((x) & 0xF) << 0)
1559 #define G_028238_TARGET0_ENABLE(x) (((x) >> 0) & 0xF)
1560 #define C_028238_TARGET0_ENABLE 0xFFFFFFF0
1561 #define S_028238_TARGET1_ENABLE(x) (((x) & 0xF) << 4)
1562 #define G_028238_TARGET1_ENABLE(x) (((x) >> 4) & 0xF)
1563 #define C_028238_TARGET1_ENABLE 0xFFFFFF0F
1564 #define S_028238_TARGET2_ENABLE(x) (((x) & 0xF) << 8)
1565 #define G_028238_TARGET2_ENABLE(x) (((x) >> 8) & 0xF)
1566 #define C_028238_TARGET2_ENABLE 0xFFFFF0FF
1567 #define S_028238_TARGET3_ENABLE(x) (((x) & 0xF) << 12)
1568 #define G_028238_TARGET3_ENABLE(x) (((x) >> 12) & 0xF)
1569 #define C_028238_TARGET3_ENABLE 0xFFFF0FFF
1570 #define S_028238_TARGET4_ENABLE(x) (((x) & 0xF) << 16)
1571 #define G_028238_TARGET4_ENABLE(x) (((x) >> 16) & 0xF)
1572 #define C_028238_TARGET4_ENABLE 0xFFF0FFFF
1573 #define S_028238_TARGET5_ENABLE(x) (((x) & 0xF) << 20)
1574 #define G_028238_TARGET5_ENABLE(x) (((x) >> 20) & 0xF)
1575 #define C_028238_TARGET5_ENABLE 0xFF0FFFFF
1576 #define S_028238_TARGET6_ENABLE(x) (((x) & 0xF) << 24)
1577 #define G_028238_TARGET6_ENABLE(x) (((x) >> 24) & 0xF)
1578 #define C_028238_TARGET6_ENABLE 0xF0FFFFFF
1579 #define S_028238_TARGET7_ENABLE(x) (((x) & 0xF) << 28)
1580 #define G_028238_TARGET7_ENABLE(x) (((x) >> 28) & 0xF)
1581 #define C_028238_TARGET7_ENABLE 0x0FFFFFFF
1582 #define R_02823C_CB_SHADER_MASK 0x02823C
1583 #define S_02823C_OUTPUT0_ENABLE(x) (((x) & 0xF) << 0)
1584 #define G_02823C_OUTPUT0_ENABLE(x) (((x) >> 0) & 0xF)
1585 #define C_02823C_OUTPUT0_ENABLE 0xFFFFFFF0
1586 #define S_02823C_OUTPUT1_ENABLE(x) (((x) & 0xF) << 4)
1587 #define G_02823C_OUTPUT1_ENABLE(x) (((x) >> 4) & 0xF)
1588 #define C_02823C_OUTPUT1_ENABLE 0xFFFFFF0F
1589 #define S_02823C_OUTPUT2_ENABLE(x) (((x) & 0xF) << 8)
1590 #define G_02823C_OUTPUT2_ENABLE(x) (((x) >> 8) & 0xF)
1591 #define C_02823C_OUTPUT2_ENABLE 0xFFFFF0FF
1592 #define S_02823C_OUTPUT3_ENABLE(x) (((x) & 0xF) << 12)
1593 #define G_02823C_OUTPUT3_ENABLE(x) (((x) >> 12) & 0xF)
1594 #define C_02823C_OUTPUT3_ENABLE 0xFFFF0FFF
1595 #define S_02823C_OUTPUT4_ENABLE(x) (((x) & 0xF) << 16)
1596 #define G_02823C_OUTPUT4_ENABLE(x) (((x) >> 16) & 0xF)
1597 #define C_02823C_OUTPUT4_ENABLE 0xFFF0FFFF
1598 #define S_02823C_OUTPUT5_ENABLE(x) (((x) & 0xF) << 20)
1599 #define G_02823C_OUTPUT5_ENABLE(x) (((x) >> 20) & 0xF)
1600 #define C_02823C_OUTPUT5_ENABLE 0xFF0FFFFF
1601 #define S_02823C_OUTPUT6_ENABLE(x) (((x) & 0xF) << 24)
1602 #define G_02823C_OUTPUT6_ENABLE(x) (((x) >> 24) & 0xF)
1603 #define C_02823C_OUTPUT6_ENABLE 0xF0FFFFFF
1604 #define S_02823C_OUTPUT7_ENABLE(x) (((x) & 0xF) << 28)
1605 #define G_02823C_OUTPUT7_ENABLE(x) (((x) >> 28) & 0xF)
1606 #define C_02823C_OUTPUT7_ENABLE 0x0FFFFFFF
1607 #define R_028AB0_VGT_STRMOUT_EN 0x028AB0
1608 #define S_028AB0_STREAMOUT(x) (((x) & 0x1) << 0)
1609 #define G_028AB0_STREAMOUT(x) (((x) >> 0) & 0x1)
1610 #define C_028AB0_STREAMOUT 0xFFFFFFFE
1611 #define R_028B20_VGT_STRMOUT_BUFFER_EN 0x028B20
1612 #define S_028B20_BUFFER_0_EN(x) (((x) & 0x1) << 0)
1613 #define G_028B20_BUFFER_0_EN(x) (((x) >> 0) & 0x1)
1614 #define C_028B20_BUFFER_0_EN 0xFFFFFFFE
1615 #define S_028B20_BUFFER_1_EN(x) (((x) & 0x1) << 1)
1616 #define G_028B20_BUFFER_1_EN(x) (((x) >> 1) & 0x1)
1617 #define C_028B20_BUFFER_1_EN 0xFFFFFFFD
1618 #define S_028B20_BUFFER_2_EN(x) (((x) & 0x1) << 2)
1619 #define G_028B20_BUFFER_2_EN(x) (((x) >> 2) & 0x1)
1620 #define C_028B20_BUFFER_2_EN 0xFFFFFFFB
1621 #define S_028B20_BUFFER_3_EN(x) (((x) & 0x1) << 3)
1622 #define G_028B20_BUFFER_3_EN(x) (((x) >> 3) & 0x1)
1623 #define C_028B20_BUFFER_3_EN 0xFFFFFFF7
1624 #define S_028B20_SIZE(x) (((x) & 0xFFFFFFFF) << 0)
1625 #define G_028B20_SIZE(x) (((x) >> 0) & 0xFFFFFFFF)
1626 #define C_028B20_SIZE 0x00000000
1627 #define R_038000_SQ_TEX_RESOURCE_WORD0_0 0x038000
1628 #define S_038000_DIM(x) (((x) & 0x7) << 0)
1629 #define G_038000_DIM(x) (((x) >> 0) & 0x7)
1630 #define C_038000_DIM 0xFFFFFFF8
1631 #define V_038000_SQ_TEX_DIM_1D 0x00000000
1632 #define V_038000_SQ_TEX_DIM_2D 0x00000001
1633 #define V_038000_SQ_TEX_DIM_3D 0x00000002
1634 #define V_038000_SQ_TEX_DIM_CUBEMAP 0x00000003
1635 #define V_038000_SQ_TEX_DIM_1D_ARRAY 0x00000004
1636 #define V_038000_SQ_TEX_DIM_2D_ARRAY 0x00000005
1637 #define V_038000_SQ_TEX_DIM_2D_MSAA 0x00000006
1638 #define V_038000_SQ_TEX_DIM_2D_ARRAY_MSAA 0x00000007
1639 #define S_038000_TILE_MODE(x) (((x) & 0xF) << 3)
1640 #define G_038000_TILE_MODE(x) (((x) >> 3) & 0xF)
1641 #define C_038000_TILE_MODE 0xFFFFFF87
1642 #define V_038000_ARRAY_LINEAR_GENERAL 0x00000000
1643 #define V_038000_ARRAY_LINEAR_ALIGNED 0x00000001
1644 #define V_038000_ARRAY_1D_TILED_THIN1 0x00000002
1645 #define V_038000_ARRAY_2D_TILED_THIN1 0x00000004
1646 #define S_038000_TILE_TYPE(x) (((x) & 0x1) << 7)
1647 #define G_038000_TILE_TYPE(x) (((x) >> 7) & 0x1)
1648 #define C_038000_TILE_TYPE 0xFFFFFF7F
1649 #define S_038000_PITCH(x) (((x) & 0x7FF) << 8)
1650 #define G_038000_PITCH(x) (((x) >> 8) & 0x7FF)
1651 #define C_038000_PITCH 0xFFF800FF
1652 #define S_038000_TEX_WIDTH(x) (((x) & 0x1FFF) << 19)
1653 #define G_038000_TEX_WIDTH(x) (((x) >> 19) & 0x1FFF)
1654 #define C_038000_TEX_WIDTH 0x0007FFFF
1655 #define R_038004_SQ_TEX_RESOURCE_WORD1_0 0x038004
1656 #define S_038004_TEX_HEIGHT(x) (((x) & 0x1FFF) << 0)
1657 #define G_038004_TEX_HEIGHT(x) (((x) >> 0) & 0x1FFF)
1658 #define C_038004_TEX_HEIGHT 0xFFFFE000
1659 #define S_038004_TEX_DEPTH(x) (((x) & 0x1FFF) << 13)
1660 #define G_038004_TEX_DEPTH(x) (((x) >> 13) & 0x1FFF)
1661 #define C_038004_TEX_DEPTH 0xFC001FFF
1662 #define S_038004_DATA_FORMAT(x) (((x) & 0x3F) << 26)
1663 #define G_038004_DATA_FORMAT(x) (((x) >> 26) & 0x3F)
1664 #define C_038004_DATA_FORMAT 0x03FFFFFF
1665 #define V_038004_COLOR_INVALID 0x00000000
1666 #define V_038004_COLOR_8 0x00000001
1667 #define V_038004_COLOR_4_4 0x00000002
1668 #define V_038004_COLOR_3_3_2 0x00000003
1669 #define V_038004_COLOR_16 0x00000005
1670 #define V_038004_COLOR_16_FLOAT 0x00000006
1671 #define V_038004_COLOR_8_8 0x00000007
1672 #define V_038004_COLOR_5_6_5 0x00000008
1673 #define V_038004_COLOR_6_5_5 0x00000009
1674 #define V_038004_COLOR_1_5_5_5 0x0000000A
1675 #define V_038004_COLOR_4_4_4_4 0x0000000B
1676 #define V_038004_COLOR_5_5_5_1 0x0000000C
1677 #define V_038004_COLOR_32 0x0000000D
1678 #define V_038004_COLOR_32_FLOAT 0x0000000E
1679 #define V_038004_COLOR_16_16 0x0000000F
1680 #define V_038004_COLOR_16_16_FLOAT 0x00000010
1681 #define V_038004_COLOR_8_24 0x00000011
1682 #define V_038004_COLOR_8_24_FLOAT 0x00000012
1683 #define V_038004_COLOR_24_8 0x00000013
1684 #define V_038004_COLOR_24_8_FLOAT 0x00000014
1685 #define V_038004_COLOR_10_11_11 0x00000015
1686 #define V_038004_COLOR_10_11_11_FLOAT 0x00000016
1687 #define V_038004_COLOR_11_11_10 0x00000017
1688 #define V_038004_COLOR_11_11_10_FLOAT 0x00000018
1689 #define V_038004_COLOR_2_10_10_10 0x00000019
1690 #define V_038004_COLOR_8_8_8_8 0x0000001A
1691 #define V_038004_COLOR_10_10_10_2 0x0000001B
1692 #define V_038004_COLOR_X24_8_32_FLOAT 0x0000001C
1693 #define V_038004_COLOR_32_32 0x0000001D
1694 #define V_038004_COLOR_32_32_FLOAT 0x0000001E
1695 #define V_038004_COLOR_16_16_16_16 0x0000001F
1696 #define V_038004_COLOR_16_16_16_16_FLOAT 0x00000020
1697 #define V_038004_COLOR_32_32_32_32 0x00000022
1698 #define V_038004_COLOR_32_32_32_32_FLOAT 0x00000023
1699 #define V_038004_FMT_1 0x00000025
1700 #define V_038004_FMT_GB_GR 0x00000027
1701 #define V_038004_FMT_BG_RG 0x00000028
1702 #define V_038004_FMT_32_AS_8 0x00000029
1703 #define V_038004_FMT_32_AS_8_8 0x0000002A
1704 #define V_038004_FMT_5_9_9_9_SHAREDEXP 0x0000002B
1705 #define V_038004_FMT_8_8_8 0x0000002C
1706 #define V_038004_FMT_16_16_16 0x0000002D
1707 #define V_038004_FMT_16_16_16_FLOAT 0x0000002E
1708 #define V_038004_FMT_32_32_32 0x0000002F
1709 #define V_038004_FMT_32_32_32_FLOAT 0x00000030
1710 #define V_038004_FMT_BC1 0x00000031
1711 #define V_038004_FMT_BC2 0x00000032
1712 #define V_038004_FMT_BC3 0x00000033
1713 #define V_038004_FMT_BC4 0x00000034
1714 #define V_038004_FMT_BC5 0x00000035
1715 #define V_038004_FMT_BC6 0x00000036
1716 #define V_038004_FMT_BC7 0x00000037
1717 #define V_038004_FMT_32_AS_32_32_32_32 0x00000038
1718 #define R_038010_SQ_TEX_RESOURCE_WORD4_0 0x038010
1719 #define S_038010_FORMAT_COMP_X(x) (((x) & 0x3) << 0)
1720 #define G_038010_FORMAT_COMP_X(x) (((x) >> 0) & 0x3)
1721 #define C_038010_FORMAT_COMP_X 0xFFFFFFFC
1722 #define S_038010_FORMAT_COMP_Y(x) (((x) & 0x3) << 2)
1723 #define G_038010_FORMAT_COMP_Y(x) (((x) >> 2) & 0x3)
1724 #define C_038010_FORMAT_COMP_Y 0xFFFFFFF3
1725 #define S_038010_FORMAT_COMP_Z(x) (((x) & 0x3) << 4)
1726 #define G_038010_FORMAT_COMP_Z(x) (((x) >> 4) & 0x3)
1727 #define C_038010_FORMAT_COMP_Z 0xFFFFFFCF
1728 #define S_038010_FORMAT_COMP_W(x) (((x) & 0x3) << 6)
1729 #define G_038010_FORMAT_COMP_W(x) (((x) >> 6) & 0x3)
1730 #define C_038010_FORMAT_COMP_W 0xFFFFFF3F
1731 #define S_038010_NUM_FORMAT_ALL(x) (((x) & 0x3) << 8)
1732 #define G_038010_NUM_FORMAT_ALL(x) (((x) >> 8) & 0x3)
1733 #define C_038010_NUM_FORMAT_ALL 0xFFFFFCFF
1734 #define S_038010_SRF_MODE_ALL(x) (((x) & 0x1) << 10)
1735 #define G_038010_SRF_MODE_ALL(x) (((x) >> 10) & 0x1)
1736 #define C_038010_SRF_MODE_ALL 0xFFFFFBFF
1737 #define S_038010_FORCE_DEGAMMA(x) (((x) & 0x1) << 11)
1738 #define G_038010_FORCE_DEGAMMA(x) (((x) >> 11) & 0x1)
1739 #define C_038010_FORCE_DEGAMMA 0xFFFFF7FF
1740 #define S_038010_ENDIAN_SWAP(x) (((x) & 0x3) << 12)
1741 #define G_038010_ENDIAN_SWAP(x) (((x) >> 12) & 0x3)
1742 #define C_038010_ENDIAN_SWAP 0xFFFFCFFF
1743 #define S_038010_REQUEST_SIZE(x) (((x) & 0x3) << 14)
1744 #define G_038010_REQUEST_SIZE(x) (((x) >> 14) & 0x3)
1745 #define C_038010_REQUEST_SIZE 0xFFFF3FFF
1746 #define S_038010_DST_SEL_X(x) (((x) & 0x7) << 16)
1747 #define G_038010_DST_SEL_X(x) (((x) >> 16) & 0x7)
1748 #define C_038010_DST_SEL_X 0xFFF8FFFF
1749 #define S_038010_DST_SEL_Y(x) (((x) & 0x7) << 19)
1750 #define G_038010_DST_SEL_Y(x) (((x) >> 19) & 0x7)
1751 #define C_038010_DST_SEL_Y 0xFFC7FFFF
1752 #define S_038010_DST_SEL_Z(x) (((x) & 0x7) << 22)
1753 #define G_038010_DST_SEL_Z(x) (((x) >> 22) & 0x7)
1754 #define C_038010_DST_SEL_Z 0xFE3FFFFF
1755 #define S_038010_DST_SEL_W(x) (((x) & 0x7) << 25)
1756 #define G_038010_DST_SEL_W(x) (((x) >> 25) & 0x7)
1757 #define C_038010_DST_SEL_W 0xF1FFFFFF
1764 #define S_038010_BASE_LEVEL(x) (((x) & 0xF) << 28)
1765 #define G_038010_BASE_LEVEL(x) (((x) >> 28) & 0xF)
1766 #define C_038010_BASE_LEVEL 0x0FFFFFFF
1767 #define R_038014_SQ_TEX_RESOURCE_WORD5_0 0x038014
1768 #define S_038014_LAST_LEVEL(x) (((x) & 0xF) << 0)
1769 #define G_038014_LAST_LEVEL(x) (((x) >> 0) & 0xF)
1770 #define C_038014_LAST_LEVEL 0xFFFFFFF0
1771 #define S_038014_BASE_ARRAY(x) (((x) & 0x1FFF) << 4)
1772 #define G_038014_BASE_ARRAY(x) (((x) >> 4) & 0x1FFF)
1773 #define C_038014_BASE_ARRAY 0xFFFE000F
1774 #define S_038014_LAST_ARRAY(x) (((x) & 0x1FFF) << 17)
1775 #define G_038014_LAST_ARRAY(x) (((x) >> 17) & 0x1FFF)
1776 #define C_038014_LAST_ARRAY 0xC001FFFF
1777 #define R_0288A8_SQ_ESGS_RING_ITEMSIZE 0x0288A8
1778 #define S_0288A8_ITEMSIZE(x) (((x) & 0x7FFF) << 0)
1779 #define G_0288A8_ITEMSIZE(x) (((x) >> 0) & 0x7FFF)
1780 #define C_0288A8_ITEMSIZE 0xFFFF8000
1781 #define R_008C44_SQ_ESGS_RING_SIZE 0x008C44
1782 #define S_008C44_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0)
1783 #define G_008C44_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF)
1784 #define C_008C44_MEM_SIZE 0x00000000
1785 #define R_0288B0_SQ_ESTMP_RING_ITEMSIZE 0x0288B0
1786 #define S_0288B0_ITEMSIZE(x) (((x) & 0x7FFF) << 0)
1787 #define G_0288B0_ITEMSIZE(x) (((x) >> 0) & 0x7FFF)
1788 #define C_0288B0_ITEMSIZE 0xFFFF8000
1789 #define R_008C54_SQ_ESTMP_RING_SIZE 0x008C54
1790 #define S_008C54_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0)
1791 #define G_008C54_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF)
1792 #define C_008C54_MEM_SIZE 0x00000000
1793 #define R_0288C0_SQ_FBUF_RING_ITEMSIZE 0x0288C0
1794 #define S_0288C0_ITEMSIZE(x) (((x) & 0x7FFF) << 0)
1795 #define G_0288C0_ITEMSIZE(x) (((x) >> 0) & 0x7FFF)
1796 #define C_0288C0_ITEMSIZE 0xFFFF8000
1797 #define R_008C74_SQ_FBUF_RING_SIZE 0x008C74
1798 #define S_008C74_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0)
1799 #define G_008C74_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF)
1800 #define C_008C74_MEM_SIZE 0x00000000
1801 #define R_0288B4_SQ_GSTMP_RING_ITEMSIZE 0x0288B4
1802 #define S_0288B4_ITEMSIZE(x) (((x) & 0x7FFF) << 0)
1803 #define G_0288B4_ITEMSIZE(x) (((x) >> 0) & 0x7FFF)
1804 #define C_0288B4_ITEMSIZE 0xFFFF8000
1805 #define R_008C5C_SQ_GSTMP_RING_SIZE 0x008C5C
1806 #define S_008C5C_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0)
1807 #define G_008C5C_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF)
1808 #define C_008C5C_MEM_SIZE 0x00000000
1809 #define R_0288AC_SQ_GSVS_RING_ITEMSIZE 0x0288AC
1810 #define S_0288AC_ITEMSIZE(x) (((x) & 0x7FFF) << 0)
1811 #define G_0288AC_ITEMSIZE(x) (((x) >> 0) & 0x7FFF)
1812 #define C_0288AC_ITEMSIZE 0xFFFF8000
1813 #define R_008C4C_SQ_GSVS_RING_SIZE 0x008C4C
1814 #define S_008C4C_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0)
1815 #define G_008C4C_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF)
1816 #define C_008C4C_MEM_SIZE 0x00000000
1817 #define R_0288BC_SQ_PSTMP_RING_ITEMSIZE 0x0288BC
1818 #define S_0288BC_ITEMSIZE(x) (((x) & 0x7FFF) << 0)
1819 #define G_0288BC_ITEMSIZE(x) (((x) >> 0) & 0x7FFF)
1820 #define C_0288BC_ITEMSIZE 0xFFFF8000
1821 #define R_008C6C_SQ_PSTMP_RING_SIZE 0x008C6C
1822 #define S_008C6C_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0)
1823 #define G_008C6C_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF)
1824 #define C_008C6C_MEM_SIZE 0x00000000
1825 #define R_0288C4_SQ_REDUC_RING_ITEMSIZE 0x0288C4
1826 #define S_0288C4_ITEMSIZE(x) (((x) & 0x7FFF) << 0)
1827 #define G_0288C4_ITEMSIZE(x) (((x) >> 0) & 0x7FFF)
1828 #define C_0288C4_ITEMSIZE 0xFFFF8000
1829 #define R_008C7C_SQ_REDUC_RING_SIZE 0x008C7C
1830 #define S_008C7C_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0)
1831 #define G_008C7C_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF)
1832 #define C_008C7C_MEM_SIZE 0x00000000
1833 #define R_0288B8_SQ_VSTMP_RING_ITEMSIZE 0x0288B8
1834 #define S_0288B8_ITEMSIZE(x) (((x) & 0x7FFF) << 0)
1835 #define G_0288B8_ITEMSIZE(x) (((x) >> 0) & 0x7FFF)
1836 #define C_0288B8_ITEMSIZE 0xFFFF8000
1837 #define R_008C64_SQ_VSTMP_RING_SIZE 0x008C64
1838 #define S_008C64_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0)
1839 #define G_008C64_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF)
1840 #define C_008C64_MEM_SIZE 0x00000000
1841 #define R_0288C8_SQ_GS_VERT_ITEMSIZE 0x0288C8
1842 #define S_0288C8_ITEMSIZE(x) (((x) & 0x7FFF) << 0)
1843 #define G_0288C8_ITEMSIZE(x) (((x) >> 0) & 0x7FFF)
1844 #define C_0288C8_ITEMSIZE 0xFFFF8000
1845 #define R_028010_DB_DEPTH_INFO 0x028010
1846 #define S_028010_FORMAT(x) (((x) & 0x7) << 0)
1847 #define G_028010_FORMAT(x) (((x) >> 0) & 0x7)
1848 #define C_028010_FORMAT 0xFFFFFFF8
1849 #define V_028010_DEPTH_INVALID 0x00000000
1850 #define V_028010_DEPTH_16 0x00000001
1851 #define V_028010_DEPTH_X8_24 0x00000002
1852 #define V_028010_DEPTH_8_24 0x00000003
1853 #define V_028010_DEPTH_X8_24_FLOAT 0x00000004
1854 #define V_028010_DEPTH_8_24_FLOAT 0x00000005
1855 #define V_028010_DEPTH_32_FLOAT 0x00000006
1856 #define V_028010_DEPTH_X24_8_32_FLOAT 0x00000007
1857 #define S_028010_READ_SIZE(x) (((x) & 0x1) << 3)
1858 #define G_028010_READ_SIZE(x) (((x) >> 3) & 0x1)
1859 #define C_028010_READ_SIZE 0xFFFFFFF7
1860 #define S_028010_ARRAY_MODE(x) (((x) & 0xF) << 15)
1861 #define G_028010_ARRAY_MODE(x) (((x) >> 15) & 0xF)
1862 #define C_028010_ARRAY_MODE 0xFFF87FFF
1863 #define V_028010_ARRAY_1D_TILED_THIN1 0x00000002
1864 #define V_028010_ARRAY_2D_TILED_THIN1 0x00000004
1865 #define S_028010_TILE_SURFACE_ENABLE(x) (((x) & 0x1) << 25)
1866 #define G_028010_TILE_SURFACE_ENABLE(x) (((x) >> 25) & 0x1)
1867 #define C_028010_TILE_SURFACE_ENABLE 0xFDFFFFFF
1868 #define S_028010_TILE_COMPACT(x) (((x) & 0x1) << 26)
1869 #define G_028010_TILE_COMPACT(x) (((x) >> 26) & 0x1)
1870 #define C_028010_TILE_COMPACT 0xFBFFFFFF
1871 #define S_028010_ZRANGE_PRECISION(x) (((x) & 0x1) << 31)
1872 #define G_028010_ZRANGE_PRECISION(x) (((x) >> 31) & 0x1)
1873 #define C_028010_ZRANGE_PRECISION 0x7FFFFFFF
1874 #define R_028000_DB_DEPTH_SIZE 0x028000
1875 #define S_028000_PITCH_TILE_MAX(x) (((x) & 0x3FF) << 0)
1876 #define G_028000_PITCH_TILE_MAX(x) (((x) >> 0) & 0x3FF)
1877 #define C_028000_PITCH_TILE_MAX 0xFFFFFC00
1878 #define S_028000_SLICE_TILE_MAX(x) (((x) & 0xFFFFF) << 10)
1879 #define G_028000_SLICE_TILE_MAX(x) (((x) >> 10) & 0xFFFFF)
1880 #define C_028000_SLICE_TILE_MAX 0xC00003FF
1881 #define R_028004_DB_DEPTH_VIEW 0x028004
1882 #define S_028004_SLICE_START(x) (((x) & 0x7FF) << 0)
1883 #define G_028004_SLICE_START(x) (((x) >> 0) & 0x7FF)
1884 #define C_028004_SLICE_START 0xFFFFF800
1885 #define S_028004_SLICE_MAX(x) (((x) & 0x7FF) << 13)
1886 #define G_028004_SLICE_MAX(x) (((x) >> 13) & 0x7FF)
1887 #define C_028004_SLICE_MAX 0xFF001FFF
1888 #define R_028800_DB_DEPTH_CONTROL 0x028800
1889 #define S_028800_STENCIL_ENABLE(x) (((x) & 0x1) << 0)
1890 #define G_028800_STENCIL_ENABLE(x) (((x) >> 0) & 0x1)
1891 #define C_028800_STENCIL_ENABLE 0xFFFFFFFE
1892 #define S_028800_Z_ENABLE(x) (((x) & 0x1) << 1)
1893 #define G_028800_Z_ENABLE(x) (((x) >> 1) & 0x1)
1894 #define C_028800_Z_ENABLE 0xFFFFFFFD
1895 #define S_028800_Z_WRITE_ENABLE(x) (((x) & 0x1) << 2)
1896 #define G_028800_Z_WRITE_ENABLE(x) (((x) >> 2) & 0x1)
1897 #define C_028800_Z_WRITE_ENABLE 0xFFFFFFFB
1898 #define S_028800_ZFUNC(x) (((x) & 0x7) << 4)
1899 #define G_028800_ZFUNC(x) (((x) >> 4) & 0x7)
1900 #define C_028800_ZFUNC 0xFFFFFF8F
1901 #define S_028800_BACKFACE_ENABLE(x) (((x) & 0x1) << 7)
1902 #define G_028800_BACKFACE_ENABLE(x) (((x) >> 7) & 0x1)
1903 #define C_028800_BACKFACE_ENABLE 0xFFFFFF7F
1904 #define S_028800_STENCILFUNC(x) (((x) & 0x7) << 8)
1905 #define G_028800_STENCILFUNC(x) (((x) >> 8) & 0x7)
1906 #define C_028800_STENCILFUNC 0xFFFFF8FF
1907 #define S_028800_STENCILFAIL(x) (((x) & 0x7) << 11)
1908 #define G_028800_STENCILFAIL(x) (((x) >> 11) & 0x7)
1909 #define C_028800_STENCILFAIL 0xFFFFC7FF
1910 #define S_028800_STENCILZPASS(x) (((x) & 0x7) << 14)
1911 #define G_028800_STENCILZPASS(x) (((x) >> 14) & 0x7)
1912 #define C_028800_STENCILZPASS 0xFFFE3FFF
1913 #define S_028800_STENCILZFAIL(x) (((x) & 0x7) << 17)
1914 #define G_028800_STENCILZFAIL(x) (((x) >> 17) & 0x7)
1915 #define C_028800_STENCILZFAIL 0xFFF1FFFF
1916 #define S_028800_STENCILFUNC_BF(x) (((x) & 0x7) << 20)
1917 #define G_028800_STENCILFUNC_BF(x) (((x) >> 20) & 0x7)
1918 #define C_028800_STENCILFUNC_BF 0xFF8FFFFF
1919 #define S_028800_STENCILFAIL_BF(x) (((x) & 0x7) << 23)
1920 #define G_028800_STENCILFAIL_BF(x) (((x) >> 23) & 0x7)
1921 #define C_028800_STENCILFAIL_BF 0xFC7FFFFF
1922 #define S_028800_STENCILZPASS_BF(x) (((x) & 0x7) << 26)
1923 #define G_028800_STENCILZPASS_BF(x) (((x) >> 26) & 0x7)
1924 #define C_028800_STENCILZPASS_BF 0xE3FFFFFF
1925 #define S_028800_STENCILZFAIL_BF(x) (((x) & 0x7) << 29)
1926 #define G_028800_STENCILZFAIL_BF(x) (((x) >> 29) & 0x7)
1927 #define C_028800_STENCILZFAIL_BF 0x1FFFFFFF