drivers/gpu/drm/radeon/r600.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/slab.h>
  29 #include <linux/seq_file.h>
  30 #include <linux/firmware.h>
  31 #include <linux/module.h>
  32 #include <drm/drmP.h>
  33 #include <drm/radeon_drm.h>
  34 #include "radeon.h"
  35 #include "radeon_asic.h"
  36 #include "radeon_mode.h"
  37 #include "r600d.h"
  38 #include "atom.h"
  39 #include "avivod.h"
  40 #include "radeon_ucode.h"
  41
  42 /* Firmware Names */
  43 MODULE_FIRMWARE("radeon/R600_pfp.bin");
  44 MODULE_FIRMWARE("radeon/R600_me.bin");
  45 MODULE_FIRMWARE("radeon/RV610_pfp.bin");
  46 MODULE_FIRMWARE("radeon/RV610_me.bin");
  47 MODULE_FIRMWARE("radeon/RV630_pfp.bin");
  48 MODULE_FIRMWARE("radeon/RV630_me.bin");
  49 MODULE_FIRMWARE("radeon/RV620_pfp.bin");
  50 MODULE_FIRMWARE("radeon/RV620_me.bin");
  51 MODULE_FIRMWARE("radeon/RV635_pfp.bin");
  52 MODULE_FIRMWARE("radeon/RV635_me.bin");
  53 MODULE_FIRMWARE("radeon/RV670_pfp.bin");
  54 MODULE_FIRMWARE("radeon/RV670_me.bin");
  55 MODULE_FIRMWARE("radeon/RS780_pfp.bin");
  56 MODULE_FIRMWARE("radeon/RS780_me.bin");
  57 MODULE_FIRMWARE("radeon/RV770_pfp.bin");
  58 MODULE_FIRMWARE("radeon/RV770_me.bin");
  59 MODULE_FIRMWARE("radeon/RV770_smc.bin");
  60 MODULE_FIRMWARE("radeon/RV730_pfp.bin");
  61 MODULE_FIRMWARE("radeon/RV730_me.bin");
  62 MODULE_FIRMWARE("radeon/RV730_smc.bin");
  63 MODULE_FIRMWARE("radeon/RV740_smc.bin");
  64 MODULE_FIRMWARE("radeon/RV710_pfp.bin");
  65 MODULE_FIRMWARE("radeon/RV710_me.bin");
  66 MODULE_FIRMWARE("radeon/RV710_smc.bin");
  67 MODULE_FIRMWARE("radeon/R600_rlc.bin");
  68 MODULE_FIRMWARE("radeon/R700_rlc.bin");
  69 MODULE_FIRMWARE("radeon/CEDAR_pfp.bin");
  70 MODULE_FIRMWARE("radeon/CEDAR_me.bin");
  71 MODULE_FIRMWARE("radeon/CEDAR_rlc.bin");
  72 MODULE_FIRMWARE("radeon/CEDAR_smc.bin");
  73 MODULE_FIRMWARE("radeon/REDWOOD_pfp.bin");
  74 MODULE_FIRMWARE("radeon/REDWOOD_me.bin");
  75 MODULE_FIRMWARE("radeon/REDWOOD_rlc.bin");
  76 MODULE_FIRMWARE("radeon/REDWOOD_smc.bin");
  77 MODULE_FIRMWARE("radeon/JUNIPER_pfp.bin");
  78 MODULE_FIRMWARE("radeon/JUNIPER_me.bin");
  79 MODULE_FIRMWARE("radeon/JUNIPER_rlc.bin");
  80 MODULE_FIRMWARE("radeon/JUNIPER_smc.bin");
  81 MODULE_FIRMWARE("radeon/CYPRESS_pfp.bin");
  82 MODULE_FIRMWARE("radeon/CYPRESS_me.bin");
  83 MODULE_FIRMWARE("radeon/CYPRESS_rlc.bin");
  84 MODULE_FIRMWARE("radeon/CYPRESS_smc.bin");
  85 MODULE_FIRMWARE("radeon/PALM_pfp.bin");
  86 MODULE_FIRMWARE("radeon/PALM_me.bin");
  87 MODULE_FIRMWARE("radeon/SUMO_rlc.bin");
  88 MODULE_FIRMWARE("radeon/SUMO_pfp.bin");
  89 MODULE_FIRMWARE("radeon/SUMO_me.bin");
  90 MODULE_FIRMWARE("radeon/SUMO2_pfp.bin");
  91 MODULE_FIRMWARE("radeon/SUMO2_me.bin");
  92
  93 static const u32 crtc_offsets[2] =
  94 {
  95         0,
  96         AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL
  97 };
  98
  99 int r600_debugfs_mc_info_init(struct radeon_device *rdev);
 100
 101 /* r600,rv610,rv630,rv620,rv635,rv670 */
 102 int r600_mc_wait_for_idle(struct radeon_device *rdev);
 103 static void r600_gpu_init(struct radeon_device *rdev);
 104 void r600_fini(struct radeon_device *rdev);
 105 void r600_irq_disable(struct radeon_device *rdev);
 106 static void r600_pcie_gen2_enable(struct radeon_device *rdev);
 107 extern int evergreen_rlc_resume(struct radeon_device *rdev);
 108
 109 /**
 110  * r600_get_xclk - get the xclk
 111  *
 112  * @rdev: radeon_device pointer
 113  *
 114  * Returns the reference clock used by the gfx engine
 115  * (r6xx, IGPs, APUs).
 116  */
 117 u32 r600_get_xclk(struct radeon_device *rdev)
 118 {
 119         return rdev->clock.spll.reference_freq;
 120 }
 121
 122 int r600_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)
 123 {
 124         return 0;
 125 }
 126
 127 void dce3_program_fmt(struct drm_encoder *encoder)
 128 {
 129         struct drm_device *dev = encoder->dev;
 130         struct radeon_device *rdev = dev->dev_private;
 131         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 132         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
 133         struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
 134         int bpc = 0;
 135         u32 tmp = 0;
 136         bool dither = false;
 137
 138         if (connector)
 139                 bpc = radeon_get_monitor_bpc(connector);
 140
 141         /* LVDS FMT is set up by atom */
 142         if (radeon_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
 143                 return;
 144
 145         /* not needed for analog */
 146         if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) ||
 147             (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2))
 148                 return;
 149
 150         if (bpc == 0)
 151                 return;
 152
 153         switch (bpc) {
 154         case 6:
 155                 if (dither)
 156                         /* XXX sort out optimal dither settings */
 157                         tmp |= FMT_SPATIAL_DITHER_EN;
 158                 else
 159                         tmp |= FMT_TRUNCATE_EN;
 160                 break;
 161         case 8:
 162                 if (dither)
 163                         /* XXX sort out optimal dither settings */
 164                         tmp |= (FMT_SPATIAL_DITHER_EN | FMT_SPATIAL_DITHER_DEPTH);
 165                 else
 166                         tmp |= (FMT_TRUNCATE_EN | FMT_TRUNCATE_DEPTH);
 167                 break;
 168         case 10:
 169         default:
 170                 /* not needed */
 171                 break;
 172         }
 173
 174         WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp);
 175 }
 176
 177 /* get temperature in millidegrees */
 178 int rv6xx_get_temp(struct radeon_device *rdev)
 179 {
 180         u32 temp = (RREG32(CG_THERMAL_STATUS) & ASIC_T_MASK) >>
 181                 ASIC_T_SHIFT;
 182         int actual_temp = temp & 0xff;
 183
 184         if (temp & 0x100)
 185                 actual_temp -= 256;
 186
 187         return actual_temp * 1000;
 188 }
 189
 190 void r600_pm_get_dynpm_state(struct radeon_device *rdev)
 191 {
 192         int i;
 193
 194         rdev->pm.dynpm_can_upclock = true;
 195         rdev->pm.dynpm_can_downclock = true;
 196
 197         /* power state array is low to high, default is first */
 198         if ((rdev->flags & RADEON_IS_IGP) || (rdev->family == CHIP_R600)) {
 199                 int min_power_state_index = 0;
 200
 201                 if (rdev->pm.num_power_states > 2)
 202                         min_power_state_index = 1;
 203
 204                 switch (rdev->pm.dynpm_planned_action) {
 205                 case DYNPM_ACTION_MINIMUM:
 206                         rdev->pm.requested_power_state_index = min_power_state_index;
 207                         rdev->pm.requested_clock_mode_index = 0;
 208                         rdev->pm.dynpm_can_downclock = false;
 209                         break;
 210                 case DYNPM_ACTION_DOWNCLOCK:
 211                         if (rdev->pm.current_power_state_index == min_power_state_index) {
 212                                 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
 213                                 rdev->pm.dynpm_can_downclock = false;
 214                         } else {
 215                                 if (rdev->pm.active_crtc_count > 1) {
 216                                         for (i = 0; i < rdev->pm.num_power_states; i++) {
 217                                                 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
 218                                                         continue;
 219                                                 else if (i >= rdev->pm.current_power_state_index) {
 220                                                         rdev->pm.requested_power_state_index =
 221                                                                 rdev->pm.current_power_state_index;
 222                                                         break;
 223                                                 } else {
 224                                                         rdev->pm.requested_power_state_index = i;
 225                                                         break;
 226                                                 }
 227                                         }
 228                                 } else {
 229                                         if (rdev->pm.current_power_state_index == 0)
 230                                                 rdev->pm.requested_power_state_index =
 231                                                         rdev->pm.num_power_states - 1;
 232                                         else
 233                                                 rdev->pm.requested_power_state_index =
 234                                                         rdev->pm.current_power_state_index - 1;
 235                                 }
 236                         }
 237                         rdev->pm.requested_clock_mode_index = 0;
 238                         /* don't use the power state if crtcs are active and no display flag is set */
 239                         if ((rdev->pm.active_crtc_count > 0) &&
 240                             (rdev->pm.power_state[rdev->pm.requested_power_state_index].
 241                              clock_info[rdev->pm.requested_clock_mode_index].flags &
 242                              RADEON_PM_MODE_NO_DISPLAY)) {
 243                                 rdev->pm.requested_power_state_index++;
 244                         }
 245                         break;
 246                 case DYNPM_ACTION_UPCLOCK:
 247                         if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) {
 248                                 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
 249                                 rdev->pm.dynpm_can_upclock = false;
 250                         } else {
 251                                 if (rdev->pm.active_crtc_count > 1) {
 252                                         for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) {
 253                                                 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
 254                                                         continue;
 255                                                 else if (i <= rdev->pm.current_power_state_index) {
 256                                                         rdev->pm.requested_power_state_index =
 257                                                                 rdev->pm.current_power_state_index;
 258                                                         break;
 259                                                 } else {
 260                                                         rdev->pm.requested_power_state_index = i;
 261                                                         break;
 262                                                 }
 263                                         }
 264                                 } else
 265                                         rdev->pm.requested_power_state_index =
 266                                                 rdev->pm.current_power_state_index + 1;
 267                         }
 268                         rdev->pm.requested_clock_mode_index = 0;
 269                         break;
 270                 case DYNPM_ACTION_DEFAULT:
 271                         rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
 272                         rdev->pm.requested_clock_mode_index = 0;
 273                         rdev->pm.dynpm_can_upclock = false;
 274                         break;
 275                 case DYNPM_ACTION_NONE:
 276                 default:
 277                         DRM_ERROR("Requested mode for not defined action\n");
 278                         return;
 279                 }
 280         } else {
 281                 /* XXX select a power state based on AC/DC, single/dualhead, etc. */
 282                 /* for now just select the first power state and switch between clock modes */
 283                 /* power state array is low to high, default is first (0) */
 284                 if (rdev->pm.active_crtc_count > 1) {
 285                         rdev->pm.requested_power_state_index = -1;
 286                         /* start at 1 as we don't want the default mode */
 287                         for (i = 1; i < rdev->pm.num_power_states; i++) {
 288                                 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
 289                                         continue;
 290                                 else if ((rdev->pm.power_state[i].type == POWER_STATE_TYPE_PERFORMANCE) ||
 291                                          (rdev->pm.power_state[i].type == POWER_STATE_TYPE_BATTERY)) {
 292                                         rdev->pm.requested_power_state_index = i;
 293                                         break;
 294                                 }
 295                         }
 296                         /* if nothing selected, grab the default state. */
 297                         if (rdev->pm.requested_power_state_index == -1)
 298                                 rdev->pm.requested_power_state_index = 0;
 299                 } else
 300                         rdev->pm.requested_power_state_index = 1;
 301
 302                 switch (rdev->pm.dynpm_planned_action) {
 303                 case DYNPM_ACTION_MINIMUM:
 304                         rdev->pm.requested_clock_mode_index = 0;
 305                         rdev->pm.dynpm_can_downclock = false;
 306                         break;
 307                 case DYNPM_ACTION_DOWNCLOCK:
 308                         if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) {
 309                                 if (rdev->pm.current_clock_mode_index == 0) {
 310                                         rdev->pm.requested_clock_mode_index = 0;
 311                                         rdev->pm.dynpm_can_downclock = false;
 312                                 } else
 313                                         rdev->pm.requested_clock_mode_index =
 314                                                 rdev->pm.current_clock_mode_index - 1;
 315                         } else {
 316                                 rdev->pm.requested_clock_mode_index = 0;
 317                                 rdev->pm.dynpm_can_downclock = false;
 318                         }
 319                         /* don't use the power state if crtcs are active and no display flag is set */
 320                         if ((rdev->pm.active_crtc_count > 0) &&
 321                             (rdev->pm.power_state[rdev->pm.requested_power_state_index].
 322                              clock_info[rdev->pm.requested_clock_mode_index].flags &
 323                              RADEON_PM_MODE_NO_DISPLAY)) {
 324                                 rdev->pm.requested_clock_mode_index++;
 325                         }
 326                         break;
 327                 case DYNPM_ACTION_UPCLOCK:
 328                         if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) {
 329                                 if (rdev->pm.current_clock_mode_index ==
 330                                     (rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1)) {
 331                                         rdev->pm.requested_clock_mode_index = rdev->pm.current_clock_mode_index;
 332                                         rdev->pm.dynpm_can_upclock = false;
 333                                 } else
 334                                         rdev->pm.requested_clock_mode_index =
 335                                                 rdev->pm.current_clock_mode_index + 1;
 336                         } else {
 337                                 rdev->pm.requested_clock_mode_index =
 338                                         rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1;
 339                                 rdev->pm.dynpm_can_upclock = false;
 340                         }
 341                         break;
 342                 case DYNPM_ACTION_DEFAULT:
 343                         rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
 344                         rdev->pm.requested_clock_mode_index = 0;
 345                         rdev->pm.dynpm_can_upclock = false;
 346                         break;
 347                 case DYNPM_ACTION_NONE:
 348                 default:
 349                         DRM_ERROR("Requested mode for not defined action\n");
 350                         return;
 351                 }
 352         }
 353
 354         DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n",
 355                   rdev->pm.power_state[rdev->pm.requested_power_state_index].
 356                   clock_info[rdev->pm.requested_clock_mode_index].sclk,
 357                   rdev->pm.power_state[rdev->pm.requested_power_state_index].
 358                   clock_info[rdev->pm.requested_clock_mode_index].mclk,
 359                   rdev->pm.power_state[rdev->pm.requested_power_state_index].
 360                   pcie_lanes);
 361 }
 362
 363 void rs780_pm_init_profile(struct radeon_device *rdev)
 364 {
 365         if (rdev->pm.num_power_states == 2) {
 366                 /* default */
 367                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 368                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 369                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 370                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
 371                 /* low sh */
 372                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0;
 373                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0;
 374                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 375                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 376                 /* mid sh */
 377                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0;
 378                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0;
 379                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 380                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
 381                 /* high sh */
 382                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0;
 383                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1;
 384                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 385                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
 386                 /* low mh */
 387                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0;
 388                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0;
 389                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 390                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 391                 /* mid mh */
 392                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0;
 393                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0;
 394                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 395                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
 396                 /* high mh */
 397                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0;
 398                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 1;
 399                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 400                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
 401         } else if (rdev->pm.num_power_states == 3) {
 402                 /* default */
 403                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 404                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 405                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 406                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
 407                 /* low sh */
 408                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1;
 409                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1;
 410                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 411                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 412                 /* mid sh */
 413                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1;
 414                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1;
 415                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 416                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
 417                 /* high sh */
 418                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1;
 419                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 2;
 420                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 421                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
 422                 /* low mh */
 423                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 1;
 424                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 1;
 425                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 426                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 427                 /* mid mh */
 428                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 1;
 429                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 1;
 430                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 431                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
 432                 /* high mh */
 433                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 1;
 434                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2;
 435                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 436                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
 437         } else {
 438                 /* default */
 439                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 440                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 441                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 442                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
 443                 /* low sh */
 444                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 2;
 445                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 2;
 446                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 447                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 448                 /* mid sh */
 449                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 2;
 450                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 2;
 451                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 452                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
 453                 /* high sh */
 454                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 2;
 455                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 3;
 456                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 457                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
 458                 /* low mh */
 459                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2;
 460                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0;
 461                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 462                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 463                 /* mid mh */
 464                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2;
 465                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0;
 466                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 467                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
 468                 /* high mh */
 469                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2;
 470                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 3;
 471                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 472                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
 473         }
 474 }
 475
 476 void r600_pm_init_profile(struct radeon_device *rdev)
 477 {
 478         int idx;
 479
 480         if (rdev->family == CHIP_R600) {
 481                 /* XXX */
 482                 /* default */
 483                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 484                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 485                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 486                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
 487                 /* low sh */
 488                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 489                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 490                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 491                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 492                 /* mid sh */
 493                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 494                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 495                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 496                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
 497                 /* high sh */
 498                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 499                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 500                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 501                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
 502                 /* low mh */
 503                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 504                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 505                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 506                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 507                 /* mid mh */
 508                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 509                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 510                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 511                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
 512                 /* high mh */
 513                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 514                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 515                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 516                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
 517         } else {
 518                 if (rdev->pm.num_power_states < 4) {
 519                         /* default */
 520                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 521                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 522                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 523                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2;
 524                         /* low sh */
 525                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1;
 526                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1;
 527                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 528                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 529                         /* mid sh */
 530                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1;
 531                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1;
 532                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 533                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
 534                         /* high sh */
 535                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1;
 536                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1;
 537                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 538                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2;
 539                         /* low mh */
 540                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2;
 541                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 2;
 542                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 543                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 544                         /* low mh */
 545                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2;
 546                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 2;
 547                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 548                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
 549                         /* high mh */
 550                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2;
 551                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2;
 552                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 553                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2;
 554                 } else {
 555                         /* default */
 556                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 557                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 558                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 559                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2;
 560                         /* low sh */
 561                         if (rdev->flags & RADEON_IS_MOBILITY)
 562                                 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
 563                         else
 564                                 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
 565                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = idx;
 566                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = idx;
 567                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 568                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 569                         /* mid sh */
 570                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = idx;
 571                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = idx;
 572                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 573                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
 574                         /* high sh */
 575                         idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
 576                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = idx;
 577                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = idx;
 578                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 579                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2;
 580                         /* low mh */
 581                         if (rdev->flags & RADEON_IS_MOBILITY)
 582                                 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1);
 583                         else
 584                                 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
 585                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = idx;
 586                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = idx;
 587                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 588                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 589                         /* mid mh */
 590                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = idx;
 591                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = idx;
 592                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 593                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
 594                         /* high mh */
 595                         idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
 596                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = idx;
 597                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = idx;
 598                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 599                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2;
 600                 }
 601         }
 602 }
 603
 604 void r600_pm_misc(struct radeon_device *rdev)
 605 {
 606         int req_ps_idx = rdev->pm.requested_power_state_index;
 607         int req_cm_idx = rdev->pm.requested_clock_mode_index;
 608         struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx];
 609         struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
 610
 611         if ((voltage->type == VOLTAGE_SW) && voltage->voltage) {
 612                 /* 0xff01 is a flag rather then an actual voltage */
 613                 if (voltage->voltage == 0xff01)
 614                         return;
 615                 if (voltage->voltage != rdev->pm.current_vddc) {
 616                         radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC);
 617                         rdev->pm.current_vddc = voltage->voltage;
 618                         DRM_DEBUG_DRIVER("Setting: v: %d\n", voltage->voltage);
 619                 }
 620         }
 621 }
 622
 623 bool r600_gui_idle(struct radeon_device *rdev)
 624 {
 625         if (RREG32(GRBM_STATUS) & GUI_ACTIVE)
 626                 return false;
 627         else
 628                 return true;
 629 }
 630
 631 /* hpd for digital panel detect/disconnect */
 632 bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
 633 {
 634         bool connected = false;
 635
 636         if (ASIC_IS_DCE3(rdev)) {
 637                 switch (hpd) {
 638                 case RADEON_HPD_1:
 639                         if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE)
 640                                 connected = true;
 641                         break;
 642                 case RADEON_HPD_2:
 643                         if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE)
 644                                 connected = true;
 645                         break;
 646                 case RADEON_HPD_3:
 647                         if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE)
 648                                 connected = true;
 649                         break;
 650                 case RADEON_HPD_4:
 651                         if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE)
 652                                 connected = true;
 653                         break;
 654                         /* DCE 3.2 */
 655                 case RADEON_HPD_5:
 656                         if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE)
 657                                 connected = true;
 658                         break;
 659                 case RADEON_HPD_6:
 660                         if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE)
 661                                 connected = true;
 662                         break;
 663                 default:
 664                         break;
 665                 }
 666         } else {
 667                 switch (hpd) {
 668                 case RADEON_HPD_1:
 669                         if (RREG32(DC_HOT_PLUG_DETECT1_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
 670                                 connected = true;
 671                         break;
 672                 case RADEON_HPD_2:
 673                         if (RREG32(DC_HOT_PLUG_DETECT2_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
 674                                 connected = true;
 675                         break;
 676                 case RADEON_HPD_3:
 677                         if (RREG32(DC_HOT_PLUG_DETECT3_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
 678                                 connected = true;
 679                         break;
 680                 default:
 681                         break;
 682                 }
 683         }
 684         return connected;
 685 }
 686
 687 void r600_hpd_set_polarity(struct radeon_device *rdev,
 688                            enum radeon_hpd_id hpd)
 689 {
 690         u32 tmp;
 691         bool connected = r600_hpd_sense(rdev, hpd);
 692
 693         if (ASIC_IS_DCE3(rdev)) {
 694                 switch (hpd) {
 695                 case RADEON_HPD_1:
 696                         tmp = RREG32(DC_HPD1_INT_CONTROL);
 697                         if (connected)
 698                                 tmp &= ~DC_HPDx_INT_POLARITY;
 699                         else
 700                                 tmp |= DC_HPDx_INT_POLARITY;
 701                         WREG32(DC_HPD1_INT_CONTROL, tmp);
 702                         break;
 703                 case RADEON_HPD_2:
 704                         tmp = RREG32(DC_HPD2_INT_CONTROL);
 705                         if (connected)
 706                                 tmp &= ~DC_HPDx_INT_POLARITY;
 707                         else
 708                                 tmp |= DC_HPDx_INT_POLARITY;
 709                         WREG32(DC_HPD2_INT_CONTROL, tmp);
 710                         break;
 711                 case RADEON_HPD_3:
 712                         tmp = RREG32(DC_HPD3_INT_CONTROL);
 713                         if (connected)
 714                                 tmp &= ~DC_HPDx_INT_POLARITY;
 715                         else
 716                                 tmp |= DC_HPDx_INT_POLARITY;
 717                         WREG32(DC_HPD3_INT_CONTROL, tmp);
 718                         break;
 719                 case RADEON_HPD_4:
 720                         tmp = RREG32(DC_HPD4_INT_CONTROL);
 721                         if (connected)
 722                                 tmp &= ~DC_HPDx_INT_POLARITY;
 723                         else
 724                                 tmp |= DC_HPDx_INT_POLARITY;
 725                         WREG32(DC_HPD4_INT_CONTROL, tmp);
 726                         break;
 727                 case RADEON_HPD_5:
 728                         tmp = RREG32(DC_HPD5_INT_CONTROL);
 729                         if (connected)
 730                                 tmp &= ~DC_HPDx_INT_POLARITY;
 731                         else
 732                                 tmp |= DC_HPDx_INT_POLARITY;
 733                         WREG32(DC_HPD5_INT_CONTROL, tmp);
 734                         break;
 735                         /* DCE 3.2 */
 736                 case RADEON_HPD_6:
 737                         tmp = RREG32(DC_HPD6_INT_CONTROL);
 738                         if (connected)
 739                                 tmp &= ~DC_HPDx_INT_POLARITY;
 740                         else
 741                                 tmp |= DC_HPDx_INT_POLARITY;
 742                         WREG32(DC_HPD6_INT_CONTROL, tmp);
 743                         break;
 744                 default:
 745                         break;
 746                 }
 747         } else {
 748                 switch (hpd) {
 749                 case RADEON_HPD_1:
 750                         tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
 751                         if (connected)
 752                                 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
 753                         else
 754                                 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
 755                         WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
 756                         break;
 757                 case RADEON_HPD_2:
 758                         tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
 759                         if (connected)
 760                                 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
 761                         else
 762                                 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
 763                         WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
 764                         break;
 765                 case RADEON_HPD_3:
 766                         tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
 767                         if (connected)
 768                                 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
 769                         else
 770                                 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
 771                         WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
 772                         break;
 773                 default:
 774                         break;
 775                 }
 776         }
 777 }
 778
 779 void r600_hpd_init(struct radeon_device *rdev)
 780 {
 781         struct drm_device *dev = rdev->ddev;
 782         struct drm_connector *connector;
 783         unsigned enable = 0;
 784
 785         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 786                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 787
 788                 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
 789                     connector->connector_type == DRM_MODE_CONNECTOR_LVDS) {
 790                         /* don't try to enable hpd on eDP or LVDS avoid breaking the
 791                          * aux dp channel on imac and help (but not completely fix)
 792                          * https://bugzilla.redhat.com/show_bug.cgi?id=726143
 793                          */
 794                         continue;
 795                 }
 796                 if (ASIC_IS_DCE3(rdev)) {
 797                         u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) | DC_HPDx_RX_INT_TIMER(0xfa);
 798                         if (ASIC_IS_DCE32(rdev))
 799                                 tmp |= DC_HPDx_EN;
 800
 801                         switch (radeon_connector->hpd.hpd) {
 802                         case RADEON_HPD_1:
 803                                 WREG32(DC_HPD1_CONTROL, tmp);
 804                                 break;
 805                         case RADEON_HPD_2:
 806                                 WREG32(DC_HPD2_CONTROL, tmp);
 807                                 break;
 808                         case RADEON_HPD_3:
 809                                 WREG32(DC_HPD3_CONTROL, tmp);
 810                                 break;
 811                         case RADEON_HPD_4:
 812                                 WREG32(DC_HPD4_CONTROL, tmp);
 813                                 break;
 814                                 /* DCE 3.2 */
 815                         case RADEON_HPD_5:
 816                                 WREG32(DC_HPD5_CONTROL, tmp);
 817                                 break;
 818                         case RADEON_HPD_6:
 819                                 WREG32(DC_HPD6_CONTROL, tmp);
 820                                 break;
 821                         default:
 822                                 break;
 823                         }
 824                 } else {
 825                         switch (radeon_connector->hpd.hpd) {
 826                         case RADEON_HPD_1:
 827                                 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, DC_HOT_PLUG_DETECTx_EN);
 828                                 break;
 829                         case RADEON_HPD_2:
 830                                 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, DC_HOT_PLUG_DETECTx_EN);
 831                                 break;
 832                         case RADEON_HPD_3:
 833                                 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, DC_HOT_PLUG_DETECTx_EN);
 834                                 break;
 835                         default:
 836                                 break;
 837                         }
 838                 }
 839                 enable |= 1 << radeon_connector->hpd.hpd;
 840                 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
 841         }
 842         radeon_irq_kms_enable_hpd(rdev, enable);
 843 }
 844
 845 void r600_hpd_fini(struct radeon_device *rdev)
 846 {
 847         struct drm_device *dev = rdev->ddev;
 848         struct drm_connector *connector;
 849         unsigned disable = 0;
 850
 851         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 852                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 853                 if (ASIC_IS_DCE3(rdev)) {
 854                         switch (radeon_connector->hpd.hpd) {
 855                         case RADEON_HPD_1:
 856                                 WREG32(DC_HPD1_CONTROL, 0);
 857                                 break;
 858                         case RADEON_HPD_2:
 859                                 WREG32(DC_HPD2_CONTROL, 0);
 860                                 break;
 861                         case RADEON_HPD_3:
 862                                 WREG32(DC_HPD3_CONTROL, 0);
 863                                 break;
 864                         case RADEON_HPD_4:
 865                                 WREG32(DC_HPD4_CONTROL, 0);
 866                                 break;
 867                                 /* DCE 3.2 */
 868                         case RADEON_HPD_5:
 869                                 WREG32(DC_HPD5_CONTROL, 0);
 870                                 break;
 871                         case RADEON_HPD_6:
 872                                 WREG32(DC_HPD6_CONTROL, 0);
 873                                 break;
 874                         default:
 875                                 break;
 876                         }
 877                 } else {
 878                         switch (radeon_connector->hpd.hpd) {
 879                         case RADEON_HPD_1:
 880                                 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, 0);
 881                                 break;
 882                         case RADEON_HPD_2:
 883                                 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, 0);
 884                                 break;
 885                         case RADEON_HPD_3:
 886                                 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, 0);
 887                                 break;
 888                         default:
 889                                 break;
 890                         }
 891                 }
 892                 disable |= 1 << radeon_connector->hpd.hpd;
 893         }
 894         radeon_irq_kms_disable_hpd(rdev, disable);
 895 }
 896
 897 /*
 898  * R600 PCIE GART
 899  */
 900 void r600_pcie_gart_tlb_flush(struct radeon_device *rdev)
 901 {
 902         unsigned i;
 903         u32 tmp;
 904
 905         /* flush hdp cache so updates hit vram */
 906         if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) &&
 907             !(rdev->flags & RADEON_IS_AGP)) {
 908                 void __iomem *ptr = (void *)rdev->gart.ptr;
 909                 u32 tmp;
 910
 911                 /* r7xx hw bug.  write to HDP_DEBUG1 followed by fb read
 912                  * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL
 913                  * This seems to cause problems on some AGP cards. Just use the old
 914                  * method for them.
 915                  */
 916                 WREG32(HDP_DEBUG1, 0);
 917                 tmp = readl((void __iomem *)ptr);
 918         } else
 919                 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
 920
 921         WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12);
 922         WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12);
 923         WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
 924         for (i = 0; i < rdev->usec_timeout; i++) {
 925                 /* read MC_STATUS */
 926                 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
 927                 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
 928                 if (tmp == 2) {
 929                         printk(KERN_WARNING "[drm] r600 flush TLB failed\n");
 930                         return;
 931                 }
 932                 if (tmp) {
 933                         return;
 934                 }
 935                 udelay(1);
 936         }
 937 }
 938
 939 int r600_pcie_gart_init(struct radeon_device *rdev)
 940 {
 941         int r;
 942
 943         if (rdev->gart.robj) {
 944                 WARN(1, "R600 PCIE GART already initialized\n");
 945                 return 0;
 946         }
 947         /* Initialize common gart structure */
 948         r = radeon_gart_init(rdev);
 949         if (r)
 950                 return r;
 951         rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
 952         return radeon_gart_table_vram_alloc(rdev);
 953 }
 954
 955 static int r600_pcie_gart_enable(struct radeon_device *rdev)
 956 {
 957         u32 tmp;
 958         int r, i;
 959
 960         if (rdev->gart.robj == NULL) {
 961                 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
 962                 return -EINVAL;
 963         }
 964         r = radeon_gart_table_vram_pin(rdev);
 965         if (r)
 966                 return r;
 967         radeon_gart_restore(rdev);
 968
 969         /* Setup L2 cache */
 970         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
 971                                 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
 972                                 EFFECTIVE_L2_QUEUE_SIZE(7));
 973         WREG32(VM_L2_CNTL2, 0);
 974         WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
 975         /* Setup TLB control */
 976         tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
 977                 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
 978                 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
 979                 ENABLE_WAIT_L2_QUERY;
 980         WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
 981         WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
 982         WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
 983         WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
 984         WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
 985         WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
 986         WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
 987         WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
 988         WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
 989         WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
 990         WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
 991         WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
 992         WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
 993         WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
 994         WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
 995         WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
 996         WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
 997         WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
 998                                 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
 999         WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
1000                         (u32)(rdev->dummy_page.addr >> 12));
1001         for (i = 1; i < 7; i++)
1002                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
1003
1004         r600_pcie_gart_tlb_flush(rdev);
1005         DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
1006                  (unsigned)(rdev->mc.gtt_size >> 20),
1007                  (unsigned long long)rdev->gart.table_addr);
1008         rdev->gart.ready = true;
1009         return 0;
1010 }
1011
1012 static void r600_pcie_gart_disable(struct radeon_device *rdev)
1013 {
1014         u32 tmp;
1015         int i;
1016
1017         /* Disable all tables */
1018         for (i = 0; i < 7; i++)
1019                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
1020
1021         /* Disable L2 cache */
1022         WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
1023                                 EFFECTIVE_L2_QUEUE_SIZE(7));
1024         WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
1025         /* Setup L1 TLB control */
1026         tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
1027                 ENABLE_WAIT_L2_QUERY;
1028         WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
1029         WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
1030         WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
1031         WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
1032         WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
1033         WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
1034         WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
1035         WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
1036         WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp);
1037         WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp);
1038         WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
1039         WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
1040         WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp);
1041         WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
1042         radeon_gart_table_vram_unpin(rdev);
1043 }
1044
1045 static void r600_pcie_gart_fini(struct radeon_device *rdev)
1046 {
1047         radeon_gart_fini(rdev);
1048         r600_pcie_gart_disable(rdev);
1049         radeon_gart_table_vram_free(rdev);
1050 }
1051
1052 static void r600_agp_enable(struct radeon_device *rdev)
1053 {
1054         u32 tmp;
1055         int i;
1056
1057         /* Setup L2 cache */
1058         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
1059                                 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
1060                                 EFFECTIVE_L2_QUEUE_SIZE(7));
1061         WREG32(VM_L2_CNTL2, 0);
1062         WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
1063         /* Setup TLB control */
1064         tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
1065                 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
1066                 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
1067                 ENABLE_WAIT_L2_QUERY;
1068         WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
1069         WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
1070         WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
1071         WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
1072         WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
1073         WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
1074         WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
1075         WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
1076         WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
1077         WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
1078         WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
1079         WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
1080         WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
1081         WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
1082         for (i = 0; i < 7; i++)
1083                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
1084 }
1085
1086 int r600_mc_wait_for_idle(struct radeon_device *rdev)
1087 {
1088         unsigned i;
1089         u32 tmp;
1090
1091         for (i = 0; i < rdev->usec_timeout; i++) {
1092                 /* read MC_STATUS */
1093                 tmp = RREG32(R_000E50_SRBM_STATUS) & 0x3F00;
1094                 if (!tmp)
1095                         return 0;
1096                 udelay(1);
1097         }
1098         return -1;
1099 }
1100
1101 uint32_t rs780_mc_rreg(struct radeon_device *rdev, uint32_t reg)
1102 {
1103         unsigned long flags;
1104         uint32_t r;
1105
1106         spin_lock_irqsave(&rdev->mc_idx_lock, flags);
1107         WREG32(R_0028F8_MC_INDEX, S_0028F8_MC_IND_ADDR(reg));
1108         r = RREG32(R_0028FC_MC_DATA);
1109         WREG32(R_0028F8_MC_INDEX, ~C_0028F8_MC_IND_ADDR);
1110         spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
1111         return r;
1112 }
1113
1114 void rs780_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
1115 {
1116         unsigned long flags;
1117
1118         spin_lock_irqsave(&rdev->mc_idx_lock, flags);
1119         WREG32(R_0028F8_MC_INDEX, S_0028F8_MC_IND_ADDR(reg) |
1120                 S_0028F8_MC_IND_WR_EN(1));
1121         WREG32(R_0028FC_MC_DATA, v);
1122         WREG32(R_0028F8_MC_INDEX, 0x7F);
1123         spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
1124 }
1125
1126 static void r600_mc_program(struct radeon_device *rdev)
1127 {
1128         struct rv515_mc_save save;
1129         u32 tmp;
1130         int i, j;
1131
1132         /* Initialize HDP */
1133         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1134                 WREG32((0x2c14 + j), 0x00000000);
1135                 WREG32((0x2c18 + j), 0x00000000);
1136                 WREG32((0x2c1c + j), 0x00000000);
1137                 WREG32((0x2c20 + j), 0x00000000);
1138                 WREG32((0x2c24 + j), 0x00000000);
1139         }
1140         WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
1141
1142         rv515_mc_stop(rdev, &save);
1143         if (r600_mc_wait_for_idle(rdev)) {
1144                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1145         }
1146         /* Lockout access through VGA aperture (doesn't exist before R600) */
1147         WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
1148         /* Update configuration */
1149         if (rdev->flags & RADEON_IS_AGP) {
1150                 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
1151                         /* VRAM before AGP */
1152                         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1153                                 rdev->mc.vram_start >> 12);
1154                         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1155                                 rdev->mc.gtt_end >> 12);
1156                 } else {
1157                         /* VRAM after AGP */
1158                         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1159                                 rdev->mc.gtt_start >> 12);
1160                         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1161                                 rdev->mc.vram_end >> 12);
1162                 }
1163         } else {
1164                 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12);
1165                 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end >> 12);
1166         }
1167         WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12);
1168         tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
1169         tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
1170         WREG32(MC_VM_FB_LOCATION, tmp);
1171         WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
1172         WREG32(HDP_NONSURFACE_INFO, (2 << 7));
1173         WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
1174         if (rdev->flags & RADEON_IS_AGP) {
1175                 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 22);
1176                 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 22);
1177                 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
1178         } else {
1179                 WREG32(MC_VM_AGP_BASE, 0);
1180                 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
1181                 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
1182         }
1183         if (r600_mc_wait_for_idle(rdev)) {
1184                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1185         }
1186         rv515_mc_resume(rdev, &save);
1187         /* we need to own VRAM, so turn off the VGA renderer here
1188          * to stop it overwriting our objects */
1189         rv515_vga_render_disable(rdev);
1190 }
1191
1192 /**
1193  * r600_vram_gtt_location - try to find VRAM & GTT location
1194  * @rdev: radeon device structure holding all necessary informations
1195  * @mc: memory controller structure holding memory informations
1196  *
1197  * Function will place try to place VRAM at same place as in CPU (PCI)
1198  * address space as some GPU seems to have issue when we reprogram at
1199  * different address space.
1200  *
1201  * If there is not enough space to fit the unvisible VRAM after the
1202  * aperture then we limit the VRAM size to the aperture.
1203  *
1204  * If we are using AGP then place VRAM adjacent to AGP aperture are we need
1205  * them to be in one from GPU point of view so that we can program GPU to
1206  * catch access outside them (weird GPU policy see ??).
1207  *
1208  * This function will never fails, worst case are limiting VRAM or GTT.
1209  *
1210  * Note: GTT start, end, size should be initialized before calling this
1211  * function on AGP platform.
1212  */
1213 static void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
1214 {
1215         u64 size_bf, size_af;
1216
1217         if (mc->mc_vram_size > 0xE0000000) {
1218                 /* leave room for at least 512M GTT */
1219                 dev_warn(rdev->dev, "limiting VRAM\n");
1220                 mc->real_vram_size = 0xE0000000;
1221                 mc->mc_vram_size = 0xE0000000;
1222         }
1223         if (rdev->flags & RADEON_IS_AGP) {
1224                 size_bf = mc->gtt_start;
1225                 size_af = mc->mc_mask - mc->gtt_end;
1226                 if (size_bf > size_af) {
1227                         if (mc->mc_vram_size > size_bf) {
1228                                 dev_warn(rdev->dev, "limiting VRAM\n");
1229                                 mc->real_vram_size = size_bf;
1230                                 mc->mc_vram_size = size_bf;
1231                         }
1232                         mc->vram_start = mc->gtt_start - mc->mc_vram_size;
1233                 } else {
1234                         if (mc->mc_vram_size > size_af) {
1235                                 dev_warn(rdev->dev, "limiting VRAM\n");
1236                                 mc->real_vram_size = size_af;
1237                                 mc->mc_vram_size = size_af;
1238                         }
1239                         mc->vram_start = mc->gtt_end + 1;
1240                 }
1241                 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
1242                 dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n",
1243                                 mc->mc_vram_size >> 20, mc->vram_start,
1244                                 mc->vram_end, mc->real_vram_size >> 20);
1245         } else {
1246                 u64 base = 0;
1247                 if (rdev->flags & RADEON_IS_IGP) {
1248                         base = RREG32(MC_VM_FB_LOCATION) & 0xFFFF;
1249                         base <<= 24;
1250                 }
1251                 radeon_vram_location(rdev, &rdev->mc, base);
1252                 rdev->mc.gtt_base_align = 0;
1253                 radeon_gtt_location(rdev, mc);
1254         }
1255 }
1256
1257 static int r600_mc_init(struct radeon_device *rdev)
1258 {
1259         u32 tmp;
1260         int chansize, numchan;
1261         uint32_t h_addr, l_addr;
1262         unsigned long long k8_addr;
1263
1264         /* Get VRAM informations */
1265         rdev->mc.vram_is_ddr = true;
1266         tmp = RREG32(RAMCFG);
1267         if (tmp & CHANSIZE_OVERRIDE) {
1268                 chansize = 16;
1269         } else if (tmp & CHANSIZE_MASK) {
1270                 chansize = 64;
1271         } else {
1272                 chansize = 32;
1273         }
1274         tmp = RREG32(CHMAP);
1275         switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
1276         case 0:
1277         default:
1278                 numchan = 1;
1279                 break;
1280         case 1:
1281                 numchan = 2;
1282                 break;
1283         case 2:
1284                 numchan = 4;
1285                 break;
1286         case 3:
1287                 numchan = 8;
1288                 break;
1289         }
1290         rdev->mc.vram_width = numchan * chansize;
1291         /* Could aper size report 0 ? */
1292         rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
1293         rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
1294         /* Setup GPU memory space */
1295         rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
1296         rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
1297         rdev->mc.visible_vram_size = rdev->mc.aper_size;
1298         r600_vram_gtt_location(rdev, &rdev->mc);
1299
1300         if (rdev->flags & RADEON_IS_IGP) {
1301                 rs690_pm_info(rdev);
1302                 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
1303
1304                 if (rdev->family == CHIP_RS780 || rdev->family == CHIP_RS880) {
1305                         /* Use K8 direct mapping for fast fb access. */
1306                         rdev->fastfb_working = false;
1307                         h_addr = G_000012_K8_ADDR_EXT(RREG32_MC(R_000012_MC_MISC_UMA_CNTL));
1308                         l_addr = RREG32_MC(R_000011_K8_FB_LOCATION);
1309                         k8_addr = ((unsigned long long)h_addr) << 32 | l_addr;
1310 #if defined(CONFIG_X86_32) && !defined(CONFIG_X86_PAE)
1311                         if (k8_addr + rdev->mc.visible_vram_size < 0x100000000ULL)
1312 #endif
1313                         {
1314                                 /* FastFB shall be used with UMA memory. Here it is simply disabled when sideport
1315                                 * memory is present.
1316                                 */
1317                                 if (rdev->mc.igp_sideport_enabled == false && radeon_fastfb == 1) {
1318                                         DRM_INFO("Direct mapping: aper base at 0x%llx, replaced by direct mapping base 0x%llx.\n",
1319                                                 (unsigned long long)rdev->mc.aper_base, k8_addr);
1320                                         rdev->mc.aper_base = (resource_size_t)k8_addr;
1321                                         rdev->fastfb_working = true;
1322                                 }
1323                         }
1324                 }
1325         }
1326
1327         radeon_update_bandwidth_info(rdev);
1328         return 0;
1329 }
1330
1331 int r600_vram_scratch_init(struct radeon_device *rdev)
1332 {
1333         int r;
1334
1335         if (rdev->vram_scratch.robj == NULL) {
1336                 r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE,
1337                                      PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM,
1338                                      NULL, &rdev->vram_scratch.robj);
1339                 if (r) {
1340                         return r;
1341                 }
1342         }
1343
1344         r = radeon_bo_reserve(rdev->vram_scratch.robj, false);
1345         if (unlikely(r != 0))
1346                 return r;
1347         r = radeon_bo_pin(rdev->vram_scratch.robj,
1348                           RADEON_GEM_DOMAIN_VRAM, &rdev->vram_scratch.gpu_addr);
1349         if (r) {
1350                 radeon_bo_unreserve(rdev->vram_scratch.robj);
1351                 return r;
1352         }
1353         r = radeon_bo_kmap(rdev->vram_scratch.robj,
1354                                 (void **)&rdev->vram_scratch.ptr);
1355         if (r)
1356                 radeon_bo_unpin(rdev->vram_scratch.robj);
1357         radeon_bo_unreserve(rdev->vram_scratch.robj);
1358
1359         return r;
1360 }
1361
1362 void r600_vram_scratch_fini(struct radeon_device *rdev)
1363 {
1364         int r;
1365
1366         if (rdev->vram_scratch.robj == NULL) {
1367                 return;
1368         }
1369         r = radeon_bo_reserve(rdev->vram_scratch.robj, false);
1370         if (likely(r == 0)) {
1371                 radeon_bo_kunmap(rdev->vram_scratch.robj);
1372                 radeon_bo_unpin(rdev->vram_scratch.robj);
1373                 radeon_bo_unreserve(rdev->vram_scratch.robj);
1374         }
1375         radeon_bo_unref(&rdev->vram_scratch.robj);
1376 }
1377
1378 void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung)
1379 {
1380         u32 tmp = RREG32(R600_BIOS_3_SCRATCH);
1381
1382         if (hung)
1383                 tmp |= ATOM_S3_ASIC_GUI_ENGINE_HUNG;
1384         else
1385                 tmp &= ~ATOM_S3_ASIC_GUI_ENGINE_HUNG;
1386
1387         WREG32(R600_BIOS_3_SCRATCH, tmp);
1388 }
1389
1390 static void r600_print_gpu_status_regs(struct radeon_device *rdev)
1391 {
1392         dev_info(rdev->dev, "  R_008010_GRBM_STATUS      = 0x%08X\n",
1393                  RREG32(R_008010_GRBM_STATUS));
1394         dev_info(rdev->dev, "  R_008014_GRBM_STATUS2     = 0x%08X\n",
1395                  RREG32(R_008014_GRBM_STATUS2));
1396         dev_info(rdev->dev, "  R_000E50_SRBM_STATUS      = 0x%08X\n",
1397                  RREG32(R_000E50_SRBM_STATUS));
1398         dev_info(rdev->dev, "  R_008674_CP_STALLED_STAT1 = 0x%08X\n",
1399                  RREG32(CP_STALLED_STAT1));
1400         dev_info(rdev->dev, "  R_008678_CP_STALLED_STAT2 = 0x%08X\n",
1401                  RREG32(CP_STALLED_STAT2));
1402         dev_info(rdev->dev, "  R_00867C_CP_BUSY_STAT     = 0x%08X\n",
1403                  RREG32(CP_BUSY_STAT));
1404         dev_info(rdev->dev, "  R_008680_CP_STAT          = 0x%08X\n",
1405                  RREG32(CP_STAT));
1406         dev_info(rdev->dev, "  R_00D034_DMA_STATUS_REG   = 0x%08X\n",
1407                 RREG32(DMA_STATUS_REG));
1408 }
1409
1410 static bool r600_is_display_hung(struct radeon_device *rdev)
1411 {
1412         u32 crtc_hung = 0;
1413         u32 crtc_status[2];
1414         u32 i, j, tmp;
1415
1416         for (i = 0; i < rdev->num_crtc; i++) {
1417                 if (RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]) & AVIVO_CRTC_EN) {
1418                         crtc_status[i] = RREG32(AVIVO_D1CRTC_STATUS_HV_COUNT + crtc_offsets[i]);
1419                         crtc_hung |= (1 << i);
1420                 }
1421         }
1422
1423         for (j = 0; j < 10; j++) {
1424                 for (i = 0; i < rdev->num_crtc; i++) {
1425                         if (crtc_hung & (1 << i)) {
1426                                 tmp = RREG32(AVIVO_D1CRTC_STATUS_HV_COUNT + crtc_offsets[i]);
1427                                 if (tmp != crtc_status[i])
1428                                         crtc_hung &= ~(1 << i);
1429                         }
1430                 }
1431                 if (crtc_hung == 0)
1432                         return false;
1433                 udelay(100);
1434         }
1435
1436         return true;
1437 }
1438
1439 u32 r600_gpu_check_soft_reset(struct radeon_device *rdev)
1440 {
1441         u32 reset_mask = 0;
1442         u32 tmp;
1443
1444         /* GRBM_STATUS */
1445         tmp = RREG32(R_008010_GRBM_STATUS);
1446         if (rdev->family >= CHIP_RV770) {
1447                 if (G_008010_PA_BUSY(tmp) | G_008010_SC_BUSY(tmp) |
1448                     G_008010_SH_BUSY(tmp) | G_008010_SX_BUSY(tmp) |
1449                     G_008010_TA_BUSY(tmp) | G_008010_VGT_BUSY(tmp) |
1450                     G_008010_DB03_BUSY(tmp) | G_008010_CB03_BUSY(tmp) |
1451                     G_008010_SPI03_BUSY(tmp) | G_008010_VGT_BUSY_NO_DMA(tmp))
1452                         reset_mask |= RADEON_RESET_GFX;
1453         } else {
1454                 if (G_008010_PA_BUSY(tmp) | G_008010_SC_BUSY(tmp) |
1455                     G_008010_SH_BUSY(tmp) | G_008010_SX_BUSY(tmp) |
1456                     G_008010_TA03_BUSY(tmp) | G_008010_VGT_BUSY(tmp) |
1457                     G_008010_DB03_BUSY(tmp) | G_008010_CB03_BUSY(tmp) |
1458                     G_008010_SPI03_BUSY(tmp) | G_008010_VGT_BUSY_NO_DMA(tmp))
1459                         reset_mask |= RADEON_RESET_GFX;
1460         }
1461
1462         if (G_008010_CF_RQ_PENDING(tmp) | G_008010_PF_RQ_PENDING(tmp) |
1463             G_008010_CP_BUSY(tmp) | G_008010_CP_COHERENCY_BUSY(tmp))
1464                 reset_mask |= RADEON_RESET_CP;
1465
1466         if (G_008010_GRBM_EE_BUSY(tmp))
1467                 reset_mask |= RADEON_RESET_GRBM | RADEON_RESET_GFX | RADEON_RESET_CP;
1468
1469         /* DMA_STATUS_REG */
1470         tmp = RREG32(DMA_STATUS_REG);
1471         if (!(tmp & DMA_IDLE))
1472                 reset_mask |= RADEON_RESET_DMA;
1473
1474         /* SRBM_STATUS */
1475         tmp = RREG32(R_000E50_SRBM_STATUS);
1476         if (G_000E50_RLC_RQ_PENDING(tmp) | G_000E50_RLC_BUSY(tmp))
1477                 reset_mask |= RADEON_RESET_RLC;
1478
1479         if (G_000E50_IH_BUSY(tmp))
1480                 reset_mask |= RADEON_RESET_IH;
1481
1482         if (G_000E50_SEM_BUSY(tmp))
1483                 reset_mask |= RADEON_RESET_SEM;
1484
1485         if (G_000E50_GRBM_RQ_PENDING(tmp))
1486                 reset_mask |= RADEON_RESET_GRBM;
1487
1488         if (G_000E50_VMC_BUSY(tmp))
1489                 reset_mask |= RADEON_RESET_VMC;
1490
1491         if (G_000E50_MCB_BUSY(tmp) | G_000E50_MCDZ_BUSY(tmp) |
1492             G_000E50_MCDY_BUSY(tmp) | G_000E50_MCDX_BUSY(tmp) |
1493             G_000E50_MCDW_BUSY(tmp))
1494                 reset_mask |= RADEON_RESET_MC;
1495
1496         if (r600_is_display_hung(rdev))
1497                 reset_mask |= RADEON_RESET_DISPLAY;
1498
1499         /* Skip MC reset as it's mostly likely not hung, just busy */
1500         if (reset_mask & RADEON_RESET_MC) {
1501                 DRM_DEBUG("MC busy: 0x%08X, clearing.\n", reset_mask);
1502                 reset_mask &= ~RADEON_RESET_MC;
1503         }
1504
1505         return reset_mask;
1506 }
1507
1508 static void r600_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)
1509 {
1510         struct rv515_mc_save save;
1511         u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
1512         u32 tmp;
1513
1514         if (reset_mask == 0)
1515                 return;
1516
1517         dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask);
1518
1519         r600_print_gpu_status_regs(rdev);
1520
1521         /* Disable CP parsing/prefetching */
1522         if (rdev->family >= CHIP_RV770)
1523                 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1) | S_0086D8_CP_PFP_HALT(1));
1524         else
1525                 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
1526
1527         /* disable the RLC */
1528         WREG32(RLC_CNTL, 0);
1529
1530         if (reset_mask & RADEON_RESET_DMA) {
1531                 /* Disable DMA */
1532                 tmp = RREG32(DMA_RB_CNTL);
1533                 tmp &= ~DMA_RB_ENABLE;
1534                 WREG32(DMA_RB_CNTL, tmp);
1535         }
1536
1537         mdelay(50);
1538
1539         rv515_mc_stop(rdev, &save);
1540         if (r600_mc_wait_for_idle(rdev)) {
1541                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1542         }
1543
1544         if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE)) {
1545                 if (rdev->family >= CHIP_RV770)
1546                         grbm_soft_reset |= S_008020_SOFT_RESET_DB(1) |
1547                                 S_008020_SOFT_RESET_CB(1) |
1548                                 S_008020_SOFT_RESET_PA(1) |
1549                                 S_008020_SOFT_RESET_SC(1) |
1550                                 S_008020_SOFT_RESET_SPI(1) |
1551                                 S_008020_SOFT_RESET_SX(1) |
1552                                 S_008020_SOFT_RESET_SH(1) |
1553                                 S_008020_SOFT_RESET_TC(1) |
1554                                 S_008020_SOFT_RESET_TA(1) |
1555                                 S_008020_SOFT_RESET_VC(1) |
1556                                 S_008020_SOFT_RESET_VGT(1);
1557                 else
1558                         grbm_soft_reset |= S_008020_SOFT_RESET_CR(1) |
1559                                 S_008020_SOFT_RESET_DB(1) |
1560                                 S_008020_SOFT_RESET_CB(1) |
1561                                 S_008020_SOFT_RESET_PA(1) |
1562                                 S_008020_SOFT_RESET_SC(1) |
1563                                 S_008020_SOFT_RESET_SMX(1) |
1564                                 S_008020_SOFT_RESET_SPI(1) |
1565                                 S_008020_SOFT_RESET_SX(1) |
1566                                 S_008020_SOFT_RESET_SH(1) |
1567                                 S_008020_SOFT_RESET_TC(1) |
1568                                 S_008020_SOFT_RESET_TA(1) |
1569                                 S_008020_SOFT_RESET_VC(1) |
1570                                 S_008020_SOFT_RESET_VGT(1);
1571         }
1572
1573         if (reset_mask & RADEON_RESET_CP) {
1574                 grbm_soft_reset |= S_008020_SOFT_RESET_CP(1) |
1575                         S_008020_SOFT_RESET_VGT(1);
1576
1577                 srbm_soft_reset |= S_000E60_SOFT_RESET_GRBM(1);
1578         }
1579
1580         if (reset_mask & RADEON_RESET_DMA) {
1581                 if (rdev->family >= CHIP_RV770)
1582                         srbm_soft_reset |= RV770_SOFT_RESET_DMA;
1583                 else
1584                         srbm_soft_reset |= SOFT_RESET_DMA;
1585         }
1586
1587         if (reset_mask & RADEON_RESET_RLC)
1588                 srbm_soft_reset |= S_000E60_SOFT_RESET_RLC(1);
1589
1590         if (reset_mask & RADEON_RESET_SEM)
1591                 srbm_soft_reset |= S_000E60_SOFT_RESET_SEM(1);
1592
1593         if (reset_mask & RADEON_RESET_IH)
1594                 srbm_soft_reset |= S_000E60_SOFT_RESET_IH(1);
1595
1596         if (reset_mask & RADEON_RESET_GRBM)
1597                 srbm_soft_reset |= S_000E60_SOFT_RESET_GRBM(1);
1598
1599         if (!(rdev->flags & RADEON_IS_IGP)) {
1600                 if (reset_mask & RADEON_RESET_MC)
1601                         srbm_soft_reset |= S_000E60_SOFT_RESET_MC(1);
1602         }
1603
1604         if (reset_mask & RADEON_RESET_VMC)
1605                 srbm_soft_reset |= S_000E60_SOFT_RESET_VMC(1);
1606
1607         if (grbm_soft_reset) {
1608                 tmp = RREG32(R_008020_GRBM_SOFT_RESET);
1609                 tmp |= grbm_soft_reset;
1610                 dev_info(rdev->dev, "R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
1611                 WREG32(R_008020_GRBM_SOFT_RESET, tmp);
1612                 tmp = RREG32(R_008020_GRBM_SOFT_RESET);
1613
1614                 udelay(50);
1615
1616                 tmp &= ~grbm_soft_reset;
1617                 WREG32(R_008020_GRBM_SOFT_RESET, tmp);
1618                 tmp = RREG32(R_008020_GRBM_SOFT_RESET);
1619         }
1620
1621         if (srbm_soft_reset) {
1622                 tmp = RREG32(SRBM_SOFT_RESET);
1623                 tmp |= srbm_soft_reset;
1624                 dev_info(rdev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1625                 WREG32(SRBM_SOFT_RESET, tmp);
1626                 tmp = RREG32(SRBM_SOFT_RESET);
1627
1628                 udelay(50);
1629
1630                 tmp &= ~srbm_soft_reset;
1631                 WREG32(SRBM_SOFT_RESET, tmp);
1632                 tmp = RREG32(SRBM_SOFT_RESET);
1633         }
1634
1635         /* Wait a little for things to settle down */
1636         mdelay(1);
1637
1638         rv515_mc_resume(rdev, &save);
1639         udelay(50);
1640
1641         r600_print_gpu_status_regs(rdev);
1642 }
1643
1644 int r600_asic_reset(struct radeon_device *rdev)
1645 {
1646         u32 reset_mask;
1647
1648         reset_mask = r600_gpu_check_soft_reset(rdev);
1649
1650         if (reset_mask)
1651                 r600_set_bios_scratch_engine_hung(rdev, true);
1652
1653         r600_gpu_soft_reset(rdev, reset_mask);
1654
1655         reset_mask = r600_gpu_check_soft_reset(rdev);
1656
1657         if (!reset_mask)
1658                 r600_set_bios_scratch_engine_hung(rdev, false);
1659
1660         return 0;
1661 }
1662
1663 /**
1664  * r600_gfx_is_lockup - Check if the GFX engine is locked up
1665  *
1666  * @rdev: radeon_device pointer
1667  * @ring: radeon_ring structure holding ring information
1668  *
1669  * Check if the GFX engine is locked up.
1670  * Returns true if the engine appears to be locked up, false if not.
1671  */
1672 bool r600_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
1673 {
1674         u32 reset_mask = r600_gpu_check_soft_reset(rdev);
1675
1676         if (!(reset_mask & (RADEON_RESET_GFX |
1677                             RADEON_RESET_COMPUTE |
1678                             RADEON_RESET_CP))) {
1679                 radeon_ring_lockup_update(ring);
1680                 return false;
1681         }
1682         /* force CP activities */
1683         radeon_ring_force_activity(rdev, ring);
1684         return radeon_ring_test_lockup(rdev, ring);
1685 }
1686
1687 u32 r6xx_remap_render_backend(struct radeon_device *rdev,
1688                               u32 tiling_pipe_num,
1689                               u32 max_rb_num,
1690                               u32 total_max_rb_num,
1691                               u32 disabled_rb_mask)
1692 {
1693         u32 rendering_pipe_num, rb_num_width, req_rb_num;
1694         u32 pipe_rb_ratio, pipe_rb_remain, tmp;
1695         u32 data = 0, mask = 1 << (max_rb_num - 1);
1696         unsigned i, j;
1697
1698         /* mask out the RBs that don't exist on that asic */
1699         tmp = disabled_rb_mask | ((0xff << max_rb_num) & 0xff);
1700         /* make sure at least one RB is available */
1701         if ((tmp & 0xff) != 0xff)
1702                 disabled_rb_mask = tmp;
1703
1704         rendering_pipe_num = 1 << tiling_pipe_num;
1705         req_rb_num = total_max_rb_num - r600_count_pipe_bits(disabled_rb_mask);
1706         BUG_ON(rendering_pipe_num < req_rb_num);
1707
1708         pipe_rb_ratio = rendering_pipe_num / req_rb_num;
1709         pipe_rb_remain = rendering_pipe_num - pipe_rb_ratio * req_rb_num;
1710
1711         if (rdev->family <= CHIP_RV740) {
1712                 /* r6xx/r7xx */
1713                 rb_num_width = 2;
1714         } else {
1715                 /* eg+ */
1716                 rb_num_width = 4;
1717         }
1718
1719         for (i = 0; i < max_rb_num; i++) {
1720                 if (!(mask & disabled_rb_mask)) {
1721                         for (j = 0; j < pipe_rb_ratio; j++) {
1722                                 data <<= rb_num_width;
1723                                 data |= max_rb_num - i - 1;
1724                         }
1725                         if (pipe_rb_remain) {
1726                                 data <<= rb_num_width;
1727                                 data |= max_rb_num - i - 1;
1728                                 pipe_rb_remain--;
1729                         }
1730                 }
1731                 mask >>= 1;
1732         }
1733
1734         return data;
1735 }
1736
1737 int r600_count_pipe_bits(uint32_t val)
1738 {
1739         return hweight32(val);
1740 }
1741
1742 static void r600_gpu_init(struct radeon_device *rdev)
1743 {
1744         u32 tiling_config;
1745         u32 ramcfg;
1746         u32 cc_rb_backend_disable;
1747         u32 cc_gc_shader_pipe_config;
1748         u32 tmp;
1749         int i, j;
1750         u32 sq_config;
1751         u32 sq_gpr_resource_mgmt_1 = 0;
1752         u32 sq_gpr_resource_mgmt_2 = 0;
1753         u32 sq_thread_resource_mgmt = 0;
1754         u32 sq_stack_resource_mgmt_1 = 0;
1755         u32 sq_stack_resource_mgmt_2 = 0;
1756         u32 disabled_rb_mask;
1757
1758         rdev->config.r600.tiling_group_size = 256;
1759         switch (rdev->family) {
1760         case CHIP_R600:
1761                 rdev->config.r600.max_pipes = 4;
1762                 rdev->config.r600.max_tile_pipes = 8;
1763                 rdev->config.r600.max_simds = 4;
1764                 rdev->config.r600.max_backends = 4;
1765                 rdev->config.r600.max_gprs = 256;
1766                 rdev->config.r600.max_threads = 192;
1767                 rdev->config.r600.max_stack_entries = 256;
1768                 rdev->config.r600.max_hw_contexts = 8;
1769                 rdev->config.r600.max_gs_threads = 16;
1770                 rdev->config.r600.sx_max_export_size = 128;
1771                 rdev->config.r600.sx_max_export_pos_size = 16;
1772                 rdev->config.r600.sx_max_export_smx_size = 128;
1773                 rdev->config.r600.sq_num_cf_insts = 2;
1774                 break;
1775         case CHIP_RV630:
1776         case CHIP_RV635:
1777                 rdev->config.r600.max_pipes = 2;
1778                 rdev->config.r600.max_tile_pipes = 2;
1779                 rdev->config.r600.max_simds = 3;
1780                 rdev->config.r600.max_backends = 1;
1781                 rdev->config.r600.max_gprs = 128;
1782                 rdev->config.r600.max_threads = 192;
1783                 rdev->config.r600.max_stack_entries = 128;
1784                 rdev->config.r600.max_hw_contexts = 8;
1785                 rdev->config.r600.max_gs_threads = 4;
1786                 rdev->config.r600.sx_max_export_size = 128;
1787                 rdev->config.r600.sx_max_export_pos_size = 16;
1788                 rdev->config.r600.sx_max_export_smx_size = 128;
1789                 rdev->config.r600.sq_num_cf_insts = 2;
1790                 break;
1791         case CHIP_RV610:
1792         case CHIP_RV620:
1793         case CHIP_RS780:
1794         case CHIP_RS880:
1795                 rdev->config.r600.max_pipes = 1;
1796                 rdev->config.r600.max_tile_pipes = 1;
1797                 rdev->config.r600.max_simds = 2;
1798                 rdev->config.r600.max_backends = 1;
1799                 rdev->config.r600.max_gprs = 128;
1800                 rdev->config.r600.max_threads = 192;
1801                 rdev->config.r600.max_stack_entries = 128;
1802                 rdev->config.r600.max_hw_contexts = 4;
1803                 rdev->config.r600.max_gs_threads = 4;
1804                 rdev->config.r600.sx_max_export_size = 128;
1805                 rdev->config.r600.sx_max_export_pos_size = 16;
1806                 rdev->config.r600.sx_max_export_smx_size = 128;
1807                 rdev->config.r600.sq_num_cf_insts = 1;
1808                 break;
1809         case CHIP_RV670:
1810                 rdev->config.r600.max_pipes = 4;
1811                 rdev->config.r600.max_tile_pipes = 4;
1812                 rdev->config.r600.max_simds = 4;
1813                 rdev->config.r600.max_backends = 4;
1814                 rdev->config.r600.max_gprs = 192;
1815                 rdev->config.r600.max_threads = 192;
1816                 rdev->config.r600.max_stack_entries = 256;
1817                 rdev->config.r600.max_hw_contexts = 8;
1818                 rdev->config.r600.max_gs_threads = 16;
1819                 rdev->config.r600.sx_max_export_size = 128;
1820                 rdev->config.r600.sx_max_export_pos_size = 16;
1821                 rdev->config.r600.sx_max_export_smx_size = 128;
1822                 rdev->config.r600.sq_num_cf_insts = 2;
1823                 break;
1824         default:
1825                 break;
1826         }
1827
1828         /* Initialize HDP */
1829         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1830                 WREG32((0x2c14 + j), 0x00000000);
1831                 WREG32((0x2c18 + j), 0x00000000);
1832                 WREG32((0x2c1c + j), 0x00000000);
1833                 WREG32((0x2c20 + j), 0x00000000);
1834                 WREG32((0x2c24 + j), 0x00000000);
1835         }
1836
1837         WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
1838
1839         /* Setup tiling */
1840         tiling_config = 0;
1841         ramcfg = RREG32(RAMCFG);
1842         switch (rdev->config.r600.max_tile_pipes) {
1843         case 1:
1844                 tiling_config |= PIPE_TILING(0);
1845                 break;
1846         case 2:
1847                 tiling_config |= PIPE_TILING(1);
1848                 break;
1849         case 4:
1850                 tiling_config |= PIPE_TILING(2);
1851                 break;
1852         case 8:
1853                 tiling_config |= PIPE_TILING(3);
1854                 break;
1855         default:
1856                 break;
1857         }
1858         rdev->config.r600.tiling_npipes = rdev->config.r600.max_tile_pipes;
1859         rdev->config.r600.tiling_nbanks = 4 << ((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
1860         tiling_config |= BANK_TILING((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
1861         tiling_config |= GROUP_SIZE((ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT);
1862
1863         tmp = (ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
1864         if (tmp > 3) {
1865                 tiling_config |= ROW_TILING(3);
1866                 tiling_config |= SAMPLE_SPLIT(3);
1867         } else {
1868                 tiling_config |= ROW_TILING(tmp);
1869                 tiling_config |= SAMPLE_SPLIT(tmp);
1870         }
1871         tiling_config |= BANK_SWAPS(1);
1872
1873         cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000;
1874         tmp = R6XX_MAX_BACKENDS -
1875                 r600_count_pipe_bits((cc_rb_backend_disable >> 16) & R6XX_MAX_BACKENDS_MASK);
1876         if (tmp < rdev->config.r600.max_backends) {
1877                 rdev->config.r600.max_backends = tmp;
1878         }
1879
1880         cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0x00ffff00;
1881         tmp = R6XX_MAX_PIPES -
1882                 r600_count_pipe_bits((cc_gc_shader_pipe_config >> 8) & R6XX_MAX_PIPES_MASK);
1883         if (tmp < rdev->config.r600.max_pipes) {
1884                 rdev->config.r600.max_pipes = tmp;
1885         }
1886         tmp = R6XX_MAX_SIMDS -
1887                 r600_count_pipe_bits((cc_gc_shader_pipe_config >> 16) & R6XX_MAX_SIMDS_MASK);
1888         if (tmp < rdev->config.r600.max_simds) {
1889                 rdev->config.r600.max_simds = tmp;
1890         }
1891
1892         disabled_rb_mask = (RREG32(CC_RB_BACKEND_DISABLE) >> 16) & R6XX_MAX_BACKENDS_MASK;
1893         tmp = (tiling_config & PIPE_TILING__MASK) >> PIPE_TILING__SHIFT;
1894         tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.r600.max_backends,
1895                                         R6XX_MAX_BACKENDS, disabled_rb_mask);
1896         tiling_config |= tmp << 16;
1897         rdev->config.r600.backend_map = tmp;
1898
1899         rdev->config.r600.tile_config = tiling_config;
1900         WREG32(GB_TILING_CONFIG, tiling_config);
1901         WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff);
1902         WREG32(HDP_TILING_CONFIG, tiling_config & 0xffff);
1903         WREG32(DMA_TILING_CONFIG, tiling_config & 0xffff);
1904
1905         tmp = R6XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8);
1906         WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK);
1907         WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((tmp * 4) - 2) & VTX_REUSE_DEPTH_MASK);
1908
1909         /* Setup some CP states */
1910         WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | ROQ_IB2_START(0x2b)));
1911         WREG32(CP_MEQ_THRESHOLDS, (MEQ_END(0x40) | ROQ_END(0x40)));
1912
1913         WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | SYNC_GRADIENT |
1914                              SYNC_WALKER | SYNC_ALIGNER));
1915         /* Setup various GPU states */
1916         if (rdev->family == CHIP_RV670)
1917                 WREG32(ARB_GDEC_RD_CNTL, 0x00000021);
1918
1919         tmp = RREG32(SX_DEBUG_1);
1920         tmp |= SMX_EVENT_RELEASE;
1921         if ((rdev->family > CHIP_R600))
1922                 tmp |= ENABLE_NEW_SMX_ADDRESS;
1923         WREG32(SX_DEBUG_1, tmp);
1924
1925         if (((rdev->family) == CHIP_R600) ||
1926             ((rdev->family) == CHIP_RV630) ||
1927             ((rdev->family) == CHIP_RV610) ||
1928             ((rdev->family) == CHIP_RV620) ||
1929             ((rdev->family) == CHIP_RS780) ||
1930             ((rdev->family) == CHIP_RS880)) {
1931                 WREG32(DB_DEBUG, PREZ_MUST_WAIT_FOR_POSTZ_DONE);
1932         } else {
1933                 WREG32(DB_DEBUG, 0);
1934         }
1935         WREG32(DB_WATERMARKS, (DEPTH_FREE(4) | DEPTH_CACHELINE_FREE(16) |
1936                                DEPTH_FLUSH(16) | DEPTH_PENDING_FREE(4)));
1937
1938         WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1939         WREG32(VGT_NUM_INSTANCES, 0);
1940
1941         WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0));
1942         WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(0));
1943
1944         tmp = RREG32(SQ_MS_FIFO_SIZES);
1945         if (((rdev->family) == CHIP_RV610) ||
1946             ((rdev->family) == CHIP_RV620) ||
1947             ((rdev->family) == CHIP_RS780) ||
1948             ((rdev->family) == CHIP_RS880)) {
1949                 tmp = (CACHE_FIFO_SIZE(0xa) |
1950                        FETCH_FIFO_HIWATER(0xa) |
1951                        DONE_FIFO_HIWATER(0xe0) |
1952                        ALU_UPDATE_FIFO_HIWATER(0x8));
1953         } else if (((rdev->family) == CHIP_R600) ||
1954                    ((rdev->family) == CHIP_RV630)) {
1955                 tmp &= ~DONE_FIFO_HIWATER(0xff);
1956                 tmp |= DONE_FIFO_HIWATER(0x4);
1957         }
1958         WREG32(SQ_MS_FIFO_SIZES, tmp);
1959
1960         /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
1961          * should be adjusted as needed by the 2D/3D drivers.  This just sets default values
1962          */
1963         sq_config = RREG32(SQ_CONFIG);
1964         sq_config &= ~(PS_PRIO(3) |
1965                        VS_PRIO(3) |
1966                        GS_PRIO(3) |
1967                        ES_PRIO(3));
1968         sq_config |= (DX9_CONSTS |
1969                       VC_ENABLE |
1970                       PS_PRIO(0) |
1971                       VS_PRIO(1) |
1972                       GS_PRIO(2) |
1973                       ES_PRIO(3));
1974
1975         if ((rdev->family) == CHIP_R600) {
1976                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(124) |
1977                                           NUM_VS_GPRS(124) |
1978                                           NUM_CLAUSE_TEMP_GPRS(4));
1979                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(0) |
1980                                           NUM_ES_GPRS(0));
1981                 sq_thread_resource_mgmt = (NUM_PS_THREADS(136) |
1982                                            NUM_VS_THREADS(48) |
1983                                            NUM_GS_THREADS(4) |
1984                                            NUM_ES_THREADS(4));
1985                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(128) |
1986                                             NUM_VS_STACK_ENTRIES(128));
1987                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(0) |
1988                                             NUM_ES_STACK_ENTRIES(0));
1989         } else if (((rdev->family) == CHIP_RV610) ||
1990                    ((rdev->family) == CHIP_RV620) ||
1991                    ((rdev->family) == CHIP_RS780) ||
1992                    ((rdev->family) == CHIP_RS880)) {
1993                 /* no vertex cache */
1994                 sq_config &= ~VC_ENABLE;
1995
1996                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1997                                           NUM_VS_GPRS(44) |
1998                                           NUM_CLAUSE_TEMP_GPRS(2));
1999                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
2000                                           NUM_ES_GPRS(17));
2001                 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
2002                                            NUM_VS_THREADS(78) |
2003                                            NUM_GS_THREADS(4) |
2004                                            NUM_ES_THREADS(31));
2005                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
2006                                             NUM_VS_STACK_ENTRIES(40));
2007                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
2008                                             NUM_ES_STACK_ENTRIES(16));
2009         } else if (((rdev->family) == CHIP_RV630) ||
2010                    ((rdev->family) == CHIP_RV635)) {
2011                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
2012                                           NUM_VS_GPRS(44) |
2013                                           NUM_CLAUSE_TEMP_GPRS(2));
2014                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(18) |
2015                                           NUM_ES_GPRS(18));
2016                 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
2017                                            NUM_VS_THREADS(78) |
2018                                            NUM_GS_THREADS(4) |
2019                                            NUM_ES_THREADS(31));
2020                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
2021                                             NUM_VS_STACK_ENTRIES(40));
2022                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
2023                                             NUM_ES_STACK_ENTRIES(16));
2024         } else if ((rdev->family) == CHIP_RV670) {
2025                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
2026                                           NUM_VS_GPRS(44) |
2027                                           NUM_CLAUSE_TEMP_GPRS(2));
2028                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
2029                                           NUM_ES_GPRS(17));
2030                 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
2031                                            NUM_VS_THREADS(78) |
2032                                            NUM_GS_THREADS(4) |
2033                                            NUM_ES_THREADS(31));
2034                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(64) |
2035                                             NUM_VS_STACK_ENTRIES(64));
2036                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(64) |
2037                                             NUM_ES_STACK_ENTRIES(64));
2038         }
2039
2040         WREG32(SQ_CONFIG, sq_config);
2041         WREG32(SQ_GPR_RESOURCE_MGMT_1,  sq_gpr_resource_mgmt_1);
2042         WREG32(SQ_GPR_RESOURCE_MGMT_2,  sq_gpr_resource_mgmt_2);
2043         WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
2044         WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
2045         WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
2046
2047         if (((rdev->family) == CHIP_RV610) ||
2048             ((rdev->family) == CHIP_RV620) ||
2049             ((rdev->family) == CHIP_RS780) ||
2050             ((rdev->family) == CHIP_RS880)) {
2051                 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(TC_ONLY));
2052         } else {
2053                 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC));
2054         }
2055
2056         /* More default values. 2D/3D driver should adjust as needed */
2057         WREG32(PA_SC_AA_SAMPLE_LOCS_2S, (S0_X(0xc) | S0_Y(0x4) |
2058                                          S1_X(0x4) | S1_Y(0xc)));
2059         WREG32(PA_SC_AA_SAMPLE_LOCS_4S, (S0_X(0xe) | S0_Y(0xe) |
2060                                          S1_X(0x2) | S1_Y(0x2) |
2061                                          S2_X(0xa) | S2_Y(0x6) |
2062                                          S3_X(0x6) | S3_Y(0xa)));
2063         WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD0, (S0_X(0xe) | S0_Y(0xb) |
2064                                              S1_X(0x4) | S1_Y(0xc) |
2065                                              S2_X(0x1) | S2_Y(0x6) |
2066                                              S3_X(0xa) | S3_Y(0xe)));
2067         WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD1, (S4_X(0x6) | S4_Y(0x1) |
2068                                              S5_X(0x0) | S5_Y(0x0) |
2069                                              S6_X(0xb) | S6_Y(0x4) |
2070                                              S7_X(0x7) | S7_Y(0x8)));
2071
2072         WREG32(VGT_STRMOUT_EN, 0);
2073         tmp = rdev->config.r600.max_pipes * 16;
2074         switch (rdev->family) {
2075         case CHIP_RV610:
2076         case CHIP_RV620:
2077         case CHIP_RS780:
2078         case CHIP_RS880:
2079                 tmp += 32;
2080                 break;
2081         case CHIP_RV670:
2082                 tmp += 128;
2083                 break;
2084         default:
2085                 break;
2086         }
2087         if (tmp > 256) {
2088                 tmp = 256;
2089         }
2090         WREG32(VGT_ES_PER_GS, 128);
2091         WREG32(VGT_GS_PER_ES, tmp);
2092         WREG32(VGT_GS_PER_VS, 2);
2093         WREG32(VGT_GS_VERTEX_REUSE, 16);
2094
2095         /* more default values. 2D/3D driver should adjust as needed */
2096         WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
2097         WREG32(VGT_STRMOUT_EN, 0);
2098         WREG32(SX_MISC, 0);
2099         WREG32(PA_SC_MODE_CNTL, 0);
2100         WREG32(PA_SC_AA_CONFIG, 0);
2101         WREG32(PA_SC_LINE_STIPPLE, 0);
2102         WREG32(SPI_INPUT_Z, 0);
2103         WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));
2104         WREG32(CB_COLOR7_FRAG, 0);
2105
2106         /* Clear render buffer base addresses */
2107         WREG32(CB_COLOR0_BASE, 0);
2108         WREG32(CB_COLOR1_BASE, 0);
2109         WREG32(CB_COLOR2_BASE, 0);
2110         WREG32(CB_COLOR3_BASE, 0);
2111         WREG32(CB_COLOR4_BASE, 0);
2112         WREG32(CB_COLOR5_BASE, 0);
2113         WREG32(CB_COLOR6_BASE, 0);
2114         WREG32(CB_COLOR7_BASE, 0);
2115         WREG32(CB_COLOR7_FRAG, 0);
2116
2117         switch (rdev->family) {
2118         case CHIP_RV610:
2119         case CHIP_RV620:
2120         case CHIP_RS780:
2121         case CHIP_RS880:
2122                 tmp = TC_L2_SIZE(8);
2123                 break;
2124         case CHIP_RV630:
2125         case CHIP_RV635:
2126                 tmp = TC_L2_SIZE(4);
2127                 break;
2128         case CHIP_R600:
2129                 tmp = TC_L2_SIZE(0) | L2_DISABLE_LATE_HIT;
2130                 break;
2131         default:
2132                 tmp = TC_L2_SIZE(0);
2133                 break;
2134         }
2135         WREG32(TC_CNTL, tmp);
2136
2137         tmp = RREG32(HDP_HOST_PATH_CNTL);
2138         WREG32(HDP_HOST_PATH_CNTL, tmp);
2139
2140         tmp = RREG32(ARB_POP);
2141         tmp |= ENABLE_TC128;
2142         WREG32(ARB_POP, tmp);
2143
2144         WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
2145         WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
2146                                NUM_CLIP_SEQ(3)));
2147         WREG32(PA_SC_ENHANCE, FORCE_EOV_MAX_CLK_CNT(4095));
2148         WREG32(VC_ENHANCE, 0);
2149 }
2150
2151
2152 /*
2153  * Indirect registers accessor
2154  */
2155 u32 r600_pciep_rreg(struct radeon_device *rdev, u32 reg)
2156 {
2157         unsigned long flags;
2158         u32 r;
2159
2160         spin_lock_irqsave(&rdev->pciep_idx_lock, flags);
2161         WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
2162         (void)RREG32(PCIE_PORT_INDEX);
2163         r = RREG32(PCIE_PORT_DATA);
2164         spin_unlock_irqrestore(&rdev->pciep_idx_lock, flags);
2165         return r;
2166 }
2167
2168 void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2169 {
2170         unsigned long flags;
2171
2172         spin_lock_irqsave(&rdev->pciep_idx_lock, flags);
2173         WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
2174         (void)RREG32(PCIE_PORT_INDEX);
2175         WREG32(PCIE_PORT_DATA, (v));
2176         (void)RREG32(PCIE_PORT_DATA);
2177         spin_unlock_irqrestore(&rdev->pciep_idx_lock, flags);
2178 }
2179
2180 /*
2181  * CP & Ring
2182  */
2183 void r600_cp_stop(struct radeon_device *rdev)
2184 {
2185         radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
2186         WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
2187         WREG32(SCRATCH_UMSK, 0);
2188         rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
2189 }
2190
2191 int r600_init_microcode(struct radeon_device *rdev)
2192 {
2193         const char *chip_name;
2194         const char *rlc_chip_name;
2195         const char *smc_chip_name = "RV770";
2196         size_t pfp_req_size, me_req_size, rlc_req_size, smc_req_size = 0;
2197         char fw_name[30];
2198         int err;
2199
2200         DRM_DEBUG("\n");
2201
2202         switch (rdev->family) {
2203         case CHIP_R600:
2204                 chip_name = "R600";
2205                 rlc_chip_name = "R600";
2206                 break;
2207         case CHIP_RV610:
2208                 chip_name = "RV610";
2209                 rlc_chip_name = "R600";
2210                 break;
2211         case CHIP_RV630:
2212                 chip_name = "RV630";
2213                 rlc_chip_name = "R600";
2214                 break;
2215         case CHIP_RV620:
2216                 chip_name = "RV620";
2217                 rlc_chip_name = "R600";
2218                 break;
2219         case CHIP_RV635:
2220                 chip_name = "RV635";
2221                 rlc_chip_name = "R600";
2222                 break;
2223         case CHIP_RV670:
2224                 chip_name = "RV670";
2225                 rlc_chip_name = "R600";
2226                 break;
2227         case CHIP_RS780:
2228         case CHIP_RS880:
2229                 chip_name = "RS780";
2230                 rlc_chip_name = "R600";
2231                 break;
2232         case CHIP_RV770:
2233                 chip_name = "RV770";
2234                 rlc_chip_name = "R700";
2235                 smc_chip_name = "RV770";
2236                 smc_req_size = ALIGN(RV770_SMC_UCODE_SIZE, 4);
2237                 break;
2238         case CHIP_RV730:
2239                 chip_name = "RV730";
2240                 rlc_chip_name = "R700";
2241                 smc_chip_name = "RV730";
2242                 smc_req_size = ALIGN(RV730_SMC_UCODE_SIZE, 4);
2243                 break;
2244         case CHIP_RV710:
2245                 chip_name = "RV710";
2246                 rlc_chip_name = "R700";
2247                 smc_chip_name = "RV710";
2248                 smc_req_size = ALIGN(RV710_SMC_UCODE_SIZE, 4);
2249                 break;
2250         case CHIP_RV740:
2251                 chip_name = "RV730";
2252                 rlc_chip_name = "R700";
2253                 smc_chip_name = "RV740";
2254                 smc_req_size = ALIGN(RV740_SMC_UCODE_SIZE, 4);
2255                 break;
2256         case CHIP_CEDAR:
2257                 chip_name = "CEDAR";
2258                 rlc_chip_name = "CEDAR";
2259                 smc_chip_name = "CEDAR";
2260                 smc_req_size = ALIGN(CEDAR_SMC_UCODE_SIZE, 4);
2261                 break;
2262         case CHIP_REDWOOD:
2263                 chip_name = "REDWOOD";
2264                 rlc_chip_name = "REDWOOD";
2265                 smc_chip_name = "REDWOOD";
2266                 smc_req_size = ALIGN(REDWOOD_SMC_UCODE_SIZE, 4);
2267                 break;
2268         case CHIP_JUNIPER:
2269                 chip_name = "JUNIPER";
2270                 rlc_chip_name = "JUNIPER";
2271                 smc_chip_name = "JUNIPER";
2272                 smc_req_size = ALIGN(JUNIPER_SMC_UCODE_SIZE, 4);
2273                 break;
2274         case CHIP_CYPRESS:
2275         case CHIP_HEMLOCK:
2276                 chip_name = "CYPRESS";
2277                 rlc_chip_name = "CYPRESS";
2278                 smc_chip_name = "CYPRESS";
2279                 smc_req_size = ALIGN(CYPRESS_SMC_UCODE_SIZE, 4);
2280                 break;
2281         case CHIP_PALM:
2282                 chip_name = "PALM";
2283                 rlc_chip_name = "SUMO";
2284                 break;
2285         case CHIP_SUMO:
2286                 chip_name = "SUMO";
2287                 rlc_chip_name = "SUMO";
2288                 break;
2289         case CHIP_SUMO2:
2290                 chip_name = "SUMO2";
2291                 rlc_chip_name = "SUMO";
2292                 break;
2293         default: BUG();
2294         }
2295
2296         if (rdev->family >= CHIP_CEDAR) {
2297                 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
2298                 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
2299                 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
2300         } else if (rdev->family >= CHIP_RV770) {
2301                 pfp_req_size = R700_PFP_UCODE_SIZE * 4;
2302                 me_req_size = R700_PM4_UCODE_SIZE * 4;
2303                 rlc_req_size = R700_RLC_UCODE_SIZE * 4;
2304         } else {
2305                 pfp_req_size = R600_PFP_UCODE_SIZE * 4;
2306                 me_req_size = R600_PM4_UCODE_SIZE * 12;
2307                 rlc_req_size = R600_RLC_UCODE_SIZE * 4;
2308         }
2309
2310         DRM_INFO("Loading %s Microcode\n", chip_name);
2311
2312         snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
2313         err = request_firmware(&rdev->pfp_fw, fw_name, rdev->dev);
2314         if (err)
2315                 goto out;
2316         if (rdev->pfp_fw->size != pfp_req_size) {
2317                 printk(KERN_ERR
2318                        "r600_cp: Bogus length %zu in firmware \"%s\"\n",
2319                        rdev->pfp_fw->size, fw_name);
2320                 err = -EINVAL;
2321                 goto out;
2322         }
2323
2324         snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
2325         err = request_firmware(&rdev->me_fw, fw_name, rdev->dev);
2326         if (err)
2327                 goto out;
2328         if (rdev->me_fw->size != me_req_size) {
2329                 printk(KERN_ERR
2330                        "r600_cp: Bogus length %zu in firmware \"%s\"\n",
2331                        rdev->me_fw->size, fw_name);
2332                 err = -EINVAL;
2333         }
2334
2335         snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name);
2336         err = request_firmware(&rdev->rlc_fw, fw_name, rdev->dev);
2337         if (err)
2338                 goto out;
2339         if (rdev->rlc_fw->size != rlc_req_size) {
2340                 printk(KERN_ERR
2341                        "r600_rlc: Bogus length %zu in firmware \"%s\"\n",
2342                        rdev->rlc_fw->size, fw_name);
2343                 err = -EINVAL;
2344         }
2345
2346         if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_HEMLOCK)) {
2347                 snprintf(fw_name, sizeof(fw_name), "radeon/%s_smc.bin", smc_chip_name);
2348                 err = request_firmware(&rdev->smc_fw, fw_name, rdev->dev);
2349                 if (err) {
2350                         printk(KERN_ERR
2351                                "smc: error loading firmware \"%s\"\n",
2352                                fw_name);
2353                         release_firmware(rdev->smc_fw);
2354                         rdev->smc_fw = NULL;
2355                 } else if (rdev->smc_fw->size != smc_req_size) {
2356                         printk(KERN_ERR
2357                                "smc: Bogus length %zu in firmware \"%s\"\n",
2358                                rdev->smc_fw->size, fw_name);
2359                         err = -EINVAL;
2360                 }
2361         }
2362
2363 out:
2364         if (err) {
2365                 if (err != -EINVAL)
2366                         printk(KERN_ERR
2367                                "r600_cp: Failed to load firmware \"%s\"\n",
2368                                fw_name);
2369                 release_firmware(rdev->pfp_fw);
2370                 rdev->pfp_fw = NULL;
2371                 release_firmware(rdev->me_fw);
2372                 rdev->me_fw = NULL;
2373                 release_firmware(rdev->rlc_fw);
2374                 rdev->rlc_fw = NULL;
2375                 release_firmware(rdev->smc_fw);
2376                 rdev->smc_fw = NULL;
2377         }
2378         return err;
2379 }
2380
2381 static int r600_cp_load_microcode(struct radeon_device *rdev)
2382 {
2383         const __be32 *fw_data;
2384         int i;
2385
2386         if (!rdev->me_fw || !rdev->pfp_fw)
2387                 return -EINVAL;
2388
2389         r600_cp_stop(rdev);
2390
2391         WREG32(CP_RB_CNTL,
2392 #ifdef __BIG_ENDIAN
2393                BUF_SWAP_32BIT |
2394 #endif
2395                RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
2396
2397         /* Reset cp */
2398         WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
2399         RREG32(GRBM_SOFT_RESET);
2400         mdelay(15);
2401         WREG32(GRBM_SOFT_RESET, 0);
2402
2403         WREG32(CP_ME_RAM_WADDR, 0);
2404
2405         fw_data = (const __be32 *)rdev->me_fw->data;
2406         WREG32(CP_ME_RAM_WADDR, 0);
2407         for (i = 0; i < R600_PM4_UCODE_SIZE * 3; i++)
2408                 WREG32(CP_ME_RAM_DATA,
2409                        be32_to_cpup(fw_data++));
2410
2411         fw_data = (const __be32 *)rdev->pfp_fw->data;
2412         WREG32(CP_PFP_UCODE_ADDR, 0);
2413         for (i = 0; i < R600_PFP_UCODE_SIZE; i++)
2414                 WREG32(CP_PFP_UCODE_DATA,
2415                        be32_to_cpup(fw_data++));
2416
2417         WREG32(CP_PFP_UCODE_ADDR, 0);
2418         WREG32(CP_ME_RAM_WADDR, 0);
2419         WREG32(CP_ME_RAM_RADDR, 0);
2420         return 0;
2421 }
2422
2423 int r600_cp_start(struct radeon_device *rdev)
2424 {
2425         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2426         int r;
2427         uint32_t cp_me;
2428
2429         r = radeon_ring_lock(rdev, ring, 7);
2430         if (r) {
2431                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
2432                 return r;
2433         }
2434         radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));
2435         radeon_ring_write(ring, 0x1);
2436         if (rdev->family >= CHIP_RV770) {
2437                 radeon_ring_write(ring, 0x0);
2438                 radeon_ring_write(ring, rdev->config.rv770.max_hw_contexts - 1);
2439         } else {
2440                 radeon_ring_write(ring, 0x3);
2441                 radeon_ring_write(ring, rdev->config.r600.max_hw_contexts - 1);
2442         }
2443         radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
2444         radeon_ring_write(ring, 0);
2445         radeon_ring_write(ring, 0);
2446         radeon_ring_unlock_commit(rdev, ring);
2447
2448         cp_me = 0xff;
2449         WREG32(R_0086D8_CP_ME_CNTL, cp_me);
2450         return 0;
2451 }
2452
2453 int r600_cp_resume(struct radeon_device *rdev)
2454 {
2455         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2456         u32 tmp;
2457         u32 rb_bufsz;
2458         int r;
2459
2460         /* Reset cp */
2461         WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
2462         RREG32(GRBM_SOFT_RESET);
2463         mdelay(15);
2464         WREG32(GRBM_SOFT_RESET, 0);
2465
2466         /* Set ring buffer size */
2467         rb_bufsz = order_base_2(ring->ring_size / 8);
2468         tmp = (order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2469 #ifdef __BIG_ENDIAN
2470         tmp |= BUF_SWAP_32BIT;
2471 #endif
2472         WREG32(CP_RB_CNTL, tmp);
2473         WREG32(CP_SEM_WAIT_TIMER, 0x0);
2474
2475         /* Set the write pointer delay */
2476         WREG32(CP_RB_WPTR_DELAY, 0);
2477
2478         /* Initialize the ring buffer's read and write pointers */
2479         WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
2480         WREG32(CP_RB_RPTR_WR, 0);
2481         ring->wptr = 0;
2482         WREG32(CP_RB_WPTR, ring->wptr);
2483
2484         /* set the wb address whether it's enabled or not */
2485         WREG32(CP_RB_RPTR_ADDR,
2486                ((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC));
2487         WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
2488         WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
2489
2490         if (rdev->wb.enabled)
2491                 WREG32(SCRATCH_UMSK, 0xff);
2492         else {
2493                 tmp |= RB_NO_UPDATE;
2494                 WREG32(SCRATCH_UMSK, 0);
2495         }
2496
2497         mdelay(1);
2498         WREG32(CP_RB_CNTL, tmp);
2499
2500         WREG32(CP_RB_BASE, ring->gpu_addr >> 8);
2501         WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
2502
2503         ring->rptr = RREG32(CP_RB_RPTR);
2504
2505         r600_cp_start(rdev);
2506         ring->ready = true;
2507         r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring);
2508         if (r) {
2509                 ring->ready = false;
2510                 return r;
2511         }
2512         return 0;
2513 }
2514
2515 void r600_ring_init(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ring_size)
2516 {
2517         u32 rb_bufsz;
2518         int r;
2519
2520         /* Align ring size */
2521         rb_bufsz = order_base_2(ring_size / 8);
2522         ring_size = (1 << (rb_bufsz + 1)) * 4;
2523         ring->ring_size = ring_size;
2524         ring->align_mask = 16 - 1;
2525
2526         if (radeon_ring_supports_scratch_reg(rdev, ring)) {
2527                 r = radeon_scratch_get(rdev, &ring->rptr_save_reg);
2528                 if (r) {
2529                         DRM_ERROR("failed to get scratch reg for rptr save (%d).\n", r);
2530                         ring->rptr_save_reg = 0;
2531                 }
2532         }
2533 }
2534
2535 void r600_cp_fini(struct radeon_device *rdev)
2536 {
2537         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2538         r600_cp_stop(rdev);
2539         radeon_ring_fini(rdev, ring);
2540         radeon_scratch_free(rdev, ring->rptr_save_reg);
2541 }
2542
2543 /*
2544  * GPU scratch registers helpers function.
2545  */
2546 void r600_scratch_init(struct radeon_device *rdev)
2547 {
2548         int i;
2549
2550         rdev->scratch.num_reg = 7;
2551         rdev->scratch.reg_base = SCRATCH_REG0;
2552         for (i = 0; i < rdev->scratch.num_reg; i++) {
2553                 rdev->scratch.free[i] = true;
2554                 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);
2555         }
2556 }
2557
2558 int r600_ring_test(struct radeon_device *rdev, struct radeon_ring *ring)
2559 {
2560         uint32_t scratch;
2561         uint32_t tmp = 0;
2562         unsigned i;
2563         int r;
2564
2565         r = radeon_scratch_get(rdev, &scratch);
2566         if (r) {
2567                 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
2568                 return r;
2569         }
2570         WREG32(scratch, 0xCAFEDEAD);
2571         r = radeon_ring_lock(rdev, ring, 3);
2572         if (r) {
2573                 DRM_ERROR("radeon: cp failed to lock ring %d (%d).\n", ring->idx, r);
2574                 radeon_scratch_free(rdev, scratch);
2575                 return r;
2576         }
2577         radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2578         radeon_ring_write(ring, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
2579         radeon_ring_write(ring, 0xDEADBEEF);
2580         radeon_ring_unlock_commit(rdev, ring);
2581         for (i = 0; i < rdev->usec_timeout; i++) {
2582                 tmp = RREG32(scratch);
2583                 if (tmp == 0xDEADBEEF)
2584                         break;
2585                 DRM_UDELAY(1);
2586         }
2587         if (i < rdev->usec_timeout) {
2588                 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
2589         } else {
2590                 DRM_ERROR("radeon: ring %d test failed (scratch(0x%04X)=0x%08X)\n",
2591                           ring->idx, scratch, tmp);
2592                 r = -EINVAL;
2593         }
2594         radeon_scratch_free(rdev, scratch);
2595         return r;
2596 }
2597
2598 /*
2599  * CP fences/semaphores
2600  */
2601
2602 void r600_fence_ring_emit(struct radeon_device *rdev,
2603                           struct radeon_fence *fence)
2604 {
2605         struct radeon_ring *ring = &rdev->ring[fence->ring];
2606
2607         if (rdev->wb.use_event) {
2608                 u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
2609                 /* flush read cache over gart */
2610                 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
2611                 radeon_ring_write(ring, PACKET3_TC_ACTION_ENA |
2612                                         PACKET3_VC_ACTION_ENA |
2613                                         PACKET3_SH_ACTION_ENA);
2614                 radeon_ring_write(ring, 0xFFFFFFFF);
2615                 radeon_ring_write(ring, 0);
2616                 radeon_ring_write(ring, 10); /* poll interval */
2617                 /* EVENT_WRITE_EOP - flush caches, send int */
2618                 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
2619                 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5));
2620                 radeon_ring_write(ring, addr & 0xffffffff);
2621                 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2));
2622                 radeon_ring_write(ring, fence->seq);
2623                 radeon_ring_write(ring, 0);
2624         } else {
2625                 /* flush read cache over gart */
2626                 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
2627                 radeon_ring_write(ring, PACKET3_TC_ACTION_ENA |
2628                                         PACKET3_VC_ACTION_ENA |
2629                                         PACKET3_SH_ACTION_ENA);
2630                 radeon_ring_write(ring, 0xFFFFFFFF);
2631                 radeon_ring_write(ring, 0);
2632                 radeon_ring_write(ring, 10); /* poll interval */
2633                 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0));
2634                 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0));
2635                 /* wait for 3D idle clean */
2636                 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2637                 radeon_ring_write(ring, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
2638                 radeon_ring_write(ring, WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit);
2639                 /* Emit fence sequence & fire IRQ */
2640                 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2641                 radeon_ring_write(ring, ((rdev->fence_drv[fence->ring].scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
2642                 radeon_ring_write(ring, fence->seq);
2643                 /* CP_INTERRUPT packet 3 no longer exists, use packet 0 */
2644                 radeon_ring_write(ring, PACKET0(CP_INT_STATUS, 0));
2645                 radeon_ring_write(ring, RB_INT_STAT);
2646         }
2647 }
2648
2649 void r600_semaphore_ring_emit(struct radeon_device *rdev,
2650                               struct radeon_ring *ring,
2651                               struct radeon_semaphore *semaphore,
2652                               bool emit_wait)
2653 {
2654         uint64_t addr = semaphore->gpu_addr;
2655         unsigned sel = emit_wait ? PACKET3_SEM_SEL_WAIT : PACKET3_SEM_SEL_SIGNAL;
2656
2657         if (rdev->family < CHIP_CAYMAN)
2658                 sel |= PACKET3_SEM_WAIT_ON_SIGNAL;
2659
2660         radeon_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 1));
2661         radeon_ring_write(ring, addr & 0xffffffff);
2662         radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | sel);
2663 }
2664
2665 /**
2666  * r600_copy_cpdma - copy pages using the CP DMA engine
2667  *
2668  * @rdev: radeon_device pointer
2669  * @src_offset: src GPU address
2670  * @dst_offset: dst GPU address
2671  * @num_gpu_pages: number of GPU pages to xfer
2672  * @fence: radeon fence object
2673  *
2674  * Copy GPU paging using the CP DMA engine (r6xx+).
2675  * Used by the radeon ttm implementation to move pages if
2676  * registered as the asic copy callback.
2677  */
2678 int r600_copy_cpdma(struct radeon_device *rdev,
2679                     uint64_t src_offset, uint64_t dst_offset,
2680                     unsigned num_gpu_pages,
2681                     struct radeon_fence **fence)
2682 {
2683         struct radeon_semaphore *sem = NULL;
2684         int ring_index = rdev->asic->copy.blit_ring_index;
2685         struct radeon_ring *ring = &rdev->ring[ring_index];
2686         u32 size_in_bytes, cur_size_in_bytes, tmp;
2687         int i, num_loops;
2688         int r = 0;
2689
2690         r = radeon_semaphore_create(rdev, &sem);
2691         if (r) {
2692                 DRM_ERROR("radeon: moving bo (%d).\n", r);
2693                 return r;
2694         }
2695
2696         size_in_bytes = (num_gpu_pages << RADEON_GPU_PAGE_SHIFT);
2697         num_loops = DIV_ROUND_UP(size_in_bytes, 0x1fffff);
2698         r = radeon_ring_lock(rdev, ring, num_loops * 6 + 24);
2699         if (r) {
2700                 DRM_ERROR("radeon: moving bo (%d).\n", r);
2701                 radeon_semaphore_free(rdev, &sem, NULL);
2702                 return r;
2703         }
2704
2705         if (radeon_fence_need_sync(*fence, ring->idx)) {
2706                 radeon_semaphore_sync_rings(rdev, sem, (*fence)->ring,
2707                                             ring->idx);
2708                 radeon_fence_note_sync(*fence, ring->idx);
2709         } else {
2710                 radeon_semaphore_free(rdev, &sem, NULL);
2711         }
2712
2713         radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2714         radeon_ring_write(ring, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
2715         radeon_ring_write(ring, WAIT_3D_IDLE_bit);
2716         for (i = 0; i < num_loops; i++) {
2717                 cur_size_in_bytes = size_in_bytes;
2718                 if (cur_size_in_bytes > 0x1fffff)
2719                         cur_size_in_bytes = 0x1fffff;
2720                 size_in_bytes -= cur_size_in_bytes;
2721                 tmp = upper_32_bits(src_offset) & 0xff;
2722                 if (size_in_bytes == 0)
2723                         tmp |= PACKET3_CP_DMA_CP_SYNC;
2724                 radeon_ring_write(ring, PACKET3(PACKET3_CP_DMA, 4));
2725                 radeon_ring_write(ring, src_offset & 0xffffffff);
2726                 radeon_ring_write(ring, tmp);
2727                 radeon_ring_write(ring, dst_offset & 0xffffffff);
2728                 radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff);
2729                 radeon_ring_write(ring, cur_size_in_bytes);
2730                 src_offset += cur_size_in_bytes;
2731                 dst_offset += cur_size_in_bytes;
2732         }
2733         radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2734         radeon_ring_write(ring, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
2735         radeon_ring_write(ring, WAIT_CP_DMA_IDLE_bit);
2736
2737         r = radeon_fence_emit(rdev, fence, ring->idx);
2738         if (r) {
2739                 radeon_ring_unlock_undo(rdev, ring);
2740                 return r;
2741         }
2742
2743         radeon_ring_unlock_commit(rdev, ring);
2744         radeon_semaphore_free(rdev, &sem, *fence);
2745
2746         return r;
2747 }
2748
2749 int r600_set_surface_reg(struct radeon_device *rdev, int reg,
2750                          uint32_t tiling_flags, uint32_t pitch,
2751                          uint32_t offset, uint32_t obj_size)
2752 {
2753         /* FIXME: implement */
2754         return 0;
2755 }
2756
2757 void r600_clear_surface_reg(struct radeon_device *rdev, int reg)
2758 {
2759         /* FIXME: implement */
2760 }
2761
2762 static int r600_startup(struct radeon_device *rdev)
2763 {
2764         struct radeon_ring *ring;
2765         int r;
2766
2767         /* enable pcie gen2 link */
2768         r600_pcie_gen2_enable(rdev);
2769
2770         /* scratch needs to be initialized before MC */
2771         r = r600_vram_scratch_init(rdev);
2772         if (r)
2773                 return r;
2774
2775         r600_mc_program(rdev);
2776
2777         if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
2778                 r = r600_init_microcode(rdev);
2779                 if (r) {
2780                         DRM_ERROR("Failed to load firmware!\n");
2781                         return r;
2782                 }
2783         }
2784
2785         if (rdev->flags & RADEON_IS_AGP) {
2786                 r600_agp_enable(rdev);
2787         } else {
2788                 r = r600_pcie_gart_enable(rdev);
2789                 if (r)
2790                         return r;
2791         }
2792         r600_gpu_init(rdev);
2793
2794         /* allocate wb buffer */
2795         r = radeon_wb_init(rdev);
2796         if (r)
2797                 return r;
2798
2799         r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
2800         if (r) {
2801                 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
2802                 return r;
2803         }
2804
2805         r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_DMA_INDEX);
2806         if (r) {
2807                 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r);
2808                 return r;
2809         }
2810
2811         /* Enable IRQ */
2812         if (!rdev->irq.installed) {
2813                 r = radeon_irq_kms_init(rdev);
2814                 if (r)
2815                         return r;
2816         }
2817
2818         r = r600_irq_init(rdev);
2819         if (r) {
2820                 DRM_ERROR("radeon: IH init failed (%d).\n", r);
2821                 radeon_irq_kms_fini(rdev);
2822                 return r;
2823         }
2824         r600_irq_set(rdev);
2825
2826         ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2827         r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
2828                              R600_CP_RB_RPTR, R600_CP_RB_WPTR,
2829                              RADEON_CP_PACKET2);
2830         if (r)
2831                 return r;
2832
2833         ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
2834         r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET,
2835                              DMA_RB_RPTR, DMA_RB_WPTR,
2836                              DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0));
2837         if (r)
2838                 return r;
2839
2840         r = r600_cp_load_microcode(rdev);
2841         if (r)
2842                 return r;
2843         r = r600_cp_resume(rdev);
2844         if (r)
2845                 return r;
2846
2847         r = r600_dma_resume(rdev);
2848         if (r)
2849                 return r;
2850
2851         r = radeon_ib_pool_init(rdev);
2852         if (r) {
2853                 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
2854                 return r;
2855         }
2856
2857         r = r600_audio_init(rdev);
2858         if (r) {
2859                 DRM_ERROR("radeon: audio init failed\n");
2860                 return r;
2861         }
2862
2863         return 0;
2864 }
2865
2866 void r600_vga_set_state(struct radeon_device *rdev, bool state)
2867 {
2868         uint32_t temp;
2869
2870         temp = RREG32(CONFIG_CNTL);
2871         if (state == false) {
2872                 temp &= ~(1<<0);
2873                 temp |= (1<<1);
2874         } else {
2875                 temp &= ~(1<<1);
2876         }
2877         WREG32(CONFIG_CNTL, temp);
2878 }
2879
2880 int r600_resume(struct radeon_device *rdev)
2881 {
2882         int r;
2883
2884         /* Do not reset GPU before posting, on r600 hw unlike on r500 hw,
2885          * posting will perform necessary task to bring back GPU into good
2886          * shape.
2887          */
2888         /* post card */
2889         atom_asic_init(rdev->mode_info.atom_context);
2890
2891         rdev->accel_working = true;
2892         r = r600_startup(rdev);
2893         if (r) {
2894                 DRM_ERROR("r600 startup failed on resume\n");
2895                 rdev->accel_working = false;
2896                 return r;
2897         }
2898
2899         return r;
2900 }
2901
2902 int r600_suspend(struct radeon_device *rdev)
2903 {
2904         r600_audio_fini(rdev);
2905         r600_cp_stop(rdev);
2906         r600_dma_stop(rdev);
2907         r600_irq_suspend(rdev);
2908         radeon_wb_disable(rdev);
2909         r600_pcie_gart_disable(rdev);
2910
2911         return 0;
2912 }
2913
2914 /* Plan is to move initialization in that function and use
2915  * helper function so that radeon_device_init pretty much
2916  * do nothing more than calling asic specific function. This
2917  * should also allow to remove a bunch of callback function
2918  * like vram_info.
2919  */
2920 int r600_init(struct radeon_device *rdev)
2921 {
2922         int r;
2923
2924         if (r600_debugfs_mc_info_init(rdev)) {
2925                 DRM_ERROR("Failed to register debugfs file for mc !\n");
2926         }
2927         /* Read BIOS */
2928         if (!radeon_get_bios(rdev)) {
2929                 if (ASIC_IS_AVIVO(rdev))
2930                         return -EINVAL;
2931         }
2932         /* Must be an ATOMBIOS */
2933         if (!rdev->is_atom_bios) {
2934                 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
2935                 return -EINVAL;
2936         }
2937         r = radeon_atombios_init(rdev);
2938         if (r)
2939                 return r;
2940         /* Post card if necessary */
2941         if (!radeon_card_posted(rdev)) {
2942                 if (!rdev->bios) {
2943                         dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
2944                         return -EINVAL;
2945                 }
2946                 DRM_INFO("GPU not posted. posting now...\n");
2947                 atom_asic_init(rdev->mode_info.atom_context);
2948         }
2949         /* Initialize scratch registers */
2950         r600_scratch_init(rdev);
2951         /* Initialize surface registers */
2952         radeon_surface_init(rdev);
2953         /* Initialize clocks */
2954         radeon_get_clock_info(rdev->ddev);
2955         /* Fence driver */
2956         r = radeon_fence_driver_init(rdev);
2957         if (r)
2958                 return r;
2959         if (rdev->flags & RADEON_IS_AGP) {
2960                 r = radeon_agp_init(rdev);
2961                 if (r)
2962                         radeon_agp_disable(rdev);
2963         }
2964         r = r600_mc_init(rdev);
2965         if (r)
2966                 return r;
2967         /* Memory manager */
2968         r = radeon_bo_init(rdev);
2969         if (r)
2970                 return r;
2971
2972         rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL;
2973         r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024);
2974
2975         rdev->ring[R600_RING_TYPE_DMA_INDEX].ring_obj = NULL;
2976         r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX], 64 * 1024);
2977
2978         rdev->ih.ring_obj = NULL;
2979         r600_ih_ring_init(rdev, 64 * 1024);
2980
2981         r = r600_pcie_gart_init(rdev);
2982         if (r)
2983                 return r;
2984
2985         rdev->accel_working = true;
2986         r = r600_startup(rdev);
2987         if (r) {
2988                 dev_err(rdev->dev, "disabling GPU acceleration\n");
2989                 r600_cp_fini(rdev);
2990                 r600_dma_fini(rdev);
2991                 r600_irq_fini(rdev);
2992                 radeon_wb_fini(rdev);
2993                 radeon_ib_pool_fini(rdev);
2994                 radeon_irq_kms_fini(rdev);
2995                 r600_pcie_gart_fini(rdev);
2996                 rdev->accel_working = false;
2997         }
2998
2999         return 0;
3000 }
3001
3002 void r600_fini(struct radeon_device *rdev)
3003 {
3004         r600_audio_fini(rdev);
3005         r600_cp_fini(rdev);
3006         r600_dma_fini(rdev);
3007         r600_irq_fini(rdev);
3008         radeon_wb_fini(rdev);
3009         radeon_ib_pool_fini(rdev);
3010         radeon_irq_kms_fini(rdev);
3011         r600_pcie_gart_fini(rdev);
3012         r600_vram_scratch_fini(rdev);
3013         radeon_agp_fini(rdev);
3014         radeon_gem_fini(rdev);
3015         radeon_fence_driver_fini(rdev);
3016         radeon_bo_fini(rdev);
3017         radeon_atombios_fini(rdev);
3018         kfree(rdev->bios);
3019         rdev->bios = NULL;
3020 }
3021
3022
3023 /*
3024  * CS stuff
3025  */
3026 void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
3027 {
3028         struct radeon_ring *ring = &rdev->ring[ib->ring];
3029         u32 next_rptr;
3030
3031         if (ring->rptr_save_reg) {
3032                 next_rptr = ring->wptr + 3 + 4;
3033                 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
3034                 radeon_ring_write(ring, ((ring->rptr_save_reg -
3035                                          PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
3036                 radeon_ring_write(ring, next_rptr);
3037         } else if (rdev->wb.enabled) {
3038                 next_rptr = ring->wptr + 5 + 4;
3039                 radeon_ring_write(ring, PACKET3(PACKET3_MEM_WRITE, 3));
3040                 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
3041                 radeon_ring_write(ring, (upper_32_bits(ring->next_rptr_gpu_addr) & 0xff) | (1 << 18));
3042                 radeon_ring_write(ring, next_rptr);
3043                 radeon_ring_write(ring, 0);
3044         }
3045
3046         radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
3047         radeon_ring_write(ring,
3048 #ifdef __BIG_ENDIAN
3049                           (2 << 0) |
3050 #endif
3051                           (ib->gpu_addr & 0xFFFFFFFC));
3052         radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF);
3053         radeon_ring_write(ring, ib->length_dw);
3054 }
3055
3056 int r600_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
3057 {
3058         struct radeon_ib ib;
3059         uint32_t scratch;
3060         uint32_t tmp = 0;
3061         unsigned i;
3062         int r;
3063
3064         r = radeon_scratch_get(rdev, &scratch);
3065         if (r) {
3066                 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
3067                 return r;
3068         }
3069         WREG32(scratch, 0xCAFEDEAD);
3070         r = radeon_ib_get(rdev, ring->idx, &ib, NULL, 256);
3071         if (r) {
3072                 DRM_ERROR("radeon: failed to get ib (%d).\n", r);
3073                 goto free_scratch;
3074         }
3075         ib.ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1);
3076         ib.ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
3077         ib.ptr[2] = 0xDEADBEEF;
3078         ib.length_dw = 3;
3079         r = radeon_ib_schedule(rdev, &ib, NULL);
3080         if (r) {
3081                 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
3082                 goto free_ib;
3083         }
3084         r = radeon_fence_wait(ib.fence, false);
3085         if (r) {
3086                 DRM_ERROR("radeon: fence wait failed (%d).\n", r);
3087                 goto free_ib;
3088         }
3089         for (i = 0; i < rdev->usec_timeout; i++) {
3090                 tmp = RREG32(scratch);
3091                 if (tmp == 0xDEADBEEF)
3092                         break;
3093                 DRM_UDELAY(1);
3094         }
3095         if (i < rdev->usec_timeout) {
3096                 DRM_INFO("ib test on ring %d succeeded in %u usecs\n", ib.fence->ring, i);
3097         } else {
3098                 DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n",
3099                           scratch, tmp);
3100                 r = -EINVAL;
3101         }
3102 free_ib:
3103         radeon_ib_free(rdev, &ib);
3104 free_scratch:
3105         radeon_scratch_free(rdev, scratch);
3106         return r;
3107 }
3108
3109 /*
3110  * Interrupts
3111  *
3112  * Interrupts use a ring buffer on r6xx/r7xx hardware.  It works pretty
3113  * the same as the CP ring buffer, but in reverse.  Rather than the CPU
3114  * writing to the ring and the GPU consuming, the GPU writes to the ring
3115  * and host consumes.  As the host irq handler processes interrupts, it
3116  * increments the rptr.  When the rptr catches up with the wptr, all the
3117  * current interrupts have been processed.
3118  */
3119
3120 void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size)
3121 {
3122         u32 rb_bufsz;
3123
3124         /* Align ring size */
3125         rb_bufsz = order_base_2(ring_size / 4);
3126         ring_size = (1 << rb_bufsz) * 4;
3127         rdev->ih.ring_size = ring_size;
3128         rdev->ih.ptr_mask = rdev->ih.ring_size - 1;
3129         rdev->ih.rptr = 0;
3130 }
3131
3132 int r600_ih_ring_alloc(struct radeon_device *rdev)
3133 {
3134         int r;
3135
3136         /* Allocate ring buffer */
3137         if (rdev->ih.ring_obj == NULL) {
3138                 r = radeon_bo_create(rdev, rdev->ih.ring_size,
3139                                      PAGE_SIZE, true,
3140                                      RADEON_GEM_DOMAIN_GTT,
3141                                      NULL, &rdev->ih.ring_obj);
3142                 if (r) {
3143                         DRM_ERROR("radeon: failed to create ih ring buffer (%d).\n", r);
3144                         return r;
3145                 }
3146                 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
3147                 if (unlikely(r != 0))
3148                         return r;
3149                 r = radeon_bo_pin(rdev->ih.ring_obj,
3150                                   RADEON_GEM_DOMAIN_GTT,
3151                                   &rdev->ih.gpu_addr);
3152                 if (r) {
3153                         radeon_bo_unreserve(rdev->ih.ring_obj);
3154                         DRM_ERROR("radeon: failed to pin ih ring buffer (%d).\n", r);
3155                         return r;
3156                 }
3157                 r = radeon_bo_kmap(rdev->ih.ring_obj,
3158                                    (void **)&rdev->ih.ring);
3159                 radeon_bo_unreserve(rdev->ih.ring_obj);
3160                 if (r) {
3161                         DRM_ERROR("radeon: failed to map ih ring buffer (%d).\n", r);
3162                         return r;
3163                 }
3164         }
3165         return 0;
3166 }
3167
3168 void r600_ih_ring_fini(struct radeon_device *rdev)
3169 {
3170         int r;
3171         if (rdev->ih.ring_obj) {
3172                 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
3173                 if (likely(r == 0)) {
3174                         radeon_bo_kunmap(rdev->ih.ring_obj);
3175                         radeon_bo_unpin(rdev->ih.ring_obj);
3176                         radeon_bo_unreserve(rdev->ih.ring_obj);
3177                 }
3178                 radeon_bo_unref(&rdev->ih.ring_obj);
3179                 rdev->ih.ring = NULL;
3180                 rdev->ih.ring_obj = NULL;
3181         }
3182 }
3183
3184 void r600_rlc_stop(struct radeon_device *rdev)
3185 {
3186
3187         if ((rdev->family >= CHIP_RV770) &&
3188             (rdev->family <= CHIP_RV740)) {
3189                 /* r7xx asics need to soft reset RLC before halting */
3190                 WREG32(SRBM_SOFT_RESET, SOFT_RESET_RLC);
3191                 RREG32(SRBM_SOFT_RESET);
3192                 mdelay(15);
3193                 WREG32(SRBM_SOFT_RESET, 0);
3194                 RREG32(SRBM_SOFT_RESET);
3195         }
3196
3197         WREG32(RLC_CNTL, 0);
3198 }
3199
3200 static void r600_rlc_start(struct radeon_device *rdev)
3201 {
3202         WREG32(RLC_CNTL, RLC_ENABLE);
3203 }
3204
3205 static int r600_rlc_resume(struct radeon_device *rdev)
3206 {
3207         u32 i;
3208         const __be32 *fw_data;
3209
3210         if (!rdev->rlc_fw)
3211                 return -EINVAL;
3212
3213         r600_rlc_stop(rdev);
3214
3215         WREG32(RLC_HB_CNTL, 0);
3216
3217         WREG32(RLC_HB_BASE, 0);
3218         WREG32(RLC_HB_RPTR, 0);
3219         WREG32(RLC_HB_WPTR, 0);
3220         WREG32(RLC_HB_WPTR_LSB_ADDR, 0);
3221         WREG32(RLC_HB_WPTR_MSB_ADDR, 0);
3222         WREG32(RLC_MC_CNTL, 0);
3223         WREG32(RLC_UCODE_CNTL, 0);
3224
3225         fw_data = (const __be32 *)rdev->rlc_fw->data;
3226         if (rdev->family >= CHIP_RV770) {
3227                 for (i = 0; i < R700_RLC_UCODE_SIZE; i++) {
3228                         WREG32(RLC_UCODE_ADDR, i);
3229                         WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
3230                 }
3231         } else {
3232                 for (i = 0; i < R600_RLC_UCODE_SIZE; i++) {
3233                         WREG32(RLC_UCODE_ADDR, i);
3234                         WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
3235                 }
3236         }
3237         WREG32(RLC_UCODE_ADDR, 0);
3238
3239         r600_rlc_start(rdev);
3240
3241         return 0;
3242 }
3243
3244 static void r600_enable_interrupts(struct radeon_device *rdev)
3245 {
3246         u32 ih_cntl = RREG32(IH_CNTL);
3247         u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
3248
3249         ih_cntl |= ENABLE_INTR;
3250         ih_rb_cntl |= IH_RB_ENABLE;
3251         WREG32(IH_CNTL, ih_cntl);
3252         WREG32(IH_RB_CNTL, ih_rb_cntl);
3253         rdev->ih.enabled = true;
3254 }
3255
3256 void r600_disable_interrupts(struct radeon_device *rdev)
3257 {
3258         u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
3259         u32 ih_cntl = RREG32(IH_CNTL);
3260
3261         ih_rb_cntl &= ~IH_RB_ENABLE;
3262         ih_cntl &= ~ENABLE_INTR;
3263         WREG32(IH_RB_CNTL, ih_rb_cntl);
3264         WREG32(IH_CNTL, ih_cntl);
3265         /* set rptr, wptr to 0 */
3266         WREG32(IH_RB_RPTR, 0);
3267         WREG32(IH_RB_WPTR, 0);
3268         rdev->ih.enabled = false;
3269         rdev->ih.rptr = 0;
3270 }
3271
3272 static void r600_disable_interrupt_state(struct radeon_device *rdev)
3273 {
3274         u32 tmp;
3275
3276         WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
3277         tmp = RREG32(DMA_CNTL) & ~TRAP_ENABLE;
3278         WREG32(DMA_CNTL, tmp);
3279         WREG32(GRBM_INT_CNTL, 0);
3280         WREG32(DxMODE_INT_MASK, 0);
3281         WREG32(D1GRPH_INTERRUPT_CONTROL, 0);
3282         WREG32(D2GRPH_INTERRUPT_CONTROL, 0);
3283         if (ASIC_IS_DCE3(rdev)) {
3284                 WREG32(DCE3_DACA_AUTODETECT_INT_CONTROL, 0);
3285                 WREG32(DCE3_DACB_AUTODETECT_INT_CONTROL, 0);
3286                 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3287                 WREG32(DC_HPD1_INT_CONTROL, tmp);
3288                 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3289                 WREG32(DC_HPD2_INT_CONTROL, tmp);
3290                 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3291                 WREG32(DC_HPD3_INT_CONTROL, tmp);
3292                 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3293                 WREG32(DC_HPD4_INT_CONTROL, tmp);
3294                 if (ASIC_IS_DCE32(rdev)) {
3295                         tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3296                         WREG32(DC_HPD5_INT_CONTROL, tmp);
3297                         tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3298                         WREG32(DC_HPD6_INT_CONTROL, tmp);
3299                         tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3300                         WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, tmp);
3301                         tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3302                         WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, tmp);
3303                 } else {
3304                         tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3305                         WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp);
3306                         tmp = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3307                         WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, tmp);
3308                 }
3309         } else {
3310                 WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
3311                 WREG32(DACB_AUTODETECT_INT_CONTROL, 0);
3312                 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
3313                 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
3314                 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
3315                 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
3316                 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
3317                 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
3318                 tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3319                 WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp);
3320                 tmp = RREG32(HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3321                 WREG32(HDMI1_AUDIO_PACKET_CONTROL, tmp);
3322         }
3323 }
3324
3325 int r600_irq_init(struct radeon_device *rdev)
3326 {
3327         int ret = 0;
3328         int rb_bufsz;
3329         u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
3330
3331         /* allocate ring */
3332         ret = r600_ih_ring_alloc(rdev);
3333         if (ret)
3334                 return ret;
3335
3336         /* disable irqs */
3337         r600_disable_interrupts(rdev);
3338
3339         /* init rlc */
3340         if (rdev->family >= CHIP_CEDAR)
3341                 ret = evergreen_rlc_resume(rdev);
3342         else
3343                 ret = r600_rlc_resume(rdev);
3344         if (ret) {
3345                 r600_ih_ring_fini(rdev);
3346                 return ret;
3347         }
3348
3349         /* setup interrupt control */
3350         /* set dummy read address to ring address */
3351         WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8);
3352         interrupt_cntl = RREG32(INTERRUPT_CNTL);
3353         /* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled without msi
3354          * IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_EN
3355          */
3356         interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE;
3357         /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */
3358         interrupt_cntl &= ~IH_REQ_NONSNOOP_EN;
3359         WREG32(INTERRUPT_CNTL, interrupt_cntl);
3360
3361         WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8);
3362         rb_bufsz = order_base_2(rdev->ih.ring_size / 4);
3363
3364         ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE |
3365                       IH_WPTR_OVERFLOW_CLEAR |
3366                       (rb_bufsz << 1));
3367
3368         if (rdev->wb.enabled)
3369                 ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE;
3370
3371         /* set the writeback address whether it's enabled or not */
3372         WREG32(IH_RB_WPTR_ADDR_LO, (rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFFFFFFFC);
3373         WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF);
3374
3375         WREG32(IH_RB_CNTL, ih_rb_cntl);
3376
3377         /* set rptr, wptr to 0 */
3378         WREG32(IH_RB_RPTR, 0);
3379         WREG32(IH_RB_WPTR, 0);
3380
3381         /* Default settings for IH_CNTL (disabled at first) */
3382         ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10);
3383         /* RPTR_REARM only works if msi's are enabled */
3384         if (rdev->msi_enabled)
3385                 ih_cntl |= RPTR_REARM;
3386         WREG32(IH_CNTL, ih_cntl);
3387
3388         /* force the active interrupt state to all disabled */
3389         if (rdev->family >= CHIP_CEDAR)
3390                 evergreen_disable_interrupt_state(rdev);
3391         else
3392                 r600_disable_interrupt_state(rdev);
3393
3394         /* at this point everything should be setup correctly to enable master */
3395         pci_set_master(rdev->pdev);
3396
3397         /* enable irqs */
3398         r600_enable_interrupts(rdev);
3399
3400         return ret;
3401 }
3402
3403 void r600_irq_suspend(struct radeon_device *rdev)
3404 {
3405         r600_irq_disable(rdev);
3406         r600_rlc_stop(rdev);
3407 }
3408
3409 void r600_irq_fini(struct radeon_device *rdev)
3410 {
3411         r600_irq_suspend(rdev);
3412         r600_ih_ring_fini(rdev);
3413 }
3414
3415 int r600_irq_set(struct radeon_device *rdev)
3416 {
3417         u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
3418         u32 mode_int = 0;
3419         u32 hpd1, hpd2, hpd3, hpd4 = 0, hpd5 = 0, hpd6 = 0;
3420         u32 grbm_int_cntl = 0;
3421         u32 hdmi0, hdmi1;
3422         u32 d1grph = 0, d2grph = 0;
3423         u32 dma_cntl;
3424         u32 thermal_int = 0;
3425
3426         if (!rdev->irq.installed) {
3427                 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
3428                 return -EINVAL;
3429         }
3430         /* don't enable anything if the ih is disabled */
3431         if (!rdev->ih.enabled) {
3432                 r600_disable_interrupts(rdev);
3433                 /* force the active interrupt state to all disabled */
3434                 r600_disable_interrupt_state(rdev);
3435                 return 0;
3436         }
3437
3438         if (ASIC_IS_DCE3(rdev)) {
3439                 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
3440                 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
3441                 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
3442                 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
3443                 if (ASIC_IS_DCE32(rdev)) {
3444                         hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
3445                         hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
3446                         hdmi0 = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
3447                         hdmi1 = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
3448                 } else {
3449                         hdmi0 = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3450                         hdmi1 = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3451                 }
3452         } else {
3453                 hpd1 = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & ~DC_HPDx_INT_EN;
3454                 hpd2 = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & ~DC_HPDx_INT_EN;
3455                 hpd3 = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & ~DC_HPDx_INT_EN;
3456                 hdmi0 = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3457                 hdmi1 = RREG32(HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3458         }
3459
3460         dma_cntl = RREG32(DMA_CNTL) & ~TRAP_ENABLE;
3461
3462         if ((rdev->family > CHIP_R600) && (rdev->family < CHIP_RV770)) {
3463                 thermal_int = RREG32(CG_THERMAL_INT) &
3464                         ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW);
3465         } else if (rdev->family >= CHIP_RV770) {
3466                 thermal_int = RREG32(RV770_CG_THERMAL_INT) &
3467                         ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW);
3468         }
3469         if (rdev->irq.dpm_thermal) {
3470                 DRM_DEBUG("dpm thermal\n");
3471                 thermal_int |= THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW;
3472         }
3473
3474         if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
3475                 DRM_DEBUG("r600_irq_set: sw int\n");
3476                 cp_int_cntl |= RB_INT_ENABLE;
3477                 cp_int_cntl |= TIME_STAMP_INT_ENABLE;
3478         }
3479
3480         if (atomic_read(&rdev->irq.ring_int[R600_RING_TYPE_DMA_INDEX])) {
3481                 DRM_DEBUG("r600_irq_set: sw int dma\n");
3482                 dma_cntl |= TRAP_ENABLE;
3483         }
3484
3485         if (rdev->irq.crtc_vblank_int[0] ||
3486             atomic_read(&rdev->irq.pflip[0])) {
3487                 DRM_DEBUG("r600_irq_set: vblank 0\n");
3488                 mode_int |= D1MODE_VBLANK_INT_MASK;
3489         }
3490         if (rdev->irq.crtc_vblank_int[1] ||
3491             atomic_read(&rdev->irq.pflip[1])) {
3492                 DRM_DEBUG("r600_irq_set: vblank 1\n");
3493                 mode_int |= D2MODE_VBLANK_INT_MASK;
3494         }
3495         if (rdev->irq.hpd[0]) {
3496                 DRM_DEBUG("r600_irq_set: hpd 1\n");
3497                 hpd1 |= DC_HPDx_INT_EN;
3498         }
3499         if (rdev->irq.hpd[1]) {
3500                 DRM_DEBUG("r600_irq_set: hpd 2\n");
3501                 hpd2 |= DC_HPDx_INT_EN;
3502         }
3503         if (rdev->irq.hpd[2]) {
3504                 DRM_DEBUG("r600_irq_set: hpd 3\n");
3505                 hpd3 |= DC_HPDx_INT_EN;
3506         }
3507         if (rdev->irq.hpd[3]) {
3508                 DRM_DEBUG("r600_irq_set: hpd 4\n");
3509                 hpd4 |= DC_HPDx_INT_EN;
3510         }
3511         if (rdev->irq.hpd[4]) {
3512                 DRM_DEBUG("r600_irq_set: hpd 5\n");
3513                 hpd5 |= DC_HPDx_INT_EN;
3514         }
3515         if (rdev->irq.hpd[5]) {
3516                 DRM_DEBUG("r600_irq_set: hpd 6\n");
3517                 hpd6 |= DC_HPDx_INT_EN;
3518         }
3519         if (rdev->irq.afmt[0]) {
3520                 DRM_DEBUG("r600_irq_set: hdmi 0\n");
3521                 hdmi0 |= HDMI0_AZ_FORMAT_WTRIG_MASK;
3522         }
3523         if (rdev->irq.afmt[1]) {
3524                 DRM_DEBUG("r600_irq_set: hdmi 0\n");
3525                 hdmi1 |= HDMI0_AZ_FORMAT_WTRIG_MASK;
3526         }
3527
3528         WREG32(CP_INT_CNTL, cp_int_cntl);
3529         WREG32(DMA_CNTL, dma_cntl);
3530         WREG32(DxMODE_INT_MASK, mode_int);
3531         WREG32(D1GRPH_INTERRUPT_CONTROL, d1grph);
3532         WREG32(D2GRPH_INTERRUPT_CONTROL, d2grph);
3533         WREG32(GRBM_INT_CNTL, grbm_int_cntl);
3534         if (ASIC_IS_DCE3(rdev)) {
3535                 WREG32(DC_HPD1_INT_CONTROL, hpd1);
3536                 WREG32(DC_HPD2_INT_CONTROL, hpd2);
3537                 WREG32(DC_HPD3_INT_CONTROL, hpd3);
3538                 WREG32(DC_HPD4_INT_CONTROL, hpd4);
3539                 if (ASIC_IS_DCE32(rdev)) {
3540                         WREG32(DC_HPD5_INT_CONTROL, hpd5);
3541                         WREG32(DC_HPD6_INT_CONTROL, hpd6);
3542                         WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, hdmi0);
3543                         WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, hdmi1);
3544                 } else {
3545                         WREG32(HDMI0_AUDIO_PACKET_CONTROL, hdmi0);
3546                         WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, hdmi1);
3547                 }
3548         } else {
3549                 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1);
3550                 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2);
3551                 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, hpd3);
3552                 WREG32(HDMI0_AUDIO_PACKET_CONTROL, hdmi0);
3553                 WREG32(HDMI1_AUDIO_PACKET_CONTROL, hdmi1);
3554         }
3555         if ((rdev->family > CHIP_R600) && (rdev->family < CHIP_RV770)) {
3556                 WREG32(CG_THERMAL_INT, thermal_int);
3557         } else if (rdev->family >= CHIP_RV770) {
3558                 WREG32(RV770_CG_THERMAL_INT, thermal_int);
3559         }
3560
3561         return 0;
3562 }
3563
3564 static void r600_irq_ack(struct radeon_device *rdev)
3565 {
3566         u32 tmp;
3567
3568         if (ASIC_IS_DCE3(rdev)) {
3569                 rdev->irq.stat_regs.r600.disp_int = RREG32(DCE3_DISP_INTERRUPT_STATUS);
3570                 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE);
3571                 rdev->irq.stat_regs.r600.disp_int_cont2 = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE2);
3572                 if (ASIC_IS_DCE32(rdev)) {
3573                         rdev->irq.stat_regs.r600.hdmi0_status = RREG32(AFMT_STATUS + DCE3_HDMI_OFFSET0);
3574                         rdev->irq.stat_regs.r600.hdmi1_status = RREG32(AFMT_STATUS + DCE3_HDMI_OFFSET1);
3575                 } else {
3576                         rdev->irq.stat_regs.r600.hdmi0_status = RREG32(HDMI0_STATUS);
3577                         rdev->irq.stat_regs.r600.hdmi1_status = RREG32(DCE3_HDMI1_STATUS);
3578                 }
3579         } else {
3580                 rdev->irq.stat_regs.r600.disp_int = RREG32(DISP_INTERRUPT_STATUS);
3581                 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
3582                 rdev->irq.stat_regs.r600.disp_int_cont2 = 0;
3583                 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(HDMI0_STATUS);
3584                 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(HDMI1_STATUS);
3585         }
3586         rdev->irq.stat_regs.r600.d1grph_int = RREG32(D1GRPH_INTERRUPT_STATUS);
3587         rdev->irq.stat_regs.r600.d2grph_int = RREG32(D2GRPH_INTERRUPT_STATUS);
3588
3589         if (rdev->irq.stat_regs.r600.d1grph_int & DxGRPH_PFLIP_INT_OCCURRED)
3590                 WREG32(D1GRPH_INTERRUPT_STATUS, DxGRPH_PFLIP_INT_CLEAR);
3591         if (rdev->irq.stat_regs.r600.d2grph_int & DxGRPH_PFLIP_INT_OCCURRED)
3592                 WREG32(D2GRPH_INTERRUPT_STATUS, DxGRPH_PFLIP_INT_CLEAR);
3593         if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT)
3594                 WREG32(D1MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
3595         if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT)
3596                 WREG32(D1MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
3597         if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT)
3598                 WREG32(D2MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
3599         if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT)
3600                 WREG32(D2MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
3601         if (rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT) {
3602                 if (ASIC_IS_DCE3(rdev)) {
3603                         tmp = RREG32(DC_HPD1_INT_CONTROL);
3604                         tmp |= DC_HPDx_INT_ACK;
3605                         WREG32(DC_HPD1_INT_CONTROL, tmp);
3606                 } else {
3607                         tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
3608                         tmp |= DC_HPDx_INT_ACK;
3609                         WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
3610                 }
3611         }
3612         if (rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT) {
3613                 if (ASIC_IS_DCE3(rdev)) {
3614                         tmp = RREG32(DC_HPD2_INT_CONTROL);
3615                         tmp |= DC_HPDx_INT_ACK;
3616                         WREG32(DC_HPD2_INT_CONTROL, tmp);
3617                 } else {
3618                         tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
3619                         tmp |= DC_HPDx_INT_ACK;
3620                         WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
3621                 }
3622         }
3623         if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT) {
3624                 if (ASIC_IS_DCE3(rdev)) {
3625                         tmp = RREG32(DC_HPD3_INT_CONTROL);
3626                         tmp |= DC_HPDx_INT_ACK;
3627                         WREG32(DC_HPD3_INT_CONTROL, tmp);
3628                 } else {
3629                         tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
3630                         tmp |= DC_HPDx_INT_ACK;
3631                         WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
3632                 }
3633         }
3634         if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT) {
3635                 tmp = RREG32(DC_HPD4_INT_CONTROL);
3636                 tmp |= DC_HPDx_INT_ACK;
3637                 WREG32(DC_HPD4_INT_CONTROL, tmp);
3638         }
3639         if (ASIC_IS_DCE32(rdev)) {
3640                 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT) {
3641                         tmp = RREG32(DC_HPD5_INT_CONTROL);
3642                         tmp |= DC_HPDx_INT_ACK;
3643                         WREG32(DC_HPD5_INT_CONTROL, tmp);
3644                 }
3645                 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT) {
3646                         tmp = RREG32(DC_HPD5_INT_CONTROL);
3647                         tmp |= DC_HPDx_INT_ACK;
3648                         WREG32(DC_HPD6_INT_CONTROL, tmp);
3649                 }
3650                 if (rdev->irq.stat_regs.r600.hdmi0_status & AFMT_AZ_FORMAT_WTRIG) {
3651                         tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0);
3652                         tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
3653                         WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, tmp);
3654                 }
3655                 if (rdev->irq.stat_regs.r600.hdmi1_status & AFMT_AZ_FORMAT_WTRIG) {
3656                         tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1);
3657                         tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
3658                         WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, tmp);
3659                 }
3660         } else {
3661                 if (rdev->irq.stat_regs.r600.hdmi0_status & HDMI0_AZ_FORMAT_WTRIG) {
3662                         tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL);
3663                         tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK;
3664                         WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp);
3665                 }
3666                 if (rdev->irq.stat_regs.r600.hdmi1_status & HDMI0_AZ_FORMAT_WTRIG) {
3667                         if (ASIC_IS_DCE3(rdev)) {
3668                                 tmp = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL);
3669                                 tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK;
3670                                 WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, tmp);
3671                         } else {
3672                                 tmp = RREG32(HDMI1_AUDIO_PACKET_CONTROL);
3673                                 tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK;
3674                                 WREG32(HDMI1_AUDIO_PACKET_CONTROL, tmp);
3675                         }
3676                 }
3677         }
3678 }
3679
3680 void r600_irq_disable(struct radeon_device *rdev)
3681 {
3682         r600_disable_interrupts(rdev);
3683         /* Wait and acknowledge irq */
3684         mdelay(1);
3685         r600_irq_ack(rdev);
3686         r600_disable_interrupt_state(rdev);
3687 }
3688
3689 static u32 r600_get_ih_wptr(struct radeon_device *rdev)
3690 {
3691         u32 wptr, tmp;
3692
3693         if (rdev->wb.enabled)
3694                 wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]);
3695         else
3696                 wptr = RREG32(IH_RB_WPTR);
3697
3698         if (wptr & RB_OVERFLOW) {
3699                 /* When a ring buffer overflow happen start parsing interrupt
3700                  * from the last not overwritten vector (wptr + 16). Hopefully
3701                  * this should allow us to catchup.
3702                  */
3703                 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n",
3704                         wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask);
3705                 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
3706                 tmp = RREG32(IH_RB_CNTL);
3707                 tmp |= IH_WPTR_OVERFLOW_CLEAR;
3708                 WREG32(IH_RB_CNTL, tmp);
3709         }
3710         return (wptr & rdev->ih.ptr_mask);
3711 }
3712
3713 /*        r600 IV Ring
3714  * Each IV ring entry is 128 bits:
3715  * [7:0]    - interrupt source id
3716  * [31:8]   - reserved
3717  * [59:32]  - interrupt source data
3718  * [127:60]  - reserved
3719  *
3720  * The basic interrupt vector entries
3721  * are decoded as follows:
3722  * src_id  src_data  description
3723  *      1         0  D1 Vblank
3724  *      1         1  D1 Vline
3725  *      5         0  D2 Vblank
3726  *      5         1  D2 Vline
3727  *     19         0  FP Hot plug detection A
3728  *     19         1  FP Hot plug detection B
3729  *     19         2  DAC A auto-detection
3730  *     19         3  DAC B auto-detection
3731  *     21         4  HDMI block A
3732  *     21         5  HDMI block B
3733  *    176         -  CP_INT RB
3734  *    177         -  CP_INT IB1
3735  *    178         -  CP_INT IB2
3736  *    181         -  EOP Interrupt
3737  *    233         -  GUI Idle
3738  *
3739  * Note, these are based on r600 and may need to be
3740  * adjusted or added to on newer asics
3741  */
3742
3743 int r600_irq_process(struct radeon_device *rdev)
3744 {
3745         u32 wptr;
3746         u32 rptr;
3747         u32 src_id, src_data;
3748         u32 ring_index;
3749         bool queue_hotplug = false;
3750         bool queue_hdmi = false;
3751         bool queue_thermal = false;
3752
3753         if (!rdev->ih.enabled || rdev->shutdown)
3754                 return IRQ_NONE;
3755
3756         /* No MSIs, need a dummy read to flush PCI DMAs */
3757         if (!rdev->msi_enabled)
3758                 RREG32(IH_RB_WPTR);
3759
3760         wptr = r600_get_ih_wptr(rdev);
3761
3762 restart_ih:
3763         /* is somebody else already processing irqs? */
3764         if (atomic_xchg(&rdev->ih.lock, 1))
3765                 return IRQ_NONE;
3766
3767         rptr = rdev->ih.rptr;
3768         DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
3769
3770         /* Order reading of wptr vs. reading of IH ring data */
3771         rmb();
3772
3773         /* display interrupts */
3774         r600_irq_ack(rdev);
3775
3776         while (rptr != wptr) {
3777                 /* wptr/rptr are in bytes! */
3778                 ring_index = rptr / 4;
3779                 src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff;
3780                 src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff;
3781
3782                 switch (src_id) {
3783                 case 1: /* D1 vblank/vline */
3784                         switch (src_data) {
3785                         case 0: /* D1 vblank */
3786                                 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT) {
3787                                         if (rdev->irq.crtc_vblank_int[0]) {
3788                                                 drm_handle_vblank(rdev->ddev, 0);
3789                                                 rdev->pm.vblank_sync = true;
3790                                                 wake_up(&rdev->irq.vblank_queue);
3791                                         }
3792                                         if (atomic_read(&rdev->irq.pflip[0]))
3793                                                 radeon_crtc_handle_flip(rdev, 0);
3794                                         rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VBLANK_INTERRUPT;
3795                                         DRM_DEBUG("IH: D1 vblank\n");
3796                                 }
3797                                 break;
3798                         case 1: /* D1 vline */
3799                                 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT) {
3800                                         rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VLINE_INTERRUPT;
3801                                         DRM_DEBUG("IH: D1 vline\n");
3802                                 }
3803                                 break;
3804                         default:
3805                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3806                                 break;
3807                         }
3808                         break;
3809                 case 5: /* D2 vblank/vline */
3810                         switch (src_data) {
3811                         case 0: /* D2 vblank */
3812                                 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT) {
3813                                         if (rdev->irq.crtc_vblank_int[1]) {
3814                                                 drm_handle_vblank(rdev->ddev, 1);
3815                                                 rdev->pm.vblank_sync = true;
3816                                                 wake_up(&rdev->irq.vblank_queue);
3817                                         }
3818                                         if (atomic_read(&rdev->irq.pflip[1]))
3819                                                 radeon_crtc_handle_flip(rdev, 1);
3820                                         rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VBLANK_INTERRUPT;
3821                                         DRM_DEBUG("IH: D2 vblank\n");
3822                                 }
3823                                 break;
3824                         case 1: /* D1 vline */
3825                                 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT) {
3826                                         rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VLINE_INTERRUPT;
3827                                         DRM_DEBUG("IH: D2 vline\n");
3828                                 }
3829                                 break;
3830                         default:
3831                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3832                                 break;
3833                         }
3834                         break;
3835                 case 19: /* HPD/DAC hotplug */
3836                         switch (src_data) {
3837                         case 0:
3838                                 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT) {
3839                                         rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD1_INTERRUPT;
3840                                         queue_hotplug = true;
3841                                         DRM_DEBUG("IH: HPD1\n");
3842                                 }
3843                                 break;
3844                         case 1:
3845                                 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT) {
3846                                         rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD2_INTERRUPT;
3847                                         queue_hotplug = true;
3848                                         DRM_DEBUG("IH: HPD2\n");
3849                                 }
3850                                 break;
3851                         case 4:
3852                                 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT) {
3853                                         rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD3_INTERRUPT;
3854                                         queue_hotplug = true;
3855                                         DRM_DEBUG("IH: HPD3\n");
3856                                 }
3857                                 break;
3858                         case 5:
3859                                 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT) {
3860                                         rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD4_INTERRUPT;
3861                                         queue_hotplug = true;
3862                                         DRM_DEBUG("IH: HPD4\n");
3863                                 }
3864                                 break;
3865                         case 10:
3866                                 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT) {
3867                                         rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD5_INTERRUPT;
3868                                         queue_hotplug = true;
3869                                         DRM_DEBUG("IH: HPD5\n");
3870                                 }
3871                                 break;
3872                         case 12:
3873                                 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT) {
3874                                         rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD6_INTERRUPT;
3875                                         queue_hotplug = true;
3876                                         DRM_DEBUG("IH: HPD6\n");
3877                                 }
3878                                 break;
3879                         default:
3880                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3881                                 break;
3882                         }
3883                         break;
3884                 case 21: /* hdmi */
3885                         switch (src_data) {
3886                         case 4:
3887                                 if (rdev->irq.stat_regs.r600.hdmi0_status & HDMI0_AZ_FORMAT_WTRIG) {
3888                                         rdev->irq.stat_regs.r600.hdmi0_status &= ~HDMI0_AZ_FORMAT_WTRIG;
3889                                         queue_hdmi = true;
3890                                         DRM_DEBUG("IH: HDMI0\n");
3891                                 }
3892                                 break;
3893                         case 5:
3894                                 if (rdev->irq.stat_regs.r600.hdmi1_status & HDMI0_AZ_FORMAT_WTRIG) {
3895                                         rdev->irq.stat_regs.r600.hdmi1_status &= ~HDMI0_AZ_FORMAT_WTRIG;
3896                                         queue_hdmi = true;
3897                                         DRM_DEBUG("IH: HDMI1\n");
3898                                 }
3899                                 break;
3900                         default:
3901                                 DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data);
3902                                 break;
3903                         }
3904                         break;
3905                 case 176: /* CP_INT in ring buffer */
3906                 case 177: /* CP_INT in IB1 */
3907                 case 178: /* CP_INT in IB2 */
3908                         DRM_DEBUG("IH: CP int: 0x%08x\n", src_data);
3909                         radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
3910                         break;
3911                 case 181: /* CP EOP event */
3912                         DRM_DEBUG("IH: CP EOP\n");
3913                         radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
3914                         break;
3915                 case 224: /* DMA trap event */
3916                         DRM_DEBUG("IH: DMA trap\n");
3917                         radeon_fence_process(rdev, R600_RING_TYPE_DMA_INDEX);
3918                         break;
3919                 case 230: /* thermal low to high */
3920                         DRM_DEBUG("IH: thermal low to high\n");
3921                         rdev->pm.dpm.thermal.high_to_low = false;
3922                         queue_thermal = true;
3923                         break;
3924                 case 231: /* thermal high to low */
3925                         DRM_DEBUG("IH: thermal high to low\n");
3926                         rdev->pm.dpm.thermal.high_to_low = true;
3927                         queue_thermal = true;
3928                         break;
3929                 case 233: /* GUI IDLE */
3930                         DRM_DEBUG("IH: GUI idle\n");
3931                         break;
3932                 default:
3933                         DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3934                         break;
3935                 }
3936
3937                 /* wptr/rptr are in bytes! */
3938                 rptr += 16;
3939                 rptr &= rdev->ih.ptr_mask;
3940         }
3941         if (queue_hotplug)
3942                 schedule_work(&rdev->hotplug_work);
3943         if (queue_hdmi)
3944                 schedule_work(&rdev->audio_work);
3945         if (queue_thermal && rdev->pm.dpm_enabled)
3946                 schedule_work(&rdev->pm.dpm.thermal.work);
3947         rdev->ih.rptr = rptr;
3948         WREG32(IH_RB_RPTR, rdev->ih.rptr);
3949         atomic_set(&rdev->ih.lock, 0);
3950
3951         /* make sure wptr hasn't changed while processing */
3952         wptr = r600_get_ih_wptr(rdev);
3953         if (wptr != rptr)
3954                 goto restart_ih;
3955
3956         return IRQ_HANDLED;
3957 }
3958
3959 /*
3960  * Debugfs info
3961  */
3962 #if defined(CONFIG_DEBUG_FS)
3963
3964 static int r600_debugfs_mc_info(struct seq_file *m, void *data)
3965 {
3966         struct drm_info_node *node = (struct drm_info_node *) m->private;
3967         struct drm_device *dev = node->minor->dev;
3968         struct radeon_device *rdev = dev->dev_private;
3969
3970         DREG32_SYS(m, rdev, R_000E50_SRBM_STATUS);
3971         DREG32_SYS(m, rdev, VM_L2_STATUS);
3972         return 0;
3973 }
3974
3975 static struct drm_info_list r600_mc_info_list[] = {
3976         {"r600_mc_info", r600_debugfs_mc_info, 0, NULL},
3977 };
3978 #endif
3979
3980 int r600_debugfs_mc_info_init(struct radeon_device *rdev)
3981 {
3982 #if defined(CONFIG_DEBUG_FS)
3983         return radeon_debugfs_add_files(rdev, r600_mc_info_list, ARRAY_SIZE(r600_mc_info_list));
3984 #else
3985         return 0;
3986 #endif
3987 }
3988
3989 /**
3990  * r600_ioctl_wait_idle - flush host path cache on wait idle ioctl
3991  * rdev: radeon device structure
3992  * bo: buffer object struct which userspace is waiting for idle
3993  *
3994  * Some R6XX/R7XX doesn't seems to take into account HDP flush performed
3995  * through ring buffer, this leads to corruption in rendering, see
3996  * http://bugzilla.kernel.org/show_bug.cgi?id=15186 to avoid this we
3997  * directly perform HDP flush by writing register through MMIO.
3998  */
3999 void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo)
4000 {
4001         /* r7xx hw bug.  write to HDP_DEBUG1 followed by fb read
4002          * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL.
4003          * This seems to cause problems on some AGP cards. Just use the old
4004          * method for them.
4005          */
4006         if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) &&
4007             rdev->vram_scratch.ptr && !(rdev->flags & RADEON_IS_AGP)) {
4008                 void __iomem *ptr = (void *)rdev->vram_scratch.ptr;
4009                 u32 tmp;
4010
4011                 WREG32(HDP_DEBUG1, 0);
4012                 tmp = readl((void __iomem *)ptr);
4013         } else
4014                 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
4015 }
4016
4017 void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes)
4018 {
4019         u32 link_width_cntl, mask;
4020
4021         if (rdev->flags & RADEON_IS_IGP)
4022                 return;
4023
4024         if (!(rdev->flags & RADEON_IS_PCIE))
4025                 return;
4026
4027         /* x2 cards have a special sequence */
4028         if (ASIC_IS_X2(rdev))
4029                 return;
4030
4031         radeon_gui_idle(rdev);
4032
4033         switch (lanes) {
4034         case 0:
4035                 mask = RADEON_PCIE_LC_LINK_WIDTH_X0;
4036                 break;
4037         case 1:
4038                 mask = RADEON_PCIE_LC_LINK_WIDTH_X1;
4039                 break;
4040         case 2:
4041                 mask = RADEON_PCIE_LC_LINK_WIDTH_X2;
4042                 break;
4043         case 4:
4044                 mask = RADEON_PCIE_LC_LINK_WIDTH_X4;
4045                 break;
4046         case 8:
4047                 mask = RADEON_PCIE_LC_LINK_WIDTH_X8;
4048                 break;
4049         case 12:
4050                 /* not actually supported */
4051                 mask = RADEON_PCIE_LC_LINK_WIDTH_X12;
4052                 break;
4053         case 16:
4054                 mask = RADEON_PCIE_LC_LINK_WIDTH_X16;
4055                 break;
4056         default:
4057                 DRM_ERROR("invalid pcie lane request: %d\n", lanes);
4058                 return;
4059         }
4060
4061         link_width_cntl = RREG32_PCIE_PORT(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
4062         link_width_cntl &= ~RADEON_PCIE_LC_LINK_WIDTH_MASK;
4063         link_width_cntl |= mask << RADEON_PCIE_LC_LINK_WIDTH_SHIFT;
4064         link_width_cntl |= (RADEON_PCIE_LC_RECONFIG_NOW |
4065                             R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE);
4066
4067         WREG32_PCIE_PORT(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
4068 }
4069
4070 int r600_get_pcie_lanes(struct radeon_device *rdev)
4071 {
4072         u32 link_width_cntl;
4073
4074         if (rdev->flags & RADEON_IS_IGP)
4075                 return 0;
4076
4077         if (!(rdev->flags & RADEON_IS_PCIE))
4078                 return 0;
4079
4080         /* x2 cards have a special sequence */
4081         if (ASIC_IS_X2(rdev))
4082                 return 0;
4083
4084         radeon_gui_idle(rdev);
4085
4086         link_width_cntl = RREG32_PCIE_PORT(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
4087
4088         switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT) {
4089         case RADEON_PCIE_LC_LINK_WIDTH_X1:
4090                 return 1;
4091         case RADEON_PCIE_LC_LINK_WIDTH_X2:
4092                 return 2;
4093         case RADEON_PCIE_LC_LINK_WIDTH_X4:
4094                 return 4;
4095         case RADEON_PCIE_LC_LINK_WIDTH_X8:
4096                 return 8;
4097         case RADEON_PCIE_LC_LINK_WIDTH_X12:
4098                 /* not actually supported */
4099                 return 12;
4100         case RADEON_PCIE_LC_LINK_WIDTH_X0:
4101         case RADEON_PCIE_LC_LINK_WIDTH_X16:
4102         default:
4103                 return 16;
4104         }
4105 }
4106
4107 static void r600_pcie_gen2_enable(struct radeon_device *rdev)
4108 {
4109         u32 link_width_cntl, lanes, speed_cntl, training_cntl, tmp;
4110         u16 link_cntl2;
4111
4112         if (radeon_pcie_gen2 == 0)
4113                 return;
4114
4115         if (rdev->flags & RADEON_IS_IGP)
4116                 return;
4117
4118         if (!(rdev->flags & RADEON_IS_PCIE))
4119                 return;
4120
4121         /* x2 cards have a special sequence */
4122         if (ASIC_IS_X2(rdev))
4123                 return;
4124
4125         /* only RV6xx+ chips are supported */
4126         if (rdev->family <= CHIP_R600)
4127                 return;
4128
4129         if ((rdev->pdev->bus->max_bus_speed != PCIE_SPEED_5_0GT) &&
4130                 (rdev->pdev->bus->max_bus_speed != PCIE_SPEED_8_0GT))
4131                 return;
4132
4133         speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
4134         if (speed_cntl & LC_CURRENT_DATA_RATE) {
4135                 DRM_INFO("PCIE gen 2 link speeds already enabled\n");
4136                 return;
4137         }
4138
4139         DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n");
4140
4141         /* 55 nm r6xx asics */
4142         if ((rdev->family == CHIP_RV670) ||
4143             (rdev->family == CHIP_RV620) ||
4144             (rdev->family == CHIP_RV635)) {
4145                 /* advertise upconfig capability */
4146                 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
4147                 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
4148                 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
4149                 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
4150                 if (link_width_cntl & LC_RENEGOTIATION_SUPPORT) {
4151                         lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT;
4152                         link_width_cntl &= ~(LC_LINK_WIDTH_MASK |
4153                                              LC_RECONFIG_ARC_MISSING_ESCAPE);
4154                         link_width_cntl |= lanes | LC_RECONFIG_NOW | LC_RENEGOTIATE_EN;
4155                         WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
4156                 } else {
4157                         link_width_cntl |= LC_UPCONFIGURE_DIS;
4158                         WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
4159                 }
4160         }
4161
4162         speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
4163         if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) &&
4164             (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
4165
4166                 /* 55 nm r6xx asics */
4167                 if ((rdev->family == CHIP_RV670) ||
4168                     (rdev->family == CHIP_RV620) ||
4169                     (rdev->family == CHIP_RV635)) {
4170                         WREG32(MM_CFGREGS_CNTL, 0x8);
4171                         link_cntl2 = RREG32(0x4088);
4172                         WREG32(MM_CFGREGS_CNTL, 0);
4173                         /* not supported yet */
4174                         if (link_cntl2 & SELECTABLE_DEEMPHASIS)
4175                                 return;
4176                 }
4177
4178                 speed_cntl &= ~LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK;
4179                 speed_cntl |= (0x3 << LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT);
4180                 speed_cntl &= ~LC_VOLTAGE_TIMER_SEL_MASK;
4181                 speed_cntl &= ~LC_FORCE_DIS_HW_SPEED_CHANGE;
4182                 speed_cntl |= LC_FORCE_EN_HW_SPEED_CHANGE;
4183                 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
4184
4185                 tmp = RREG32(0x541c);
4186                 WREG32(0x541c, tmp | 0x8);
4187                 WREG32(MM_CFGREGS_CNTL, MM_WR_TO_CFG_EN);
4188                 link_cntl2 = RREG16(0x4088);
4189                 link_cntl2 &= ~TARGET_LINK_SPEED_MASK;
4190                 link_cntl2 |= 0x2;
4191                 WREG16(0x4088, link_cntl2);
4192                 WREG32(MM_CFGREGS_CNTL, 0);
4193
4194                 if ((rdev->family == CHIP_RV670) ||
4195                     (rdev->family == CHIP_RV620) ||
4196                     (rdev->family == CHIP_RV635)) {
4197                         training_cntl = RREG32_PCIE_PORT(PCIE_LC_TRAINING_CNTL);
4198                         training_cntl &= ~LC_POINT_7_PLUS_EN;
4199                         WREG32_PCIE_PORT(PCIE_LC_TRAINING_CNTL, training_cntl);
4200                 } else {
4201                         speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
4202                         speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN;
4203                         WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
4204                 }
4205
4206                 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
4207                 speed_cntl |= LC_GEN2_EN_STRAP;
4208                 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
4209
4210         } else {
4211                 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
4212                 /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */
4213                 if (1)
4214                         link_width_cntl |= LC_UPCONFIGURE_DIS;
4215                 else
4216                         link_width_cntl &= ~LC_UPCONFIGURE_DIS;
4217                 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
4218         }
4219 }
4220
4221 /**
4222  * r600_get_gpu_clock_counter - return GPU clock counter snapshot
4223  *
4224  * @rdev: radeon_device pointer
4225  *
4226  * Fetches a GPU clock counter snapshot (R6xx-cayman).
4227  * Returns the 64 bit clock counter snapshot.
4228  */
4229 uint64_t r600_get_gpu_clock_counter(struct radeon_device *rdev)
4230 {
4231         uint64_t clock;
4232
4233         mutex_lock(&rdev->gpu_clock_mutex);
4234         WREG32(RLC_CAPTURE_GPU_CLOCK_COUNT, 1);
4235         clock = (uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_LSB) |
4236                 ((uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
4237         mutex_unlock(&rdev->gpu_clock_mutex);
4238         return clock;
4239 }