drivers/gpu/drm/radeon/r300.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/seq_file.h>
  29 #include <linux/slab.h>
  30 #include <drm/drmP.h>
  31 #include <drm/drm.h>
  32 #include <drm/drm_crtc_helper.h>
  33 #include "radeon_reg.h"
  34 #include "radeon.h"
  35 #include "radeon_asic.h"
  36 #include "radeon_drm.h"
  37 #include "r100_track.h"
  38 #include "r300d.h"
  39 #include "rv350d.h"
  40 #include "r300_reg_safe.h"
  41
  42 /* This files gather functions specifics to: r300,r350,rv350,rv370,rv380
  43  *
  44  * GPU Errata:
  45  * - HOST_PATH_CNTL: r300 family seems to dislike write to HOST_PATH_CNTL
  46  *   using MMIO to flush host path read cache, this lead to HARDLOCKUP.
  47  *   However, scheduling such write to the ring seems harmless, i suspect
  48  *   the CP read collide with the flush somehow, or maybe the MC, hard to
  49  *   tell. (Jerome Glisse)
  50  */
  51
  52 /*
  53  * rv370,rv380 PCIE GART
  54  */
  55 static int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev);
  56
  57 void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev)
  58 {
  59         uint32_t tmp;
  60         int i;
  61
  62         /* Workaround HW bug do flush 2 times */
  63         for (i = 0; i < 2; i++) {
  64                 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
  65                 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp | RADEON_PCIE_TX_GART_INVALIDATE_TLB);
  66                 (void)RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
  67                 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
  68         }
  69         mb();
  70 }
  71
  72 #define R300_PTE_WRITEABLE (1 << 2)
  73 #define R300_PTE_READABLE  (1 << 3)
  74
  75 int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
  76 {
  77         void __iomem *ptr = rdev->gart.ptr;
  78
  79         if (i < 0 || i > rdev->gart.num_gpu_pages) {
  80                 return -EINVAL;
  81         }
  82         addr = (lower_32_bits(addr) >> 8) |
  83                ((upper_32_bits(addr) & 0xff) << 24) |
  84                R300_PTE_WRITEABLE | R300_PTE_READABLE;
  85         /* on x86 we want this to be CPU endian, on powerpc
  86          * on powerpc without HW swappers, it'll get swapped on way
  87          * into VRAM - so no need for cpu_to_le32 on VRAM tables */
  88         writel(addr, ((void __iomem *)ptr) + (i * 4));
  89         return 0;
  90 }
  91
  92 int rv370_pcie_gart_init(struct radeon_device *rdev)
  93 {
  94         int r;
  95
  96         if (rdev->gart.robj) {
  97                 WARN(1, "RV370 PCIE GART already initialized\n");
  98                 return 0;
  99         }
 100         /* Initialize common gart structure */
 101         r = radeon_gart_init(rdev);
 102         if (r)
 103                 return r;
 104         r = rv370_debugfs_pcie_gart_info_init(rdev);
 105         if (r)
 106                 DRM_ERROR("Failed to register debugfs file for PCIE gart !\n");
 107         rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
 108         rdev->asic->gart.tlb_flush = &rv370_pcie_gart_tlb_flush;
 109         rdev->asic->gart.set_page = &rv370_pcie_gart_set_page;
 110         return radeon_gart_table_vram_alloc(rdev);
 111 }
 112
 113 int rv370_pcie_gart_enable(struct radeon_device *rdev)
 114 {
 115         uint32_t table_addr;
 116         uint32_t tmp;
 117         int r;
 118
 119         if (rdev->gart.robj == NULL) {
 120                 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
 121                 return -EINVAL;
 122         }
 123         r = radeon_gart_table_vram_pin(rdev);
 124         if (r)
 125                 return r;
 126         radeon_gart_restore(rdev);
 127         /* discard memory request outside of configured range */
 128         tmp = RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
 129         WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
 130         WREG32_PCIE(RADEON_PCIE_TX_GART_START_LO, rdev->mc.gtt_start);
 131         tmp = rdev->mc.gtt_end & ~RADEON_GPU_PAGE_MASK;
 132         WREG32_PCIE(RADEON_PCIE_TX_GART_END_LO, tmp);
 133         WREG32_PCIE(RADEON_PCIE_TX_GART_START_HI, 0);
 134         WREG32_PCIE(RADEON_PCIE_TX_GART_END_HI, 0);
 135         table_addr = rdev->gart.table_addr;
 136         WREG32_PCIE(RADEON_PCIE_TX_GART_BASE, table_addr);
 137         /* FIXME: setup default page */
 138         WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO, rdev->mc.vram_start);
 139         WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_HI, 0);
 140         /* Clear error */
 141         WREG32_PCIE(RADEON_PCIE_TX_GART_ERROR, 0);
 142         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
 143         tmp |= RADEON_PCIE_TX_GART_EN;
 144         tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
 145         WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
 146         rv370_pcie_gart_tlb_flush(rdev);
 147         DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
 148                  (unsigned)(rdev->mc.gtt_size >> 20),
 149                  (unsigned long long)table_addr);
 150         rdev->gart.ready = true;
 151         return 0;
 152 }
 153
 154 void rv370_pcie_gart_disable(struct radeon_device *rdev)
 155 {
 156         u32 tmp;
 157
 158         WREG32_PCIE(RADEON_PCIE_TX_GART_START_LO, 0);
 159         WREG32_PCIE(RADEON_PCIE_TX_GART_END_LO, 0);
 160         WREG32_PCIE(RADEON_PCIE_TX_GART_START_HI, 0);
 161         WREG32_PCIE(RADEON_PCIE_TX_GART_END_HI, 0);
 162         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
 163         tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
 164         WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp & ~RADEON_PCIE_TX_GART_EN);
 165         radeon_gart_table_vram_unpin(rdev);
 166 }
 167
 168 void rv370_pcie_gart_fini(struct radeon_device *rdev)
 169 {
 170         radeon_gart_fini(rdev);
 171         rv370_pcie_gart_disable(rdev);
 172         radeon_gart_table_vram_free(rdev);
 173 }
 174
 175 void r300_fence_ring_emit(struct radeon_device *rdev,
 176                           struct radeon_fence *fence)
 177 {
 178         struct radeon_ring *ring = &rdev->ring[fence->ring];
 179
 180         /* Who ever call radeon_fence_emit should call ring_lock and ask
 181          * for enough space (today caller are ib schedule and buffer move) */
 182         /* Write SC register so SC & US assert idle */
 183         radeon_ring_write(ring, PACKET0(R300_RE_SCISSORS_TL, 0));
 184         radeon_ring_write(ring, 0);
 185         radeon_ring_write(ring, PACKET0(R300_RE_SCISSORS_BR, 0));
 186         radeon_ring_write(ring, 0);
 187         /* Flush 3D cache */
 188         radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
 189         radeon_ring_write(ring, R300_RB3D_DC_FLUSH);
 190         radeon_ring_write(ring, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
 191         radeon_ring_write(ring, R300_ZC_FLUSH);
 192         /* Wait until IDLE & CLEAN */
 193         radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
 194         radeon_ring_write(ring, (RADEON_WAIT_3D_IDLECLEAN |
 195                                  RADEON_WAIT_2D_IDLECLEAN |
 196                                  RADEON_WAIT_DMA_GUI_IDLE));
 197         radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));
 198         radeon_ring_write(ring, rdev->config.r300.hdp_cntl |
 199                                 RADEON_HDP_READ_BUFFER_INVALIDATE);
 200         radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));
 201         radeon_ring_write(ring, rdev->config.r300.hdp_cntl);
 202         /* Emit fence sequence & fire IRQ */
 203         radeon_ring_write(ring, PACKET0(rdev->fence_drv[fence->ring].scratch_reg, 0));
 204         radeon_ring_write(ring, fence->seq);
 205         radeon_ring_write(ring, PACKET0(RADEON_GEN_INT_STATUS, 0));
 206         radeon_ring_write(ring, RADEON_SW_INT_FIRE);
 207 }
 208
 209 void r300_ring_start(struct radeon_device *rdev, struct radeon_ring *ring)
 210 {
 211         unsigned gb_tile_config;
 212         int r;
 213
 214         /* Sub pixel 1/12 so we can have 4K rendering according to doc */
 215         gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16);
 216         switch(rdev->num_gb_pipes) {
 217         case 2:
 218                 gb_tile_config |= R300_PIPE_COUNT_R300;
 219                 break;
 220         case 3:
 221                 gb_tile_config |= R300_PIPE_COUNT_R420_3P;
 222                 break;
 223         case 4:
 224                 gb_tile_config |= R300_PIPE_COUNT_R420;
 225                 break;
 226         case 1:
 227         default:
 228                 gb_tile_config |= R300_PIPE_COUNT_RV350;
 229                 break;
 230         }
 231
 232         r = radeon_ring_lock(rdev, ring, 64);
 233         if (r) {
 234                 return;
 235         }
 236         radeon_ring_write(ring, PACKET0(RADEON_ISYNC_CNTL, 0));
 237         radeon_ring_write(ring,
 238                           RADEON_ISYNC_ANY2D_IDLE3D |
 239                           RADEON_ISYNC_ANY3D_IDLE2D |
 240                           RADEON_ISYNC_WAIT_IDLEGUI |
 241                           RADEON_ISYNC_CPSCRATCH_IDLEGUI);
 242         radeon_ring_write(ring, PACKET0(R300_GB_TILE_CONFIG, 0));
 243         radeon_ring_write(ring, gb_tile_config);
 244         radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
 245         radeon_ring_write(ring,
 246                           RADEON_WAIT_2D_IDLECLEAN |
 247                           RADEON_WAIT_3D_IDLECLEAN);
 248         radeon_ring_write(ring, PACKET0(R300_DST_PIPE_CONFIG, 0));
 249         radeon_ring_write(ring, R300_PIPE_AUTO_CONFIG);
 250         radeon_ring_write(ring, PACKET0(R300_GB_SELECT, 0));
 251         radeon_ring_write(ring, 0);
 252         radeon_ring_write(ring, PACKET0(R300_GB_ENABLE, 0));
 253         radeon_ring_write(ring, 0);
 254         radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
 255         radeon_ring_write(ring, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE);
 256         radeon_ring_write(ring, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
 257         radeon_ring_write(ring, R300_ZC_FLUSH | R300_ZC_FREE);
 258         radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
 259         radeon_ring_write(ring,
 260                           RADEON_WAIT_2D_IDLECLEAN |
 261                           RADEON_WAIT_3D_IDLECLEAN);
 262         radeon_ring_write(ring, PACKET0(R300_GB_AA_CONFIG, 0));
 263         radeon_ring_write(ring, 0);
 264         radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
 265         radeon_ring_write(ring, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE);
 266         radeon_ring_write(ring, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
 267         radeon_ring_write(ring, R300_ZC_FLUSH | R300_ZC_FREE);
 268         radeon_ring_write(ring, PACKET0(R300_GB_MSPOS0, 0));
 269         radeon_ring_write(ring,
 270                           ((6 << R300_MS_X0_SHIFT) |
 271                            (6 << R300_MS_Y0_SHIFT) |
 272                            (6 << R300_MS_X1_SHIFT) |
 273                            (6 << R300_MS_Y1_SHIFT) |
 274                            (6 << R300_MS_X2_SHIFT) |
 275                            (6 << R300_MS_Y2_SHIFT) |
 276                            (6 << R300_MSBD0_Y_SHIFT) |
 277                            (6 << R300_MSBD0_X_SHIFT)));
 278         radeon_ring_write(ring, PACKET0(R300_GB_MSPOS1, 0));
 279         radeon_ring_write(ring,
 280                           ((6 << R300_MS_X3_SHIFT) |
 281                            (6 << R300_MS_Y3_SHIFT) |
 282                            (6 << R300_MS_X4_SHIFT) |
 283                            (6 << R300_MS_Y4_SHIFT) |
 284                            (6 << R300_MS_X5_SHIFT) |
 285                            (6 << R300_MS_Y5_SHIFT) |
 286                            (6 << R300_MSBD1_SHIFT)));
 287         radeon_ring_write(ring, PACKET0(R300_GA_ENHANCE, 0));
 288         radeon_ring_write(ring, R300_GA_DEADLOCK_CNTL | R300_GA_FASTSYNC_CNTL);
 289         radeon_ring_write(ring, PACKET0(R300_GA_POLY_MODE, 0));
 290         radeon_ring_write(ring,
 291                           R300_FRONT_PTYPE_TRIANGE | R300_BACK_PTYPE_TRIANGE);
 292         radeon_ring_write(ring, PACKET0(R300_GA_ROUND_MODE, 0));
 293         radeon_ring_write(ring,
 294                           R300_GEOMETRY_ROUND_NEAREST |
 295                           R300_COLOR_ROUND_NEAREST);
 296         radeon_ring_unlock_commit(rdev, ring);
 297 }
 298
 299 void r300_errata(struct radeon_device *rdev)
 300 {
 301         rdev->pll_errata = 0;
 302
 303         if (rdev->family == CHIP_R300 &&
 304             (RREG32(RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) == RADEON_CFG_ATI_REV_A11) {
 305                 rdev->pll_errata |= CHIP_ERRATA_R300_CG;
 306         }
 307 }
 308
 309 int r300_mc_wait_for_idle(struct radeon_device *rdev)
 310 {
 311         unsigned i;
 312         uint32_t tmp;
 313
 314         for (i = 0; i < rdev->usec_timeout; i++) {
 315                 /* read MC_STATUS */
 316                 tmp = RREG32(RADEON_MC_STATUS);
 317                 if (tmp & R300_MC_IDLE) {
 318                         return 0;
 319                 }
 320                 DRM_UDELAY(1);
 321         }
 322         return -1;
 323 }
 324
 325 void r300_gpu_init(struct radeon_device *rdev)
 326 {
 327         uint32_t gb_tile_config, tmp;
 328
 329         if ((rdev->family == CHIP_R300 && rdev->pdev->device != 0x4144) ||
 330             (rdev->family == CHIP_R350 && rdev->pdev->device != 0x4148)) {
 331                 /* r300,r350 */
 332                 rdev->num_gb_pipes = 2;
 333         } else {
 334                 /* rv350,rv370,rv380,r300 AD, r350 AH */
 335                 rdev->num_gb_pipes = 1;
 336         }
 337         rdev->num_z_pipes = 1;
 338         gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16);
 339         switch (rdev->num_gb_pipes) {
 340         case 2:
 341                 gb_tile_config |= R300_PIPE_COUNT_R300;
 342                 break;
 343         case 3:
 344                 gb_tile_config |= R300_PIPE_COUNT_R420_3P;
 345                 break;
 346         case 4:
 347                 gb_tile_config |= R300_PIPE_COUNT_R420;
 348                 break;
 349         default:
 350         case 1:
 351                 gb_tile_config |= R300_PIPE_COUNT_RV350;
 352                 break;
 353         }
 354         WREG32(R300_GB_TILE_CONFIG, gb_tile_config);
 355
 356         if (r100_gui_wait_for_idle(rdev)) {
 357                 printk(KERN_WARNING "Failed to wait GUI idle while "
 358                        "programming pipes. Bad things might happen.\n");
 359         }
 360
 361         tmp = RREG32(R300_DST_PIPE_CONFIG);
 362         WREG32(R300_DST_PIPE_CONFIG, tmp | R300_PIPE_AUTO_CONFIG);
 363
 364         WREG32(R300_RB2D_DSTCACHE_MODE,
 365                R300_DC_AUTOFLUSH_ENABLE |
 366                R300_DC_DC_DISABLE_IGNORE_PE);
 367
 368         if (r100_gui_wait_for_idle(rdev)) {
 369                 printk(KERN_WARNING "Failed to wait GUI idle while "
 370                        "programming pipes. Bad things might happen.\n");
 371         }
 372         if (r300_mc_wait_for_idle(rdev)) {
 373                 printk(KERN_WARNING "Failed to wait MC idle while "
 374                        "programming pipes. Bad things might happen.\n");
 375         }
 376         DRM_INFO("radeon: %d quad pipes, %d Z pipes initialized.\n",
 377                  rdev->num_gb_pipes, rdev->num_z_pipes);
 378 }
 379
 380 bool r300_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
 381 {
 382         u32 rbbm_status;
 383         int r;
 384
 385         rbbm_status = RREG32(R_000E40_RBBM_STATUS);
 386         if (!G_000E40_GUI_ACTIVE(rbbm_status)) {
 387                 r100_gpu_lockup_update(&rdev->config.r300.lockup, ring);
 388                 return false;
 389         }
 390         /* force CP activities */
 391         r = radeon_ring_lock(rdev, ring, 2);
 392         if (!r) {
 393                 /* PACKET2 NOP */
 394                 radeon_ring_write(ring, 0x80000000);
 395                 radeon_ring_write(ring, 0x80000000);
 396                 radeon_ring_unlock_commit(rdev, ring);
 397         }
 398         ring->rptr = RREG32(RADEON_CP_RB_RPTR);
 399         return r100_gpu_cp_is_lockup(rdev, &rdev->config.r300.lockup, ring);
 400 }
 401
 402 int r300_asic_reset(struct radeon_device *rdev)
 403 {
 404         struct r100_mc_save save;
 405         u32 status, tmp;
 406         int ret = 0;
 407
 408         status = RREG32(R_000E40_RBBM_STATUS);
 409         if (!G_000E40_GUI_ACTIVE(status)) {
 410                 return 0;
 411         }
 412         r100_mc_stop(rdev, &save);
 413         status = RREG32(R_000E40_RBBM_STATUS);
 414         dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
 415         /* stop CP */
 416         WREG32(RADEON_CP_CSQ_CNTL, 0);
 417         tmp = RREG32(RADEON_CP_RB_CNTL);
 418         WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
 419         WREG32(RADEON_CP_RB_RPTR_WR, 0);
 420         WREG32(RADEON_CP_RB_WPTR, 0);
 421         WREG32(RADEON_CP_RB_CNTL, tmp);
 422         /* save PCI state */
 423         pci_save_state(rdev->pdev);
 424         /* disable bus mastering */
 425         r100_bm_disable(rdev);
 426         WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_VAP(1) |
 427                                         S_0000F0_SOFT_RESET_GA(1));
 428         RREG32(R_0000F0_RBBM_SOFT_RESET);
 429         mdelay(500);
 430         WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
 431         mdelay(1);
 432         status = RREG32(R_000E40_RBBM_STATUS);
 433         dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
 434         /* resetting the CP seems to be problematic sometimes it end up
 435          * hard locking the computer, but it's necessary for successful
 436          * reset more test & playing is needed on R3XX/R4XX to find a
 437          * reliable (if any solution)
 438          */
 439         WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1));
 440         RREG32(R_0000F0_RBBM_SOFT_RESET);
 441         mdelay(500);
 442         WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
 443         mdelay(1);
 444         status = RREG32(R_000E40_RBBM_STATUS);
 445         dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
 446         /* restore PCI & busmastering */
 447         pci_restore_state(rdev->pdev);
 448         r100_enable_bm(rdev);
 449         /* Check if GPU is idle */
 450         if (G_000E40_GA_BUSY(status) || G_000E40_VAP_BUSY(status)) {
 451                 dev_err(rdev->dev, "failed to reset GPU\n");
 452                 ret = -1;
 453         } else
 454                 dev_info(rdev->dev, "GPU reset succeed\n");
 455         r100_mc_resume(rdev, &save);
 456         return ret;
 457 }
 458
 459 /*
 460  * r300,r350,rv350,rv380 VRAM info
 461  */
 462 void r300_mc_init(struct radeon_device *rdev)
 463 {
 464         u64 base;
 465         u32 tmp;
 466
 467         /* DDR for all card after R300 & IGP */
 468         rdev->mc.vram_is_ddr = true;
 469         tmp = RREG32(RADEON_MEM_CNTL);
 470         tmp &= R300_MEM_NUM_CHANNELS_MASK;
 471         switch (tmp) {
 472         case 0: rdev->mc.vram_width = 64; break;
 473         case 1: rdev->mc.vram_width = 128; break;
 474         case 2: rdev->mc.vram_width = 256; break;
 475         default:  rdev->mc.vram_width = 128; break;
 476         }
 477         r100_vram_init_sizes(rdev);
 478         base = rdev->mc.aper_base;
 479         if (rdev->flags & RADEON_IS_IGP)
 480                 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
 481         radeon_vram_location(rdev, &rdev->mc, base);
 482         rdev->mc.gtt_base_align = 0;
 483         if (!(rdev->flags & RADEON_IS_AGP))
 484                 radeon_gtt_location(rdev, &rdev->mc);
 485         radeon_update_bandwidth_info(rdev);
 486 }
 487
 488 void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes)
 489 {
 490         uint32_t link_width_cntl, mask;
 491
 492         if (rdev->flags & RADEON_IS_IGP)
 493                 return;
 494
 495         if (!(rdev->flags & RADEON_IS_PCIE))
 496                 return;
 497
 498         /* FIXME wait for idle */
 499
 500         switch (lanes) {
 501         case 0:
 502                 mask = RADEON_PCIE_LC_LINK_WIDTH_X0;
 503                 break;
 504         case 1:
 505                 mask = RADEON_PCIE_LC_LINK_WIDTH_X1;
 506                 break;
 507         case 2:
 508                 mask = RADEON_PCIE_LC_LINK_WIDTH_X2;
 509                 break;
 510         case 4:
 511                 mask = RADEON_PCIE_LC_LINK_WIDTH_X4;
 512                 break;
 513         case 8:
 514                 mask = RADEON_PCIE_LC_LINK_WIDTH_X8;
 515                 break;
 516         case 12:
 517                 mask = RADEON_PCIE_LC_LINK_WIDTH_X12;
 518                 break;
 519         case 16:
 520         default:
 521                 mask = RADEON_PCIE_LC_LINK_WIDTH_X16;
 522                 break;
 523         }
 524
 525         link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
 526
 527         if ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) ==
 528             (mask << RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT))
 529                 return;
 530
 531         link_width_cntl &= ~(RADEON_PCIE_LC_LINK_WIDTH_MASK |
 532                              RADEON_PCIE_LC_RECONFIG_NOW |
 533                              RADEON_PCIE_LC_RECONFIG_LATER |
 534                              RADEON_PCIE_LC_SHORT_RECONFIG_EN);
 535         link_width_cntl |= mask;
 536         WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
 537         WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, (link_width_cntl |
 538                                                      RADEON_PCIE_LC_RECONFIG_NOW));
 539
 540         /* wait for lane set to complete */
 541         link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
 542         while (link_width_cntl == 0xffffffff)
 543                 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
 544
 545 }
 546
 547 int rv370_get_pcie_lanes(struct radeon_device *rdev)
 548 {
 549         u32 link_width_cntl;
 550
 551         if (rdev->flags & RADEON_IS_IGP)
 552                 return 0;
 553
 554         if (!(rdev->flags & RADEON_IS_PCIE))
 555                 return 0;
 556
 557         /* FIXME wait for idle */
 558
 559         link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
 560
 561         switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT) {
 562         case RADEON_PCIE_LC_LINK_WIDTH_X0:
 563                 return 0;
 564         case RADEON_PCIE_LC_LINK_WIDTH_X1:
 565                 return 1;
 566         case RADEON_PCIE_LC_LINK_WIDTH_X2:
 567                 return 2;
 568         case RADEON_PCIE_LC_LINK_WIDTH_X4:
 569                 return 4;
 570         case RADEON_PCIE_LC_LINK_WIDTH_X8:
 571                 return 8;
 572         case RADEON_PCIE_LC_LINK_WIDTH_X16:
 573         default:
 574                 return 16;
 575         }
 576 }
 577
 578 #if defined(CONFIG_DEBUG_FS)
 579 static int rv370_debugfs_pcie_gart_info(struct seq_file *m, void *data)
 580 {
 581         struct drm_info_node *node = (struct drm_info_node *) m->private;
 582         struct drm_device *dev = node->minor->dev;
 583         struct radeon_device *rdev = dev->dev_private;
 584         uint32_t tmp;
 585
 586         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
 587         seq_printf(m, "PCIE_TX_GART_CNTL 0x%08x\n", tmp);
 588         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_BASE);
 589         seq_printf(m, "PCIE_TX_GART_BASE 0x%08x\n", tmp);
 590         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_LO);
 591         seq_printf(m, "PCIE_TX_GART_START_LO 0x%08x\n", tmp);
 592         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_HI);
 593         seq_printf(m, "PCIE_TX_GART_START_HI 0x%08x\n", tmp);
 594         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_LO);
 595         seq_printf(m, "PCIE_TX_GART_END_LO 0x%08x\n", tmp);
 596         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_HI);
 597         seq_printf(m, "PCIE_TX_GART_END_HI 0x%08x\n", tmp);
 598         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_ERROR);
 599         seq_printf(m, "PCIE_TX_GART_ERROR 0x%08x\n", tmp);
 600         return 0;
 601 }
 602
 603 static struct drm_info_list rv370_pcie_gart_info_list[] = {
 604         {"rv370_pcie_gart_info", rv370_debugfs_pcie_gart_info, 0, NULL},
 605 };
 606 #endif
 607
 608 static int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev)
 609 {
 610 #if defined(CONFIG_DEBUG_FS)
 611         return radeon_debugfs_add_files(rdev, rv370_pcie_gart_info_list, 1);
 612 #else
 613         return 0;
 614 #endif
 615 }
 616
 617 static int r300_packet0_check(struct radeon_cs_parser *p,
 618                 struct radeon_cs_packet *pkt,
 619                 unsigned idx, unsigned reg)
 620 {
 621         struct radeon_cs_reloc *reloc;
 622         struct r100_cs_track *track;
 623         volatile uint32_t *ib;
 624         uint32_t tmp, tile_flags = 0;
 625         unsigned i;
 626         int r;
 627         u32 idx_value;
 628
 629         ib = p->ib->ptr;
 630         track = (struct r100_cs_track *)p->track;
 631         idx_value = radeon_get_ib_value(p, idx);
 632
 633         switch(reg) {
 634         case AVIVO_D1MODE_VLINE_START_END:
 635         case RADEON_CRTC_GUI_TRIG_VLINE:
 636                 r = r100_cs_packet_parse_vline(p);
 637                 if (r) {
 638                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
 639                                         idx, reg);
 640                         r100_cs_dump_packet(p, pkt);
 641                         return r;
 642                 }
 643                 break;
 644         case RADEON_DST_PITCH_OFFSET:
 645         case RADEON_SRC_PITCH_OFFSET:
 646                 r = r100_reloc_pitch_offset(p, pkt, idx, reg);
 647                 if (r)
 648                         return r;
 649                 break;
 650         case R300_RB3D_COLOROFFSET0:
 651         case R300_RB3D_COLOROFFSET1:
 652         case R300_RB3D_COLOROFFSET2:
 653         case R300_RB3D_COLOROFFSET3:
 654                 i = (reg - R300_RB3D_COLOROFFSET0) >> 2;
 655                 r = r100_cs_packet_next_reloc(p, &reloc);
 656                 if (r) {
 657                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
 658                                         idx, reg);
 659                         r100_cs_dump_packet(p, pkt);
 660                         return r;
 661                 }
 662                 track->cb[i].robj = reloc->robj;
 663                 track->cb[i].offset = idx_value;
 664                 track->cb_dirty = true;
 665                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
 666                 break;
 667         case R300_ZB_DEPTHOFFSET:
 668                 r = r100_cs_packet_next_reloc(p, &reloc);
 669                 if (r) {
 670                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
 671                                         idx, reg);
 672                         r100_cs_dump_packet(p, pkt);
 673                         return r;
 674                 }
 675                 track->zb.robj = reloc->robj;
 676                 track->zb.offset = idx_value;
 677                 track->zb_dirty = true;
 678                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
 679                 break;
 680         case R300_TX_OFFSET_0:
 681         case R300_TX_OFFSET_0+4:
 682         case R300_TX_OFFSET_0+8:
 683         case R300_TX_OFFSET_0+12:
 684         case R300_TX_OFFSET_0+16:
 685         case R300_TX_OFFSET_0+20:
 686         case R300_TX_OFFSET_0+24:
 687         case R300_TX_OFFSET_0+28:
 688         case R300_TX_OFFSET_0+32:
 689         case R300_TX_OFFSET_0+36:
 690         case R300_TX_OFFSET_0+40:
 691         case R300_TX_OFFSET_0+44:
 692         case R300_TX_OFFSET_0+48:
 693         case R300_TX_OFFSET_0+52:
 694         case R300_TX_OFFSET_0+56:
 695         case R300_TX_OFFSET_0+60:
 696                 i = (reg - R300_TX_OFFSET_0) >> 2;
 697                 r = r100_cs_packet_next_reloc(p, &reloc);
 698                 if (r) {
 699                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
 700                                         idx, reg);
 701                         r100_cs_dump_packet(p, pkt);
 702                         return r;
 703                 }
 704
 705                 if (p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS) {
 706                         ib[idx] = (idx_value & 31) | /* keep the 1st 5 bits */
 707                                   ((idx_value & ~31) + (u32)reloc->lobj.gpu_offset);
 708                 } else {
 709                         if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
 710                                 tile_flags |= R300_TXO_MACRO_TILE;
 711                         if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
 712                                 tile_flags |= R300_TXO_MICRO_TILE;
 713                         else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO_SQUARE)
 714                                 tile_flags |= R300_TXO_MICRO_TILE_SQUARE;
 715
 716                         tmp = idx_value + ((u32)reloc->lobj.gpu_offset);
 717                         tmp |= tile_flags;
 718                         ib[idx] = tmp;
 719                 }
 720                 track->textures[i].robj = reloc->robj;
 721                 track->tex_dirty = true;
 722                 break;
 723         /* Tracked registers */
 724         case 0x2084:
 725                 /* VAP_VF_CNTL */
 726                 track->vap_vf_cntl = idx_value;
 727                 break;
 728         case 0x20B4:
 729                 /* VAP_VTX_SIZE */
 730                 track->vtx_size = idx_value & 0x7F;
 731                 break;
 732         case 0x2134:
 733                 /* VAP_VF_MAX_VTX_INDX */
 734                 track->max_indx = idx_value & 0x00FFFFFFUL;
 735                 break;
 736         case 0x2088:
 737                 /* VAP_ALT_NUM_VERTICES - only valid on r500 */
 738                 if (p->rdev->family < CHIP_RV515)
 739                         goto fail;
 740                 track->vap_alt_nverts = idx_value & 0xFFFFFF;
 741                 break;
 742         case 0x43E4:
 743                 /* SC_SCISSOR1 */
 744                 track->maxy = ((idx_value >> 13) & 0x1FFF) + 1;
 745                 if (p->rdev->family < CHIP_RV515) {
 746                         track->maxy -= 1440;
 747                 }
 748                 track->cb_dirty = true;
 749                 track->zb_dirty = true;
 750                 break;
 751         case 0x4E00:
 752                 /* RB3D_CCTL */
 753                 if ((idx_value & (1 << 10)) && /* CMASK_ENABLE */
 754                     p->rdev->cmask_filp != p->filp) {
 755                         DRM_ERROR("Invalid RB3D_CCTL: Cannot enable CMASK.\n");
 756                         return -EINVAL;
 757                 }
 758                 track->num_cb = ((idx_value >> 5) & 0x3) + 1;
 759                 track->cb_dirty = true;
 760                 break;
 761         case 0x4E38:
 762         case 0x4E3C:
 763         case 0x4E40:
 764         case 0x4E44:
 765                 /* RB3D_COLORPITCH0 */
 766                 /* RB3D_COLORPITCH1 */
 767                 /* RB3D_COLORPITCH2 */
 768                 /* RB3D_COLORPITCH3 */
 769                 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
 770                         r = r100_cs_packet_next_reloc(p, &reloc);
 771                         if (r) {
 772                                 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
 773                                           idx, reg);
 774                                 r100_cs_dump_packet(p, pkt);
 775                                 return r;
 776                         }
 777
 778                         if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
 779                                 tile_flags |= R300_COLOR_TILE_ENABLE;
 780                         if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
 781                                 tile_flags |= R300_COLOR_MICROTILE_ENABLE;
 782                         else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO_SQUARE)
 783                                 tile_flags |= R300_COLOR_MICROTILE_SQUARE_ENABLE;
 784
 785                         tmp = idx_value & ~(0x7 << 16);
 786                         tmp |= tile_flags;
 787                         ib[idx] = tmp;
 788                 }
 789                 i = (reg - 0x4E38) >> 2;
 790                 track->cb[i].pitch = idx_value & 0x3FFE;
 791                 switch (((idx_value >> 21) & 0xF)) {
 792                 case 9:
 793                 case 11:
 794                 case 12:
 795                         track->cb[i].cpp = 1;
 796                         break;
 797                 case 3:
 798                 case 4:
 799                 case 13:
 800                 case 15:
 801                         track->cb[i].cpp = 2;
 802                         break;
 803                 case 5:
 804                         if (p->rdev->family < CHIP_RV515) {
 805                                 DRM_ERROR("Invalid color buffer format (%d)!\n",
 806                                           ((idx_value >> 21) & 0xF));
 807                                 return -EINVAL;
 808                         }
 809                         /* Pass through. */
 810                 case 6:
 811                         track->cb[i].cpp = 4;
 812                         break;
 813                 case 10:
 814                         track->cb[i].cpp = 8;
 815                         break;
 816                 case 7:
 817                         track->cb[i].cpp = 16;
 818                         break;
 819                 default:
 820                         DRM_ERROR("Invalid color buffer format (%d) !\n",
 821                                   ((idx_value >> 21) & 0xF));
 822                         return -EINVAL;
 823                 }
 824                 track->cb_dirty = true;
 825                 break;
 826         case 0x4F00:
 827                 /* ZB_CNTL */
 828                 if (idx_value & 2) {
 829                         track->z_enabled = true;
 830                 } else {
 831                         track->z_enabled = false;
 832                 }
 833                 track->zb_dirty = true;
 834                 break;
 835         case 0x4F10:
 836                 /* ZB_FORMAT */
 837                 switch ((idx_value & 0xF)) {
 838                 case 0:
 839                 case 1:
 840                         track->zb.cpp = 2;
 841                         break;
 842                 case 2:
 843                         track->zb.cpp = 4;
 844                         break;
 845                 default:
 846                         DRM_ERROR("Invalid z buffer format (%d) !\n",
 847                                   (idx_value & 0xF));
 848                         return -EINVAL;
 849                 }
 850                 track->zb_dirty = true;
 851                 break;
 852         case 0x4F24:
 853                 /* ZB_DEPTHPITCH */
 854                 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
 855                         r = r100_cs_packet_next_reloc(p, &reloc);
 856                         if (r) {
 857                                 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
 858                                           idx, reg);
 859                                 r100_cs_dump_packet(p, pkt);
 860                                 return r;
 861                         }
 862
 863                         if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
 864                                 tile_flags |= R300_DEPTHMACROTILE_ENABLE;
 865                         if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
 866                                 tile_flags |= R300_DEPTHMICROTILE_TILED;
 867                         else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO_SQUARE)
 868                                 tile_flags |= R300_DEPTHMICROTILE_TILED_SQUARE;
 869
 870                         tmp = idx_value & ~(0x7 << 16);
 871                         tmp |= tile_flags;
 872                         ib[idx] = tmp;
 873                 }
 874                 track->zb.pitch = idx_value & 0x3FFC;
 875                 track->zb_dirty = true;
 876                 break;
 877         case 0x4104:
 878                 /* TX_ENABLE */
 879                 for (i = 0; i < 16; i++) {
 880                         bool enabled;
 881
 882                         enabled = !!(idx_value & (1 << i));
 883                         track->textures[i].enabled = enabled;
 884                 }
 885                 track->tex_dirty = true;
 886                 break;
 887         case 0x44C0:
 888         case 0x44C4:
 889         case 0x44C8:
 890         case 0x44CC:
 891         case 0x44D0:
 892         case 0x44D4:
 893         case 0x44D8:
 894         case 0x44DC:
 895         case 0x44E0:
 896         case 0x44E4:
 897         case 0x44E8:
 898         case 0x44EC:
 899         case 0x44F0:
 900         case 0x44F4:
 901         case 0x44F8:
 902         case 0x44FC:
 903                 /* TX_FORMAT1_[0-15] */
 904                 i = (reg - 0x44C0) >> 2;
 905                 tmp = (idx_value >> 25) & 0x3;
 906                 track->textures[i].tex_coord_type = tmp;
 907                 switch ((idx_value & 0x1F)) {
 908                 case R300_TX_FORMAT_X8:
 909                 case R300_TX_FORMAT_Y4X4:
 910                 case R300_TX_FORMAT_Z3Y3X2:
 911                         track->textures[i].cpp = 1;
 912                         track->textures[i].compress_format = R100_TRACK_COMP_NONE;
 913                         break;
 914                 case R300_TX_FORMAT_X16:
 915                 case R300_TX_FORMAT_FL_I16:
 916                 case R300_TX_FORMAT_Y8X8:
 917                 case R300_TX_FORMAT_Z5Y6X5:
 918                 case R300_TX_FORMAT_Z6Y5X5:
 919                 case R300_TX_FORMAT_W4Z4Y4X4:
 920                 case R300_TX_FORMAT_W1Z5Y5X5:
 921                 case R300_TX_FORMAT_D3DMFT_CxV8U8:
 922                 case R300_TX_FORMAT_B8G8_B8G8:
 923                 case R300_TX_FORMAT_G8R8_G8B8:
 924                         track->textures[i].cpp = 2;
 925                         track->textures[i].compress_format = R100_TRACK_COMP_NONE;
 926                         break;
 927                 case R300_TX_FORMAT_Y16X16:
 928                 case R300_TX_FORMAT_FL_I16A16:
 929                 case R300_TX_FORMAT_Z11Y11X10:
 930                 case R300_TX_FORMAT_Z10Y11X11:
 931                 case R300_TX_FORMAT_W8Z8Y8X8:
 932                 case R300_TX_FORMAT_W2Z10Y10X10:
 933                 case 0x17:
 934                 case R300_TX_FORMAT_FL_I32:
 935                 case 0x1e:
 936                         track->textures[i].cpp = 4;
 937                         track->textures[i].compress_format = R100_TRACK_COMP_NONE;
 938                         break;
 939                 case R300_TX_FORMAT_W16Z16Y16X16:
 940                 case R300_TX_FORMAT_FL_R16G16B16A16:
 941                 case R300_TX_FORMAT_FL_I32A32:
 942                         track->textures[i].cpp = 8;
 943                         track->textures[i].compress_format = R100_TRACK_COMP_NONE;
 944                         break;
 945                 case R300_TX_FORMAT_FL_R32G32B32A32:
 946                         track->textures[i].cpp = 16;
 947                         track->textures[i].compress_format = R100_TRACK_COMP_NONE;
 948                         break;
 949                 case R300_TX_FORMAT_DXT1:
 950                         track->textures[i].cpp = 1;
 951                         track->textures[i].compress_format = R100_TRACK_COMP_DXT1;
 952                         break;
 953                 case R300_TX_FORMAT_ATI2N:
 954                         if (p->rdev->family < CHIP_R420) {
 955                                 DRM_ERROR("Invalid texture format %u\n",
 956                                           (idx_value & 0x1F));
 957                                 return -EINVAL;
 958                         }
 959                         /* The same rules apply as for DXT3/5. */
 960                         /* Pass through. */
 961                 case R300_TX_FORMAT_DXT3:
 962                 case R300_TX_FORMAT_DXT5:
 963                         track->textures[i].cpp = 1;
 964                         track->textures[i].compress_format = R100_TRACK_COMP_DXT35;
 965                         break;
 966                 default:
 967                         DRM_ERROR("Invalid texture format %u\n",
 968                                   (idx_value & 0x1F));
 969                         return -EINVAL;
 970                 }
 971                 track->tex_dirty = true;
 972                 break;
 973         case 0x4400:
 974         case 0x4404:
 975         case 0x4408:
 976         case 0x440C:
 977         case 0x4410:
 978         case 0x4414:
 979         case 0x4418:
 980         case 0x441C:
 981         case 0x4420:
 982         case 0x4424:
 983         case 0x4428:
 984         case 0x442C:
 985         case 0x4430:
 986         case 0x4434:
 987         case 0x4438:
 988         case 0x443C:
 989                 /* TX_FILTER0_[0-15] */
 990                 i = (reg - 0x4400) >> 2;
 991                 tmp = idx_value & 0x7;
 992                 if (tmp == 2 || tmp == 4 || tmp == 6) {
 993                         track->textures[i].roundup_w = false;
 994                 }
 995                 tmp = (idx_value >> 3) & 0x7;
 996                 if (tmp == 2 || tmp == 4 || tmp == 6) {
 997                         track->textures[i].roundup_h = false;
 998                 }
 999                 track->tex_dirty = true;
1000                 break;
1001         case 0x4500:
1002         case 0x4504:
1003         case 0x4508:
1004         case 0x450C:
1005         case 0x4510:
1006         case 0x4514:
1007         case 0x4518:
1008         case 0x451C:
1009         case 0x4520:
1010         case 0x4524:
1011         case 0x4528:
1012         case 0x452C:
1013         case 0x4530:
1014         case 0x4534:
1015         case 0x4538:
1016         case 0x453C:
1017                 /* TX_FORMAT2_[0-15] */
1018                 i = (reg - 0x4500) >> 2;
1019                 tmp = idx_value & 0x3FFF;
1020                 track->textures[i].pitch = tmp + 1;
1021                 if (p->rdev->family >= CHIP_RV515) {
1022                         tmp = ((idx_value >> 15) & 1) << 11;
1023                         track->textures[i].width_11 = tmp;
1024                         tmp = ((idx_value >> 16) & 1) << 11;
1025                         track->textures[i].height_11 = tmp;
1026
1027                         /* ATI1N */
1028                         if (idx_value & (1 << 14)) {
1029                                 /* The same rules apply as for DXT1. */
1030                                 track->textures[i].compress_format =
1031                                         R100_TRACK_COMP_DXT1;
1032                         }
1033                 } else if (idx_value & (1 << 14)) {
1034                         DRM_ERROR("Forbidden bit TXFORMAT_MSB\n");
1035                         return -EINVAL;
1036                 }
1037                 track->tex_dirty = true;
1038                 break;
1039         case 0x4480:
1040         case 0x4484:
1041         case 0x4488:
1042         case 0x448C:
1043         case 0x4490:
1044         case 0x4494:
1045         case 0x4498:
1046         case 0x449C:
1047         case 0x44A0:
1048         case 0x44A4:
1049         case 0x44A8:
1050         case 0x44AC:
1051         case 0x44B0:
1052         case 0x44B4:
1053         case 0x44B8:
1054         case 0x44BC:
1055                 /* TX_FORMAT0_[0-15] */
1056                 i = (reg - 0x4480) >> 2;
1057                 tmp = idx_value & 0x7FF;
1058                 track->textures[i].width = tmp + 1;
1059                 tmp = (idx_value >> 11) & 0x7FF;
1060                 track->textures[i].height = tmp + 1;
1061                 tmp = (idx_value >> 26) & 0xF;
1062                 track->textures[i].num_levels = tmp;
1063                 tmp = idx_value & (1 << 31);
1064                 track->textures[i].use_pitch = !!tmp;
1065                 tmp = (idx_value >> 22) & 0xF;
1066                 track->textures[i].txdepth = tmp;
1067                 track->tex_dirty = true;
1068                 break;
1069         case R300_ZB_ZPASS_ADDR:
1070                 r = r100_cs_packet_next_reloc(p, &reloc);
1071                 if (r) {
1072                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1073                                         idx, reg);
1074                         r100_cs_dump_packet(p, pkt);
1075                         return r;
1076                 }
1077                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1078                 break;
1079         case 0x4e0c:
1080                 /* RB3D_COLOR_CHANNEL_MASK */
1081                 track->color_channel_mask = idx_value;
1082                 track->cb_dirty = true;
1083                 break;
1084         case 0x43a4:
1085                 /* SC_HYPERZ_EN */
1086                 /* r300c emits this register - we need to disable hyperz for it
1087                  * without complaining */
1088                 if (p->rdev->hyperz_filp != p->filp) {
1089                         if (idx_value & 0x1)
1090                                 ib[idx] = idx_value & ~1;
1091                 }
1092                 break;
1093         case 0x4f1c:
1094                 /* ZB_BW_CNTL */
1095                 track->zb_cb_clear = !!(idx_value & (1 << 5));
1096                 track->cb_dirty = true;
1097                 track->zb_dirty = true;
1098                 if (p->rdev->hyperz_filp != p->filp) {
1099                         if (idx_value & (R300_HIZ_ENABLE |
1100                                          R300_RD_COMP_ENABLE |
1101                                          R300_WR_COMP_ENABLE |
1102                                          R300_FAST_FILL_ENABLE))
1103                                 goto fail;
1104                 }
1105                 break;
1106         case 0x4e04:
1107                 /* RB3D_BLENDCNTL */
1108                 track->blend_read_enable = !!(idx_value & (1 << 2));
1109                 track->cb_dirty = true;
1110                 break;
1111         case R300_RB3D_AARESOLVE_OFFSET:
1112                 r = r100_cs_packet_next_reloc(p, &reloc);
1113                 if (r) {
1114                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1115                                   idx, reg);
1116                         r100_cs_dump_packet(p, pkt);
1117                         return r;
1118                 }
1119                 track->aa.robj = reloc->robj;
1120                 track->aa.offset = idx_value;
1121                 track->aa_dirty = true;
1122                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1123                 break;
1124         case R300_RB3D_AARESOLVE_PITCH:
1125                 track->aa.pitch = idx_value & 0x3FFE;
1126                 track->aa_dirty = true;
1127                 break;
1128         case R300_RB3D_AARESOLVE_CTL:
1129                 track->aaresolve = idx_value & 0x1;
1130                 track->aa_dirty = true;
1131                 break;
1132         case 0x4f30: /* ZB_MASK_OFFSET */
1133         case 0x4f34: /* ZB_ZMASK_PITCH */
1134         case 0x4f44: /* ZB_HIZ_OFFSET */
1135         case 0x4f54: /* ZB_HIZ_PITCH */
1136                 if (idx_value && (p->rdev->hyperz_filp != p->filp))
1137                         goto fail;
1138                 break;
1139         case 0x4028:
1140                 if (idx_value && (p->rdev->hyperz_filp != p->filp))
1141                         goto fail;
1142                 /* GB_Z_PEQ_CONFIG */
1143                 if (p->rdev->family >= CHIP_RV350)
1144                         break;
1145                 goto fail;
1146                 break;
1147         case 0x4be8:
1148                 /* valid register only on RV530 */
1149                 if (p->rdev->family == CHIP_RV530)
1150                         break;
1151                 /* fallthrough do not move */
1152         default:
1153                 goto fail;
1154         }
1155         return 0;
1156 fail:
1157         printk(KERN_ERR "Forbidden register 0x%04X in cs at %d (val=%08x)\n",
1158                reg, idx, idx_value);
1159         return -EINVAL;
1160 }
1161
1162 static int r300_packet3_check(struct radeon_cs_parser *p,
1163                               struct radeon_cs_packet *pkt)
1164 {
1165         struct radeon_cs_reloc *reloc;
1166         struct r100_cs_track *track;
1167         volatile uint32_t *ib;
1168         unsigned idx;
1169         int r;
1170
1171         ib = p->ib->ptr;
1172         idx = pkt->idx + 1;
1173         track = (struct r100_cs_track *)p->track;
1174         switch(pkt->opcode) {
1175         case PACKET3_3D_LOAD_VBPNTR:
1176                 r = r100_packet3_load_vbpntr(p, pkt, idx);
1177                 if (r)
1178                         return r;
1179                 break;
1180         case PACKET3_INDX_BUFFER:
1181                 r = r100_cs_packet_next_reloc(p, &reloc);
1182                 if (r) {
1183                         DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1184                         r100_cs_dump_packet(p, pkt);
1185                         return r;
1186                 }
1187                 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset);
1188                 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
1189                 if (r) {
1190                         return r;
1191                 }
1192                 break;
1193         /* Draw packet */
1194         case PACKET3_3D_DRAW_IMMD:
1195                 /* Number of dwords is vtx_size * (num_vertices - 1)
1196                  * PRIM_WALK must be equal to 3 vertex data in embedded
1197                  * in cmd stream */
1198                 if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) {
1199                         DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1200                         return -EINVAL;
1201                 }
1202                 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1203                 track->immd_dwords = pkt->count - 1;
1204                 r = r100_cs_track_check(p->rdev, track);
1205                 if (r) {
1206                         return r;
1207                 }
1208                 break;
1209         case PACKET3_3D_DRAW_IMMD_2:
1210                 /* Number of dwords is vtx_size * (num_vertices - 1)
1211                  * PRIM_WALK must be equal to 3 vertex data in embedded
1212                  * in cmd stream */
1213                 if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) {
1214                         DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1215                         return -EINVAL;
1216                 }
1217                 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1218                 track->immd_dwords = pkt->count;
1219                 r = r100_cs_track_check(p->rdev, track);
1220                 if (r) {
1221                         return r;
1222                 }
1223                 break;
1224         case PACKET3_3D_DRAW_VBUF:
1225                 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1226                 r = r100_cs_track_check(p->rdev, track);
1227                 if (r) {
1228                         return r;
1229                 }
1230                 break;
1231         case PACKET3_3D_DRAW_VBUF_2:
1232                 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1233                 r = r100_cs_track_check(p->rdev, track);
1234                 if (r) {
1235                         return r;
1236                 }
1237                 break;
1238         case PACKET3_3D_DRAW_INDX:
1239                 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1240                 r = r100_cs_track_check(p->rdev, track);
1241                 if (r) {
1242                         return r;
1243                 }
1244                 break;
1245         case PACKET3_3D_DRAW_INDX_2:
1246                 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1247                 r = r100_cs_track_check(p->rdev, track);
1248                 if (r) {
1249                         return r;
1250                 }
1251                 break;
1252         case PACKET3_3D_CLEAR_HIZ:
1253         case PACKET3_3D_CLEAR_ZMASK:
1254                 if (p->rdev->hyperz_filp != p->filp)
1255                         return -EINVAL;
1256                 break;
1257         case PACKET3_3D_CLEAR_CMASK:
1258                 if (p->rdev->cmask_filp != p->filp)
1259                         return -EINVAL;
1260                 break;
1261         case PACKET3_NOP:
1262                 break;
1263         default:
1264                 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
1265                 return -EINVAL;
1266         }
1267         return 0;
1268 }
1269
1270 int r300_cs_parse(struct radeon_cs_parser *p)
1271 {
1272         struct radeon_cs_packet pkt;
1273         struct r100_cs_track *track;
1274         int r;
1275
1276         track = kzalloc(sizeof(*track), GFP_KERNEL);
1277         if (track == NULL)
1278                 return -ENOMEM;
1279         r100_cs_track_clear(p->rdev, track);
1280         p->track = track;
1281         do {
1282                 r = r100_cs_packet_parse(p, &pkt, p->idx);
1283                 if (r) {
1284                         return r;
1285                 }
1286                 p->idx += pkt.count + 2;
1287                 switch (pkt.type) {
1288                 case PACKET_TYPE0:
1289                         r = r100_cs_parse_packet0(p, &pkt,
1290                                                   p->rdev->config.r300.reg_safe_bm,
1291                                                   p->rdev->config.r300.reg_safe_bm_size,
1292                                                   &r300_packet0_check);
1293                         break;
1294                 case PACKET_TYPE2:
1295                         break;
1296                 case PACKET_TYPE3:
1297                         r = r300_packet3_check(p, &pkt);
1298                         break;
1299                 default:
1300                         DRM_ERROR("Unknown packet type %d !\n", pkt.type);
1301                         return -EINVAL;
1302                 }
1303                 if (r) {
1304                         return r;
1305                 }
1306         } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
1307         return 0;
1308 }
1309
1310 void r300_set_reg_safe(struct radeon_device *rdev)
1311 {
1312         rdev->config.r300.reg_safe_bm = r300_reg_safe_bm;
1313         rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r300_reg_safe_bm);
1314 }
1315
1316 void r300_mc_program(struct radeon_device *rdev)
1317 {
1318         struct r100_mc_save save;
1319         int r;
1320
1321         r = r100_debugfs_mc_info_init(rdev);
1322         if (r) {
1323                 dev_err(rdev->dev, "Failed to create r100_mc debugfs file.\n");
1324         }
1325
1326         /* Stops all mc clients */
1327         r100_mc_stop(rdev, &save);
1328         if (rdev->flags & RADEON_IS_AGP) {
1329                 WREG32(R_00014C_MC_AGP_LOCATION,
1330                         S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) |
1331                         S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
1332                 WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
1333                 WREG32(R_00015C_AGP_BASE_2,
1334                         upper_32_bits(rdev->mc.agp_base) & 0xff);
1335         } else {
1336                 WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF);
1337                 WREG32(R_000170_AGP_BASE, 0);
1338                 WREG32(R_00015C_AGP_BASE_2, 0);
1339         }
1340         /* Wait for mc idle */
1341         if (r300_mc_wait_for_idle(rdev))
1342                 DRM_INFO("Failed to wait MC idle before programming MC.\n");
1343         /* Program MC, should be a 32bits limited address space */
1344         WREG32(R_000148_MC_FB_LOCATION,
1345                 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
1346                 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
1347         r100_mc_resume(rdev, &save);
1348 }
1349
1350 void r300_clock_startup(struct radeon_device *rdev)
1351 {
1352         u32 tmp;
1353
1354         if (radeon_dynclks != -1 && radeon_dynclks)
1355                 radeon_legacy_set_clock_gating(rdev, 1);
1356         /* We need to force on some of the block */
1357         tmp = RREG32_PLL(R_00000D_SCLK_CNTL);
1358         tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
1359         if ((rdev->family == CHIP_RV350) || (rdev->family == CHIP_RV380))
1360                 tmp |= S_00000D_FORCE_VAP(1);
1361         WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
1362 }
1363
1364 static int r300_startup(struct radeon_device *rdev)
1365 {
1366         int r;
1367
1368         /* set common regs */
1369         r100_set_common_regs(rdev);
1370         /* program mc */
1371         r300_mc_program(rdev);
1372         /* Resume clock */
1373         r300_clock_startup(rdev);
1374         /* Initialize GPU configuration (# pipes, ...) */
1375         r300_gpu_init(rdev);
1376         /* Initialize GART (initialize after TTM so we can allocate
1377          * memory through TTM but finalize after TTM) */
1378         if (rdev->flags & RADEON_IS_PCIE) {
1379                 r = rv370_pcie_gart_enable(rdev);
1380                 if (r)
1381                         return r;
1382         }
1383
1384         if (rdev->family == CHIP_R300 ||
1385             rdev->family == CHIP_R350 ||
1386             rdev->family == CHIP_RV350)
1387                 r100_enable_bm(rdev);
1388
1389         if (rdev->flags & RADEON_IS_PCI) {
1390                 r = r100_pci_gart_enable(rdev);
1391                 if (r)
1392                         return r;
1393         }
1394
1395         /* allocate wb buffer */
1396         r = radeon_wb_init(rdev);
1397         if (r)
1398                 return r;
1399
1400         r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
1401         if (r) {
1402                 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
1403                 return r;
1404         }
1405
1406         /* Enable IRQ */
1407         r100_irq_set(rdev);
1408         rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
1409         /* 1M ring buffer */
1410         r = r100_cp_init(rdev, 1024 * 1024);
1411         if (r) {
1412                 dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
1413                 return r;
1414         }
1415
1416         r = radeon_ib_pool_start(rdev);
1417         if (r)
1418                 return r;
1419
1420         r = radeon_ib_ring_tests(rdev);
1421         if (r)
1422                 return r;
1423
1424         return 0;
1425 }
1426
1427 int r300_resume(struct radeon_device *rdev)
1428 {
1429         int r;
1430
1431         /* Make sur GART are not working */
1432         if (rdev->flags & RADEON_IS_PCIE)
1433                 rv370_pcie_gart_disable(rdev);
1434         if (rdev->flags & RADEON_IS_PCI)
1435                 r100_pci_gart_disable(rdev);
1436         /* Resume clock before doing reset */
1437         r300_clock_startup(rdev);
1438         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
1439         if (radeon_asic_reset(rdev)) {
1440                 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
1441                         RREG32(R_000E40_RBBM_STATUS),
1442                         RREG32(R_0007C0_CP_STAT));
1443         }
1444         /* post */
1445         radeon_combios_asic_init(rdev->ddev);
1446         /* Resume clock after posting */
1447         r300_clock_startup(rdev);
1448         /* Initialize surface registers */
1449         radeon_surface_init(rdev);
1450
1451         rdev->accel_working = true;
1452         r = r300_startup(rdev);
1453         if (r) {
1454                 rdev->accel_working = false;
1455         }
1456         return r;
1457 }
1458
1459 int r300_suspend(struct radeon_device *rdev)
1460 {
1461         radeon_ib_pool_suspend(rdev);
1462         r100_cp_disable(rdev);
1463         radeon_wb_disable(rdev);
1464         r100_irq_disable(rdev);
1465         if (rdev->flags & RADEON_IS_PCIE)
1466                 rv370_pcie_gart_disable(rdev);
1467         if (rdev->flags & RADEON_IS_PCI)
1468                 r100_pci_gart_disable(rdev);
1469         return 0;
1470 }
1471
1472 void r300_fini(struct radeon_device *rdev)
1473 {
1474         r100_cp_fini(rdev);
1475         radeon_wb_fini(rdev);
1476         r100_ib_fini(rdev);
1477         radeon_gem_fini(rdev);
1478         if (rdev->flags & RADEON_IS_PCIE)
1479                 rv370_pcie_gart_fini(rdev);
1480         if (rdev->flags & RADEON_IS_PCI)
1481                 r100_pci_gart_fini(rdev);
1482         radeon_agp_fini(rdev);
1483         radeon_irq_kms_fini(rdev);
1484         radeon_fence_driver_fini(rdev);
1485         radeon_bo_fini(rdev);
1486         radeon_atombios_fini(rdev);
1487         kfree(rdev->bios);
1488         rdev->bios = NULL;
1489 }
1490
1491 int r300_init(struct radeon_device *rdev)
1492 {
1493         int r;
1494
1495         /* Disable VGA */
1496         r100_vga_render_disable(rdev);
1497         /* Initialize scratch registers */
1498         radeon_scratch_init(rdev);
1499         /* Initialize surface registers */
1500         radeon_surface_init(rdev);
1501         /* TODO: disable VGA need to use VGA request */
1502         /* restore some register to sane defaults */
1503         r100_restore_sanity(rdev);
1504         /* BIOS*/
1505         if (!radeon_get_bios(rdev)) {
1506                 if (ASIC_IS_AVIVO(rdev))
1507                         return -EINVAL;
1508         }
1509         if (rdev->is_atom_bios) {
1510                 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
1511                 return -EINVAL;
1512         } else {
1513                 r = radeon_combios_init(rdev);
1514                 if (r)
1515                         return r;
1516         }
1517         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
1518         if (radeon_asic_reset(rdev)) {
1519                 dev_warn(rdev->dev,
1520                         "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
1521                         RREG32(R_000E40_RBBM_STATUS),
1522                         RREG32(R_0007C0_CP_STAT));
1523         }
1524         /* check if cards are posted or not */
1525         if (radeon_boot_test_post_card(rdev) == false)
1526                 return -EINVAL;
1527         /* Set asic errata */
1528         r300_errata(rdev);
1529         /* Initialize clocks */
1530         radeon_get_clock_info(rdev->ddev);
1531         /* initialize AGP */
1532         if (rdev->flags & RADEON_IS_AGP) {
1533                 r = radeon_agp_init(rdev);
1534                 if (r) {
1535                         radeon_agp_disable(rdev);
1536                 }
1537         }
1538         /* initialize memory controller */
1539         r300_mc_init(rdev);
1540         /* Fence driver */
1541         r = radeon_fence_driver_init(rdev);
1542         if (r)
1543                 return r;
1544         r = radeon_irq_kms_init(rdev);
1545         if (r)
1546                 return r;
1547         /* Memory manager */
1548         r = radeon_bo_init(rdev);
1549         if (r)
1550                 return r;
1551         if (rdev->flags & RADEON_IS_PCIE) {
1552                 r = rv370_pcie_gart_init(rdev);
1553                 if (r)
1554                         return r;
1555         }
1556         if (rdev->flags & RADEON_IS_PCI) {
1557                 r = r100_pci_gart_init(rdev);
1558                 if (r)
1559                         return r;
1560         }
1561         r300_set_reg_safe(rdev);
1562
1563         r = radeon_ib_pool_init(rdev);
1564         rdev->accel_working = true;
1565         if (r) {
1566                 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
1567                 rdev->accel_working = false;
1568         }
1569
1570         r = r300_startup(rdev);
1571         if (r) {
1572                 /* Somethings want wront with the accel init stop accel */
1573                 dev_err(rdev->dev, "Disabling GPU acceleration\n");
1574                 r100_cp_fini(rdev);
1575                 radeon_wb_fini(rdev);
1576                 r100_ib_fini(rdev);
1577                 radeon_irq_kms_fini(rdev);
1578                 if (rdev->flags & RADEON_IS_PCIE)
1579                         rv370_pcie_gart_fini(rdev);
1580                 if (rdev->flags & RADEON_IS_PCI)
1581                         r100_pci_gart_fini(rdev);
1582                 radeon_agp_fini(rdev);
1583                 rdev->accel_working = false;
1584         }
1585         return 0;
1586 }