2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/seq_file.h>
31 #include "radeon_drm.h"
32 #include "radeon_reg.h"
36 #include <linux/firmware.h>
37 #include <linux/platform_device.h>
39 #include "r100_reg_safe.h"
40 #include "rn50_reg_safe.h"
43 #define FIRMWARE_R100 "radeon/R100_cp.bin"
44 #define FIRMWARE_R200 "radeon/R200_cp.bin"
45 #define FIRMWARE_R300 "radeon/R300_cp.bin"
46 #define FIRMWARE_R420 "radeon/R420_cp.bin"
47 #define FIRMWARE_RS690 "radeon/RS690_cp.bin"
48 #define FIRMWARE_RS600 "radeon/RS600_cp.bin"
49 #define FIRMWARE_R520 "radeon/R520_cp.bin"
51 MODULE_FIRMWARE(FIRMWARE_R100);
52 MODULE_FIRMWARE(FIRMWARE_R200);
53 MODULE_FIRMWARE(FIRMWARE_R300);
54 MODULE_FIRMWARE(FIRMWARE_R420);
55 MODULE_FIRMWARE(FIRMWARE_RS690);
56 MODULE_FIRMWARE(FIRMWARE_RS600);
57 MODULE_FIRMWARE(FIRMWARE_R520);
59 #include "r100_track.h"
61 /* This files gather functions specifics to:
62 * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
64 * Some of these functions might be used by newer ASICs.
66 int r200_init(struct radeon_device *rdev);
67 void r100_hdp_reset(struct radeon_device *rdev);
68 void r100_gpu_init(struct radeon_device *rdev);
69 int r100_gui_wait_for_idle(struct radeon_device *rdev);
70 int r100_mc_wait_for_idle(struct radeon_device *rdev);
71 void r100_gpu_wait_for_vsync(struct radeon_device *rdev);
72 void r100_gpu_wait_for_vsync2(struct radeon_device *rdev);
73 int r100_debugfs_mc_info_init(struct radeon_device *rdev);
79 void r100_pci_gart_tlb_flush(struct radeon_device *rdev)
81 /* TODO: can we do somethings here ? */
82 /* It seems hw only cache one entry so we should discard this
83 * entry otherwise if first GPU GART read hit this entry it
84 * could end up in wrong address. */
87 int r100_pci_gart_init(struct radeon_device *rdev)
91 if (rdev->gart.table.ram.ptr) {
92 WARN(1, "R100 PCI GART already initialized.\n");
95 /* Initialize common gart structure */
96 r = radeon_gart_init(rdev);
99 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
100 rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush;
101 rdev->asic->gart_set_page = &r100_pci_gart_set_page;
102 return radeon_gart_table_ram_alloc(rdev);
105 int r100_pci_gart_enable(struct radeon_device *rdev)
109 /* discard memory request outside of configured range */
110 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
111 WREG32(RADEON_AIC_CNTL, tmp);
112 /* set address range for PCI address translate */
113 WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_location);
114 tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;
115 WREG32(RADEON_AIC_HI_ADDR, tmp);
116 /* Enable bus mastering */
117 tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
118 WREG32(RADEON_BUS_CNTL, tmp);
119 /* set PCI GART page-table base address */
120 WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr);
121 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN;
122 WREG32(RADEON_AIC_CNTL, tmp);
123 r100_pci_gart_tlb_flush(rdev);
124 rdev->gart.ready = true;
128 void r100_pci_gart_disable(struct radeon_device *rdev)
132 /* discard memory request outside of configured range */
133 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
134 WREG32(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN);
135 WREG32(RADEON_AIC_LO_ADDR, 0);
136 WREG32(RADEON_AIC_HI_ADDR, 0);
139 int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
141 if (i < 0 || i > rdev->gart.num_gpu_pages) {
144 rdev->gart.table.ram.ptr[i] = cpu_to_le32(lower_32_bits(addr));
148 void r100_pci_gart_fini(struct radeon_device *rdev)
150 r100_pci_gart_disable(rdev);
151 radeon_gart_table_ram_free(rdev);
152 radeon_gart_fini(rdev);
159 void r100_mc_disable_clients(struct radeon_device *rdev)
161 uint32_t ov0_scale_cntl, crtc_ext_cntl, crtc_gen_cntl, crtc2_gen_cntl;
163 /* FIXME: is this function correct for rs100,rs200,rs300 ? */
164 if (r100_gui_wait_for_idle(rdev)) {
165 printk(KERN_WARNING "Failed to wait GUI idle while "
166 "programming pipes. Bad things might happen.\n");
169 /* stop display and memory access */
170 ov0_scale_cntl = RREG32(RADEON_OV0_SCALE_CNTL);
171 WREG32(RADEON_OV0_SCALE_CNTL, ov0_scale_cntl & ~RADEON_SCALER_ENABLE);
172 crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
173 WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl | RADEON_CRTC_DISPLAY_DIS);
174 crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
176 r100_gpu_wait_for_vsync(rdev);
178 WREG32(RADEON_CRTC_GEN_CNTL,
179 (crtc_gen_cntl & ~(RADEON_CRTC_CUR_EN | RADEON_CRTC_ICON_EN)) |
180 RADEON_CRTC_DISP_REQ_EN_B | RADEON_CRTC_EXT_DISP_EN);
182 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
183 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
185 r100_gpu_wait_for_vsync2(rdev);
186 WREG32(RADEON_CRTC2_GEN_CNTL,
188 ~(RADEON_CRTC2_CUR_EN | RADEON_CRTC2_ICON_EN)) |
189 RADEON_CRTC2_DISP_REQ_EN_B);
195 void r100_mc_setup(struct radeon_device *rdev)
200 r = r100_debugfs_mc_info_init(rdev);
202 DRM_ERROR("Failed to register debugfs file for R100 MC !\n");
204 /* Write VRAM size in case we are limiting it */
205 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
206 /* Novell bug 204882 for RN50/M6/M7 with 8/16/32MB VRAM,
207 * if the aperture is 64MB but we have 32MB VRAM
208 * we report only 32MB VRAM but we have to set MC_FB_LOCATION
209 * to 64MB, otherwise the gpu accidentially dies */
210 tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1;
211 tmp = REG_SET(RADEON_MC_FB_TOP, tmp >> 16);
212 tmp |= REG_SET(RADEON_MC_FB_START, rdev->mc.vram_location >> 16);
213 WREG32(RADEON_MC_FB_LOCATION, tmp);
215 /* Enable bus mastering */
216 tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
217 WREG32(RADEON_BUS_CNTL, tmp);
219 if (rdev->flags & RADEON_IS_AGP) {
220 tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;
221 tmp = REG_SET(RADEON_MC_AGP_TOP, tmp >> 16);
222 tmp |= REG_SET(RADEON_MC_AGP_START, rdev->mc.gtt_location >> 16);
223 WREG32(RADEON_MC_AGP_LOCATION, tmp);
224 WREG32(RADEON_AGP_BASE, rdev->mc.agp_base);
226 WREG32(RADEON_MC_AGP_LOCATION, 0x0FFFFFFF);
227 WREG32(RADEON_AGP_BASE, 0);
230 tmp = RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL;
232 WREG32(RADEON_HOST_PATH_CNTL, tmp | RADEON_HDP_SOFT_RESET | RADEON_HDP_READ_BUFFER_INVALIDATE);
233 (void)RREG32(RADEON_HOST_PATH_CNTL);
234 WREG32(RADEON_HOST_PATH_CNTL, tmp);
235 (void)RREG32(RADEON_HOST_PATH_CNTL);
238 int r100_mc_init(struct radeon_device *rdev)
242 if (r100_debugfs_rbbm_init(rdev)) {
243 DRM_ERROR("Failed to register debugfs file for RBBM !\n");
247 /* Disable gart which also disable out of gart access */
248 r100_pci_gart_disable(rdev);
250 /* Setup GPU memory space */
251 rdev->mc.gtt_location = 0xFFFFFFFFUL;
252 if (rdev->flags & RADEON_IS_AGP) {
253 r = radeon_agp_init(rdev);
255 printk(KERN_WARNING "[drm] Disabling AGP\n");
256 rdev->flags &= ~RADEON_IS_AGP;
257 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
259 rdev->mc.gtt_location = rdev->mc.agp_base;
262 r = radeon_mc_setup(rdev);
267 r100_mc_disable_clients(rdev);
268 if (r100_mc_wait_for_idle(rdev)) {
269 printk(KERN_WARNING "Failed to wait MC idle while "
270 "programming pipes. Bad things might happen.\n");
277 void r100_mc_fini(struct radeon_device *rdev)
285 int r100_irq_set(struct radeon_device *rdev)
289 if (rdev->irq.sw_int) {
290 tmp |= RADEON_SW_INT_ENABLE;
292 if (rdev->irq.crtc_vblank_int[0]) {
293 tmp |= RADEON_CRTC_VBLANK_MASK;
295 if (rdev->irq.crtc_vblank_int[1]) {
296 tmp |= RADEON_CRTC2_VBLANK_MASK;
298 WREG32(RADEON_GEN_INT_CNTL, tmp);
302 void r100_irq_disable(struct radeon_device *rdev)
306 WREG32(R_000040_GEN_INT_CNTL, 0);
307 /* Wait and acknowledge irq */
309 tmp = RREG32(R_000044_GEN_INT_STATUS);
310 WREG32(R_000044_GEN_INT_STATUS, tmp);
313 static inline uint32_t r100_irq_ack(struct radeon_device *rdev)
315 uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS);
316 uint32_t irq_mask = RADEON_SW_INT_TEST | RADEON_CRTC_VBLANK_STAT |
317 RADEON_CRTC2_VBLANK_STAT;
320 WREG32(RADEON_GEN_INT_STATUS, irqs);
322 return irqs & irq_mask;
325 int r100_irq_process(struct radeon_device *rdev)
329 status = r100_irq_ack(rdev);
333 if (rdev->shutdown) {
338 if (status & RADEON_SW_INT_TEST) {
339 radeon_fence_process(rdev);
341 /* Vertical blank interrupts */
342 if (status & RADEON_CRTC_VBLANK_STAT) {
343 drm_handle_vblank(rdev->ddev, 0);
345 if (status & RADEON_CRTC2_VBLANK_STAT) {
346 drm_handle_vblank(rdev->ddev, 1);
348 status = r100_irq_ack(rdev);
353 u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc)
356 return RREG32(RADEON_CRTC_CRNT_FRAME);
358 return RREG32(RADEON_CRTC2_CRNT_FRAME);
365 void r100_fence_ring_emit(struct radeon_device *rdev,
366 struct radeon_fence *fence)
368 /* Who ever call radeon_fence_emit should call ring_lock and ask
369 * for enough space (today caller are ib schedule and buffer move) */
370 /* Wait until IDLE & CLEAN */
371 radeon_ring_write(rdev, PACKET0(0x1720, 0));
372 radeon_ring_write(rdev, (1 << 16) | (1 << 17));
373 /* Emit fence sequence & fire IRQ */
374 radeon_ring_write(rdev, PACKET0(rdev->fence_drv.scratch_reg, 0));
375 radeon_ring_write(rdev, fence->seq);
376 radeon_ring_write(rdev, PACKET0(RADEON_GEN_INT_STATUS, 0));
377 radeon_ring_write(rdev, RADEON_SW_INT_FIRE);
384 int r100_wb_init(struct radeon_device *rdev)
388 if (rdev->wb.wb_obj == NULL) {
389 r = radeon_object_create(rdev, NULL, 4096,
391 RADEON_GEM_DOMAIN_GTT,
392 false, &rdev->wb.wb_obj);
394 DRM_ERROR("radeon: failed to create WB buffer (%d).\n", r);
397 r = radeon_object_pin(rdev->wb.wb_obj,
398 RADEON_GEM_DOMAIN_GTT,
401 DRM_ERROR("radeon: failed to pin WB buffer (%d).\n", r);
404 r = radeon_object_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb);
406 DRM_ERROR("radeon: failed to map WB buffer (%d).\n", r);
410 WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr);
411 WREG32(R_00070C_CP_RB_RPTR_ADDR,
412 S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + 1024) >> 2));
413 WREG32(R_000770_SCRATCH_UMSK, 0xff);
417 void r100_wb_disable(struct radeon_device *rdev)
419 WREG32(R_000770_SCRATCH_UMSK, 0);
422 void r100_wb_fini(struct radeon_device *rdev)
424 r100_wb_disable(rdev);
425 if (rdev->wb.wb_obj) {
426 radeon_object_kunmap(rdev->wb.wb_obj);
427 radeon_object_unpin(rdev->wb.wb_obj);
428 radeon_object_unref(&rdev->wb.wb_obj);
430 rdev->wb.wb_obj = NULL;
434 int r100_copy_blit(struct radeon_device *rdev,
438 struct radeon_fence *fence)
441 uint32_t stride_bytes = PAGE_SIZE;
443 uint32_t stride_pixels;
448 /* radeon limited to 16k stride */
449 stride_bytes &= 0x3fff;
450 /* radeon pitch is /64 */
451 pitch = stride_bytes / 64;
452 stride_pixels = stride_bytes / 4;
453 num_loops = DIV_ROUND_UP(num_pages, 8191);
455 /* Ask for enough room for blit + flush + fence */
456 ndw = 64 + (10 * num_loops);
457 r = radeon_ring_lock(rdev, ndw);
459 DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw);
462 while (num_pages > 0) {
463 cur_pages = num_pages;
464 if (cur_pages > 8191) {
467 num_pages -= cur_pages;
469 /* pages are in Y direction - height
470 page width in X direction - width */
471 radeon_ring_write(rdev, PACKET3(PACKET3_BITBLT_MULTI, 8));
472 radeon_ring_write(rdev,
473 RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
474 RADEON_GMC_DST_PITCH_OFFSET_CNTL |
475 RADEON_GMC_SRC_CLIPPING |
476 RADEON_GMC_DST_CLIPPING |
477 RADEON_GMC_BRUSH_NONE |
478 (RADEON_COLOR_FORMAT_ARGB8888 << 8) |
479 RADEON_GMC_SRC_DATATYPE_COLOR |
481 RADEON_DP_SRC_SOURCE_MEMORY |
482 RADEON_GMC_CLR_CMP_CNTL_DIS |
483 RADEON_GMC_WR_MSK_DIS);
484 radeon_ring_write(rdev, (pitch << 22) | (src_offset >> 10));
485 radeon_ring_write(rdev, (pitch << 22) | (dst_offset >> 10));
486 radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16));
487 radeon_ring_write(rdev, 0);
488 radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16));
489 radeon_ring_write(rdev, num_pages);
490 radeon_ring_write(rdev, num_pages);
491 radeon_ring_write(rdev, cur_pages | (stride_pixels << 16));
493 radeon_ring_write(rdev, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0));
494 radeon_ring_write(rdev, RADEON_RB2D_DC_FLUSH_ALL);
495 radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
496 radeon_ring_write(rdev,
497 RADEON_WAIT_2D_IDLECLEAN |
498 RADEON_WAIT_HOST_IDLECLEAN |
499 RADEON_WAIT_DMA_GUI_IDLE);
501 r = radeon_fence_emit(rdev, fence);
503 radeon_ring_unlock_commit(rdev);
511 static int r100_cp_wait_for_idle(struct radeon_device *rdev)
516 for (i = 0; i < rdev->usec_timeout; i++) {
517 tmp = RREG32(R_000E40_RBBM_STATUS);
518 if (!G_000E40_CP_CMDSTRM_BUSY(tmp)) {
526 void r100_ring_start(struct radeon_device *rdev)
530 r = radeon_ring_lock(rdev, 2);
534 radeon_ring_write(rdev, PACKET0(RADEON_ISYNC_CNTL, 0));
535 radeon_ring_write(rdev,
536 RADEON_ISYNC_ANY2D_IDLE3D |
537 RADEON_ISYNC_ANY3D_IDLE2D |
538 RADEON_ISYNC_WAIT_IDLEGUI |
539 RADEON_ISYNC_CPSCRATCH_IDLEGUI);
540 radeon_ring_unlock_commit(rdev);
544 /* Load the microcode for the CP */
545 static int r100_cp_init_microcode(struct radeon_device *rdev)
547 struct platform_device *pdev;
548 const char *fw_name = NULL;
553 pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
556 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
559 if ((rdev->family == CHIP_R100) || (rdev->family == CHIP_RV100) ||
560 (rdev->family == CHIP_RV200) || (rdev->family == CHIP_RS100) ||
561 (rdev->family == CHIP_RS200)) {
562 DRM_INFO("Loading R100 Microcode\n");
563 fw_name = FIRMWARE_R100;
564 } else if ((rdev->family == CHIP_R200) ||
565 (rdev->family == CHIP_RV250) ||
566 (rdev->family == CHIP_RV280) ||
567 (rdev->family == CHIP_RS300)) {
568 DRM_INFO("Loading R200 Microcode\n");
569 fw_name = FIRMWARE_R200;
570 } else if ((rdev->family == CHIP_R300) ||
571 (rdev->family == CHIP_R350) ||
572 (rdev->family == CHIP_RV350) ||
573 (rdev->family == CHIP_RV380) ||
574 (rdev->family == CHIP_RS400) ||
575 (rdev->family == CHIP_RS480)) {
576 DRM_INFO("Loading R300 Microcode\n");
577 fw_name = FIRMWARE_R300;
578 } else if ((rdev->family == CHIP_R420) ||
579 (rdev->family == CHIP_R423) ||
580 (rdev->family == CHIP_RV410)) {
581 DRM_INFO("Loading R400 Microcode\n");
582 fw_name = FIRMWARE_R420;
583 } else if ((rdev->family == CHIP_RS690) ||
584 (rdev->family == CHIP_RS740)) {
585 DRM_INFO("Loading RS690/RS740 Microcode\n");
586 fw_name = FIRMWARE_RS690;
587 } else if (rdev->family == CHIP_RS600) {
588 DRM_INFO("Loading RS600 Microcode\n");
589 fw_name = FIRMWARE_RS600;
590 } else if ((rdev->family == CHIP_RV515) ||
591 (rdev->family == CHIP_R520) ||
592 (rdev->family == CHIP_RV530) ||
593 (rdev->family == CHIP_R580) ||
594 (rdev->family == CHIP_RV560) ||
595 (rdev->family == CHIP_RV570)) {
596 DRM_INFO("Loading R500 Microcode\n");
597 fw_name = FIRMWARE_R520;
600 err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
601 platform_device_unregister(pdev);
603 printk(KERN_ERR "radeon_cp: Failed to load firmware \"%s\"\n",
605 } else if (rdev->me_fw->size % 8) {
607 "radeon_cp: Bogus length %zu in firmware \"%s\"\n",
608 rdev->me_fw->size, fw_name);
610 release_firmware(rdev->me_fw);
615 static void r100_cp_load_microcode(struct radeon_device *rdev)
617 const __be32 *fw_data;
620 if (r100_gui_wait_for_idle(rdev)) {
621 printk(KERN_WARNING "Failed to wait GUI idle while "
622 "programming pipes. Bad things might happen.\n");
626 size = rdev->me_fw->size / 4;
627 fw_data = (const __be32 *)&rdev->me_fw->data[0];
628 WREG32(RADEON_CP_ME_RAM_ADDR, 0);
629 for (i = 0; i < size; i += 2) {
630 WREG32(RADEON_CP_ME_RAM_DATAH,
631 be32_to_cpup(&fw_data[i]));
632 WREG32(RADEON_CP_ME_RAM_DATAL,
633 be32_to_cpup(&fw_data[i + 1]));
638 int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
643 unsigned pre_write_timer;
644 unsigned pre_write_limit;
645 unsigned indirect2_start;
646 unsigned indirect1_start;
650 if (r100_debugfs_cp_init(rdev)) {
651 DRM_ERROR("Failed to register debugfs file for CP !\n");
654 tmp = RREG32(RADEON_CP_CSQ_STAT);
655 if ((tmp & (1 << 31))) {
656 DRM_INFO("radeon: cp busy (0x%08X) resetting\n", tmp);
657 WREG32(RADEON_CP_CSQ_MODE, 0);
658 WREG32(RADEON_CP_CSQ_CNTL, 0);
659 WREG32(RADEON_RBBM_SOFT_RESET, RADEON_SOFT_RESET_CP);
660 tmp = RREG32(RADEON_RBBM_SOFT_RESET);
662 WREG32(RADEON_RBBM_SOFT_RESET, 0);
663 tmp = RREG32(RADEON_RBBM_SOFT_RESET);
665 tmp = RREG32(RADEON_CP_CSQ_STAT);
666 if ((tmp & (1 << 31))) {
667 DRM_INFO("radeon: cp reset failed (0x%08X)\n", tmp);
670 DRM_INFO("radeon: cp idle (0x%08X)\n", tmp);
674 r = r100_cp_init_microcode(rdev);
676 DRM_ERROR("Failed to load firmware!\n");
681 /* Align ring size */
682 rb_bufsz = drm_order(ring_size / 8);
683 ring_size = (1 << (rb_bufsz + 1)) * 4;
684 r100_cp_load_microcode(rdev);
685 r = radeon_ring_init(rdev, ring_size);
689 /* Each time the cp read 1024 bytes (16 dword/quadword) update
690 * the rptr copy in system ram */
692 /* cp will read 128bytes at a time (4 dwords) */
694 rdev->cp.align_mask = 16 - 1;
695 /* Write to CP_RB_WPTR will be delayed for pre_write_timer clocks */
696 pre_write_timer = 64;
697 /* Force CP_RB_WPTR write if written more than one time before the
701 /* Setup the cp cache like this (cache size is 96 dwords) :
705 * So ring cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
706 * indirect1 cache size is 64dwords (> (2 * max_fetch = 2 * 4dwords))
707 * indirect2 cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
708 * Idea being that most of the gpu cmd will be through indirect1 buffer
709 * so it gets the bigger cache.
711 indirect2_start = 80;
712 indirect1_start = 16;
714 WREG32(0x718, pre_write_timer | (pre_write_limit << 28));
715 WREG32(RADEON_CP_RB_CNTL,
717 RADEON_BUF_SWAP_32BIT |
719 REG_SET(RADEON_RB_BUFSZ, rb_bufsz) |
720 REG_SET(RADEON_RB_BLKSZ, rb_blksz) |
721 REG_SET(RADEON_MAX_FETCH, max_fetch) |
722 RADEON_RB_NO_UPDATE);
723 /* Set ring address */
724 DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)rdev->cp.gpu_addr);
725 WREG32(RADEON_CP_RB_BASE, rdev->cp.gpu_addr);
726 /* Force read & write ptr to 0 */
727 tmp = RREG32(RADEON_CP_RB_CNTL);
728 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
729 WREG32(RADEON_CP_RB_RPTR_WR, 0);
730 WREG32(RADEON_CP_RB_WPTR, 0);
731 WREG32(RADEON_CP_RB_CNTL, tmp);
733 rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR);
734 rdev->cp.wptr = RREG32(RADEON_CP_RB_WPTR);
735 /* Set cp mode to bus mastering & enable cp*/
736 WREG32(RADEON_CP_CSQ_MODE,
737 REG_SET(RADEON_INDIRECT2_START, indirect2_start) |
738 REG_SET(RADEON_INDIRECT1_START, indirect1_start));
740 WREG32(0x744, 0x00004D4D);
741 WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM);
742 radeon_ring_start(rdev);
743 r = radeon_ring_test(rdev);
745 DRM_ERROR("radeon: cp isn't working (%d).\n", r);
748 rdev->cp.ready = true;
752 void r100_cp_fini(struct radeon_device *rdev)
754 if (r100_cp_wait_for_idle(rdev)) {
755 DRM_ERROR("Wait for CP idle timeout, shutting down CP.\n");
758 r100_cp_disable(rdev);
759 radeon_ring_fini(rdev);
760 DRM_INFO("radeon: cp finalized\n");
763 void r100_cp_disable(struct radeon_device *rdev)
766 rdev->cp.ready = false;
767 WREG32(RADEON_CP_CSQ_MODE, 0);
768 WREG32(RADEON_CP_CSQ_CNTL, 0);
769 if (r100_gui_wait_for_idle(rdev)) {
770 printk(KERN_WARNING "Failed to wait GUI idle while "
771 "programming pipes. Bad things might happen.\n");
775 int r100_cp_reset(struct radeon_device *rdev)
781 reinit_cp = rdev->cp.ready;
782 rdev->cp.ready = false;
783 WREG32(RADEON_CP_CSQ_MODE, 0);
784 WREG32(RADEON_CP_CSQ_CNTL, 0);
785 WREG32(RADEON_RBBM_SOFT_RESET, RADEON_SOFT_RESET_CP);
786 (void)RREG32(RADEON_RBBM_SOFT_RESET);
788 WREG32(RADEON_RBBM_SOFT_RESET, 0);
789 /* Wait to prevent race in RBBM_STATUS */
791 for (i = 0; i < rdev->usec_timeout; i++) {
792 tmp = RREG32(RADEON_RBBM_STATUS);
793 if (!(tmp & (1 << 16))) {
794 DRM_INFO("CP reset succeed (RBBM_STATUS=0x%08X)\n",
797 return r100_cp_init(rdev, rdev->cp.ring_size);
803 tmp = RREG32(RADEON_RBBM_STATUS);
804 DRM_ERROR("Failed to reset CP (RBBM_STATUS=0x%08X)!\n", tmp);
808 void r100_cp_commit(struct radeon_device *rdev)
810 WREG32(RADEON_CP_RB_WPTR, rdev->cp.wptr);
811 (void)RREG32(RADEON_CP_RB_WPTR);
818 int r100_cs_parse_packet0(struct radeon_cs_parser *p,
819 struct radeon_cs_packet *pkt,
820 const unsigned *auth, unsigned n,
821 radeon_packet0_check_t check)
830 /* Check that register fall into register range
831 * determined by the number of entry (n) in the
832 * safe register bitmap.
834 if (pkt->one_reg_wr) {
835 if ((reg >> 7) > n) {
839 if (((reg + (pkt->count << 2)) >> 7) > n) {
843 for (i = 0; i <= pkt->count; i++, idx++) {
845 m = 1 << ((reg >> 2) & 31);
847 r = check(p, pkt, idx, reg);
852 if (pkt->one_reg_wr) {
853 if (!(auth[j] & m)) {
863 void r100_cs_dump_packet(struct radeon_cs_parser *p,
864 struct radeon_cs_packet *pkt)
866 volatile uint32_t *ib;
872 for (i = 0; i <= (pkt->count + 1); i++, idx++) {
873 DRM_INFO("ib[%d]=0x%08X\n", idx, ib[idx]);
878 * r100_cs_packet_parse() - parse cp packet and point ib index to next packet
879 * @parser: parser structure holding parsing context.
880 * @pkt: where to store packet informations
882 * Assume that chunk_ib_index is properly set. Will return -EINVAL
883 * if packet is bigger than remaining ib size. or if packets is unknown.
885 int r100_cs_packet_parse(struct radeon_cs_parser *p,
886 struct radeon_cs_packet *pkt,
889 struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
892 if (idx >= ib_chunk->length_dw) {
893 DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
894 idx, ib_chunk->length_dw);
897 header = radeon_get_ib_value(p, idx);
899 pkt->type = CP_PACKET_GET_TYPE(header);
900 pkt->count = CP_PACKET_GET_COUNT(header);
903 pkt->reg = CP_PACKET0_GET_REG(header);
904 pkt->one_reg_wr = CP_PACKET0_GET_ONE_REG_WR(header);
907 pkt->opcode = CP_PACKET3_GET_OPCODE(header);
913 DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx);
916 if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) {
917 DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
918 pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw);
925 * r100_cs_packet_next_vline() - parse userspace VLINE packet
926 * @parser: parser structure holding parsing context.
928 * Userspace sends a special sequence for VLINE waits.
929 * PACKET0 - VLINE_START_END + value
930 * PACKET0 - WAIT_UNTIL +_value
931 * RELOC (P3) - crtc_id in reloc.
933 * This function parses this and relocates the VLINE START END
934 * and WAIT UNTIL packets to the correct crtc.
935 * It also detects a switched off crtc and nulls out the
938 int r100_cs_packet_parse_vline(struct radeon_cs_parser *p)
940 struct drm_mode_object *obj;
941 struct drm_crtc *crtc;
942 struct radeon_crtc *radeon_crtc;
943 struct radeon_cs_packet p3reloc, waitreloc;
946 uint32_t header, h_idx, reg;
947 volatile uint32_t *ib;
951 /* parse the wait until */
952 r = r100_cs_packet_parse(p, &waitreloc, p->idx);
956 /* check its a wait until and only 1 count */
957 if (waitreloc.reg != RADEON_WAIT_UNTIL ||
958 waitreloc.count != 0) {
959 DRM_ERROR("vline wait had illegal wait until segment\n");
964 if (radeon_get_ib_value(p, waitreloc.idx + 1) != RADEON_WAIT_CRTC_VLINE) {
965 DRM_ERROR("vline wait had illegal wait until\n");
970 /* jump over the NOP */
971 r = r100_cs_packet_parse(p, &p3reloc, p->idx + waitreloc.count + 2);
976 p->idx += waitreloc.count + 2;
977 p->idx += p3reloc.count + 2;
979 header = radeon_get_ib_value(p, h_idx);
980 crtc_id = radeon_get_ib_value(p, h_idx + 5);
982 mutex_lock(&p->rdev->ddev->mode_config.mutex);
983 obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC);
985 DRM_ERROR("cannot find crtc %d\n", crtc_id);
989 crtc = obj_to_crtc(obj);
990 radeon_crtc = to_radeon_crtc(crtc);
991 crtc_id = radeon_crtc->crtc_id;
993 if (!crtc->enabled) {
994 /* if the CRTC isn't enabled - we need to nop out the wait until */
995 ib[h_idx + 2] = PACKET2(0);
996 ib[h_idx + 3] = PACKET2(0);
997 } else if (crtc_id == 1) {
999 case AVIVO_D1MODE_VLINE_START_END:
1000 header &= ~R300_CP_PACKET0_REG_MASK;
1001 header |= AVIVO_D2MODE_VLINE_START_END >> 2;
1003 case RADEON_CRTC_GUI_TRIG_VLINE:
1004 header &= ~R300_CP_PACKET0_REG_MASK;
1005 header |= RADEON_CRTC2_GUI_TRIG_VLINE >> 2;
1008 DRM_ERROR("unknown crtc reloc\n");
1013 ib[h_idx + 3] |= RADEON_ENG_DISPLAY_SELECT_CRTC1;
1016 mutex_unlock(&p->rdev->ddev->mode_config.mutex);
1021 * r100_cs_packet_next_reloc() - parse next packet which should be reloc packet3
1022 * @parser: parser structure holding parsing context.
1023 * @data: pointer to relocation data
1024 * @offset_start: starting offset
1025 * @offset_mask: offset mask (to align start offset on)
1026 * @reloc: reloc informations
1028 * Check next packet is relocation packet3, do bo validation and compute
1029 * GPU offset using the provided start.
1031 int r100_cs_packet_next_reloc(struct radeon_cs_parser *p,
1032 struct radeon_cs_reloc **cs_reloc)
1034 struct radeon_cs_chunk *relocs_chunk;
1035 struct radeon_cs_packet p3reloc;
1039 if (p->chunk_relocs_idx == -1) {
1040 DRM_ERROR("No relocation chunk !\n");
1044 relocs_chunk = &p->chunks[p->chunk_relocs_idx];
1045 r = r100_cs_packet_parse(p, &p3reloc, p->idx);
1049 p->idx += p3reloc.count + 2;
1050 if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
1051 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
1053 r100_cs_dump_packet(p, &p3reloc);
1056 idx = radeon_get_ib_value(p, p3reloc.idx + 1);
1057 if (idx >= relocs_chunk->length_dw) {
1058 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
1059 idx, relocs_chunk->length_dw);
1060 r100_cs_dump_packet(p, &p3reloc);
1063 /* FIXME: we assume reloc size is 4 dwords */
1064 *cs_reloc = p->relocs_ptr[(idx / 4)];
1068 static int r100_get_vtx_size(uint32_t vtx_fmt)
1072 /* ordered according to bits in spec */
1073 if (vtx_fmt & RADEON_SE_VTX_FMT_W0)
1075 if (vtx_fmt & RADEON_SE_VTX_FMT_FPCOLOR)
1077 if (vtx_fmt & RADEON_SE_VTX_FMT_FPALPHA)
1079 if (vtx_fmt & RADEON_SE_VTX_FMT_PKCOLOR)
1081 if (vtx_fmt & RADEON_SE_VTX_FMT_FPSPEC)
1083 if (vtx_fmt & RADEON_SE_VTX_FMT_FPFOG)
1085 if (vtx_fmt & RADEON_SE_VTX_FMT_PKSPEC)
1087 if (vtx_fmt & RADEON_SE_VTX_FMT_ST0)
1089 if (vtx_fmt & RADEON_SE_VTX_FMT_ST1)
1091 if (vtx_fmt & RADEON_SE_VTX_FMT_Q1)
1093 if (vtx_fmt & RADEON_SE_VTX_FMT_ST2)
1095 if (vtx_fmt & RADEON_SE_VTX_FMT_Q2)
1097 if (vtx_fmt & RADEON_SE_VTX_FMT_ST3)
1099 if (vtx_fmt & RADEON_SE_VTX_FMT_Q3)
1101 if (vtx_fmt & RADEON_SE_VTX_FMT_Q0)
1104 if (vtx_fmt & (0x7 << 15))
1105 vtx_size += (vtx_fmt >> 15) & 0x7;
1106 if (vtx_fmt & RADEON_SE_VTX_FMT_N0)
1108 if (vtx_fmt & RADEON_SE_VTX_FMT_XY1)
1110 if (vtx_fmt & RADEON_SE_VTX_FMT_Z1)
1112 if (vtx_fmt & RADEON_SE_VTX_FMT_W1)
1114 if (vtx_fmt & RADEON_SE_VTX_FMT_N1)
1116 if (vtx_fmt & RADEON_SE_VTX_FMT_Z)
1121 static int r100_packet0_check(struct radeon_cs_parser *p,
1122 struct radeon_cs_packet *pkt,
1123 unsigned idx, unsigned reg)
1125 struct radeon_cs_reloc *reloc;
1126 struct r100_cs_track *track;
1127 volatile uint32_t *ib;
1135 track = (struct r100_cs_track *)p->track;
1137 idx_value = radeon_get_ib_value(p, idx);
1140 case RADEON_CRTC_GUI_TRIG_VLINE:
1141 r = r100_cs_packet_parse_vline(p);
1143 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1145 r100_cs_dump_packet(p, pkt);
1149 /* FIXME: only allow PACKET3 blit? easier to check for out of
1151 case RADEON_DST_PITCH_OFFSET:
1152 case RADEON_SRC_PITCH_OFFSET:
1153 r = r100_reloc_pitch_offset(p, pkt, idx, reg);
1157 case RADEON_RB3D_DEPTHOFFSET:
1158 r = r100_cs_packet_next_reloc(p, &reloc);
1160 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1162 r100_cs_dump_packet(p, pkt);
1165 track->zb.robj = reloc->robj;
1166 track->zb.offset = idx_value;
1167 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1169 case RADEON_RB3D_COLOROFFSET:
1170 r = r100_cs_packet_next_reloc(p, &reloc);
1172 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1174 r100_cs_dump_packet(p, pkt);
1177 track->cb[0].robj = reloc->robj;
1178 track->cb[0].offset = idx_value;
1179 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1181 case RADEON_PP_TXOFFSET_0:
1182 case RADEON_PP_TXOFFSET_1:
1183 case RADEON_PP_TXOFFSET_2:
1184 i = (reg - RADEON_PP_TXOFFSET_0) / 24;
1185 r = r100_cs_packet_next_reloc(p, &reloc);
1187 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1189 r100_cs_dump_packet(p, pkt);
1192 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1193 track->textures[i].robj = reloc->robj;
1195 case RADEON_PP_CUBIC_OFFSET_T0_0:
1196 case RADEON_PP_CUBIC_OFFSET_T0_1:
1197 case RADEON_PP_CUBIC_OFFSET_T0_2:
1198 case RADEON_PP_CUBIC_OFFSET_T0_3:
1199 case RADEON_PP_CUBIC_OFFSET_T0_4:
1200 i = (reg - RADEON_PP_CUBIC_OFFSET_T0_0) / 4;
1201 r = r100_cs_packet_next_reloc(p, &reloc);
1203 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1205 r100_cs_dump_packet(p, pkt);
1208 track->textures[0].cube_info[i].offset = idx_value;
1209 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1210 track->textures[0].cube_info[i].robj = reloc->robj;
1212 case RADEON_PP_CUBIC_OFFSET_T1_0:
1213 case RADEON_PP_CUBIC_OFFSET_T1_1:
1214 case RADEON_PP_CUBIC_OFFSET_T1_2:
1215 case RADEON_PP_CUBIC_OFFSET_T1_3:
1216 case RADEON_PP_CUBIC_OFFSET_T1_4:
1217 i = (reg - RADEON_PP_CUBIC_OFFSET_T1_0) / 4;
1218 r = r100_cs_packet_next_reloc(p, &reloc);
1220 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1222 r100_cs_dump_packet(p, pkt);
1225 track->textures[1].cube_info[i].offset = idx_value;
1226 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1227 track->textures[1].cube_info[i].robj = reloc->robj;
1229 case RADEON_PP_CUBIC_OFFSET_T2_0:
1230 case RADEON_PP_CUBIC_OFFSET_T2_1:
1231 case RADEON_PP_CUBIC_OFFSET_T2_2:
1232 case RADEON_PP_CUBIC_OFFSET_T2_3:
1233 case RADEON_PP_CUBIC_OFFSET_T2_4:
1234 i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4;
1235 r = r100_cs_packet_next_reloc(p, &reloc);
1237 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1239 r100_cs_dump_packet(p, pkt);
1242 track->textures[2].cube_info[i].offset = idx_value;
1243 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1244 track->textures[2].cube_info[i].robj = reloc->robj;
1246 case RADEON_RE_WIDTH_HEIGHT:
1247 track->maxy = ((idx_value >> 16) & 0x7FF);
1249 case RADEON_RB3D_COLORPITCH:
1250 r = r100_cs_packet_next_reloc(p, &reloc);
1252 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1254 r100_cs_dump_packet(p, pkt);
1258 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
1259 tile_flags |= RADEON_COLOR_TILE_ENABLE;
1260 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
1261 tile_flags |= RADEON_COLOR_MICROTILE_ENABLE;
1263 tmp = idx_value & ~(0x7 << 16);
1267 track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK;
1269 case RADEON_RB3D_DEPTHPITCH:
1270 track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK;
1272 case RADEON_RB3D_CNTL:
1273 switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) {
1279 track->cb[0].cpp = 1;
1284 track->cb[0].cpp = 2;
1287 track->cb[0].cpp = 4;
1290 DRM_ERROR("Invalid color buffer format (%d) !\n",
1291 ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f));
1294 track->z_enabled = !!(idx_value & RADEON_Z_ENABLE);
1296 case RADEON_RB3D_ZSTENCILCNTL:
1297 switch (idx_value & 0xf) {
1313 case RADEON_RB3D_ZPASS_ADDR:
1314 r = r100_cs_packet_next_reloc(p, &reloc);
1316 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1318 r100_cs_dump_packet(p, pkt);
1321 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1323 case RADEON_PP_CNTL:
1325 uint32_t temp = idx_value >> 4;
1326 for (i = 0; i < track->num_texture; i++)
1327 track->textures[i].enabled = !!(temp & (1 << i));
1330 case RADEON_SE_VF_CNTL:
1331 track->vap_vf_cntl = idx_value;
1333 case RADEON_SE_VTX_FMT:
1334 track->vtx_size = r100_get_vtx_size(idx_value);
1336 case RADEON_PP_TEX_SIZE_0:
1337 case RADEON_PP_TEX_SIZE_1:
1338 case RADEON_PP_TEX_SIZE_2:
1339 i = (reg - RADEON_PP_TEX_SIZE_0) / 8;
1340 track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1;
1341 track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1;
1343 case RADEON_PP_TEX_PITCH_0:
1344 case RADEON_PP_TEX_PITCH_1:
1345 case RADEON_PP_TEX_PITCH_2:
1346 i = (reg - RADEON_PP_TEX_PITCH_0) / 8;
1347 track->textures[i].pitch = idx_value + 32;
1349 case RADEON_PP_TXFILTER_0:
1350 case RADEON_PP_TXFILTER_1:
1351 case RADEON_PP_TXFILTER_2:
1352 i = (reg - RADEON_PP_TXFILTER_0) / 24;
1353 track->textures[i].num_levels = ((idx_value & RADEON_MAX_MIP_LEVEL_MASK)
1354 >> RADEON_MAX_MIP_LEVEL_SHIFT);
1355 tmp = (idx_value >> 23) & 0x7;
1356 if (tmp == 2 || tmp == 6)
1357 track->textures[i].roundup_w = false;
1358 tmp = (idx_value >> 27) & 0x7;
1359 if (tmp == 2 || tmp == 6)
1360 track->textures[i].roundup_h = false;
1362 case RADEON_PP_TXFORMAT_0:
1363 case RADEON_PP_TXFORMAT_1:
1364 case RADEON_PP_TXFORMAT_2:
1365 i = (reg - RADEON_PP_TXFORMAT_0) / 24;
1366 if (idx_value & RADEON_TXFORMAT_NON_POWER2) {
1367 track->textures[i].use_pitch = 1;
1369 track->textures[i].use_pitch = 0;
1370 track->textures[i].width = 1 << ((idx_value >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK);
1371 track->textures[i].height = 1 << ((idx_value >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK);
1373 if (idx_value & RADEON_TXFORMAT_CUBIC_MAP_ENABLE)
1374 track->textures[i].tex_coord_type = 2;
1375 switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) {
1376 case RADEON_TXFORMAT_I8:
1377 case RADEON_TXFORMAT_RGB332:
1378 case RADEON_TXFORMAT_Y8:
1379 track->textures[i].cpp = 1;
1381 case RADEON_TXFORMAT_AI88:
1382 case RADEON_TXFORMAT_ARGB1555:
1383 case RADEON_TXFORMAT_RGB565:
1384 case RADEON_TXFORMAT_ARGB4444:
1385 case RADEON_TXFORMAT_VYUY422:
1386 case RADEON_TXFORMAT_YVYU422:
1387 case RADEON_TXFORMAT_DXT1:
1388 case RADEON_TXFORMAT_SHADOW16:
1389 case RADEON_TXFORMAT_LDUDV655:
1390 case RADEON_TXFORMAT_DUDV88:
1391 track->textures[i].cpp = 2;
1393 case RADEON_TXFORMAT_ARGB8888:
1394 case RADEON_TXFORMAT_RGBA8888:
1395 case RADEON_TXFORMAT_DXT23:
1396 case RADEON_TXFORMAT_DXT45:
1397 case RADEON_TXFORMAT_SHADOW32:
1398 case RADEON_TXFORMAT_LDUDUV8888:
1399 track->textures[i].cpp = 4;
1402 track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf);
1403 track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf);
1405 case RADEON_PP_CUBIC_FACES_0:
1406 case RADEON_PP_CUBIC_FACES_1:
1407 case RADEON_PP_CUBIC_FACES_2:
1409 i = (reg - RADEON_PP_CUBIC_FACES_0) / 4;
1410 for (face = 0; face < 4; face++) {
1411 track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf);
1412 track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf);
1416 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
1423 int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
1424 struct radeon_cs_packet *pkt,
1425 struct radeon_object *robj)
1430 value = radeon_get_ib_value(p, idx + 2);
1431 if ((value + 1) > radeon_object_size(robj)) {
1432 DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER "
1433 "(need %u have %lu) !\n",
1435 radeon_object_size(robj));
1441 static int r100_packet3_check(struct radeon_cs_parser *p,
1442 struct radeon_cs_packet *pkt)
1444 struct radeon_cs_reloc *reloc;
1445 struct r100_cs_track *track;
1447 volatile uint32_t *ib;
1452 track = (struct r100_cs_track *)p->track;
1453 switch (pkt->opcode) {
1454 case PACKET3_3D_LOAD_VBPNTR:
1455 r = r100_packet3_load_vbpntr(p, pkt, idx);
1459 case PACKET3_INDX_BUFFER:
1460 r = r100_cs_packet_next_reloc(p, &reloc);
1462 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1463 r100_cs_dump_packet(p, pkt);
1466 ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->lobj.gpu_offset);
1467 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
1473 /* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */
1474 r = r100_cs_packet_next_reloc(p, &reloc);
1476 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1477 r100_cs_dump_packet(p, pkt);
1480 ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->lobj.gpu_offset);
1481 track->num_arrays = 1;
1482 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 2));
1484 track->arrays[0].robj = reloc->robj;
1485 track->arrays[0].esize = track->vtx_size;
1487 track->max_indx = radeon_get_ib_value(p, idx+1);
1489 track->vap_vf_cntl = radeon_get_ib_value(p, idx+3);
1490 track->immd_dwords = pkt->count - 1;
1491 r = r100_cs_track_check(p->rdev, track);
1495 case PACKET3_3D_DRAW_IMMD:
1496 if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) {
1497 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1500 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1501 track->immd_dwords = pkt->count - 1;
1502 r = r100_cs_track_check(p->rdev, track);
1506 /* triggers drawing using in-packet vertex data */
1507 case PACKET3_3D_DRAW_IMMD_2:
1508 if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) {
1509 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1512 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1513 track->immd_dwords = pkt->count;
1514 r = r100_cs_track_check(p->rdev, track);
1518 /* triggers drawing using in-packet vertex data */
1519 case PACKET3_3D_DRAW_VBUF_2:
1520 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1521 r = r100_cs_track_check(p->rdev, track);
1525 /* triggers drawing of vertex buffers setup elsewhere */
1526 case PACKET3_3D_DRAW_INDX_2:
1527 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1528 r = r100_cs_track_check(p->rdev, track);
1532 /* triggers drawing using indices to vertex buffer */
1533 case PACKET3_3D_DRAW_VBUF:
1534 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1535 r = r100_cs_track_check(p->rdev, track);
1539 /* triggers drawing of vertex buffers setup elsewhere */
1540 case PACKET3_3D_DRAW_INDX:
1541 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1542 r = r100_cs_track_check(p->rdev, track);
1546 /* triggers drawing using indices to vertex buffer */
1550 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
1556 int r100_cs_parse(struct radeon_cs_parser *p)
1558 struct radeon_cs_packet pkt;
1559 struct r100_cs_track *track;
1562 track = kzalloc(sizeof(*track), GFP_KERNEL);
1563 r100_cs_track_clear(p->rdev, track);
1566 r = r100_cs_packet_parse(p, &pkt, p->idx);
1570 p->idx += pkt.count + 2;
1573 if (p->rdev->family >= CHIP_R200)
1574 r = r100_cs_parse_packet0(p, &pkt,
1575 p->rdev->config.r100.reg_safe_bm,
1576 p->rdev->config.r100.reg_safe_bm_size,
1577 &r200_packet0_check);
1579 r = r100_cs_parse_packet0(p, &pkt,
1580 p->rdev->config.r100.reg_safe_bm,
1581 p->rdev->config.r100.reg_safe_bm_size,
1582 &r100_packet0_check);
1587 r = r100_packet3_check(p, &pkt);
1590 DRM_ERROR("Unknown packet type %d !\n",
1597 } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
1603 * Global GPU functions
1605 void r100_errata(struct radeon_device *rdev)
1607 rdev->pll_errata = 0;
1609 if (rdev->family == CHIP_RV200 || rdev->family == CHIP_RS200) {
1610 rdev->pll_errata |= CHIP_ERRATA_PLL_DUMMYREADS;
1613 if (rdev->family == CHIP_RV100 ||
1614 rdev->family == CHIP_RS100 ||
1615 rdev->family == CHIP_RS200) {
1616 rdev->pll_errata |= CHIP_ERRATA_PLL_DELAY;
1620 /* Wait for vertical sync on primary CRTC */
1621 void r100_gpu_wait_for_vsync(struct radeon_device *rdev)
1623 uint32_t crtc_gen_cntl, tmp;
1626 crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
1627 if ((crtc_gen_cntl & RADEON_CRTC_DISP_REQ_EN_B) ||
1628 !(crtc_gen_cntl & RADEON_CRTC_EN)) {
1631 /* Clear the CRTC_VBLANK_SAVE bit */
1632 WREG32(RADEON_CRTC_STATUS, RADEON_CRTC_VBLANK_SAVE_CLEAR);
1633 for (i = 0; i < rdev->usec_timeout; i++) {
1634 tmp = RREG32(RADEON_CRTC_STATUS);
1635 if (tmp & RADEON_CRTC_VBLANK_SAVE) {
1642 /* Wait for vertical sync on secondary CRTC */
1643 void r100_gpu_wait_for_vsync2(struct radeon_device *rdev)
1645 uint32_t crtc2_gen_cntl, tmp;
1648 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
1649 if ((crtc2_gen_cntl & RADEON_CRTC2_DISP_REQ_EN_B) ||
1650 !(crtc2_gen_cntl & RADEON_CRTC2_EN))
1653 /* Clear the CRTC_VBLANK_SAVE bit */
1654 WREG32(RADEON_CRTC2_STATUS, RADEON_CRTC2_VBLANK_SAVE_CLEAR);
1655 for (i = 0; i < rdev->usec_timeout; i++) {
1656 tmp = RREG32(RADEON_CRTC2_STATUS);
1657 if (tmp & RADEON_CRTC2_VBLANK_SAVE) {
1664 int r100_rbbm_fifo_wait_for_entry(struct radeon_device *rdev, unsigned n)
1669 for (i = 0; i < rdev->usec_timeout; i++) {
1670 tmp = RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK;
1679 int r100_gui_wait_for_idle(struct radeon_device *rdev)
1684 if (r100_rbbm_fifo_wait_for_entry(rdev, 64)) {
1685 printk(KERN_WARNING "radeon: wait for empty RBBM fifo failed !"
1686 " Bad things might happen.\n");
1688 for (i = 0; i < rdev->usec_timeout; i++) {
1689 tmp = RREG32(RADEON_RBBM_STATUS);
1690 if (!(tmp & (1 << 31))) {
1698 int r100_mc_wait_for_idle(struct radeon_device *rdev)
1703 for (i = 0; i < rdev->usec_timeout; i++) {
1704 /* read MC_STATUS */
1705 tmp = RREG32(0x0150);
1706 if (tmp & (1 << 2)) {
1714 void r100_gpu_init(struct radeon_device *rdev)
1716 /* TODO: anythings to do here ? pipes ? */
1717 r100_hdp_reset(rdev);
1720 void r100_hdp_reset(struct radeon_device *rdev)
1724 tmp = RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL;
1726 WREG32(RADEON_HOST_PATH_CNTL, tmp | RADEON_HDP_SOFT_RESET | RADEON_HDP_READ_BUFFER_INVALIDATE);
1727 (void)RREG32(RADEON_HOST_PATH_CNTL);
1729 WREG32(RADEON_RBBM_SOFT_RESET, 0);
1730 WREG32(RADEON_HOST_PATH_CNTL, tmp);
1731 (void)RREG32(RADEON_HOST_PATH_CNTL);
1734 int r100_rb2d_reset(struct radeon_device *rdev)
1739 WREG32(RADEON_RBBM_SOFT_RESET, RADEON_SOFT_RESET_E2);
1740 (void)RREG32(RADEON_RBBM_SOFT_RESET);
1742 WREG32(RADEON_RBBM_SOFT_RESET, 0);
1743 /* Wait to prevent race in RBBM_STATUS */
1745 for (i = 0; i < rdev->usec_timeout; i++) {
1746 tmp = RREG32(RADEON_RBBM_STATUS);
1747 if (!(tmp & (1 << 26))) {
1748 DRM_INFO("RB2D reset succeed (RBBM_STATUS=0x%08X)\n",
1754 tmp = RREG32(RADEON_RBBM_STATUS);
1755 DRM_ERROR("Failed to reset RB2D (RBBM_STATUS=0x%08X)!\n", tmp);
1759 int r100_gpu_reset(struct radeon_device *rdev)
1763 /* reset order likely matter */
1764 status = RREG32(RADEON_RBBM_STATUS);
1766 r100_hdp_reset(rdev);
1768 if (status & ((1 << 17) | (1 << 18) | (1 << 27))) {
1769 r100_rb2d_reset(rdev);
1771 /* TODO: reset 3D engine */
1773 status = RREG32(RADEON_RBBM_STATUS);
1774 if (status & (1 << 16)) {
1775 r100_cp_reset(rdev);
1777 /* Check if GPU is idle */
1778 status = RREG32(RADEON_RBBM_STATUS);
1779 if (status & (1 << 31)) {
1780 DRM_ERROR("Failed to reset GPU (RBBM_STATUS=0x%08X)\n", status);
1783 DRM_INFO("GPU reset succeed (RBBM_STATUS=0x%08X)\n", status);
1791 static void r100_vram_get_type(struct radeon_device *rdev)
1795 rdev->mc.vram_is_ddr = false;
1796 if (rdev->flags & RADEON_IS_IGP)
1797 rdev->mc.vram_is_ddr = true;
1798 else if (RREG32(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR)
1799 rdev->mc.vram_is_ddr = true;
1800 if ((rdev->family == CHIP_RV100) ||
1801 (rdev->family == CHIP_RS100) ||
1802 (rdev->family == CHIP_RS200)) {
1803 tmp = RREG32(RADEON_MEM_CNTL);
1804 if (tmp & RV100_HALF_MODE) {
1805 rdev->mc.vram_width = 32;
1807 rdev->mc.vram_width = 64;
1809 if (rdev->flags & RADEON_SINGLE_CRTC) {
1810 rdev->mc.vram_width /= 4;
1811 rdev->mc.vram_is_ddr = true;
1813 } else if (rdev->family <= CHIP_RV280) {
1814 tmp = RREG32(RADEON_MEM_CNTL);
1815 if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) {
1816 rdev->mc.vram_width = 128;
1818 rdev->mc.vram_width = 64;
1822 rdev->mc.vram_width = 128;
1826 static u32 r100_get_accessible_vram(struct radeon_device *rdev)
1831 aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
1833 /* Set HDP_APER_CNTL only on cards that are known not to be broken,
1834 * that is has the 2nd generation multifunction PCI interface
1836 if (rdev->family == CHIP_RV280 ||
1837 rdev->family >= CHIP_RV350) {
1838 WREG32_P(RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL,
1839 ~RADEON_HDP_APER_CNTL);
1840 DRM_INFO("Generation 2 PCI interface, using max accessible memory\n");
1841 return aper_size * 2;
1844 /* Older cards have all sorts of funny issues to deal with. First
1845 * check if it's a multifunction card by reading the PCI config
1846 * header type... Limit those to one aperture size
1848 pci_read_config_byte(rdev->pdev, 0xe, &byte);
1850 DRM_INFO("Generation 1 PCI interface in multifunction mode\n");
1851 DRM_INFO("Limiting VRAM to one aperture\n");
1855 /* Single function older card. We read HDP_APER_CNTL to see how the BIOS
1856 * have set it up. We don't write this as it's broken on some ASICs but
1857 * we expect the BIOS to have done the right thing (might be too optimistic...)
1859 if (RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL)
1860 return aper_size * 2;
1864 void r100_vram_init_sizes(struct radeon_device *rdev)
1866 u64 config_aper_size;
1869 config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
1871 if (rdev->flags & RADEON_IS_IGP) {
1873 /* read NB_TOM to get the amount of ram stolen for the GPU */
1874 tom = RREG32(RADEON_NB_TOM);
1875 rdev->mc.real_vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16);
1876 /* for IGPs we need to keep VRAM where it was put by the BIOS */
1877 rdev->mc.vram_location = (tom & 0xffff) << 16;
1878 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
1879 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
1881 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
1882 /* Some production boards of m6 will report 0
1885 if (rdev->mc.real_vram_size == 0) {
1886 rdev->mc.real_vram_size = 8192 * 1024;
1887 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
1889 /* let driver place VRAM */
1890 rdev->mc.vram_location = 0xFFFFFFFFUL;
1891 /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM -
1892 * Novell bug 204882 + along with lots of ubuntu ones */
1893 if (config_aper_size > rdev->mc.real_vram_size)
1894 rdev->mc.mc_vram_size = config_aper_size;
1896 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
1899 /* work out accessible VRAM */
1900 accessible = r100_get_accessible_vram(rdev);
1902 rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
1903 rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
1905 if (accessible > rdev->mc.aper_size)
1906 accessible = rdev->mc.aper_size;
1908 if (rdev->mc.mc_vram_size > rdev->mc.aper_size)
1909 rdev->mc.mc_vram_size = rdev->mc.aper_size;
1911 if (rdev->mc.real_vram_size > rdev->mc.aper_size)
1912 rdev->mc.real_vram_size = rdev->mc.aper_size;
1915 void r100_vga_set_state(struct radeon_device *rdev, bool state)
1919 temp = RREG32(RADEON_CONFIG_CNTL);
1920 if (state == false) {
1926 WREG32(RADEON_CONFIG_CNTL, temp);
1929 void r100_vram_info(struct radeon_device *rdev)
1931 r100_vram_get_type(rdev);
1933 r100_vram_init_sizes(rdev);
1938 * Indirect registers accessor
1940 void r100_pll_errata_after_index(struct radeon_device *rdev)
1942 if (!(rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS)) {
1945 (void)RREG32(RADEON_CLOCK_CNTL_DATA);
1946 (void)RREG32(RADEON_CRTC_GEN_CNTL);
1949 static void r100_pll_errata_after_data(struct radeon_device *rdev)
1951 /* This workarounds is necessary on RV100, RS100 and RS200 chips
1952 * or the chip could hang on a subsequent access
1954 if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) {
1958 /* This function is required to workaround a hardware bug in some (all?)
1959 * revisions of the R300. This workaround should be called after every
1960 * CLOCK_CNTL_INDEX register access. If not, register reads afterward
1961 * may not be correct.
1963 if (rdev->pll_errata & CHIP_ERRATA_R300_CG) {
1966 save = RREG32(RADEON_CLOCK_CNTL_INDEX);
1967 tmp = save & ~(0x3f | RADEON_PLL_WR_EN);
1968 WREG32(RADEON_CLOCK_CNTL_INDEX, tmp);
1969 tmp = RREG32(RADEON_CLOCK_CNTL_DATA);
1970 WREG32(RADEON_CLOCK_CNTL_INDEX, save);
1974 uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg)
1978 WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f);
1979 r100_pll_errata_after_index(rdev);
1980 data = RREG32(RADEON_CLOCK_CNTL_DATA);
1981 r100_pll_errata_after_data(rdev);
1985 void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
1987 WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) | RADEON_PLL_WR_EN));
1988 r100_pll_errata_after_index(rdev);
1989 WREG32(RADEON_CLOCK_CNTL_DATA, v);
1990 r100_pll_errata_after_data(rdev);
1993 int r100_init(struct radeon_device *rdev)
1995 if (ASIC_IS_RN50(rdev)) {
1996 rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm;
1997 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(rn50_reg_safe_bm);
1998 } else if (rdev->family < CHIP_R200) {
1999 rdev->config.r100.reg_safe_bm = r100_reg_safe_bm;
2000 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm);
2002 return r200_init(rdev);
2010 #if defined(CONFIG_DEBUG_FS)
2011 static int r100_debugfs_rbbm_info(struct seq_file *m, void *data)
2013 struct drm_info_node *node = (struct drm_info_node *) m->private;
2014 struct drm_device *dev = node->minor->dev;
2015 struct radeon_device *rdev = dev->dev_private;
2016 uint32_t reg, value;
2019 seq_printf(m, "RBBM_STATUS 0x%08x\n", RREG32(RADEON_RBBM_STATUS));
2020 seq_printf(m, "RBBM_CMDFIFO_STAT 0x%08x\n", RREG32(0xE7C));
2021 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2022 for (i = 0; i < 64; i++) {
2023 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i | 0x100);
2024 reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA) - 1) >> 2;
2025 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i);
2026 value = RREG32(RADEON_RBBM_CMDFIFO_DATA);
2027 seq_printf(m, "[0x%03X] 0x%04X=0x%08X\n", i, reg, value);
2032 static int r100_debugfs_cp_ring_info(struct seq_file *m, void *data)
2034 struct drm_info_node *node = (struct drm_info_node *) m->private;
2035 struct drm_device *dev = node->minor->dev;
2036 struct radeon_device *rdev = dev->dev_private;
2038 unsigned count, i, j;
2040 radeon_ring_free_size(rdev);
2041 rdp = RREG32(RADEON_CP_RB_RPTR);
2042 wdp = RREG32(RADEON_CP_RB_WPTR);
2043 count = (rdp + rdev->cp.ring_size - wdp) & rdev->cp.ptr_mask;
2044 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2045 seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp);
2046 seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp);
2047 seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw);
2048 seq_printf(m, "%u dwords in ring\n", count);
2049 for (j = 0; j <= count; j++) {
2050 i = (rdp + j) & rdev->cp.ptr_mask;
2051 seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]);
2057 static int r100_debugfs_cp_csq_fifo(struct seq_file *m, void *data)
2059 struct drm_info_node *node = (struct drm_info_node *) m->private;
2060 struct drm_device *dev = node->minor->dev;
2061 struct radeon_device *rdev = dev->dev_private;
2062 uint32_t csq_stat, csq2_stat, tmp;
2063 unsigned r_rptr, r_wptr, ib1_rptr, ib1_wptr, ib2_rptr, ib2_wptr;
2066 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2067 seq_printf(m, "CP_CSQ_MODE 0x%08x\n", RREG32(RADEON_CP_CSQ_MODE));
2068 csq_stat = RREG32(RADEON_CP_CSQ_STAT);
2069 csq2_stat = RREG32(RADEON_CP_CSQ2_STAT);
2070 r_rptr = (csq_stat >> 0) & 0x3ff;
2071 r_wptr = (csq_stat >> 10) & 0x3ff;
2072 ib1_rptr = (csq_stat >> 20) & 0x3ff;
2073 ib1_wptr = (csq2_stat >> 0) & 0x3ff;
2074 ib2_rptr = (csq2_stat >> 10) & 0x3ff;
2075 ib2_wptr = (csq2_stat >> 20) & 0x3ff;
2076 seq_printf(m, "CP_CSQ_STAT 0x%08x\n", csq_stat);
2077 seq_printf(m, "CP_CSQ2_STAT 0x%08x\n", csq2_stat);
2078 seq_printf(m, "Ring rptr %u\n", r_rptr);
2079 seq_printf(m, "Ring wptr %u\n", r_wptr);
2080 seq_printf(m, "Indirect1 rptr %u\n", ib1_rptr);
2081 seq_printf(m, "Indirect1 wptr %u\n", ib1_wptr);
2082 seq_printf(m, "Indirect2 rptr %u\n", ib2_rptr);
2083 seq_printf(m, "Indirect2 wptr %u\n", ib2_wptr);
2084 /* FIXME: 0, 128, 640 depends on fifo setup see cp_init_kms
2085 * 128 = indirect1_start * 8 & 640 = indirect2_start * 8 */
2086 seq_printf(m, "Ring fifo:\n");
2087 for (i = 0; i < 256; i++) {
2088 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2089 tmp = RREG32(RADEON_CP_CSQ_DATA);
2090 seq_printf(m, "rfifo[%04d]=0x%08X\n", i, tmp);
2092 seq_printf(m, "Indirect1 fifo:\n");
2093 for (i = 256; i <= 512; i++) {
2094 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2095 tmp = RREG32(RADEON_CP_CSQ_DATA);
2096 seq_printf(m, "ib1fifo[%04d]=0x%08X\n", i, tmp);
2098 seq_printf(m, "Indirect2 fifo:\n");
2099 for (i = 640; i < ib1_wptr; i++) {
2100 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2101 tmp = RREG32(RADEON_CP_CSQ_DATA);
2102 seq_printf(m, "ib2fifo[%04d]=0x%08X\n", i, tmp);
2107 static int r100_debugfs_mc_info(struct seq_file *m, void *data)
2109 struct drm_info_node *node = (struct drm_info_node *) m->private;
2110 struct drm_device *dev = node->minor->dev;
2111 struct radeon_device *rdev = dev->dev_private;
2114 tmp = RREG32(RADEON_CONFIG_MEMSIZE);
2115 seq_printf(m, "CONFIG_MEMSIZE 0x%08x\n", tmp);
2116 tmp = RREG32(RADEON_MC_FB_LOCATION);
2117 seq_printf(m, "MC_FB_LOCATION 0x%08x\n", tmp);
2118 tmp = RREG32(RADEON_BUS_CNTL);
2119 seq_printf(m, "BUS_CNTL 0x%08x\n", tmp);
2120 tmp = RREG32(RADEON_MC_AGP_LOCATION);
2121 seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp);
2122 tmp = RREG32(RADEON_AGP_BASE);
2123 seq_printf(m, "AGP_BASE 0x%08x\n", tmp);
2124 tmp = RREG32(RADEON_HOST_PATH_CNTL);
2125 seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp);
2126 tmp = RREG32(0x01D0);
2127 seq_printf(m, "AIC_CTRL 0x%08x\n", tmp);
2128 tmp = RREG32(RADEON_AIC_LO_ADDR);
2129 seq_printf(m, "AIC_LO_ADDR 0x%08x\n", tmp);
2130 tmp = RREG32(RADEON_AIC_HI_ADDR);
2131 seq_printf(m, "AIC_HI_ADDR 0x%08x\n", tmp);
2132 tmp = RREG32(0x01E4);
2133 seq_printf(m, "AIC_TLB_ADDR 0x%08x\n", tmp);
2137 static struct drm_info_list r100_debugfs_rbbm_list[] = {
2138 {"r100_rbbm_info", r100_debugfs_rbbm_info, 0, NULL},
2141 static struct drm_info_list r100_debugfs_cp_list[] = {
2142 {"r100_cp_ring_info", r100_debugfs_cp_ring_info, 0, NULL},
2143 {"r100_cp_csq_fifo", r100_debugfs_cp_csq_fifo, 0, NULL},
2146 static struct drm_info_list r100_debugfs_mc_info_list[] = {
2147 {"r100_mc_info", r100_debugfs_mc_info, 0, NULL},
2151 int r100_debugfs_rbbm_init(struct radeon_device *rdev)
2153 #if defined(CONFIG_DEBUG_FS)
2154 return radeon_debugfs_add_files(rdev, r100_debugfs_rbbm_list, 1);
2160 int r100_debugfs_cp_init(struct radeon_device *rdev)
2162 #if defined(CONFIG_DEBUG_FS)
2163 return radeon_debugfs_add_files(rdev, r100_debugfs_cp_list, 2);
2169 int r100_debugfs_mc_info_init(struct radeon_device *rdev)
2171 #if defined(CONFIG_DEBUG_FS)
2172 return radeon_debugfs_add_files(rdev, r100_debugfs_mc_info_list, 1);
2178 int r100_set_surface_reg(struct radeon_device *rdev, int reg,
2179 uint32_t tiling_flags, uint32_t pitch,
2180 uint32_t offset, uint32_t obj_size)
2182 int surf_index = reg * 16;
2185 /* r100/r200 divide by 16 */
2186 if (rdev->family < CHIP_R300)
2191 if (rdev->family <= CHIP_RS200) {
2192 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
2193 == (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
2194 flags |= RADEON_SURF_TILE_COLOR_BOTH;
2195 if (tiling_flags & RADEON_TILING_MACRO)
2196 flags |= RADEON_SURF_TILE_COLOR_MACRO;
2197 } else if (rdev->family <= CHIP_RV280) {
2198 if (tiling_flags & (RADEON_TILING_MACRO))
2199 flags |= R200_SURF_TILE_COLOR_MACRO;
2200 if (tiling_flags & RADEON_TILING_MICRO)
2201 flags |= R200_SURF_TILE_COLOR_MICRO;
2203 if (tiling_flags & RADEON_TILING_MACRO)
2204 flags |= R300_SURF_TILE_MACRO;
2205 if (tiling_flags & RADEON_TILING_MICRO)
2206 flags |= R300_SURF_TILE_MICRO;
2209 if (tiling_flags & RADEON_TILING_SWAP_16BIT)
2210 flags |= RADEON_SURF_AP0_SWP_16BPP | RADEON_SURF_AP1_SWP_16BPP;
2211 if (tiling_flags & RADEON_TILING_SWAP_32BIT)
2212 flags |= RADEON_SURF_AP0_SWP_32BPP | RADEON_SURF_AP1_SWP_32BPP;
2214 DRM_DEBUG("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1);
2215 WREG32(RADEON_SURFACE0_INFO + surf_index, flags);
2216 WREG32(RADEON_SURFACE0_LOWER_BOUND + surf_index, offset);
2217 WREG32(RADEON_SURFACE0_UPPER_BOUND + surf_index, offset + obj_size - 1);
2221 void r100_clear_surface_reg(struct radeon_device *rdev, int reg)
2223 int surf_index = reg * 16;
2224 WREG32(RADEON_SURFACE0_INFO + surf_index, 0);
2227 void r100_bandwidth_update(struct radeon_device *rdev)
2229 fixed20_12 trcd_ff, trp_ff, tras_ff, trbs_ff, tcas_ff;
2230 fixed20_12 sclk_ff, mclk_ff, sclk_eff_ff, sclk_delay_ff;
2231 fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff, crit_point_ff;
2232 uint32_t temp, data, mem_trcd, mem_trp, mem_tras;
2233 fixed20_12 memtcas_ff[8] = {
2242 fixed20_12 memtcas_rs480_ff[8] = {
2252 fixed20_12 memtcas2_ff[8] = {
2262 fixed20_12 memtrbs[8] = {
2272 fixed20_12 memtrbs_r4xx[8] = {
2282 fixed20_12 min_mem_eff;
2283 fixed20_12 mc_latency_sclk, mc_latency_mclk, k1;
2284 fixed20_12 cur_latency_mclk, cur_latency_sclk;
2285 fixed20_12 disp_latency, disp_latency_overhead, disp_drain_rate,
2286 disp_drain_rate2, read_return_rate;
2287 fixed20_12 time_disp1_drop_priority;
2289 int cur_size = 16; /* in octawords */
2290 int critical_point = 0, critical_point2;
2291 /* uint32_t read_return_rate, time_disp1_drop_priority; */
2292 int stop_req, max_stop_req;
2293 struct drm_display_mode *mode1 = NULL;
2294 struct drm_display_mode *mode2 = NULL;
2295 uint32_t pixel_bytes1 = 0;
2296 uint32_t pixel_bytes2 = 0;
2298 if (rdev->mode_info.crtcs[0]->base.enabled) {
2299 mode1 = &rdev->mode_info.crtcs[0]->base.mode;
2300 pixel_bytes1 = rdev->mode_info.crtcs[0]->base.fb->bits_per_pixel / 8;
2302 if (rdev->mode_info.crtcs[1]->base.enabled) {
2303 mode2 = &rdev->mode_info.crtcs[1]->base.mode;
2304 pixel_bytes2 = rdev->mode_info.crtcs[1]->base.fb->bits_per_pixel / 8;
2307 min_mem_eff.full = rfixed_const_8(0);
2309 if ((rdev->disp_priority == 2) && ASIC_IS_R300(rdev)) {
2310 uint32_t mc_init_misc_lat_timer = RREG32(R300_MC_INIT_MISC_LAT_TIMER);
2311 mc_init_misc_lat_timer &= ~(R300_MC_DISP1R_INIT_LAT_MASK << R300_MC_DISP1R_INIT_LAT_SHIFT);
2312 mc_init_misc_lat_timer &= ~(R300_MC_DISP0R_INIT_LAT_MASK << R300_MC_DISP0R_INIT_LAT_SHIFT);
2313 /* check crtc enables */
2315 mc_init_misc_lat_timer |= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT);
2317 mc_init_misc_lat_timer |= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT);
2318 WREG32(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer);
2322 * determine is there is enough bw for current mode
2324 mclk_ff.full = rfixed_const(rdev->clock.default_mclk);
2325 temp_ff.full = rfixed_const(100);
2326 mclk_ff.full = rfixed_div(mclk_ff, temp_ff);
2327 sclk_ff.full = rfixed_const(rdev->clock.default_sclk);
2328 sclk_ff.full = rfixed_div(sclk_ff, temp_ff);
2330 temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1);
2331 temp_ff.full = rfixed_const(temp);
2332 mem_bw.full = rfixed_mul(mclk_ff, temp_ff);
2336 peak_disp_bw.full = 0;
2338 temp_ff.full = rfixed_const(1000);
2339 pix_clk.full = rfixed_const(mode1->clock); /* convert to fixed point */
2340 pix_clk.full = rfixed_div(pix_clk, temp_ff);
2341 temp_ff.full = rfixed_const(pixel_bytes1);
2342 peak_disp_bw.full += rfixed_mul(pix_clk, temp_ff);
2345 temp_ff.full = rfixed_const(1000);
2346 pix_clk2.full = rfixed_const(mode2->clock); /* convert to fixed point */
2347 pix_clk2.full = rfixed_div(pix_clk2, temp_ff);
2348 temp_ff.full = rfixed_const(pixel_bytes2);
2349 peak_disp_bw.full += rfixed_mul(pix_clk2, temp_ff);
2352 mem_bw.full = rfixed_mul(mem_bw, min_mem_eff);
2353 if (peak_disp_bw.full >= mem_bw.full) {
2354 DRM_ERROR("You may not have enough display bandwidth for current mode\n"
2355 "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n");
2358 /* Get values from the EXT_MEM_CNTL register...converting its contents. */
2359 temp = RREG32(RADEON_MEM_TIMING_CNTL);
2360 if ((rdev->family == CHIP_RV100) || (rdev->flags & RADEON_IS_IGP)) { /* RV100, M6, IGPs */
2361 mem_trcd = ((temp >> 2) & 0x3) + 1;
2362 mem_trp = ((temp & 0x3)) + 1;
2363 mem_tras = ((temp & 0x70) >> 4) + 1;
2364 } else if (rdev->family == CHIP_R300 ||
2365 rdev->family == CHIP_R350) { /* r300, r350 */
2366 mem_trcd = (temp & 0x7) + 1;
2367 mem_trp = ((temp >> 8) & 0x7) + 1;
2368 mem_tras = ((temp >> 11) & 0xf) + 4;
2369 } else if (rdev->family == CHIP_RV350 ||
2370 rdev->family <= CHIP_RV380) {
2372 mem_trcd = (temp & 0x7) + 3;
2373 mem_trp = ((temp >> 8) & 0x7) + 3;
2374 mem_tras = ((temp >> 11) & 0xf) + 6;
2375 } else if (rdev->family == CHIP_R420 ||
2376 rdev->family == CHIP_R423 ||
2377 rdev->family == CHIP_RV410) {
2379 mem_trcd = (temp & 0xf) + 3;
2382 mem_trp = ((temp >> 8) & 0xf) + 3;
2385 mem_tras = ((temp >> 12) & 0x1f) + 6;
2388 } else { /* RV200, R200 */
2389 mem_trcd = (temp & 0x7) + 1;
2390 mem_trp = ((temp >> 8) & 0x7) + 1;
2391 mem_tras = ((temp >> 12) & 0xf) + 4;
2394 trcd_ff.full = rfixed_const(mem_trcd);
2395 trp_ff.full = rfixed_const(mem_trp);
2396 tras_ff.full = rfixed_const(mem_tras);
2398 /* Get values from the MEM_SDRAM_MODE_REG register...converting its */
2399 temp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
2400 data = (temp & (7 << 20)) >> 20;
2401 if ((rdev->family == CHIP_RV100) || rdev->flags & RADEON_IS_IGP) {
2402 if (rdev->family == CHIP_RS480) /* don't think rs400 */
2403 tcas_ff = memtcas_rs480_ff[data];
2405 tcas_ff = memtcas_ff[data];
2407 tcas_ff = memtcas2_ff[data];
2409 if (rdev->family == CHIP_RS400 ||
2410 rdev->family == CHIP_RS480) {
2411 /* extra cas latency stored in bits 23-25 0-4 clocks */
2412 data = (temp >> 23) & 0x7;
2414 tcas_ff.full += rfixed_const(data);
2417 if (ASIC_IS_R300(rdev) && !(rdev->flags & RADEON_IS_IGP)) {
2418 /* on the R300, Tcas is included in Trbs.
2420 temp = RREG32(RADEON_MEM_CNTL);
2421 data = (R300_MEM_NUM_CHANNELS_MASK & temp);
2423 if (R300_MEM_USE_CD_CH_ONLY & temp) {
2424 temp = RREG32(R300_MC_IND_INDEX);
2425 temp &= ~R300_MC_IND_ADDR_MASK;
2426 temp |= R300_MC_READ_CNTL_CD_mcind;
2427 WREG32(R300_MC_IND_INDEX, temp);
2428 temp = RREG32(R300_MC_IND_DATA);
2429 data = (R300_MEM_RBS_POSITION_C_MASK & temp);
2431 temp = RREG32(R300_MC_READ_CNTL_AB);
2432 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
2435 temp = RREG32(R300_MC_READ_CNTL_AB);
2436 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
2438 if (rdev->family == CHIP_RV410 ||
2439 rdev->family == CHIP_R420 ||
2440 rdev->family == CHIP_R423)
2441 trbs_ff = memtrbs_r4xx[data];
2443 trbs_ff = memtrbs[data];
2444 tcas_ff.full += trbs_ff.full;
2447 sclk_eff_ff.full = sclk_ff.full;
2449 if (rdev->flags & RADEON_IS_AGP) {
2450 fixed20_12 agpmode_ff;
2451 agpmode_ff.full = rfixed_const(radeon_agpmode);
2452 temp_ff.full = rfixed_const_666(16);
2453 sclk_eff_ff.full -= rfixed_mul(agpmode_ff, temp_ff);
2455 /* TODO PCIE lanes may affect this - agpmode == 16?? */
2457 if (ASIC_IS_R300(rdev)) {
2458 sclk_delay_ff.full = rfixed_const(250);
2460 if ((rdev->family == CHIP_RV100) ||
2461 rdev->flags & RADEON_IS_IGP) {
2462 if (rdev->mc.vram_is_ddr)
2463 sclk_delay_ff.full = rfixed_const(41);
2465 sclk_delay_ff.full = rfixed_const(33);
2467 if (rdev->mc.vram_width == 128)
2468 sclk_delay_ff.full = rfixed_const(57);
2470 sclk_delay_ff.full = rfixed_const(41);
2474 mc_latency_sclk.full = rfixed_div(sclk_delay_ff, sclk_eff_ff);
2476 if (rdev->mc.vram_is_ddr) {
2477 if (rdev->mc.vram_width == 32) {
2478 k1.full = rfixed_const(40);
2481 k1.full = rfixed_const(20);
2485 k1.full = rfixed_const(40);
2489 temp_ff.full = rfixed_const(2);
2490 mc_latency_mclk.full = rfixed_mul(trcd_ff, temp_ff);
2491 temp_ff.full = rfixed_const(c);
2492 mc_latency_mclk.full += rfixed_mul(tcas_ff, temp_ff);
2493 temp_ff.full = rfixed_const(4);
2494 mc_latency_mclk.full += rfixed_mul(tras_ff, temp_ff);
2495 mc_latency_mclk.full += rfixed_mul(trp_ff, temp_ff);
2496 mc_latency_mclk.full += k1.full;
2498 mc_latency_mclk.full = rfixed_div(mc_latency_mclk, mclk_ff);
2499 mc_latency_mclk.full += rfixed_div(temp_ff, sclk_eff_ff);
2502 HW cursor time assuming worst case of full size colour cursor.
2504 temp_ff.full = rfixed_const((2 * (cur_size - (rdev->mc.vram_is_ddr + 1))));
2505 temp_ff.full += trcd_ff.full;
2506 if (temp_ff.full < tras_ff.full)
2507 temp_ff.full = tras_ff.full;
2508 cur_latency_mclk.full = rfixed_div(temp_ff, mclk_ff);
2510 temp_ff.full = rfixed_const(cur_size);
2511 cur_latency_sclk.full = rfixed_div(temp_ff, sclk_eff_ff);
2513 Find the total latency for the display data.
2515 disp_latency_overhead.full = rfixed_const(80);
2516 disp_latency_overhead.full = rfixed_div(disp_latency_overhead, sclk_ff);
2517 mc_latency_mclk.full += disp_latency_overhead.full + cur_latency_mclk.full;
2518 mc_latency_sclk.full += disp_latency_overhead.full + cur_latency_sclk.full;
2520 if (mc_latency_mclk.full > mc_latency_sclk.full)
2521 disp_latency.full = mc_latency_mclk.full;
2523 disp_latency.full = mc_latency_sclk.full;
2525 /* setup Max GRPH_STOP_REQ default value */
2526 if (ASIC_IS_RV100(rdev))
2527 max_stop_req = 0x5c;
2529 max_stop_req = 0x7c;
2533 Set GRPH_BUFFER_CNTL register using h/w defined optimal values.
2534 GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ]
2536 stop_req = mode1->hdisplay * pixel_bytes1 / 16;
2538 if (stop_req > max_stop_req)
2539 stop_req = max_stop_req;
2542 Find the drain rate of the display buffer.
2544 temp_ff.full = rfixed_const((16/pixel_bytes1));
2545 disp_drain_rate.full = rfixed_div(pix_clk, temp_ff);
2548 Find the critical point of the display buffer.
2550 crit_point_ff.full = rfixed_mul(disp_drain_rate, disp_latency);
2551 crit_point_ff.full += rfixed_const_half(0);
2553 critical_point = rfixed_trunc(crit_point_ff);
2555 if (rdev->disp_priority == 2) {
2560 The critical point should never be above max_stop_req-4. Setting
2561 GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time.
2563 if (max_stop_req - critical_point < 4)
2566 if (critical_point == 0 && mode2 && rdev->family == CHIP_R300) {
2567 /* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/
2568 critical_point = 0x10;
2571 temp = RREG32(RADEON_GRPH_BUFFER_CNTL);
2572 temp &= ~(RADEON_GRPH_STOP_REQ_MASK);
2573 temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
2574 temp &= ~(RADEON_GRPH_START_REQ_MASK);
2575 if ((rdev->family == CHIP_R350) &&
2576 (stop_req > 0x15)) {
2579 temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
2580 temp |= RADEON_GRPH_BUFFER_SIZE;
2581 temp &= ~(RADEON_GRPH_CRITICAL_CNTL |
2582 RADEON_GRPH_CRITICAL_AT_SOF |
2583 RADEON_GRPH_STOP_CNTL);
2585 Write the result into the register.
2587 WREG32(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
2588 (critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
2591 if ((rdev->family == CHIP_RS400) ||
2592 (rdev->family == CHIP_RS480)) {
2593 /* attempt to program RS400 disp regs correctly ??? */
2594 temp = RREG32(RS400_DISP1_REG_CNTL);
2595 temp &= ~(RS400_DISP1_START_REQ_LEVEL_MASK |
2596 RS400_DISP1_STOP_REQ_LEVEL_MASK);
2597 WREG32(RS400_DISP1_REQ_CNTL1, (temp |
2598 (critical_point << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
2599 (critical_point << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
2600 temp = RREG32(RS400_DMIF_MEM_CNTL1);
2601 temp &= ~(RS400_DISP1_CRITICAL_POINT_START_MASK |
2602 RS400_DISP1_CRITICAL_POINT_STOP_MASK);
2603 WREG32(RS400_DMIF_MEM_CNTL1, (temp |
2604 (critical_point << RS400_DISP1_CRITICAL_POINT_START_SHIFT) |
2605 (critical_point << RS400_DISP1_CRITICAL_POINT_STOP_SHIFT)));
2609 DRM_DEBUG("GRPH_BUFFER_CNTL from to %x\n",
2610 /* (unsigned int)info->SavedReg->grph_buffer_cntl, */
2611 (unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL));
2616 stop_req = mode2->hdisplay * pixel_bytes2 / 16;
2618 if (stop_req > max_stop_req)
2619 stop_req = max_stop_req;
2622 Find the drain rate of the display buffer.
2624 temp_ff.full = rfixed_const((16/pixel_bytes2));
2625 disp_drain_rate2.full = rfixed_div(pix_clk2, temp_ff);
2627 grph2_cntl = RREG32(RADEON_GRPH2_BUFFER_CNTL);
2628 grph2_cntl &= ~(RADEON_GRPH_STOP_REQ_MASK);
2629 grph2_cntl |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
2630 grph2_cntl &= ~(RADEON_GRPH_START_REQ_MASK);
2631 if ((rdev->family == CHIP_R350) &&
2632 (stop_req > 0x15)) {
2635 grph2_cntl |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
2636 grph2_cntl |= RADEON_GRPH_BUFFER_SIZE;
2637 grph2_cntl &= ~(RADEON_GRPH_CRITICAL_CNTL |
2638 RADEON_GRPH_CRITICAL_AT_SOF |
2639 RADEON_GRPH_STOP_CNTL);
2641 if ((rdev->family == CHIP_RS100) ||
2642 (rdev->family == CHIP_RS200))
2643 critical_point2 = 0;
2645 temp = (rdev->mc.vram_width * rdev->mc.vram_is_ddr + 1)/128;
2646 temp_ff.full = rfixed_const(temp);
2647 temp_ff.full = rfixed_mul(mclk_ff, temp_ff);
2648 if (sclk_ff.full < temp_ff.full)
2649 temp_ff.full = sclk_ff.full;
2651 read_return_rate.full = temp_ff.full;
2654 temp_ff.full = read_return_rate.full - disp_drain_rate.full;
2655 time_disp1_drop_priority.full = rfixed_div(crit_point_ff, temp_ff);
2657 time_disp1_drop_priority.full = 0;
2659 crit_point_ff.full = disp_latency.full + time_disp1_drop_priority.full + disp_latency.full;
2660 crit_point_ff.full = rfixed_mul(crit_point_ff, disp_drain_rate2);
2661 crit_point_ff.full += rfixed_const_half(0);
2663 critical_point2 = rfixed_trunc(crit_point_ff);
2665 if (rdev->disp_priority == 2) {
2666 critical_point2 = 0;
2669 if (max_stop_req - critical_point2 < 4)
2670 critical_point2 = 0;
2674 if (critical_point2 == 0 && rdev->family == CHIP_R300) {
2675 /* some R300 cards have problem with this set to 0 */
2676 critical_point2 = 0x10;
2679 WREG32(RADEON_GRPH2_BUFFER_CNTL, ((grph2_cntl & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
2680 (critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
2682 if ((rdev->family == CHIP_RS400) ||
2683 (rdev->family == CHIP_RS480)) {
2685 /* attempt to program RS400 disp2 regs correctly ??? */
2686 temp = RREG32(RS400_DISP2_REQ_CNTL1);
2687 temp &= ~(RS400_DISP2_START_REQ_LEVEL_MASK |
2688 RS400_DISP2_STOP_REQ_LEVEL_MASK);
2689 WREG32(RS400_DISP2_REQ_CNTL1, (temp |
2690 (critical_point2 << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
2691 (critical_point2 << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
2692 temp = RREG32(RS400_DISP2_REQ_CNTL2);
2693 temp &= ~(RS400_DISP2_CRITICAL_POINT_START_MASK |
2694 RS400_DISP2_CRITICAL_POINT_STOP_MASK);
2695 WREG32(RS400_DISP2_REQ_CNTL2, (temp |
2696 (critical_point2 << RS400_DISP2_CRITICAL_POINT_START_SHIFT) |
2697 (critical_point2 << RS400_DISP2_CRITICAL_POINT_STOP_SHIFT)));
2699 WREG32(RS400_DISP2_REQ_CNTL1, 0x105DC1CC);
2700 WREG32(RS400_DISP2_REQ_CNTL2, 0x2749D000);
2701 WREG32(RS400_DMIF_MEM_CNTL1, 0x29CA71DC);
2702 WREG32(RS400_DISP1_REQ_CNTL1, 0x28FBC3AC);
2705 DRM_DEBUG("GRPH2_BUFFER_CNTL from to %x\n",
2706 (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL));
2710 static inline void r100_cs_track_texture_print(struct r100_cs_track_texture *t)
2712 DRM_ERROR("pitch %d\n", t->pitch);
2713 DRM_ERROR("width %d\n", t->width);
2714 DRM_ERROR("height %d\n", t->height);
2715 DRM_ERROR("num levels %d\n", t->num_levels);
2716 DRM_ERROR("depth %d\n", t->txdepth);
2717 DRM_ERROR("bpp %d\n", t->cpp);
2718 DRM_ERROR("coordinate type %d\n", t->tex_coord_type);
2719 DRM_ERROR("width round to power of 2 %d\n", t->roundup_w);
2720 DRM_ERROR("height round to power of 2 %d\n", t->roundup_h);
2723 static int r100_cs_track_cube(struct radeon_device *rdev,
2724 struct r100_cs_track *track, unsigned idx)
2726 unsigned face, w, h;
2727 struct radeon_object *cube_robj;
2730 for (face = 0; face < 5; face++) {
2731 cube_robj = track->textures[idx].cube_info[face].robj;
2732 w = track->textures[idx].cube_info[face].width;
2733 h = track->textures[idx].cube_info[face].height;
2736 size *= track->textures[idx].cpp;
2738 size += track->textures[idx].cube_info[face].offset;
2740 if (size > radeon_object_size(cube_robj)) {
2741 DRM_ERROR("Cube texture offset greater than object size %lu %lu\n",
2742 size, radeon_object_size(cube_robj));
2743 r100_cs_track_texture_print(&track->textures[idx]);
2750 static int r100_cs_track_texture_check(struct radeon_device *rdev,
2751 struct r100_cs_track *track)
2753 struct radeon_object *robj;
2755 unsigned u, i, w, h;
2758 for (u = 0; u < track->num_texture; u++) {
2759 if (!track->textures[u].enabled)
2761 robj = track->textures[u].robj;
2763 DRM_ERROR("No texture bound to unit %u\n", u);
2767 for (i = 0; i <= track->textures[u].num_levels; i++) {
2768 if (track->textures[u].use_pitch) {
2769 if (rdev->family < CHIP_R300)
2770 w = (track->textures[u].pitch / track->textures[u].cpp) / (1 << i);
2772 w = track->textures[u].pitch / (1 << i);
2774 w = track->textures[u].width / (1 << i);
2775 if (rdev->family >= CHIP_RV515)
2776 w |= track->textures[u].width_11;
2777 if (track->textures[u].roundup_w)
2778 w = roundup_pow_of_two(w);
2780 h = track->textures[u].height / (1 << i);
2781 if (rdev->family >= CHIP_RV515)
2782 h |= track->textures[u].height_11;
2783 if (track->textures[u].roundup_h)
2784 h = roundup_pow_of_two(h);
2787 size *= track->textures[u].cpp;
2788 switch (track->textures[u].tex_coord_type) {
2792 size *= (1 << track->textures[u].txdepth);
2795 if (track->separate_cube) {
2796 ret = r100_cs_track_cube(rdev, track, u);
2803 DRM_ERROR("Invalid texture coordinate type %u for unit "
2804 "%u\n", track->textures[u].tex_coord_type, u);
2807 if (size > radeon_object_size(robj)) {
2808 DRM_ERROR("Texture of unit %u needs %lu bytes but is "
2809 "%lu\n", u, size, radeon_object_size(robj));
2810 r100_cs_track_texture_print(&track->textures[u]);
2817 int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track)
2824 for (i = 0; i < track->num_cb; i++) {
2825 if (track->cb[i].robj == NULL) {
2826 DRM_ERROR("[drm] No buffer for color buffer %d !\n", i);
2829 size = track->cb[i].pitch * track->cb[i].cpp * track->maxy;
2830 size += track->cb[i].offset;
2831 if (size > radeon_object_size(track->cb[i].robj)) {
2832 DRM_ERROR("[drm] Buffer too small for color buffer %d "
2833 "(need %lu have %lu) !\n", i, size,
2834 radeon_object_size(track->cb[i].robj));
2835 DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n",
2836 i, track->cb[i].pitch, track->cb[i].cpp,
2837 track->cb[i].offset, track->maxy);
2841 if (track->z_enabled) {
2842 if (track->zb.robj == NULL) {
2843 DRM_ERROR("[drm] No buffer for z buffer !\n");
2846 size = track->zb.pitch * track->zb.cpp * track->maxy;
2847 size += track->zb.offset;
2848 if (size > radeon_object_size(track->zb.robj)) {
2849 DRM_ERROR("[drm] Buffer too small for z buffer "
2850 "(need %lu have %lu) !\n", size,
2851 radeon_object_size(track->zb.robj));
2852 DRM_ERROR("[drm] zbuffer (%u %u %u %u)\n",
2853 track->zb.pitch, track->zb.cpp,
2854 track->zb.offset, track->maxy);
2858 prim_walk = (track->vap_vf_cntl >> 4) & 0x3;
2859 nverts = (track->vap_vf_cntl >> 16) & 0xFFFF;
2860 switch (prim_walk) {
2862 for (i = 0; i < track->num_arrays; i++) {
2863 size = track->arrays[i].esize * track->max_indx * 4;
2864 if (track->arrays[i].robj == NULL) {
2865 DRM_ERROR("(PW %u) Vertex array %u no buffer "
2866 "bound\n", prim_walk, i);
2869 if (size > radeon_object_size(track->arrays[i].robj)) {
2870 DRM_ERROR("(PW %u) Vertex array %u need %lu dwords "
2871 "have %lu dwords\n", prim_walk, i,
2873 radeon_object_size(track->arrays[i].robj) >> 2);
2874 DRM_ERROR("Max indices %u\n", track->max_indx);
2880 for (i = 0; i < track->num_arrays; i++) {
2881 size = track->arrays[i].esize * (nverts - 1) * 4;
2882 if (track->arrays[i].robj == NULL) {
2883 DRM_ERROR("(PW %u) Vertex array %u no buffer "
2884 "bound\n", prim_walk, i);
2887 if (size > radeon_object_size(track->arrays[i].robj)) {
2888 DRM_ERROR("(PW %u) Vertex array %u need %lu dwords "
2889 "have %lu dwords\n", prim_walk, i, size >> 2,
2890 radeon_object_size(track->arrays[i].robj) >> 2);
2896 size = track->vtx_size * nverts;
2897 if (size != track->immd_dwords) {
2898 DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n",
2899 track->immd_dwords, size);
2900 DRM_ERROR("VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n",
2901 nverts, track->vtx_size);
2906 DRM_ERROR("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n",
2910 return r100_cs_track_texture_check(rdev, track);
2913 void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track)
2917 if (rdev->family < CHIP_R300) {
2919 if (rdev->family <= CHIP_RS200)
2920 track->num_texture = 3;
2922 track->num_texture = 6;
2924 track->separate_cube = 1;
2927 track->num_texture = 16;
2929 track->separate_cube = 0;
2932 for (i = 0; i < track->num_cb; i++) {
2933 track->cb[i].robj = NULL;
2934 track->cb[i].pitch = 8192;
2935 track->cb[i].cpp = 16;
2936 track->cb[i].offset = 0;
2938 track->z_enabled = true;
2939 track->zb.robj = NULL;
2940 track->zb.pitch = 8192;
2942 track->zb.offset = 0;
2943 track->vtx_size = 0x7F;
2944 track->immd_dwords = 0xFFFFFFFFUL;
2945 track->num_arrays = 11;
2946 track->max_indx = 0x00FFFFFFUL;
2947 for (i = 0; i < track->num_arrays; i++) {
2948 track->arrays[i].robj = NULL;
2949 track->arrays[i].esize = 0x7F;
2951 for (i = 0; i < track->num_texture; i++) {
2952 track->textures[i].pitch = 16536;
2953 track->textures[i].width = 16536;
2954 track->textures[i].height = 16536;
2955 track->textures[i].width_11 = 1 << 11;
2956 track->textures[i].height_11 = 1 << 11;
2957 track->textures[i].num_levels = 12;
2958 if (rdev->family <= CHIP_RS200) {
2959 track->textures[i].tex_coord_type = 0;
2960 track->textures[i].txdepth = 0;
2962 track->textures[i].txdepth = 16;
2963 track->textures[i].tex_coord_type = 1;
2965 track->textures[i].cpp = 64;
2966 track->textures[i].robj = NULL;
2967 /* CS IB emission code makes sure texture unit are disabled */
2968 track->textures[i].enabled = false;
2969 track->textures[i].roundup_w = true;
2970 track->textures[i].roundup_h = true;
2971 if (track->separate_cube)
2972 for (face = 0; face < 5; face++) {
2973 track->textures[i].cube_info[face].robj = NULL;
2974 track->textures[i].cube_info[face].width = 16536;
2975 track->textures[i].cube_info[face].height = 16536;
2976 track->textures[i].cube_info[face].offset = 0;
2981 int r100_ring_test(struct radeon_device *rdev)
2988 r = radeon_scratch_get(rdev, &scratch);
2990 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
2993 WREG32(scratch, 0xCAFEDEAD);
2994 r = radeon_ring_lock(rdev, 2);
2996 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
2997 radeon_scratch_free(rdev, scratch);
3000 radeon_ring_write(rdev, PACKET0(scratch, 0));
3001 radeon_ring_write(rdev, 0xDEADBEEF);
3002 radeon_ring_unlock_commit(rdev);
3003 for (i = 0; i < rdev->usec_timeout; i++) {
3004 tmp = RREG32(scratch);
3005 if (tmp == 0xDEADBEEF) {
3010 if (i < rdev->usec_timeout) {
3011 DRM_INFO("ring test succeeded in %d usecs\n", i);
3013 DRM_ERROR("radeon: ring test failed (sracth(0x%04X)=0x%08X)\n",
3017 radeon_scratch_free(rdev, scratch);
3021 void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
3023 radeon_ring_write(rdev, PACKET0(RADEON_CP_IB_BASE, 1));
3024 radeon_ring_write(rdev, ib->gpu_addr);
3025 radeon_ring_write(rdev, ib->length_dw);
3028 int r100_ib_test(struct radeon_device *rdev)
3030 struct radeon_ib *ib;
3036 r = radeon_scratch_get(rdev, &scratch);
3038 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
3041 WREG32(scratch, 0xCAFEDEAD);
3042 r = radeon_ib_get(rdev, &ib);
3046 ib->ptr[0] = PACKET0(scratch, 0);
3047 ib->ptr[1] = 0xDEADBEEF;
3048 ib->ptr[2] = PACKET2(0);
3049 ib->ptr[3] = PACKET2(0);
3050 ib->ptr[4] = PACKET2(0);
3051 ib->ptr[5] = PACKET2(0);
3052 ib->ptr[6] = PACKET2(0);
3053 ib->ptr[7] = PACKET2(0);
3055 r = radeon_ib_schedule(rdev, ib);
3057 radeon_scratch_free(rdev, scratch);
3058 radeon_ib_free(rdev, &ib);
3061 r = radeon_fence_wait(ib->fence, false);
3065 for (i = 0; i < rdev->usec_timeout; i++) {
3066 tmp = RREG32(scratch);
3067 if (tmp == 0xDEADBEEF) {
3072 if (i < rdev->usec_timeout) {
3073 DRM_INFO("ib test succeeded in %u usecs\n", i);
3075 DRM_ERROR("radeon: ib test failed (sracth(0x%04X)=0x%08X)\n",
3079 radeon_scratch_free(rdev, scratch);
3080 radeon_ib_free(rdev, &ib);
3084 void r100_ib_fini(struct radeon_device *rdev)
3086 radeon_ib_pool_fini(rdev);
3089 int r100_ib_init(struct radeon_device *rdev)
3093 r = radeon_ib_pool_init(rdev);
3095 dev_err(rdev->dev, "failled initializing IB pool (%d).\n", r);
3099 r = r100_ib_test(rdev);
3101 dev_err(rdev->dev, "failled testing IB (%d).\n", r);
3108 void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save)
3110 /* Shutdown CP we shouldn't need to do that but better be safe than
3113 rdev->cp.ready = false;
3114 WREG32(R_000740_CP_CSQ_CNTL, 0);
3116 /* Save few CRTC registers */
3117 save->GENMO_WT = RREG32(R_0003C0_GENMO_WT);
3118 save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL);
3119 save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL);
3120 save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET);
3121 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3122 save->CRTC2_GEN_CNTL = RREG32(R_0003F8_CRTC2_GEN_CNTL);
3123 save->CUR2_OFFSET = RREG32(R_000360_CUR2_OFFSET);
3126 /* Disable VGA aperture access */
3127 WREG32(R_0003C0_GENMO_WT, C_0003C0_VGA_RAM_EN & save->GENMO_WT);
3128 /* Disable cursor, overlay, crtc */
3129 WREG32(R_000260_CUR_OFFSET, save->CUR_OFFSET | S_000260_CUR_LOCK(1));
3130 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL |
3131 S_000054_CRTC_DISPLAY_DIS(1));
3132 WREG32(R_000050_CRTC_GEN_CNTL,
3133 (C_000050_CRTC_CUR_EN & save->CRTC_GEN_CNTL) |
3134 S_000050_CRTC_DISP_REQ_EN_B(1));
3135 WREG32(R_000420_OV0_SCALE_CNTL,
3136 C_000420_OV0_OVERLAY_EN & RREG32(R_000420_OV0_SCALE_CNTL));
3137 WREG32(R_000260_CUR_OFFSET, C_000260_CUR_LOCK & save->CUR_OFFSET);
3138 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3139 WREG32(R_000360_CUR2_OFFSET, save->CUR2_OFFSET |
3140 S_000360_CUR2_LOCK(1));
3141 WREG32(R_0003F8_CRTC2_GEN_CNTL,
3142 (C_0003F8_CRTC2_CUR_EN & save->CRTC2_GEN_CNTL) |
3143 S_0003F8_CRTC2_DISPLAY_DIS(1) |
3144 S_0003F8_CRTC2_DISP_REQ_EN_B(1));
3145 WREG32(R_000360_CUR2_OFFSET,
3146 C_000360_CUR2_LOCK & save->CUR2_OFFSET);
3150 void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save)
3152 /* Update base address for crtc */
3153 WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_location);
3154 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3155 WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR,
3156 rdev->mc.vram_location);
3158 /* Restore CRTC registers */
3159 WREG32(R_0003C0_GENMO_WT, save->GENMO_WT);
3160 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL);
3161 WREG32(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL);
3162 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3163 WREG32(R_0003F8_CRTC2_GEN_CNTL, save->CRTC2_GEN_CNTL);