drivers/gpu/drm/radeon/r100.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/seq_file.h>
  29 #include <linux/slab.h>
  30 #include "drmP.h"
  31 #include "drm.h"
  32 #include "radeon_drm.h"
  33 #include "radeon_reg.h"
  34 #include "radeon.h"
  35 #include "radeon_asic.h"
  36 #include "r100d.h"
  37 #include "rs100d.h"
  38 #include "rv200d.h"
  39 #include "rv250d.h"
  40 #include "atom.h"
  41
  42 #include <linux/firmware.h>
  43 #include <linux/platform_device.h>
  44 #include <linux/module.h>
  45
  46 #include "r100_reg_safe.h"
  47 #include "rn50_reg_safe.h"
  48
  49 /* Firmware Names */
  50 #define FIRMWARE_R100           "radeon/R100_cp.bin"
  51 #define FIRMWARE_R200           "radeon/R200_cp.bin"
  52 #define FIRMWARE_R300           "radeon/R300_cp.bin"
  53 #define FIRMWARE_R420           "radeon/R420_cp.bin"
  54 #define FIRMWARE_RS690          "radeon/RS690_cp.bin"
  55 #define FIRMWARE_RS600          "radeon/RS600_cp.bin"
  56 #define FIRMWARE_R520           "radeon/R520_cp.bin"
  57
  58 MODULE_FIRMWARE(FIRMWARE_R100);
  59 MODULE_FIRMWARE(FIRMWARE_R200);
  60 MODULE_FIRMWARE(FIRMWARE_R300);
  61 MODULE_FIRMWARE(FIRMWARE_R420);
  62 MODULE_FIRMWARE(FIRMWARE_RS690);
  63 MODULE_FIRMWARE(FIRMWARE_RS600);
  64 MODULE_FIRMWARE(FIRMWARE_R520);
  65
  66 #include "r100_track.h"
  67
  68 /* This files gather functions specifics to:
  69  * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
  70  */
  71
  72 int r100_reloc_pitch_offset(struct radeon_cs_parser *p,
  73                             struct radeon_cs_packet *pkt,
  74                             unsigned idx,
  75                             unsigned reg)
  76 {
  77         int r;
  78         u32 tile_flags = 0;
  79         u32 tmp;
  80         struct radeon_cs_reloc *reloc;
  81         u32 value;
  82
  83         r = r100_cs_packet_next_reloc(p, &reloc);
  84         if (r) {
  85                 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
  86                           idx, reg);
  87                 r100_cs_dump_packet(p, pkt);
  88                 return r;
  89         }
  90         value = radeon_get_ib_value(p, idx);
  91         tmp = value & 0x003fffff;
  92         tmp += (((u32)reloc->lobj.gpu_offset) >> 10);
  93
  94         if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
  95                 tile_flags |= RADEON_DST_TILE_MACRO;
  96         if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) {
  97                 if (reg == RADEON_SRC_PITCH_OFFSET) {
  98                         DRM_ERROR("Cannot src blit from microtiled surface\n");
  99                         r100_cs_dump_packet(p, pkt);
 100                         return -EINVAL;
 101                 }
 102                 tile_flags |= RADEON_DST_TILE_MICRO;
 103         }
 104
 105         tmp |= tile_flags;
 106         p->ib->ptr[idx] = (value & 0x3fc00000) | tmp;
 107         return 0;
 108 }
 109
 110 int r100_packet3_load_vbpntr(struct radeon_cs_parser *p,
 111                              struct radeon_cs_packet *pkt,
 112                              int idx)
 113 {
 114         unsigned c, i;
 115         struct radeon_cs_reloc *reloc;
 116         struct r100_cs_track *track;
 117         int r = 0;
 118         volatile uint32_t *ib;
 119         u32 idx_value;
 120
 121         ib = p->ib->ptr;
 122         track = (struct r100_cs_track *)p->track;
 123         c = radeon_get_ib_value(p, idx++) & 0x1F;
 124         if (c > 16) {
 125             DRM_ERROR("Only 16 vertex buffers are allowed %d\n",
 126                       pkt->opcode);
 127             r100_cs_dump_packet(p, pkt);
 128             return -EINVAL;
 129         }
 130         track->num_arrays = c;
 131         for (i = 0; i < (c - 1); i+=2, idx+=3) {
 132                 r = r100_cs_packet_next_reloc(p, &reloc);
 133                 if (r) {
 134                         DRM_ERROR("No reloc for packet3 %d\n",
 135                                   pkt->opcode);
 136                         r100_cs_dump_packet(p, pkt);
 137                         return r;
 138                 }
 139                 idx_value = radeon_get_ib_value(p, idx);
 140                 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset);
 141
 142                 track->arrays[i + 0].esize = idx_value >> 8;
 143                 track->arrays[i + 0].robj = reloc->robj;
 144                 track->arrays[i + 0].esize &= 0x7F;
 145                 r = r100_cs_packet_next_reloc(p, &reloc);
 146                 if (r) {
 147                         DRM_ERROR("No reloc for packet3 %d\n",
 148                                   pkt->opcode);
 149                         r100_cs_dump_packet(p, pkt);
 150                         return r;
 151                 }
 152                 ib[idx+2] = radeon_get_ib_value(p, idx + 2) + ((u32)reloc->lobj.gpu_offset);
 153                 track->arrays[i + 1].robj = reloc->robj;
 154                 track->arrays[i + 1].esize = idx_value >> 24;
 155                 track->arrays[i + 1].esize &= 0x7F;
 156         }
 157         if (c & 1) {
 158                 r = r100_cs_packet_next_reloc(p, &reloc);
 159                 if (r) {
 160                         DRM_ERROR("No reloc for packet3 %d\n",
 161                                           pkt->opcode);
 162                         r100_cs_dump_packet(p, pkt);
 163                         return r;
 164                 }
 165                 idx_value = radeon_get_ib_value(p, idx);
 166                 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset);
 167                 track->arrays[i + 0].robj = reloc->robj;
 168                 track->arrays[i + 0].esize = idx_value >> 8;
 169                 track->arrays[i + 0].esize &= 0x7F;
 170         }
 171         return r;
 172 }
 173
 174 void r100_pre_page_flip(struct radeon_device *rdev, int crtc)
 175 {
 176         /* enable the pflip int */
 177         radeon_irq_kms_pflip_irq_get(rdev, crtc);
 178 }
 179
 180 void r100_post_page_flip(struct radeon_device *rdev, int crtc)
 181 {
 182         /* disable the pflip int */
 183         radeon_irq_kms_pflip_irq_put(rdev, crtc);
 184 }
 185
 186 u32 r100_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
 187 {
 188         struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
 189         u32 tmp = ((u32)crtc_base) | RADEON_CRTC_OFFSET__OFFSET_LOCK;
 190         int i;
 191
 192         /* Lock the graphics update lock */
 193         /* update the scanout addresses */
 194         WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp);
 195
 196         /* Wait for update_pending to go high. */
 197         for (i = 0; i < rdev->usec_timeout; i++) {
 198                 if (RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET)
 199                         break;
 200                 udelay(1);
 201         }
 202         DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
 203
 204         /* Unlock the lock, so double-buffering can take place inside vblank */
 205         tmp &= ~RADEON_CRTC_OFFSET__OFFSET_LOCK;
 206         WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp);
 207
 208         /* Return current update_pending status: */
 209         return RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET;
 210 }
 211
 212 void r100_pm_get_dynpm_state(struct radeon_device *rdev)
 213 {
 214         int i;
 215         rdev->pm.dynpm_can_upclock = true;
 216         rdev->pm.dynpm_can_downclock = true;
 217
 218         switch (rdev->pm.dynpm_planned_action) {
 219         case DYNPM_ACTION_MINIMUM:
 220                 rdev->pm.requested_power_state_index = 0;
 221                 rdev->pm.dynpm_can_downclock = false;
 222                 break;
 223         case DYNPM_ACTION_DOWNCLOCK:
 224                 if (rdev->pm.current_power_state_index == 0) {
 225                         rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
 226                         rdev->pm.dynpm_can_downclock = false;
 227                 } else {
 228                         if (rdev->pm.active_crtc_count > 1) {
 229                                 for (i = 0; i < rdev->pm.num_power_states; i++) {
 230                                         if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
 231                                                 continue;
 232                                         else if (i >= rdev->pm.current_power_state_index) {
 233                                                 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
 234                                                 break;
 235                                         } else {
 236                                                 rdev->pm.requested_power_state_index = i;
 237                                                 break;
 238                                         }
 239                                 }
 240                         } else
 241                                 rdev->pm.requested_power_state_index =
 242                                         rdev->pm.current_power_state_index - 1;
 243                 }
 244                 /* don't use the power state if crtcs are active and no display flag is set */
 245                 if ((rdev->pm.active_crtc_count > 0) &&
 246                     (rdev->pm.power_state[rdev->pm.requested_power_state_index].clock_info[0].flags &
 247                      RADEON_PM_MODE_NO_DISPLAY)) {
 248                         rdev->pm.requested_power_state_index++;
 249                 }
 250                 break;
 251         case DYNPM_ACTION_UPCLOCK:
 252                 if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) {
 253                         rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
 254                         rdev->pm.dynpm_can_upclock = false;
 255                 } else {
 256                         if (rdev->pm.active_crtc_count > 1) {
 257                                 for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) {
 258                                         if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
 259                                                 continue;
 260                                         else if (i <= rdev->pm.current_power_state_index) {
 261                                                 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
 262                                                 break;
 263                                         } else {
 264                                                 rdev->pm.requested_power_state_index = i;
 265                                                 break;
 266                                         }
 267                                 }
 268                         } else
 269                                 rdev->pm.requested_power_state_index =
 270                                         rdev->pm.current_power_state_index + 1;
 271                 }
 272                 break;
 273         case DYNPM_ACTION_DEFAULT:
 274                 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
 275                 rdev->pm.dynpm_can_upclock = false;
 276                 break;
 277         case DYNPM_ACTION_NONE:
 278         default:
 279                 DRM_ERROR("Requested mode for not defined action\n");
 280                 return;
 281         }
 282         /* only one clock mode per power state */
 283         rdev->pm.requested_clock_mode_index = 0;
 284
 285         DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n",
 286                   rdev->pm.power_state[rdev->pm.requested_power_state_index].
 287                   clock_info[rdev->pm.requested_clock_mode_index].sclk,
 288                   rdev->pm.power_state[rdev->pm.requested_power_state_index].
 289                   clock_info[rdev->pm.requested_clock_mode_index].mclk,
 290                   rdev->pm.power_state[rdev->pm.requested_power_state_index].
 291                   pcie_lanes);
 292 }
 293
 294 void r100_pm_init_profile(struct radeon_device *rdev)
 295 {
 296         /* default */
 297         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 298         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 299         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 300         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
 301         /* low sh */
 302         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0;
 303         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0;
 304         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 305         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 306         /* mid sh */
 307         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0;
 308         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0;
 309         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 310         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
 311         /* high sh */
 312         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0;
 313         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 314         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 315         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
 316         /* low mh */
 317         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0;
 318         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 319         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 320         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 321         /* mid mh */
 322         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0;
 323         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 324         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 325         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
 326         /* high mh */
 327         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0;
 328         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 329         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 330         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
 331 }
 332
 333 void r100_pm_misc(struct radeon_device *rdev)
 334 {
 335         int requested_index = rdev->pm.requested_power_state_index;
 336         struct radeon_power_state *ps = &rdev->pm.power_state[requested_index];
 337         struct radeon_voltage *voltage = &ps->clock_info[0].voltage;
 338         u32 tmp, sclk_cntl, sclk_cntl2, sclk_more_cntl;
 339
 340         if ((voltage->type == VOLTAGE_GPIO) && (voltage->gpio.valid)) {
 341                 if (ps->misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) {
 342                         tmp = RREG32(voltage->gpio.reg);
 343                         if (voltage->active_high)
 344                                 tmp |= voltage->gpio.mask;
 345                         else
 346                                 tmp &= ~(voltage->gpio.mask);
 347                         WREG32(voltage->gpio.reg, tmp);
 348                         if (voltage->delay)
 349                                 udelay(voltage->delay);
 350                 } else {
 351                         tmp = RREG32(voltage->gpio.reg);
 352                         if (voltage->active_high)
 353                                 tmp &= ~voltage->gpio.mask;
 354                         else
 355                                 tmp |= voltage->gpio.mask;
 356                         WREG32(voltage->gpio.reg, tmp);
 357                         if (voltage->delay)
 358                                 udelay(voltage->delay);
 359                 }
 360         }
 361
 362         sclk_cntl = RREG32_PLL(SCLK_CNTL);
 363         sclk_cntl2 = RREG32_PLL(SCLK_CNTL2);
 364         sclk_cntl2 &= ~REDUCED_SPEED_SCLK_SEL(3);
 365         sclk_more_cntl = RREG32_PLL(SCLK_MORE_CNTL);
 366         sclk_more_cntl &= ~VOLTAGE_DELAY_SEL(3);
 367         if (ps->misc & ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN) {
 368                 sclk_more_cntl |= REDUCED_SPEED_SCLK_EN;
 369                 if (ps->misc & ATOM_PM_MISCINFO_DYN_CLK_3D_IDLE)
 370                         sclk_cntl2 |= REDUCED_SPEED_SCLK_MODE;
 371                 else
 372                         sclk_cntl2 &= ~REDUCED_SPEED_SCLK_MODE;
 373                 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2)
 374                         sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(0);
 375                 else if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4)
 376                         sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(2);
 377         } else
 378                 sclk_more_cntl &= ~REDUCED_SPEED_SCLK_EN;
 379
 380         if (ps->misc & ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN) {
 381                 sclk_more_cntl |= IO_CG_VOLTAGE_DROP;
 382                 if (voltage->delay) {
 383                         sclk_more_cntl |= VOLTAGE_DROP_SYNC;
 384                         switch (voltage->delay) {
 385                         case 33:
 386                                 sclk_more_cntl |= VOLTAGE_DELAY_SEL(0);
 387                                 break;
 388                         case 66:
 389                                 sclk_more_cntl |= VOLTAGE_DELAY_SEL(1);
 390                                 break;
 391                         case 99:
 392                                 sclk_more_cntl |= VOLTAGE_DELAY_SEL(2);
 393                                 break;
 394                         case 132:
 395                                 sclk_more_cntl |= VOLTAGE_DELAY_SEL(3);
 396                                 break;
 397                         }
 398                 } else
 399                         sclk_more_cntl &= ~VOLTAGE_DROP_SYNC;
 400         } else
 401                 sclk_more_cntl &= ~IO_CG_VOLTAGE_DROP;
 402
 403         if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN)
 404                 sclk_cntl &= ~FORCE_HDP;
 405         else
 406                 sclk_cntl |= FORCE_HDP;
 407
 408         WREG32_PLL(SCLK_CNTL, sclk_cntl);
 409         WREG32_PLL(SCLK_CNTL2, sclk_cntl2);
 410         WREG32_PLL(SCLK_MORE_CNTL, sclk_more_cntl);
 411
 412         /* set pcie lanes */
 413         if ((rdev->flags & RADEON_IS_PCIE) &&
 414             !(rdev->flags & RADEON_IS_IGP) &&
 415             rdev->asic->set_pcie_lanes &&
 416             (ps->pcie_lanes !=
 417              rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) {
 418                 radeon_set_pcie_lanes(rdev,
 419                                       ps->pcie_lanes);
 420                 DRM_DEBUG_DRIVER("Setting: p: %d\n", ps->pcie_lanes);
 421         }
 422 }
 423
 424 void r100_pm_prepare(struct radeon_device *rdev)
 425 {
 426         struct drm_device *ddev = rdev->ddev;
 427         struct drm_crtc *crtc;
 428         struct radeon_crtc *radeon_crtc;
 429         u32 tmp;
 430
 431         /* disable any active CRTCs */
 432         list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
 433                 radeon_crtc = to_radeon_crtc(crtc);
 434                 if (radeon_crtc->enabled) {
 435                         if (radeon_crtc->crtc_id) {
 436                                 tmp = RREG32(RADEON_CRTC2_GEN_CNTL);
 437                                 tmp |= RADEON_CRTC2_DISP_REQ_EN_B;
 438                                 WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
 439                         } else {
 440                                 tmp = RREG32(RADEON_CRTC_GEN_CNTL);
 441                                 tmp |= RADEON_CRTC_DISP_REQ_EN_B;
 442                                 WREG32(RADEON_CRTC_GEN_CNTL, tmp);
 443                         }
 444                 }
 445         }
 446 }
 447
 448 void r100_pm_finish(struct radeon_device *rdev)
 449 {
 450         struct drm_device *ddev = rdev->ddev;
 451         struct drm_crtc *crtc;
 452         struct radeon_crtc *radeon_crtc;
 453         u32 tmp;
 454
 455         /* enable any active CRTCs */
 456         list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
 457                 radeon_crtc = to_radeon_crtc(crtc);
 458                 if (radeon_crtc->enabled) {
 459                         if (radeon_crtc->crtc_id) {
 460                                 tmp = RREG32(RADEON_CRTC2_GEN_CNTL);
 461                                 tmp &= ~RADEON_CRTC2_DISP_REQ_EN_B;
 462                                 WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
 463                         } else {
 464                                 tmp = RREG32(RADEON_CRTC_GEN_CNTL);
 465                                 tmp &= ~RADEON_CRTC_DISP_REQ_EN_B;
 466                                 WREG32(RADEON_CRTC_GEN_CNTL, tmp);
 467                         }
 468                 }
 469         }
 470 }
 471
 472 bool r100_gui_idle(struct radeon_device *rdev)
 473 {
 474         if (RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_ACTIVE)
 475                 return false;
 476         else
 477                 return true;
 478 }
 479
 480 /* hpd for digital panel detect/disconnect */
 481 bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
 482 {
 483         bool connected = false;
 484
 485         switch (hpd) {
 486         case RADEON_HPD_1:
 487                 if (RREG32(RADEON_FP_GEN_CNTL) & RADEON_FP_DETECT_SENSE)
 488                         connected = true;
 489                 break;
 490         case RADEON_HPD_2:
 491                 if (RREG32(RADEON_FP2_GEN_CNTL) & RADEON_FP2_DETECT_SENSE)
 492                         connected = true;
 493                 break;
 494         default:
 495                 break;
 496         }
 497         return connected;
 498 }
 499
 500 void r100_hpd_set_polarity(struct radeon_device *rdev,
 501                            enum radeon_hpd_id hpd)
 502 {
 503         u32 tmp;
 504         bool connected = r100_hpd_sense(rdev, hpd);
 505
 506         switch (hpd) {
 507         case RADEON_HPD_1:
 508                 tmp = RREG32(RADEON_FP_GEN_CNTL);
 509                 if (connected)
 510                         tmp &= ~RADEON_FP_DETECT_INT_POL;
 511                 else
 512                         tmp |= RADEON_FP_DETECT_INT_POL;
 513                 WREG32(RADEON_FP_GEN_CNTL, tmp);
 514                 break;
 515         case RADEON_HPD_2:
 516                 tmp = RREG32(RADEON_FP2_GEN_CNTL);
 517                 if (connected)
 518                         tmp &= ~RADEON_FP2_DETECT_INT_POL;
 519                 else
 520                         tmp |= RADEON_FP2_DETECT_INT_POL;
 521                 WREG32(RADEON_FP2_GEN_CNTL, tmp);
 522                 break;
 523         default:
 524                 break;
 525         }
 526 }
 527
 528 void r100_hpd_init(struct radeon_device *rdev)
 529 {
 530         struct drm_device *dev = rdev->ddev;
 531         struct drm_connector *connector;
 532
 533         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 534                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 535                 switch (radeon_connector->hpd.hpd) {
 536                 case RADEON_HPD_1:
 537                         rdev->irq.hpd[0] = true;
 538                         break;
 539                 case RADEON_HPD_2:
 540                         rdev->irq.hpd[1] = true;
 541                         break;
 542                 default:
 543                         break;
 544                 }
 545                 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
 546         }
 547         if (rdev->irq.installed)
 548                 r100_irq_set(rdev);
 549 }
 550
 551 void r100_hpd_fini(struct radeon_device *rdev)
 552 {
 553         struct drm_device *dev = rdev->ddev;
 554         struct drm_connector *connector;
 555
 556         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 557                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 558                 switch (radeon_connector->hpd.hpd) {
 559                 case RADEON_HPD_1:
 560                         rdev->irq.hpd[0] = false;
 561                         break;
 562                 case RADEON_HPD_2:
 563                         rdev->irq.hpd[1] = false;
 564                         break;
 565                 default:
 566                         break;
 567                 }
 568         }
 569 }
 570
 571 /*
 572  * PCI GART
 573  */
 574 void r100_pci_gart_tlb_flush(struct radeon_device *rdev)
 575 {
 576         /* TODO: can we do somethings here ? */
 577         /* It seems hw only cache one entry so we should discard this
 578          * entry otherwise if first GPU GART read hit this entry it
 579          * could end up in wrong address. */
 580 }
 581
 582 int r100_pci_gart_init(struct radeon_device *rdev)
 583 {
 584         int r;
 585
 586         if (rdev->gart.ptr) {
 587                 WARN(1, "R100 PCI GART already initialized\n");
 588                 return 0;
 589         }
 590         /* Initialize common gart structure */
 591         r = radeon_gart_init(rdev);
 592         if (r)
 593                 return r;
 594         rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
 595         rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush;
 596         rdev->asic->gart_set_page = &r100_pci_gart_set_page;
 597         return radeon_gart_table_ram_alloc(rdev);
 598 }
 599
 600 /* required on r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
 601 void r100_enable_bm(struct radeon_device *rdev)
 602 {
 603         uint32_t tmp;
 604         /* Enable bus mastering */
 605         tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
 606         WREG32(RADEON_BUS_CNTL, tmp);
 607 }
 608
 609 int r100_pci_gart_enable(struct radeon_device *rdev)
 610 {
 611         uint32_t tmp;
 612
 613         radeon_gart_restore(rdev);
 614         /* discard memory request outside of configured range */
 615         tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
 616         WREG32(RADEON_AIC_CNTL, tmp);
 617         /* set address range for PCI address translate */
 618         WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_start);
 619         WREG32(RADEON_AIC_HI_ADDR, rdev->mc.gtt_end);
 620         /* set PCI GART page-table base address */
 621         WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr);
 622         tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN;
 623         WREG32(RADEON_AIC_CNTL, tmp);
 624         r100_pci_gart_tlb_flush(rdev);
 625         DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
 626                  (unsigned)(rdev->mc.gtt_size >> 20),
 627                  (unsigned long long)rdev->gart.table_addr);
 628         rdev->gart.ready = true;
 629         return 0;
 630 }
 631
 632 void r100_pci_gart_disable(struct radeon_device *rdev)
 633 {
 634         uint32_t tmp;
 635
 636         /* discard memory request outside of configured range */
 637         tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
 638         WREG32(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN);
 639         WREG32(RADEON_AIC_LO_ADDR, 0);
 640         WREG32(RADEON_AIC_HI_ADDR, 0);
 641 }
 642
 643 int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
 644 {
 645         u32 *gtt = rdev->gart.ptr;
 646
 647         if (i < 0 || i > rdev->gart.num_gpu_pages) {
 648                 return -EINVAL;
 649         }
 650         gtt[i] = cpu_to_le32(lower_32_bits(addr));
 651         return 0;
 652 }
 653
 654 void r100_pci_gart_fini(struct radeon_device *rdev)
 655 {
 656         radeon_gart_fini(rdev);
 657         r100_pci_gart_disable(rdev);
 658         radeon_gart_table_ram_free(rdev);
 659 }
 660
 661 int r100_irq_set(struct radeon_device *rdev)
 662 {
 663         uint32_t tmp = 0;
 664
 665         if (!rdev->irq.installed) {
 666                 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
 667                 WREG32(R_000040_GEN_INT_CNTL, 0);
 668                 return -EINVAL;
 669         }
 670         if (rdev->irq.sw_int) {
 671                 tmp |= RADEON_SW_INT_ENABLE;
 672         }
 673         if (rdev->irq.gui_idle) {
 674                 tmp |= RADEON_GUI_IDLE_MASK;
 675         }
 676         if (rdev->irq.crtc_vblank_int[0] ||
 677             rdev->irq.pflip[0]) {
 678                 tmp |= RADEON_CRTC_VBLANK_MASK;
 679         }
 680         if (rdev->irq.crtc_vblank_int[1] ||
 681             rdev->irq.pflip[1]) {
 682                 tmp |= RADEON_CRTC2_VBLANK_MASK;
 683         }
 684         if (rdev->irq.hpd[0]) {
 685                 tmp |= RADEON_FP_DETECT_MASK;
 686         }
 687         if (rdev->irq.hpd[1]) {
 688                 tmp |= RADEON_FP2_DETECT_MASK;
 689         }
 690         WREG32(RADEON_GEN_INT_CNTL, tmp);
 691         return 0;
 692 }
 693
 694 void r100_irq_disable(struct radeon_device *rdev)
 695 {
 696         u32 tmp;
 697
 698         WREG32(R_000040_GEN_INT_CNTL, 0);
 699         /* Wait and acknowledge irq */
 700         mdelay(1);
 701         tmp = RREG32(R_000044_GEN_INT_STATUS);
 702         WREG32(R_000044_GEN_INT_STATUS, tmp);
 703 }
 704
 705 static uint32_t r100_irq_ack(struct radeon_device *rdev)
 706 {
 707         uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS);
 708         uint32_t irq_mask = RADEON_SW_INT_TEST |
 709                 RADEON_CRTC_VBLANK_STAT | RADEON_CRTC2_VBLANK_STAT |
 710                 RADEON_FP_DETECT_STAT | RADEON_FP2_DETECT_STAT;
 711
 712         /* the interrupt works, but the status bit is permanently asserted */
 713         if (rdev->irq.gui_idle && radeon_gui_idle(rdev)) {
 714                 if (!rdev->irq.gui_idle_acked)
 715                         irq_mask |= RADEON_GUI_IDLE_STAT;
 716         }
 717
 718         if (irqs) {
 719                 WREG32(RADEON_GEN_INT_STATUS, irqs);
 720         }
 721         return irqs & irq_mask;
 722 }
 723
 724 int r100_irq_process(struct radeon_device *rdev)
 725 {
 726         uint32_t status, msi_rearm;
 727         bool queue_hotplug = false;
 728
 729         /* reset gui idle ack.  the status bit is broken */
 730         rdev->irq.gui_idle_acked = false;
 731
 732         status = r100_irq_ack(rdev);
 733         if (!status) {
 734                 return IRQ_NONE;
 735         }
 736         if (rdev->shutdown) {
 737                 return IRQ_NONE;
 738         }
 739         while (status) {
 740                 /* SW interrupt */
 741                 if (status & RADEON_SW_INT_TEST) {
 742                         radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
 743                 }
 744                 /* gui idle interrupt */
 745                 if (status & RADEON_GUI_IDLE_STAT) {
 746                         rdev->irq.gui_idle_acked = true;
 747                         rdev->pm.gui_idle = true;
 748                         wake_up(&rdev->irq.idle_queue);
 749                 }
 750                 /* Vertical blank interrupts */
 751                 if (status & RADEON_CRTC_VBLANK_STAT) {
 752                         if (rdev->irq.crtc_vblank_int[0]) {
 753                                 drm_handle_vblank(rdev->ddev, 0);
 754                                 rdev->pm.vblank_sync = true;
 755                                 wake_up(&rdev->irq.vblank_queue);
 756                         }
 757                         if (rdev->irq.pflip[0])
 758                                 radeon_crtc_handle_flip(rdev, 0);
 759                 }
 760                 if (status & RADEON_CRTC2_VBLANK_STAT) {
 761                         if (rdev->irq.crtc_vblank_int[1]) {
 762                                 drm_handle_vblank(rdev->ddev, 1);
 763                                 rdev->pm.vblank_sync = true;
 764                                 wake_up(&rdev->irq.vblank_queue);
 765                         }
 766                         if (rdev->irq.pflip[1])
 767                                 radeon_crtc_handle_flip(rdev, 1);
 768                 }
 769                 if (status & RADEON_FP_DETECT_STAT) {
 770                         queue_hotplug = true;
 771                         DRM_DEBUG("HPD1\n");
 772                 }
 773                 if (status & RADEON_FP2_DETECT_STAT) {
 774                         queue_hotplug = true;
 775                         DRM_DEBUG("HPD2\n");
 776                 }
 777                 status = r100_irq_ack(rdev);
 778         }
 779         /* reset gui idle ack.  the status bit is broken */
 780         rdev->irq.gui_idle_acked = false;
 781         if (queue_hotplug)
 782                 schedule_work(&rdev->hotplug_work);
 783         if (rdev->msi_enabled) {
 784                 switch (rdev->family) {
 785                 case CHIP_RS400:
 786                 case CHIP_RS480:
 787                         msi_rearm = RREG32(RADEON_AIC_CNTL) & ~RS400_MSI_REARM;
 788                         WREG32(RADEON_AIC_CNTL, msi_rearm);
 789                         WREG32(RADEON_AIC_CNTL, msi_rearm | RS400_MSI_REARM);
 790                         break;
 791                 default:
 792                         msi_rearm = RREG32(RADEON_MSI_REARM_EN) & ~RV370_MSI_REARM_EN;
 793                         WREG32(RADEON_MSI_REARM_EN, msi_rearm);
 794                         WREG32(RADEON_MSI_REARM_EN, msi_rearm | RV370_MSI_REARM_EN);
 795                         break;
 796                 }
 797         }
 798         return IRQ_HANDLED;
 799 }
 800
 801 u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc)
 802 {
 803         if (crtc == 0)
 804                 return RREG32(RADEON_CRTC_CRNT_FRAME);
 805         else
 806                 return RREG32(RADEON_CRTC2_CRNT_FRAME);
 807 }
 808
 809 /* Who ever call radeon_fence_emit should call ring_lock and ask
 810  * for enough space (today caller are ib schedule and buffer move) */
 811 void r100_fence_ring_emit(struct radeon_device *rdev,
 812                           struct radeon_fence *fence)
 813 {
 814         struct radeon_cp *cp = &rdev->cp;
 815
 816         /* We have to make sure that caches are flushed before
 817          * CPU might read something from VRAM. */
 818         radeon_ring_write(cp, PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0));
 819         radeon_ring_write(cp, RADEON_RB3D_DC_FLUSH_ALL);
 820         radeon_ring_write(cp, PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0));
 821         radeon_ring_write(cp, RADEON_RB3D_ZC_FLUSH_ALL);
 822         /* Wait until IDLE & CLEAN */
 823         radeon_ring_write(cp, PACKET0(RADEON_WAIT_UNTIL, 0));
 824         radeon_ring_write(cp, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN);
 825         radeon_ring_write(cp, PACKET0(RADEON_HOST_PATH_CNTL, 0));
 826         radeon_ring_write(cp, rdev->config.r100.hdp_cntl |
 827                                 RADEON_HDP_READ_BUFFER_INVALIDATE);
 828         radeon_ring_write(cp, PACKET0(RADEON_HOST_PATH_CNTL, 0));
 829         radeon_ring_write(cp, rdev->config.r100.hdp_cntl);
 830         /* Emit fence sequence & fire IRQ */
 831         radeon_ring_write(cp, PACKET0(rdev->fence_drv[fence->ring].scratch_reg, 0));
 832         radeon_ring_write(cp, fence->seq);
 833         radeon_ring_write(cp, PACKET0(RADEON_GEN_INT_STATUS, 0));
 834         radeon_ring_write(cp, RADEON_SW_INT_FIRE);
 835 }
 836
 837 void r100_semaphore_ring_emit(struct radeon_device *rdev,
 838                               struct radeon_cp *cp,
 839                               struct radeon_semaphore *semaphore,
 840                               bool emit_wait)
 841 {
 842         /* Unused on older asics, since we don't have semaphores or multiple rings */
 843         BUG();
 844 }
 845
 846 int r100_copy_blit(struct radeon_device *rdev,
 847                    uint64_t src_offset,
 848                    uint64_t dst_offset,
 849                    unsigned num_gpu_pages,
 850                    struct radeon_fence *fence)
 851 {
 852         struct radeon_cp *cp = &rdev->cp;
 853         uint32_t cur_pages;
 854         uint32_t stride_bytes = RADEON_GPU_PAGE_SIZE;
 855         uint32_t pitch;
 856         uint32_t stride_pixels;
 857         unsigned ndw;
 858         int num_loops;
 859         int r = 0;
 860
 861         /* radeon limited to 16k stride */
 862         stride_bytes &= 0x3fff;
 863         /* radeon pitch is /64 */
 864         pitch = stride_bytes / 64;
 865         stride_pixels = stride_bytes / 4;
 866         num_loops = DIV_ROUND_UP(num_gpu_pages, 8191);
 867
 868         /* Ask for enough room for blit + flush + fence */
 869         ndw = 64 + (10 * num_loops);
 870         r = radeon_ring_lock(rdev, cp, ndw);
 871         if (r) {
 872                 DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw);
 873                 return -EINVAL;
 874         }
 875         while (num_gpu_pages > 0) {
 876                 cur_pages = num_gpu_pages;
 877                 if (cur_pages > 8191) {
 878                         cur_pages = 8191;
 879                 }
 880                 num_gpu_pages -= cur_pages;
 881
 882                 /* pages are in Y direction - height
 883                    page width in X direction - width */
 884                 radeon_ring_write(cp, PACKET3(PACKET3_BITBLT_MULTI, 8));
 885                 radeon_ring_write(cp,
 886                                   RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
 887                                   RADEON_GMC_DST_PITCH_OFFSET_CNTL |
 888                                   RADEON_GMC_SRC_CLIPPING |
 889                                   RADEON_GMC_DST_CLIPPING |
 890                                   RADEON_GMC_BRUSH_NONE |
 891                                   (RADEON_COLOR_FORMAT_ARGB8888 << 8) |
 892                                   RADEON_GMC_SRC_DATATYPE_COLOR |
 893                                   RADEON_ROP3_S |
 894                                   RADEON_DP_SRC_SOURCE_MEMORY |
 895                                   RADEON_GMC_CLR_CMP_CNTL_DIS |
 896                                   RADEON_GMC_WR_MSK_DIS);
 897                 radeon_ring_write(cp, (pitch << 22) | (src_offset >> 10));
 898                 radeon_ring_write(cp, (pitch << 22) | (dst_offset >> 10));
 899                 radeon_ring_write(cp, (0x1fff) | (0x1fff << 16));
 900                 radeon_ring_write(cp, 0);
 901                 radeon_ring_write(cp, (0x1fff) | (0x1fff << 16));
 902                 radeon_ring_write(cp, num_gpu_pages);
 903                 radeon_ring_write(cp, num_gpu_pages);
 904                 radeon_ring_write(cp, cur_pages | (stride_pixels << 16));
 905         }
 906         radeon_ring_write(cp, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0));
 907         radeon_ring_write(cp, RADEON_RB2D_DC_FLUSH_ALL);
 908         radeon_ring_write(cp, PACKET0(RADEON_WAIT_UNTIL, 0));
 909         radeon_ring_write(cp,
 910                           RADEON_WAIT_2D_IDLECLEAN |
 911                           RADEON_WAIT_HOST_IDLECLEAN |
 912                           RADEON_WAIT_DMA_GUI_IDLE);
 913         if (fence) {
 914                 r = radeon_fence_emit(rdev, fence);
 915         }
 916         radeon_ring_unlock_commit(rdev, cp);
 917         return r;
 918 }
 919
 920 static int r100_cp_wait_for_idle(struct radeon_device *rdev)
 921 {
 922         unsigned i;
 923         u32 tmp;
 924
 925         for (i = 0; i < rdev->usec_timeout; i++) {
 926                 tmp = RREG32(R_000E40_RBBM_STATUS);
 927                 if (!G_000E40_CP_CMDSTRM_BUSY(tmp)) {
 928                         return 0;
 929                 }
 930                 udelay(1);
 931         }
 932         return -1;
 933 }
 934
 935 void r100_ring_start(struct radeon_device *rdev)
 936 {
 937         struct radeon_cp *cp = &rdev->cp;
 938         int r;
 939
 940         r = radeon_ring_lock(rdev, cp, 2);
 941         if (r) {
 942                 return;
 943         }
 944         radeon_ring_write(cp, PACKET0(RADEON_ISYNC_CNTL, 0));
 945         radeon_ring_write(cp,
 946                           RADEON_ISYNC_ANY2D_IDLE3D |
 947                           RADEON_ISYNC_ANY3D_IDLE2D |
 948                           RADEON_ISYNC_WAIT_IDLEGUI |
 949                           RADEON_ISYNC_CPSCRATCH_IDLEGUI);
 950         radeon_ring_unlock_commit(rdev, cp);
 951 }
 952
 953
 954 /* Load the microcode for the CP */
 955 static int r100_cp_init_microcode(struct radeon_device *rdev)
 956 {
 957         struct platform_device *pdev;
 958         const char *fw_name = NULL;
 959         int err;
 960
 961         DRM_DEBUG_KMS("\n");
 962
 963         pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
 964         err = IS_ERR(pdev);
 965         if (err) {
 966                 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
 967                 return -EINVAL;
 968         }
 969         if ((rdev->family == CHIP_R100) || (rdev->family == CHIP_RV100) ||
 970             (rdev->family == CHIP_RV200) || (rdev->family == CHIP_RS100) ||
 971             (rdev->family == CHIP_RS200)) {
 972                 DRM_INFO("Loading R100 Microcode\n");
 973                 fw_name = FIRMWARE_R100;
 974         } else if ((rdev->family == CHIP_R200) ||
 975                    (rdev->family == CHIP_RV250) ||
 976                    (rdev->family == CHIP_RV280) ||
 977                    (rdev->family == CHIP_RS300)) {
 978                 DRM_INFO("Loading R200 Microcode\n");
 979                 fw_name = FIRMWARE_R200;
 980         } else if ((rdev->family == CHIP_R300) ||
 981                    (rdev->family == CHIP_R350) ||
 982                    (rdev->family == CHIP_RV350) ||
 983                    (rdev->family == CHIP_RV380) ||
 984                    (rdev->family == CHIP_RS400) ||
 985                    (rdev->family == CHIP_RS480)) {
 986                 DRM_INFO("Loading R300 Microcode\n");
 987                 fw_name = FIRMWARE_R300;
 988         } else if ((rdev->family == CHIP_R420) ||
 989                    (rdev->family == CHIP_R423) ||
 990                    (rdev->family == CHIP_RV410)) {
 991                 DRM_INFO("Loading R400 Microcode\n");
 992                 fw_name = FIRMWARE_R420;
 993         } else if ((rdev->family == CHIP_RS690) ||
 994                    (rdev->family == CHIP_RS740)) {
 995                 DRM_INFO("Loading RS690/RS740 Microcode\n");
 996                 fw_name = FIRMWARE_RS690;
 997         } else if (rdev->family == CHIP_RS600) {
 998                 DRM_INFO("Loading RS600 Microcode\n");
 999                 fw_name = FIRMWARE_RS600;
1000         } else if ((rdev->family == CHIP_RV515) ||
1001                    (rdev->family == CHIP_R520) ||
1002                    (rdev->family == CHIP_RV530) ||
1003                    (rdev->family == CHIP_R580) ||
1004                    (rdev->family == CHIP_RV560) ||
1005                    (rdev->family == CHIP_RV570)) {
1006                 DRM_INFO("Loading R500 Microcode\n");
1007                 fw_name = FIRMWARE_R520;
1008         }
1009
1010         err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
1011         platform_device_unregister(pdev);
1012         if (err) {
1013                 printk(KERN_ERR "radeon_cp: Failed to load firmware \"%s\"\n",
1014                        fw_name);
1015         } else if (rdev->me_fw->size % 8) {
1016                 printk(KERN_ERR
1017                        "radeon_cp: Bogus length %zu in firmware \"%s\"\n",
1018                        rdev->me_fw->size, fw_name);
1019                 err = -EINVAL;
1020                 release_firmware(rdev->me_fw);
1021                 rdev->me_fw = NULL;
1022         }
1023         return err;
1024 }
1025
1026 static void r100_cp_load_microcode(struct radeon_device *rdev)
1027 {
1028         const __be32 *fw_data;
1029         int i, size;
1030
1031         if (r100_gui_wait_for_idle(rdev)) {
1032                 printk(KERN_WARNING "Failed to wait GUI idle while "
1033                        "programming pipes. Bad things might happen.\n");
1034         }
1035
1036         if (rdev->me_fw) {
1037                 size = rdev->me_fw->size / 4;
1038                 fw_data = (const __be32 *)&rdev->me_fw->data[0];
1039                 WREG32(RADEON_CP_ME_RAM_ADDR, 0);
1040                 for (i = 0; i < size; i += 2) {
1041                         WREG32(RADEON_CP_ME_RAM_DATAH,
1042                                be32_to_cpup(&fw_data[i]));
1043                         WREG32(RADEON_CP_ME_RAM_DATAL,
1044                                be32_to_cpup(&fw_data[i + 1]));
1045                 }
1046         }
1047 }
1048
1049 int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
1050 {
1051         struct radeon_cp *cp = &rdev->cp;
1052         unsigned rb_bufsz;
1053         unsigned rb_blksz;
1054         unsigned max_fetch;
1055         unsigned pre_write_timer;
1056         unsigned pre_write_limit;
1057         unsigned indirect2_start;
1058         unsigned indirect1_start;
1059         uint32_t tmp;
1060         int r;
1061
1062         if (r100_debugfs_cp_init(rdev)) {
1063                 DRM_ERROR("Failed to register debugfs file for CP !\n");
1064         }
1065         if (!rdev->me_fw) {
1066                 r = r100_cp_init_microcode(rdev);
1067                 if (r) {
1068                         DRM_ERROR("Failed to load firmware!\n");
1069                         return r;
1070                 }
1071         }
1072
1073         /* Align ring size */
1074         rb_bufsz = drm_order(ring_size / 8);
1075         ring_size = (1 << (rb_bufsz + 1)) * 4;
1076         r100_cp_load_microcode(rdev);
1077         r = radeon_ring_init(rdev, cp, ring_size);
1078         if (r) {
1079                 return r;
1080         }
1081         /* Each time the cp read 1024 bytes (16 dword/quadword) update
1082          * the rptr copy in system ram */
1083         rb_blksz = 9;
1084         /* cp will read 128bytes at a time (4 dwords) */
1085         max_fetch = 1;
1086         cp->align_mask = 16 - 1;
1087         /* Write to CP_RB_WPTR will be delayed for pre_write_timer clocks */
1088         pre_write_timer = 64;
1089         /* Force CP_RB_WPTR write if written more than one time before the
1090          * delay expire
1091          */
1092         pre_write_limit = 0;
1093         /* Setup the cp cache like this (cache size is 96 dwords) :
1094          *      RING            0  to 15
1095          *      INDIRECT1       16 to 79
1096          *      INDIRECT2       80 to 95
1097          * So ring cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
1098          *    indirect1 cache size is 64dwords (> (2 * max_fetch = 2 * 4dwords))
1099          *    indirect2 cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
1100          * Idea being that most of the gpu cmd will be through indirect1 buffer
1101          * so it gets the bigger cache.
1102          */
1103         indirect2_start = 80;
1104         indirect1_start = 16;
1105         /* cp setup */
1106         WREG32(0x718, pre_write_timer | (pre_write_limit << 28));
1107         tmp = (REG_SET(RADEON_RB_BUFSZ, rb_bufsz) |
1108                REG_SET(RADEON_RB_BLKSZ, rb_blksz) |
1109                REG_SET(RADEON_MAX_FETCH, max_fetch));
1110 #ifdef __BIG_ENDIAN
1111         tmp |= RADEON_BUF_SWAP_32BIT;
1112 #endif
1113         WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_NO_UPDATE);
1114
1115         /* Set ring address */
1116         DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)cp->gpu_addr);
1117         WREG32(RADEON_CP_RB_BASE, cp->gpu_addr);
1118         /* Force read & write ptr to 0 */
1119         WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA | RADEON_RB_NO_UPDATE);
1120         WREG32(RADEON_CP_RB_RPTR_WR, 0);
1121         cp->wptr = 0;
1122         WREG32(RADEON_CP_RB_WPTR, cp->wptr);
1123
1124         /* set the wb address whether it's enabled or not */
1125         WREG32(R_00070C_CP_RB_RPTR_ADDR,
1126                 S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) >> 2));
1127         WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET);
1128
1129         if (rdev->wb.enabled)
1130                 WREG32(R_000770_SCRATCH_UMSK, 0xff);
1131         else {
1132                 tmp |= RADEON_RB_NO_UPDATE;
1133                 WREG32(R_000770_SCRATCH_UMSK, 0);
1134         }
1135
1136         WREG32(RADEON_CP_RB_CNTL, tmp);
1137         udelay(10);
1138         cp->rptr = RREG32(RADEON_CP_RB_RPTR);
1139         /* Set cp mode to bus mastering & enable cp*/
1140         WREG32(RADEON_CP_CSQ_MODE,
1141                REG_SET(RADEON_INDIRECT2_START, indirect2_start) |
1142                REG_SET(RADEON_INDIRECT1_START, indirect1_start));
1143         WREG32(RADEON_CP_RB_WPTR_DELAY, 0);
1144         WREG32(RADEON_CP_CSQ_MODE, 0x00004D4D);
1145         WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM);
1146         radeon_ring_start(rdev);
1147         r = radeon_ring_test(rdev, cp);
1148         if (r) {
1149                 DRM_ERROR("radeon: cp isn't working (%d).\n", r);
1150                 return r;
1151         }
1152         cp->ready = true;
1153         radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
1154         return 0;
1155 }
1156
1157 void r100_cp_fini(struct radeon_device *rdev)
1158 {
1159         if (r100_cp_wait_for_idle(rdev)) {
1160                 DRM_ERROR("Wait for CP idle timeout, shutting down CP.\n");
1161         }
1162         /* Disable ring */
1163         r100_cp_disable(rdev);
1164         radeon_ring_fini(rdev, &rdev->cp);
1165         DRM_INFO("radeon: cp finalized\n");
1166 }
1167
1168 void r100_cp_disable(struct radeon_device *rdev)
1169 {
1170         /* Disable ring */
1171         radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
1172         rdev->cp.ready = false;
1173         WREG32(RADEON_CP_CSQ_MODE, 0);
1174         WREG32(RADEON_CP_CSQ_CNTL, 0);
1175         WREG32(R_000770_SCRATCH_UMSK, 0);
1176         if (r100_gui_wait_for_idle(rdev)) {
1177                 printk(KERN_WARNING "Failed to wait GUI idle while "
1178                        "programming pipes. Bad things might happen.\n");
1179         }
1180 }
1181
1182 void r100_cp_commit(struct radeon_device *rdev, struct radeon_cp *cp)
1183 {
1184         WREG32(RADEON_CP_RB_WPTR, cp->wptr);
1185         (void)RREG32(RADEON_CP_RB_WPTR);
1186 }
1187
1188
1189 /*
1190  * CS functions
1191  */
1192 int r100_cs_parse_packet0(struct radeon_cs_parser *p,
1193                           struct radeon_cs_packet *pkt,
1194                           const unsigned *auth, unsigned n,
1195                           radeon_packet0_check_t check)
1196 {
1197         unsigned reg;
1198         unsigned i, j, m;
1199         unsigned idx;
1200         int r;
1201
1202         idx = pkt->idx + 1;
1203         reg = pkt->reg;
1204         /* Check that register fall into register range
1205          * determined by the number of entry (n) in the
1206          * safe register bitmap.
1207          */
1208         if (pkt->one_reg_wr) {
1209                 if ((reg >> 7) > n) {
1210                         return -EINVAL;
1211                 }
1212         } else {
1213                 if (((reg + (pkt->count << 2)) >> 7) > n) {
1214                         return -EINVAL;
1215                 }
1216         }
1217         for (i = 0; i <= pkt->count; i++, idx++) {
1218                 j = (reg >> 7);
1219                 m = 1 << ((reg >> 2) & 31);
1220                 if (auth[j] & m) {
1221                         r = check(p, pkt, idx, reg);
1222                         if (r) {
1223                                 return r;
1224                         }
1225                 }
1226                 if (pkt->one_reg_wr) {
1227                         if (!(auth[j] & m)) {
1228                                 break;
1229                         }
1230                 } else {
1231                         reg += 4;
1232                 }
1233         }
1234         return 0;
1235 }
1236
1237 void r100_cs_dump_packet(struct radeon_cs_parser *p,
1238                          struct radeon_cs_packet *pkt)
1239 {
1240         volatile uint32_t *ib;
1241         unsigned i;
1242         unsigned idx;
1243
1244         ib = p->ib->ptr;
1245         idx = pkt->idx;
1246         for (i = 0; i <= (pkt->count + 1); i++, idx++) {
1247                 DRM_INFO("ib[%d]=0x%08X\n", idx, ib[idx]);
1248         }
1249 }
1250
1251 /**
1252  * r100_cs_packet_parse() - parse cp packet and point ib index to next packet
1253  * @parser:     parser structure holding parsing context.
1254  * @pkt:        where to store packet informations
1255  *
1256  * Assume that chunk_ib_index is properly set. Will return -EINVAL
1257  * if packet is bigger than remaining ib size. or if packets is unknown.
1258  **/
1259 int r100_cs_packet_parse(struct radeon_cs_parser *p,
1260                          struct radeon_cs_packet *pkt,
1261                          unsigned idx)
1262 {
1263         struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
1264         uint32_t header;
1265
1266         if (idx >= ib_chunk->length_dw) {
1267                 DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
1268                           idx, ib_chunk->length_dw);
1269                 return -EINVAL;
1270         }
1271         header = radeon_get_ib_value(p, idx);
1272         pkt->idx = idx;
1273         pkt->type = CP_PACKET_GET_TYPE(header);
1274         pkt->count = CP_PACKET_GET_COUNT(header);
1275         switch (pkt->type) {
1276         case PACKET_TYPE0:
1277                 pkt->reg = CP_PACKET0_GET_REG(header);
1278                 pkt->one_reg_wr = CP_PACKET0_GET_ONE_REG_WR(header);
1279                 break;
1280         case PACKET_TYPE3:
1281                 pkt->opcode = CP_PACKET3_GET_OPCODE(header);
1282                 break;
1283         case PACKET_TYPE2:
1284                 pkt->count = -1;
1285                 break;
1286         default:
1287                 DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx);
1288                 return -EINVAL;
1289         }
1290         if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) {
1291                 DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
1292                           pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw);
1293                 return -EINVAL;
1294         }
1295         return 0;
1296 }
1297
1298 /**
1299  * r100_cs_packet_next_vline() - parse userspace VLINE packet
1300  * @parser:             parser structure holding parsing context.
1301  *
1302  * Userspace sends a special sequence for VLINE waits.
1303  * PACKET0 - VLINE_START_END + value
1304  * PACKET0 - WAIT_UNTIL +_value
1305  * RELOC (P3) - crtc_id in reloc.
1306  *
1307  * This function parses this and relocates the VLINE START END
1308  * and WAIT UNTIL packets to the correct crtc.
1309  * It also detects a switched off crtc and nulls out the
1310  * wait in that case.
1311  */
1312 int r100_cs_packet_parse_vline(struct radeon_cs_parser *p)
1313 {
1314         struct drm_mode_object *obj;
1315         struct drm_crtc *crtc;
1316         struct radeon_crtc *radeon_crtc;
1317         struct radeon_cs_packet p3reloc, waitreloc;
1318         int crtc_id;
1319         int r;
1320         uint32_t header, h_idx, reg;
1321         volatile uint32_t *ib;
1322
1323         ib = p->ib->ptr;
1324
1325         /* parse the wait until */
1326         r = r100_cs_packet_parse(p, &waitreloc, p->idx);
1327         if (r)
1328                 return r;
1329
1330         /* check its a wait until and only 1 count */
1331         if (waitreloc.reg != RADEON_WAIT_UNTIL ||
1332             waitreloc.count != 0) {
1333                 DRM_ERROR("vline wait had illegal wait until segment\n");
1334                 return -EINVAL;
1335         }
1336
1337         if (radeon_get_ib_value(p, waitreloc.idx + 1) != RADEON_WAIT_CRTC_VLINE) {
1338                 DRM_ERROR("vline wait had illegal wait until\n");
1339                 return -EINVAL;
1340         }
1341
1342         /* jump over the NOP */
1343         r = r100_cs_packet_parse(p, &p3reloc, p->idx + waitreloc.count + 2);
1344         if (r)
1345                 return r;
1346
1347         h_idx = p->idx - 2;
1348         p->idx += waitreloc.count + 2;
1349         p->idx += p3reloc.count + 2;
1350
1351         header = radeon_get_ib_value(p, h_idx);
1352         crtc_id = radeon_get_ib_value(p, h_idx + 5);
1353         reg = CP_PACKET0_GET_REG(header);
1354         obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC);
1355         if (!obj) {
1356                 DRM_ERROR("cannot find crtc %d\n", crtc_id);
1357                 return -EINVAL;
1358         }
1359         crtc = obj_to_crtc(obj);
1360         radeon_crtc = to_radeon_crtc(crtc);
1361         crtc_id = radeon_crtc->crtc_id;
1362
1363         if (!crtc->enabled) {
1364                 /* if the CRTC isn't enabled - we need to nop out the wait until */
1365                 ib[h_idx + 2] = PACKET2(0);
1366                 ib[h_idx + 3] = PACKET2(0);
1367         } else if (crtc_id == 1) {
1368                 switch (reg) {
1369                 case AVIVO_D1MODE_VLINE_START_END:
1370                         header &= ~R300_CP_PACKET0_REG_MASK;
1371                         header |= AVIVO_D2MODE_VLINE_START_END >> 2;
1372                         break;
1373                 case RADEON_CRTC_GUI_TRIG_VLINE:
1374                         header &= ~R300_CP_PACKET0_REG_MASK;
1375                         header |= RADEON_CRTC2_GUI_TRIG_VLINE >> 2;
1376                         break;
1377                 default:
1378                         DRM_ERROR("unknown crtc reloc\n");
1379                         return -EINVAL;
1380                 }
1381                 ib[h_idx] = header;
1382                 ib[h_idx + 3] |= RADEON_ENG_DISPLAY_SELECT_CRTC1;
1383         }
1384
1385         return 0;
1386 }
1387
1388 /**
1389  * r100_cs_packet_next_reloc() - parse next packet which should be reloc packet3
1390  * @parser:             parser structure holding parsing context.
1391  * @data:               pointer to relocation data
1392  * @offset_start:       starting offset
1393  * @offset_mask:        offset mask (to align start offset on)
1394  * @reloc:              reloc informations
1395  *
1396  * Check next packet is relocation packet3, do bo validation and compute
1397  * GPU offset using the provided start.
1398  **/
1399 int r100_cs_packet_next_reloc(struct radeon_cs_parser *p,
1400                               struct radeon_cs_reloc **cs_reloc)
1401 {
1402         struct radeon_cs_chunk *relocs_chunk;
1403         struct radeon_cs_packet p3reloc;
1404         unsigned idx;
1405         int r;
1406
1407         if (p->chunk_relocs_idx == -1) {
1408                 DRM_ERROR("No relocation chunk !\n");
1409                 return -EINVAL;
1410         }
1411         *cs_reloc = NULL;
1412         relocs_chunk = &p->chunks[p->chunk_relocs_idx];
1413         r = r100_cs_packet_parse(p, &p3reloc, p->idx);
1414         if (r) {
1415                 return r;
1416         }
1417         p->idx += p3reloc.count + 2;
1418         if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
1419                 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
1420                           p3reloc.idx);
1421                 r100_cs_dump_packet(p, &p3reloc);
1422                 return -EINVAL;
1423         }
1424         idx = radeon_get_ib_value(p, p3reloc.idx + 1);
1425         if (idx >= relocs_chunk->length_dw) {
1426                 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
1427                           idx, relocs_chunk->length_dw);
1428                 r100_cs_dump_packet(p, &p3reloc);
1429                 return -EINVAL;
1430         }
1431         /* FIXME: we assume reloc size is 4 dwords */
1432         *cs_reloc = p->relocs_ptr[(idx / 4)];
1433         return 0;
1434 }
1435
1436 static int r100_get_vtx_size(uint32_t vtx_fmt)
1437 {
1438         int vtx_size;
1439         vtx_size = 2;
1440         /* ordered according to bits in spec */
1441         if (vtx_fmt & RADEON_SE_VTX_FMT_W0)
1442                 vtx_size++;
1443         if (vtx_fmt & RADEON_SE_VTX_FMT_FPCOLOR)
1444                 vtx_size += 3;
1445         if (vtx_fmt & RADEON_SE_VTX_FMT_FPALPHA)
1446                 vtx_size++;
1447         if (vtx_fmt & RADEON_SE_VTX_FMT_PKCOLOR)
1448                 vtx_size++;
1449         if (vtx_fmt & RADEON_SE_VTX_FMT_FPSPEC)
1450                 vtx_size += 3;
1451         if (vtx_fmt & RADEON_SE_VTX_FMT_FPFOG)
1452                 vtx_size++;
1453         if (vtx_fmt & RADEON_SE_VTX_FMT_PKSPEC)
1454                 vtx_size++;
1455         if (vtx_fmt & RADEON_SE_VTX_FMT_ST0)
1456                 vtx_size += 2;
1457         if (vtx_fmt & RADEON_SE_VTX_FMT_ST1)
1458                 vtx_size += 2;
1459         if (vtx_fmt & RADEON_SE_VTX_FMT_Q1)
1460                 vtx_size++;
1461         if (vtx_fmt & RADEON_SE_VTX_FMT_ST2)
1462                 vtx_size += 2;
1463         if (vtx_fmt & RADEON_SE_VTX_FMT_Q2)
1464                 vtx_size++;
1465         if (vtx_fmt & RADEON_SE_VTX_FMT_ST3)
1466                 vtx_size += 2;
1467         if (vtx_fmt & RADEON_SE_VTX_FMT_Q3)
1468                 vtx_size++;
1469         if (vtx_fmt & RADEON_SE_VTX_FMT_Q0)
1470                 vtx_size++;
1471         /* blend weight */
1472         if (vtx_fmt & (0x7 << 15))
1473                 vtx_size += (vtx_fmt >> 15) & 0x7;
1474         if (vtx_fmt & RADEON_SE_VTX_FMT_N0)
1475                 vtx_size += 3;
1476         if (vtx_fmt & RADEON_SE_VTX_FMT_XY1)
1477                 vtx_size += 2;
1478         if (vtx_fmt & RADEON_SE_VTX_FMT_Z1)
1479                 vtx_size++;
1480         if (vtx_fmt & RADEON_SE_VTX_FMT_W1)
1481                 vtx_size++;
1482         if (vtx_fmt & RADEON_SE_VTX_FMT_N1)
1483                 vtx_size++;
1484         if (vtx_fmt & RADEON_SE_VTX_FMT_Z)
1485                 vtx_size++;
1486         return vtx_size;
1487 }
1488
1489 static int r100_packet0_check(struct radeon_cs_parser *p,
1490                               struct radeon_cs_packet *pkt,
1491                               unsigned idx, unsigned reg)
1492 {
1493         struct radeon_cs_reloc *reloc;
1494         struct r100_cs_track *track;
1495         volatile uint32_t *ib;
1496         uint32_t tmp;
1497         int r;
1498         int i, face;
1499         u32 tile_flags = 0;
1500         u32 idx_value;
1501
1502         ib = p->ib->ptr;
1503         track = (struct r100_cs_track *)p->track;
1504
1505         idx_value = radeon_get_ib_value(p, idx);
1506
1507         switch (reg) {
1508         case RADEON_CRTC_GUI_TRIG_VLINE:
1509                 r = r100_cs_packet_parse_vline(p);
1510                 if (r) {
1511                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1512                                   idx, reg);
1513                         r100_cs_dump_packet(p, pkt);
1514                         return r;
1515                 }
1516                 break;
1517                 /* FIXME: only allow PACKET3 blit? easier to check for out of
1518                  * range access */
1519         case RADEON_DST_PITCH_OFFSET:
1520         case RADEON_SRC_PITCH_OFFSET:
1521                 r = r100_reloc_pitch_offset(p, pkt, idx, reg);
1522                 if (r)
1523                         return r;
1524                 break;
1525         case RADEON_RB3D_DEPTHOFFSET:
1526                 r = r100_cs_packet_next_reloc(p, &reloc);
1527                 if (r) {
1528                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1529                                   idx, reg);
1530                         r100_cs_dump_packet(p, pkt);
1531                         return r;
1532                 }
1533                 track->zb.robj = reloc->robj;
1534                 track->zb.offset = idx_value;
1535                 track->zb_dirty = true;
1536                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1537                 break;
1538         case RADEON_RB3D_COLOROFFSET:
1539                 r = r100_cs_packet_next_reloc(p, &reloc);
1540                 if (r) {
1541                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1542                                   idx, reg);
1543                         r100_cs_dump_packet(p, pkt);
1544                         return r;
1545                 }
1546                 track->cb[0].robj = reloc->robj;
1547                 track->cb[0].offset = idx_value;
1548                 track->cb_dirty = true;
1549                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1550                 break;
1551         case RADEON_PP_TXOFFSET_0:
1552         case RADEON_PP_TXOFFSET_1:
1553         case RADEON_PP_TXOFFSET_2:
1554                 i = (reg - RADEON_PP_TXOFFSET_0) / 24;
1555                 r = r100_cs_packet_next_reloc(p, &reloc);
1556                 if (r) {
1557                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1558                                   idx, reg);
1559                         r100_cs_dump_packet(p, pkt);
1560                         return r;
1561                 }
1562                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1563                 track->textures[i].robj = reloc->robj;
1564                 track->tex_dirty = true;
1565                 break;
1566         case RADEON_PP_CUBIC_OFFSET_T0_0:
1567         case RADEON_PP_CUBIC_OFFSET_T0_1:
1568         case RADEON_PP_CUBIC_OFFSET_T0_2:
1569         case RADEON_PP_CUBIC_OFFSET_T0_3:
1570         case RADEON_PP_CUBIC_OFFSET_T0_4:
1571                 i = (reg - RADEON_PP_CUBIC_OFFSET_T0_0) / 4;
1572                 r = r100_cs_packet_next_reloc(p, &reloc);
1573                 if (r) {
1574                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1575                                   idx, reg);
1576                         r100_cs_dump_packet(p, pkt);
1577                         return r;
1578                 }
1579                 track->textures[0].cube_info[i].offset = idx_value;
1580                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1581                 track->textures[0].cube_info[i].robj = reloc->robj;
1582                 track->tex_dirty = true;
1583                 break;
1584         case RADEON_PP_CUBIC_OFFSET_T1_0:
1585         case RADEON_PP_CUBIC_OFFSET_T1_1:
1586         case RADEON_PP_CUBIC_OFFSET_T1_2:
1587         case RADEON_PP_CUBIC_OFFSET_T1_3:
1588         case RADEON_PP_CUBIC_OFFSET_T1_4:
1589                 i = (reg - RADEON_PP_CUBIC_OFFSET_T1_0) / 4;
1590                 r = r100_cs_packet_next_reloc(p, &reloc);
1591                 if (r) {
1592                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1593                                   idx, reg);
1594                         r100_cs_dump_packet(p, pkt);
1595                         return r;
1596                 }
1597                 track->textures[1].cube_info[i].offset = idx_value;
1598                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1599                 track->textures[1].cube_info[i].robj = reloc->robj;
1600                 track->tex_dirty = true;
1601                 break;
1602         case RADEON_PP_CUBIC_OFFSET_T2_0:
1603         case RADEON_PP_CUBIC_OFFSET_T2_1:
1604         case RADEON_PP_CUBIC_OFFSET_T2_2:
1605         case RADEON_PP_CUBIC_OFFSET_T2_3:
1606         case RADEON_PP_CUBIC_OFFSET_T2_4:
1607                 i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4;
1608                 r = r100_cs_packet_next_reloc(p, &reloc);
1609                 if (r) {
1610                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1611                                   idx, reg);
1612                         r100_cs_dump_packet(p, pkt);
1613                         return r;
1614                 }
1615                 track->textures[2].cube_info[i].offset = idx_value;
1616                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1617                 track->textures[2].cube_info[i].robj = reloc->robj;
1618                 track->tex_dirty = true;
1619                 break;
1620         case RADEON_RE_WIDTH_HEIGHT:
1621                 track->maxy = ((idx_value >> 16) & 0x7FF);
1622                 track->cb_dirty = true;
1623                 track->zb_dirty = true;
1624                 break;
1625         case RADEON_RB3D_COLORPITCH:
1626                 r = r100_cs_packet_next_reloc(p, &reloc);
1627                 if (r) {
1628                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1629                                   idx, reg);
1630                         r100_cs_dump_packet(p, pkt);
1631                         return r;
1632                 }
1633
1634                 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
1635                         tile_flags |= RADEON_COLOR_TILE_ENABLE;
1636                 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
1637                         tile_flags |= RADEON_COLOR_MICROTILE_ENABLE;
1638
1639                 tmp = idx_value & ~(0x7 << 16);
1640                 tmp |= tile_flags;
1641                 ib[idx] = tmp;
1642
1643                 track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK;
1644                 track->cb_dirty = true;
1645                 break;
1646         case RADEON_RB3D_DEPTHPITCH:
1647                 track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK;
1648                 track->zb_dirty = true;
1649                 break;
1650         case RADEON_RB3D_CNTL:
1651                 switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) {
1652                 case 7:
1653                 case 8:
1654                 case 9:
1655                 case 11:
1656                 case 12:
1657                         track->cb[0].cpp = 1;
1658                         break;
1659                 case 3:
1660                 case 4:
1661                 case 15:
1662                         track->cb[0].cpp = 2;
1663                         break;
1664                 case 6:
1665                         track->cb[0].cpp = 4;
1666                         break;
1667                 default:
1668                         DRM_ERROR("Invalid color buffer format (%d) !\n",
1669                                   ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f));
1670                         return -EINVAL;
1671                 }
1672                 track->z_enabled = !!(idx_value & RADEON_Z_ENABLE);
1673                 track->cb_dirty = true;
1674                 track->zb_dirty = true;
1675                 break;
1676         case RADEON_RB3D_ZSTENCILCNTL:
1677                 switch (idx_value & 0xf) {
1678                 case 0:
1679                         track->zb.cpp = 2;
1680                         break;
1681                 case 2:
1682                 case 3:
1683                 case 4:
1684                 case 5:
1685                 case 9:
1686                 case 11:
1687                         track->zb.cpp = 4;
1688                         break;
1689                 default:
1690                         break;
1691                 }
1692                 track->zb_dirty = true;
1693                 break;
1694         case RADEON_RB3D_ZPASS_ADDR:
1695                 r = r100_cs_packet_next_reloc(p, &reloc);
1696                 if (r) {
1697                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1698                                   idx, reg);
1699                         r100_cs_dump_packet(p, pkt);
1700                         return r;
1701                 }
1702                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1703                 break;
1704         case RADEON_PP_CNTL:
1705                 {
1706                         uint32_t temp = idx_value >> 4;
1707                         for (i = 0; i < track->num_texture; i++)
1708                                 track->textures[i].enabled = !!(temp & (1 << i));
1709                         track->tex_dirty = true;
1710                 }
1711                 break;
1712         case RADEON_SE_VF_CNTL:
1713                 track->vap_vf_cntl = idx_value;
1714                 break;
1715         case RADEON_SE_VTX_FMT:
1716                 track->vtx_size = r100_get_vtx_size(idx_value);
1717                 break;
1718         case RADEON_PP_TEX_SIZE_0:
1719         case RADEON_PP_TEX_SIZE_1:
1720         case RADEON_PP_TEX_SIZE_2:
1721                 i = (reg - RADEON_PP_TEX_SIZE_0) / 8;
1722                 track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1;
1723                 track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1;
1724                 track->tex_dirty = true;
1725                 break;
1726         case RADEON_PP_TEX_PITCH_0:
1727         case RADEON_PP_TEX_PITCH_1:
1728         case RADEON_PP_TEX_PITCH_2:
1729                 i = (reg - RADEON_PP_TEX_PITCH_0) / 8;
1730                 track->textures[i].pitch = idx_value + 32;
1731                 track->tex_dirty = true;
1732                 break;
1733         case RADEON_PP_TXFILTER_0:
1734         case RADEON_PP_TXFILTER_1:
1735         case RADEON_PP_TXFILTER_2:
1736                 i = (reg - RADEON_PP_TXFILTER_0) / 24;
1737                 track->textures[i].num_levels = ((idx_value & RADEON_MAX_MIP_LEVEL_MASK)
1738                                                  >> RADEON_MAX_MIP_LEVEL_SHIFT);
1739                 tmp = (idx_value >> 23) & 0x7;
1740                 if (tmp == 2 || tmp == 6)
1741                         track->textures[i].roundup_w = false;
1742                 tmp = (idx_value >> 27) & 0x7;
1743                 if (tmp == 2 || tmp == 6)
1744                         track->textures[i].roundup_h = false;
1745                 track->tex_dirty = true;
1746                 break;
1747         case RADEON_PP_TXFORMAT_0:
1748         case RADEON_PP_TXFORMAT_1:
1749         case RADEON_PP_TXFORMAT_2:
1750                 i = (reg - RADEON_PP_TXFORMAT_0) / 24;
1751                 if (idx_value & RADEON_TXFORMAT_NON_POWER2) {
1752                         track->textures[i].use_pitch = 1;
1753                 } else {
1754                         track->textures[i].use_pitch = 0;
1755                         track->textures[i].width = 1 << ((idx_value >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK);
1756                         track->textures[i].height = 1 << ((idx_value >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK);
1757                 }
1758                 if (idx_value & RADEON_TXFORMAT_CUBIC_MAP_ENABLE)
1759                         track->textures[i].tex_coord_type = 2;
1760                 switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) {
1761                 case RADEON_TXFORMAT_I8:
1762                 case RADEON_TXFORMAT_RGB332:
1763                 case RADEON_TXFORMAT_Y8:
1764                         track->textures[i].cpp = 1;
1765                         track->textures[i].compress_format = R100_TRACK_COMP_NONE;
1766                         break;
1767                 case RADEON_TXFORMAT_AI88:
1768                 case RADEON_TXFORMAT_ARGB1555:
1769                 case RADEON_TXFORMAT_RGB565:
1770                 case RADEON_TXFORMAT_ARGB4444:
1771                 case RADEON_TXFORMAT_VYUY422:
1772                 case RADEON_TXFORMAT_YVYU422:
1773                 case RADEON_TXFORMAT_SHADOW16:
1774                 case RADEON_TXFORMAT_LDUDV655:
1775                 case RADEON_TXFORMAT_DUDV88:
1776                         track->textures[i].cpp = 2;
1777                         track->textures[i].compress_format = R100_TRACK_COMP_NONE;
1778                         break;
1779                 case RADEON_TXFORMAT_ARGB8888:
1780                 case RADEON_TXFORMAT_RGBA8888:
1781                 case RADEON_TXFORMAT_SHADOW32:
1782                 case RADEON_TXFORMAT_LDUDUV8888:
1783                         track->textures[i].cpp = 4;
1784                         track->textures[i].compress_format = R100_TRACK_COMP_NONE;
1785                         break;
1786                 case RADEON_TXFORMAT_DXT1:
1787                         track->textures[i].cpp = 1;
1788                         track->textures[i].compress_format = R100_TRACK_COMP_DXT1;
1789                         break;
1790                 case RADEON_TXFORMAT_DXT23:
1791                 case RADEON_TXFORMAT_DXT45:
1792                         track->textures[i].cpp = 1;
1793                         track->textures[i].compress_format = R100_TRACK_COMP_DXT35;
1794                         break;
1795                 }
1796                 track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf);
1797                 track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf);
1798                 track->tex_dirty = true;
1799                 break;
1800         case RADEON_PP_CUBIC_FACES_0:
1801         case RADEON_PP_CUBIC_FACES_1:
1802         case RADEON_PP_CUBIC_FACES_2:
1803                 tmp = idx_value;
1804                 i = (reg - RADEON_PP_CUBIC_FACES_0) / 4;
1805                 for (face = 0; face < 4; face++) {
1806                         track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf);
1807                         track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf);
1808                 }
1809                 track->tex_dirty = true;
1810                 break;
1811         default:
1812                 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
1813                        reg, idx);
1814                 return -EINVAL;
1815         }
1816         return 0;
1817 }
1818
1819 int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
1820                                          struct radeon_cs_packet *pkt,
1821                                          struct radeon_bo *robj)
1822 {
1823         unsigned idx;
1824         u32 value;
1825         idx = pkt->idx + 1;
1826         value = radeon_get_ib_value(p, idx + 2);
1827         if ((value + 1) > radeon_bo_size(robj)) {
1828                 DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER "
1829                           "(need %u have %lu) !\n",
1830                           value + 1,
1831                           radeon_bo_size(robj));
1832                 return -EINVAL;
1833         }
1834         return 0;
1835 }
1836
1837 static int r100_packet3_check(struct radeon_cs_parser *p,
1838                               struct radeon_cs_packet *pkt)
1839 {
1840         struct radeon_cs_reloc *reloc;
1841         struct r100_cs_track *track;
1842         unsigned idx;
1843         volatile uint32_t *ib;
1844         int r;
1845
1846         ib = p->ib->ptr;
1847         idx = pkt->idx + 1;
1848         track = (struct r100_cs_track *)p->track;
1849         switch (pkt->opcode) {
1850         case PACKET3_3D_LOAD_VBPNTR:
1851                 r = r100_packet3_load_vbpntr(p, pkt, idx);
1852                 if (r)
1853                         return r;
1854                 break;
1855         case PACKET3_INDX_BUFFER:
1856                 r = r100_cs_packet_next_reloc(p, &reloc);
1857                 if (r) {
1858                         DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1859                         r100_cs_dump_packet(p, pkt);
1860                         return r;
1861                 }
1862                 ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->lobj.gpu_offset);
1863                 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
1864                 if (r) {
1865                         return r;
1866                 }
1867                 break;
1868         case 0x23:
1869                 /* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */
1870                 r = r100_cs_packet_next_reloc(p, &reloc);
1871                 if (r) {
1872                         DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1873                         r100_cs_dump_packet(p, pkt);
1874                         return r;
1875                 }
1876                 ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->lobj.gpu_offset);
1877                 track->num_arrays = 1;
1878                 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 2));
1879
1880                 track->arrays[0].robj = reloc->robj;
1881                 track->arrays[0].esize = track->vtx_size;
1882
1883                 track->max_indx = radeon_get_ib_value(p, idx+1);
1884
1885                 track->vap_vf_cntl = radeon_get_ib_value(p, idx+3);
1886                 track->immd_dwords = pkt->count - 1;
1887                 r = r100_cs_track_check(p->rdev, track);
1888                 if (r)
1889                         return r;
1890                 break;
1891         case PACKET3_3D_DRAW_IMMD:
1892                 if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) {
1893                         DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1894                         return -EINVAL;
1895                 }
1896                 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 0));
1897                 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1898                 track->immd_dwords = pkt->count - 1;
1899                 r = r100_cs_track_check(p->rdev, track);
1900                 if (r)
1901                         return r;
1902                 break;
1903                 /* triggers drawing using in-packet vertex data */
1904         case PACKET3_3D_DRAW_IMMD_2:
1905                 if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) {
1906                         DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1907                         return -EINVAL;
1908                 }
1909                 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1910                 track->immd_dwords = pkt->count;
1911                 r = r100_cs_track_check(p->rdev, track);
1912                 if (r)
1913                         return r;
1914                 break;
1915                 /* triggers drawing using in-packet vertex data */
1916         case PACKET3_3D_DRAW_VBUF_2:
1917                 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1918                 r = r100_cs_track_check(p->rdev, track);
1919                 if (r)
1920                         return r;
1921                 break;
1922                 /* triggers drawing of vertex buffers setup elsewhere */
1923         case PACKET3_3D_DRAW_INDX_2:
1924                 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1925                 r = r100_cs_track_check(p->rdev, track);
1926                 if (r)
1927                         return r;
1928                 break;
1929                 /* triggers drawing using indices to vertex buffer */
1930         case PACKET3_3D_DRAW_VBUF:
1931                 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1932                 r = r100_cs_track_check(p->rdev, track);
1933                 if (r)
1934                         return r;
1935                 break;
1936                 /* triggers drawing of vertex buffers setup elsewhere */
1937         case PACKET3_3D_DRAW_INDX:
1938                 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1939                 r = r100_cs_track_check(p->rdev, track);
1940                 if (r)
1941                         return r;
1942                 break;
1943                 /* triggers drawing using indices to vertex buffer */
1944         case PACKET3_3D_CLEAR_HIZ:
1945         case PACKET3_3D_CLEAR_ZMASK:
1946                 if (p->rdev->hyperz_filp != p->filp)
1947                         return -EINVAL;
1948                 break;
1949         case PACKET3_NOP:
1950                 break;
1951         default:
1952                 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
1953                 return -EINVAL;
1954         }
1955         return 0;
1956 }
1957
1958 int r100_cs_parse(struct radeon_cs_parser *p)
1959 {
1960         struct radeon_cs_packet pkt;
1961         struct r100_cs_track *track;
1962         int r;
1963
1964         track = kzalloc(sizeof(*track), GFP_KERNEL);
1965         r100_cs_track_clear(p->rdev, track);
1966         p->track = track;
1967         do {
1968                 r = r100_cs_packet_parse(p, &pkt, p->idx);
1969                 if (r) {
1970                         return r;
1971                 }
1972                 p->idx += pkt.count + 2;
1973                 switch (pkt.type) {
1974                         case PACKET_TYPE0:
1975                                 if (p->rdev->family >= CHIP_R200)
1976                                         r = r100_cs_parse_packet0(p, &pkt,
1977                                                                   p->rdev->config.r100.reg_safe_bm,
1978                                                                   p->rdev->config.r100.reg_safe_bm_size,
1979                                                                   &r200_packet0_check);
1980                                 else
1981                                         r = r100_cs_parse_packet0(p, &pkt,
1982                                                                   p->rdev->config.r100.reg_safe_bm,
1983                                                                   p->rdev->config.r100.reg_safe_bm_size,
1984                                                                   &r100_packet0_check);
1985                                 break;
1986                         case PACKET_TYPE2:
1987                                 break;
1988                         case PACKET_TYPE3:
1989                                 r = r100_packet3_check(p, &pkt);
1990                                 break;
1991                         default:
1992                                 DRM_ERROR("Unknown packet type %d !\n",
1993                                           pkt.type);
1994                                 return -EINVAL;
1995                 }
1996                 if (r) {
1997                         return r;
1998                 }
1999         } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
2000         return 0;
2001 }
2002
2003
2004 /*
2005  * Global GPU functions
2006  */
2007 void r100_errata(struct radeon_device *rdev)
2008 {
2009         rdev->pll_errata = 0;
2010
2011         if (rdev->family == CHIP_RV200 || rdev->family == CHIP_RS200) {
2012                 rdev->pll_errata |= CHIP_ERRATA_PLL_DUMMYREADS;
2013         }
2014
2015         if (rdev->family == CHIP_RV100 ||
2016             rdev->family == CHIP_RS100 ||
2017             rdev->family == CHIP_RS200) {
2018                 rdev->pll_errata |= CHIP_ERRATA_PLL_DELAY;
2019         }
2020 }
2021
2022 /* Wait for vertical sync on primary CRTC */
2023 void r100_gpu_wait_for_vsync(struct radeon_device *rdev)
2024 {
2025         uint32_t crtc_gen_cntl, tmp;
2026         int i;
2027
2028         crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
2029         if ((crtc_gen_cntl & RADEON_CRTC_DISP_REQ_EN_B) ||
2030             !(crtc_gen_cntl & RADEON_CRTC_EN)) {
2031                 return;
2032         }
2033         /* Clear the CRTC_VBLANK_SAVE bit */
2034         WREG32(RADEON_CRTC_STATUS, RADEON_CRTC_VBLANK_SAVE_CLEAR);
2035         for (i = 0; i < rdev->usec_timeout; i++) {
2036                 tmp = RREG32(RADEON_CRTC_STATUS);
2037                 if (tmp & RADEON_CRTC_VBLANK_SAVE) {
2038                         return;
2039                 }
2040                 DRM_UDELAY(1);
2041         }
2042 }
2043
2044 /* Wait for vertical sync on secondary CRTC */
2045 void r100_gpu_wait_for_vsync2(struct radeon_device *rdev)
2046 {
2047         uint32_t crtc2_gen_cntl, tmp;
2048         int i;
2049
2050         crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
2051         if ((crtc2_gen_cntl & RADEON_CRTC2_DISP_REQ_EN_B) ||
2052             !(crtc2_gen_cntl & RADEON_CRTC2_EN))
2053                 return;
2054
2055         /* Clear the CRTC_VBLANK_SAVE bit */
2056         WREG32(RADEON_CRTC2_STATUS, RADEON_CRTC2_VBLANK_SAVE_CLEAR);
2057         for (i = 0; i < rdev->usec_timeout; i++) {
2058                 tmp = RREG32(RADEON_CRTC2_STATUS);
2059                 if (tmp & RADEON_CRTC2_VBLANK_SAVE) {
2060                         return;
2061                 }
2062                 DRM_UDELAY(1);
2063         }
2064 }
2065
2066 int r100_rbbm_fifo_wait_for_entry(struct radeon_device *rdev, unsigned n)
2067 {
2068         unsigned i;
2069         uint32_t tmp;
2070
2071         for (i = 0; i < rdev->usec_timeout; i++) {
2072                 tmp = RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK;
2073                 if (tmp >= n) {
2074                         return 0;
2075                 }
2076                 DRM_UDELAY(1);
2077         }
2078         return -1;
2079 }
2080
2081 int r100_gui_wait_for_idle(struct radeon_device *rdev)
2082 {
2083         unsigned i;
2084         uint32_t tmp;
2085
2086         if (r100_rbbm_fifo_wait_for_entry(rdev, 64)) {
2087                 printk(KERN_WARNING "radeon: wait for empty RBBM fifo failed !"
2088                        " Bad things might happen.\n");
2089         }
2090         for (i = 0; i < rdev->usec_timeout; i++) {
2091                 tmp = RREG32(RADEON_RBBM_STATUS);
2092                 if (!(tmp & RADEON_RBBM_ACTIVE)) {
2093                         return 0;
2094                 }
2095                 DRM_UDELAY(1);
2096         }
2097         return -1;
2098 }
2099
2100 int r100_mc_wait_for_idle(struct radeon_device *rdev)
2101 {
2102         unsigned i;
2103         uint32_t tmp;
2104
2105         for (i = 0; i < rdev->usec_timeout; i++) {
2106                 /* read MC_STATUS */
2107                 tmp = RREG32(RADEON_MC_STATUS);
2108                 if (tmp & RADEON_MC_IDLE) {
2109                         return 0;
2110                 }
2111                 DRM_UDELAY(1);
2112         }
2113         return -1;
2114 }
2115
2116 void r100_gpu_lockup_update(struct r100_gpu_lockup *lockup, struct radeon_cp *cp)
2117 {
2118         lockup->last_cp_rptr = cp->rptr;
2119         lockup->last_jiffies = jiffies;
2120 }
2121
2122 /**
2123  * r100_gpu_cp_is_lockup() - check if CP is lockup by recording information
2124  * @rdev:       radeon device structure
2125  * @lockup:     r100_gpu_lockup structure holding CP lockup tracking informations
2126  * @cp:         radeon_cp structure holding CP information
2127  *
2128  * We don't need to initialize the lockup tracking information as we will either
2129  * have CP rptr to a different value of jiffies wrap around which will force
2130  * initialization of the lockup tracking informations.
2131  *
2132  * A possible false positivie is if we get call after while and last_cp_rptr ==
2133  * the current CP rptr, even if it's unlikely it might happen. To avoid this
2134  * if the elapsed time since last call is bigger than 2 second than we return
2135  * false and update the tracking information. Due to this the caller must call
2136  * r100_gpu_cp_is_lockup several time in less than 2sec for lockup to be reported
2137  * the fencing code should be cautious about that.
2138  *
2139  * Caller should write to the ring to force CP to do something so we don't get
2140  * false positive when CP is just gived nothing to do.
2141  *
2142  **/
2143 bool r100_gpu_cp_is_lockup(struct radeon_device *rdev, struct r100_gpu_lockup *lockup, struct radeon_cp *cp)
2144 {
2145         unsigned long cjiffies, elapsed;
2146
2147         cjiffies = jiffies;
2148         if (!time_after(cjiffies, lockup->last_jiffies)) {
2149                 /* likely a wrap around */
2150                 lockup->last_cp_rptr = cp->rptr;
2151                 lockup->last_jiffies = jiffies;
2152                 return false;
2153         }
2154         if (cp->rptr != lockup->last_cp_rptr) {
2155                 /* CP is still working no lockup */
2156                 lockup->last_cp_rptr = cp->rptr;
2157                 lockup->last_jiffies = jiffies;
2158                 return false;
2159         }
2160         elapsed = jiffies_to_msecs(cjiffies - lockup->last_jiffies);
2161         if (elapsed >= 10000) {
2162                 dev_err(rdev->dev, "GPU lockup CP stall for more than %lumsec\n", elapsed);
2163                 return true;
2164         }
2165         /* give a chance to the GPU ... */
2166         return false;
2167 }
2168
2169 bool r100_gpu_is_lockup(struct radeon_device *rdev, struct radeon_cp *cp)
2170 {
2171         u32 rbbm_status;
2172         int r;
2173
2174         rbbm_status = RREG32(R_000E40_RBBM_STATUS);
2175         if (!G_000E40_GUI_ACTIVE(rbbm_status)) {
2176                 r100_gpu_lockup_update(&rdev->config.r100.lockup, cp);
2177                 return false;
2178         }
2179         /* force CP activities */
2180         r = radeon_ring_lock(rdev, cp, 2);
2181         if (!r) {
2182                 /* PACKET2 NOP */
2183                 radeon_ring_write(cp, 0x80000000);
2184                 radeon_ring_write(cp, 0x80000000);
2185                 radeon_ring_unlock_commit(rdev, cp);
2186         }
2187         cp->rptr = RREG32(RADEON_CP_RB_RPTR);
2188         return r100_gpu_cp_is_lockup(rdev, &rdev->config.r100.lockup, cp);
2189 }
2190
2191 void r100_bm_disable(struct radeon_device *rdev)
2192 {
2193         u32 tmp;
2194
2195         /* disable bus mastering */
2196         tmp = RREG32(R_000030_BUS_CNTL);
2197         WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000044);
2198         mdelay(1);
2199         WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000042);
2200         mdelay(1);
2201         WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000040);
2202         tmp = RREG32(RADEON_BUS_CNTL);
2203         mdelay(1);
2204         pci_read_config_word(rdev->pdev, 0x4, (u16*)&tmp);
2205         pci_write_config_word(rdev->pdev, 0x4, tmp & 0xFFFB);
2206         mdelay(1);
2207 }
2208
2209 int r100_asic_reset(struct radeon_device *rdev)
2210 {
2211         struct r100_mc_save save;
2212         u32 status, tmp;
2213         int ret = 0;
2214
2215         status = RREG32(R_000E40_RBBM_STATUS);
2216         if (!G_000E40_GUI_ACTIVE(status)) {
2217                 return 0;
2218         }
2219         r100_mc_stop(rdev, &save);
2220         status = RREG32(R_000E40_RBBM_STATUS);
2221         dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2222         /* stop CP */
2223         WREG32(RADEON_CP_CSQ_CNTL, 0);
2224         tmp = RREG32(RADEON_CP_RB_CNTL);
2225         WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
2226         WREG32(RADEON_CP_RB_RPTR_WR, 0);
2227         WREG32(RADEON_CP_RB_WPTR, 0);
2228         WREG32(RADEON_CP_RB_CNTL, tmp);
2229         /* save PCI state */
2230         pci_save_state(rdev->pdev);
2231         /* disable bus mastering */
2232         r100_bm_disable(rdev);
2233         WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_SE(1) |
2234                                         S_0000F0_SOFT_RESET_RE(1) |
2235                                         S_0000F0_SOFT_RESET_PP(1) |
2236                                         S_0000F0_SOFT_RESET_RB(1));
2237         RREG32(R_0000F0_RBBM_SOFT_RESET);
2238         mdelay(500);
2239         WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
2240         mdelay(1);
2241         status = RREG32(R_000E40_RBBM_STATUS);
2242         dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2243         /* reset CP */
2244         WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1));
2245         RREG32(R_0000F0_RBBM_SOFT_RESET);
2246         mdelay(500);
2247         WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
2248         mdelay(1);
2249         status = RREG32(R_000E40_RBBM_STATUS);
2250         dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2251         /* restore PCI & busmastering */
2252         pci_restore_state(rdev->pdev);
2253         r100_enable_bm(rdev);
2254         /* Check if GPU is idle */
2255         if (G_000E40_SE_BUSY(status) || G_000E40_RE_BUSY(status) ||
2256                 G_000E40_TAM_BUSY(status) || G_000E40_PB_BUSY(status)) {
2257                 dev_err(rdev->dev, "failed to reset GPU\n");
2258                 rdev->gpu_lockup = true;
2259                 ret = -1;
2260         } else
2261                 dev_info(rdev->dev, "GPU reset succeed\n");
2262         r100_mc_resume(rdev, &save);
2263         return ret;
2264 }
2265
2266 void r100_set_common_regs(struct radeon_device *rdev)
2267 {
2268         struct drm_device *dev = rdev->ddev;
2269         bool force_dac2 = false;
2270         u32 tmp;
2271
2272         /* set these so they don't interfere with anything */
2273         WREG32(RADEON_OV0_SCALE_CNTL, 0);
2274         WREG32(RADEON_SUBPIC_CNTL, 0);
2275         WREG32(RADEON_VIPH_CONTROL, 0);
2276         WREG32(RADEON_I2C_CNTL_1, 0);
2277         WREG32(RADEON_DVI_I2C_CNTL_1, 0);
2278         WREG32(RADEON_CAP0_TRIG_CNTL, 0);
2279         WREG32(RADEON_CAP1_TRIG_CNTL, 0);
2280
2281         /* always set up dac2 on rn50 and some rv100 as lots
2282          * of servers seem to wire it up to a VGA port but
2283          * don't report it in the bios connector
2284          * table.
2285          */
2286         switch (dev->pdev->device) {
2287                 /* RN50 */
2288         case 0x515e:
2289         case 0x5969:
2290                 force_dac2 = true;
2291                 break;
2292                 /* RV100*/
2293         case 0x5159:
2294         case 0x515a:
2295                 /* DELL triple head servers */
2296                 if ((dev->pdev->subsystem_vendor == 0x1028 /* DELL */) &&
2297                     ((dev->pdev->subsystem_device == 0x016c) ||
2298                      (dev->pdev->subsystem_device == 0x016d) ||
2299                      (dev->pdev->subsystem_device == 0x016e) ||
2300                      (dev->pdev->subsystem_device == 0x016f) ||
2301                      (dev->pdev->subsystem_device == 0x0170) ||
2302                      (dev->pdev->subsystem_device == 0x017d) ||
2303                      (dev->pdev->subsystem_device == 0x017e) ||
2304                      (dev->pdev->subsystem_device == 0x0183) ||
2305                      (dev->pdev->subsystem_device == 0x018a) ||
2306                      (dev->pdev->subsystem_device == 0x019a)))
2307                         force_dac2 = true;
2308                 break;
2309         }
2310
2311         if (force_dac2) {
2312                 u32 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
2313                 u32 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
2314                 u32 dac2_cntl = RREG32(RADEON_DAC_CNTL2);
2315
2316                 /* For CRT on DAC2, don't turn it on if BIOS didn't
2317                    enable it, even it's detected.
2318                 */
2319
2320                 /* force it to crtc0 */
2321                 dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL;
2322                 dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL;
2323                 disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
2324
2325                 /* set up the TV DAC */
2326                 tv_dac_cntl &= ~(RADEON_TV_DAC_PEDESTAL |
2327                                  RADEON_TV_DAC_STD_MASK |
2328                                  RADEON_TV_DAC_RDACPD |
2329                                  RADEON_TV_DAC_GDACPD |
2330                                  RADEON_TV_DAC_BDACPD |
2331                                  RADEON_TV_DAC_BGADJ_MASK |
2332                                  RADEON_TV_DAC_DACADJ_MASK);
2333                 tv_dac_cntl |= (RADEON_TV_DAC_NBLANK |
2334                                 RADEON_TV_DAC_NHOLD |
2335                                 RADEON_TV_DAC_STD_PS2 |
2336                                 (0x58 << 16));
2337
2338                 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
2339                 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
2340                 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
2341         }
2342
2343         /* switch PM block to ACPI mode */
2344         tmp = RREG32_PLL(RADEON_PLL_PWRMGT_CNTL);
2345         tmp &= ~RADEON_PM_MODE_SEL;
2346         WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp);
2347
2348 }
2349
2350 /*
2351  * VRAM info
2352  */
2353 static void r100_vram_get_type(struct radeon_device *rdev)
2354 {
2355         uint32_t tmp;
2356
2357         rdev->mc.vram_is_ddr = false;
2358         if (rdev->flags & RADEON_IS_IGP)
2359                 rdev->mc.vram_is_ddr = true;
2360         else if (RREG32(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR)
2361                 rdev->mc.vram_is_ddr = true;
2362         if ((rdev->family == CHIP_RV100) ||
2363             (rdev->family == CHIP_RS100) ||
2364             (rdev->family == CHIP_RS200)) {
2365                 tmp = RREG32(RADEON_MEM_CNTL);
2366                 if (tmp & RV100_HALF_MODE) {
2367                         rdev->mc.vram_width = 32;
2368                 } else {
2369                         rdev->mc.vram_width = 64;
2370                 }
2371                 if (rdev->flags & RADEON_SINGLE_CRTC) {
2372                         rdev->mc.vram_width /= 4;
2373                         rdev->mc.vram_is_ddr = true;
2374                 }
2375         } else if (rdev->family <= CHIP_RV280) {
2376                 tmp = RREG32(RADEON_MEM_CNTL);
2377                 if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) {
2378                         rdev->mc.vram_width = 128;
2379                 } else {
2380                         rdev->mc.vram_width = 64;
2381                 }
2382         } else {
2383                 /* newer IGPs */
2384                 rdev->mc.vram_width = 128;
2385         }
2386 }
2387
2388 static u32 r100_get_accessible_vram(struct radeon_device *rdev)
2389 {
2390         u32 aper_size;
2391         u8 byte;
2392
2393         aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
2394
2395         /* Set HDP_APER_CNTL only on cards that are known not to be broken,
2396          * that is has the 2nd generation multifunction PCI interface
2397          */
2398         if (rdev->family == CHIP_RV280 ||
2399             rdev->family >= CHIP_RV350) {
2400                 WREG32_P(RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL,
2401                        ~RADEON_HDP_APER_CNTL);
2402                 DRM_INFO("Generation 2 PCI interface, using max accessible memory\n");
2403                 return aper_size * 2;
2404         }
2405
2406         /* Older cards have all sorts of funny issues to deal with. First
2407          * check if it's a multifunction card by reading the PCI config
2408          * header type... Limit those to one aperture size
2409          */
2410         pci_read_config_byte(rdev->pdev, 0xe, &byte);
2411         if (byte & 0x80) {
2412                 DRM_INFO("Generation 1 PCI interface in multifunction mode\n");
2413                 DRM_INFO("Limiting VRAM to one aperture\n");
2414                 return aper_size;
2415         }
2416
2417         /* Single function older card. We read HDP_APER_CNTL to see how the BIOS
2418          * have set it up. We don't write this as it's broken on some ASICs but
2419          * we expect the BIOS to have done the right thing (might be too optimistic...)
2420          */
2421         if (RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL)
2422                 return aper_size * 2;
2423         return aper_size;
2424 }
2425
2426 void r100_vram_init_sizes(struct radeon_device *rdev)
2427 {
2428         u64 config_aper_size;
2429
2430         /* work out accessible VRAM */
2431         rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
2432         rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
2433         rdev->mc.visible_vram_size = r100_get_accessible_vram(rdev);
2434         /* FIXME we don't use the second aperture yet when we could use it */
2435         if (rdev->mc.visible_vram_size > rdev->mc.aper_size)
2436                 rdev->mc.visible_vram_size = rdev->mc.aper_size;
2437         config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
2438         if (rdev->flags & RADEON_IS_IGP) {
2439                 uint32_t tom;
2440                 /* read NB_TOM to get the amount of ram stolen for the GPU */
2441                 tom = RREG32(RADEON_NB_TOM);
2442                 rdev->mc.real_vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16);
2443                 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
2444                 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
2445         } else {
2446                 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
2447                 /* Some production boards of m6 will report 0
2448                  * if it's 8 MB
2449                  */
2450                 if (rdev->mc.real_vram_size == 0) {
2451                         rdev->mc.real_vram_size = 8192 * 1024;
2452                         WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
2453                 }
2454                 /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM -
2455                  * Novell bug 204882 + along with lots of ubuntu ones
2456                  */
2457                 if (rdev->mc.aper_size > config_aper_size)
2458                         config_aper_size = rdev->mc.aper_size;
2459
2460                 if (config_aper_size > rdev->mc.real_vram_size)
2461                         rdev->mc.mc_vram_size = config_aper_size;
2462                 else
2463                         rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
2464         }
2465 }
2466
2467 void r100_vga_set_state(struct radeon_device *rdev, bool state)
2468 {
2469         uint32_t temp;
2470
2471         temp = RREG32(RADEON_CONFIG_CNTL);
2472         if (state == false) {
2473                 temp &= ~RADEON_CFG_VGA_RAM_EN;
2474                 temp |= RADEON_CFG_VGA_IO_DIS;
2475         } else {
2476                 temp &= ~RADEON_CFG_VGA_IO_DIS;
2477         }
2478         WREG32(RADEON_CONFIG_CNTL, temp);
2479 }
2480
2481 void r100_mc_init(struct radeon_device *rdev)
2482 {
2483         u64 base;
2484
2485         r100_vram_get_type(rdev);
2486         r100_vram_init_sizes(rdev);
2487         base = rdev->mc.aper_base;
2488         if (rdev->flags & RADEON_IS_IGP)
2489                 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
2490         radeon_vram_location(rdev, &rdev->mc, base);
2491         rdev->mc.gtt_base_align = 0;
2492         if (!(rdev->flags & RADEON_IS_AGP))
2493                 radeon_gtt_location(rdev, &rdev->mc);
2494         radeon_update_bandwidth_info(rdev);
2495 }
2496
2497
2498 /*
2499  * Indirect registers accessor
2500  */
2501 void r100_pll_errata_after_index(struct radeon_device *rdev)
2502 {
2503         if (rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS) {
2504                 (void)RREG32(RADEON_CLOCK_CNTL_DATA);
2505                 (void)RREG32(RADEON_CRTC_GEN_CNTL);
2506         }
2507 }
2508
2509 static void r100_pll_errata_after_data(struct radeon_device *rdev)
2510 {
2511         /* This workarounds is necessary on RV100, RS100 and RS200 chips
2512          * or the chip could hang on a subsequent access
2513          */
2514         if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) {
2515                 udelay(5000);
2516         }
2517
2518         /* This function is required to workaround a hardware bug in some (all?)
2519          * revisions of the R300.  This workaround should be called after every
2520          * CLOCK_CNTL_INDEX register access.  If not, register reads afterward
2521          * may not be correct.
2522          */
2523         if (rdev->pll_errata & CHIP_ERRATA_R300_CG) {
2524                 uint32_t save, tmp;
2525
2526                 save = RREG32(RADEON_CLOCK_CNTL_INDEX);
2527                 tmp = save & ~(0x3f | RADEON_PLL_WR_EN);
2528                 WREG32(RADEON_CLOCK_CNTL_INDEX, tmp);
2529                 tmp = RREG32(RADEON_CLOCK_CNTL_DATA);
2530                 WREG32(RADEON_CLOCK_CNTL_INDEX, save);
2531         }
2532 }
2533
2534 uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg)
2535 {
2536         uint32_t data;
2537
2538         WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f);
2539         r100_pll_errata_after_index(rdev);
2540         data = RREG32(RADEON_CLOCK_CNTL_DATA);
2541         r100_pll_errata_after_data(rdev);
2542         return data;
2543 }
2544
2545 void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
2546 {
2547         WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) | RADEON_PLL_WR_EN));
2548         r100_pll_errata_after_index(rdev);
2549         WREG32(RADEON_CLOCK_CNTL_DATA, v);
2550         r100_pll_errata_after_data(rdev);
2551 }
2552
2553 void r100_set_safe_registers(struct radeon_device *rdev)
2554 {
2555         if (ASIC_IS_RN50(rdev)) {
2556                 rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm;
2557                 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(rn50_reg_safe_bm);
2558         } else if (rdev->family < CHIP_R200) {
2559                 rdev->config.r100.reg_safe_bm = r100_reg_safe_bm;
2560                 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm);
2561         } else {
2562                 r200_set_safe_registers(rdev);
2563         }
2564 }
2565
2566 /*
2567  * Debugfs info
2568  */
2569 #if defined(CONFIG_DEBUG_FS)
2570 static int r100_debugfs_rbbm_info(struct seq_file *m, void *data)
2571 {
2572         struct drm_info_node *node = (struct drm_info_node *) m->private;
2573         struct drm_device *dev = node->minor->dev;
2574         struct radeon_device *rdev = dev->dev_private;
2575         uint32_t reg, value;
2576         unsigned i;
2577
2578         seq_printf(m, "RBBM_STATUS 0x%08x\n", RREG32(RADEON_RBBM_STATUS));
2579         seq_printf(m, "RBBM_CMDFIFO_STAT 0x%08x\n", RREG32(0xE7C));
2580         seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2581         for (i = 0; i < 64; i++) {
2582                 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i | 0x100);
2583                 reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA) - 1) >> 2;
2584                 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i);
2585                 value = RREG32(RADEON_RBBM_CMDFIFO_DATA);
2586                 seq_printf(m, "[0x%03X] 0x%04X=0x%08X\n", i, reg, value);
2587         }
2588         return 0;
2589 }
2590
2591 static int r100_debugfs_cp_ring_info(struct seq_file *m, void *data)
2592 {
2593         struct drm_info_node *node = (struct drm_info_node *) m->private;
2594         struct drm_device *dev = node->minor->dev;
2595         struct radeon_device *rdev = dev->dev_private;
2596         struct radeon_cp *cp = &rdev->cp;
2597         uint32_t rdp, wdp;
2598         unsigned count, i, j;
2599
2600         radeon_ring_free_size(rdev, cp);
2601         rdp = RREG32(RADEON_CP_RB_RPTR);
2602         wdp = RREG32(RADEON_CP_RB_WPTR);
2603         count = (rdp + cp->ring_size - wdp) & cp->ptr_mask;
2604         seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2605         seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp);
2606         seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp);
2607         seq_printf(m, "%u free dwords in ring\n", cp->ring_free_dw);
2608         seq_printf(m, "%u dwords in ring\n", count);
2609         for (j = 0; j <= count; j++) {
2610                 i = (rdp + j) & cp->ptr_mask;
2611                 seq_printf(m, "r[%04d]=0x%08x\n", i, cp->ring[i]);
2612         }
2613         return 0;
2614 }
2615
2616
2617 static int r100_debugfs_cp_csq_fifo(struct seq_file *m, void *data)
2618 {
2619         struct drm_info_node *node = (struct drm_info_node *) m->private;
2620         struct drm_device *dev = node->minor->dev;
2621         struct radeon_device *rdev = dev->dev_private;
2622         uint32_t csq_stat, csq2_stat, tmp;
2623         unsigned r_rptr, r_wptr, ib1_rptr, ib1_wptr, ib2_rptr, ib2_wptr;
2624         unsigned i;
2625
2626         seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2627         seq_printf(m, "CP_CSQ_MODE 0x%08x\n", RREG32(RADEON_CP_CSQ_MODE));
2628         csq_stat = RREG32(RADEON_CP_CSQ_STAT);
2629         csq2_stat = RREG32(RADEON_CP_CSQ2_STAT);
2630         r_rptr = (csq_stat >> 0) & 0x3ff;
2631         r_wptr = (csq_stat >> 10) & 0x3ff;
2632         ib1_rptr = (csq_stat >> 20) & 0x3ff;
2633         ib1_wptr = (csq2_stat >> 0) & 0x3ff;
2634         ib2_rptr = (csq2_stat >> 10) & 0x3ff;
2635         ib2_wptr = (csq2_stat >> 20) & 0x3ff;
2636         seq_printf(m, "CP_CSQ_STAT 0x%08x\n", csq_stat);
2637         seq_printf(m, "CP_CSQ2_STAT 0x%08x\n", csq2_stat);
2638         seq_printf(m, "Ring rptr %u\n", r_rptr);
2639         seq_printf(m, "Ring wptr %u\n", r_wptr);
2640         seq_printf(m, "Indirect1 rptr %u\n", ib1_rptr);
2641         seq_printf(m, "Indirect1 wptr %u\n", ib1_wptr);
2642         seq_printf(m, "Indirect2 rptr %u\n", ib2_rptr);
2643         seq_printf(m, "Indirect2 wptr %u\n", ib2_wptr);
2644         /* FIXME: 0, 128, 640 depends on fifo setup see cp_init_kms
2645          * 128 = indirect1_start * 8 & 640 = indirect2_start * 8 */
2646         seq_printf(m, "Ring fifo:\n");
2647         for (i = 0; i < 256; i++) {
2648                 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2649                 tmp = RREG32(RADEON_CP_CSQ_DATA);
2650                 seq_printf(m, "rfifo[%04d]=0x%08X\n", i, tmp);
2651         }
2652         seq_printf(m, "Indirect1 fifo:\n");
2653         for (i = 256; i <= 512; i++) {
2654                 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2655                 tmp = RREG32(RADEON_CP_CSQ_DATA);
2656                 seq_printf(m, "ib1fifo[%04d]=0x%08X\n", i, tmp);
2657         }
2658         seq_printf(m, "Indirect2 fifo:\n");
2659         for (i = 640; i < ib1_wptr; i++) {
2660                 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2661                 tmp = RREG32(RADEON_CP_CSQ_DATA);
2662                 seq_printf(m, "ib2fifo[%04d]=0x%08X\n", i, tmp);
2663         }
2664         return 0;
2665 }
2666
2667 static int r100_debugfs_mc_info(struct seq_file *m, void *data)
2668 {
2669         struct drm_info_node *node = (struct drm_info_node *) m->private;
2670         struct drm_device *dev = node->minor->dev;
2671         struct radeon_device *rdev = dev->dev_private;
2672         uint32_t tmp;
2673
2674         tmp = RREG32(RADEON_CONFIG_MEMSIZE);
2675         seq_printf(m, "CONFIG_MEMSIZE 0x%08x\n", tmp);
2676         tmp = RREG32(RADEON_MC_FB_LOCATION);
2677         seq_printf(m, "MC_FB_LOCATION 0x%08x\n", tmp);
2678         tmp = RREG32(RADEON_BUS_CNTL);
2679         seq_printf(m, "BUS_CNTL 0x%08x\n", tmp);
2680         tmp = RREG32(RADEON_MC_AGP_LOCATION);
2681         seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp);
2682         tmp = RREG32(RADEON_AGP_BASE);
2683         seq_printf(m, "AGP_BASE 0x%08x\n", tmp);
2684         tmp = RREG32(RADEON_HOST_PATH_CNTL);
2685         seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp);
2686         tmp = RREG32(0x01D0);
2687         seq_printf(m, "AIC_CTRL 0x%08x\n", tmp);
2688         tmp = RREG32(RADEON_AIC_LO_ADDR);
2689         seq_printf(m, "AIC_LO_ADDR 0x%08x\n", tmp);
2690         tmp = RREG32(RADEON_AIC_HI_ADDR);
2691         seq_printf(m, "AIC_HI_ADDR 0x%08x\n", tmp);
2692         tmp = RREG32(0x01E4);
2693         seq_printf(m, "AIC_TLB_ADDR 0x%08x\n", tmp);
2694         return 0;
2695 }
2696
2697 static struct drm_info_list r100_debugfs_rbbm_list[] = {
2698         {"r100_rbbm_info", r100_debugfs_rbbm_info, 0, NULL},
2699 };
2700
2701 static struct drm_info_list r100_debugfs_cp_list[] = {
2702         {"r100_cp_ring_info", r100_debugfs_cp_ring_info, 0, NULL},
2703         {"r100_cp_csq_fifo", r100_debugfs_cp_csq_fifo, 0, NULL},
2704 };
2705
2706 static struct drm_info_list r100_debugfs_mc_info_list[] = {
2707         {"r100_mc_info", r100_debugfs_mc_info, 0, NULL},
2708 };
2709 #endif
2710
2711 int r100_debugfs_rbbm_init(struct radeon_device *rdev)
2712 {
2713 #if defined(CONFIG_DEBUG_FS)
2714         return radeon_debugfs_add_files(rdev, r100_debugfs_rbbm_list, 1);
2715 #else
2716         return 0;
2717 #endif
2718 }
2719
2720 int r100_debugfs_cp_init(struct radeon_device *rdev)
2721 {
2722 #if defined(CONFIG_DEBUG_FS)
2723         return radeon_debugfs_add_files(rdev, r100_debugfs_cp_list, 2);
2724 #else
2725         return 0;
2726 #endif
2727 }
2728
2729 int r100_debugfs_mc_info_init(struct radeon_device *rdev)
2730 {
2731 #if defined(CONFIG_DEBUG_FS)
2732         return radeon_debugfs_add_files(rdev, r100_debugfs_mc_info_list, 1);
2733 #else
2734         return 0;
2735 #endif
2736 }
2737
2738 int r100_set_surface_reg(struct radeon_device *rdev, int reg,
2739                          uint32_t tiling_flags, uint32_t pitch,
2740                          uint32_t offset, uint32_t obj_size)
2741 {
2742         int surf_index = reg * 16;
2743         int flags = 0;
2744
2745         if (rdev->family <= CHIP_RS200) {
2746                 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
2747                                  == (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
2748                         flags |= RADEON_SURF_TILE_COLOR_BOTH;
2749                 if (tiling_flags & RADEON_TILING_MACRO)
2750                         flags |= RADEON_SURF_TILE_COLOR_MACRO;
2751         } else if (rdev->family <= CHIP_RV280) {
2752                 if (tiling_flags & (RADEON_TILING_MACRO))
2753                         flags |= R200_SURF_TILE_COLOR_MACRO;
2754                 if (tiling_flags & RADEON_TILING_MICRO)
2755                         flags |= R200_SURF_TILE_COLOR_MICRO;
2756         } else {
2757                 if (tiling_flags & RADEON_TILING_MACRO)
2758                         flags |= R300_SURF_TILE_MACRO;
2759                 if (tiling_flags & RADEON_TILING_MICRO)
2760                         flags |= R300_SURF_TILE_MICRO;
2761         }
2762
2763         if (tiling_flags & RADEON_TILING_SWAP_16BIT)
2764                 flags |= RADEON_SURF_AP0_SWP_16BPP | RADEON_SURF_AP1_SWP_16BPP;
2765         if (tiling_flags & RADEON_TILING_SWAP_32BIT)
2766                 flags |= RADEON_SURF_AP0_SWP_32BPP | RADEON_SURF_AP1_SWP_32BPP;
2767
2768         /* when we aren't tiling the pitch seems to needs to be furtherdivided down. - tested on power5 + rn50 server */
2769         if (tiling_flags & (RADEON_TILING_SWAP_16BIT | RADEON_TILING_SWAP_32BIT)) {
2770                 if (!(tiling_flags & (RADEON_TILING_MACRO | RADEON_TILING_MICRO)))
2771                         if (ASIC_IS_RN50(rdev))
2772                                 pitch /= 16;
2773         }
2774
2775         /* r100/r200 divide by 16 */
2776         if (rdev->family < CHIP_R300)
2777                 flags |= pitch / 16;
2778         else
2779                 flags |= pitch / 8;
2780
2781
2782         DRM_DEBUG_KMS("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1);
2783         WREG32(RADEON_SURFACE0_INFO + surf_index, flags);
2784         WREG32(RADEON_SURFACE0_LOWER_BOUND + surf_index, offset);
2785         WREG32(RADEON_SURFACE0_UPPER_BOUND + surf_index, offset + obj_size - 1);
2786         return 0;
2787 }
2788
2789 void r100_clear_surface_reg(struct radeon_device *rdev, int reg)
2790 {
2791         int surf_index = reg * 16;
2792         WREG32(RADEON_SURFACE0_INFO + surf_index, 0);
2793 }
2794
2795 void r100_bandwidth_update(struct radeon_device *rdev)
2796 {
2797         fixed20_12 trcd_ff, trp_ff, tras_ff, trbs_ff, tcas_ff;
2798         fixed20_12 sclk_ff, mclk_ff, sclk_eff_ff, sclk_delay_ff;
2799         fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff, crit_point_ff;
2800         uint32_t temp, data, mem_trcd, mem_trp, mem_tras;
2801         fixed20_12 memtcas_ff[8] = {
2802                 dfixed_init(1),
2803                 dfixed_init(2),
2804                 dfixed_init(3),
2805                 dfixed_init(0),
2806                 dfixed_init_half(1),
2807                 dfixed_init_half(2),
2808                 dfixed_init(0),
2809         };
2810         fixed20_12 memtcas_rs480_ff[8] = {
2811                 dfixed_init(0),
2812                 dfixed_init(1),
2813                 dfixed_init(2),
2814                 dfixed_init(3),
2815                 dfixed_init(0),
2816                 dfixed_init_half(1),
2817                 dfixed_init_half(2),
2818                 dfixed_init_half(3),
2819         };
2820         fixed20_12 memtcas2_ff[8] = {
2821                 dfixed_init(0),
2822                 dfixed_init(1),
2823                 dfixed_init(2),
2824                 dfixed_init(3),
2825                 dfixed_init(4),
2826                 dfixed_init(5),
2827                 dfixed_init(6),
2828                 dfixed_init(7),
2829         };
2830         fixed20_12 memtrbs[8] = {
2831                 dfixed_init(1),
2832                 dfixed_init_half(1),
2833                 dfixed_init(2),
2834                 dfixed_init_half(2),
2835                 dfixed_init(3),
2836                 dfixed_init_half(3),
2837                 dfixed_init(4),
2838                 dfixed_init_half(4)
2839         };
2840         fixed20_12 memtrbs_r4xx[8] = {
2841                 dfixed_init(4),
2842                 dfixed_init(5),
2843                 dfixed_init(6),
2844                 dfixed_init(7),
2845                 dfixed_init(8),
2846                 dfixed_init(9),
2847                 dfixed_init(10),
2848                 dfixed_init(11)
2849         };
2850         fixed20_12 min_mem_eff;
2851         fixed20_12 mc_latency_sclk, mc_latency_mclk, k1;
2852         fixed20_12 cur_latency_mclk, cur_latency_sclk;
2853         fixed20_12 disp_latency, disp_latency_overhead, disp_drain_rate,
2854                 disp_drain_rate2, read_return_rate;
2855         fixed20_12 time_disp1_drop_priority;
2856         int c;
2857         int cur_size = 16;       /* in octawords */
2858         int critical_point = 0, critical_point2;
2859 /*      uint32_t read_return_rate, time_disp1_drop_priority; */
2860         int stop_req, max_stop_req;
2861         struct drm_display_mode *mode1 = NULL;
2862         struct drm_display_mode *mode2 = NULL;
2863         uint32_t pixel_bytes1 = 0;
2864         uint32_t pixel_bytes2 = 0;
2865
2866         radeon_update_display_priority(rdev);
2867
2868         if (rdev->mode_info.crtcs[0]->base.enabled) {
2869                 mode1 = &rdev->mode_info.crtcs[0]->base.mode;
2870                 pixel_bytes1 = rdev->mode_info.crtcs[0]->base.fb->bits_per_pixel / 8;
2871         }
2872         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
2873                 if (rdev->mode_info.crtcs[1]->base.enabled) {
2874                         mode2 = &rdev->mode_info.crtcs[1]->base.mode;
2875                         pixel_bytes2 = rdev->mode_info.crtcs[1]->base.fb->bits_per_pixel / 8;
2876                 }
2877         }
2878
2879         min_mem_eff.full = dfixed_const_8(0);
2880         /* get modes */
2881         if ((rdev->disp_priority == 2) && ASIC_IS_R300(rdev)) {
2882                 uint32_t mc_init_misc_lat_timer = RREG32(R300_MC_INIT_MISC_LAT_TIMER);
2883                 mc_init_misc_lat_timer &= ~(R300_MC_DISP1R_INIT_LAT_MASK << R300_MC_DISP1R_INIT_LAT_SHIFT);
2884                 mc_init_misc_lat_timer &= ~(R300_MC_DISP0R_INIT_LAT_MASK << R300_MC_DISP0R_INIT_LAT_SHIFT);
2885                 /* check crtc enables */
2886                 if (mode2)
2887                         mc_init_misc_lat_timer |= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT);
2888                 if (mode1)
2889                         mc_init_misc_lat_timer |= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT);
2890                 WREG32(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer);
2891         }
2892
2893         /*
2894          * determine is there is enough bw for current mode
2895          */
2896         sclk_ff = rdev->pm.sclk;
2897         mclk_ff = rdev->pm.mclk;
2898
2899         temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1);
2900         temp_ff.full = dfixed_const(temp);
2901         mem_bw.full = dfixed_mul(mclk_ff, temp_ff);
2902
2903         pix_clk.full = 0;
2904         pix_clk2.full = 0;
2905         peak_disp_bw.full = 0;
2906         if (mode1) {
2907                 temp_ff.full = dfixed_const(1000);
2908                 pix_clk.full = dfixed_const(mode1->clock); /* convert to fixed point */
2909                 pix_clk.full = dfixed_div(pix_clk, temp_ff);
2910                 temp_ff.full = dfixed_const(pixel_bytes1);
2911                 peak_disp_bw.full += dfixed_mul(pix_clk, temp_ff);
2912         }
2913         if (mode2) {
2914                 temp_ff.full = dfixed_const(1000);
2915                 pix_clk2.full = dfixed_const(mode2->clock); /* convert to fixed point */
2916                 pix_clk2.full = dfixed_div(pix_clk2, temp_ff);
2917                 temp_ff.full = dfixed_const(pixel_bytes2);
2918                 peak_disp_bw.full += dfixed_mul(pix_clk2, temp_ff);
2919         }
2920
2921         mem_bw.full = dfixed_mul(mem_bw, min_mem_eff);
2922         if (peak_disp_bw.full >= mem_bw.full) {
2923                 DRM_ERROR("You may not have enough display bandwidth for current mode\n"
2924                           "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n");
2925         }
2926
2927         /*  Get values from the EXT_MEM_CNTL register...converting its contents. */
2928         temp = RREG32(RADEON_MEM_TIMING_CNTL);
2929         if ((rdev->family == CHIP_RV100) || (rdev->flags & RADEON_IS_IGP)) { /* RV100, M6, IGPs */
2930                 mem_trcd = ((temp >> 2) & 0x3) + 1;
2931                 mem_trp  = ((temp & 0x3)) + 1;
2932                 mem_tras = ((temp & 0x70) >> 4) + 1;
2933         } else if (rdev->family == CHIP_R300 ||
2934                    rdev->family == CHIP_R350) { /* r300, r350 */
2935                 mem_trcd = (temp & 0x7) + 1;
2936                 mem_trp = ((temp >> 8) & 0x7) + 1;
2937                 mem_tras = ((temp >> 11) & 0xf) + 4;
2938         } else if (rdev->family == CHIP_RV350 ||
2939                    rdev->family <= CHIP_RV380) {
2940                 /* rv3x0 */
2941                 mem_trcd = (temp & 0x7) + 3;
2942                 mem_trp = ((temp >> 8) & 0x7) + 3;
2943                 mem_tras = ((temp >> 11) & 0xf) + 6;
2944         } else if (rdev->family == CHIP_R420 ||
2945                    rdev->family == CHIP_R423 ||
2946                    rdev->family == CHIP_RV410) {
2947                 /* r4xx */
2948                 mem_trcd = (temp & 0xf) + 3;
2949                 if (mem_trcd > 15)
2950                         mem_trcd = 15;
2951                 mem_trp = ((temp >> 8) & 0xf) + 3;
2952                 if (mem_trp > 15)
2953                         mem_trp = 15;
2954                 mem_tras = ((temp >> 12) & 0x1f) + 6;
2955                 if (mem_tras > 31)
2956                         mem_tras = 31;
2957         } else { /* RV200, R200 */
2958                 mem_trcd = (temp & 0x7) + 1;
2959                 mem_trp = ((temp >> 8) & 0x7) + 1;
2960                 mem_tras = ((temp >> 12) & 0xf) + 4;
2961         }
2962         /* convert to FF */
2963         trcd_ff.full = dfixed_const(mem_trcd);
2964         trp_ff.full = dfixed_const(mem_trp);
2965         tras_ff.full = dfixed_const(mem_tras);
2966
2967         /* Get values from the MEM_SDRAM_MODE_REG register...converting its */
2968         temp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
2969         data = (temp & (7 << 20)) >> 20;
2970         if ((rdev->family == CHIP_RV100) || rdev->flags & RADEON_IS_IGP) {
2971                 if (rdev->family == CHIP_RS480) /* don't think rs400 */
2972                         tcas_ff = memtcas_rs480_ff[data];
2973                 else
2974                         tcas_ff = memtcas_ff[data];
2975         } else
2976                 tcas_ff = memtcas2_ff[data];
2977
2978         if (rdev->family == CHIP_RS400 ||
2979             rdev->family == CHIP_RS480) {
2980                 /* extra cas latency stored in bits 23-25 0-4 clocks */
2981                 data = (temp >> 23) & 0x7;
2982                 if (data < 5)
2983                         tcas_ff.full += dfixed_const(data);
2984         }
2985
2986         if (ASIC_IS_R300(rdev) && !(rdev->flags & RADEON_IS_IGP)) {
2987                 /* on the R300, Tcas is included in Trbs.
2988                  */
2989                 temp = RREG32(RADEON_MEM_CNTL);
2990                 data = (R300_MEM_NUM_CHANNELS_MASK & temp);
2991                 if (data == 1) {
2992                         if (R300_MEM_USE_CD_CH_ONLY & temp) {
2993                                 temp = RREG32(R300_MC_IND_INDEX);
2994                                 temp &= ~R300_MC_IND_ADDR_MASK;
2995                                 temp |= R300_MC_READ_CNTL_CD_mcind;
2996                                 WREG32(R300_MC_IND_INDEX, temp);
2997                                 temp = RREG32(R300_MC_IND_DATA);
2998                                 data = (R300_MEM_RBS_POSITION_C_MASK & temp);
2999                         } else {
3000                                 temp = RREG32(R300_MC_READ_CNTL_AB);
3001                                 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
3002                         }
3003                 } else {
3004                         temp = RREG32(R300_MC_READ_CNTL_AB);
3005                         data = (R300_MEM_RBS_POSITION_A_MASK & temp);
3006                 }
3007                 if (rdev->family == CHIP_RV410 ||
3008                     rdev->family == CHIP_R420 ||
3009                     rdev->family == CHIP_R423)
3010                         trbs_ff = memtrbs_r4xx[data];
3011                 else
3012                         trbs_ff = memtrbs[data];
3013                 tcas_ff.full += trbs_ff.full;
3014         }
3015
3016         sclk_eff_ff.full = sclk_ff.full;
3017
3018         if (rdev->flags & RADEON_IS_AGP) {
3019                 fixed20_12 agpmode_ff;
3020                 agpmode_ff.full = dfixed_const(radeon_agpmode);
3021                 temp_ff.full = dfixed_const_666(16);
3022                 sclk_eff_ff.full -= dfixed_mul(agpmode_ff, temp_ff);
3023         }
3024         /* TODO PCIE lanes may affect this - agpmode == 16?? */
3025
3026         if (ASIC_IS_R300(rdev)) {
3027                 sclk_delay_ff.full = dfixed_const(250);
3028         } else {
3029                 if ((rdev->family == CHIP_RV100) ||
3030                     rdev->flags & RADEON_IS_IGP) {
3031                         if (rdev->mc.vram_is_ddr)
3032                                 sclk_delay_ff.full = dfixed_const(41);
3033                         else
3034                                 sclk_delay_ff.full = dfixed_const(33);
3035                 } else {
3036                         if (rdev->mc.vram_width == 128)
3037                                 sclk_delay_ff.full = dfixed_const(57);
3038                         else
3039                                 sclk_delay_ff.full = dfixed_const(41);
3040                 }
3041         }
3042
3043         mc_latency_sclk.full = dfixed_div(sclk_delay_ff, sclk_eff_ff);
3044
3045         if (rdev->mc.vram_is_ddr) {
3046                 if (rdev->mc.vram_width == 32) {
3047                         k1.full = dfixed_const(40);
3048                         c  = 3;
3049                 } else {
3050                         k1.full = dfixed_const(20);
3051                         c  = 1;
3052                 }
3053         } else {
3054                 k1.full = dfixed_const(40);
3055                 c  = 3;
3056         }
3057
3058         temp_ff.full = dfixed_const(2);
3059         mc_latency_mclk.full = dfixed_mul(trcd_ff, temp_ff);
3060         temp_ff.full = dfixed_const(c);
3061         mc_latency_mclk.full += dfixed_mul(tcas_ff, temp_ff);
3062         temp_ff.full = dfixed_const(4);
3063         mc_latency_mclk.full += dfixed_mul(tras_ff, temp_ff);
3064         mc_latency_mclk.full += dfixed_mul(trp_ff, temp_ff);
3065         mc_latency_mclk.full += k1.full;
3066
3067         mc_latency_mclk.full = dfixed_div(mc_latency_mclk, mclk_ff);
3068         mc_latency_mclk.full += dfixed_div(temp_ff, sclk_eff_ff);
3069
3070         /*
3071           HW cursor time assuming worst case of full size colour cursor.
3072         */
3073         temp_ff.full = dfixed_const((2 * (cur_size - (rdev->mc.vram_is_ddr + 1))));
3074         temp_ff.full += trcd_ff.full;
3075         if (temp_ff.full < tras_ff.full)
3076                 temp_ff.full = tras_ff.full;
3077         cur_latency_mclk.full = dfixed_div(temp_ff, mclk_ff);
3078
3079         temp_ff.full = dfixed_const(cur_size);
3080         cur_latency_sclk.full = dfixed_div(temp_ff, sclk_eff_ff);
3081         /*
3082           Find the total latency for the display data.
3083         */
3084         disp_latency_overhead.full = dfixed_const(8);
3085         disp_latency_overhead.full = dfixed_div(disp_latency_overhead, sclk_ff);
3086         mc_latency_mclk.full += disp_latency_overhead.full + cur_latency_mclk.full;
3087         mc_latency_sclk.full += disp_latency_overhead.full + cur_latency_sclk.full;
3088
3089         if (mc_latency_mclk.full > mc_latency_sclk.full)
3090                 disp_latency.full = mc_latency_mclk.full;
3091         else
3092                 disp_latency.full = mc_latency_sclk.full;
3093
3094         /* setup Max GRPH_STOP_REQ default value */
3095         if (ASIC_IS_RV100(rdev))
3096                 max_stop_req = 0x5c;
3097         else
3098                 max_stop_req = 0x7c;
3099
3100         if (mode1) {
3101                 /*  CRTC1
3102                     Set GRPH_BUFFER_CNTL register using h/w defined optimal values.
3103                     GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ]
3104                 */
3105                 stop_req = mode1->hdisplay * pixel_bytes1 / 16;
3106
3107                 if (stop_req > max_stop_req)
3108                         stop_req = max_stop_req;
3109
3110                 /*
3111                   Find the drain rate of the display buffer.
3112                 */
3113                 temp_ff.full = dfixed_const((16/pixel_bytes1));
3114                 disp_drain_rate.full = dfixed_div(pix_clk, temp_ff);
3115
3116                 /*
3117                   Find the critical point of the display buffer.
3118                 */
3119                 crit_point_ff.full = dfixed_mul(disp_drain_rate, disp_latency);
3120                 crit_point_ff.full += dfixed_const_half(0);
3121
3122                 critical_point = dfixed_trunc(crit_point_ff);
3123
3124                 if (rdev->disp_priority == 2) {
3125                         critical_point = 0;
3126                 }
3127
3128                 /*
3129                   The critical point should never be above max_stop_req-4.  Setting
3130                   GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time.
3131                 */
3132                 if (max_stop_req - critical_point < 4)
3133                         critical_point = 0;
3134
3135                 if (critical_point == 0 && mode2 && rdev->family == CHIP_R300) {
3136                         /* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/
3137                         critical_point = 0x10;
3138                 }
3139
3140                 temp = RREG32(RADEON_GRPH_BUFFER_CNTL);
3141                 temp &= ~(RADEON_GRPH_STOP_REQ_MASK);
3142                 temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
3143                 temp &= ~(RADEON_GRPH_START_REQ_MASK);
3144                 if ((rdev->family == CHIP_R350) &&
3145                     (stop_req > 0x15)) {
3146                         stop_req -= 0x10;
3147                 }
3148                 temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
3149                 temp |= RADEON_GRPH_BUFFER_SIZE;
3150                 temp &= ~(RADEON_GRPH_CRITICAL_CNTL   |
3151                           RADEON_GRPH_CRITICAL_AT_SOF |
3152                           RADEON_GRPH_STOP_CNTL);
3153                 /*
3154                   Write the result into the register.
3155                 */
3156                 WREG32(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
3157                                                        (critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
3158
3159 #if 0
3160                 if ((rdev->family == CHIP_RS400) ||
3161                     (rdev->family == CHIP_RS480)) {
3162                         /* attempt to program RS400 disp regs correctly ??? */
3163                         temp = RREG32(RS400_DISP1_REG_CNTL);
3164                         temp &= ~(RS400_DISP1_START_REQ_LEVEL_MASK |
3165                                   RS400_DISP1_STOP_REQ_LEVEL_MASK);
3166                         WREG32(RS400_DISP1_REQ_CNTL1, (temp |
3167                                                        (critical_point << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
3168                                                        (critical_point << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
3169                         temp = RREG32(RS400_DMIF_MEM_CNTL1);
3170                         temp &= ~(RS400_DISP1_CRITICAL_POINT_START_MASK |
3171                                   RS400_DISP1_CRITICAL_POINT_STOP_MASK);
3172                         WREG32(RS400_DMIF_MEM_CNTL1, (temp |
3173                                                       (critical_point << RS400_DISP1_CRITICAL_POINT_START_SHIFT) |
3174                                                       (critical_point << RS400_DISP1_CRITICAL_POINT_STOP_SHIFT)));
3175                 }
3176 #endif
3177
3178                 DRM_DEBUG_KMS("GRPH_BUFFER_CNTL from to %x\n",
3179                           /*      (unsigned int)info->SavedReg->grph_buffer_cntl, */
3180                           (unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL));
3181         }
3182
3183         if (mode2) {
3184                 u32 grph2_cntl;
3185                 stop_req = mode2->hdisplay * pixel_bytes2 / 16;
3186
3187                 if (stop_req > max_stop_req)
3188                         stop_req = max_stop_req;
3189
3190                 /*
3191                   Find the drain rate of the display buffer.
3192                 */
3193                 temp_ff.full = dfixed_const((16/pixel_bytes2));
3194                 disp_drain_rate2.full = dfixed_div(pix_clk2, temp_ff);
3195
3196                 grph2_cntl = RREG32(RADEON_GRPH2_BUFFER_CNTL);
3197                 grph2_cntl &= ~(RADEON_GRPH_STOP_REQ_MASK);
3198                 grph2_cntl |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
3199                 grph2_cntl &= ~(RADEON_GRPH_START_REQ_MASK);
3200                 if ((rdev->family == CHIP_R350) &&
3201                     (stop_req > 0x15)) {
3202                         stop_req -= 0x10;
3203                 }
3204                 grph2_cntl |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
3205                 grph2_cntl |= RADEON_GRPH_BUFFER_SIZE;
3206                 grph2_cntl &= ~(RADEON_GRPH_CRITICAL_CNTL   |
3207                           RADEON_GRPH_CRITICAL_AT_SOF |
3208                           RADEON_GRPH_STOP_CNTL);
3209
3210                 if ((rdev->family == CHIP_RS100) ||
3211                     (rdev->family == CHIP_RS200))
3212                         critical_point2 = 0;
3213                 else {
3214                         temp = (rdev->mc.vram_width * rdev->mc.vram_is_ddr + 1)/128;
3215                         temp_ff.full = dfixed_const(temp);
3216                         temp_ff.full = dfixed_mul(mclk_ff, temp_ff);
3217                         if (sclk_ff.full < temp_ff.full)
3218                                 temp_ff.full = sclk_ff.full;
3219
3220                         read_return_rate.full = temp_ff.full;
3221
3222                         if (mode1) {
3223                                 temp_ff.full = read_return_rate.full - disp_drain_rate.full;
3224                                 time_disp1_drop_priority.full = dfixed_div(crit_point_ff, temp_ff);
3225                         } else {
3226                                 time_disp1_drop_priority.full = 0;
3227                         }
3228                         crit_point_ff.full = disp_latency.full + time_disp1_drop_priority.full + disp_latency.full;
3229                         crit_point_ff.full = dfixed_mul(crit_point_ff, disp_drain_rate2);
3230                         crit_point_ff.full += dfixed_const_half(0);
3231
3232                         critical_point2 = dfixed_trunc(crit_point_ff);
3233
3234                         if (rdev->disp_priority == 2) {
3235                                 critical_point2 = 0;
3236                         }
3237
3238                         if (max_stop_req - critical_point2 < 4)
3239                                 critical_point2 = 0;
3240
3241                 }
3242
3243                 if (critical_point2 == 0 && rdev->family == CHIP_R300) {
3244                         /* some R300 cards have problem with this set to 0 */
3245                         critical_point2 = 0x10;
3246                 }
3247
3248                 WREG32(RADEON_GRPH2_BUFFER_CNTL, ((grph2_cntl & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
3249                                                   (critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
3250
3251                 if ((rdev->family == CHIP_RS400) ||
3252                     (rdev->family == CHIP_RS480)) {
3253 #if 0
3254                         /* attempt to program RS400 disp2 regs correctly ??? */
3255                         temp = RREG32(RS400_DISP2_REQ_CNTL1);
3256                         temp &= ~(RS400_DISP2_START_REQ_LEVEL_MASK |
3257                                   RS400_DISP2_STOP_REQ_LEVEL_MASK);
3258                         WREG32(RS400_DISP2_REQ_CNTL1, (temp |
3259                                                        (critical_point2 << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
3260                                                        (critical_point2 << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
3261                         temp = RREG32(RS400_DISP2_REQ_CNTL2);
3262                         temp &= ~(RS400_DISP2_CRITICAL_POINT_START_MASK |
3263                                   RS400_DISP2_CRITICAL_POINT_STOP_MASK);
3264                         WREG32(RS400_DISP2_REQ_CNTL2, (temp |
3265                                                        (critical_point2 << RS400_DISP2_CRITICAL_POINT_START_SHIFT) |
3266                                                        (critical_point2 << RS400_DISP2_CRITICAL_POINT_STOP_SHIFT)));
3267 #endif
3268                         WREG32(RS400_DISP2_REQ_CNTL1, 0x105DC1CC);
3269                         WREG32(RS400_DISP2_REQ_CNTL2, 0x2749D000);
3270                         WREG32(RS400_DMIF_MEM_CNTL1,  0x29CA71DC);
3271                         WREG32(RS400_DISP1_REQ_CNTL1, 0x28FBC3AC);
3272                 }
3273
3274                 DRM_DEBUG_KMS("GRPH2_BUFFER_CNTL from to %x\n",
3275                           (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL));
3276         }
3277 }
3278
3279 static void r100_cs_track_texture_print(struct r100_cs_track_texture *t)
3280 {
3281         DRM_ERROR("pitch                      %d\n", t->pitch);
3282         DRM_ERROR("use_pitch                  %d\n", t->use_pitch);
3283         DRM_ERROR("width                      %d\n", t->width);
3284         DRM_ERROR("width_11                   %d\n", t->width_11);
3285         DRM_ERROR("height                     %d\n", t->height);
3286         DRM_ERROR("height_11                  %d\n", t->height_11);
3287         DRM_ERROR("num levels                 %d\n", t->num_levels);
3288         DRM_ERROR("depth                      %d\n", t->txdepth);
3289         DRM_ERROR("bpp                        %d\n", t->cpp);
3290         DRM_ERROR("coordinate type            %d\n", t->tex_coord_type);
3291         DRM_ERROR("width round to power of 2  %d\n", t->roundup_w);
3292         DRM_ERROR("height round to power of 2 %d\n", t->roundup_h);
3293         DRM_ERROR("compress format            %d\n", t->compress_format);
3294 }
3295
3296 static int r100_track_compress_size(int compress_format, int w, int h)
3297 {
3298         int block_width, block_height, block_bytes;
3299         int wblocks, hblocks;
3300         int min_wblocks;
3301         int sz;
3302
3303         block_width = 4;
3304         block_height = 4;
3305
3306         switch (compress_format) {
3307         case R100_TRACK_COMP_DXT1:
3308                 block_bytes = 8;
3309                 min_wblocks = 4;
3310                 break;
3311         default:
3312         case R100_TRACK_COMP_DXT35:
3313                 block_bytes = 16;
3314                 min_wblocks = 2;
3315                 break;
3316         }
3317
3318         hblocks = (h + block_height - 1) / block_height;
3319         wblocks = (w + block_width - 1) / block_width;
3320         if (wblocks < min_wblocks)
3321                 wblocks = min_wblocks;
3322         sz = wblocks * hblocks * block_bytes;
3323         return sz;
3324 }
3325
3326 static int r100_cs_track_cube(struct radeon_device *rdev,
3327                               struct r100_cs_track *track, unsigned idx)
3328 {
3329         unsigned face, w, h;
3330         struct radeon_bo *cube_robj;
3331         unsigned long size;
3332         unsigned compress_format = track->textures[idx].compress_format;
3333
3334         for (face = 0; face < 5; face++) {
3335                 cube_robj = track->textures[idx].cube_info[face].robj;
3336                 w = track->textures[idx].cube_info[face].width;
3337                 h = track->textures[idx].cube_info[face].height;
3338
3339                 if (compress_format) {
3340                         size = r100_track_compress_size(compress_format, w, h);
3341                 } else
3342                         size = w * h;
3343                 size *= track->textures[idx].cpp;
3344
3345                 size += track->textures[idx].cube_info[face].offset;
3346
3347                 if (size > radeon_bo_size(cube_robj)) {
3348                         DRM_ERROR("Cube texture offset greater than object size %lu %lu\n",
3349                                   size, radeon_bo_size(cube_robj));
3350                         r100_cs_track_texture_print(&track->textures[idx]);
3351                         return -1;
3352                 }
3353         }
3354         return 0;
3355 }
3356
3357 static int r100_cs_track_texture_check(struct radeon_device *rdev,
3358                                        struct r100_cs_track *track)
3359 {
3360         struct radeon_bo *robj;
3361         unsigned long size;
3362         unsigned u, i, w, h, d;
3363         int ret;
3364
3365         for (u = 0; u < track->num_texture; u++) {
3366                 if (!track->textures[u].enabled)
3367                         continue;
3368                 if (track->textures[u].lookup_disable)
3369                         continue;
3370                 robj = track->textures[u].robj;
3371                 if (robj == NULL) {
3372                         DRM_ERROR("No texture bound to unit %u\n", u);
3373                         return -EINVAL;
3374                 }
3375                 size = 0;
3376                 for (i = 0; i <= track->textures[u].num_levels; i++) {
3377                         if (track->textures[u].use_pitch) {
3378                                 if (rdev->family < CHIP_R300)
3379                                         w = (track->textures[u].pitch / track->textures[u].cpp) / (1 << i);
3380                                 else
3381                                         w = track->textures[u].pitch / (1 << i);
3382                         } else {
3383                                 w = track->textures[u].width;
3384                                 if (rdev->family >= CHIP_RV515)
3385                                         w |= track->textures[u].width_11;
3386                                 w = w / (1 << i);
3387                                 if (track->textures[u].roundup_w)
3388                                         w = roundup_pow_of_two(w);
3389                         }
3390                         h = track->textures[u].height;
3391                         if (rdev->family >= CHIP_RV515)
3392                                 h |= track->textures[u].height_11;
3393                         h = h / (1 << i);
3394                         if (track->textures[u].roundup_h)
3395                                 h = roundup_pow_of_two(h);
3396                         if (track->textures[u].tex_coord_type == 1) {
3397                                 d = (1 << track->textures[u].txdepth) / (1 << i);
3398                                 if (!d)
3399                                         d = 1;
3400                         } else {
3401                                 d = 1;
3402                         }
3403                         if (track->textures[u].compress_format) {
3404
3405                                 size += r100_track_compress_size(track->textures[u].compress_format, w, h) * d;
3406                                 /* compressed textures are block based */
3407                         } else
3408                                 size += w * h * d;
3409                 }
3410                 size *= track->textures[u].cpp;
3411
3412                 switch (track->textures[u].tex_coord_type) {
3413                 case 0:
3414                 case 1:
3415                         break;
3416                 case 2:
3417                         if (track->separate_cube) {
3418                                 ret = r100_cs_track_cube(rdev, track, u);
3419                                 if (ret)
3420                                         return ret;
3421                         } else
3422                                 size *= 6;
3423                         break;
3424                 default:
3425                         DRM_ERROR("Invalid texture coordinate type %u for unit "
3426                                   "%u\n", track->textures[u].tex_coord_type, u);
3427                         return -EINVAL;
3428                 }
3429                 if (size > radeon_bo_size(robj)) {
3430                         DRM_ERROR("Texture of unit %u needs %lu bytes but is "
3431                                   "%lu\n", u, size, radeon_bo_size(robj));
3432                         r100_cs_track_texture_print(&track->textures[u]);
3433                         return -EINVAL;
3434                 }
3435         }
3436         return 0;
3437 }
3438
3439 int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track)
3440 {
3441         unsigned i;
3442         unsigned long size;
3443         unsigned prim_walk;
3444         unsigned nverts;
3445         unsigned num_cb = track->cb_dirty ? track->num_cb : 0;
3446
3447         if (num_cb && !track->zb_cb_clear && !track->color_channel_mask &&
3448             !track->blend_read_enable)
3449                 num_cb = 0;
3450
3451         for (i = 0; i < num_cb; i++) {
3452                 if (track->cb[i].robj == NULL) {
3453                         DRM_ERROR("[drm] No buffer for color buffer %d !\n", i);
3454                         return -EINVAL;
3455                 }
3456                 size = track->cb[i].pitch * track->cb[i].cpp * track->maxy;
3457                 size += track->cb[i].offset;
3458                 if (size > radeon_bo_size(track->cb[i].robj)) {
3459                         DRM_ERROR("[drm] Buffer too small for color buffer %d "
3460                                   "(need %lu have %lu) !\n", i, size,
3461                                   radeon_bo_size(track->cb[i].robj));
3462                         DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n",
3463                                   i, track->cb[i].pitch, track->cb[i].cpp,
3464                                   track->cb[i].offset, track->maxy);
3465                         return -EINVAL;
3466                 }
3467         }
3468         track->cb_dirty = false;
3469
3470         if (track->zb_dirty && track->z_enabled) {
3471                 if (track->zb.robj == NULL) {
3472                         DRM_ERROR("[drm] No buffer for z buffer !\n");
3473                         return -EINVAL;
3474                 }
3475                 size = track->zb.pitch * track->zb.cpp * track->maxy;
3476                 size += track->zb.offset;
3477                 if (size > radeon_bo_size(track->zb.robj)) {
3478                         DRM_ERROR("[drm] Buffer too small for z buffer "
3479                                   "(need %lu have %lu) !\n", size,
3480                                   radeon_bo_size(track->zb.robj));
3481                         DRM_ERROR("[drm] zbuffer (%u %u %u %u)\n",
3482                                   track->zb.pitch, track->zb.cpp,
3483                                   track->zb.offset, track->maxy);
3484                         return -EINVAL;
3485                 }
3486         }
3487         track->zb_dirty = false;
3488
3489         if (track->aa_dirty && track->aaresolve) {
3490                 if (track->aa.robj == NULL) {
3491                         DRM_ERROR("[drm] No buffer for AA resolve buffer %d !\n", i);
3492                         return -EINVAL;
3493                 }
3494                 /* I believe the format comes from colorbuffer0. */
3495                 size = track->aa.pitch * track->cb[0].cpp * track->maxy;
3496                 size += track->aa.offset;
3497                 if (size > radeon_bo_size(track->aa.robj)) {
3498                         DRM_ERROR("[drm] Buffer too small for AA resolve buffer %d "
3499                                   "(need %lu have %lu) !\n", i, size,
3500                                   radeon_bo_size(track->aa.robj));
3501                         DRM_ERROR("[drm] AA resolve buffer %d (%u %u %u %u)\n",
3502                                   i, track->aa.pitch, track->cb[0].cpp,
3503                                   track->aa.offset, track->maxy);
3504                         return -EINVAL;
3505                 }
3506         }
3507         track->aa_dirty = false;
3508
3509         prim_walk = (track->vap_vf_cntl >> 4) & 0x3;
3510         if (track->vap_vf_cntl & (1 << 14)) {
3511                 nverts = track->vap_alt_nverts;
3512         } else {
3513                 nverts = (track->vap_vf_cntl >> 16) & 0xFFFF;
3514         }
3515         switch (prim_walk) {
3516         case 1:
3517                 for (i = 0; i < track->num_arrays; i++) {
3518                         size = track->arrays[i].esize * track->max_indx * 4;
3519                         if (track->arrays[i].robj == NULL) {
3520                                 DRM_ERROR("(PW %u) Vertex array %u no buffer "
3521                                           "bound\n", prim_walk, i);
3522                                 return -EINVAL;
3523                         }
3524                         if (size > radeon_bo_size(track->arrays[i].robj)) {
3525                                 dev_err(rdev->dev, "(PW %u) Vertex array %u "
3526                                         "need %lu dwords have %lu dwords\n",
3527                                         prim_walk, i, size >> 2,
3528                                         radeon_bo_size(track->arrays[i].robj)
3529                                         >> 2);
3530                                 DRM_ERROR("Max indices %u\n", track->max_indx);
3531                                 return -EINVAL;
3532                         }
3533                 }
3534                 break;
3535         case 2:
3536                 for (i = 0; i < track->num_arrays; i++) {
3537                         size = track->arrays[i].esize * (nverts - 1) * 4;
3538                         if (track->arrays[i].robj == NULL) {
3539                                 DRM_ERROR("(PW %u) Vertex array %u no buffer "
3540                                           "bound\n", prim_walk, i);
3541                                 return -EINVAL;
3542                         }
3543                         if (size > radeon_bo_size(track->arrays[i].robj)) {
3544                                 dev_err(rdev->dev, "(PW %u) Vertex array %u "
3545                                         "need %lu dwords have %lu dwords\n",
3546                                         prim_walk, i, size >> 2,
3547                                         radeon_bo_size(track->arrays[i].robj)
3548                                         >> 2);
3549                                 return -EINVAL;
3550                         }
3551                 }
3552                 break;
3553         case 3:
3554                 size = track->vtx_size * nverts;
3555                 if (size != track->immd_dwords) {
3556                         DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n",
3557                                   track->immd_dwords, size);
3558                         DRM_ERROR("VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n",
3559                                   nverts, track->vtx_size);
3560                         return -EINVAL;
3561                 }
3562                 break;
3563         default:
3564                 DRM_ERROR("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n",
3565                           prim_walk);
3566                 return -EINVAL;
3567         }
3568
3569         if (track->tex_dirty) {
3570                 track->tex_dirty = false;
3571                 return r100_cs_track_texture_check(rdev, track);
3572         }
3573         return 0;
3574 }
3575
3576 void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track)
3577 {
3578         unsigned i, face;
3579
3580         track->cb_dirty = true;
3581         track->zb_dirty = true;
3582         track->tex_dirty = true;
3583         track->aa_dirty = true;
3584
3585         if (rdev->family < CHIP_R300) {
3586                 track->num_cb = 1;
3587                 if (rdev->family <= CHIP_RS200)
3588                         track->num_texture = 3;
3589                 else
3590                         track->num_texture = 6;
3591                 track->maxy = 2048;
3592                 track->separate_cube = 1;
3593         } else {
3594                 track->num_cb = 4;
3595                 track->num_texture = 16;
3596                 track->maxy = 4096;
3597                 track->separate_cube = 0;
3598                 track->aaresolve = false;
3599                 track->aa.robj = NULL;
3600         }
3601
3602         for (i = 0; i < track->num_cb; i++) {
3603                 track->cb[i].robj = NULL;
3604                 track->cb[i].pitch = 8192;
3605                 track->cb[i].cpp = 16;
3606                 track->cb[i].offset = 0;
3607         }
3608         track->z_enabled = true;
3609         track->zb.robj = NULL;
3610         track->zb.pitch = 8192;
3611         track->zb.cpp = 4;
3612         track->zb.offset = 0;
3613         track->vtx_size = 0x7F;
3614         track->immd_dwords = 0xFFFFFFFFUL;
3615         track->num_arrays = 11;
3616         track->max_indx = 0x00FFFFFFUL;
3617         for (i = 0; i < track->num_arrays; i++) {
3618                 track->arrays[i].robj = NULL;
3619                 track->arrays[i].esize = 0x7F;
3620         }
3621         for (i = 0; i < track->num_texture; i++) {
3622                 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
3623                 track->textures[i].pitch = 16536;
3624                 track->textures[i].width = 16536;
3625                 track->textures[i].height = 16536;
3626                 track->textures[i].width_11 = 1 << 11;
3627                 track->textures[i].height_11 = 1 << 11;
3628                 track->textures[i].num_levels = 12;
3629                 if (rdev->family <= CHIP_RS200) {
3630                         track->textures[i].tex_coord_type = 0;
3631                         track->textures[i].txdepth = 0;
3632                 } else {
3633                         track->textures[i].txdepth = 16;
3634                         track->textures[i].tex_coord_type = 1;
3635                 }
3636                 track->textures[i].cpp = 64;
3637                 track->textures[i].robj = NULL;
3638                 /* CS IB emission code makes sure texture unit are disabled */
3639                 track->textures[i].enabled = false;
3640                 track->textures[i].lookup_disable = false;
3641                 track->textures[i].roundup_w = true;
3642                 track->textures[i].roundup_h = true;
3643                 if (track->separate_cube)
3644                         for (face = 0; face < 5; face++) {
3645                                 track->textures[i].cube_info[face].robj = NULL;
3646                                 track->textures[i].cube_info[face].width = 16536;
3647                                 track->textures[i].cube_info[face].height = 16536;
3648                                 track->textures[i].cube_info[face].offset = 0;
3649                         }
3650         }
3651 }
3652
3653 int r100_ring_test(struct radeon_device *rdev, struct radeon_cp *cp)
3654 {
3655         uint32_t scratch;
3656         uint32_t tmp = 0;
3657         unsigned i;
3658         int r;
3659
3660         r = radeon_scratch_get(rdev, &scratch);
3661         if (r) {
3662                 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
3663                 return r;
3664         }
3665         WREG32(scratch, 0xCAFEDEAD);
3666         r = radeon_ring_lock(rdev, cp, 2);
3667         if (r) {
3668                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
3669                 radeon_scratch_free(rdev, scratch);
3670                 return r;
3671         }
3672         radeon_ring_write(cp, PACKET0(scratch, 0));
3673         radeon_ring_write(cp, 0xDEADBEEF);
3674         radeon_ring_unlock_commit(rdev, cp);
3675         for (i = 0; i < rdev->usec_timeout; i++) {
3676                 tmp = RREG32(scratch);
3677                 if (tmp == 0xDEADBEEF) {
3678                         break;
3679                 }
3680                 DRM_UDELAY(1);
3681         }
3682         if (i < rdev->usec_timeout) {
3683                 DRM_INFO("ring test succeeded in %d usecs\n", i);
3684         } else {
3685                 DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n",
3686                           scratch, tmp);
3687                 r = -EINVAL;
3688         }
3689         radeon_scratch_free(rdev, scratch);
3690         return r;
3691 }
3692
3693 void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
3694 {
3695         struct radeon_cp *cp = &rdev->cp;
3696
3697         radeon_ring_write(cp, PACKET0(RADEON_CP_IB_BASE, 1));
3698         radeon_ring_write(cp, ib->gpu_addr);
3699         radeon_ring_write(cp, ib->length_dw);
3700 }
3701
3702 int r100_ib_test(struct radeon_device *rdev)
3703 {
3704         struct radeon_ib *ib;
3705         uint32_t scratch;
3706         uint32_t tmp = 0;
3707         unsigned i;
3708         int r;
3709
3710         r = radeon_scratch_get(rdev, &scratch);
3711         if (r) {
3712                 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
3713                 return r;
3714         }
3715         WREG32(scratch, 0xCAFEDEAD);
3716         r = radeon_ib_get(rdev, RADEON_RING_TYPE_GFX_INDEX, &ib);
3717         if (r) {
3718                 return r;
3719         }
3720         ib->ptr[0] = PACKET0(scratch, 0);
3721         ib->ptr[1] = 0xDEADBEEF;
3722         ib->ptr[2] = PACKET2(0);
3723         ib->ptr[3] = PACKET2(0);
3724         ib->ptr[4] = PACKET2(0);
3725         ib->ptr[5] = PACKET2(0);
3726         ib->ptr[6] = PACKET2(0);
3727         ib->ptr[7] = PACKET2(0);
3728         ib->length_dw = 8;
3729         r = radeon_ib_schedule(rdev, ib);
3730         if (r) {
3731                 radeon_scratch_free(rdev, scratch);
3732                 radeon_ib_free(rdev, &ib);
3733                 return r;
3734         }
3735         r = radeon_fence_wait(ib->fence, false);
3736         if (r) {
3737                 return r;
3738         }
3739         for (i = 0; i < rdev->usec_timeout; i++) {
3740                 tmp = RREG32(scratch);
3741                 if (tmp == 0xDEADBEEF) {
3742                         break;
3743                 }
3744                 DRM_UDELAY(1);
3745         }
3746         if (i < rdev->usec_timeout) {
3747                 DRM_INFO("ib test succeeded in %u usecs\n", i);
3748         } else {
3749                 DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n",
3750                           scratch, tmp);
3751                 r = -EINVAL;
3752         }
3753         radeon_scratch_free(rdev, scratch);
3754         radeon_ib_free(rdev, &ib);
3755         return r;
3756 }
3757
3758 void r100_ib_fini(struct radeon_device *rdev)
3759 {
3760         radeon_ib_pool_fini(rdev);
3761 }
3762
3763 int r100_ib_init(struct radeon_device *rdev)
3764 {
3765         int r;
3766
3767         r = radeon_ib_pool_init(rdev);
3768         if (r) {
3769                 dev_err(rdev->dev, "failed initializing IB pool (%d).\n", r);
3770                 r100_ib_fini(rdev);
3771                 return r;
3772         }
3773         r = r100_ib_test(rdev);
3774         if (r) {
3775                 dev_err(rdev->dev, "failed testing IB (%d).\n", r);
3776                 r100_ib_fini(rdev);
3777                 return r;
3778         }
3779         return 0;
3780 }
3781
3782 void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save)
3783 {
3784         /* Shutdown CP we shouldn't need to do that but better be safe than
3785          * sorry
3786          */
3787         rdev->cp.ready = false;
3788         WREG32(R_000740_CP_CSQ_CNTL, 0);
3789
3790         /* Save few CRTC registers */
3791         save->GENMO_WT = RREG8(R_0003C2_GENMO_WT);
3792         save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL);
3793         save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL);
3794         save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET);
3795         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3796                 save->CRTC2_GEN_CNTL = RREG32(R_0003F8_CRTC2_GEN_CNTL);
3797                 save->CUR2_OFFSET = RREG32(R_000360_CUR2_OFFSET);
3798         }
3799
3800         /* Disable VGA aperture access */
3801         WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & save->GENMO_WT);
3802         /* Disable cursor, overlay, crtc */
3803         WREG32(R_000260_CUR_OFFSET, save->CUR_OFFSET | S_000260_CUR_LOCK(1));
3804         WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL |
3805                                         S_000054_CRTC_DISPLAY_DIS(1));
3806         WREG32(R_000050_CRTC_GEN_CNTL,
3807                         (C_000050_CRTC_CUR_EN & save->CRTC_GEN_CNTL) |
3808                         S_000050_CRTC_DISP_REQ_EN_B(1));
3809         WREG32(R_000420_OV0_SCALE_CNTL,
3810                 C_000420_OV0_OVERLAY_EN & RREG32(R_000420_OV0_SCALE_CNTL));
3811         WREG32(R_000260_CUR_OFFSET, C_000260_CUR_LOCK & save->CUR_OFFSET);
3812         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3813                 WREG32(R_000360_CUR2_OFFSET, save->CUR2_OFFSET |
3814                                                 S_000360_CUR2_LOCK(1));
3815                 WREG32(R_0003F8_CRTC2_GEN_CNTL,
3816                         (C_0003F8_CRTC2_CUR_EN & save->CRTC2_GEN_CNTL) |
3817                         S_0003F8_CRTC2_DISPLAY_DIS(1) |
3818                         S_0003F8_CRTC2_DISP_REQ_EN_B(1));
3819                 WREG32(R_000360_CUR2_OFFSET,
3820                         C_000360_CUR2_LOCK & save->CUR2_OFFSET);
3821         }
3822 }
3823
3824 void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save)
3825 {
3826         /* Update base address for crtc */
3827         WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
3828         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3829                 WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
3830         }
3831         /* Restore CRTC registers */
3832         WREG8(R_0003C2_GENMO_WT, save->GENMO_WT);
3833         WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL);
3834         WREG32(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL);
3835         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3836                 WREG32(R_0003F8_CRTC2_GEN_CNTL, save->CRTC2_GEN_CNTL);
3837         }
3838 }
3839
3840 void r100_vga_render_disable(struct radeon_device *rdev)
3841 {
3842         u32 tmp;
3843
3844         tmp = RREG8(R_0003C2_GENMO_WT);
3845         WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & tmp);
3846 }
3847
3848 static void r100_debugfs(struct radeon_device *rdev)
3849 {
3850         int r;
3851
3852         r = r100_debugfs_mc_info_init(rdev);
3853         if (r)
3854                 dev_warn(rdev->dev, "Failed to create r100_mc debugfs file.\n");
3855 }
3856
3857 static void r100_mc_program(struct radeon_device *rdev)
3858 {
3859         struct r100_mc_save save;
3860
3861         /* Stops all mc clients */
3862         r100_mc_stop(rdev, &save);
3863         if (rdev->flags & RADEON_IS_AGP) {
3864                 WREG32(R_00014C_MC_AGP_LOCATION,
3865                         S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) |
3866                         S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
3867                 WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
3868                 if (rdev->family > CHIP_RV200)
3869                         WREG32(R_00015C_AGP_BASE_2,
3870                                 upper_32_bits(rdev->mc.agp_base) & 0xff);
3871         } else {
3872                 WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF);
3873                 WREG32(R_000170_AGP_BASE, 0);
3874                 if (rdev->family > CHIP_RV200)
3875                         WREG32(R_00015C_AGP_BASE_2, 0);
3876         }
3877         /* Wait for mc idle */
3878         if (r100_mc_wait_for_idle(rdev))
3879                 dev_warn(rdev->dev, "Wait for MC idle timeout.\n");
3880         /* Program MC, should be a 32bits limited address space */
3881         WREG32(R_000148_MC_FB_LOCATION,
3882                 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
3883                 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
3884         r100_mc_resume(rdev, &save);
3885 }
3886
3887 void r100_clock_startup(struct radeon_device *rdev)
3888 {
3889         u32 tmp;
3890
3891         if (radeon_dynclks != -1 && radeon_dynclks)
3892                 radeon_legacy_set_clock_gating(rdev, 1);
3893         /* We need to force on some of the block */
3894         tmp = RREG32_PLL(R_00000D_SCLK_CNTL);
3895         tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
3896         if ((rdev->family == CHIP_RV250) || (rdev->family == CHIP_RV280))
3897                 tmp |= S_00000D_FORCE_DISP1(1) | S_00000D_FORCE_DISP2(1);
3898         WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
3899 }
3900
3901 static int r100_startup(struct radeon_device *rdev)
3902 {
3903         int r;
3904
3905         /* set common regs */
3906         r100_set_common_regs(rdev);
3907         /* program mc */
3908         r100_mc_program(rdev);
3909         /* Resume clock */
3910         r100_clock_startup(rdev);
3911         /* Initialize GART (initialize after TTM so we can allocate
3912          * memory through TTM but finalize after TTM) */
3913         r100_enable_bm(rdev);
3914         if (rdev->flags & RADEON_IS_PCI) {
3915                 r = r100_pci_gart_enable(rdev);
3916                 if (r)
3917                         return r;
3918         }
3919
3920         /* allocate wb buffer */
3921         r = radeon_wb_init(rdev);
3922         if (r)
3923                 return r;
3924
3925         /* Enable IRQ */
3926         r100_irq_set(rdev);
3927         rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
3928         /* 1M ring buffer */
3929         r = r100_cp_init(rdev, 1024 * 1024);
3930         if (r) {
3931                 dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
3932                 return r;
3933         }
3934         r = r100_ib_init(rdev);
3935         if (r) {
3936                 dev_err(rdev->dev, "failed initializing IB (%d).\n", r);
3937                 return r;
3938         }
3939         return 0;
3940 }
3941
3942 int r100_resume(struct radeon_device *rdev)
3943 {
3944         /* Make sur GART are not working */
3945         if (rdev->flags & RADEON_IS_PCI)
3946                 r100_pci_gart_disable(rdev);
3947         /* Resume clock before doing reset */
3948         r100_clock_startup(rdev);
3949         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
3950         if (radeon_asic_reset(rdev)) {
3951                 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
3952                         RREG32(R_000E40_RBBM_STATUS),
3953                         RREG32(R_0007C0_CP_STAT));
3954         }
3955         /* post */
3956         radeon_combios_asic_init(rdev->ddev);
3957         /* Resume clock after posting */
3958         r100_clock_startup(rdev);
3959         /* Initialize surface registers */
3960         radeon_surface_init(rdev);
3961         return r100_startup(rdev);
3962 }
3963
3964 int r100_suspend(struct radeon_device *rdev)
3965 {
3966         r100_cp_disable(rdev);
3967         radeon_wb_disable(rdev);
3968         r100_irq_disable(rdev);
3969         if (rdev->flags & RADEON_IS_PCI)
3970                 r100_pci_gart_disable(rdev);
3971         return 0;
3972 }
3973
3974 void r100_fini(struct radeon_device *rdev)
3975 {
3976         r100_cp_fini(rdev);
3977         radeon_wb_fini(rdev);
3978         r100_ib_fini(rdev);
3979         radeon_gem_fini(rdev);
3980         if (rdev->flags & RADEON_IS_PCI)
3981                 r100_pci_gart_fini(rdev);
3982         radeon_agp_fini(rdev);
3983         radeon_irq_kms_fini(rdev);
3984         radeon_fence_driver_fini(rdev);
3985         radeon_bo_fini(rdev);
3986         radeon_atombios_fini(rdev);
3987         kfree(rdev->bios);
3988         rdev->bios = NULL;
3989 }
3990
3991 /*
3992  * Due to how kexec works, it can leave the hw fully initialised when it
3993  * boots the new kernel. However doing our init sequence with the CP and
3994  * WB stuff setup causes GPU hangs on the RN50 at least. So at startup
3995  * do some quick sanity checks and restore sane values to avoid this
3996  * problem.
3997  */
3998 void r100_restore_sanity(struct radeon_device *rdev)
3999 {
4000         u32 tmp;
4001
4002         tmp = RREG32(RADEON_CP_CSQ_CNTL);
4003         if (tmp) {
4004                 WREG32(RADEON_CP_CSQ_CNTL, 0);
4005         }
4006         tmp = RREG32(RADEON_CP_RB_CNTL);
4007         if (tmp) {
4008                 WREG32(RADEON_CP_RB_CNTL, 0);
4009         }
4010         tmp = RREG32(RADEON_SCRATCH_UMSK);
4011         if (tmp) {
4012                 WREG32(RADEON_SCRATCH_UMSK, 0);
4013         }
4014 }
4015
4016 int r100_init(struct radeon_device *rdev)
4017 {
4018         int r;
4019
4020         /* Register debugfs file specific to this group of asics */
4021         r100_debugfs(rdev);
4022         /* Disable VGA */
4023         r100_vga_render_disable(rdev);
4024         /* Initialize scratch registers */
4025         radeon_scratch_init(rdev);
4026         /* Initialize surface registers */
4027         radeon_surface_init(rdev);
4028         /* sanity check some register to avoid hangs like after kexec */
4029         r100_restore_sanity(rdev);
4030         /* TODO: disable VGA need to use VGA request */
4031         /* BIOS*/
4032         if (!radeon_get_bios(rdev)) {
4033                 if (ASIC_IS_AVIVO(rdev))
4034                         return -EINVAL;
4035         }
4036         if (rdev->is_atom_bios) {
4037                 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
4038                 return -EINVAL;
4039         } else {
4040                 r = radeon_combios_init(rdev);
4041                 if (r)
4042                         return r;
4043         }
4044         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
4045         if (radeon_asic_reset(rdev)) {
4046                 dev_warn(rdev->dev,
4047                         "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
4048                         RREG32(R_000E40_RBBM_STATUS),
4049                         RREG32(R_0007C0_CP_STAT));
4050         }
4051         /* check if cards are posted or not */
4052         if (radeon_boot_test_post_card(rdev) == false)
4053                 return -EINVAL;
4054         /* Set asic errata */
4055         r100_errata(rdev);
4056         /* Initialize clocks */
4057         radeon_get_clock_info(rdev->ddev);
4058         /* initialize AGP */
4059         if (rdev->flags & RADEON_IS_AGP) {
4060                 r = radeon_agp_init(rdev);
4061                 if (r) {
4062                         radeon_agp_disable(rdev);
4063                 }
4064         }
4065         /* initialize VRAM */
4066         r100_mc_init(rdev);
4067         /* Fence driver */
4068         r = radeon_fence_driver_init(rdev, 1);
4069         if (r)
4070                 return r;
4071         r = radeon_irq_kms_init(rdev);
4072         if (r)
4073                 return r;
4074         /* Memory manager */
4075         r = radeon_bo_init(rdev);
4076         if (r)
4077                 return r;
4078         if (rdev->flags & RADEON_IS_PCI) {
4079                 r = r100_pci_gart_init(rdev);
4080                 if (r)
4081                         return r;
4082         }
4083         r100_set_safe_registers(rdev);
4084         rdev->accel_working = true;
4085         r = r100_startup(rdev);
4086         if (r) {
4087                 /* Somethings want wront with the accel init stop accel */
4088                 dev_err(rdev->dev, "Disabling GPU acceleration\n");
4089                 r100_cp_fini(rdev);
4090                 radeon_wb_fini(rdev);
4091                 r100_ib_fini(rdev);
4092                 radeon_irq_kms_fini(rdev);
4093                 if (rdev->flags & RADEON_IS_PCI)
4094                         r100_pci_gart_fini(rdev);
4095                 rdev->accel_working = false;
4096         }
4097         return 0;
4098 }
4099
4100 uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg)
4101 {
4102         if (reg < rdev->rmmio_size)
4103                 return readl(((void __iomem *)rdev->rmmio) + reg);
4104         else {
4105                 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
4106                 return readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
4107         }
4108 }
4109
4110 void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
4111 {
4112         if (reg < rdev->rmmio_size)
4113                 writel(v, ((void __iomem *)rdev->rmmio) + reg);
4114         else {
4115                 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
4116                 writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
4117         }
4118 }
4119
4120 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg)
4121 {
4122         if (reg < rdev->rio_mem_size)
4123                 return ioread32(rdev->rio_mem + reg);
4124         else {
4125                 iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX);
4126                 return ioread32(rdev->rio_mem + RADEON_MM_DATA);
4127         }
4128 }
4129
4130 void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v)
4131 {
4132         if (reg < rdev->rio_mem_size)
4133                 iowrite32(v, rdev->rio_mem + reg);
4134         else {
4135                 iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX);
4136                 iowrite32(v, rdev->rio_mem + RADEON_MM_DATA);
4137         }
4138 }