2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Christian König.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Christian König
27 #include <linux/hdmi.h>
29 #include <drm/radeon_drm.h>
31 #include "radeon_asic.h"
32 #include "evergreend.h"
36 * update the N and CTS parameters for a given pixel clock rate
38 static void evergreen_hdmi_update_ACR(struct drm_encoder *encoder, uint32_t clock)
40 struct drm_device *dev = encoder->dev;
41 struct radeon_device *rdev = dev->dev_private;
42 struct radeon_hdmi_acr acr = r600_hdmi_acr(clock);
43 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
44 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
45 uint32_t offset = dig->afmt->offset;
47 WREG32(HDMI_ACR_32_0 + offset, HDMI_ACR_CTS_32(acr.cts_32khz));
48 WREG32(HDMI_ACR_32_1 + offset, acr.n_32khz);
50 WREG32(HDMI_ACR_44_0 + offset, HDMI_ACR_CTS_44(acr.cts_44_1khz));
51 WREG32(HDMI_ACR_44_1 + offset, acr.n_44_1khz);
53 WREG32(HDMI_ACR_48_0 + offset, HDMI_ACR_CTS_48(acr.cts_48khz));
54 WREG32(HDMI_ACR_48_1 + offset, acr.n_48khz);
58 * build a HDMI Video Info Frame
60 static void evergreen_hdmi_update_avi_infoframe(struct drm_encoder *encoder,
61 void *buffer, size_t size)
63 struct drm_device *dev = encoder->dev;
64 struct radeon_device *rdev = dev->dev_private;
65 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
66 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
67 uint32_t offset = dig->afmt->offset;
68 uint8_t *frame = buffer + 3;
70 /* Our header values (type, version, length) should be alright, Intel
71 * is using the same. Checksum function also seems to be OK, it works
72 * fine for audio infoframe. However calculated value is always lower
73 * by 2 in comparison to fglrx. It breaks displaying anything in case
74 * of TVs that strictly check the checksum. Hack it manually here to
75 * workaround this issue. */
78 WREG32(AFMT_AVI_INFO0 + offset,
79 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
80 WREG32(AFMT_AVI_INFO1 + offset,
81 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24));
82 WREG32(AFMT_AVI_INFO2 + offset,
83 frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24));
84 WREG32(AFMT_AVI_INFO3 + offset,
85 frame[0xC] | (frame[0xD] << 8));
89 * update the info frames with the data from the current display mode
91 void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode)
93 struct drm_device *dev = encoder->dev;
94 struct radeon_device *rdev = dev->dev_private;
95 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
96 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
97 u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
98 struct hdmi_avi_infoframe frame;
102 /* Silent, r600_hdmi_enable will raise WARN for us */
103 if (!dig->afmt->enabled)
105 offset = dig->afmt->offset;
107 r600_audio_set_clock(encoder, mode->clock);
109 WREG32(HDMI_VBI_PACKET_CONTROL + offset,
110 HDMI_NULL_SEND); /* send null packets when required */
112 WREG32(AFMT_AUDIO_CRC_CONTROL + offset, 0x1000);
114 WREG32(HDMI_VBI_PACKET_CONTROL + offset,
115 HDMI_NULL_SEND | /* send null packets when required */
116 HDMI_GC_SEND | /* send general control packets */
117 HDMI_GC_CONT); /* send general control packets every frame */
119 WREG32(HDMI_INFOFRAME_CONTROL0 + offset,
120 HDMI_AUDIO_INFO_SEND | /* enable audio info frames (frames won't be set until audio is enabled) */
121 HDMI_AUDIO_INFO_CONT); /* required for audio info values to be updated */
123 WREG32(AFMT_INFOFRAME_CONTROL0 + offset,
124 AFMT_AUDIO_INFO_UPDATE); /* required for audio info values to be updated */
126 WREG32(HDMI_INFOFRAME_CONTROL1 + offset,
127 HDMI_AUDIO_INFO_LINE(2)); /* anything other than 0 */
129 WREG32(HDMI_GC + offset, 0); /* unset HDMI_GC_AVMUTE */
131 WREG32(HDMI_AUDIO_PACKET_CONTROL + offset,
132 HDMI_AUDIO_DELAY_EN(1) | /* set the default audio delay */
133 HDMI_AUDIO_PACKETS_PER_LINE(3)); /* should be suffient for all audio modes and small enough for all hblanks */
135 WREG32(AFMT_AUDIO_PACKET_CONTROL + offset,
136 AFMT_60958_CS_UPDATE); /* allow 60958 channel status fields to be updated */
138 /* fglrx clears sth in AFMT_AUDIO_PACKET_CONTROL2 here */
140 WREG32(HDMI_ACR_PACKET_CONTROL + offset,
141 HDMI_ACR_AUTO_SEND | /* allow hw to sent ACR packets when required */
142 HDMI_ACR_SOURCE); /* select SW CTS value */
144 evergreen_hdmi_update_ACR(encoder, mode->clock);
146 err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
148 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err);
152 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
154 DRM_ERROR("failed to pack AVI infoframe: %zd\n", err);
158 evergreen_hdmi_update_avi_infoframe(encoder, buffer, sizeof(buffer));
160 WREG32_OR(HDMI_INFOFRAME_CONTROL0 + offset,
161 HDMI_AVI_INFO_SEND | /* enable AVI info frames */
162 HDMI_AVI_INFO_CONT); /* required for audio info values to be updated */
164 WREG32_P(HDMI_INFOFRAME_CONTROL1 + offset,
165 HDMI_AVI_INFO_LINE(2), /* anything other than 0 */
166 ~HDMI_AVI_INFO_LINE_MASK);
168 WREG32_OR(AFMT_AUDIO_PACKET_CONTROL + offset,
169 AFMT_AUDIO_SAMPLE_SEND); /* send audio packets */
171 /* it's unknown what these bits do excatly, but it's indeed quite useful for debugging */
172 WREG32(AFMT_RAMP_CONTROL0 + offset, 0x00FFFFFF);
173 WREG32(AFMT_RAMP_CONTROL1 + offset, 0x007FFFFF);
174 WREG32(AFMT_RAMP_CONTROL2 + offset, 0x00000001);
175 WREG32(AFMT_RAMP_CONTROL3 + offset, 0x00000001);