drivers/gpu/drm/radeon/evergreen.c

   1 /*
   2  * Copyright 2010 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Alex Deucher
  23  */
  24 #include <linux/firmware.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/slab.h>
  27 #include "drmP.h"
  28 #include "radeon.h"
  29 #include "radeon_asic.h"
  30 #include "radeon_drm.h"
  31 #include "evergreend.h"
  32 #include "atom.h"
  33 #include "avivod.h"
  34 #include "evergreen_reg.h"
  35 #include "evergreen_blit_shaders.h"
  36
  37 #define EVERGREEN_PFP_UCODE_SIZE 1120
  38 #define EVERGREEN_PM4_UCODE_SIZE 1376
  39
  40 static const u32 crtc_offsets[6] =
  41 {
  42         EVERGREEN_CRTC0_REGISTER_OFFSET,
  43         EVERGREEN_CRTC1_REGISTER_OFFSET,
  44         EVERGREEN_CRTC2_REGISTER_OFFSET,
  45         EVERGREEN_CRTC3_REGISTER_OFFSET,
  46         EVERGREEN_CRTC4_REGISTER_OFFSET,
  47         EVERGREEN_CRTC5_REGISTER_OFFSET
  48 };
  49
  50 static void evergreen_gpu_init(struct radeon_device *rdev);
  51 void evergreen_fini(struct radeon_device *rdev);
  52 void evergreen_pcie_gen2_enable(struct radeon_device *rdev);
  53 extern void cayman_cp_int_cntl_setup(struct radeon_device *rdev,
  54                                      int ring, u32 cp_int_cntl);
  55
  56 void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
  57                              unsigned *bankh, unsigned *mtaspect,
  58                              unsigned *tile_split)
  59 {
  60         *bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK;
  61         *bankh = (tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) & RADEON_TILING_EG_BANKH_MASK;
  62         *mtaspect = (tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK;
  63         *tile_split = (tiling_flags >> RADEON_TILING_EG_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_TILE_SPLIT_MASK;
  64         switch (*bankw) {
  65         default:
  66         case 1: *bankw = EVERGREEN_ADDR_SURF_BANK_WIDTH_1; break;
  67         case 2: *bankw = EVERGREEN_ADDR_SURF_BANK_WIDTH_2; break;
  68         case 4: *bankw = EVERGREEN_ADDR_SURF_BANK_WIDTH_4; break;
  69         case 8: *bankw = EVERGREEN_ADDR_SURF_BANK_WIDTH_8; break;
  70         }
  71         switch (*bankh) {
  72         default:
  73         case 1: *bankh = EVERGREEN_ADDR_SURF_BANK_HEIGHT_1; break;
  74         case 2: *bankh = EVERGREEN_ADDR_SURF_BANK_HEIGHT_2; break;
  75         case 4: *bankh = EVERGREEN_ADDR_SURF_BANK_HEIGHT_4; break;
  76         case 8: *bankh = EVERGREEN_ADDR_SURF_BANK_HEIGHT_8; break;
  77         }
  78         switch (*mtaspect) {
  79         default:
  80         case 1: *mtaspect = EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_1; break;
  81         case 2: *mtaspect = EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_2; break;
  82         case 4: *mtaspect = EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_4; break;
  83         case 8: *mtaspect = EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_8; break;
  84         }
  85 }
  86
  87 void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev)
  88 {
  89         u16 ctl, v;
  90         int cap, err;
  91
  92         cap = pci_pcie_cap(rdev->pdev);
  93         if (!cap)
  94                 return;
  95
  96         err = pci_read_config_word(rdev->pdev, cap + PCI_EXP_DEVCTL, &ctl);
  97         if (err)
  98                 return;
  99
 100         v = (ctl & PCI_EXP_DEVCTL_READRQ) >> 12;
 101
 102         /* if bios or OS sets MAX_READ_REQUEST_SIZE to an invalid value, fix it
 103          * to avoid hangs or perfomance issues
 104          */
 105         if ((v == 0) || (v == 6) || (v == 7)) {
 106                 ctl &= ~PCI_EXP_DEVCTL_READRQ;
 107                 ctl |= (2 << 12);
 108                 pci_write_config_word(rdev->pdev, cap + PCI_EXP_DEVCTL, ctl);
 109         }
 110 }
 111
 112 void dce4_wait_for_vblank(struct radeon_device *rdev, int crtc)
 113 {
 114         int i;
 115
 116         if (crtc >= rdev->num_crtc)
 117                 return;
 118
 119         if (RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[crtc]) & EVERGREEN_CRTC_MASTER_EN) {
 120                 for (i = 0; i < rdev->usec_timeout; i++) {
 121                         if (!(RREG32(EVERGREEN_CRTC_STATUS + crtc_offsets[crtc]) & EVERGREEN_CRTC_V_BLANK))
 122                                 break;
 123                         udelay(1);
 124                 }
 125                 for (i = 0; i < rdev->usec_timeout; i++) {
 126                         if (RREG32(EVERGREEN_CRTC_STATUS + crtc_offsets[crtc]) & EVERGREEN_CRTC_V_BLANK)
 127                                 break;
 128                         udelay(1);
 129                 }
 130         }
 131 }
 132
 133 void evergreen_pre_page_flip(struct radeon_device *rdev, int crtc)
 134 {
 135         /* enable the pflip int */
 136         radeon_irq_kms_pflip_irq_get(rdev, crtc);
 137 }
 138
 139 void evergreen_post_page_flip(struct radeon_device *rdev, int crtc)
 140 {
 141         /* disable the pflip int */
 142         radeon_irq_kms_pflip_irq_put(rdev, crtc);
 143 }
 144
 145 u32 evergreen_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
 146 {
 147         struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
 148         u32 tmp = RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset);
 149         int i;
 150
 151         /* Lock the graphics update lock */
 152         tmp |= EVERGREEN_GRPH_UPDATE_LOCK;
 153         WREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
 154
 155         /* update the scanout addresses */
 156         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
 157                upper_32_bits(crtc_base));
 158         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
 159                (u32)crtc_base);
 160
 161         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
 162                upper_32_bits(crtc_base));
 163         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
 164                (u32)crtc_base);
 165
 166         /* Wait for update_pending to go high. */
 167         for (i = 0; i < rdev->usec_timeout; i++) {
 168                 if (RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset) & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING)
 169                         break;
 170                 udelay(1);
 171         }
 172         DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
 173
 174         /* Unlock the lock, so double-buffering can take place inside vblank */
 175         tmp &= ~EVERGREEN_GRPH_UPDATE_LOCK;
 176         WREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
 177
 178         /* Return current update_pending status: */
 179         return RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset) & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING;
 180 }
 181
 182 /* get temperature in millidegrees */
 183 int evergreen_get_temp(struct radeon_device *rdev)
 184 {
 185         u32 temp, toffset;
 186         int actual_temp = 0;
 187
 188         if (rdev->family == CHIP_JUNIPER) {
 189                 toffset = (RREG32(CG_THERMAL_CTRL) & TOFFSET_MASK) >>
 190                         TOFFSET_SHIFT;
 191                 temp = (RREG32(CG_TS0_STATUS) & TS0_ADC_DOUT_MASK) >>
 192                         TS0_ADC_DOUT_SHIFT;
 193
 194                 if (toffset & 0x100)
 195                         actual_temp = temp / 2 - (0x200 - toffset);
 196                 else
 197                         actual_temp = temp / 2 + toffset;
 198
 199                 actual_temp = actual_temp * 1000;
 200
 201         } else {
 202                 temp = (RREG32(CG_MULT_THERMAL_STATUS) & ASIC_T_MASK) >>
 203                         ASIC_T_SHIFT;
 204
 205                 if (temp & 0x400)
 206                         actual_temp = -256;
 207                 else if (temp & 0x200)
 208                         actual_temp = 255;
 209                 else if (temp & 0x100) {
 210                         actual_temp = temp & 0x1ff;
 211                         actual_temp |= ~0x1ff;
 212                 } else
 213                         actual_temp = temp & 0xff;
 214
 215                 actual_temp = (actual_temp * 1000) / 2;
 216         }
 217
 218         return actual_temp;
 219 }
 220
 221 int sumo_get_temp(struct radeon_device *rdev)
 222 {
 223         u32 temp = RREG32(CG_THERMAL_STATUS) & 0xff;
 224         int actual_temp = temp - 49;
 225
 226         return actual_temp * 1000;
 227 }
 228
 229 void sumo_pm_init_profile(struct radeon_device *rdev)
 230 {
 231         int idx;
 232
 233         /* default */
 234         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 235         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 236         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 237         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
 238
 239         /* low,mid sh/mh */
 240         if (rdev->flags & RADEON_IS_MOBILITY)
 241                 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
 242         else
 243                 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
 244
 245         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = idx;
 246         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = idx;
 247         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 248         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 249
 250         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = idx;
 251         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = idx;
 252         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 253         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 254
 255         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = idx;
 256         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = idx;
 257         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 258         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
 259
 260         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = idx;
 261         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = idx;
 262         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 263         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
 264
 265         /* high sh/mh */
 266         idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
 267         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = idx;
 268         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = idx;
 269         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 270         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx =
 271                 rdev->pm.power_state[idx].num_clock_modes - 1;
 272
 273         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = idx;
 274         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = idx;
 275         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 276         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx =
 277                 rdev->pm.power_state[idx].num_clock_modes - 1;
 278 }
 279
 280 void evergreen_pm_misc(struct radeon_device *rdev)
 281 {
 282         int req_ps_idx = rdev->pm.requested_power_state_index;
 283         int req_cm_idx = rdev->pm.requested_clock_mode_index;
 284         struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx];
 285         struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
 286
 287         if (voltage->type == VOLTAGE_SW) {
 288                 /* 0xff01 is a flag rather then an actual voltage */
 289                 if (voltage->voltage == 0xff01)
 290                         return;
 291                 if (voltage->voltage && (voltage->voltage != rdev->pm.current_vddc)) {
 292                         radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC);
 293                         rdev->pm.current_vddc = voltage->voltage;
 294                         DRM_DEBUG("Setting: vddc: %d\n", voltage->voltage);
 295                 }
 296                 /* 0xff01 is a flag rather then an actual voltage */
 297                 if (voltage->vddci == 0xff01)
 298                         return;
 299                 if (voltage->vddci && (voltage->vddci != rdev->pm.current_vddci)) {
 300                         radeon_atom_set_voltage(rdev, voltage->vddci, SET_VOLTAGE_TYPE_ASIC_VDDCI);
 301                         rdev->pm.current_vddci = voltage->vddci;
 302                         DRM_DEBUG("Setting: vddci: %d\n", voltage->vddci);
 303                 }
 304         }
 305 }
 306
 307 void evergreen_pm_prepare(struct radeon_device *rdev)
 308 {
 309         struct drm_device *ddev = rdev->ddev;
 310         struct drm_crtc *crtc;
 311         struct radeon_crtc *radeon_crtc;
 312         u32 tmp;
 313
 314         /* disable any active CRTCs */
 315         list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
 316                 radeon_crtc = to_radeon_crtc(crtc);
 317                 if (radeon_crtc->enabled) {
 318                         tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset);
 319                         tmp |= EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
 320                         WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
 321                 }
 322         }
 323 }
 324
 325 void evergreen_pm_finish(struct radeon_device *rdev)
 326 {
 327         struct drm_device *ddev = rdev->ddev;
 328         struct drm_crtc *crtc;
 329         struct radeon_crtc *radeon_crtc;
 330         u32 tmp;
 331
 332         /* enable any active CRTCs */
 333         list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
 334                 radeon_crtc = to_radeon_crtc(crtc);
 335                 if (radeon_crtc->enabled) {
 336                         tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset);
 337                         tmp &= ~EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
 338                         WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
 339                 }
 340         }
 341 }
 342
 343 bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
 344 {
 345         bool connected = false;
 346
 347         switch (hpd) {
 348         case RADEON_HPD_1:
 349                 if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE)
 350                         connected = true;
 351                 break;
 352         case RADEON_HPD_2:
 353                 if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE)
 354                         connected = true;
 355                 break;
 356         case RADEON_HPD_3:
 357                 if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE)
 358                         connected = true;
 359                 break;
 360         case RADEON_HPD_4:
 361                 if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE)
 362                         connected = true;
 363                 break;
 364         case RADEON_HPD_5:
 365                 if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE)
 366                         connected = true;
 367                 break;
 368         case RADEON_HPD_6:
 369                 if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE)
 370                         connected = true;
 371                         break;
 372         default:
 373                 break;
 374         }
 375
 376         return connected;
 377 }
 378
 379 void evergreen_hpd_set_polarity(struct radeon_device *rdev,
 380                                 enum radeon_hpd_id hpd)
 381 {
 382         u32 tmp;
 383         bool connected = evergreen_hpd_sense(rdev, hpd);
 384
 385         switch (hpd) {
 386         case RADEON_HPD_1:
 387                 tmp = RREG32(DC_HPD1_INT_CONTROL);
 388                 if (connected)
 389                         tmp &= ~DC_HPDx_INT_POLARITY;
 390                 else
 391                         tmp |= DC_HPDx_INT_POLARITY;
 392                 WREG32(DC_HPD1_INT_CONTROL, tmp);
 393                 break;
 394         case RADEON_HPD_2:
 395                 tmp = RREG32(DC_HPD2_INT_CONTROL);
 396                 if (connected)
 397                         tmp &= ~DC_HPDx_INT_POLARITY;
 398                 else
 399                         tmp |= DC_HPDx_INT_POLARITY;
 400                 WREG32(DC_HPD2_INT_CONTROL, tmp);
 401                 break;
 402         case RADEON_HPD_3:
 403                 tmp = RREG32(DC_HPD3_INT_CONTROL);
 404                 if (connected)
 405                         tmp &= ~DC_HPDx_INT_POLARITY;
 406                 else
 407                         tmp |= DC_HPDx_INT_POLARITY;
 408                 WREG32(DC_HPD3_INT_CONTROL, tmp);
 409                 break;
 410         case RADEON_HPD_4:
 411                 tmp = RREG32(DC_HPD4_INT_CONTROL);
 412                 if (connected)
 413                         tmp &= ~DC_HPDx_INT_POLARITY;
 414                 else
 415                         tmp |= DC_HPDx_INT_POLARITY;
 416                 WREG32(DC_HPD4_INT_CONTROL, tmp);
 417                 break;
 418         case RADEON_HPD_5:
 419                 tmp = RREG32(DC_HPD5_INT_CONTROL);
 420                 if (connected)
 421                         tmp &= ~DC_HPDx_INT_POLARITY;
 422                 else
 423                         tmp |= DC_HPDx_INT_POLARITY;
 424                 WREG32(DC_HPD5_INT_CONTROL, tmp);
 425                         break;
 426         case RADEON_HPD_6:
 427                 tmp = RREG32(DC_HPD6_INT_CONTROL);
 428                 if (connected)
 429                         tmp &= ~DC_HPDx_INT_POLARITY;
 430                 else
 431                         tmp |= DC_HPDx_INT_POLARITY;
 432                 WREG32(DC_HPD6_INT_CONTROL, tmp);
 433                 break;
 434         default:
 435                 break;
 436         }
 437 }
 438
 439 void evergreen_hpd_init(struct radeon_device *rdev)
 440 {
 441         struct drm_device *dev = rdev->ddev;
 442         struct drm_connector *connector;
 443         u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) |
 444                 DC_HPDx_RX_INT_TIMER(0xfa) | DC_HPDx_EN;
 445
 446         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 447                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 448
 449                 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
 450                     connector->connector_type == DRM_MODE_CONNECTOR_LVDS) {
 451                         /* don't try to enable hpd on eDP or LVDS avoid breaking the
 452                          * aux dp channel on imac and help (but not completely fix)
 453                          * https://bugzilla.redhat.com/show_bug.cgi?id=726143
 454                          * also avoid interrupt storms during dpms.
 455                          */
 456                         continue;
 457                 }
 458                 switch (radeon_connector->hpd.hpd) {
 459                 case RADEON_HPD_1:
 460                         WREG32(DC_HPD1_CONTROL, tmp);
 461                         rdev->irq.hpd[0] = true;
 462                         break;
 463                 case RADEON_HPD_2:
 464                         WREG32(DC_HPD2_CONTROL, tmp);
 465                         rdev->irq.hpd[1] = true;
 466                         break;
 467                 case RADEON_HPD_3:
 468                         WREG32(DC_HPD3_CONTROL, tmp);
 469                         rdev->irq.hpd[2] = true;
 470                         break;
 471                 case RADEON_HPD_4:
 472                         WREG32(DC_HPD4_CONTROL, tmp);
 473                         rdev->irq.hpd[3] = true;
 474                         break;
 475                 case RADEON_HPD_5:
 476                         WREG32(DC_HPD5_CONTROL, tmp);
 477                         rdev->irq.hpd[4] = true;
 478                         break;
 479                 case RADEON_HPD_6:
 480                         WREG32(DC_HPD6_CONTROL, tmp);
 481                         rdev->irq.hpd[5] = true;
 482                         break;
 483                 default:
 484                         break;
 485                 }
 486                 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
 487         }
 488         if (rdev->irq.installed)
 489                 evergreen_irq_set(rdev);
 490 }
 491
 492 void evergreen_hpd_fini(struct radeon_device *rdev)
 493 {
 494         struct drm_device *dev = rdev->ddev;
 495         struct drm_connector *connector;
 496
 497         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 498                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 499                 switch (radeon_connector->hpd.hpd) {
 500                 case RADEON_HPD_1:
 501                         WREG32(DC_HPD1_CONTROL, 0);
 502                         rdev->irq.hpd[0] = false;
 503                         break;
 504                 case RADEON_HPD_2:
 505                         WREG32(DC_HPD2_CONTROL, 0);
 506                         rdev->irq.hpd[1] = false;
 507                         break;
 508                 case RADEON_HPD_3:
 509                         WREG32(DC_HPD3_CONTROL, 0);
 510                         rdev->irq.hpd[2] = false;
 511                         break;
 512                 case RADEON_HPD_4:
 513                         WREG32(DC_HPD4_CONTROL, 0);
 514                         rdev->irq.hpd[3] = false;
 515                         break;
 516                 case RADEON_HPD_5:
 517                         WREG32(DC_HPD5_CONTROL, 0);
 518                         rdev->irq.hpd[4] = false;
 519                         break;
 520                 case RADEON_HPD_6:
 521                         WREG32(DC_HPD6_CONTROL, 0);
 522                         rdev->irq.hpd[5] = false;
 523                         break;
 524                 default:
 525                         break;
 526                 }
 527         }
 528 }
 529
 530 /* watermark setup */
 531
 532 static u32 evergreen_line_buffer_adjust(struct radeon_device *rdev,
 533                                         struct radeon_crtc *radeon_crtc,
 534                                         struct drm_display_mode *mode,
 535                                         struct drm_display_mode *other_mode)
 536 {
 537         u32 tmp, buffer_alloc, i;
 538         u32 pipe_offset = radeon_crtc->crtc_id * 0x20;
 539         /*
 540          * Line Buffer Setup
 541          * There are 3 line buffers, each one shared by 2 display controllers.
 542          * DC_LB_MEMORY_SPLIT controls how that line buffer is shared between
 543          * the display controllers.  The paritioning is done via one of four
 544          * preset allocations specified in bits 2:0:
 545          * first display controller
 546          *  0 - first half of lb (3840 * 2)
 547          *  1 - first 3/4 of lb (5760 * 2)
 548          *  2 - whole lb (7680 * 2), other crtc must be disabled
 549          *  3 - first 1/4 of lb (1920 * 2)
 550          * second display controller
 551          *  4 - second half of lb (3840 * 2)
 552          *  5 - second 3/4 of lb (5760 * 2)
 553          *  6 - whole lb (7680 * 2), other crtc must be disabled
 554          *  7 - last 1/4 of lb (1920 * 2)
 555          */
 556         /* this can get tricky if we have two large displays on a paired group
 557          * of crtcs.  Ideally for multiple large displays we'd assign them to
 558          * non-linked crtcs for maximum line buffer allocation.
 559          */
 560         if (radeon_crtc->base.enabled && mode) {
 561                 if (other_mode) {
 562                         tmp = 0; /* 1/2 */
 563                         buffer_alloc = 1;
 564                 } else {
 565                         tmp = 2; /* whole */
 566                         buffer_alloc = 2;
 567                 }
 568         } else {
 569                 tmp = 0;
 570                 buffer_alloc = 0;
 571         }
 572
 573         /* second controller of the pair uses second half of the lb */
 574         if (radeon_crtc->crtc_id % 2)
 575                 tmp += 4;
 576         WREG32(DC_LB_MEMORY_SPLIT + radeon_crtc->crtc_offset, tmp);
 577
 578         if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) {
 579                 WREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset,
 580                        DMIF_BUFFERS_ALLOCATED(buffer_alloc));
 581                 for (i = 0; i < rdev->usec_timeout; i++) {
 582                         if (RREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset) &
 583                             DMIF_BUFFERS_ALLOCATED_COMPLETED)
 584                                 break;
 585                         udelay(1);
 586                 }
 587         }
 588
 589         if (radeon_crtc->base.enabled && mode) {
 590                 switch (tmp) {
 591                 case 0:
 592                 case 4:
 593                 default:
 594                         if (ASIC_IS_DCE5(rdev))
 595                                 return 4096 * 2;
 596                         else
 597                                 return 3840 * 2;
 598                 case 1:
 599                 case 5:
 600                         if (ASIC_IS_DCE5(rdev))
 601                                 return 6144 * 2;
 602                         else
 603                                 return 5760 * 2;
 604                 case 2:
 605                 case 6:
 606                         if (ASIC_IS_DCE5(rdev))
 607                                 return 8192 * 2;
 608                         else
 609                                 return 7680 * 2;
 610                 case 3:
 611                 case 7:
 612                         if (ASIC_IS_DCE5(rdev))
 613                                 return 2048 * 2;
 614                         else
 615                                 return 1920 * 2;
 616                 }
 617         }
 618
 619         /* controller not enabled, so no lb used */
 620         return 0;
 621 }
 622
 623 u32 evergreen_get_number_of_dram_channels(struct radeon_device *rdev)
 624 {
 625         u32 tmp = RREG32(MC_SHARED_CHMAP);
 626
 627         switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
 628         case 0:
 629         default:
 630                 return 1;
 631         case 1:
 632                 return 2;
 633         case 2:
 634                 return 4;
 635         case 3:
 636                 return 8;
 637         }
 638 }
 639
 640 struct evergreen_wm_params {
 641         u32 dram_channels; /* number of dram channels */
 642         u32 yclk;          /* bandwidth per dram data pin in kHz */
 643         u32 sclk;          /* engine clock in kHz */
 644         u32 disp_clk;      /* display clock in kHz */
 645         u32 src_width;     /* viewport width */
 646         u32 active_time;   /* active display time in ns */
 647         u32 blank_time;    /* blank time in ns */
 648         bool interlaced;    /* mode is interlaced */
 649         fixed20_12 vsc;    /* vertical scale ratio */
 650         u32 num_heads;     /* number of active crtcs */
 651         u32 bytes_per_pixel; /* bytes per pixel display + overlay */
 652         u32 lb_size;       /* line buffer allocated to pipe */
 653         u32 vtaps;         /* vertical scaler taps */
 654 };
 655
 656 static u32 evergreen_dram_bandwidth(struct evergreen_wm_params *wm)
 657 {
 658         /* Calculate DRAM Bandwidth and the part allocated to display. */
 659         fixed20_12 dram_efficiency; /* 0.7 */
 660         fixed20_12 yclk, dram_channels, bandwidth;
 661         fixed20_12 a;
 662
 663         a.full = dfixed_const(1000);
 664         yclk.full = dfixed_const(wm->yclk);
 665         yclk.full = dfixed_div(yclk, a);
 666         dram_channels.full = dfixed_const(wm->dram_channels * 4);
 667         a.full = dfixed_const(10);
 668         dram_efficiency.full = dfixed_const(7);
 669         dram_efficiency.full = dfixed_div(dram_efficiency, a);
 670         bandwidth.full = dfixed_mul(dram_channels, yclk);
 671         bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
 672
 673         return dfixed_trunc(bandwidth);
 674 }
 675
 676 static u32 evergreen_dram_bandwidth_for_display(struct evergreen_wm_params *wm)
 677 {
 678         /* Calculate DRAM Bandwidth and the part allocated to display. */
 679         fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
 680         fixed20_12 yclk, dram_channels, bandwidth;
 681         fixed20_12 a;
 682
 683         a.full = dfixed_const(1000);
 684         yclk.full = dfixed_const(wm->yclk);
 685         yclk.full = dfixed_div(yclk, a);
 686         dram_channels.full = dfixed_const(wm->dram_channels * 4);
 687         a.full = dfixed_const(10);
 688         disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
 689         disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
 690         bandwidth.full = dfixed_mul(dram_channels, yclk);
 691         bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
 692
 693         return dfixed_trunc(bandwidth);
 694 }
 695
 696 static u32 evergreen_data_return_bandwidth(struct evergreen_wm_params *wm)
 697 {
 698         /* Calculate the display Data return Bandwidth */
 699         fixed20_12 return_efficiency; /* 0.8 */
 700         fixed20_12 sclk, bandwidth;
 701         fixed20_12 a;
 702
 703         a.full = dfixed_const(1000);
 704         sclk.full = dfixed_const(wm->sclk);
 705         sclk.full = dfixed_div(sclk, a);
 706         a.full = dfixed_const(10);
 707         return_efficiency.full = dfixed_const(8);
 708         return_efficiency.full = dfixed_div(return_efficiency, a);
 709         a.full = dfixed_const(32);
 710         bandwidth.full = dfixed_mul(a, sclk);
 711         bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
 712
 713         return dfixed_trunc(bandwidth);
 714 }
 715
 716 static u32 evergreen_dmif_request_bandwidth(struct evergreen_wm_params *wm)
 717 {
 718         /* Calculate the DMIF Request Bandwidth */
 719         fixed20_12 disp_clk_request_efficiency; /* 0.8 */
 720         fixed20_12 disp_clk, bandwidth;
 721         fixed20_12 a;
 722
 723         a.full = dfixed_const(1000);
 724         disp_clk.full = dfixed_const(wm->disp_clk);
 725         disp_clk.full = dfixed_div(disp_clk, a);
 726         a.full = dfixed_const(10);
 727         disp_clk_request_efficiency.full = dfixed_const(8);
 728         disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
 729         a.full = dfixed_const(32);
 730         bandwidth.full = dfixed_mul(a, disp_clk);
 731         bandwidth.full = dfixed_mul(bandwidth, disp_clk_request_efficiency);
 732
 733         return dfixed_trunc(bandwidth);
 734 }
 735
 736 static u32 evergreen_available_bandwidth(struct evergreen_wm_params *wm)
 737 {
 738         /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
 739         u32 dram_bandwidth = evergreen_dram_bandwidth(wm);
 740         u32 data_return_bandwidth = evergreen_data_return_bandwidth(wm);
 741         u32 dmif_req_bandwidth = evergreen_dmif_request_bandwidth(wm);
 742
 743         return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
 744 }
 745
 746 static u32 evergreen_average_bandwidth(struct evergreen_wm_params *wm)
 747 {
 748         /* Calculate the display mode Average Bandwidth
 749          * DisplayMode should contain the source and destination dimensions,
 750          * timing, etc.
 751          */
 752         fixed20_12 bpp;
 753         fixed20_12 line_time;
 754         fixed20_12 src_width;
 755         fixed20_12 bandwidth;
 756         fixed20_12 a;
 757
 758         a.full = dfixed_const(1000);
 759         line_time.full = dfixed_const(wm->active_time + wm->blank_time);
 760         line_time.full = dfixed_div(line_time, a);
 761         bpp.full = dfixed_const(wm->bytes_per_pixel);
 762         src_width.full = dfixed_const(wm->src_width);
 763         bandwidth.full = dfixed_mul(src_width, bpp);
 764         bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
 765         bandwidth.full = dfixed_div(bandwidth, line_time);
 766
 767         return dfixed_trunc(bandwidth);
 768 }
 769
 770 static u32 evergreen_latency_watermark(struct evergreen_wm_params *wm)
 771 {
 772         /* First calcualte the latency in ns */
 773         u32 mc_latency = 2000; /* 2000 ns. */
 774         u32 available_bandwidth = evergreen_available_bandwidth(wm);
 775         u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
 776         u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
 777         u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
 778         u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
 779                 (wm->num_heads * cursor_line_pair_return_time);
 780         u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
 781         u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
 782         fixed20_12 a, b, c;
 783
 784         if (wm->num_heads == 0)
 785                 return 0;
 786
 787         a.full = dfixed_const(2);
 788         b.full = dfixed_const(1);
 789         if ((wm->vsc.full > a.full) ||
 790             ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
 791             (wm->vtaps >= 5) ||
 792             ((wm->vsc.full >= a.full) && wm->interlaced))
 793                 max_src_lines_per_dst_line = 4;
 794         else
 795                 max_src_lines_per_dst_line = 2;
 796
 797         a.full = dfixed_const(available_bandwidth);
 798         b.full = dfixed_const(wm->num_heads);
 799         a.full = dfixed_div(a, b);
 800
 801         b.full = dfixed_const(1000);
 802         c.full = dfixed_const(wm->disp_clk);
 803         b.full = dfixed_div(c, b);
 804         c.full = dfixed_const(wm->bytes_per_pixel);
 805         b.full = dfixed_mul(b, c);
 806
 807         lb_fill_bw = min(dfixed_trunc(a), dfixed_trunc(b));
 808
 809         a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
 810         b.full = dfixed_const(1000);
 811         c.full = dfixed_const(lb_fill_bw);
 812         b.full = dfixed_div(c, b);
 813         a.full = dfixed_div(a, b);
 814         line_fill_time = dfixed_trunc(a);
 815
 816         if (line_fill_time < wm->active_time)
 817                 return latency;
 818         else
 819                 return latency + (line_fill_time - wm->active_time);
 820
 821 }
 822
 823 static bool evergreen_average_bandwidth_vs_dram_bandwidth_for_display(struct evergreen_wm_params *wm)
 824 {
 825         if (evergreen_average_bandwidth(wm) <=
 826             (evergreen_dram_bandwidth_for_display(wm) / wm->num_heads))
 827                 return true;
 828         else
 829                 return false;
 830 };
 831
 832 static bool evergreen_average_bandwidth_vs_available_bandwidth(struct evergreen_wm_params *wm)
 833 {
 834         if (evergreen_average_bandwidth(wm) <=
 835             (evergreen_available_bandwidth(wm) / wm->num_heads))
 836                 return true;
 837         else
 838                 return false;
 839 };
 840
 841 static bool evergreen_check_latency_hiding(struct evergreen_wm_params *wm)
 842 {
 843         u32 lb_partitions = wm->lb_size / wm->src_width;
 844         u32 line_time = wm->active_time + wm->blank_time;
 845         u32 latency_tolerant_lines;
 846         u32 latency_hiding;
 847         fixed20_12 a;
 848
 849         a.full = dfixed_const(1);
 850         if (wm->vsc.full > a.full)
 851                 latency_tolerant_lines = 1;
 852         else {
 853                 if (lb_partitions <= (wm->vtaps + 1))
 854                         latency_tolerant_lines = 1;
 855                 else
 856                         latency_tolerant_lines = 2;
 857         }
 858
 859         latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
 860
 861         if (evergreen_latency_watermark(wm) <= latency_hiding)
 862                 return true;
 863         else
 864                 return false;
 865 }
 866
 867 static void evergreen_program_watermarks(struct radeon_device *rdev,
 868                                          struct radeon_crtc *radeon_crtc,
 869                                          u32 lb_size, u32 num_heads)
 870 {
 871         struct drm_display_mode *mode = &radeon_crtc->base.mode;
 872         struct evergreen_wm_params wm;
 873         u32 pixel_period;
 874         u32 line_time = 0;
 875         u32 latency_watermark_a = 0, latency_watermark_b = 0;
 876         u32 priority_a_mark = 0, priority_b_mark = 0;
 877         u32 priority_a_cnt = PRIORITY_OFF;
 878         u32 priority_b_cnt = PRIORITY_OFF;
 879         u32 pipe_offset = radeon_crtc->crtc_id * 16;
 880         u32 tmp, arb_control3;
 881         fixed20_12 a, b, c;
 882
 883         if (radeon_crtc->base.enabled && num_heads && mode) {
 884                 pixel_period = 1000000 / (u32)mode->clock;
 885                 line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535);
 886                 priority_a_cnt = 0;
 887                 priority_b_cnt = 0;
 888
 889                 wm.yclk = rdev->pm.current_mclk * 10;
 890                 wm.sclk = rdev->pm.current_sclk * 10;
 891                 wm.disp_clk = mode->clock;
 892                 wm.src_width = mode->crtc_hdisplay;
 893                 wm.active_time = mode->crtc_hdisplay * pixel_period;
 894                 wm.blank_time = line_time - wm.active_time;
 895                 wm.interlaced = false;
 896                 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
 897                         wm.interlaced = true;
 898                 wm.vsc = radeon_crtc->vsc;
 899                 wm.vtaps = 1;
 900                 if (radeon_crtc->rmx_type != RMX_OFF)
 901                         wm.vtaps = 2;
 902                 wm.bytes_per_pixel = 4; /* XXX: get this from fb config */
 903                 wm.lb_size = lb_size;
 904                 wm.dram_channels = evergreen_get_number_of_dram_channels(rdev);
 905                 wm.num_heads = num_heads;
 906
 907                 /* set for high clocks */
 908                 latency_watermark_a = min(evergreen_latency_watermark(&wm), (u32)65535);
 909                 /* set for low clocks */
 910                 /* wm.yclk = low clk; wm.sclk = low clk */
 911                 latency_watermark_b = min(evergreen_latency_watermark(&wm), (u32)65535);
 912
 913                 /* possibly force display priority to high */
 914                 /* should really do this at mode validation time... */
 915                 if (!evergreen_average_bandwidth_vs_dram_bandwidth_for_display(&wm) ||
 916                     !evergreen_average_bandwidth_vs_available_bandwidth(&wm) ||
 917                     !evergreen_check_latency_hiding(&wm) ||
 918                     (rdev->disp_priority == 2)) {
 919                         DRM_DEBUG_KMS("force priority to high\n");
 920                         priority_a_cnt |= PRIORITY_ALWAYS_ON;
 921                         priority_b_cnt |= PRIORITY_ALWAYS_ON;
 922                 }
 923
 924                 a.full = dfixed_const(1000);
 925                 b.full = dfixed_const(mode->clock);
 926                 b.full = dfixed_div(b, a);
 927                 c.full = dfixed_const(latency_watermark_a);
 928                 c.full = dfixed_mul(c, b);
 929                 c.full = dfixed_mul(c, radeon_crtc->hsc);
 930                 c.full = dfixed_div(c, a);
 931                 a.full = dfixed_const(16);
 932                 c.full = dfixed_div(c, a);
 933                 priority_a_mark = dfixed_trunc(c);
 934                 priority_a_cnt |= priority_a_mark & PRIORITY_MARK_MASK;
 935
 936                 a.full = dfixed_const(1000);
 937                 b.full = dfixed_const(mode->clock);
 938                 b.full = dfixed_div(b, a);
 939                 c.full = dfixed_const(latency_watermark_b);
 940                 c.full = dfixed_mul(c, b);
 941                 c.full = dfixed_mul(c, radeon_crtc->hsc);
 942                 c.full = dfixed_div(c, a);
 943                 a.full = dfixed_const(16);
 944                 c.full = dfixed_div(c, a);
 945                 priority_b_mark = dfixed_trunc(c);
 946                 priority_b_cnt |= priority_b_mark & PRIORITY_MARK_MASK;
 947         }
 948
 949         /* select wm A */
 950         arb_control3 = RREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset);
 951         tmp = arb_control3;
 952         tmp &= ~LATENCY_WATERMARK_MASK(3);
 953         tmp |= LATENCY_WATERMARK_MASK(1);
 954         WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp);
 955         WREG32(PIPE0_LATENCY_CONTROL + pipe_offset,
 956                (LATENCY_LOW_WATERMARK(latency_watermark_a) |
 957                 LATENCY_HIGH_WATERMARK(line_time)));
 958         /* select wm B */
 959         tmp = RREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset);
 960         tmp &= ~LATENCY_WATERMARK_MASK(3);
 961         tmp |= LATENCY_WATERMARK_MASK(2);
 962         WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp);
 963         WREG32(PIPE0_LATENCY_CONTROL + pipe_offset,
 964                (LATENCY_LOW_WATERMARK(latency_watermark_b) |
 965                 LATENCY_HIGH_WATERMARK(line_time)));
 966         /* restore original selection */
 967         WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, arb_control3);
 968
 969         /* write the priority marks */
 970         WREG32(PRIORITY_A_CNT + radeon_crtc->crtc_offset, priority_a_cnt);
 971         WREG32(PRIORITY_B_CNT + radeon_crtc->crtc_offset, priority_b_cnt);
 972
 973 }
 974
 975 void evergreen_bandwidth_update(struct radeon_device *rdev)
 976 {
 977         struct drm_display_mode *mode0 = NULL;
 978         struct drm_display_mode *mode1 = NULL;
 979         u32 num_heads = 0, lb_size;
 980         int i;
 981
 982         radeon_update_display_priority(rdev);
 983
 984         for (i = 0; i < rdev->num_crtc; i++) {
 985                 if (rdev->mode_info.crtcs[i]->base.enabled)
 986                         num_heads++;
 987         }
 988         for (i = 0; i < rdev->num_crtc; i += 2) {
 989                 mode0 = &rdev->mode_info.crtcs[i]->base.mode;
 990                 mode1 = &rdev->mode_info.crtcs[i+1]->base.mode;
 991                 lb_size = evergreen_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i], mode0, mode1);
 992                 evergreen_program_watermarks(rdev, rdev->mode_info.crtcs[i], lb_size, num_heads);
 993                 lb_size = evergreen_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i+1], mode1, mode0);
 994                 evergreen_program_watermarks(rdev, rdev->mode_info.crtcs[i+1], lb_size, num_heads);
 995         }
 996 }
 997
 998 int evergreen_mc_wait_for_idle(struct radeon_device *rdev)
 999 {
1000         unsigned i;
1001         u32 tmp;
1002
1003         for (i = 0; i < rdev->usec_timeout; i++) {
1004                 /* read MC_STATUS */
1005                 tmp = RREG32(SRBM_STATUS) & 0x1F00;
1006                 if (!tmp)
1007                         return 0;
1008                 udelay(1);
1009         }
1010         return -1;
1011 }
1012
1013 /*
1014  * GART
1015  */
1016 void evergreen_pcie_gart_tlb_flush(struct radeon_device *rdev)
1017 {
1018         unsigned i;
1019         u32 tmp;
1020
1021         WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
1022
1023         WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
1024         for (i = 0; i < rdev->usec_timeout; i++) {
1025                 /* read MC_STATUS */
1026                 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
1027                 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
1028                 if (tmp == 2) {
1029                         printk(KERN_WARNING "[drm] r600 flush TLB failed\n");
1030                         return;
1031                 }
1032                 if (tmp) {
1033                         return;
1034                 }
1035                 udelay(1);
1036         }
1037 }
1038
1039 int evergreen_pcie_gart_enable(struct radeon_device *rdev)
1040 {
1041         u32 tmp;
1042         int r;
1043
1044         if (rdev->gart.robj == NULL) {
1045                 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
1046                 return -EINVAL;
1047         }
1048         r = radeon_gart_table_vram_pin(rdev);
1049         if (r)
1050                 return r;
1051         radeon_gart_restore(rdev);
1052         /* Setup L2 cache */
1053         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
1054                                 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
1055                                 EFFECTIVE_L2_QUEUE_SIZE(7));
1056         WREG32(VM_L2_CNTL2, 0);
1057         WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
1058         /* Setup TLB control */
1059         tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
1060                 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
1061                 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
1062                 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
1063         if (rdev->flags & RADEON_IS_IGP) {
1064                 WREG32(FUS_MC_VM_MD_L1_TLB0_CNTL, tmp);
1065                 WREG32(FUS_MC_VM_MD_L1_TLB1_CNTL, tmp);
1066                 WREG32(FUS_MC_VM_MD_L1_TLB2_CNTL, tmp);
1067         } else {
1068                 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
1069                 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
1070                 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
1071                 if ((rdev->family == CHIP_JUNIPER) ||
1072                     (rdev->family == CHIP_CYPRESS) ||
1073                     (rdev->family == CHIP_HEMLOCK) ||
1074                     (rdev->family == CHIP_BARTS))
1075                         WREG32(MC_VM_MD_L1_TLB3_CNTL, tmp);
1076         }
1077         WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
1078         WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
1079         WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
1080         WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
1081         WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
1082         WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
1083         WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
1084         WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
1085                                 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
1086         WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
1087                         (u32)(rdev->dummy_page.addr >> 12));
1088         WREG32(VM_CONTEXT1_CNTL, 0);
1089
1090         evergreen_pcie_gart_tlb_flush(rdev);
1091         DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
1092                  (unsigned)(rdev->mc.gtt_size >> 20),
1093                  (unsigned long long)rdev->gart.table_addr);
1094         rdev->gart.ready = true;
1095         return 0;
1096 }
1097
1098 void evergreen_pcie_gart_disable(struct radeon_device *rdev)
1099 {
1100         u32 tmp;
1101
1102         /* Disable all tables */
1103         WREG32(VM_CONTEXT0_CNTL, 0);
1104         WREG32(VM_CONTEXT1_CNTL, 0);
1105
1106         /* Setup L2 cache */
1107         WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
1108                                 EFFECTIVE_L2_QUEUE_SIZE(7));
1109         WREG32(VM_L2_CNTL2, 0);
1110         WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
1111         /* Setup TLB control */
1112         tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
1113         WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
1114         WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
1115         WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
1116         WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
1117         WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
1118         WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
1119         WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
1120         radeon_gart_table_vram_unpin(rdev);
1121 }
1122
1123 void evergreen_pcie_gart_fini(struct radeon_device *rdev)
1124 {
1125         evergreen_pcie_gart_disable(rdev);
1126         radeon_gart_table_vram_free(rdev);
1127         radeon_gart_fini(rdev);
1128 }
1129
1130
1131 void evergreen_agp_enable(struct radeon_device *rdev)
1132 {
1133         u32 tmp;
1134
1135         /* Setup L2 cache */
1136         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
1137                                 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
1138                                 EFFECTIVE_L2_QUEUE_SIZE(7));
1139         WREG32(VM_L2_CNTL2, 0);
1140         WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
1141         /* Setup TLB control */
1142         tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
1143                 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
1144                 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
1145                 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
1146         WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
1147         WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
1148         WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
1149         WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
1150         WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
1151         WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
1152         WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
1153         WREG32(VM_CONTEXT0_CNTL, 0);
1154         WREG32(VM_CONTEXT1_CNTL, 0);
1155 }
1156
1157 void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save)
1158 {
1159         u32 crtc_enabled, tmp, frame_count, blackout;
1160         int i, j;
1161
1162         save->vga_render_control = RREG32(VGA_RENDER_CONTROL);
1163         save->vga_hdp_control = RREG32(VGA_HDP_CONTROL);
1164
1165         /* disable VGA render */
1166         WREG32(VGA_RENDER_CONTROL, 0);
1167         /* blank the display controllers */
1168         for (i = 0; i < rdev->num_crtc; i++) {
1169                 crtc_enabled = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]) & EVERGREEN_CRTC_MASTER_EN;
1170                 if (crtc_enabled) {
1171                         save->crtc_enabled[i] = true;
1172                         if (ASIC_IS_DCE6(rdev)) {
1173                                 tmp = RREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i]);
1174                                 if (!(tmp & EVERGREEN_CRTC_BLANK_DATA_EN)) {
1175                                         radeon_wait_for_vblank(rdev, i);
1176                                         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
1177                                         tmp |= EVERGREEN_CRTC_BLANK_DATA_EN;
1178                                         WREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
1179                                 }
1180                         } else {
1181                                 tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]);
1182                                 if (!(tmp & EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE)) {
1183                                         radeon_wait_for_vblank(rdev, i);
1184                                         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
1185                                         tmp |= EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
1186                                         WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp);
1187                                         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
1188                                 }
1189                         }
1190                         /* wait for the next frame */
1191                         frame_count = radeon_get_vblank_counter(rdev, i);
1192                         for (j = 0; j < rdev->usec_timeout; j++) {
1193                                 if (radeon_get_vblank_counter(rdev, i) != frame_count)
1194                                         break;
1195                                 udelay(1);
1196                         }
1197
1198                         /* XXX this is a hack to avoid strange behavior with EFI on certain systems */
1199                         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
1200                         tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]);
1201                         tmp &= ~EVERGREEN_CRTC_MASTER_EN;
1202                         WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp);
1203                         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
1204                         save->crtc_enabled[i] = false;
1205                         /* ***** */
1206                 } else {
1207                         save->crtc_enabled[i] = false;
1208                 }
1209         }
1210
1211         radeon_mc_wait_for_idle(rdev);
1212
1213         blackout = RREG32(MC_SHARED_BLACKOUT_CNTL);
1214         if ((blackout & BLACKOUT_MODE_MASK) != 1) {
1215                 /* Block CPU access */
1216                 WREG32(BIF_FB_EN, 0);
1217                 /* blackout the MC */
1218                 blackout &= ~BLACKOUT_MODE_MASK;
1219                 WREG32(MC_SHARED_BLACKOUT_CNTL, blackout | 1);
1220         }
1221         /* wait for the MC to settle */
1222         udelay(100);
1223
1224         /* lock double buffered regs */
1225         for (i = 0; i < rdev->num_crtc; i++) {
1226                 if (save->crtc_enabled[i]) {
1227                         tmp = RREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i]);
1228                         if (!(tmp & EVERGREEN_GRPH_UPDATE_LOCK)) {
1229                                 tmp |= EVERGREEN_GRPH_UPDATE_LOCK;
1230                                 WREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i], tmp);
1231                         }
1232                         tmp = RREG32(EVERGREEN_MASTER_UPDATE_LOCK + crtc_offsets[i]);
1233                         if (!(tmp & 1)) {
1234                                 tmp |= 1;
1235                                 WREG32(EVERGREEN_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
1236                         }
1237                 }
1238         }
1239 }
1240
1241 void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save)
1242 {
1243         u32 tmp, frame_count;
1244         int i, j;
1245
1246         /* update crtc base addresses */
1247         for (i = 0; i < rdev->num_crtc; i++) {
1248                 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],
1249                        upper_32_bits(rdev->mc.vram_start));
1250                 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],
1251                        upper_32_bits(rdev->mc.vram_start));
1252                 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i],
1253                        (u32)rdev->mc.vram_start);
1254                 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i],
1255                        (u32)rdev->mc.vram_start);
1256         }
1257         WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(rdev->mc.vram_start));
1258         WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start);
1259
1260         /* unlock regs and wait for update */
1261         for (i = 0; i < rdev->num_crtc; i++) {
1262                 if (save->crtc_enabled[i]) {
1263                         tmp = RREG32(EVERGREEN_MASTER_UPDATE_MODE + crtc_offsets[i]);
1264                         if ((tmp & 0x3) != 0) {
1265                                 tmp &= ~0x3;
1266                                 WREG32(EVERGREEN_MASTER_UPDATE_MODE + crtc_offsets[i], tmp);
1267                         }
1268                         tmp = RREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i]);
1269                         if (tmp & EVERGREEN_GRPH_UPDATE_LOCK) {
1270                                 tmp &= ~EVERGREEN_GRPH_UPDATE_LOCK;
1271                                 WREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i], tmp);
1272                         }
1273                         tmp = RREG32(EVERGREEN_MASTER_UPDATE_LOCK + crtc_offsets[i]);
1274                         if (tmp & 1) {
1275                                 tmp &= ~1;
1276                                 WREG32(EVERGREEN_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
1277                         }
1278                         for (j = 0; j < rdev->usec_timeout; j++) {
1279                                 tmp = RREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i]);
1280                                 if ((tmp & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING) == 0)
1281                                         break;
1282                                 udelay(1);
1283                         }
1284                 }
1285         }
1286
1287         /* unblackout the MC */
1288         tmp = RREG32(MC_SHARED_BLACKOUT_CNTL);
1289         tmp &= ~BLACKOUT_MODE_MASK;
1290         WREG32(MC_SHARED_BLACKOUT_CNTL, tmp);
1291         /* allow CPU access */
1292         WREG32(BIF_FB_EN, FB_READ_EN | FB_WRITE_EN);
1293
1294         for (i = 0; i < rdev->num_crtc; i++) {
1295                 if (save->crtc_enabled[i]) {
1296                         if (ASIC_IS_DCE6(rdev)) {
1297                                 tmp = RREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i]);
1298                                 tmp |= EVERGREEN_CRTC_BLANK_DATA_EN;
1299                                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
1300                                 WREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
1301                                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
1302                         } else {
1303                                 tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]);
1304                                 tmp &= ~EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
1305                                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
1306                                 WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp);
1307                                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
1308                         }
1309                         /* wait for the next frame */
1310                         frame_count = radeon_get_vblank_counter(rdev, i);
1311                         for (j = 0; j < rdev->usec_timeout; j++) {
1312                                 if (radeon_get_vblank_counter(rdev, i) != frame_count)
1313                                         break;
1314                                 udelay(1);
1315                         }
1316                 }
1317         }
1318         /* Unlock vga access */
1319         WREG32(VGA_HDP_CONTROL, save->vga_hdp_control);
1320         mdelay(1);
1321         WREG32(VGA_RENDER_CONTROL, save->vga_render_control);
1322 }
1323
1324 void evergreen_mc_program(struct radeon_device *rdev)
1325 {
1326         struct evergreen_mc_save save;
1327         u32 tmp;
1328         int i, j;
1329
1330         /* Initialize HDP */
1331         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1332                 WREG32((0x2c14 + j), 0x00000000);
1333                 WREG32((0x2c18 + j), 0x00000000);
1334                 WREG32((0x2c1c + j), 0x00000000);
1335                 WREG32((0x2c20 + j), 0x00000000);
1336                 WREG32((0x2c24 + j), 0x00000000);
1337         }
1338         WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
1339
1340         evergreen_mc_stop(rdev, &save);
1341         if (evergreen_mc_wait_for_idle(rdev)) {
1342                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1343         }
1344         /* Lockout access through VGA aperture*/
1345         WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
1346         /* Update configuration */
1347         if (rdev->flags & RADEON_IS_AGP) {
1348                 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
1349                         /* VRAM before AGP */
1350                         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1351                                 rdev->mc.vram_start >> 12);
1352                         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1353                                 rdev->mc.gtt_end >> 12);
1354                 } else {
1355                         /* VRAM after AGP */
1356                         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1357                                 rdev->mc.gtt_start >> 12);
1358                         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1359                                 rdev->mc.vram_end >> 12);
1360                 }
1361         } else {
1362                 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1363                         rdev->mc.vram_start >> 12);
1364                 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1365                         rdev->mc.vram_end >> 12);
1366         }
1367         WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12);
1368         /* llano/ontario only */
1369         if ((rdev->family == CHIP_PALM) ||
1370             (rdev->family == CHIP_SUMO) ||
1371             (rdev->family == CHIP_SUMO2)) {
1372                 tmp = RREG32(MC_FUS_VM_FB_OFFSET) & 0x000FFFFF;
1373                 tmp |= ((rdev->mc.vram_end >> 20) & 0xF) << 24;
1374                 tmp |= ((rdev->mc.vram_start >> 20) & 0xF) << 20;
1375                 WREG32(MC_FUS_VM_FB_OFFSET, tmp);
1376         }
1377         tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
1378         tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
1379         WREG32(MC_VM_FB_LOCATION, tmp);
1380         WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
1381         WREG32(HDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));
1382         WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
1383         if (rdev->flags & RADEON_IS_AGP) {
1384                 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16);
1385                 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16);
1386                 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
1387         } else {
1388                 WREG32(MC_VM_AGP_BASE, 0);
1389                 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
1390                 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
1391         }
1392         if (evergreen_mc_wait_for_idle(rdev)) {
1393                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1394         }
1395         evergreen_mc_resume(rdev, &save);
1396         /* we need to own VRAM, so turn off the VGA renderer here
1397          * to stop it overwriting our objects */
1398         rv515_vga_render_disable(rdev);
1399 }
1400
1401 /*
1402  * CP.
1403  */
1404 void evergreen_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
1405 {
1406         struct radeon_ring *ring = &rdev->ring[ib->fence->ring];
1407
1408         /* set to DX10/11 mode */
1409         radeon_ring_write(ring, PACKET3(PACKET3_MODE_CONTROL, 0));
1410         radeon_ring_write(ring, 1);
1411         /* FIXME: implement */
1412         radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
1413         radeon_ring_write(ring,
1414 #ifdef __BIG_ENDIAN
1415                           (2 << 0) |
1416 #endif
1417                           (ib->gpu_addr & 0xFFFFFFFC));
1418         radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF);
1419         radeon_ring_write(ring, ib->length_dw);
1420 }
1421
1422
1423 static int evergreen_cp_load_microcode(struct radeon_device *rdev)
1424 {
1425         const __be32 *fw_data;
1426         int i;
1427
1428         if (!rdev->me_fw || !rdev->pfp_fw)
1429                 return -EINVAL;
1430
1431         r700_cp_stop(rdev);
1432         WREG32(CP_RB_CNTL,
1433 #ifdef __BIG_ENDIAN
1434                BUF_SWAP_32BIT |
1435 #endif
1436                RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
1437
1438         fw_data = (const __be32 *)rdev->pfp_fw->data;
1439         WREG32(CP_PFP_UCODE_ADDR, 0);
1440         for (i = 0; i < EVERGREEN_PFP_UCODE_SIZE; i++)
1441                 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
1442         WREG32(CP_PFP_UCODE_ADDR, 0);
1443
1444         fw_data = (const __be32 *)rdev->me_fw->data;
1445         WREG32(CP_ME_RAM_WADDR, 0);
1446         for (i = 0; i < EVERGREEN_PM4_UCODE_SIZE; i++)
1447                 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
1448
1449         WREG32(CP_PFP_UCODE_ADDR, 0);
1450         WREG32(CP_ME_RAM_WADDR, 0);
1451         WREG32(CP_ME_RAM_RADDR, 0);
1452         return 0;
1453 }
1454
1455 static int evergreen_cp_start(struct radeon_device *rdev)
1456 {
1457         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1458         int r, i;
1459         uint32_t cp_me;
1460
1461         r = radeon_ring_lock(rdev, ring, 7);
1462         if (r) {
1463                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1464                 return r;
1465         }
1466         radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));
1467         radeon_ring_write(ring, 0x1);
1468         radeon_ring_write(ring, 0x0);
1469         radeon_ring_write(ring, rdev->config.evergreen.max_hw_contexts - 1);
1470         radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
1471         radeon_ring_write(ring, 0);
1472         radeon_ring_write(ring, 0);
1473         radeon_ring_unlock_commit(rdev, ring);
1474
1475         cp_me = 0xff;
1476         WREG32(CP_ME_CNTL, cp_me);
1477
1478         r = radeon_ring_lock(rdev, ring, evergreen_default_size + 19);
1479         if (r) {
1480                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1481                 return r;
1482         }
1483
1484         /* setup clear context state */
1485         radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1486         radeon_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
1487
1488         for (i = 0; i < evergreen_default_size; i++)
1489                 radeon_ring_write(ring, evergreen_default_state[i]);
1490
1491         radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1492         radeon_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
1493
1494         /* set clear context state */
1495         radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
1496         radeon_ring_write(ring, 0);
1497
1498         /* SQ_VTX_BASE_VTX_LOC */
1499         radeon_ring_write(ring, 0xc0026f00);
1500         radeon_ring_write(ring, 0x00000000);
1501         radeon_ring_write(ring, 0x00000000);
1502         radeon_ring_write(ring, 0x00000000);
1503
1504         /* Clear consts */
1505         radeon_ring_write(ring, 0xc0036f00);
1506         radeon_ring_write(ring, 0x00000bc4);
1507         radeon_ring_write(ring, 0xffffffff);
1508         radeon_ring_write(ring, 0xffffffff);
1509         radeon_ring_write(ring, 0xffffffff);
1510
1511         radeon_ring_write(ring, 0xc0026900);
1512         radeon_ring_write(ring, 0x00000316);
1513         radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
1514         radeon_ring_write(ring, 0x00000010); /*  */
1515
1516         radeon_ring_unlock_commit(rdev, ring);
1517
1518         return 0;
1519 }
1520
1521 int evergreen_cp_resume(struct radeon_device *rdev)
1522 {
1523         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1524         u32 tmp;
1525         u32 rb_bufsz;
1526         int r;
1527
1528         /* Reset cp; if cp is reset, then PA, SH, VGT also need to be reset */
1529         WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP |
1530                                  SOFT_RESET_PA |
1531                                  SOFT_RESET_SH |
1532                                  SOFT_RESET_VGT |
1533                                  SOFT_RESET_SPI |
1534                                  SOFT_RESET_SX));
1535         RREG32(GRBM_SOFT_RESET);
1536         mdelay(15);
1537         WREG32(GRBM_SOFT_RESET, 0);
1538         RREG32(GRBM_SOFT_RESET);
1539
1540         /* Set ring buffer size */
1541         rb_bufsz = drm_order(ring->ring_size / 8);
1542         tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
1543 #ifdef __BIG_ENDIAN
1544         tmp |= BUF_SWAP_32BIT;
1545 #endif
1546         WREG32(CP_RB_CNTL, tmp);
1547         WREG32(CP_SEM_WAIT_TIMER, 0x0);
1548         WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);
1549
1550         /* Set the write pointer delay */
1551         WREG32(CP_RB_WPTR_DELAY, 0);
1552
1553         /* Initialize the ring buffer's read and write pointers */
1554         WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
1555         WREG32(CP_RB_RPTR_WR, 0);
1556         ring->wptr = 0;
1557         WREG32(CP_RB_WPTR, ring->wptr);
1558
1559         /* set the wb address wether it's enabled or not */
1560         WREG32(CP_RB_RPTR_ADDR,
1561                ((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC));
1562         WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
1563         WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
1564
1565         if (rdev->wb.enabled)
1566                 WREG32(SCRATCH_UMSK, 0xff);
1567         else {
1568                 tmp |= RB_NO_UPDATE;
1569                 WREG32(SCRATCH_UMSK, 0);
1570         }
1571
1572         mdelay(1);
1573         WREG32(CP_RB_CNTL, tmp);
1574
1575         WREG32(CP_RB_BASE, ring->gpu_addr >> 8);
1576         WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
1577
1578         ring->rptr = RREG32(CP_RB_RPTR);
1579
1580         evergreen_cp_start(rdev);
1581         ring->ready = true;
1582         r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring);
1583         if (r) {
1584                 ring->ready = false;
1585                 return r;
1586         }
1587         return 0;
1588 }
1589
1590 /*
1591  * Core functions
1592  */
1593 static u32 evergreen_get_tile_pipe_to_backend_map(struct radeon_device *rdev,
1594                                                   u32 num_tile_pipes,
1595                                                   u32 num_backends,
1596                                                   u32 backend_disable_mask)
1597 {
1598         u32 backend_map = 0;
1599         u32 enabled_backends_mask = 0;
1600         u32 enabled_backends_count = 0;
1601         u32 cur_pipe;
1602         u32 swizzle_pipe[EVERGREEN_MAX_PIPES];
1603         u32 cur_backend = 0;
1604         u32 i;
1605         bool force_no_swizzle;
1606
1607         if (num_tile_pipes > EVERGREEN_MAX_PIPES)
1608                 num_tile_pipes = EVERGREEN_MAX_PIPES;
1609         if (num_tile_pipes < 1)
1610                 num_tile_pipes = 1;
1611         if (num_backends > EVERGREEN_MAX_BACKENDS)
1612                 num_backends = EVERGREEN_MAX_BACKENDS;
1613         if (num_backends < 1)
1614                 num_backends = 1;
1615
1616         for (i = 0; i < EVERGREEN_MAX_BACKENDS; ++i) {
1617                 if (((backend_disable_mask >> i) & 1) == 0) {
1618                         enabled_backends_mask |= (1 << i);
1619                         ++enabled_backends_count;
1620                 }
1621                 if (enabled_backends_count == num_backends)
1622                         break;
1623         }
1624
1625         if (enabled_backends_count == 0) {
1626                 enabled_backends_mask = 1;
1627                 enabled_backends_count = 1;
1628         }
1629
1630         if (enabled_backends_count != num_backends)
1631                 num_backends = enabled_backends_count;
1632
1633         memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * EVERGREEN_MAX_PIPES);
1634         switch (rdev->family) {
1635         case CHIP_CEDAR:
1636         case CHIP_REDWOOD:
1637         case CHIP_PALM:
1638         case CHIP_SUMO:
1639         case CHIP_SUMO2:
1640         case CHIP_TURKS:
1641         case CHIP_CAICOS:
1642                 force_no_swizzle = false;
1643                 break;
1644         case CHIP_CYPRESS:
1645         case CHIP_HEMLOCK:
1646         case CHIP_JUNIPER:
1647         case CHIP_BARTS:
1648         default:
1649                 force_no_swizzle = true;
1650                 break;
1651         }
1652         if (force_no_swizzle) {
1653                 bool last_backend_enabled = false;
1654
1655                 force_no_swizzle = false;
1656                 for (i = 0; i < EVERGREEN_MAX_BACKENDS; ++i) {
1657                         if (((enabled_backends_mask >> i) & 1) == 1) {
1658                                 if (last_backend_enabled)
1659                                         force_no_swizzle = true;
1660                                 last_backend_enabled = true;
1661                         } else
1662                                 last_backend_enabled = false;
1663                 }
1664         }
1665
1666         switch (num_tile_pipes) {
1667         case 1:
1668         case 3:
1669         case 5:
1670         case 7:
1671                 DRM_ERROR("odd number of pipes!\n");
1672                 break;
1673         case 2:
1674                 swizzle_pipe[0] = 0;
1675                 swizzle_pipe[1] = 1;
1676                 break;
1677         case 4:
1678                 if (force_no_swizzle) {
1679                         swizzle_pipe[0] = 0;
1680                         swizzle_pipe[1] = 1;
1681                         swizzle_pipe[2] = 2;
1682                         swizzle_pipe[3] = 3;
1683                 } else {
1684                         swizzle_pipe[0] = 0;
1685                         swizzle_pipe[1] = 2;
1686                         swizzle_pipe[2] = 1;
1687                         swizzle_pipe[3] = 3;
1688                 }
1689                 break;
1690         case 6:
1691                 if (force_no_swizzle) {
1692                         swizzle_pipe[0] = 0;
1693                         swizzle_pipe[1] = 1;
1694                         swizzle_pipe[2] = 2;
1695                         swizzle_pipe[3] = 3;
1696                         swizzle_pipe[4] = 4;
1697                         swizzle_pipe[5] = 5;
1698                 } else {
1699                         swizzle_pipe[0] = 0;
1700                         swizzle_pipe[1] = 2;
1701                         swizzle_pipe[2] = 4;
1702                         swizzle_pipe[3] = 1;
1703                         swizzle_pipe[4] = 3;
1704                         swizzle_pipe[5] = 5;
1705                 }
1706                 break;
1707         case 8:
1708                 if (force_no_swizzle) {
1709                         swizzle_pipe[0] = 0;
1710                         swizzle_pipe[1] = 1;
1711                         swizzle_pipe[2] = 2;
1712                         swizzle_pipe[3] = 3;
1713                         swizzle_pipe[4] = 4;
1714                         swizzle_pipe[5] = 5;
1715                         swizzle_pipe[6] = 6;
1716                         swizzle_pipe[7] = 7;
1717                 } else {
1718                         swizzle_pipe[0] = 0;
1719                         swizzle_pipe[1] = 2;
1720                         swizzle_pipe[2] = 4;
1721                         swizzle_pipe[3] = 6;
1722                         swizzle_pipe[4] = 1;
1723                         swizzle_pipe[5] = 3;
1724                         swizzle_pipe[6] = 5;
1725                         swizzle_pipe[7] = 7;
1726                 }
1727                 break;
1728         }
1729
1730         for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
1731                 while (((1 << cur_backend) & enabled_backends_mask) == 0)
1732                         cur_backend = (cur_backend + 1) % EVERGREEN_MAX_BACKENDS;
1733
1734                 backend_map |= (((cur_backend & 0xf) << (swizzle_pipe[cur_pipe] * 4)));
1735
1736                 cur_backend = (cur_backend + 1) % EVERGREEN_MAX_BACKENDS;
1737         }
1738
1739         return backend_map;
1740 }
1741
1742 static void evergreen_gpu_init(struct radeon_device *rdev)
1743 {
1744         u32 cc_rb_backend_disable = 0;
1745         u32 cc_gc_shader_pipe_config;
1746         u32 gb_addr_config = 0;
1747         u32 mc_shared_chmap, mc_arb_ramcfg;
1748         u32 gb_backend_map;
1749         u32 grbm_gfx_index;
1750         u32 sx_debug_1;
1751         u32 smx_dc_ctl0;
1752         u32 sq_config;
1753         u32 sq_lds_resource_mgmt;
1754         u32 sq_gpr_resource_mgmt_1;
1755         u32 sq_gpr_resource_mgmt_2;
1756         u32 sq_gpr_resource_mgmt_3;
1757         u32 sq_thread_resource_mgmt;
1758         u32 sq_thread_resource_mgmt_2;
1759         u32 sq_stack_resource_mgmt_1;
1760         u32 sq_stack_resource_mgmt_2;
1761         u32 sq_stack_resource_mgmt_3;
1762         u32 vgt_cache_invalidation;
1763         u32 hdp_host_path_cntl, tmp;
1764         int i, j, num_shader_engines, ps_thread_count;
1765
1766         switch (rdev->family) {
1767         case CHIP_CYPRESS:
1768         case CHIP_HEMLOCK:
1769                 rdev->config.evergreen.num_ses = 2;
1770                 rdev->config.evergreen.max_pipes = 4;
1771                 rdev->config.evergreen.max_tile_pipes = 8;
1772                 rdev->config.evergreen.max_simds = 10;
1773                 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
1774                 rdev->config.evergreen.max_gprs = 256;
1775                 rdev->config.evergreen.max_threads = 248;
1776                 rdev->config.evergreen.max_gs_threads = 32;
1777                 rdev->config.evergreen.max_stack_entries = 512;
1778                 rdev->config.evergreen.sx_num_of_sets = 4;
1779                 rdev->config.evergreen.sx_max_export_size = 256;
1780                 rdev->config.evergreen.sx_max_export_pos_size = 64;
1781                 rdev->config.evergreen.sx_max_export_smx_size = 192;
1782                 rdev->config.evergreen.max_hw_contexts = 8;
1783                 rdev->config.evergreen.sq_num_cf_insts = 2;
1784
1785                 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1786                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1787                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1788                 break;
1789         case CHIP_JUNIPER:
1790                 rdev->config.evergreen.num_ses = 1;
1791                 rdev->config.evergreen.max_pipes = 4;
1792                 rdev->config.evergreen.max_tile_pipes = 4;
1793                 rdev->config.evergreen.max_simds = 10;
1794                 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
1795                 rdev->config.evergreen.max_gprs = 256;
1796                 rdev->config.evergreen.max_threads = 248;
1797                 rdev->config.evergreen.max_gs_threads = 32;
1798                 rdev->config.evergreen.max_stack_entries = 512;
1799                 rdev->config.evergreen.sx_num_of_sets = 4;
1800                 rdev->config.evergreen.sx_max_export_size = 256;
1801                 rdev->config.evergreen.sx_max_export_pos_size = 64;
1802                 rdev->config.evergreen.sx_max_export_smx_size = 192;
1803                 rdev->config.evergreen.max_hw_contexts = 8;
1804                 rdev->config.evergreen.sq_num_cf_insts = 2;
1805
1806                 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1807                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1808                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1809                 break;
1810         case CHIP_REDWOOD:
1811                 rdev->config.evergreen.num_ses = 1;
1812                 rdev->config.evergreen.max_pipes = 4;
1813                 rdev->config.evergreen.max_tile_pipes = 4;
1814                 rdev->config.evergreen.max_simds = 5;
1815                 rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses;
1816                 rdev->config.evergreen.max_gprs = 256;
1817                 rdev->config.evergreen.max_threads = 248;
1818                 rdev->config.evergreen.max_gs_threads = 32;
1819                 rdev->config.evergreen.max_stack_entries = 256;
1820                 rdev->config.evergreen.sx_num_of_sets = 4;
1821                 rdev->config.evergreen.sx_max_export_size = 256;
1822                 rdev->config.evergreen.sx_max_export_pos_size = 64;
1823                 rdev->config.evergreen.sx_max_export_smx_size = 192;
1824                 rdev->config.evergreen.max_hw_contexts = 8;
1825                 rdev->config.evergreen.sq_num_cf_insts = 2;
1826
1827                 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1828                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1829                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1830                 break;
1831         case CHIP_CEDAR:
1832         default:
1833                 rdev->config.evergreen.num_ses = 1;
1834                 rdev->config.evergreen.max_pipes = 2;
1835                 rdev->config.evergreen.max_tile_pipes = 2;
1836                 rdev->config.evergreen.max_simds = 2;
1837                 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1838                 rdev->config.evergreen.max_gprs = 256;
1839                 rdev->config.evergreen.max_threads = 192;
1840                 rdev->config.evergreen.max_gs_threads = 16;
1841                 rdev->config.evergreen.max_stack_entries = 256;
1842                 rdev->config.evergreen.sx_num_of_sets = 4;
1843                 rdev->config.evergreen.sx_max_export_size = 128;
1844                 rdev->config.evergreen.sx_max_export_pos_size = 32;
1845                 rdev->config.evergreen.sx_max_export_smx_size = 96;
1846                 rdev->config.evergreen.max_hw_contexts = 4;
1847                 rdev->config.evergreen.sq_num_cf_insts = 1;
1848
1849                 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1850                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1851                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1852                 break;
1853         case CHIP_PALM:
1854                 rdev->config.evergreen.num_ses = 1;
1855                 rdev->config.evergreen.max_pipes = 2;
1856                 rdev->config.evergreen.max_tile_pipes = 2;
1857                 rdev->config.evergreen.max_simds = 2;
1858                 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1859                 rdev->config.evergreen.max_gprs = 256;
1860                 rdev->config.evergreen.max_threads = 192;
1861                 rdev->config.evergreen.max_gs_threads = 16;
1862                 rdev->config.evergreen.max_stack_entries = 256;
1863                 rdev->config.evergreen.sx_num_of_sets = 4;
1864                 rdev->config.evergreen.sx_max_export_size = 128;
1865                 rdev->config.evergreen.sx_max_export_pos_size = 32;
1866                 rdev->config.evergreen.sx_max_export_smx_size = 96;
1867                 rdev->config.evergreen.max_hw_contexts = 4;
1868                 rdev->config.evergreen.sq_num_cf_insts = 1;
1869
1870                 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1871                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1872                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1873                 break;
1874         case CHIP_SUMO:
1875                 rdev->config.evergreen.num_ses = 1;
1876                 rdev->config.evergreen.max_pipes = 4;
1877                 rdev->config.evergreen.max_tile_pipes = 4;
1878                 if (rdev->pdev->device == 0x9648)
1879                         rdev->config.evergreen.max_simds = 3;
1880                 else if ((rdev->pdev->device == 0x9647) ||
1881                          (rdev->pdev->device == 0x964a))
1882                         rdev->config.evergreen.max_simds = 4;
1883                 else
1884                         rdev->config.evergreen.max_simds = 5;
1885                 rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses;
1886                 rdev->config.evergreen.max_gprs = 256;
1887                 rdev->config.evergreen.max_threads = 248;
1888                 rdev->config.evergreen.max_gs_threads = 32;
1889                 rdev->config.evergreen.max_stack_entries = 256;
1890                 rdev->config.evergreen.sx_num_of_sets = 4;
1891                 rdev->config.evergreen.sx_max_export_size = 256;
1892                 rdev->config.evergreen.sx_max_export_pos_size = 64;
1893                 rdev->config.evergreen.sx_max_export_smx_size = 192;
1894                 rdev->config.evergreen.max_hw_contexts = 8;
1895                 rdev->config.evergreen.sq_num_cf_insts = 2;
1896
1897                 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1898                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1899                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1900                 break;
1901         case CHIP_SUMO2:
1902                 rdev->config.evergreen.num_ses = 1;
1903                 rdev->config.evergreen.max_pipes = 4;
1904                 rdev->config.evergreen.max_tile_pipes = 4;
1905                 rdev->config.evergreen.max_simds = 2;
1906                 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1907                 rdev->config.evergreen.max_gprs = 256;
1908                 rdev->config.evergreen.max_threads = 248;
1909                 rdev->config.evergreen.max_gs_threads = 32;
1910                 rdev->config.evergreen.max_stack_entries = 512;
1911                 rdev->config.evergreen.sx_num_of_sets = 4;
1912                 rdev->config.evergreen.sx_max_export_size = 256;
1913                 rdev->config.evergreen.sx_max_export_pos_size = 64;
1914                 rdev->config.evergreen.sx_max_export_smx_size = 192;
1915                 rdev->config.evergreen.max_hw_contexts = 4;
1916                 rdev->config.evergreen.sq_num_cf_insts = 2;
1917
1918                 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1919                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1920                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1921                 break;
1922         case CHIP_BARTS:
1923                 rdev->config.evergreen.num_ses = 2;
1924                 rdev->config.evergreen.max_pipes = 4;
1925                 rdev->config.evergreen.max_tile_pipes = 8;
1926                 rdev->config.evergreen.max_simds = 7;
1927                 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
1928                 rdev->config.evergreen.max_gprs = 256;
1929                 rdev->config.evergreen.max_threads = 248;
1930                 rdev->config.evergreen.max_gs_threads = 32;
1931                 rdev->config.evergreen.max_stack_entries = 512;
1932                 rdev->config.evergreen.sx_num_of_sets = 4;
1933                 rdev->config.evergreen.sx_max_export_size = 256;
1934                 rdev->config.evergreen.sx_max_export_pos_size = 64;
1935                 rdev->config.evergreen.sx_max_export_smx_size = 192;
1936                 rdev->config.evergreen.max_hw_contexts = 8;
1937                 rdev->config.evergreen.sq_num_cf_insts = 2;
1938
1939                 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1940                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1941                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1942                 break;
1943         case CHIP_TURKS:
1944                 rdev->config.evergreen.num_ses = 1;
1945                 rdev->config.evergreen.max_pipes = 4;
1946                 rdev->config.evergreen.max_tile_pipes = 4;
1947                 rdev->config.evergreen.max_simds = 6;
1948                 rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses;
1949                 rdev->config.evergreen.max_gprs = 256;
1950                 rdev->config.evergreen.max_threads = 248;
1951                 rdev->config.evergreen.max_gs_threads = 32;
1952                 rdev->config.evergreen.max_stack_entries = 256;
1953                 rdev->config.evergreen.sx_num_of_sets = 4;
1954                 rdev->config.evergreen.sx_max_export_size = 256;
1955                 rdev->config.evergreen.sx_max_export_pos_size = 64;
1956                 rdev->config.evergreen.sx_max_export_smx_size = 192;
1957                 rdev->config.evergreen.max_hw_contexts = 8;
1958                 rdev->config.evergreen.sq_num_cf_insts = 2;
1959
1960                 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1961                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1962                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1963                 break;
1964         case CHIP_CAICOS:
1965                 rdev->config.evergreen.num_ses = 1;
1966                 rdev->config.evergreen.max_pipes = 2;
1967                 rdev->config.evergreen.max_tile_pipes = 2;
1968                 rdev->config.evergreen.max_simds = 2;
1969                 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1970                 rdev->config.evergreen.max_gprs = 256;
1971                 rdev->config.evergreen.max_threads = 192;
1972                 rdev->config.evergreen.max_gs_threads = 16;
1973                 rdev->config.evergreen.max_stack_entries = 256;
1974                 rdev->config.evergreen.sx_num_of_sets = 4;
1975                 rdev->config.evergreen.sx_max_export_size = 128;
1976                 rdev->config.evergreen.sx_max_export_pos_size = 32;
1977                 rdev->config.evergreen.sx_max_export_smx_size = 96;
1978                 rdev->config.evergreen.max_hw_contexts = 4;
1979                 rdev->config.evergreen.sq_num_cf_insts = 1;
1980
1981                 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1982                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1983                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1984                 break;
1985         }
1986
1987         /* Initialize HDP */
1988         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1989                 WREG32((0x2c14 + j), 0x00000000);
1990                 WREG32((0x2c18 + j), 0x00000000);
1991                 WREG32((0x2c1c + j), 0x00000000);
1992                 WREG32((0x2c20 + j), 0x00000000);
1993                 WREG32((0x2c24 + j), 0x00000000);
1994         }
1995
1996         WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
1997
1998         evergreen_fix_pci_max_read_req_size(rdev);
1999
2000         cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & ~2;
2001
2002         cc_gc_shader_pipe_config |=
2003                 INACTIVE_QD_PIPES((EVERGREEN_MAX_PIPES_MASK << rdev->config.evergreen.max_pipes)
2004                                   & EVERGREEN_MAX_PIPES_MASK);
2005         cc_gc_shader_pipe_config |=
2006                 INACTIVE_SIMDS((EVERGREEN_MAX_SIMDS_MASK << rdev->config.evergreen.max_simds)
2007                                & EVERGREEN_MAX_SIMDS_MASK);
2008
2009         cc_rb_backend_disable =
2010                 BACKEND_DISABLE((EVERGREEN_MAX_BACKENDS_MASK << rdev->config.evergreen.max_backends)
2011                                 & EVERGREEN_MAX_BACKENDS_MASK);
2012
2013
2014         mc_shared_chmap = RREG32(MC_SHARED_CHMAP);
2015         if ((rdev->family == CHIP_PALM) ||
2016             (rdev->family == CHIP_SUMO) ||
2017             (rdev->family == CHIP_SUMO2))
2018                 mc_arb_ramcfg = RREG32(FUS_MC_ARB_RAMCFG);
2019         else
2020                 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
2021
2022         switch (rdev->config.evergreen.max_tile_pipes) {
2023         case 1:
2024         default:
2025                 gb_addr_config |= NUM_PIPES(0);
2026                 break;
2027         case 2:
2028                 gb_addr_config |= NUM_PIPES(1);
2029                 break;
2030         case 4:
2031                 gb_addr_config |= NUM_PIPES(2);
2032                 break;
2033         case 8:
2034                 gb_addr_config |= NUM_PIPES(3);
2035                 break;
2036         }
2037
2038         gb_addr_config |= PIPE_INTERLEAVE_SIZE((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT);
2039         gb_addr_config |= BANK_INTERLEAVE_SIZE(0);
2040         gb_addr_config |= NUM_SHADER_ENGINES(rdev->config.evergreen.num_ses - 1);
2041         gb_addr_config |= SHADER_ENGINE_TILE_SIZE(1);
2042         gb_addr_config |= NUM_GPUS(0); /* Hemlock? */
2043         gb_addr_config |= MULTI_GPU_TILE_SIZE(2);
2044
2045         if (((mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT) > 2)
2046                 gb_addr_config |= ROW_SIZE(2);
2047         else
2048                 gb_addr_config |= ROW_SIZE((mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT);
2049
2050         if (rdev->ddev->pdev->device == 0x689e) {
2051                 u32 efuse_straps_4;
2052                 u32 efuse_straps_3;
2053                 u8 efuse_box_bit_131_124;
2054
2055                 WREG32(RCU_IND_INDEX, 0x204);
2056                 efuse_straps_4 = RREG32(RCU_IND_DATA);
2057                 WREG32(RCU_IND_INDEX, 0x203);
2058                 efuse_straps_3 = RREG32(RCU_IND_DATA);
2059                 efuse_box_bit_131_124 = (u8)(((efuse_straps_4 & 0xf) << 4) | ((efuse_straps_3 & 0xf0000000) >> 28));
2060
2061                 switch(efuse_box_bit_131_124) {
2062                 case 0x00:
2063                         gb_backend_map = 0x76543210;
2064                         break;
2065                 case 0x55:
2066                         gb_backend_map = 0x77553311;
2067                         break;
2068                 case 0x56:
2069                         gb_backend_map = 0x77553300;
2070                         break;
2071                 case 0x59:
2072                         gb_backend_map = 0x77552211;
2073                         break;
2074                 case 0x66:
2075                         gb_backend_map = 0x77443300;
2076                         break;
2077                 case 0x99:
2078                         gb_backend_map = 0x66552211;
2079                         break;
2080                 case 0x5a:
2081                         gb_backend_map = 0x77552200;
2082                         break;
2083                 case 0xaa:
2084                         gb_backend_map = 0x66442200;
2085                         break;
2086                 case 0x95:
2087                         gb_backend_map = 0x66553311;
2088                         break;
2089                 default:
2090                         DRM_ERROR("bad backend map, using default\n");
2091                         gb_backend_map =
2092                                 evergreen_get_tile_pipe_to_backend_map(rdev,
2093                                                                        rdev->config.evergreen.max_tile_pipes,
2094                                                                        rdev->config.evergreen.max_backends,
2095                                                                        ((EVERGREEN_MAX_BACKENDS_MASK <<
2096                                                                    rdev->config.evergreen.max_backends) &
2097                                                                         EVERGREEN_MAX_BACKENDS_MASK));
2098                         break;
2099                 }
2100         } else if (rdev->ddev->pdev->device == 0x68b9) {
2101                 u32 efuse_straps_3;
2102                 u8 efuse_box_bit_127_124;
2103
2104                 WREG32(RCU_IND_INDEX, 0x203);
2105                 efuse_straps_3 = RREG32(RCU_IND_DATA);
2106                 efuse_box_bit_127_124 = (u8)((efuse_straps_3 & 0xF0000000) >> 28);
2107
2108                 switch(efuse_box_bit_127_124) {
2109                 case 0x0:
2110                         gb_backend_map = 0x00003210;
2111                         break;
2112                 case 0x5:
2113                 case 0x6:
2114                 case 0x9:
2115                 case 0xa:
2116                         gb_backend_map = 0x00003311;
2117                         break;
2118                 default:
2119                         DRM_ERROR("bad backend map, using default\n");
2120                         gb_backend_map =
2121                                 evergreen_get_tile_pipe_to_backend_map(rdev,
2122                                                                        rdev->config.evergreen.max_tile_pipes,
2123                                                                        rdev->config.evergreen.max_backends,
2124                                                                        ((EVERGREEN_MAX_BACKENDS_MASK <<
2125                                                                    rdev->config.evergreen.max_backends) &
2126                                                                         EVERGREEN_MAX_BACKENDS_MASK));
2127                         break;
2128                 }
2129         } else {
2130                 switch (rdev->family) {
2131                 case CHIP_CYPRESS:
2132                 case CHIP_HEMLOCK:
2133                 case CHIP_BARTS:
2134                         gb_backend_map = 0x66442200;
2135                         break;
2136                 case CHIP_JUNIPER:
2137                         gb_backend_map = 0x00002200;
2138                         break;
2139                 default:
2140                         gb_backend_map =
2141                                 evergreen_get_tile_pipe_to_backend_map(rdev,
2142                                                                        rdev->config.evergreen.max_tile_pipes,
2143                                                                        rdev->config.evergreen.max_backends,
2144                                                                        ((EVERGREEN_MAX_BACKENDS_MASK <<
2145                                                                          rdev->config.evergreen.max_backends) &
2146                                                                         EVERGREEN_MAX_BACKENDS_MASK));
2147                 }
2148         }
2149
2150         /* setup tiling info dword.  gb_addr_config is not adequate since it does
2151          * not have bank info, so create a custom tiling dword.
2152          * bits 3:0   num_pipes
2153          * bits 7:4   num_banks
2154          * bits 11:8  group_size
2155          * bits 15:12 row_size
2156          */
2157         rdev->config.evergreen.tile_config = 0;
2158         switch (rdev->config.evergreen.max_tile_pipes) {
2159         case 1:
2160         default:
2161                 rdev->config.evergreen.tile_config |= (0 << 0);
2162                 break;
2163         case 2:
2164                 rdev->config.evergreen.tile_config |= (1 << 0);
2165                 break;
2166         case 4:
2167                 rdev->config.evergreen.tile_config |= (2 << 0);
2168                 break;
2169         case 8:
2170                 rdev->config.evergreen.tile_config |= (3 << 0);
2171                 break;
2172         }
2173         /* num banks is 8 on all fusion asics. 0 = 4, 1 = 8, 2 = 16 */
2174         if (rdev->flags & RADEON_IS_IGP)
2175                 rdev->config.evergreen.tile_config |= 1 << 4;
2176         else {
2177                 switch ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) {
2178                 case 0: /* four banks */
2179                         rdev->config.evergreen.tile_config |= 0 << 4;
2180                         break;
2181                 case 1: /* eight banks */
2182                         rdev->config.evergreen.tile_config |= 1 << 4;
2183                         break;
2184                 case 2: /* sixteen banks */
2185                 default:
2186                         rdev->config.evergreen.tile_config |= 2 << 4;
2187                         break;
2188                 }
2189         }
2190         rdev->config.evergreen.tile_config |=
2191                 ((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT) << 8;
2192         rdev->config.evergreen.tile_config |=
2193                 ((gb_addr_config & 0x30000000) >> 28) << 12;
2194
2195         rdev->config.evergreen.backend_map = gb_backend_map;
2196         WREG32(GB_BACKEND_MAP, gb_backend_map);
2197         WREG32(GB_ADDR_CONFIG, gb_addr_config);
2198         WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
2199         WREG32(HDP_ADDR_CONFIG, gb_addr_config);
2200
2201         num_shader_engines = ((RREG32(GB_ADDR_CONFIG) & NUM_SHADER_ENGINES(3)) >> 12) + 1;
2202         grbm_gfx_index = INSTANCE_BROADCAST_WRITES;
2203
2204         for (i = 0; i < rdev->config.evergreen.num_ses; i++) {
2205                 u32 rb = cc_rb_backend_disable | (0xf0 << 16);
2206                 u32 sp = cc_gc_shader_pipe_config;
2207                 u32 gfx = grbm_gfx_index | SE_INDEX(i);
2208
2209                 if (i == num_shader_engines) {
2210                         rb |= BACKEND_DISABLE(EVERGREEN_MAX_BACKENDS_MASK);
2211                         sp |= INACTIVE_SIMDS(EVERGREEN_MAX_SIMDS_MASK);
2212                 }
2213
2214                 WREG32(GRBM_GFX_INDEX, gfx);
2215                 WREG32(RLC_GFX_INDEX, gfx);
2216
2217                 WREG32(CC_RB_BACKEND_DISABLE, rb);
2218                 WREG32(CC_SYS_RB_BACKEND_DISABLE, rb);
2219                 WREG32(GC_USER_RB_BACKEND_DISABLE, rb);
2220                 WREG32(CC_GC_SHADER_PIPE_CONFIG, sp);
2221         }
2222
2223         grbm_gfx_index = INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES;
2224         WREG32(GRBM_GFX_INDEX, grbm_gfx_index);
2225         WREG32(RLC_GFX_INDEX, grbm_gfx_index);
2226
2227         WREG32(CGTS_SYS_TCC_DISABLE, 0);
2228         WREG32(CGTS_TCC_DISABLE, 0);
2229         WREG32(CGTS_USER_SYS_TCC_DISABLE, 0);
2230         WREG32(CGTS_USER_TCC_DISABLE, 0);
2231
2232         /* set HW defaults for 3D engine */
2233         WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) |
2234                                      ROQ_IB2_START(0x2b)));
2235
2236         WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30));
2237
2238         WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO |
2239                              SYNC_GRADIENT |
2240                              SYNC_WALKER |
2241                              SYNC_ALIGNER));
2242
2243         sx_debug_1 = RREG32(SX_DEBUG_1);
2244         sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS;
2245         WREG32(SX_DEBUG_1, sx_debug_1);
2246
2247
2248         smx_dc_ctl0 = RREG32(SMX_DC_CTL0);
2249         smx_dc_ctl0 &= ~NUMBER_OF_SETS(0x1ff);
2250         smx_dc_ctl0 |= NUMBER_OF_SETS(rdev->config.evergreen.sx_num_of_sets);
2251         WREG32(SMX_DC_CTL0, smx_dc_ctl0);
2252
2253         if (rdev->family <= CHIP_SUMO2)
2254                 WREG32(SMX_SAR_CTL0, 0x00010000);
2255
2256         WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_size / 4) - 1) |
2257                                         POSITION_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_pos_size / 4) - 1) |
2258                                         SMX_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_smx_size / 4) - 1)));
2259
2260         WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.evergreen.sc_prim_fifo_size) |
2261                                  SC_HIZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_hiz_tile_fifo_size) |
2262                                  SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_earlyz_tile_fifo_size)));
2263
2264         WREG32(VGT_NUM_INSTANCES, 1);
2265         WREG32(SPI_CONFIG_CNTL, 0);
2266         WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));
2267         WREG32(CP_PERFMON_CNTL, 0);
2268
2269         WREG32(SQ_MS_FIFO_SIZES, (CACHE_FIFO_SIZE(16 * rdev->config.evergreen.sq_num_cf_insts) |
2270                                   FETCH_FIFO_HIWATER(0x4) |
2271                                   DONE_FIFO_HIWATER(0xe0) |
2272                                   ALU_UPDATE_FIFO_HIWATER(0x8)));
2273
2274         sq_config = RREG32(SQ_CONFIG);
2275         sq_config &= ~(PS_PRIO(3) |
2276                        VS_PRIO(3) |
2277                        GS_PRIO(3) |
2278                        ES_PRIO(3));
2279         sq_config |= (VC_ENABLE |
2280                       EXPORT_SRC_C |
2281                       PS_PRIO(0) |
2282                       VS_PRIO(1) |
2283                       GS_PRIO(2) |
2284                       ES_PRIO(3));
2285
2286         switch (rdev->family) {
2287         case CHIP_CEDAR:
2288         case CHIP_PALM:
2289         case CHIP_SUMO:
2290         case CHIP_SUMO2:
2291         case CHIP_CAICOS:
2292                 /* no vertex cache */
2293                 sq_config &= ~VC_ENABLE;
2294                 break;
2295         default:
2296                 break;
2297         }
2298
2299         sq_lds_resource_mgmt = RREG32(SQ_LDS_RESOURCE_MGMT);
2300
2301         sq_gpr_resource_mgmt_1 = NUM_PS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2))* 12 / 32);
2302         sq_gpr_resource_mgmt_1 |= NUM_VS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 6 / 32);
2303         sq_gpr_resource_mgmt_1 |= NUM_CLAUSE_TEMP_GPRS(4);
2304         sq_gpr_resource_mgmt_2 = NUM_GS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 4 / 32);
2305         sq_gpr_resource_mgmt_2 |= NUM_ES_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 4 / 32);
2306         sq_gpr_resource_mgmt_3 = NUM_HS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32);
2307         sq_gpr_resource_mgmt_3 |= NUM_LS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32);
2308
2309         switch (rdev->family) {
2310         case CHIP_CEDAR:
2311         case CHIP_PALM:
2312         case CHIP_SUMO:
2313         case CHIP_SUMO2:
2314                 ps_thread_count = 96;
2315                 break;
2316         default:
2317                 ps_thread_count = 128;
2318                 break;
2319         }
2320
2321         sq_thread_resource_mgmt = NUM_PS_THREADS(ps_thread_count);
2322         sq_thread_resource_mgmt |= NUM_VS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2323         sq_thread_resource_mgmt |= NUM_GS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2324         sq_thread_resource_mgmt |= NUM_ES_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2325         sq_thread_resource_mgmt_2 = NUM_HS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2326         sq_thread_resource_mgmt_2 |= NUM_LS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2327
2328         sq_stack_resource_mgmt_1 = NUM_PS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2329         sq_stack_resource_mgmt_1 |= NUM_VS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2330         sq_stack_resource_mgmt_2 = NUM_GS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2331         sq_stack_resource_mgmt_2 |= NUM_ES_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2332         sq_stack_resource_mgmt_3 = NUM_HS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2333         sq_stack_resource_mgmt_3 |= NUM_LS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2334
2335         WREG32(SQ_CONFIG, sq_config);
2336         WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1);
2337         WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2);
2338         WREG32(SQ_GPR_RESOURCE_MGMT_3, sq_gpr_resource_mgmt_3);
2339         WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
2340         WREG32(SQ_THREAD_RESOURCE_MGMT_2, sq_thread_resource_mgmt_2);
2341         WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
2342         WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
2343         WREG32(SQ_STACK_RESOURCE_MGMT_3, sq_stack_resource_mgmt_3);
2344         WREG32(SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0);
2345         WREG32(SQ_LDS_RESOURCE_MGMT, sq_lds_resource_mgmt);
2346
2347         WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
2348                                           FORCE_EOV_MAX_REZ_CNT(255)));
2349
2350         switch (rdev->family) {
2351         case CHIP_CEDAR:
2352         case CHIP_PALM:
2353         case CHIP_SUMO:
2354         case CHIP_SUMO2:
2355         case CHIP_CAICOS:
2356                 vgt_cache_invalidation = CACHE_INVALIDATION(TC_ONLY);
2357                 break;
2358         default:
2359                 vgt_cache_invalidation = CACHE_INVALIDATION(VC_AND_TC);
2360                 break;
2361         }
2362         vgt_cache_invalidation |= AUTO_INVLD_EN(ES_AND_GS_AUTO);
2363         WREG32(VGT_CACHE_INVALIDATION, vgt_cache_invalidation);
2364
2365         WREG32(VGT_GS_VERTEX_REUSE, 16);
2366         WREG32(PA_SU_LINE_STIPPLE_VALUE, 0);
2367         WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
2368
2369         WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
2370         WREG32(VGT_OUT_DEALLOC_CNTL, 16);
2371
2372         WREG32(CB_PERF_CTR0_SEL_0, 0);
2373         WREG32(CB_PERF_CTR0_SEL_1, 0);
2374         WREG32(CB_PERF_CTR1_SEL_0, 0);
2375         WREG32(CB_PERF_CTR1_SEL_1, 0);
2376         WREG32(CB_PERF_CTR2_SEL_0, 0);
2377         WREG32(CB_PERF_CTR2_SEL_1, 0);
2378         WREG32(CB_PERF_CTR3_SEL_0, 0);
2379         WREG32(CB_PERF_CTR3_SEL_1, 0);
2380
2381         /* clear render buffer base addresses */
2382         WREG32(CB_COLOR0_BASE, 0);
2383         WREG32(CB_COLOR1_BASE, 0);
2384         WREG32(CB_COLOR2_BASE, 0);
2385         WREG32(CB_COLOR3_BASE, 0);
2386         WREG32(CB_COLOR4_BASE, 0);
2387         WREG32(CB_COLOR5_BASE, 0);
2388         WREG32(CB_COLOR6_BASE, 0);
2389         WREG32(CB_COLOR7_BASE, 0);
2390         WREG32(CB_COLOR8_BASE, 0);
2391         WREG32(CB_COLOR9_BASE, 0);
2392         WREG32(CB_COLOR10_BASE, 0);
2393         WREG32(CB_COLOR11_BASE, 0);
2394
2395         /* set the shader const cache sizes to 0 */
2396         for (i = SQ_ALU_CONST_BUFFER_SIZE_PS_0; i < 0x28200; i += 4)
2397                 WREG32(i, 0);
2398         for (i = SQ_ALU_CONST_BUFFER_SIZE_HS_0; i < 0x29000; i += 4)
2399                 WREG32(i, 0);
2400
2401         tmp = RREG32(HDP_MISC_CNTL);
2402         tmp |= HDP_FLUSH_INVALIDATE_CACHE;
2403         WREG32(HDP_MISC_CNTL, tmp);
2404
2405         hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
2406         WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
2407
2408         WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));
2409
2410         udelay(50);
2411
2412 }
2413
2414 int evergreen_mc_init(struct radeon_device *rdev)
2415 {
2416         u32 tmp;
2417         int chansize, numchan;
2418
2419         /* Get VRAM informations */
2420         rdev->mc.vram_is_ddr = true;
2421         if ((rdev->family == CHIP_PALM) ||
2422             (rdev->family == CHIP_SUMO) ||
2423             (rdev->family == CHIP_SUMO2))
2424                 tmp = RREG32(FUS_MC_ARB_RAMCFG);
2425         else
2426                 tmp = RREG32(MC_ARB_RAMCFG);
2427         if (tmp & CHANSIZE_OVERRIDE) {
2428                 chansize = 16;
2429         } else if (tmp & CHANSIZE_MASK) {
2430                 chansize = 64;
2431         } else {
2432                 chansize = 32;
2433         }
2434         tmp = RREG32(MC_SHARED_CHMAP);
2435         switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
2436         case 0:
2437         default:
2438                 numchan = 1;
2439                 break;
2440         case 1:
2441                 numchan = 2;
2442                 break;
2443         case 2:
2444                 numchan = 4;
2445                 break;
2446         case 3:
2447                 numchan = 8;
2448                 break;
2449         }
2450         rdev->mc.vram_width = numchan * chansize;
2451         /* Could aper size report 0 ? */
2452         rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
2453         rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
2454         /* Setup GPU memory space */
2455         if ((rdev->family == CHIP_PALM) ||
2456             (rdev->family == CHIP_SUMO) ||
2457             (rdev->family == CHIP_SUMO2)) {
2458                 /* size in bytes on fusion */
2459                 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
2460                 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
2461         } else {
2462                 /* size in MB on evergreen/cayman/tn */
2463                 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024ULL * 1024ULL;
2464                 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024ULL * 1024ULL;
2465         }
2466         rdev->mc.visible_vram_size = rdev->mc.aper_size;
2467         r700_vram_gtt_location(rdev, &rdev->mc);
2468         radeon_update_bandwidth_info(rdev);
2469
2470         return 0;
2471 }
2472
2473 bool evergreen_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
2474 {
2475         u32 srbm_status;
2476         u32 grbm_status;
2477         u32 grbm_status_se0, grbm_status_se1;
2478         struct r100_gpu_lockup *lockup = &rdev->config.evergreen.lockup;
2479         int r;
2480
2481         srbm_status = RREG32(SRBM_STATUS);
2482         grbm_status = RREG32(GRBM_STATUS);
2483         grbm_status_se0 = RREG32(GRBM_STATUS_SE0);
2484         grbm_status_se1 = RREG32(GRBM_STATUS_SE1);
2485         if (!(grbm_status & GUI_ACTIVE)) {
2486                 r100_gpu_lockup_update(lockup, ring);
2487                 return false;
2488         }
2489         /* force CP activities */
2490         r = radeon_ring_lock(rdev, ring, 2);
2491         if (!r) {
2492                 /* PACKET2 NOP */
2493                 radeon_ring_write(ring, 0x80000000);
2494                 radeon_ring_write(ring, 0x80000000);
2495                 radeon_ring_unlock_commit(rdev, ring);
2496         }
2497         ring->rptr = RREG32(CP_RB_RPTR);
2498         return r100_gpu_cp_is_lockup(rdev, lockup, ring);
2499 }
2500
2501 static int evergreen_gpu_soft_reset(struct radeon_device *rdev)
2502 {
2503         struct evergreen_mc_save save;
2504         u32 grbm_reset = 0;
2505
2506         if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE))
2507                 return 0;
2508
2509         dev_info(rdev->dev, "GPU softreset \n");
2510         dev_info(rdev->dev, "  GRBM_STATUS=0x%08X\n",
2511                 RREG32(GRBM_STATUS));
2512         dev_info(rdev->dev, "  GRBM_STATUS_SE0=0x%08X\n",
2513                 RREG32(GRBM_STATUS_SE0));
2514         dev_info(rdev->dev, "  GRBM_STATUS_SE1=0x%08X\n",
2515                 RREG32(GRBM_STATUS_SE1));
2516         dev_info(rdev->dev, "  SRBM_STATUS=0x%08X\n",
2517                 RREG32(SRBM_STATUS));
2518         evergreen_mc_stop(rdev, &save);
2519         if (evergreen_mc_wait_for_idle(rdev)) {
2520                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
2521         }
2522         /* Disable CP parsing/prefetching */
2523         WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT);
2524
2525         /* reset all the gfx blocks */
2526         grbm_reset = (SOFT_RESET_CP |
2527                       SOFT_RESET_CB |
2528                       SOFT_RESET_DB |
2529                       SOFT_RESET_PA |
2530                       SOFT_RESET_SC |
2531                       SOFT_RESET_SPI |
2532                       SOFT_RESET_SH |
2533                       SOFT_RESET_SX |
2534                       SOFT_RESET_TC |
2535                       SOFT_RESET_TA |
2536                       SOFT_RESET_VC |
2537                       SOFT_RESET_VGT);
2538
2539         dev_info(rdev->dev, "  GRBM_SOFT_RESET=0x%08X\n", grbm_reset);
2540         WREG32(GRBM_SOFT_RESET, grbm_reset);
2541         (void)RREG32(GRBM_SOFT_RESET);
2542         udelay(50);
2543         WREG32(GRBM_SOFT_RESET, 0);
2544         (void)RREG32(GRBM_SOFT_RESET);
2545         /* Wait a little for things to settle down */
2546         udelay(50);
2547         dev_info(rdev->dev, "  GRBM_STATUS=0x%08X\n",
2548                 RREG32(GRBM_STATUS));
2549         dev_info(rdev->dev, "  GRBM_STATUS_SE0=0x%08X\n",
2550                 RREG32(GRBM_STATUS_SE0));
2551         dev_info(rdev->dev, "  GRBM_STATUS_SE1=0x%08X\n",
2552                 RREG32(GRBM_STATUS_SE1));
2553         dev_info(rdev->dev, "  SRBM_STATUS=0x%08X\n",
2554                 RREG32(SRBM_STATUS));
2555         evergreen_mc_resume(rdev, &save);
2556         return 0;
2557 }
2558
2559 int evergreen_asic_reset(struct radeon_device *rdev)
2560 {
2561         return evergreen_gpu_soft_reset(rdev);
2562 }
2563
2564 /* Interrupts */
2565
2566 u32 evergreen_get_vblank_counter(struct radeon_device *rdev, int crtc)
2567 {
2568         switch (crtc) {
2569         case 0:
2570                 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC0_REGISTER_OFFSET);
2571         case 1:
2572                 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC1_REGISTER_OFFSET);
2573         case 2:
2574                 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC2_REGISTER_OFFSET);
2575         case 3:
2576                 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC3_REGISTER_OFFSET);
2577         case 4:
2578                 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC4_REGISTER_OFFSET);
2579         case 5:
2580                 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC5_REGISTER_OFFSET);
2581         default:
2582                 return 0;
2583         }
2584 }
2585
2586 void evergreen_disable_interrupt_state(struct radeon_device *rdev)
2587 {
2588         u32 tmp;
2589
2590         if (rdev->family >= CHIP_CAYMAN) {
2591                 cayman_cp_int_cntl_setup(rdev, 0,
2592                                          CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
2593                 cayman_cp_int_cntl_setup(rdev, 1, 0);
2594                 cayman_cp_int_cntl_setup(rdev, 2, 0);
2595         } else
2596                 WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
2597         WREG32(GRBM_INT_CNTL, 0);
2598         WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
2599         WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
2600         if (rdev->num_crtc >= 4) {
2601                 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
2602                 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
2603         }
2604         if (rdev->num_crtc >= 6) {
2605                 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
2606                 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
2607         }
2608
2609         WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
2610         WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
2611         if (rdev->num_crtc >= 4) {
2612                 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
2613                 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
2614         }
2615         if (rdev->num_crtc >= 6) {
2616                 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
2617                 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
2618         }
2619
2620         /* only one DAC on DCE6 */
2621         if (!ASIC_IS_DCE6(rdev))
2622                 WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
2623         WREG32(DACB_AUTODETECT_INT_CONTROL, 0);
2624
2625         tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2626         WREG32(DC_HPD1_INT_CONTROL, tmp);
2627         tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2628         WREG32(DC_HPD2_INT_CONTROL, tmp);
2629         tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2630         WREG32(DC_HPD3_INT_CONTROL, tmp);
2631         tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2632         WREG32(DC_HPD4_INT_CONTROL, tmp);
2633         tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2634         WREG32(DC_HPD5_INT_CONTROL, tmp);
2635         tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2636         WREG32(DC_HPD6_INT_CONTROL, tmp);
2637
2638 }
2639
2640 int evergreen_irq_set(struct radeon_device *rdev)
2641 {
2642         u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
2643         u32 cp_int_cntl1 = 0, cp_int_cntl2 = 0;
2644         u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0;
2645         u32 hpd1, hpd2, hpd3, hpd4, hpd5, hpd6;
2646         u32 grbm_int_cntl = 0;
2647         u32 grph1 = 0, grph2 = 0, grph3 = 0, grph4 = 0, grph5 = 0, grph6 = 0;
2648
2649         if (!rdev->irq.installed) {
2650                 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
2651                 return -EINVAL;
2652         }
2653         /* don't enable anything if the ih is disabled */
2654         if (!rdev->ih.enabled) {
2655                 r600_disable_interrupts(rdev);
2656                 /* force the active interrupt state to all disabled */
2657                 evergreen_disable_interrupt_state(rdev);
2658                 return 0;
2659         }
2660
2661         hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
2662         hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
2663         hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
2664         hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
2665         hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
2666         hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
2667
2668         if (rdev->family >= CHIP_CAYMAN) {
2669                 /* enable CP interrupts on all rings */
2670                 if (rdev->irq.sw_int[RADEON_RING_TYPE_GFX_INDEX]) {
2671                         DRM_DEBUG("evergreen_irq_set: sw int gfx\n");
2672                         cp_int_cntl |= TIME_STAMP_INT_ENABLE;
2673                 }
2674                 if (rdev->irq.sw_int[CAYMAN_RING_TYPE_CP1_INDEX]) {
2675                         DRM_DEBUG("evergreen_irq_set: sw int cp1\n");
2676                         cp_int_cntl1 |= TIME_STAMP_INT_ENABLE;
2677                 }
2678                 if (rdev->irq.sw_int[CAYMAN_RING_TYPE_CP2_INDEX]) {
2679                         DRM_DEBUG("evergreen_irq_set: sw int cp2\n");
2680                         cp_int_cntl2 |= TIME_STAMP_INT_ENABLE;
2681                 }
2682         } else {
2683                 if (rdev->irq.sw_int[RADEON_RING_TYPE_GFX_INDEX]) {
2684                         DRM_DEBUG("evergreen_irq_set: sw int gfx\n");
2685                         cp_int_cntl |= RB_INT_ENABLE;
2686                         cp_int_cntl |= TIME_STAMP_INT_ENABLE;
2687                 }
2688         }
2689
2690         if (rdev->irq.crtc_vblank_int[0] ||
2691             rdev->irq.pflip[0]) {
2692                 DRM_DEBUG("evergreen_irq_set: vblank 0\n");
2693                 crtc1 |= VBLANK_INT_MASK;
2694         }
2695         if (rdev->irq.crtc_vblank_int[1] ||
2696             rdev->irq.pflip[1]) {
2697                 DRM_DEBUG("evergreen_irq_set: vblank 1\n");
2698                 crtc2 |= VBLANK_INT_MASK;
2699         }
2700         if (rdev->irq.crtc_vblank_int[2] ||
2701             rdev->irq.pflip[2]) {
2702                 DRM_DEBUG("evergreen_irq_set: vblank 2\n");
2703                 crtc3 |= VBLANK_INT_MASK;
2704         }
2705         if (rdev->irq.crtc_vblank_int[3] ||
2706             rdev->irq.pflip[3]) {
2707                 DRM_DEBUG("evergreen_irq_set: vblank 3\n");
2708                 crtc4 |= VBLANK_INT_MASK;
2709         }
2710         if (rdev->irq.crtc_vblank_int[4] ||
2711             rdev->irq.pflip[4]) {
2712                 DRM_DEBUG("evergreen_irq_set: vblank 4\n");
2713                 crtc5 |= VBLANK_INT_MASK;
2714         }
2715         if (rdev->irq.crtc_vblank_int[5] ||
2716             rdev->irq.pflip[5]) {
2717                 DRM_DEBUG("evergreen_irq_set: vblank 5\n");
2718                 crtc6 |= VBLANK_INT_MASK;
2719         }
2720         if (rdev->irq.hpd[0]) {
2721                 DRM_DEBUG("evergreen_irq_set: hpd 1\n");
2722                 hpd1 |= DC_HPDx_INT_EN;
2723         }
2724         if (rdev->irq.hpd[1]) {
2725                 DRM_DEBUG("evergreen_irq_set: hpd 2\n");
2726                 hpd2 |= DC_HPDx_INT_EN;
2727         }
2728         if (rdev->irq.hpd[2]) {
2729                 DRM_DEBUG("evergreen_irq_set: hpd 3\n");
2730                 hpd3 |= DC_HPDx_INT_EN;
2731         }
2732         if (rdev->irq.hpd[3]) {
2733                 DRM_DEBUG("evergreen_irq_set: hpd 4\n");
2734                 hpd4 |= DC_HPDx_INT_EN;
2735         }
2736         if (rdev->irq.hpd[4]) {
2737                 DRM_DEBUG("evergreen_irq_set: hpd 5\n");
2738                 hpd5 |= DC_HPDx_INT_EN;
2739         }
2740         if (rdev->irq.hpd[5]) {
2741                 DRM_DEBUG("evergreen_irq_set: hpd 6\n");
2742                 hpd6 |= DC_HPDx_INT_EN;
2743         }
2744         if (rdev->irq.gui_idle) {
2745                 DRM_DEBUG("gui idle\n");
2746                 grbm_int_cntl |= GUI_IDLE_INT_ENABLE;
2747         }
2748
2749         if (rdev->family >= CHIP_CAYMAN) {
2750                 cayman_cp_int_cntl_setup(rdev, 0, cp_int_cntl);
2751                 cayman_cp_int_cntl_setup(rdev, 1, cp_int_cntl1);
2752                 cayman_cp_int_cntl_setup(rdev, 2, cp_int_cntl2);
2753         } else
2754                 WREG32(CP_INT_CNTL, cp_int_cntl);
2755         WREG32(GRBM_INT_CNTL, grbm_int_cntl);
2756
2757         WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1);
2758         WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2);
2759         if (rdev->num_crtc >= 4) {
2760                 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, crtc3);
2761                 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, crtc4);
2762         }
2763         if (rdev->num_crtc >= 6) {
2764                 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, crtc5);
2765                 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6);
2766         }
2767
2768         WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, grph1);
2769         WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, grph2);
2770         if (rdev->num_crtc >= 4) {
2771                 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, grph3);
2772                 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, grph4);
2773         }
2774         if (rdev->num_crtc >= 6) {
2775                 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, grph5);
2776                 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, grph6);
2777         }
2778
2779         WREG32(DC_HPD1_INT_CONTROL, hpd1);
2780         WREG32(DC_HPD2_INT_CONTROL, hpd2);
2781         WREG32(DC_HPD3_INT_CONTROL, hpd3);
2782         WREG32(DC_HPD4_INT_CONTROL, hpd4);
2783         WREG32(DC_HPD5_INT_CONTROL, hpd5);
2784         WREG32(DC_HPD6_INT_CONTROL, hpd6);
2785
2786         return 0;
2787 }
2788
2789 static void evergreen_irq_ack(struct radeon_device *rdev)
2790 {
2791         u32 tmp;
2792
2793         rdev->irq.stat_regs.evergreen.disp_int = RREG32(DISP_INTERRUPT_STATUS);
2794         rdev->irq.stat_regs.evergreen.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
2795         rdev->irq.stat_regs.evergreen.disp_int_cont2 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE2);
2796         rdev->irq.stat_regs.evergreen.disp_int_cont3 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE3);
2797         rdev->irq.stat_regs.evergreen.disp_int_cont4 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE4);
2798         rdev->irq.stat_regs.evergreen.disp_int_cont5 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE5);
2799         rdev->irq.stat_regs.evergreen.d1grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET);
2800         rdev->irq.stat_regs.evergreen.d2grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET);
2801         if (rdev->num_crtc >= 4) {
2802                 rdev->irq.stat_regs.evergreen.d3grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET);
2803                 rdev->irq.stat_regs.evergreen.d4grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET);
2804         }
2805         if (rdev->num_crtc >= 6) {
2806                 rdev->irq.stat_regs.evergreen.d5grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET);
2807                 rdev->irq.stat_regs.evergreen.d6grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET);
2808         }
2809
2810         if (rdev->irq.stat_regs.evergreen.d1grph_int & GRPH_PFLIP_INT_OCCURRED)
2811                 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2812         if (rdev->irq.stat_regs.evergreen.d2grph_int & GRPH_PFLIP_INT_OCCURRED)
2813                 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2814         if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT)
2815                 WREG32(VBLANK_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VBLANK_ACK);
2816         if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT)
2817                 WREG32(VLINE_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VLINE_ACK);
2818         if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT)
2819                 WREG32(VBLANK_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VBLANK_ACK);
2820         if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT)
2821                 WREG32(VLINE_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VLINE_ACK);
2822
2823         if (rdev->num_crtc >= 4) {
2824                 if (rdev->irq.stat_regs.evergreen.d3grph_int & GRPH_PFLIP_INT_OCCURRED)
2825                         WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2826                 if (rdev->irq.stat_regs.evergreen.d4grph_int & GRPH_PFLIP_INT_OCCURRED)
2827                         WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2828                 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT)
2829                         WREG32(VBLANK_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VBLANK_ACK);
2830                 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT)
2831                         WREG32(VLINE_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VLINE_ACK);
2832                 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT)
2833                         WREG32(VBLANK_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VBLANK_ACK);
2834                 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT)
2835                         WREG32(VLINE_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VLINE_ACK);
2836         }
2837
2838         if (rdev->num_crtc >= 6) {
2839                 if (rdev->irq.stat_regs.evergreen.d5grph_int & GRPH_PFLIP_INT_OCCURRED)
2840                         WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2841                 if (rdev->irq.stat_regs.evergreen.d6grph_int & GRPH_PFLIP_INT_OCCURRED)
2842                         WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2843                 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT)
2844                         WREG32(VBLANK_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VBLANK_ACK);
2845                 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT)
2846                         WREG32(VLINE_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VLINE_ACK);
2847                 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT)
2848                         WREG32(VBLANK_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VBLANK_ACK);
2849                 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT)
2850                         WREG32(VLINE_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VLINE_ACK);
2851         }
2852
2853         if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) {
2854                 tmp = RREG32(DC_HPD1_INT_CONTROL);
2855                 tmp |= DC_HPDx_INT_ACK;
2856                 WREG32(DC_HPD1_INT_CONTROL, tmp);
2857         }
2858         if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) {
2859                 tmp = RREG32(DC_HPD2_INT_CONTROL);
2860                 tmp |= DC_HPDx_INT_ACK;
2861                 WREG32(DC_HPD2_INT_CONTROL, tmp);
2862         }
2863         if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) {
2864                 tmp = RREG32(DC_HPD3_INT_CONTROL);
2865                 tmp |= DC_HPDx_INT_ACK;
2866                 WREG32(DC_HPD3_INT_CONTROL, tmp);
2867         }
2868         if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) {
2869                 tmp = RREG32(DC_HPD4_INT_CONTROL);
2870                 tmp |= DC_HPDx_INT_ACK;
2871                 WREG32(DC_HPD4_INT_CONTROL, tmp);
2872         }
2873         if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) {
2874                 tmp = RREG32(DC_HPD5_INT_CONTROL);
2875                 tmp |= DC_HPDx_INT_ACK;
2876                 WREG32(DC_HPD5_INT_CONTROL, tmp);
2877         }
2878         if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) {
2879                 tmp = RREG32(DC_HPD5_INT_CONTROL);
2880                 tmp |= DC_HPDx_INT_ACK;
2881                 WREG32(DC_HPD6_INT_CONTROL, tmp);
2882         }
2883 }
2884
2885 void evergreen_irq_disable(struct radeon_device *rdev)
2886 {
2887         r600_disable_interrupts(rdev);
2888         /* Wait and acknowledge irq */
2889         mdelay(1);
2890         evergreen_irq_ack(rdev);
2891         evergreen_disable_interrupt_state(rdev);
2892 }
2893
2894 void evergreen_irq_suspend(struct radeon_device *rdev)
2895 {
2896         evergreen_irq_disable(rdev);
2897         r600_rlc_stop(rdev);
2898 }
2899
2900 static u32 evergreen_get_ih_wptr(struct radeon_device *rdev)
2901 {
2902         u32 wptr, tmp;
2903
2904         if (rdev->wb.enabled)
2905                 wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]);
2906         else
2907                 wptr = RREG32(IH_RB_WPTR);
2908
2909         if (wptr & RB_OVERFLOW) {
2910                 /* When a ring buffer overflow happen start parsing interrupt
2911                  * from the last not overwritten vector (wptr + 16). Hopefully
2912                  * this should allow us to catchup.
2913                  */
2914                 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n",
2915                         wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask);
2916                 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
2917                 tmp = RREG32(IH_RB_CNTL);
2918                 tmp |= IH_WPTR_OVERFLOW_CLEAR;
2919                 WREG32(IH_RB_CNTL, tmp);
2920         }
2921         return (wptr & rdev->ih.ptr_mask);
2922 }
2923
2924 int evergreen_irq_process(struct radeon_device *rdev)
2925 {
2926         u32 wptr;
2927         u32 rptr;
2928         u32 src_id, src_data;
2929         u32 ring_index;
2930         unsigned long flags;
2931         bool queue_hotplug = false;
2932
2933         if (!rdev->ih.enabled || rdev->shutdown)
2934                 return IRQ_NONE;
2935
2936         wptr = evergreen_get_ih_wptr(rdev);
2937         rptr = rdev->ih.rptr;
2938         DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
2939
2940         spin_lock_irqsave(&rdev->ih.lock, flags);
2941         if (rptr == wptr) {
2942                 spin_unlock_irqrestore(&rdev->ih.lock, flags);
2943                 return IRQ_NONE;
2944         }
2945 restart_ih:
2946         /* Order reading of wptr vs. reading of IH ring data */
2947         rmb();
2948
2949         /* display interrupts */
2950         evergreen_irq_ack(rdev);
2951
2952         rdev->ih.wptr = wptr;
2953         while (rptr != wptr) {
2954                 /* wptr/rptr are in bytes! */
2955                 ring_index = rptr / 4;
2956                 src_id =  le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff;
2957                 src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff;
2958
2959                 switch (src_id) {
2960                 case 1: /* D1 vblank/vline */
2961                         switch (src_data) {
2962                         case 0: /* D1 vblank */
2963                                 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT) {
2964                                         if (rdev->irq.crtc_vblank_int[0]) {
2965                                                 drm_handle_vblank(rdev->ddev, 0);
2966                                                 rdev->pm.vblank_sync = true;
2967                                                 wake_up(&rdev->irq.vblank_queue);
2968                                         }
2969                                         if (rdev->irq.pflip[0])
2970                                                 radeon_crtc_handle_flip(rdev, 0);
2971                                         rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VBLANK_INTERRUPT;
2972                                         DRM_DEBUG("IH: D1 vblank\n");
2973                                 }
2974                                 break;
2975                         case 1: /* D1 vline */
2976                                 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT) {
2977                                         rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VLINE_INTERRUPT;
2978                                         DRM_DEBUG("IH: D1 vline\n");
2979                                 }
2980                                 break;
2981                         default:
2982                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2983                                 break;
2984                         }
2985                         break;
2986                 case 2: /* D2 vblank/vline */
2987                         switch (src_data) {
2988                         case 0: /* D2 vblank */
2989                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT) {
2990                                         if (rdev->irq.crtc_vblank_int[1]) {
2991                                                 drm_handle_vblank(rdev->ddev, 1);
2992                                                 rdev->pm.vblank_sync = true;
2993                                                 wake_up(&rdev->irq.vblank_queue);
2994                                         }
2995                                         if (rdev->irq.pflip[1])
2996                                                 radeon_crtc_handle_flip(rdev, 1);
2997                                         rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VBLANK_INTERRUPT;
2998                                         DRM_DEBUG("IH: D2 vblank\n");
2999                                 }
3000                                 break;
3001                         case 1: /* D2 vline */
3002                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT) {
3003                                         rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VLINE_INTERRUPT;
3004                                         DRM_DEBUG("IH: D2 vline\n");
3005                                 }
3006                                 break;
3007                         default:
3008                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3009                                 break;
3010                         }
3011                         break;
3012                 case 3: /* D3 vblank/vline */
3013                         switch (src_data) {
3014                         case 0: /* D3 vblank */
3015                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT) {
3016                                         if (rdev->irq.crtc_vblank_int[2]) {
3017                                                 drm_handle_vblank(rdev->ddev, 2);
3018                                                 rdev->pm.vblank_sync = true;
3019                                                 wake_up(&rdev->irq.vblank_queue);
3020                                         }
3021                                         if (rdev->irq.pflip[2])
3022                                                 radeon_crtc_handle_flip(rdev, 2);
3023                                         rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VBLANK_INTERRUPT;
3024                                         DRM_DEBUG("IH: D3 vblank\n");
3025                                 }
3026                                 break;
3027                         case 1: /* D3 vline */
3028                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT) {
3029                                         rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VLINE_INTERRUPT;
3030                                         DRM_DEBUG("IH: D3 vline\n");
3031                                 }
3032                                 break;
3033                         default:
3034                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3035                                 break;
3036                         }
3037                         break;
3038                 case 4: /* D4 vblank/vline */
3039                         switch (src_data) {
3040                         case 0: /* D4 vblank */
3041                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT) {
3042                                         if (rdev->irq.crtc_vblank_int[3]) {
3043                                                 drm_handle_vblank(rdev->ddev, 3);
3044                                                 rdev->pm.vblank_sync = true;
3045                                                 wake_up(&rdev->irq.vblank_queue);
3046                                         }
3047                                         if (rdev->irq.pflip[3])
3048                                                 radeon_crtc_handle_flip(rdev, 3);
3049                                         rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VBLANK_INTERRUPT;
3050                                         DRM_DEBUG("IH: D4 vblank\n");
3051                                 }
3052                                 break;
3053                         case 1: /* D4 vline */
3054                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT) {
3055                                         rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VLINE_INTERRUPT;
3056                                         DRM_DEBUG("IH: D4 vline\n");
3057                                 }
3058                                 break;
3059                         default:
3060                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3061                                 break;
3062                         }
3063                         break;
3064                 case 5: /* D5 vblank/vline */
3065                         switch (src_data) {
3066                         case 0: /* D5 vblank */
3067                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT) {
3068                                         if (rdev->irq.crtc_vblank_int[4]) {
3069                                                 drm_handle_vblank(rdev->ddev, 4);
3070                                                 rdev->pm.vblank_sync = true;
3071                                                 wake_up(&rdev->irq.vblank_queue);
3072                                         }
3073                                         if (rdev->irq.pflip[4])
3074                                                 radeon_crtc_handle_flip(rdev, 4);
3075                                         rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VBLANK_INTERRUPT;
3076                                         DRM_DEBUG("IH: D5 vblank\n");
3077                                 }
3078                                 break;
3079                         case 1: /* D5 vline */
3080                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT) {
3081                                         rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VLINE_INTERRUPT;
3082                                         DRM_DEBUG("IH: D5 vline\n");
3083                                 }
3084                                 break;
3085                         default:
3086                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3087                                 break;
3088                         }
3089                         break;
3090                 case 6: /* D6 vblank/vline */
3091                         switch (src_data) {
3092                         case 0: /* D6 vblank */
3093                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT) {
3094                                         if (rdev->irq.crtc_vblank_int[5]) {
3095                                                 drm_handle_vblank(rdev->ddev, 5);
3096                                                 rdev->pm.vblank_sync = true;
3097                                                 wake_up(&rdev->irq.vblank_queue);
3098                                         }
3099                                         if (rdev->irq.pflip[5])
3100                                                 radeon_crtc_handle_flip(rdev, 5);
3101                                         rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VBLANK_INTERRUPT;
3102                                         DRM_DEBUG("IH: D6 vblank\n");
3103                                 }
3104                                 break;
3105                         case 1: /* D6 vline */
3106                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT) {
3107                                         rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VLINE_INTERRUPT;
3108                                         DRM_DEBUG("IH: D6 vline\n");
3109                                 }
3110                                 break;
3111                         default:
3112                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3113                                 break;
3114                         }
3115                         break;
3116                 case 42: /* HPD hotplug */
3117                         switch (src_data) {
3118                         case 0:
3119                                 if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) {
3120                                         rdev->irq.stat_regs.evergreen.disp_int &= ~DC_HPD1_INTERRUPT;
3121                                         queue_hotplug = true;
3122                                         DRM_DEBUG("IH: HPD1\n");
3123                                 }
3124                                 break;
3125                         case 1:
3126                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) {
3127                                         rdev->irq.stat_regs.evergreen.disp_int_cont &= ~DC_HPD2_INTERRUPT;
3128                                         queue_hotplug = true;
3129                                         DRM_DEBUG("IH: HPD2\n");
3130                                 }
3131                                 break;
3132                         case 2:
3133                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) {
3134                                         rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~DC_HPD3_INTERRUPT;
3135                                         queue_hotplug = true;
3136                                         DRM_DEBUG("IH: HPD3\n");
3137                                 }
3138                                 break;
3139                         case 3:
3140                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) {
3141                                         rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~DC_HPD4_INTERRUPT;
3142                                         queue_hotplug = true;
3143                                         DRM_DEBUG("IH: HPD4\n");
3144                                 }
3145                                 break;
3146                         case 4:
3147                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) {
3148                                         rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~DC_HPD5_INTERRUPT;
3149                                         queue_hotplug = true;
3150                                         DRM_DEBUG("IH: HPD5\n");
3151                                 }
3152                                 break;
3153                         case 5:
3154                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) {
3155                                         rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~DC_HPD6_INTERRUPT;
3156                                         queue_hotplug = true;
3157                                         DRM_DEBUG("IH: HPD6\n");
3158                                 }
3159                                 break;
3160                         default:
3161                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3162                                 break;
3163                         }
3164                         break;
3165                 case 176: /* CP_INT in ring buffer */
3166                 case 177: /* CP_INT in IB1 */
3167                 case 178: /* CP_INT in IB2 */
3168                         DRM_DEBUG("IH: CP int: 0x%08x\n", src_data);
3169                         radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
3170                         break;
3171                 case 181: /* CP EOP event */
3172                         DRM_DEBUG("IH: CP EOP\n");
3173                         if (rdev->family >= CHIP_CAYMAN) {
3174                                 switch (src_data) {
3175                                 case 0:
3176                                         radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
3177                                         break;
3178                                 case 1:
3179                                         radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP1_INDEX);
3180                                         break;
3181                                 case 2:
3182                                         radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP2_INDEX);
3183                                         break;
3184                                 }
3185                         } else
3186                                 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
3187                         break;
3188                 case 233: /* GUI IDLE */
3189                         DRM_DEBUG("IH: GUI idle\n");
3190                         rdev->pm.gui_idle = true;
3191                         wake_up(&rdev->irq.idle_queue);
3192                         break;
3193                 default:
3194                         DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3195                         break;
3196                 }
3197
3198                 /* wptr/rptr are in bytes! */
3199                 rptr += 16;
3200                 rptr &= rdev->ih.ptr_mask;
3201         }
3202         /* make sure wptr hasn't changed while processing */
3203         wptr = evergreen_get_ih_wptr(rdev);
3204         if (wptr != rdev->ih.wptr)
3205                 goto restart_ih;
3206         if (queue_hotplug)
3207                 schedule_work(&rdev->hotplug_work);
3208         rdev->ih.rptr = rptr;
3209         WREG32(IH_RB_RPTR, rdev->ih.rptr);
3210         spin_unlock_irqrestore(&rdev->ih.lock, flags);
3211         return IRQ_HANDLED;
3212 }
3213
3214 static int evergreen_startup(struct radeon_device *rdev)
3215 {
3216         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
3217         int r;
3218
3219         /* enable pcie gen2 link */
3220         evergreen_pcie_gen2_enable(rdev);
3221
3222         evergreen_mc_program(rdev);
3223
3224         if (ASIC_IS_DCE5(rdev)) {
3225                 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw || !rdev->mc_fw) {
3226                         r = ni_init_microcode(rdev);
3227                         if (r) {
3228                                 DRM_ERROR("Failed to load firmware!\n");
3229                                 return r;
3230                         }
3231                 }
3232                 r = ni_mc_load_microcode(rdev);
3233                 if (r) {
3234                         DRM_ERROR("Failed to load MC firmware!\n");
3235                         return r;
3236                 }
3237         } else {
3238                 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
3239                         r = r600_init_microcode(rdev);
3240                         if (r) {
3241                                 DRM_ERROR("Failed to load firmware!\n");
3242                                 return r;
3243                         }
3244                 }
3245         }
3246
3247         r = r600_vram_scratch_init(rdev);
3248         if (r)
3249                 return r;
3250
3251         if (rdev->flags & RADEON_IS_AGP) {
3252                 evergreen_agp_enable(rdev);
3253         } else {
3254                 r = evergreen_pcie_gart_enable(rdev);
3255                 if (r)
3256                         return r;
3257         }
3258         evergreen_gpu_init(rdev);
3259
3260         r = evergreen_blit_init(rdev);
3261         if (r) {
3262                 r600_blit_fini(rdev);
3263                 rdev->asic->copy.copy = NULL;
3264                 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
3265         }
3266
3267         /* allocate wb buffer */
3268         r = radeon_wb_init(rdev);
3269         if (r)
3270                 return r;
3271
3272         r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
3273         if (r) {
3274                 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
3275                 return r;
3276         }
3277
3278         /* Enable IRQ */
3279         if (!rdev->irq.installed) {
3280                 r = radeon_irq_kms_init(rdev);
3281                 if (r)
3282                         return r;
3283         }
3284
3285         r = r600_irq_init(rdev);
3286         if (r) {
3287                 DRM_ERROR("radeon: IH init failed (%d).\n", r);
3288                 radeon_irq_kms_fini(rdev);
3289                 return r;
3290         }
3291         evergreen_irq_set(rdev);
3292
3293         r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
3294                              R600_CP_RB_RPTR, R600_CP_RB_WPTR,
3295                              0, 0xfffff, RADEON_CP_PACKET2);
3296         if (r)
3297                 return r;
3298         r = evergreen_cp_load_microcode(rdev);
3299         if (r)
3300                 return r;
3301         r = evergreen_cp_resume(rdev);
3302         if (r)
3303                 return r;
3304
3305         r = radeon_ib_pool_start(rdev);
3306         if (r)
3307                 return r;
3308
3309         r = radeon_ib_test(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
3310         if (r) {
3311                 DRM_ERROR("radeon: failed testing IB (%d).\n", r);
3312                 rdev->accel_working = false;
3313                 return r;
3314         }
3315
3316         r = r600_audio_init(rdev);
3317         if (r) {
3318                 DRM_ERROR("radeon: audio init failed\n");
3319                 return r;
3320         }
3321
3322         return 0;
3323 }
3324
3325 int evergreen_resume(struct radeon_device *rdev)
3326 {
3327         int r;
3328
3329         /* reset the asic, the gfx blocks are often in a bad state
3330          * after the driver is unloaded or after a resume
3331          */
3332         if (radeon_asic_reset(rdev))
3333                 dev_warn(rdev->dev, "GPU reset failed !\n");
3334         /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
3335          * posting will perform necessary task to bring back GPU into good
3336          * shape.
3337          */
3338         /* post card */
3339         atom_asic_init(rdev->mode_info.atom_context);
3340
3341         rdev->accel_working = true;
3342         r = evergreen_startup(rdev);
3343         if (r) {
3344                 DRM_ERROR("evergreen startup failed on resume\n");
3345                 rdev->accel_working = false;
3346                 return r;
3347         }
3348
3349         return r;
3350
3351 }
3352
3353 int evergreen_suspend(struct radeon_device *rdev)
3354 {
3355         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
3356
3357         r600_audio_fini(rdev);
3358         /* FIXME: we should wait for ring to be empty */
3359         radeon_ib_pool_suspend(rdev);
3360         r600_blit_suspend(rdev);
3361         r700_cp_stop(rdev);
3362         ring->ready = false;
3363         evergreen_irq_suspend(rdev);
3364         radeon_wb_disable(rdev);
3365         evergreen_pcie_gart_disable(rdev);
3366
3367         return 0;
3368 }
3369
3370 /* Plan is to move initialization in that function and use
3371  * helper function so that radeon_device_init pretty much
3372  * do nothing more than calling asic specific function. This
3373  * should also allow to remove a bunch of callback function
3374  * like vram_info.
3375  */
3376 int evergreen_init(struct radeon_device *rdev)
3377 {
3378         int r;
3379
3380         /* This don't do much */
3381         r = radeon_gem_init(rdev);
3382         if (r)
3383                 return r;
3384         /* Read BIOS */
3385         if (!radeon_get_bios(rdev)) {
3386                 if (ASIC_IS_AVIVO(rdev))
3387                         return -EINVAL;
3388         }
3389         /* Must be an ATOMBIOS */
3390         if (!rdev->is_atom_bios) {
3391                 dev_err(rdev->dev, "Expecting atombios for evergreen GPU\n");
3392                 return -EINVAL;
3393         }
3394         r = radeon_atombios_init(rdev);
3395         if (r)
3396                 return r;
3397         /* reset the asic, the gfx blocks are often in a bad state
3398          * after the driver is unloaded or after a resume
3399          */
3400         if (radeon_asic_reset(rdev))
3401                 dev_warn(rdev->dev, "GPU reset failed !\n");
3402         /* Post card if necessary */
3403         if (!radeon_card_posted(rdev)) {
3404                 if (!rdev->bios) {
3405                         dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
3406                         return -EINVAL;
3407                 }
3408                 DRM_INFO("GPU not posted. posting now...\n");
3409                 atom_asic_init(rdev->mode_info.atom_context);
3410         }
3411         /* Initialize scratch registers */
3412         r600_scratch_init(rdev);
3413         /* Initialize surface registers */
3414         radeon_surface_init(rdev);
3415         /* Initialize clocks */
3416         radeon_get_clock_info(rdev->ddev);
3417         /* Fence driver */
3418         r = radeon_fence_driver_init(rdev);
3419         if (r)
3420                 return r;
3421         /* initialize AGP */
3422         if (rdev->flags & RADEON_IS_AGP) {
3423                 r = radeon_agp_init(rdev);
3424                 if (r)
3425                         radeon_agp_disable(rdev);
3426         }
3427         /* initialize memory controller */
3428         r = evergreen_mc_init(rdev);
3429         if (r)
3430                 return r;
3431         /* Memory manager */
3432         r = radeon_bo_init(rdev);
3433         if (r)
3434                 return r;
3435
3436         rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL;
3437         r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024);
3438
3439         rdev->ih.ring_obj = NULL;
3440         r600_ih_ring_init(rdev, 64 * 1024);
3441
3442         r = r600_pcie_gart_init(rdev);
3443         if (r)
3444                 return r;
3445
3446         r = radeon_ib_pool_init(rdev);
3447         rdev->accel_working = true;
3448         if (r) {
3449                 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
3450                 rdev->accel_working = false;
3451         }
3452
3453         r = evergreen_startup(rdev);
3454         if (r) {
3455                 dev_err(rdev->dev, "disabling GPU acceleration\n");
3456                 r700_cp_fini(rdev);
3457                 r600_irq_fini(rdev);
3458                 radeon_wb_fini(rdev);
3459                 r100_ib_fini(rdev);
3460                 radeon_irq_kms_fini(rdev);
3461                 evergreen_pcie_gart_fini(rdev);
3462                 rdev->accel_working = false;
3463         }
3464
3465         /* Don't start up if the MC ucode is missing on BTC parts.
3466          * The default clocks and voltages before the MC ucode
3467          * is loaded are not suffient for advanced operations.
3468          */
3469         if (ASIC_IS_DCE5(rdev)) {
3470                 if (!rdev->mc_fw && !(rdev->flags & RADEON_IS_IGP)) {
3471                         DRM_ERROR("radeon: MC ucode required for NI+.\n");
3472                         return -EINVAL;
3473                 }
3474         }
3475
3476         return 0;
3477 }
3478
3479 void evergreen_fini(struct radeon_device *rdev)
3480 {
3481         r600_audio_fini(rdev);
3482         r600_blit_fini(rdev);
3483         r700_cp_fini(rdev);
3484         r600_irq_fini(rdev);
3485         radeon_wb_fini(rdev);
3486         r100_ib_fini(rdev);
3487         radeon_irq_kms_fini(rdev);
3488         evergreen_pcie_gart_fini(rdev);
3489         r600_vram_scratch_fini(rdev);
3490         radeon_gem_fini(rdev);
3491         radeon_semaphore_driver_fini(rdev);
3492         radeon_fence_driver_fini(rdev);
3493         radeon_agp_fini(rdev);
3494         radeon_bo_fini(rdev);
3495         radeon_atombios_fini(rdev);
3496         kfree(rdev->bios);
3497         rdev->bios = NULL;
3498 }
3499
3500 void evergreen_pcie_gen2_enable(struct radeon_device *rdev)
3501 {
3502         u32 link_width_cntl, speed_cntl;
3503
3504         if (radeon_pcie_gen2 == 0)
3505                 return;
3506
3507         if (rdev->flags & RADEON_IS_IGP)
3508                 return;
3509
3510         if (!(rdev->flags & RADEON_IS_PCIE))
3511                 return;
3512
3513         /* x2 cards have a special sequence */
3514         if (ASIC_IS_X2(rdev))
3515                 return;
3516
3517         speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3518         if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) ||
3519             (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
3520
3521                 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
3522                 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
3523                 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3524
3525                 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3526                 speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN;
3527                 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3528
3529                 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3530                 speed_cntl |= LC_CLR_FAILED_SPD_CHANGE_CNT;
3531                 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3532
3533                 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3534                 speed_cntl &= ~LC_CLR_FAILED_SPD_CHANGE_CNT;
3535                 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3536
3537                 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3538                 speed_cntl |= LC_GEN2_EN_STRAP;
3539                 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3540
3541         } else {
3542                 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
3543                 /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */
3544                 if (1)
3545                         link_width_cntl |= LC_UPCONFIGURE_DIS;
3546                 else
3547                         link_width_cntl &= ~LC_UPCONFIGURE_DIS;
3548                 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3549         }
3550 }