2 * Copyright 2012 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
22 * Authors: Alex Deucher
25 #include <linux/firmware.h>
26 #include <linux/module.h>
27 #include <linux/pci.h>
28 #include <linux/slab.h>
30 #include <drm/drm_vblank.h>
33 #include "evergreen.h"
34 #include "cik_blit_shaders.h"
37 #include "clearstate_ci.h"
40 #include "radeon_asic.h"
41 #include "radeon_audio.h"
42 #include "radeon_ucode.h"
46 #define SH_MEM_CONFIG_GFX_DEFAULT \
47 ALIGNMENT_MODE(SH_MEM_ALIGNMENT_MODE_UNALIGNED)
49 MODULE_FIRMWARE("radeon/BONAIRE_pfp.bin");
50 MODULE_FIRMWARE("radeon/BONAIRE_me.bin");
51 MODULE_FIRMWARE("radeon/BONAIRE_ce.bin");
52 MODULE_FIRMWARE("radeon/BONAIRE_mec.bin");
53 MODULE_FIRMWARE("radeon/BONAIRE_mc.bin");
54 MODULE_FIRMWARE("radeon/BONAIRE_mc2.bin");
55 MODULE_FIRMWARE("radeon/BONAIRE_rlc.bin");
56 MODULE_FIRMWARE("radeon/BONAIRE_sdma.bin");
57 MODULE_FIRMWARE("radeon/BONAIRE_smc.bin");
59 MODULE_FIRMWARE("radeon/bonaire_pfp.bin");
60 MODULE_FIRMWARE("radeon/bonaire_me.bin");
61 MODULE_FIRMWARE("radeon/bonaire_ce.bin");
62 MODULE_FIRMWARE("radeon/bonaire_mec.bin");
63 MODULE_FIRMWARE("radeon/bonaire_mc.bin");
64 MODULE_FIRMWARE("radeon/bonaire_rlc.bin");
65 MODULE_FIRMWARE("radeon/bonaire_sdma.bin");
66 MODULE_FIRMWARE("radeon/bonaire_smc.bin");
67 MODULE_FIRMWARE("radeon/bonaire_k_smc.bin");
69 MODULE_FIRMWARE("radeon/HAWAII_pfp.bin");
70 MODULE_FIRMWARE("radeon/HAWAII_me.bin");
71 MODULE_FIRMWARE("radeon/HAWAII_ce.bin");
72 MODULE_FIRMWARE("radeon/HAWAII_mec.bin");
73 MODULE_FIRMWARE("radeon/HAWAII_mc.bin");
74 MODULE_FIRMWARE("radeon/HAWAII_mc2.bin");
75 MODULE_FIRMWARE("radeon/HAWAII_rlc.bin");
76 MODULE_FIRMWARE("radeon/HAWAII_sdma.bin");
77 MODULE_FIRMWARE("radeon/HAWAII_smc.bin");
79 MODULE_FIRMWARE("radeon/hawaii_pfp.bin");
80 MODULE_FIRMWARE("radeon/hawaii_me.bin");
81 MODULE_FIRMWARE("radeon/hawaii_ce.bin");
82 MODULE_FIRMWARE("radeon/hawaii_mec.bin");
83 MODULE_FIRMWARE("radeon/hawaii_mc.bin");
84 MODULE_FIRMWARE("radeon/hawaii_rlc.bin");
85 MODULE_FIRMWARE("radeon/hawaii_sdma.bin");
86 MODULE_FIRMWARE("radeon/hawaii_smc.bin");
87 MODULE_FIRMWARE("radeon/hawaii_k_smc.bin");
89 MODULE_FIRMWARE("radeon/KAVERI_pfp.bin");
90 MODULE_FIRMWARE("radeon/KAVERI_me.bin");
91 MODULE_FIRMWARE("radeon/KAVERI_ce.bin");
92 MODULE_FIRMWARE("radeon/KAVERI_mec.bin");
93 MODULE_FIRMWARE("radeon/KAVERI_rlc.bin");
94 MODULE_FIRMWARE("radeon/KAVERI_sdma.bin");
96 MODULE_FIRMWARE("radeon/kaveri_pfp.bin");
97 MODULE_FIRMWARE("radeon/kaveri_me.bin");
98 MODULE_FIRMWARE("radeon/kaveri_ce.bin");
99 MODULE_FIRMWARE("radeon/kaveri_mec.bin");
100 MODULE_FIRMWARE("radeon/kaveri_mec2.bin");
101 MODULE_FIRMWARE("radeon/kaveri_rlc.bin");
102 MODULE_FIRMWARE("radeon/kaveri_sdma.bin");
104 MODULE_FIRMWARE("radeon/KABINI_pfp.bin");
105 MODULE_FIRMWARE("radeon/KABINI_me.bin");
106 MODULE_FIRMWARE("radeon/KABINI_ce.bin");
107 MODULE_FIRMWARE("radeon/KABINI_mec.bin");
108 MODULE_FIRMWARE("radeon/KABINI_rlc.bin");
109 MODULE_FIRMWARE("radeon/KABINI_sdma.bin");
111 MODULE_FIRMWARE("radeon/kabini_pfp.bin");
112 MODULE_FIRMWARE("radeon/kabini_me.bin");
113 MODULE_FIRMWARE("radeon/kabini_ce.bin");
114 MODULE_FIRMWARE("radeon/kabini_mec.bin");
115 MODULE_FIRMWARE("radeon/kabini_rlc.bin");
116 MODULE_FIRMWARE("radeon/kabini_sdma.bin");
118 MODULE_FIRMWARE("radeon/MULLINS_pfp.bin");
119 MODULE_FIRMWARE("radeon/MULLINS_me.bin");
120 MODULE_FIRMWARE("radeon/MULLINS_ce.bin");
121 MODULE_FIRMWARE("radeon/MULLINS_mec.bin");
122 MODULE_FIRMWARE("radeon/MULLINS_rlc.bin");
123 MODULE_FIRMWARE("radeon/MULLINS_sdma.bin");
125 MODULE_FIRMWARE("radeon/mullins_pfp.bin");
126 MODULE_FIRMWARE("radeon/mullins_me.bin");
127 MODULE_FIRMWARE("radeon/mullins_ce.bin");
128 MODULE_FIRMWARE("radeon/mullins_mec.bin");
129 MODULE_FIRMWARE("radeon/mullins_rlc.bin");
130 MODULE_FIRMWARE("radeon/mullins_sdma.bin");
132 static u32 cik_get_cu_active_bitmap(struct radeon_device *rdev, u32 se, u32 sh);
133 static void cik_rlc_stop(struct radeon_device *rdev);
134 static void cik_pcie_gen3_enable(struct radeon_device *rdev);
135 static void cik_program_aspm(struct radeon_device *rdev);
136 static void cik_init_pg(struct radeon_device *rdev);
137 static void cik_init_cg(struct radeon_device *rdev);
138 static void cik_fini_pg(struct radeon_device *rdev);
139 static void cik_fini_cg(struct radeon_device *rdev);
140 static void cik_enable_gui_idle_interrupt(struct radeon_device *rdev,
144 * cik_get_allowed_info_register - fetch the register for the info ioctl
146 * @rdev: radeon_device pointer
147 * @reg: register offset in bytes
148 * @val: register value
150 * Returns 0 for success or -EINVAL for an invalid register
153 int cik_get_allowed_info_register(struct radeon_device *rdev,
159 case GRBM_STATUS_SE0:
160 case GRBM_STATUS_SE1:
161 case GRBM_STATUS_SE2:
162 case GRBM_STATUS_SE3:
165 case (SDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET):
166 case (SDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET):
177 * Indirect registers accessor
179 u32 cik_didt_rreg(struct radeon_device *rdev, u32 reg)
184 spin_lock_irqsave(&rdev->didt_idx_lock, flags);
185 WREG32(CIK_DIDT_IND_INDEX, (reg));
186 r = RREG32(CIK_DIDT_IND_DATA);
187 spin_unlock_irqrestore(&rdev->didt_idx_lock, flags);
191 void cik_didt_wreg(struct radeon_device *rdev, u32 reg, u32 v)
195 spin_lock_irqsave(&rdev->didt_idx_lock, flags);
196 WREG32(CIK_DIDT_IND_INDEX, (reg));
197 WREG32(CIK_DIDT_IND_DATA, (v));
198 spin_unlock_irqrestore(&rdev->didt_idx_lock, flags);
201 /* get temperature in millidegrees */
202 int ci_get_temp(struct radeon_device *rdev)
207 temp = (RREG32_SMC(CG_MULT_THERMAL_STATUS) & CTF_TEMP_MASK) >>
213 actual_temp = temp & 0x1ff;
215 return actual_temp * 1000;
218 /* get temperature in millidegrees */
219 int kv_get_temp(struct radeon_device *rdev)
224 temp = RREG32_SMC(0xC0300E0C);
227 actual_temp = (temp / 8) - 49;
231 return actual_temp * 1000;
235 * Indirect registers accessor
237 u32 cik_pciep_rreg(struct radeon_device *rdev, u32 reg)
242 spin_lock_irqsave(&rdev->pciep_idx_lock, flags);
243 WREG32(PCIE_INDEX, reg);
244 (void)RREG32(PCIE_INDEX);
245 r = RREG32(PCIE_DATA);
246 spin_unlock_irqrestore(&rdev->pciep_idx_lock, flags);
250 void cik_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v)
254 spin_lock_irqsave(&rdev->pciep_idx_lock, flags);
255 WREG32(PCIE_INDEX, reg);
256 (void)RREG32(PCIE_INDEX);
257 WREG32(PCIE_DATA, v);
258 (void)RREG32(PCIE_DATA);
259 spin_unlock_irqrestore(&rdev->pciep_idx_lock, flags);
262 static const u32 spectre_rlc_save_restore_register_list[] =
264 (0x0e00 << 16) | (0xc12c >> 2),
266 (0x0e00 << 16) | (0xc140 >> 2),
268 (0x0e00 << 16) | (0xc150 >> 2),
270 (0x0e00 << 16) | (0xc15c >> 2),
272 (0x0e00 << 16) | (0xc168 >> 2),
274 (0x0e00 << 16) | (0xc170 >> 2),
276 (0x0e00 << 16) | (0xc178 >> 2),
278 (0x0e00 << 16) | (0xc204 >> 2),
280 (0x0e00 << 16) | (0xc2b4 >> 2),
282 (0x0e00 << 16) | (0xc2b8 >> 2),
284 (0x0e00 << 16) | (0xc2bc >> 2),
286 (0x0e00 << 16) | (0xc2c0 >> 2),
288 (0x0e00 << 16) | (0x8228 >> 2),
290 (0x0e00 << 16) | (0x829c >> 2),
292 (0x0e00 << 16) | (0x869c >> 2),
294 (0x0600 << 16) | (0x98f4 >> 2),
296 (0x0e00 << 16) | (0x98f8 >> 2),
298 (0x0e00 << 16) | (0x9900 >> 2),
300 (0x0e00 << 16) | (0xc260 >> 2),
302 (0x0e00 << 16) | (0x90e8 >> 2),
304 (0x0e00 << 16) | (0x3c000 >> 2),
306 (0x0e00 << 16) | (0x3c00c >> 2),
308 (0x0e00 << 16) | (0x8c1c >> 2),
310 (0x0e00 << 16) | (0x9700 >> 2),
312 (0x0e00 << 16) | (0xcd20 >> 2),
314 (0x4e00 << 16) | (0xcd20 >> 2),
316 (0x5e00 << 16) | (0xcd20 >> 2),
318 (0x6e00 << 16) | (0xcd20 >> 2),
320 (0x7e00 << 16) | (0xcd20 >> 2),
322 (0x8e00 << 16) | (0xcd20 >> 2),
324 (0x9e00 << 16) | (0xcd20 >> 2),
326 (0xae00 << 16) | (0xcd20 >> 2),
328 (0xbe00 << 16) | (0xcd20 >> 2),
330 (0x0e00 << 16) | (0x89bc >> 2),
332 (0x0e00 << 16) | (0x8900 >> 2),
335 (0x0e00 << 16) | (0xc130 >> 2),
337 (0x0e00 << 16) | (0xc134 >> 2),
339 (0x0e00 << 16) | (0xc1fc >> 2),
341 (0x0e00 << 16) | (0xc208 >> 2),
343 (0x0e00 << 16) | (0xc264 >> 2),
345 (0x0e00 << 16) | (0xc268 >> 2),
347 (0x0e00 << 16) | (0xc26c >> 2),
349 (0x0e00 << 16) | (0xc270 >> 2),
351 (0x0e00 << 16) | (0xc274 >> 2),
353 (0x0e00 << 16) | (0xc278 >> 2),
355 (0x0e00 << 16) | (0xc27c >> 2),
357 (0x0e00 << 16) | (0xc280 >> 2),
359 (0x0e00 << 16) | (0xc284 >> 2),
361 (0x0e00 << 16) | (0xc288 >> 2),
363 (0x0e00 << 16) | (0xc28c >> 2),
365 (0x0e00 << 16) | (0xc290 >> 2),
367 (0x0e00 << 16) | (0xc294 >> 2),
369 (0x0e00 << 16) | (0xc298 >> 2),
371 (0x0e00 << 16) | (0xc29c >> 2),
373 (0x0e00 << 16) | (0xc2a0 >> 2),
375 (0x0e00 << 16) | (0xc2a4 >> 2),
377 (0x0e00 << 16) | (0xc2a8 >> 2),
379 (0x0e00 << 16) | (0xc2ac >> 2),
381 (0x0e00 << 16) | (0xc2b0 >> 2),
383 (0x0e00 << 16) | (0x301d0 >> 2),
385 (0x0e00 << 16) | (0x30238 >> 2),
387 (0x0e00 << 16) | (0x30250 >> 2),
389 (0x0e00 << 16) | (0x30254 >> 2),
391 (0x0e00 << 16) | (0x30258 >> 2),
393 (0x0e00 << 16) | (0x3025c >> 2),
395 (0x4e00 << 16) | (0xc900 >> 2),
397 (0x5e00 << 16) | (0xc900 >> 2),
399 (0x6e00 << 16) | (0xc900 >> 2),
401 (0x7e00 << 16) | (0xc900 >> 2),
403 (0x8e00 << 16) | (0xc900 >> 2),
405 (0x9e00 << 16) | (0xc900 >> 2),
407 (0xae00 << 16) | (0xc900 >> 2),
409 (0xbe00 << 16) | (0xc900 >> 2),
411 (0x4e00 << 16) | (0xc904 >> 2),
413 (0x5e00 << 16) | (0xc904 >> 2),
415 (0x6e00 << 16) | (0xc904 >> 2),
417 (0x7e00 << 16) | (0xc904 >> 2),
419 (0x8e00 << 16) | (0xc904 >> 2),
421 (0x9e00 << 16) | (0xc904 >> 2),
423 (0xae00 << 16) | (0xc904 >> 2),
425 (0xbe00 << 16) | (0xc904 >> 2),
427 (0x4e00 << 16) | (0xc908 >> 2),
429 (0x5e00 << 16) | (0xc908 >> 2),
431 (0x6e00 << 16) | (0xc908 >> 2),
433 (0x7e00 << 16) | (0xc908 >> 2),
435 (0x8e00 << 16) | (0xc908 >> 2),
437 (0x9e00 << 16) | (0xc908 >> 2),
439 (0xae00 << 16) | (0xc908 >> 2),
441 (0xbe00 << 16) | (0xc908 >> 2),
443 (0x4e00 << 16) | (0xc90c >> 2),
445 (0x5e00 << 16) | (0xc90c >> 2),
447 (0x6e00 << 16) | (0xc90c >> 2),
449 (0x7e00 << 16) | (0xc90c >> 2),
451 (0x8e00 << 16) | (0xc90c >> 2),
453 (0x9e00 << 16) | (0xc90c >> 2),
455 (0xae00 << 16) | (0xc90c >> 2),
457 (0xbe00 << 16) | (0xc90c >> 2),
459 (0x4e00 << 16) | (0xc910 >> 2),
461 (0x5e00 << 16) | (0xc910 >> 2),
463 (0x6e00 << 16) | (0xc910 >> 2),
465 (0x7e00 << 16) | (0xc910 >> 2),
467 (0x8e00 << 16) | (0xc910 >> 2),
469 (0x9e00 << 16) | (0xc910 >> 2),
471 (0xae00 << 16) | (0xc910 >> 2),
473 (0xbe00 << 16) | (0xc910 >> 2),
475 (0x0e00 << 16) | (0xc99c >> 2),
477 (0x0e00 << 16) | (0x9834 >> 2),
479 (0x0000 << 16) | (0x30f00 >> 2),
481 (0x0001 << 16) | (0x30f00 >> 2),
483 (0x0000 << 16) | (0x30f04 >> 2),
485 (0x0001 << 16) | (0x30f04 >> 2),
487 (0x0000 << 16) | (0x30f08 >> 2),
489 (0x0001 << 16) | (0x30f08 >> 2),
491 (0x0000 << 16) | (0x30f0c >> 2),
493 (0x0001 << 16) | (0x30f0c >> 2),
495 (0x0600 << 16) | (0x9b7c >> 2),
497 (0x0e00 << 16) | (0x8a14 >> 2),
499 (0x0e00 << 16) | (0x8a18 >> 2),
501 (0x0600 << 16) | (0x30a00 >> 2),
503 (0x0e00 << 16) | (0x8bf0 >> 2),
505 (0x0e00 << 16) | (0x8bcc >> 2),
507 (0x0e00 << 16) | (0x8b24 >> 2),
509 (0x0e00 << 16) | (0x30a04 >> 2),
511 (0x0600 << 16) | (0x30a10 >> 2),
513 (0x0600 << 16) | (0x30a14 >> 2),
515 (0x0600 << 16) | (0x30a18 >> 2),
517 (0x0600 << 16) | (0x30a2c >> 2),
519 (0x0e00 << 16) | (0xc700 >> 2),
521 (0x0e00 << 16) | (0xc704 >> 2),
523 (0x0e00 << 16) | (0xc708 >> 2),
525 (0x0e00 << 16) | (0xc768 >> 2),
527 (0x0400 << 16) | (0xc770 >> 2),
529 (0x0400 << 16) | (0xc774 >> 2),
531 (0x0400 << 16) | (0xc778 >> 2),
533 (0x0400 << 16) | (0xc77c >> 2),
535 (0x0400 << 16) | (0xc780 >> 2),
537 (0x0400 << 16) | (0xc784 >> 2),
539 (0x0400 << 16) | (0xc788 >> 2),
541 (0x0400 << 16) | (0xc78c >> 2),
543 (0x0400 << 16) | (0xc798 >> 2),
545 (0x0400 << 16) | (0xc79c >> 2),
547 (0x0400 << 16) | (0xc7a0 >> 2),
549 (0x0400 << 16) | (0xc7a4 >> 2),
551 (0x0400 << 16) | (0xc7a8 >> 2),
553 (0x0400 << 16) | (0xc7ac >> 2),
555 (0x0400 << 16) | (0xc7b0 >> 2),
557 (0x0400 << 16) | (0xc7b4 >> 2),
559 (0x0e00 << 16) | (0x9100 >> 2),
561 (0x0e00 << 16) | (0x3c010 >> 2),
563 (0x0e00 << 16) | (0x92a8 >> 2),
565 (0x0e00 << 16) | (0x92ac >> 2),
567 (0x0e00 << 16) | (0x92b4 >> 2),
569 (0x0e00 << 16) | (0x92b8 >> 2),
571 (0x0e00 << 16) | (0x92bc >> 2),
573 (0x0e00 << 16) | (0x92c0 >> 2),
575 (0x0e00 << 16) | (0x92c4 >> 2),
577 (0x0e00 << 16) | (0x92c8 >> 2),
579 (0x0e00 << 16) | (0x92cc >> 2),
581 (0x0e00 << 16) | (0x92d0 >> 2),
583 (0x0e00 << 16) | (0x8c00 >> 2),
585 (0x0e00 << 16) | (0x8c04 >> 2),
587 (0x0e00 << 16) | (0x8c20 >> 2),
589 (0x0e00 << 16) | (0x8c38 >> 2),
591 (0x0e00 << 16) | (0x8c3c >> 2),
593 (0x0e00 << 16) | (0xae00 >> 2),
595 (0x0e00 << 16) | (0x9604 >> 2),
597 (0x0e00 << 16) | (0xac08 >> 2),
599 (0x0e00 << 16) | (0xac0c >> 2),
601 (0x0e00 << 16) | (0xac10 >> 2),
603 (0x0e00 << 16) | (0xac14 >> 2),
605 (0x0e00 << 16) | (0xac58 >> 2),
607 (0x0e00 << 16) | (0xac68 >> 2),
609 (0x0e00 << 16) | (0xac6c >> 2),
611 (0x0e00 << 16) | (0xac70 >> 2),
613 (0x0e00 << 16) | (0xac74 >> 2),
615 (0x0e00 << 16) | (0xac78 >> 2),
617 (0x0e00 << 16) | (0xac7c >> 2),
619 (0x0e00 << 16) | (0xac80 >> 2),
621 (0x0e00 << 16) | (0xac84 >> 2),
623 (0x0e00 << 16) | (0xac88 >> 2),
625 (0x0e00 << 16) | (0xac8c >> 2),
627 (0x0e00 << 16) | (0x970c >> 2),
629 (0x0e00 << 16) | (0x9714 >> 2),
631 (0x0e00 << 16) | (0x9718 >> 2),
633 (0x0e00 << 16) | (0x971c >> 2),
635 (0x0e00 << 16) | (0x31068 >> 2),
637 (0x4e00 << 16) | (0x31068 >> 2),
639 (0x5e00 << 16) | (0x31068 >> 2),
641 (0x6e00 << 16) | (0x31068 >> 2),
643 (0x7e00 << 16) | (0x31068 >> 2),
645 (0x8e00 << 16) | (0x31068 >> 2),
647 (0x9e00 << 16) | (0x31068 >> 2),
649 (0xae00 << 16) | (0x31068 >> 2),
651 (0xbe00 << 16) | (0x31068 >> 2),
653 (0x0e00 << 16) | (0xcd10 >> 2),
655 (0x0e00 << 16) | (0xcd14 >> 2),
657 (0x0e00 << 16) | (0x88b0 >> 2),
659 (0x0e00 << 16) | (0x88b4 >> 2),
661 (0x0e00 << 16) | (0x88b8 >> 2),
663 (0x0e00 << 16) | (0x88bc >> 2),
665 (0x0400 << 16) | (0x89c0 >> 2),
667 (0x0e00 << 16) | (0x88c4 >> 2),
669 (0x0e00 << 16) | (0x88c8 >> 2),
671 (0x0e00 << 16) | (0x88d0 >> 2),
673 (0x0e00 << 16) | (0x88d4 >> 2),
675 (0x0e00 << 16) | (0x88d8 >> 2),
677 (0x0e00 << 16) | (0x8980 >> 2),
679 (0x0e00 << 16) | (0x30938 >> 2),
681 (0x0e00 << 16) | (0x3093c >> 2),
683 (0x0e00 << 16) | (0x30940 >> 2),
685 (0x0e00 << 16) | (0x89a0 >> 2),
687 (0x0e00 << 16) | (0x30900 >> 2),
689 (0x0e00 << 16) | (0x30904 >> 2),
691 (0x0e00 << 16) | (0x89b4 >> 2),
693 (0x0e00 << 16) | (0x3c210 >> 2),
695 (0x0e00 << 16) | (0x3c214 >> 2),
697 (0x0e00 << 16) | (0x3c218 >> 2),
699 (0x0e00 << 16) | (0x8904 >> 2),
702 (0x0e00 << 16) | (0x8c28 >> 2),
703 (0x0e00 << 16) | (0x8c2c >> 2),
704 (0x0e00 << 16) | (0x8c30 >> 2),
705 (0x0e00 << 16) | (0x8c34 >> 2),
706 (0x0e00 << 16) | (0x9600 >> 2),
709 static const u32 kalindi_rlc_save_restore_register_list[] =
711 (0x0e00 << 16) | (0xc12c >> 2),
713 (0x0e00 << 16) | (0xc140 >> 2),
715 (0x0e00 << 16) | (0xc150 >> 2),
717 (0x0e00 << 16) | (0xc15c >> 2),
719 (0x0e00 << 16) | (0xc168 >> 2),
721 (0x0e00 << 16) | (0xc170 >> 2),
723 (0x0e00 << 16) | (0xc204 >> 2),
725 (0x0e00 << 16) | (0xc2b4 >> 2),
727 (0x0e00 << 16) | (0xc2b8 >> 2),
729 (0x0e00 << 16) | (0xc2bc >> 2),
731 (0x0e00 << 16) | (0xc2c0 >> 2),
733 (0x0e00 << 16) | (0x8228 >> 2),
735 (0x0e00 << 16) | (0x829c >> 2),
737 (0x0e00 << 16) | (0x869c >> 2),
739 (0x0600 << 16) | (0x98f4 >> 2),
741 (0x0e00 << 16) | (0x98f8 >> 2),
743 (0x0e00 << 16) | (0x9900 >> 2),
745 (0x0e00 << 16) | (0xc260 >> 2),
747 (0x0e00 << 16) | (0x90e8 >> 2),
749 (0x0e00 << 16) | (0x3c000 >> 2),
751 (0x0e00 << 16) | (0x3c00c >> 2),
753 (0x0e00 << 16) | (0x8c1c >> 2),
755 (0x0e00 << 16) | (0x9700 >> 2),
757 (0x0e00 << 16) | (0xcd20 >> 2),
759 (0x4e00 << 16) | (0xcd20 >> 2),
761 (0x5e00 << 16) | (0xcd20 >> 2),
763 (0x6e00 << 16) | (0xcd20 >> 2),
765 (0x7e00 << 16) | (0xcd20 >> 2),
767 (0x0e00 << 16) | (0x89bc >> 2),
769 (0x0e00 << 16) | (0x8900 >> 2),
772 (0x0e00 << 16) | (0xc130 >> 2),
774 (0x0e00 << 16) | (0xc134 >> 2),
776 (0x0e00 << 16) | (0xc1fc >> 2),
778 (0x0e00 << 16) | (0xc208 >> 2),
780 (0x0e00 << 16) | (0xc264 >> 2),
782 (0x0e00 << 16) | (0xc268 >> 2),
784 (0x0e00 << 16) | (0xc26c >> 2),
786 (0x0e00 << 16) | (0xc270 >> 2),
788 (0x0e00 << 16) | (0xc274 >> 2),
790 (0x0e00 << 16) | (0xc28c >> 2),
792 (0x0e00 << 16) | (0xc290 >> 2),
794 (0x0e00 << 16) | (0xc294 >> 2),
796 (0x0e00 << 16) | (0xc298 >> 2),
798 (0x0e00 << 16) | (0xc2a0 >> 2),
800 (0x0e00 << 16) | (0xc2a4 >> 2),
802 (0x0e00 << 16) | (0xc2a8 >> 2),
804 (0x0e00 << 16) | (0xc2ac >> 2),
806 (0x0e00 << 16) | (0x301d0 >> 2),
808 (0x0e00 << 16) | (0x30238 >> 2),
810 (0x0e00 << 16) | (0x30250 >> 2),
812 (0x0e00 << 16) | (0x30254 >> 2),
814 (0x0e00 << 16) | (0x30258 >> 2),
816 (0x0e00 << 16) | (0x3025c >> 2),
818 (0x4e00 << 16) | (0xc900 >> 2),
820 (0x5e00 << 16) | (0xc900 >> 2),
822 (0x6e00 << 16) | (0xc900 >> 2),
824 (0x7e00 << 16) | (0xc900 >> 2),
826 (0x4e00 << 16) | (0xc904 >> 2),
828 (0x5e00 << 16) | (0xc904 >> 2),
830 (0x6e00 << 16) | (0xc904 >> 2),
832 (0x7e00 << 16) | (0xc904 >> 2),
834 (0x4e00 << 16) | (0xc908 >> 2),
836 (0x5e00 << 16) | (0xc908 >> 2),
838 (0x6e00 << 16) | (0xc908 >> 2),
840 (0x7e00 << 16) | (0xc908 >> 2),
842 (0x4e00 << 16) | (0xc90c >> 2),
844 (0x5e00 << 16) | (0xc90c >> 2),
846 (0x6e00 << 16) | (0xc90c >> 2),
848 (0x7e00 << 16) | (0xc90c >> 2),
850 (0x4e00 << 16) | (0xc910 >> 2),
852 (0x5e00 << 16) | (0xc910 >> 2),
854 (0x6e00 << 16) | (0xc910 >> 2),
856 (0x7e00 << 16) | (0xc910 >> 2),
858 (0x0e00 << 16) | (0xc99c >> 2),
860 (0x0e00 << 16) | (0x9834 >> 2),
862 (0x0000 << 16) | (0x30f00 >> 2),
864 (0x0000 << 16) | (0x30f04 >> 2),
866 (0x0000 << 16) | (0x30f08 >> 2),
868 (0x0000 << 16) | (0x30f0c >> 2),
870 (0x0600 << 16) | (0x9b7c >> 2),
872 (0x0e00 << 16) | (0x8a14 >> 2),
874 (0x0e00 << 16) | (0x8a18 >> 2),
876 (0x0600 << 16) | (0x30a00 >> 2),
878 (0x0e00 << 16) | (0x8bf0 >> 2),
880 (0x0e00 << 16) | (0x8bcc >> 2),
882 (0x0e00 << 16) | (0x8b24 >> 2),
884 (0x0e00 << 16) | (0x30a04 >> 2),
886 (0x0600 << 16) | (0x30a10 >> 2),
888 (0x0600 << 16) | (0x30a14 >> 2),
890 (0x0600 << 16) | (0x30a18 >> 2),
892 (0x0600 << 16) | (0x30a2c >> 2),
894 (0x0e00 << 16) | (0xc700 >> 2),
896 (0x0e00 << 16) | (0xc704 >> 2),
898 (0x0e00 << 16) | (0xc708 >> 2),
900 (0x0e00 << 16) | (0xc768 >> 2),
902 (0x0400 << 16) | (0xc770 >> 2),
904 (0x0400 << 16) | (0xc774 >> 2),
906 (0x0400 << 16) | (0xc798 >> 2),
908 (0x0400 << 16) | (0xc79c >> 2),
910 (0x0e00 << 16) | (0x9100 >> 2),
912 (0x0e00 << 16) | (0x3c010 >> 2),
914 (0x0e00 << 16) | (0x8c00 >> 2),
916 (0x0e00 << 16) | (0x8c04 >> 2),
918 (0x0e00 << 16) | (0x8c20 >> 2),
920 (0x0e00 << 16) | (0x8c38 >> 2),
922 (0x0e00 << 16) | (0x8c3c >> 2),
924 (0x0e00 << 16) | (0xae00 >> 2),
926 (0x0e00 << 16) | (0x9604 >> 2),
928 (0x0e00 << 16) | (0xac08 >> 2),
930 (0x0e00 << 16) | (0xac0c >> 2),
932 (0x0e00 << 16) | (0xac10 >> 2),
934 (0x0e00 << 16) | (0xac14 >> 2),
936 (0x0e00 << 16) | (0xac58 >> 2),
938 (0x0e00 << 16) | (0xac68 >> 2),
940 (0x0e00 << 16) | (0xac6c >> 2),
942 (0x0e00 << 16) | (0xac70 >> 2),
944 (0x0e00 << 16) | (0xac74 >> 2),
946 (0x0e00 << 16) | (0xac78 >> 2),
948 (0x0e00 << 16) | (0xac7c >> 2),
950 (0x0e00 << 16) | (0xac80 >> 2),
952 (0x0e00 << 16) | (0xac84 >> 2),
954 (0x0e00 << 16) | (0xac88 >> 2),
956 (0x0e00 << 16) | (0xac8c >> 2),
958 (0x0e00 << 16) | (0x970c >> 2),
960 (0x0e00 << 16) | (0x9714 >> 2),
962 (0x0e00 << 16) | (0x9718 >> 2),
964 (0x0e00 << 16) | (0x971c >> 2),
966 (0x0e00 << 16) | (0x31068 >> 2),
968 (0x4e00 << 16) | (0x31068 >> 2),
970 (0x5e00 << 16) | (0x31068 >> 2),
972 (0x6e00 << 16) | (0x31068 >> 2),
974 (0x7e00 << 16) | (0x31068 >> 2),
976 (0x0e00 << 16) | (0xcd10 >> 2),
978 (0x0e00 << 16) | (0xcd14 >> 2),
980 (0x0e00 << 16) | (0x88b0 >> 2),
982 (0x0e00 << 16) | (0x88b4 >> 2),
984 (0x0e00 << 16) | (0x88b8 >> 2),
986 (0x0e00 << 16) | (0x88bc >> 2),
988 (0x0400 << 16) | (0x89c0 >> 2),
990 (0x0e00 << 16) | (0x88c4 >> 2),
992 (0x0e00 << 16) | (0x88c8 >> 2),
994 (0x0e00 << 16) | (0x88d0 >> 2),
996 (0x0e00 << 16) | (0x88d4 >> 2),
998 (0x0e00 << 16) | (0x88d8 >> 2),
1000 (0x0e00 << 16) | (0x8980 >> 2),
1002 (0x0e00 << 16) | (0x30938 >> 2),
1004 (0x0e00 << 16) | (0x3093c >> 2),
1006 (0x0e00 << 16) | (0x30940 >> 2),
1008 (0x0e00 << 16) | (0x89a0 >> 2),
1010 (0x0e00 << 16) | (0x30900 >> 2),
1012 (0x0e00 << 16) | (0x30904 >> 2),
1014 (0x0e00 << 16) | (0x89b4 >> 2),
1016 (0x0e00 << 16) | (0x3e1fc >> 2),
1018 (0x0e00 << 16) | (0x3c210 >> 2),
1020 (0x0e00 << 16) | (0x3c214 >> 2),
1022 (0x0e00 << 16) | (0x3c218 >> 2),
1024 (0x0e00 << 16) | (0x8904 >> 2),
1027 (0x0e00 << 16) | (0x8c28 >> 2),
1028 (0x0e00 << 16) | (0x8c2c >> 2),
1029 (0x0e00 << 16) | (0x8c30 >> 2),
1030 (0x0e00 << 16) | (0x8c34 >> 2),
1031 (0x0e00 << 16) | (0x9600 >> 2),
1034 static const u32 bonaire_golden_spm_registers[] =
1036 0x30800, 0xe0ffffff, 0xe0000000
1039 static const u32 bonaire_golden_common_registers[] =
1041 0xc770, 0xffffffff, 0x00000800,
1042 0xc774, 0xffffffff, 0x00000800,
1043 0xc798, 0xffffffff, 0x00007fbf,
1044 0xc79c, 0xffffffff, 0x00007faf
1047 static const u32 bonaire_golden_registers[] =
1049 0x3354, 0x00000333, 0x00000333,
1050 0x3350, 0x000c0fc0, 0x00040200,
1051 0x9a10, 0x00010000, 0x00058208,
1052 0x3c000, 0xffff1fff, 0x00140000,
1053 0x3c200, 0xfdfc0fff, 0x00000100,
1054 0x3c234, 0x40000000, 0x40000200,
1055 0x9830, 0xffffffff, 0x00000000,
1056 0x9834, 0xf00fffff, 0x00000400,
1057 0x9838, 0x0002021c, 0x00020200,
1058 0xc78, 0x00000080, 0x00000000,
1059 0x5bb0, 0x000000f0, 0x00000070,
1060 0x5bc0, 0xf0311fff, 0x80300000,
1061 0x98f8, 0x73773777, 0x12010001,
1062 0x350c, 0x00810000, 0x408af000,
1063 0x7030, 0x31000111, 0x00000011,
1064 0x2f48, 0x73773777, 0x12010001,
1065 0x220c, 0x00007fb6, 0x0021a1b1,
1066 0x2210, 0x00007fb6, 0x002021b1,
1067 0x2180, 0x00007fb6, 0x00002191,
1068 0x2218, 0x00007fb6, 0x002121b1,
1069 0x221c, 0x00007fb6, 0x002021b1,
1070 0x21dc, 0x00007fb6, 0x00002191,
1071 0x21e0, 0x00007fb6, 0x00002191,
1072 0x3628, 0x0000003f, 0x0000000a,
1073 0x362c, 0x0000003f, 0x0000000a,
1074 0x2ae4, 0x00073ffe, 0x000022a2,
1075 0x240c, 0x000007ff, 0x00000000,
1076 0x8a14, 0xf000003f, 0x00000007,
1077 0x8bf0, 0x00002001, 0x00000001,
1078 0x8b24, 0xffffffff, 0x00ffffff,
1079 0x30a04, 0x0000ff0f, 0x00000000,
1080 0x28a4c, 0x07ffffff, 0x06000000,
1081 0x4d8, 0x00000fff, 0x00000100,
1082 0x3e78, 0x00000001, 0x00000002,
1083 0x9100, 0x03000000, 0x0362c688,
1084 0x8c00, 0x000000ff, 0x00000001,
1085 0xe40, 0x00001fff, 0x00001fff,
1086 0x9060, 0x0000007f, 0x00000020,
1087 0x9508, 0x00010000, 0x00010000,
1088 0xac14, 0x000003ff, 0x000000f3,
1089 0xac0c, 0xffffffff, 0x00001032
1092 static const u32 bonaire_mgcg_cgcg_init[] =
1094 0xc420, 0xffffffff, 0xfffffffc,
1095 0x30800, 0xffffffff, 0xe0000000,
1096 0x3c2a0, 0xffffffff, 0x00000100,
1097 0x3c208, 0xffffffff, 0x00000100,
1098 0x3c2c0, 0xffffffff, 0xc0000100,
1099 0x3c2c8, 0xffffffff, 0xc0000100,
1100 0x3c2c4, 0xffffffff, 0xc0000100,
1101 0x55e4, 0xffffffff, 0x00600100,
1102 0x3c280, 0xffffffff, 0x00000100,
1103 0x3c214, 0xffffffff, 0x06000100,
1104 0x3c220, 0xffffffff, 0x00000100,
1105 0x3c218, 0xffffffff, 0x06000100,
1106 0x3c204, 0xffffffff, 0x00000100,
1107 0x3c2e0, 0xffffffff, 0x00000100,
1108 0x3c224, 0xffffffff, 0x00000100,
1109 0x3c200, 0xffffffff, 0x00000100,
1110 0x3c230, 0xffffffff, 0x00000100,
1111 0x3c234, 0xffffffff, 0x00000100,
1112 0x3c250, 0xffffffff, 0x00000100,
1113 0x3c254, 0xffffffff, 0x00000100,
1114 0x3c258, 0xffffffff, 0x00000100,
1115 0x3c25c, 0xffffffff, 0x00000100,
1116 0x3c260, 0xffffffff, 0x00000100,
1117 0x3c27c, 0xffffffff, 0x00000100,
1118 0x3c278, 0xffffffff, 0x00000100,
1119 0x3c210, 0xffffffff, 0x06000100,
1120 0x3c290, 0xffffffff, 0x00000100,
1121 0x3c274, 0xffffffff, 0x00000100,
1122 0x3c2b4, 0xffffffff, 0x00000100,
1123 0x3c2b0, 0xffffffff, 0x00000100,
1124 0x3c270, 0xffffffff, 0x00000100,
1125 0x30800, 0xffffffff, 0xe0000000,
1126 0x3c020, 0xffffffff, 0x00010000,
1127 0x3c024, 0xffffffff, 0x00030002,
1128 0x3c028, 0xffffffff, 0x00040007,
1129 0x3c02c, 0xffffffff, 0x00060005,
1130 0x3c030, 0xffffffff, 0x00090008,
1131 0x3c034, 0xffffffff, 0x00010000,
1132 0x3c038, 0xffffffff, 0x00030002,
1133 0x3c03c, 0xffffffff, 0x00040007,
1134 0x3c040, 0xffffffff, 0x00060005,
1135 0x3c044, 0xffffffff, 0x00090008,
1136 0x3c048, 0xffffffff, 0x00010000,
1137 0x3c04c, 0xffffffff, 0x00030002,
1138 0x3c050, 0xffffffff, 0x00040007,
1139 0x3c054, 0xffffffff, 0x00060005,
1140 0x3c058, 0xffffffff, 0x00090008,
1141 0x3c05c, 0xffffffff, 0x00010000,
1142 0x3c060, 0xffffffff, 0x00030002,
1143 0x3c064, 0xffffffff, 0x00040007,
1144 0x3c068, 0xffffffff, 0x00060005,
1145 0x3c06c, 0xffffffff, 0x00090008,
1146 0x3c070, 0xffffffff, 0x00010000,
1147 0x3c074, 0xffffffff, 0x00030002,
1148 0x3c078, 0xffffffff, 0x00040007,
1149 0x3c07c, 0xffffffff, 0x00060005,
1150 0x3c080, 0xffffffff, 0x00090008,
1151 0x3c084, 0xffffffff, 0x00010000,
1152 0x3c088, 0xffffffff, 0x00030002,
1153 0x3c08c, 0xffffffff, 0x00040007,
1154 0x3c090, 0xffffffff, 0x00060005,
1155 0x3c094, 0xffffffff, 0x00090008,
1156 0x3c098, 0xffffffff, 0x00010000,
1157 0x3c09c, 0xffffffff, 0x00030002,
1158 0x3c0a0, 0xffffffff, 0x00040007,
1159 0x3c0a4, 0xffffffff, 0x00060005,
1160 0x3c0a8, 0xffffffff, 0x00090008,
1161 0x3c000, 0xffffffff, 0x96e00200,
1162 0x8708, 0xffffffff, 0x00900100,
1163 0xc424, 0xffffffff, 0x0020003f,
1164 0x38, 0xffffffff, 0x0140001c,
1165 0x3c, 0x000f0000, 0x000f0000,
1166 0x220, 0xffffffff, 0xC060000C,
1167 0x224, 0xc0000fff, 0x00000100,
1168 0xf90, 0xffffffff, 0x00000100,
1169 0xf98, 0x00000101, 0x00000000,
1170 0x20a8, 0xffffffff, 0x00000104,
1171 0x55e4, 0xff000fff, 0x00000100,
1172 0x30cc, 0xc0000fff, 0x00000104,
1173 0xc1e4, 0x00000001, 0x00000001,
1174 0xd00c, 0xff000ff0, 0x00000100,
1175 0xd80c, 0xff000ff0, 0x00000100
1178 static const u32 spectre_golden_spm_registers[] =
1180 0x30800, 0xe0ffffff, 0xe0000000
1183 static const u32 spectre_golden_common_registers[] =
1185 0xc770, 0xffffffff, 0x00000800,
1186 0xc774, 0xffffffff, 0x00000800,
1187 0xc798, 0xffffffff, 0x00007fbf,
1188 0xc79c, 0xffffffff, 0x00007faf
1191 static const u32 spectre_golden_registers[] =
1193 0x3c000, 0xffff1fff, 0x96940200,
1194 0x3c00c, 0xffff0001, 0xff000000,
1195 0x3c200, 0xfffc0fff, 0x00000100,
1196 0x6ed8, 0x00010101, 0x00010000,
1197 0x9834, 0xf00fffff, 0x00000400,
1198 0x9838, 0xfffffffc, 0x00020200,
1199 0x5bb0, 0x000000f0, 0x00000070,
1200 0x5bc0, 0xf0311fff, 0x80300000,
1201 0x98f8, 0x73773777, 0x12010001,
1202 0x9b7c, 0x00ff0000, 0x00fc0000,
1203 0x2f48, 0x73773777, 0x12010001,
1204 0x8a14, 0xf000003f, 0x00000007,
1205 0x8b24, 0xffffffff, 0x00ffffff,
1206 0x28350, 0x3f3f3fff, 0x00000082,
1207 0x28354, 0x0000003f, 0x00000000,
1208 0x3e78, 0x00000001, 0x00000002,
1209 0x913c, 0xffff03df, 0x00000004,
1210 0xc768, 0x00000008, 0x00000008,
1211 0x8c00, 0x000008ff, 0x00000800,
1212 0x9508, 0x00010000, 0x00010000,
1213 0xac0c, 0xffffffff, 0x54763210,
1214 0x214f8, 0x01ff01ff, 0x00000002,
1215 0x21498, 0x007ff800, 0x00200000,
1216 0x2015c, 0xffffffff, 0x00000f40,
1217 0x30934, 0xffffffff, 0x00000001
1220 static const u32 spectre_mgcg_cgcg_init[] =
1222 0xc420, 0xffffffff, 0xfffffffc,
1223 0x30800, 0xffffffff, 0xe0000000,
1224 0x3c2a0, 0xffffffff, 0x00000100,
1225 0x3c208, 0xffffffff, 0x00000100,
1226 0x3c2c0, 0xffffffff, 0x00000100,
1227 0x3c2c8, 0xffffffff, 0x00000100,
1228 0x3c2c4, 0xffffffff, 0x00000100,
1229 0x55e4, 0xffffffff, 0x00600100,
1230 0x3c280, 0xffffffff, 0x00000100,
1231 0x3c214, 0xffffffff, 0x06000100,
1232 0x3c220, 0xffffffff, 0x00000100,
1233 0x3c218, 0xffffffff, 0x06000100,
1234 0x3c204, 0xffffffff, 0x00000100,
1235 0x3c2e0, 0xffffffff, 0x00000100,
1236 0x3c224, 0xffffffff, 0x00000100,
1237 0x3c200, 0xffffffff, 0x00000100,
1238 0x3c230, 0xffffffff, 0x00000100,
1239 0x3c234, 0xffffffff, 0x00000100,
1240 0x3c250, 0xffffffff, 0x00000100,
1241 0x3c254, 0xffffffff, 0x00000100,
1242 0x3c258, 0xffffffff, 0x00000100,
1243 0x3c25c, 0xffffffff, 0x00000100,
1244 0x3c260, 0xffffffff, 0x00000100,
1245 0x3c27c, 0xffffffff, 0x00000100,
1246 0x3c278, 0xffffffff, 0x00000100,
1247 0x3c210, 0xffffffff, 0x06000100,
1248 0x3c290, 0xffffffff, 0x00000100,
1249 0x3c274, 0xffffffff, 0x00000100,
1250 0x3c2b4, 0xffffffff, 0x00000100,
1251 0x3c2b0, 0xffffffff, 0x00000100,
1252 0x3c270, 0xffffffff, 0x00000100,
1253 0x30800, 0xffffffff, 0xe0000000,
1254 0x3c020, 0xffffffff, 0x00010000,
1255 0x3c024, 0xffffffff, 0x00030002,
1256 0x3c028, 0xffffffff, 0x00040007,
1257 0x3c02c, 0xffffffff, 0x00060005,
1258 0x3c030, 0xffffffff, 0x00090008,
1259 0x3c034, 0xffffffff, 0x00010000,
1260 0x3c038, 0xffffffff, 0x00030002,
1261 0x3c03c, 0xffffffff, 0x00040007,
1262 0x3c040, 0xffffffff, 0x00060005,
1263 0x3c044, 0xffffffff, 0x00090008,
1264 0x3c048, 0xffffffff, 0x00010000,
1265 0x3c04c, 0xffffffff, 0x00030002,
1266 0x3c050, 0xffffffff, 0x00040007,
1267 0x3c054, 0xffffffff, 0x00060005,
1268 0x3c058, 0xffffffff, 0x00090008,
1269 0x3c05c, 0xffffffff, 0x00010000,
1270 0x3c060, 0xffffffff, 0x00030002,
1271 0x3c064, 0xffffffff, 0x00040007,
1272 0x3c068, 0xffffffff, 0x00060005,
1273 0x3c06c, 0xffffffff, 0x00090008,
1274 0x3c070, 0xffffffff, 0x00010000,
1275 0x3c074, 0xffffffff, 0x00030002,
1276 0x3c078, 0xffffffff, 0x00040007,
1277 0x3c07c, 0xffffffff, 0x00060005,
1278 0x3c080, 0xffffffff, 0x00090008,
1279 0x3c084, 0xffffffff, 0x00010000,
1280 0x3c088, 0xffffffff, 0x00030002,
1281 0x3c08c, 0xffffffff, 0x00040007,
1282 0x3c090, 0xffffffff, 0x00060005,
1283 0x3c094, 0xffffffff, 0x00090008,
1284 0x3c098, 0xffffffff, 0x00010000,
1285 0x3c09c, 0xffffffff, 0x00030002,
1286 0x3c0a0, 0xffffffff, 0x00040007,
1287 0x3c0a4, 0xffffffff, 0x00060005,
1288 0x3c0a8, 0xffffffff, 0x00090008,
1289 0x3c0ac, 0xffffffff, 0x00010000,
1290 0x3c0b0, 0xffffffff, 0x00030002,
1291 0x3c0b4, 0xffffffff, 0x00040007,
1292 0x3c0b8, 0xffffffff, 0x00060005,
1293 0x3c0bc, 0xffffffff, 0x00090008,
1294 0x3c000, 0xffffffff, 0x96e00200,
1295 0x8708, 0xffffffff, 0x00900100,
1296 0xc424, 0xffffffff, 0x0020003f,
1297 0x38, 0xffffffff, 0x0140001c,
1298 0x3c, 0x000f0000, 0x000f0000,
1299 0x220, 0xffffffff, 0xC060000C,
1300 0x224, 0xc0000fff, 0x00000100,
1301 0xf90, 0xffffffff, 0x00000100,
1302 0xf98, 0x00000101, 0x00000000,
1303 0x20a8, 0xffffffff, 0x00000104,
1304 0x55e4, 0xff000fff, 0x00000100,
1305 0x30cc, 0xc0000fff, 0x00000104,
1306 0xc1e4, 0x00000001, 0x00000001,
1307 0xd00c, 0xff000ff0, 0x00000100,
1308 0xd80c, 0xff000ff0, 0x00000100
1311 static const u32 kalindi_golden_spm_registers[] =
1313 0x30800, 0xe0ffffff, 0xe0000000
1316 static const u32 kalindi_golden_common_registers[] =
1318 0xc770, 0xffffffff, 0x00000800,
1319 0xc774, 0xffffffff, 0x00000800,
1320 0xc798, 0xffffffff, 0x00007fbf,
1321 0xc79c, 0xffffffff, 0x00007faf
1324 static const u32 kalindi_golden_registers[] =
1326 0x3c000, 0xffffdfff, 0x6e944040,
1327 0x55e4, 0xff607fff, 0xfc000100,
1328 0x3c220, 0xff000fff, 0x00000100,
1329 0x3c224, 0xff000fff, 0x00000100,
1330 0x3c200, 0xfffc0fff, 0x00000100,
1331 0x6ed8, 0x00010101, 0x00010000,
1332 0x9830, 0xffffffff, 0x00000000,
1333 0x9834, 0xf00fffff, 0x00000400,
1334 0x5bb0, 0x000000f0, 0x00000070,
1335 0x5bc0, 0xf0311fff, 0x80300000,
1336 0x98f8, 0x73773777, 0x12010001,
1337 0x98fc, 0xffffffff, 0x00000010,
1338 0x9b7c, 0x00ff0000, 0x00fc0000,
1339 0x8030, 0x00001f0f, 0x0000100a,
1340 0x2f48, 0x73773777, 0x12010001,
1341 0x2408, 0x000fffff, 0x000c007f,
1342 0x8a14, 0xf000003f, 0x00000007,
1343 0x8b24, 0x3fff3fff, 0x00ffcfff,
1344 0x30a04, 0x0000ff0f, 0x00000000,
1345 0x28a4c, 0x07ffffff, 0x06000000,
1346 0x4d8, 0x00000fff, 0x00000100,
1347 0x3e78, 0x00000001, 0x00000002,
1348 0xc768, 0x00000008, 0x00000008,
1349 0x8c00, 0x000000ff, 0x00000003,
1350 0x214f8, 0x01ff01ff, 0x00000002,
1351 0x21498, 0x007ff800, 0x00200000,
1352 0x2015c, 0xffffffff, 0x00000f40,
1353 0x88c4, 0x001f3ae3, 0x00000082,
1354 0x88d4, 0x0000001f, 0x00000010,
1355 0x30934, 0xffffffff, 0x00000000
1358 static const u32 kalindi_mgcg_cgcg_init[] =
1360 0xc420, 0xffffffff, 0xfffffffc,
1361 0x30800, 0xffffffff, 0xe0000000,
1362 0x3c2a0, 0xffffffff, 0x00000100,
1363 0x3c208, 0xffffffff, 0x00000100,
1364 0x3c2c0, 0xffffffff, 0x00000100,
1365 0x3c2c8, 0xffffffff, 0x00000100,
1366 0x3c2c4, 0xffffffff, 0x00000100,
1367 0x55e4, 0xffffffff, 0x00600100,
1368 0x3c280, 0xffffffff, 0x00000100,
1369 0x3c214, 0xffffffff, 0x06000100,
1370 0x3c220, 0xffffffff, 0x00000100,
1371 0x3c218, 0xffffffff, 0x06000100,
1372 0x3c204, 0xffffffff, 0x00000100,
1373 0x3c2e0, 0xffffffff, 0x00000100,
1374 0x3c224, 0xffffffff, 0x00000100,
1375 0x3c200, 0xffffffff, 0x00000100,
1376 0x3c230, 0xffffffff, 0x00000100,
1377 0x3c234, 0xffffffff, 0x00000100,
1378 0x3c250, 0xffffffff, 0x00000100,
1379 0x3c254, 0xffffffff, 0x00000100,
1380 0x3c258, 0xffffffff, 0x00000100,
1381 0x3c25c, 0xffffffff, 0x00000100,
1382 0x3c260, 0xffffffff, 0x00000100,
1383 0x3c27c, 0xffffffff, 0x00000100,
1384 0x3c278, 0xffffffff, 0x00000100,
1385 0x3c210, 0xffffffff, 0x06000100,
1386 0x3c290, 0xffffffff, 0x00000100,
1387 0x3c274, 0xffffffff, 0x00000100,
1388 0x3c2b4, 0xffffffff, 0x00000100,
1389 0x3c2b0, 0xffffffff, 0x00000100,
1390 0x3c270, 0xffffffff, 0x00000100,
1391 0x30800, 0xffffffff, 0xe0000000,
1392 0x3c020, 0xffffffff, 0x00010000,
1393 0x3c024, 0xffffffff, 0x00030002,
1394 0x3c028, 0xffffffff, 0x00040007,
1395 0x3c02c, 0xffffffff, 0x00060005,
1396 0x3c030, 0xffffffff, 0x00090008,
1397 0x3c034, 0xffffffff, 0x00010000,
1398 0x3c038, 0xffffffff, 0x00030002,
1399 0x3c03c, 0xffffffff, 0x00040007,
1400 0x3c040, 0xffffffff, 0x00060005,
1401 0x3c044, 0xffffffff, 0x00090008,
1402 0x3c000, 0xffffffff, 0x96e00200,
1403 0x8708, 0xffffffff, 0x00900100,
1404 0xc424, 0xffffffff, 0x0020003f,
1405 0x38, 0xffffffff, 0x0140001c,
1406 0x3c, 0x000f0000, 0x000f0000,
1407 0x220, 0xffffffff, 0xC060000C,
1408 0x224, 0xc0000fff, 0x00000100,
1409 0x20a8, 0xffffffff, 0x00000104,
1410 0x55e4, 0xff000fff, 0x00000100,
1411 0x30cc, 0xc0000fff, 0x00000104,
1412 0xc1e4, 0x00000001, 0x00000001,
1413 0xd00c, 0xff000ff0, 0x00000100,
1414 0xd80c, 0xff000ff0, 0x00000100
1417 static const u32 hawaii_golden_spm_registers[] =
1419 0x30800, 0xe0ffffff, 0xe0000000
1422 static const u32 hawaii_golden_common_registers[] =
1424 0x30800, 0xffffffff, 0xe0000000,
1425 0x28350, 0xffffffff, 0x3a00161a,
1426 0x28354, 0xffffffff, 0x0000002e,
1427 0x9a10, 0xffffffff, 0x00018208,
1428 0x98f8, 0xffffffff, 0x12011003
1431 static const u32 hawaii_golden_registers[] =
1433 0x3354, 0x00000333, 0x00000333,
1434 0x9a10, 0x00010000, 0x00058208,
1435 0x9830, 0xffffffff, 0x00000000,
1436 0x9834, 0xf00fffff, 0x00000400,
1437 0x9838, 0x0002021c, 0x00020200,
1438 0xc78, 0x00000080, 0x00000000,
1439 0x5bb0, 0x000000f0, 0x00000070,
1440 0x5bc0, 0xf0311fff, 0x80300000,
1441 0x350c, 0x00810000, 0x408af000,
1442 0x7030, 0x31000111, 0x00000011,
1443 0x2f48, 0x73773777, 0x12010001,
1444 0x2120, 0x0000007f, 0x0000001b,
1445 0x21dc, 0x00007fb6, 0x00002191,
1446 0x3628, 0x0000003f, 0x0000000a,
1447 0x362c, 0x0000003f, 0x0000000a,
1448 0x2ae4, 0x00073ffe, 0x000022a2,
1449 0x240c, 0x000007ff, 0x00000000,
1450 0x8bf0, 0x00002001, 0x00000001,
1451 0x8b24, 0xffffffff, 0x00ffffff,
1452 0x30a04, 0x0000ff0f, 0x00000000,
1453 0x28a4c, 0x07ffffff, 0x06000000,
1454 0x3e78, 0x00000001, 0x00000002,
1455 0xc768, 0x00000008, 0x00000008,
1456 0xc770, 0x00000f00, 0x00000800,
1457 0xc774, 0x00000f00, 0x00000800,
1458 0xc798, 0x00ffffff, 0x00ff7fbf,
1459 0xc79c, 0x00ffffff, 0x00ff7faf,
1460 0x8c00, 0x000000ff, 0x00000800,
1461 0xe40, 0x00001fff, 0x00001fff,
1462 0x9060, 0x0000007f, 0x00000020,
1463 0x9508, 0x00010000, 0x00010000,
1464 0xae00, 0x00100000, 0x000ff07c,
1465 0xac14, 0x000003ff, 0x0000000f,
1466 0xac10, 0xffffffff, 0x7564fdec,
1467 0xac0c, 0xffffffff, 0x3120b9a8,
1468 0xac08, 0x20000000, 0x0f9c0000
1471 static const u32 hawaii_mgcg_cgcg_init[] =
1473 0xc420, 0xffffffff, 0xfffffffd,
1474 0x30800, 0xffffffff, 0xe0000000,
1475 0x3c2a0, 0xffffffff, 0x00000100,
1476 0x3c208, 0xffffffff, 0x00000100,
1477 0x3c2c0, 0xffffffff, 0x00000100,
1478 0x3c2c8, 0xffffffff, 0x00000100,
1479 0x3c2c4, 0xffffffff, 0x00000100,
1480 0x55e4, 0xffffffff, 0x00200100,
1481 0x3c280, 0xffffffff, 0x00000100,
1482 0x3c214, 0xffffffff, 0x06000100,
1483 0x3c220, 0xffffffff, 0x00000100,
1484 0x3c218, 0xffffffff, 0x06000100,
1485 0x3c204, 0xffffffff, 0x00000100,
1486 0x3c2e0, 0xffffffff, 0x00000100,
1487 0x3c224, 0xffffffff, 0x00000100,
1488 0x3c200, 0xffffffff, 0x00000100,
1489 0x3c230, 0xffffffff, 0x00000100,
1490 0x3c234, 0xffffffff, 0x00000100,
1491 0x3c250, 0xffffffff, 0x00000100,
1492 0x3c254, 0xffffffff, 0x00000100,
1493 0x3c258, 0xffffffff, 0x00000100,
1494 0x3c25c, 0xffffffff, 0x00000100,
1495 0x3c260, 0xffffffff, 0x00000100,
1496 0x3c27c, 0xffffffff, 0x00000100,
1497 0x3c278, 0xffffffff, 0x00000100,
1498 0x3c210, 0xffffffff, 0x06000100,
1499 0x3c290, 0xffffffff, 0x00000100,
1500 0x3c274, 0xffffffff, 0x00000100,
1501 0x3c2b4, 0xffffffff, 0x00000100,
1502 0x3c2b0, 0xffffffff, 0x00000100,
1503 0x3c270, 0xffffffff, 0x00000100,
1504 0x30800, 0xffffffff, 0xe0000000,
1505 0x3c020, 0xffffffff, 0x00010000,
1506 0x3c024, 0xffffffff, 0x00030002,
1507 0x3c028, 0xffffffff, 0x00040007,
1508 0x3c02c, 0xffffffff, 0x00060005,
1509 0x3c030, 0xffffffff, 0x00090008,
1510 0x3c034, 0xffffffff, 0x00010000,
1511 0x3c038, 0xffffffff, 0x00030002,
1512 0x3c03c, 0xffffffff, 0x00040007,
1513 0x3c040, 0xffffffff, 0x00060005,
1514 0x3c044, 0xffffffff, 0x00090008,
1515 0x3c048, 0xffffffff, 0x00010000,
1516 0x3c04c, 0xffffffff, 0x00030002,
1517 0x3c050, 0xffffffff, 0x00040007,
1518 0x3c054, 0xffffffff, 0x00060005,
1519 0x3c058, 0xffffffff, 0x00090008,
1520 0x3c05c, 0xffffffff, 0x00010000,
1521 0x3c060, 0xffffffff, 0x00030002,
1522 0x3c064, 0xffffffff, 0x00040007,
1523 0x3c068, 0xffffffff, 0x00060005,
1524 0x3c06c, 0xffffffff, 0x00090008,
1525 0x3c070, 0xffffffff, 0x00010000,
1526 0x3c074, 0xffffffff, 0x00030002,
1527 0x3c078, 0xffffffff, 0x00040007,
1528 0x3c07c, 0xffffffff, 0x00060005,
1529 0x3c080, 0xffffffff, 0x00090008,
1530 0x3c084, 0xffffffff, 0x00010000,
1531 0x3c088, 0xffffffff, 0x00030002,
1532 0x3c08c, 0xffffffff, 0x00040007,
1533 0x3c090, 0xffffffff, 0x00060005,
1534 0x3c094, 0xffffffff, 0x00090008,
1535 0x3c098, 0xffffffff, 0x00010000,
1536 0x3c09c, 0xffffffff, 0x00030002,
1537 0x3c0a0, 0xffffffff, 0x00040007,
1538 0x3c0a4, 0xffffffff, 0x00060005,
1539 0x3c0a8, 0xffffffff, 0x00090008,
1540 0x3c0ac, 0xffffffff, 0x00010000,
1541 0x3c0b0, 0xffffffff, 0x00030002,
1542 0x3c0b4, 0xffffffff, 0x00040007,
1543 0x3c0b8, 0xffffffff, 0x00060005,
1544 0x3c0bc, 0xffffffff, 0x00090008,
1545 0x3c0c0, 0xffffffff, 0x00010000,
1546 0x3c0c4, 0xffffffff, 0x00030002,
1547 0x3c0c8, 0xffffffff, 0x00040007,
1548 0x3c0cc, 0xffffffff, 0x00060005,
1549 0x3c0d0, 0xffffffff, 0x00090008,
1550 0x3c0d4, 0xffffffff, 0x00010000,
1551 0x3c0d8, 0xffffffff, 0x00030002,
1552 0x3c0dc, 0xffffffff, 0x00040007,
1553 0x3c0e0, 0xffffffff, 0x00060005,
1554 0x3c0e4, 0xffffffff, 0x00090008,
1555 0x3c0e8, 0xffffffff, 0x00010000,
1556 0x3c0ec, 0xffffffff, 0x00030002,
1557 0x3c0f0, 0xffffffff, 0x00040007,
1558 0x3c0f4, 0xffffffff, 0x00060005,
1559 0x3c0f8, 0xffffffff, 0x00090008,
1560 0xc318, 0xffffffff, 0x00020200,
1561 0x3350, 0xffffffff, 0x00000200,
1562 0x15c0, 0xffffffff, 0x00000400,
1563 0x55e8, 0xffffffff, 0x00000000,
1564 0x2f50, 0xffffffff, 0x00000902,
1565 0x3c000, 0xffffffff, 0x96940200,
1566 0x8708, 0xffffffff, 0x00900100,
1567 0xc424, 0xffffffff, 0x0020003f,
1568 0x38, 0xffffffff, 0x0140001c,
1569 0x3c, 0x000f0000, 0x000f0000,
1570 0x220, 0xffffffff, 0xc060000c,
1571 0x224, 0xc0000fff, 0x00000100,
1572 0xf90, 0xffffffff, 0x00000100,
1573 0xf98, 0x00000101, 0x00000000,
1574 0x20a8, 0xffffffff, 0x00000104,
1575 0x55e4, 0xff000fff, 0x00000100,
1576 0x30cc, 0xc0000fff, 0x00000104,
1577 0xc1e4, 0x00000001, 0x00000001,
1578 0xd00c, 0xff000ff0, 0x00000100,
1579 0xd80c, 0xff000ff0, 0x00000100
1582 static const u32 godavari_golden_registers[] =
1584 0x55e4, 0xff607fff, 0xfc000100,
1585 0x6ed8, 0x00010101, 0x00010000,
1586 0x9830, 0xffffffff, 0x00000000,
1587 0x98302, 0xf00fffff, 0x00000400,
1588 0x6130, 0xffffffff, 0x00010000,
1589 0x5bb0, 0x000000f0, 0x00000070,
1590 0x5bc0, 0xf0311fff, 0x80300000,
1591 0x98f8, 0x73773777, 0x12010001,
1592 0x98fc, 0xffffffff, 0x00000010,
1593 0x8030, 0x00001f0f, 0x0000100a,
1594 0x2f48, 0x73773777, 0x12010001,
1595 0x2408, 0x000fffff, 0x000c007f,
1596 0x8a14, 0xf000003f, 0x00000007,
1597 0x8b24, 0xffffffff, 0x00ff0fff,
1598 0x30a04, 0x0000ff0f, 0x00000000,
1599 0x28a4c, 0x07ffffff, 0x06000000,
1600 0x4d8, 0x00000fff, 0x00000100,
1601 0xd014, 0x00010000, 0x00810001,
1602 0xd814, 0x00010000, 0x00810001,
1603 0x3e78, 0x00000001, 0x00000002,
1604 0xc768, 0x00000008, 0x00000008,
1605 0xc770, 0x00000f00, 0x00000800,
1606 0xc774, 0x00000f00, 0x00000800,
1607 0xc798, 0x00ffffff, 0x00ff7fbf,
1608 0xc79c, 0x00ffffff, 0x00ff7faf,
1609 0x8c00, 0x000000ff, 0x00000001,
1610 0x214f8, 0x01ff01ff, 0x00000002,
1611 0x21498, 0x007ff800, 0x00200000,
1612 0x2015c, 0xffffffff, 0x00000f40,
1613 0x88c4, 0x001f3ae3, 0x00000082,
1614 0x88d4, 0x0000001f, 0x00000010,
1615 0x30934, 0xffffffff, 0x00000000
1619 static void cik_init_golden_registers(struct radeon_device *rdev)
1621 switch (rdev->family) {
1623 radeon_program_register_sequence(rdev,
1624 bonaire_mgcg_cgcg_init,
1625 (const u32)ARRAY_SIZE(bonaire_mgcg_cgcg_init));
1626 radeon_program_register_sequence(rdev,
1627 bonaire_golden_registers,
1628 (const u32)ARRAY_SIZE(bonaire_golden_registers));
1629 radeon_program_register_sequence(rdev,
1630 bonaire_golden_common_registers,
1631 (const u32)ARRAY_SIZE(bonaire_golden_common_registers));
1632 radeon_program_register_sequence(rdev,
1633 bonaire_golden_spm_registers,
1634 (const u32)ARRAY_SIZE(bonaire_golden_spm_registers));
1637 radeon_program_register_sequence(rdev,
1638 kalindi_mgcg_cgcg_init,
1639 (const u32)ARRAY_SIZE(kalindi_mgcg_cgcg_init));
1640 radeon_program_register_sequence(rdev,
1641 kalindi_golden_registers,
1642 (const u32)ARRAY_SIZE(kalindi_golden_registers));
1643 radeon_program_register_sequence(rdev,
1644 kalindi_golden_common_registers,
1645 (const u32)ARRAY_SIZE(kalindi_golden_common_registers));
1646 radeon_program_register_sequence(rdev,
1647 kalindi_golden_spm_registers,
1648 (const u32)ARRAY_SIZE(kalindi_golden_spm_registers));
1651 radeon_program_register_sequence(rdev,
1652 kalindi_mgcg_cgcg_init,
1653 (const u32)ARRAY_SIZE(kalindi_mgcg_cgcg_init));
1654 radeon_program_register_sequence(rdev,
1655 godavari_golden_registers,
1656 (const u32)ARRAY_SIZE(godavari_golden_registers));
1657 radeon_program_register_sequence(rdev,
1658 kalindi_golden_common_registers,
1659 (const u32)ARRAY_SIZE(kalindi_golden_common_registers));
1660 radeon_program_register_sequence(rdev,
1661 kalindi_golden_spm_registers,
1662 (const u32)ARRAY_SIZE(kalindi_golden_spm_registers));
1665 radeon_program_register_sequence(rdev,
1666 spectre_mgcg_cgcg_init,
1667 (const u32)ARRAY_SIZE(spectre_mgcg_cgcg_init));
1668 radeon_program_register_sequence(rdev,
1669 spectre_golden_registers,
1670 (const u32)ARRAY_SIZE(spectre_golden_registers));
1671 radeon_program_register_sequence(rdev,
1672 spectre_golden_common_registers,
1673 (const u32)ARRAY_SIZE(spectre_golden_common_registers));
1674 radeon_program_register_sequence(rdev,
1675 spectre_golden_spm_registers,
1676 (const u32)ARRAY_SIZE(spectre_golden_spm_registers));
1679 radeon_program_register_sequence(rdev,
1680 hawaii_mgcg_cgcg_init,
1681 (const u32)ARRAY_SIZE(hawaii_mgcg_cgcg_init));
1682 radeon_program_register_sequence(rdev,
1683 hawaii_golden_registers,
1684 (const u32)ARRAY_SIZE(hawaii_golden_registers));
1685 radeon_program_register_sequence(rdev,
1686 hawaii_golden_common_registers,
1687 (const u32)ARRAY_SIZE(hawaii_golden_common_registers));
1688 radeon_program_register_sequence(rdev,
1689 hawaii_golden_spm_registers,
1690 (const u32)ARRAY_SIZE(hawaii_golden_spm_registers));
1698 * cik_get_xclk - get the xclk
1700 * @rdev: radeon_device pointer
1702 * Returns the reference clock used by the gfx engine
1705 u32 cik_get_xclk(struct radeon_device *rdev)
1707 u32 reference_clock = rdev->clock.spll.reference_freq;
1709 if (rdev->flags & RADEON_IS_IGP) {
1710 if (RREG32_SMC(GENERAL_PWRMGT) & GPU_COUNTER_CLK)
1711 return reference_clock / 2;
1713 if (RREG32_SMC(CG_CLKPIN_CNTL) & XTALIN_DIVIDE)
1714 return reference_clock / 4;
1716 return reference_clock;
1720 * cik_mm_rdoorbell - read a doorbell dword
1722 * @rdev: radeon_device pointer
1723 * @index: doorbell index
1725 * Returns the value in the doorbell aperture at the
1726 * requested doorbell index (CIK).
1728 u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 index)
1730 if (index < rdev->doorbell.num_doorbells) {
1731 return readl(rdev->doorbell.ptr + index);
1733 DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index);
1739 * cik_mm_wdoorbell - write a doorbell dword
1741 * @rdev: radeon_device pointer
1742 * @index: doorbell index
1743 * @v: value to write
1745 * Writes @v to the doorbell aperture at the
1746 * requested doorbell index (CIK).
1748 void cik_mm_wdoorbell(struct radeon_device *rdev, u32 index, u32 v)
1750 if (index < rdev->doorbell.num_doorbells) {
1751 writel(v, rdev->doorbell.ptr + index);
1753 DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index);
1757 #define BONAIRE_IO_MC_REGS_SIZE 36
1759 static const u32 bonaire_io_mc_regs[BONAIRE_IO_MC_REGS_SIZE][2] =
1761 {0x00000070, 0x04400000},
1762 {0x00000071, 0x80c01803},
1763 {0x00000072, 0x00004004},
1764 {0x00000073, 0x00000100},
1765 {0x00000074, 0x00ff0000},
1766 {0x00000075, 0x34000000},
1767 {0x00000076, 0x08000014},
1768 {0x00000077, 0x00cc08ec},
1769 {0x00000078, 0x00000400},
1770 {0x00000079, 0x00000000},
1771 {0x0000007a, 0x04090000},
1772 {0x0000007c, 0x00000000},
1773 {0x0000007e, 0x4408a8e8},
1774 {0x0000007f, 0x00000304},
1775 {0x00000080, 0x00000000},
1776 {0x00000082, 0x00000001},
1777 {0x00000083, 0x00000002},
1778 {0x00000084, 0xf3e4f400},
1779 {0x00000085, 0x052024e3},
1780 {0x00000087, 0x00000000},
1781 {0x00000088, 0x01000000},
1782 {0x0000008a, 0x1c0a0000},
1783 {0x0000008b, 0xff010000},
1784 {0x0000008d, 0xffffefff},
1785 {0x0000008e, 0xfff3efff},
1786 {0x0000008f, 0xfff3efbf},
1787 {0x00000092, 0xf7ffffff},
1788 {0x00000093, 0xffffff7f},
1789 {0x00000095, 0x00101101},
1790 {0x00000096, 0x00000fff},
1791 {0x00000097, 0x00116fff},
1792 {0x00000098, 0x60010000},
1793 {0x00000099, 0x10010000},
1794 {0x0000009a, 0x00006000},
1795 {0x0000009b, 0x00001000},
1796 {0x0000009f, 0x00b48000}
1799 #define HAWAII_IO_MC_REGS_SIZE 22
1801 static const u32 hawaii_io_mc_regs[HAWAII_IO_MC_REGS_SIZE][2] =
1803 {0x0000007d, 0x40000000},
1804 {0x0000007e, 0x40180304},
1805 {0x0000007f, 0x0000ff00},
1806 {0x00000081, 0x00000000},
1807 {0x00000083, 0x00000800},
1808 {0x00000086, 0x00000000},
1809 {0x00000087, 0x00000100},
1810 {0x00000088, 0x00020100},
1811 {0x00000089, 0x00000000},
1812 {0x0000008b, 0x00040000},
1813 {0x0000008c, 0x00000100},
1814 {0x0000008e, 0xff010000},
1815 {0x00000090, 0xffffefff},
1816 {0x00000091, 0xfff3efff},
1817 {0x00000092, 0xfff3efbf},
1818 {0x00000093, 0xf7ffffff},
1819 {0x00000094, 0xffffff7f},
1820 {0x00000095, 0x00000fff},
1821 {0x00000096, 0x00116fff},
1822 {0x00000097, 0x60010000},
1823 {0x00000098, 0x10010000},
1824 {0x0000009f, 0x00c79000}
1829 * cik_srbm_select - select specific register instances
1831 * @rdev: radeon_device pointer
1832 * @me: selected ME (micro engine)
1837 * Switches the currently active registers instances. Some
1838 * registers are instanced per VMID, others are instanced per
1839 * me/pipe/queue combination.
1841 static void cik_srbm_select(struct radeon_device *rdev,
1842 u32 me, u32 pipe, u32 queue, u32 vmid)
1844 u32 srbm_gfx_cntl = (PIPEID(pipe & 0x3) |
1847 QUEUEID(queue & 0x7));
1848 WREG32(SRBM_GFX_CNTL, srbm_gfx_cntl);
1853 * ci_mc_load_microcode - load MC ucode into the hw
1855 * @rdev: radeon_device pointer
1857 * Load the GDDR MC ucode into the hw (CIK).
1858 * Returns 0 on success, error on failure.
1860 int ci_mc_load_microcode(struct radeon_device *rdev)
1862 const __be32 *fw_data = NULL;
1863 const __le32 *new_fw_data = NULL;
1865 u32 *io_mc_regs = NULL;
1866 const __le32 *new_io_mc_regs = NULL;
1867 int i, regs_size, ucode_size;
1873 const struct mc_firmware_header_v1_0 *hdr =
1874 (const struct mc_firmware_header_v1_0 *)rdev->mc_fw->data;
1876 radeon_ucode_print_mc_hdr(&hdr->header);
1878 regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2);
1879 new_io_mc_regs = (const __le32 *)
1880 (rdev->mc_fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes));
1881 ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
1882 new_fw_data = (const __le32 *)
1883 (rdev->mc_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
1885 ucode_size = rdev->mc_fw->size / 4;
1887 switch (rdev->family) {
1889 io_mc_regs = (u32 *)&bonaire_io_mc_regs;
1890 regs_size = BONAIRE_IO_MC_REGS_SIZE;
1893 io_mc_regs = (u32 *)&hawaii_io_mc_regs;
1894 regs_size = HAWAII_IO_MC_REGS_SIZE;
1899 fw_data = (const __be32 *)rdev->mc_fw->data;
1902 running = RREG32(MC_SEQ_SUP_CNTL) & RUN_MASK;
1905 /* reset the engine and set to writable */
1906 WREG32(MC_SEQ_SUP_CNTL, 0x00000008);
1907 WREG32(MC_SEQ_SUP_CNTL, 0x00000010);
1909 /* load mc io regs */
1910 for (i = 0; i < regs_size; i++) {
1912 WREG32(MC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(new_io_mc_regs++));
1913 WREG32(MC_SEQ_IO_DEBUG_DATA, le32_to_cpup(new_io_mc_regs++));
1915 WREG32(MC_SEQ_IO_DEBUG_INDEX, io_mc_regs[(i << 1)]);
1916 WREG32(MC_SEQ_IO_DEBUG_DATA, io_mc_regs[(i << 1) + 1]);
1920 tmp = RREG32(MC_SEQ_MISC0);
1921 if ((rdev->pdev->device == 0x6649) && ((tmp & 0xff00) == 0x5600)) {
1922 WREG32(MC_SEQ_IO_DEBUG_INDEX, 5);
1923 WREG32(MC_SEQ_IO_DEBUG_DATA, 0x00000023);
1924 WREG32(MC_SEQ_IO_DEBUG_INDEX, 9);
1925 WREG32(MC_SEQ_IO_DEBUG_DATA, 0x000001f0);
1928 /* load the MC ucode */
1929 for (i = 0; i < ucode_size; i++) {
1931 WREG32(MC_SEQ_SUP_PGM, le32_to_cpup(new_fw_data++));
1933 WREG32(MC_SEQ_SUP_PGM, be32_to_cpup(fw_data++));
1936 /* put the engine back into the active state */
1937 WREG32(MC_SEQ_SUP_CNTL, 0x00000008);
1938 WREG32(MC_SEQ_SUP_CNTL, 0x00000004);
1939 WREG32(MC_SEQ_SUP_CNTL, 0x00000001);
1941 /* wait for training to complete */
1942 for (i = 0; i < rdev->usec_timeout; i++) {
1943 if (RREG32(MC_SEQ_TRAIN_WAKEUP_CNTL) & TRAIN_DONE_D0)
1947 for (i = 0; i < rdev->usec_timeout; i++) {
1948 if (RREG32(MC_SEQ_TRAIN_WAKEUP_CNTL) & TRAIN_DONE_D1)
1958 * cik_init_microcode - load ucode images from disk
1960 * @rdev: radeon_device pointer
1962 * Use the firmware interface to load the ucode images into
1963 * the driver (not loaded into hw).
1964 * Returns 0 on success, error on failure.
1966 static int cik_init_microcode(struct radeon_device *rdev)
1968 const char *chip_name;
1969 const char *new_chip_name;
1970 size_t pfp_req_size, me_req_size, ce_req_size,
1971 mec_req_size, rlc_req_size, mc_req_size = 0,
1972 sdma_req_size, smc_req_size = 0, mc2_req_size = 0;
1977 bool new_smc = false;
1981 switch (rdev->family) {
1983 chip_name = "BONAIRE";
1984 if ((rdev->pdev->revision == 0x80) ||
1985 (rdev->pdev->revision == 0x81) ||
1986 (rdev->pdev->device == 0x665f))
1988 new_chip_name = "bonaire";
1989 pfp_req_size = CIK_PFP_UCODE_SIZE * 4;
1990 me_req_size = CIK_ME_UCODE_SIZE * 4;
1991 ce_req_size = CIK_CE_UCODE_SIZE * 4;
1992 mec_req_size = CIK_MEC_UCODE_SIZE * 4;
1993 rlc_req_size = BONAIRE_RLC_UCODE_SIZE * 4;
1994 mc_req_size = BONAIRE_MC_UCODE_SIZE * 4;
1995 mc2_req_size = BONAIRE_MC2_UCODE_SIZE * 4;
1996 sdma_req_size = CIK_SDMA_UCODE_SIZE * 4;
1997 smc_req_size = ALIGN(BONAIRE_SMC_UCODE_SIZE, 4);
2001 chip_name = "HAWAII";
2002 if (rdev->pdev->revision == 0x80)
2004 new_chip_name = "hawaii";
2005 pfp_req_size = CIK_PFP_UCODE_SIZE * 4;
2006 me_req_size = CIK_ME_UCODE_SIZE * 4;
2007 ce_req_size = CIK_CE_UCODE_SIZE * 4;
2008 mec_req_size = CIK_MEC_UCODE_SIZE * 4;
2009 rlc_req_size = BONAIRE_RLC_UCODE_SIZE * 4;
2010 mc_req_size = HAWAII_MC_UCODE_SIZE * 4;
2011 mc2_req_size = HAWAII_MC2_UCODE_SIZE * 4;
2012 sdma_req_size = CIK_SDMA_UCODE_SIZE * 4;
2013 smc_req_size = ALIGN(HAWAII_SMC_UCODE_SIZE, 4);
2017 chip_name = "KAVERI";
2018 new_chip_name = "kaveri";
2019 pfp_req_size = CIK_PFP_UCODE_SIZE * 4;
2020 me_req_size = CIK_ME_UCODE_SIZE * 4;
2021 ce_req_size = CIK_CE_UCODE_SIZE * 4;
2022 mec_req_size = CIK_MEC_UCODE_SIZE * 4;
2023 rlc_req_size = KV_RLC_UCODE_SIZE * 4;
2024 sdma_req_size = CIK_SDMA_UCODE_SIZE * 4;
2028 chip_name = "KABINI";
2029 new_chip_name = "kabini";
2030 pfp_req_size = CIK_PFP_UCODE_SIZE * 4;
2031 me_req_size = CIK_ME_UCODE_SIZE * 4;
2032 ce_req_size = CIK_CE_UCODE_SIZE * 4;
2033 mec_req_size = CIK_MEC_UCODE_SIZE * 4;
2034 rlc_req_size = KB_RLC_UCODE_SIZE * 4;
2035 sdma_req_size = CIK_SDMA_UCODE_SIZE * 4;
2039 chip_name = "MULLINS";
2040 new_chip_name = "mullins";
2041 pfp_req_size = CIK_PFP_UCODE_SIZE * 4;
2042 me_req_size = CIK_ME_UCODE_SIZE * 4;
2043 ce_req_size = CIK_CE_UCODE_SIZE * 4;
2044 mec_req_size = CIK_MEC_UCODE_SIZE * 4;
2045 rlc_req_size = ML_RLC_UCODE_SIZE * 4;
2046 sdma_req_size = CIK_SDMA_UCODE_SIZE * 4;
2052 DRM_INFO("Loading %s Microcode\n", new_chip_name);
2054 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", new_chip_name);
2055 err = request_firmware(&rdev->pfp_fw, fw_name, rdev->dev);
2057 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
2058 err = request_firmware(&rdev->pfp_fw, fw_name, rdev->dev);
2061 if (rdev->pfp_fw->size != pfp_req_size) {
2062 pr_err("cik_cp: Bogus length %zu in firmware \"%s\"\n",
2063 rdev->pfp_fw->size, fw_name);
2068 err = radeon_ucode_validate(rdev->pfp_fw);
2070 pr_err("cik_fw: validation failed for firmware \"%s\"\n",
2078 snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", new_chip_name);
2079 err = request_firmware(&rdev->me_fw, fw_name, rdev->dev);
2081 snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
2082 err = request_firmware(&rdev->me_fw, fw_name, rdev->dev);
2085 if (rdev->me_fw->size != me_req_size) {
2086 pr_err("cik_cp: Bogus length %zu in firmware \"%s\"\n",
2087 rdev->me_fw->size, fw_name);
2091 err = radeon_ucode_validate(rdev->me_fw);
2093 pr_err("cik_fw: validation failed for firmware \"%s\"\n",
2101 snprintf(fw_name, sizeof(fw_name), "radeon/%s_ce.bin", new_chip_name);
2102 err = request_firmware(&rdev->ce_fw, fw_name, rdev->dev);
2104 snprintf(fw_name, sizeof(fw_name), "radeon/%s_ce.bin", chip_name);
2105 err = request_firmware(&rdev->ce_fw, fw_name, rdev->dev);
2108 if (rdev->ce_fw->size != ce_req_size) {
2109 pr_err("cik_cp: Bogus length %zu in firmware \"%s\"\n",
2110 rdev->ce_fw->size, fw_name);
2114 err = radeon_ucode_validate(rdev->ce_fw);
2116 pr_err("cik_fw: validation failed for firmware \"%s\"\n",
2124 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mec.bin", new_chip_name);
2125 err = request_firmware(&rdev->mec_fw, fw_name, rdev->dev);
2127 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mec.bin", chip_name);
2128 err = request_firmware(&rdev->mec_fw, fw_name, rdev->dev);
2131 if (rdev->mec_fw->size != mec_req_size) {
2132 pr_err("cik_cp: Bogus length %zu in firmware \"%s\"\n",
2133 rdev->mec_fw->size, fw_name);
2137 err = radeon_ucode_validate(rdev->mec_fw);
2139 pr_err("cik_fw: validation failed for firmware \"%s\"\n",
2147 if (rdev->family == CHIP_KAVERI) {
2148 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mec2.bin", new_chip_name);
2149 err = request_firmware(&rdev->mec2_fw, fw_name, rdev->dev);
2153 err = radeon_ucode_validate(rdev->mec2_fw);
2162 snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", new_chip_name);
2163 err = request_firmware(&rdev->rlc_fw, fw_name, rdev->dev);
2165 snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", chip_name);
2166 err = request_firmware(&rdev->rlc_fw, fw_name, rdev->dev);
2169 if (rdev->rlc_fw->size != rlc_req_size) {
2170 pr_err("cik_rlc: Bogus length %zu in firmware \"%s\"\n",
2171 rdev->rlc_fw->size, fw_name);
2175 err = radeon_ucode_validate(rdev->rlc_fw);
2177 pr_err("cik_fw: validation failed for firmware \"%s\"\n",
2185 snprintf(fw_name, sizeof(fw_name), "radeon/%s_sdma.bin", new_chip_name);
2186 err = request_firmware(&rdev->sdma_fw, fw_name, rdev->dev);
2188 snprintf(fw_name, sizeof(fw_name), "radeon/%s_sdma.bin", chip_name);
2189 err = request_firmware(&rdev->sdma_fw, fw_name, rdev->dev);
2192 if (rdev->sdma_fw->size != sdma_req_size) {
2193 pr_err("cik_sdma: Bogus length %zu in firmware \"%s\"\n",
2194 rdev->sdma_fw->size, fw_name);
2198 err = radeon_ucode_validate(rdev->sdma_fw);
2200 pr_err("cik_fw: validation failed for firmware \"%s\"\n",
2208 /* No SMC, MC ucode on APUs */
2209 if (!(rdev->flags & RADEON_IS_IGP)) {
2210 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", new_chip_name);
2211 err = request_firmware(&rdev->mc_fw, fw_name, rdev->dev);
2213 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc2.bin", chip_name);
2214 err = request_firmware(&rdev->mc_fw, fw_name, rdev->dev);
2216 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", chip_name);
2217 err = request_firmware(&rdev->mc_fw, fw_name, rdev->dev);
2221 if ((rdev->mc_fw->size != mc_req_size) &&
2222 (rdev->mc_fw->size != mc2_req_size)){
2223 pr_err("cik_mc: Bogus length %zu in firmware \"%s\"\n",
2224 rdev->mc_fw->size, fw_name);
2227 DRM_INFO("%s: %zu bytes\n", fw_name, rdev->mc_fw->size);
2229 err = radeon_ucode_validate(rdev->mc_fw);
2231 pr_err("cik_fw: validation failed for firmware \"%s\"\n",
2240 snprintf(fw_name, sizeof(fw_name), "radeon/%s_k_smc.bin", new_chip_name);
2242 snprintf(fw_name, sizeof(fw_name), "radeon/%s_smc.bin", new_chip_name);
2243 err = request_firmware(&rdev->smc_fw, fw_name, rdev->dev);
2245 snprintf(fw_name, sizeof(fw_name), "radeon/%s_smc.bin", chip_name);
2246 err = request_firmware(&rdev->smc_fw, fw_name, rdev->dev);
2248 pr_err("smc: error loading firmware \"%s\"\n",
2250 release_firmware(rdev->smc_fw);
2251 rdev->smc_fw = NULL;
2253 } else if (rdev->smc_fw->size != smc_req_size) {
2254 pr_err("cik_smc: Bogus length %zu in firmware \"%s\"\n",
2255 rdev->smc_fw->size, fw_name);
2259 err = radeon_ucode_validate(rdev->smc_fw);
2261 pr_err("cik_fw: validation failed for firmware \"%s\"\n",
2271 rdev->new_fw = false;
2272 } else if (new_fw < num_fw) {
2273 pr_err("ci_fw: mixing new and old firmware!\n");
2276 rdev->new_fw = true;
2282 pr_err("cik_cp: Failed to load firmware \"%s\"\n",
2284 release_firmware(rdev->pfp_fw);
2285 rdev->pfp_fw = NULL;
2286 release_firmware(rdev->me_fw);
2288 release_firmware(rdev->ce_fw);
2290 release_firmware(rdev->mec_fw);
2291 rdev->mec_fw = NULL;
2292 release_firmware(rdev->mec2_fw);
2293 rdev->mec2_fw = NULL;
2294 release_firmware(rdev->rlc_fw);
2295 rdev->rlc_fw = NULL;
2296 release_firmware(rdev->sdma_fw);
2297 rdev->sdma_fw = NULL;
2298 release_firmware(rdev->mc_fw);
2300 release_firmware(rdev->smc_fw);
2301 rdev->smc_fw = NULL;
2310 * cik_tiling_mode_table_init - init the hw tiling table
2312 * @rdev: radeon_device pointer
2314 * Starting with SI, the tiling setup is done globally in a
2315 * set of 32 tiling modes. Rather than selecting each set of
2316 * parameters per surface as on older asics, we just select
2317 * which index in the tiling table we want to use, and the
2318 * surface uses those parameters (CIK).
2320 static void cik_tiling_mode_table_init(struct radeon_device *rdev)
2322 u32 *tile = rdev->config.cik.tile_mode_array;
2323 u32 *macrotile = rdev->config.cik.macrotile_mode_array;
2324 const u32 num_tile_mode_states =
2325 ARRAY_SIZE(rdev->config.cik.tile_mode_array);
2326 const u32 num_secondary_tile_mode_states =
2327 ARRAY_SIZE(rdev->config.cik.macrotile_mode_array);
2328 u32 reg_offset, split_equal_to_row_size;
2329 u32 num_pipe_configs;
2330 u32 num_rbs = rdev->config.cik.max_backends_per_se *
2331 rdev->config.cik.max_shader_engines;
2333 switch (rdev->config.cik.mem_row_size_in_kb) {
2335 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_1KB;
2339 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_2KB;
2342 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_4KB;
2346 num_pipe_configs = rdev->config.cik.max_tile_pipes;
2347 if (num_pipe_configs > 8)
2348 num_pipe_configs = 16;
2350 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
2351 tile[reg_offset] = 0;
2352 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
2353 macrotile[reg_offset] = 0;
2355 switch(num_pipe_configs) {
2357 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2358 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2359 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2360 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B));
2361 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2362 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2363 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2364 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B));
2365 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2366 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2367 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2368 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
2369 tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2370 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2371 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2372 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B));
2373 tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2374 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2375 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2376 TILE_SPLIT(split_equal_to_row_size));
2377 tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2378 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2379 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2380 tile[6] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2381 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2382 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2383 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
2384 tile[7] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2385 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2386 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2387 TILE_SPLIT(split_equal_to_row_size));
2388 tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
2389 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16));
2390 tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2391 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2392 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
2393 tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2394 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2395 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2396 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2397 tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2398 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2399 PIPE_CONFIG(ADDR_SURF_P16_32x32_8x16) |
2400 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2401 tile[12] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2402 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2403 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2404 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2405 tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2406 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2407 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
2408 tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2409 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2410 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2411 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2412 tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2413 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2414 PIPE_CONFIG(ADDR_SURF_P16_32x32_8x16) |
2415 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2416 tile[17] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2417 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2418 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2419 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2420 tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2421 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2422 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
2423 tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2424 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2425 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2426 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2427 tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2428 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2429 PIPE_CONFIG(ADDR_SURF_P16_32x32_8x16) |
2430 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2431 tile[30] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2432 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2433 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2434 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2436 macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2437 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2438 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2439 NUM_BANKS(ADDR_SURF_16_BANK));
2440 macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2441 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2442 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2443 NUM_BANKS(ADDR_SURF_16_BANK));
2444 macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2445 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2446 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2447 NUM_BANKS(ADDR_SURF_16_BANK));
2448 macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2449 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2450 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2451 NUM_BANKS(ADDR_SURF_16_BANK));
2452 macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2453 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2454 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2455 NUM_BANKS(ADDR_SURF_8_BANK));
2456 macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2457 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2458 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2459 NUM_BANKS(ADDR_SURF_4_BANK));
2460 macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2461 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2462 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2463 NUM_BANKS(ADDR_SURF_2_BANK));
2464 macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2465 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2466 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2467 NUM_BANKS(ADDR_SURF_16_BANK));
2468 macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2469 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2470 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2471 NUM_BANKS(ADDR_SURF_16_BANK));
2472 macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2473 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2474 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2475 NUM_BANKS(ADDR_SURF_16_BANK));
2476 macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2477 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2478 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2479 NUM_BANKS(ADDR_SURF_8_BANK));
2480 macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2481 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2482 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2483 NUM_BANKS(ADDR_SURF_4_BANK));
2484 macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2485 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2486 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2487 NUM_BANKS(ADDR_SURF_2_BANK));
2488 macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2489 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2490 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2491 NUM_BANKS(ADDR_SURF_2_BANK));
2493 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
2494 WREG32(GB_TILE_MODE0 + (reg_offset * 4), tile[reg_offset]);
2495 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
2496 WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), macrotile[reg_offset]);
2500 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2501 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2502 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2503 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B));
2504 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2505 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2506 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2507 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B));
2508 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2509 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2510 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2511 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
2512 tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2513 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2514 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2515 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B));
2516 tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2517 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2518 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2519 TILE_SPLIT(split_equal_to_row_size));
2520 tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2521 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2522 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2523 tile[6] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2524 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2525 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2526 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
2527 tile[7] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2528 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2529 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2530 TILE_SPLIT(split_equal_to_row_size));
2531 tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
2532 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16));
2533 tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2534 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2535 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
2536 tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2537 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2538 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2539 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2540 tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2541 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2542 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2543 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2544 tile[12] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2545 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2546 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2547 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2548 tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2549 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2550 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
2551 tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2552 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2553 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2554 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2555 tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2556 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2557 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2558 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2559 tile[17] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2560 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2561 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2562 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2563 tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2564 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2565 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
2566 tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2567 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2568 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2569 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2570 tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2571 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2572 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2573 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2574 tile[30] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2575 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2576 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2577 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2579 macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2580 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2581 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2582 NUM_BANKS(ADDR_SURF_16_BANK));
2583 macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2584 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2585 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2586 NUM_BANKS(ADDR_SURF_16_BANK));
2587 macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2588 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2589 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2590 NUM_BANKS(ADDR_SURF_16_BANK));
2591 macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2592 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2593 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2594 NUM_BANKS(ADDR_SURF_16_BANK));
2595 macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2596 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2597 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2598 NUM_BANKS(ADDR_SURF_8_BANK));
2599 macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2600 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2601 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2602 NUM_BANKS(ADDR_SURF_4_BANK));
2603 macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2604 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2605 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2606 NUM_BANKS(ADDR_SURF_2_BANK));
2607 macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2608 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
2609 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2610 NUM_BANKS(ADDR_SURF_16_BANK));
2611 macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2612 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2613 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2614 NUM_BANKS(ADDR_SURF_16_BANK));
2615 macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2616 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2617 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2618 NUM_BANKS(ADDR_SURF_16_BANK));
2619 macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2620 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2621 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2622 NUM_BANKS(ADDR_SURF_16_BANK));
2623 macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2624 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2625 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2626 NUM_BANKS(ADDR_SURF_8_BANK));
2627 macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2628 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2629 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2630 NUM_BANKS(ADDR_SURF_4_BANK));
2631 macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2632 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2633 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2634 NUM_BANKS(ADDR_SURF_2_BANK));
2636 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
2637 WREG32(GB_TILE_MODE0 + (reg_offset * 4), tile[reg_offset]);
2638 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
2639 WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), macrotile[reg_offset]);
2644 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2645 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2646 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2647 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B));
2648 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2649 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2650 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2651 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B));
2652 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2653 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2654 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2655 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
2656 tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2657 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2658 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2659 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B));
2660 tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2661 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2662 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2663 TILE_SPLIT(split_equal_to_row_size));
2664 tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2665 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2666 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2667 tile[6] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2668 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2669 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2670 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
2671 tile[7] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2672 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2673 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2674 TILE_SPLIT(split_equal_to_row_size));
2675 tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
2676 PIPE_CONFIG(ADDR_SURF_P4_16x16));
2677 tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2678 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2679 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
2680 tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2681 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2682 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2683 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2684 tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2685 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2686 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2687 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2688 tile[12] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2689 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2690 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2691 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2692 tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2693 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2694 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
2695 tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2696 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2697 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2698 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2699 tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2700 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2701 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2702 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2703 tile[17] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2704 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2705 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2706 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2707 tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2708 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2709 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
2710 tile[28] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2711 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2712 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2713 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2714 tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2715 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2716 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2717 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2718 tile[30] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2719 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2720 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2721 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2723 } else if (num_rbs < 4) {
2724 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2725 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2726 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2727 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B));
2728 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2729 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2730 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2731 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B));
2732 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2733 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2734 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2735 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
2736 tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2737 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2738 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2739 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B));
2740 tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2741 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2742 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2743 TILE_SPLIT(split_equal_to_row_size));
2744 tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2745 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2746 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2747 tile[6] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2748 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2749 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2750 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
2751 tile[7] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2752 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2753 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2754 TILE_SPLIT(split_equal_to_row_size));
2755 tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
2756 PIPE_CONFIG(ADDR_SURF_P4_8x16));
2757 tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2758 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2759 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
2760 tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2761 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2762 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2763 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2764 tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2765 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2766 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2767 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2768 tile[12] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2769 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2770 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2771 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2772 tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2773 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2774 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
2775 tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2776 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2777 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2778 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2779 tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2780 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2781 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2782 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2783 tile[17] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2784 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2785 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2786 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2787 tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2788 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2789 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
2790 tile[28] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2791 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2792 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2793 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2794 tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2795 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2796 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2797 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2798 tile[30] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2799 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2800 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2801 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2804 macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2805 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2806 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2807 NUM_BANKS(ADDR_SURF_16_BANK));
2808 macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2809 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2810 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2811 NUM_BANKS(ADDR_SURF_16_BANK));
2812 macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2813 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2814 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2815 NUM_BANKS(ADDR_SURF_16_BANK));
2816 macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2817 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2818 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2819 NUM_BANKS(ADDR_SURF_16_BANK));
2820 macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2821 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2822 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2823 NUM_BANKS(ADDR_SURF_16_BANK));
2824 macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2825 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2826 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2827 NUM_BANKS(ADDR_SURF_8_BANK));
2828 macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2829 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2830 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2831 NUM_BANKS(ADDR_SURF_4_BANK));
2832 macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
2833 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
2834 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2835 NUM_BANKS(ADDR_SURF_16_BANK));
2836 macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
2837 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2838 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2839 NUM_BANKS(ADDR_SURF_16_BANK));
2840 macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2841 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2842 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2843 NUM_BANKS(ADDR_SURF_16_BANK));
2844 macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2845 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2846 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2847 NUM_BANKS(ADDR_SURF_16_BANK));
2848 macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2849 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2850 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2851 NUM_BANKS(ADDR_SURF_16_BANK));
2852 macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2853 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2854 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2855 NUM_BANKS(ADDR_SURF_8_BANK));
2856 macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2857 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2858 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2859 NUM_BANKS(ADDR_SURF_4_BANK));
2861 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
2862 WREG32(GB_TILE_MODE0 + (reg_offset * 4), tile[reg_offset]);
2863 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
2864 WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), macrotile[reg_offset]);
2868 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2869 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2870 PIPE_CONFIG(ADDR_SURF_P2) |
2871 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B));
2872 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2873 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2874 PIPE_CONFIG(ADDR_SURF_P2) |
2875 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B));
2876 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2877 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2878 PIPE_CONFIG(ADDR_SURF_P2) |
2879 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
2880 tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2881 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2882 PIPE_CONFIG(ADDR_SURF_P2) |
2883 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B));
2884 tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2885 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2886 PIPE_CONFIG(ADDR_SURF_P2) |
2887 TILE_SPLIT(split_equal_to_row_size));
2888 tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2889 PIPE_CONFIG(ADDR_SURF_P2) |
2890 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2891 tile[6] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2892 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2893 PIPE_CONFIG(ADDR_SURF_P2) |
2894 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
2895 tile[7] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2896 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2897 PIPE_CONFIG(ADDR_SURF_P2) |
2898 TILE_SPLIT(split_equal_to_row_size));
2899 tile[8] = ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
2900 PIPE_CONFIG(ADDR_SURF_P2);
2901 tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2902 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2903 PIPE_CONFIG(ADDR_SURF_P2));
2904 tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2905 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2906 PIPE_CONFIG(ADDR_SURF_P2) |
2907 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2908 tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2909 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2910 PIPE_CONFIG(ADDR_SURF_P2) |
2911 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2912 tile[12] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2913 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2914 PIPE_CONFIG(ADDR_SURF_P2) |
2915 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2916 tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2917 PIPE_CONFIG(ADDR_SURF_P2) |
2918 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
2919 tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2920 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2921 PIPE_CONFIG(ADDR_SURF_P2) |
2922 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2923 tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2924 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2925 PIPE_CONFIG(ADDR_SURF_P2) |
2926 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2927 tile[17] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2928 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2929 PIPE_CONFIG(ADDR_SURF_P2) |
2930 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2931 tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2932 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2933 PIPE_CONFIG(ADDR_SURF_P2));
2934 tile[28] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2935 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2936 PIPE_CONFIG(ADDR_SURF_P2) |
2937 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2938 tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2939 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2940 PIPE_CONFIG(ADDR_SURF_P2) |
2941 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2942 tile[30] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2943 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2944 PIPE_CONFIG(ADDR_SURF_P2) |
2945 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2947 macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
2948 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2949 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2950 NUM_BANKS(ADDR_SURF_16_BANK));
2951 macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
2952 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2953 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2954 NUM_BANKS(ADDR_SURF_16_BANK));
2955 macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2956 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2957 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2958 NUM_BANKS(ADDR_SURF_16_BANK));
2959 macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2960 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2961 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2962 NUM_BANKS(ADDR_SURF_16_BANK));
2963 macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2964 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2965 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2966 NUM_BANKS(ADDR_SURF_16_BANK));
2967 macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2968 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2969 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2970 NUM_BANKS(ADDR_SURF_16_BANK));
2971 macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2972 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2973 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2974 NUM_BANKS(ADDR_SURF_8_BANK));
2975 macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
2976 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
2977 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2978 NUM_BANKS(ADDR_SURF_16_BANK));
2979 macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
2980 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2981 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2982 NUM_BANKS(ADDR_SURF_16_BANK));
2983 macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
2984 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2985 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2986 NUM_BANKS(ADDR_SURF_16_BANK));
2987 macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
2988 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2989 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2990 NUM_BANKS(ADDR_SURF_16_BANK));
2991 macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2992 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2993 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2994 NUM_BANKS(ADDR_SURF_16_BANK));
2995 macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2996 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2997 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2998 NUM_BANKS(ADDR_SURF_16_BANK));
2999 macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3000 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3001 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3002 NUM_BANKS(ADDR_SURF_8_BANK));
3004 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
3005 WREG32(GB_TILE_MODE0 + (reg_offset * 4), tile[reg_offset]);
3006 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
3007 WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), macrotile[reg_offset]);
3011 DRM_ERROR("unknown num pipe config: 0x%x\n", num_pipe_configs);
3016 * cik_select_se_sh - select which SE, SH to address
3018 * @rdev: radeon_device pointer
3019 * @se_num: shader engine to address
3020 * @sh_num: sh block to address
3022 * Select which SE, SH combinations to address. Certain
3023 * registers are instanced per SE or SH. 0xffffffff means
3024 * broadcast to all SEs or SHs (CIK).
3026 static void cik_select_se_sh(struct radeon_device *rdev,
3027 u32 se_num, u32 sh_num)
3029 u32 data = INSTANCE_BROADCAST_WRITES;
3031 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff))
3032 data |= SH_BROADCAST_WRITES | SE_BROADCAST_WRITES;
3033 else if (se_num == 0xffffffff)
3034 data |= SE_BROADCAST_WRITES | SH_INDEX(sh_num);
3035 else if (sh_num == 0xffffffff)
3036 data |= SH_BROADCAST_WRITES | SE_INDEX(se_num);
3038 data |= SH_INDEX(sh_num) | SE_INDEX(se_num);
3039 WREG32(GRBM_GFX_INDEX, data);
3043 * cik_create_bitmask - create a bitmask
3045 * @bit_width: length of the mask
3047 * create a variable length bit mask (CIK).
3048 * Returns the bitmask.
3050 static u32 cik_create_bitmask(u32 bit_width)
3054 for (i = 0; i < bit_width; i++) {
3062 * cik_get_rb_disabled - computes the mask of disabled RBs
3064 * @rdev: radeon_device pointer
3065 * @max_rb_num_per_se: max RBs (render backends) per SE (shader engine) for the asic
3066 * @sh_per_se: number of SH blocks per SE for the asic
3068 * Calculates the bitmask of disabled RBs (CIK).
3069 * Returns the disabled RB bitmask.
3071 static u32 cik_get_rb_disabled(struct radeon_device *rdev,
3072 u32 max_rb_num_per_se,
3077 data = RREG32(CC_RB_BACKEND_DISABLE);
3079 data &= BACKEND_DISABLE_MASK;
3082 data |= RREG32(GC_USER_RB_BACKEND_DISABLE);
3084 data >>= BACKEND_DISABLE_SHIFT;
3086 mask = cik_create_bitmask(max_rb_num_per_se / sh_per_se);
3092 * cik_setup_rb - setup the RBs on the asic
3094 * @rdev: radeon_device pointer
3095 * @se_num: number of SEs (shader engines) for the asic
3096 * @sh_per_se: number of SH blocks per SE for the asic
3097 * @max_rb_num_per_se: max RBs (render backends) per SE for the asic
3099 * Configures per-SE/SH RB registers (CIK).
3101 static void cik_setup_rb(struct radeon_device *rdev,
3102 u32 se_num, u32 sh_per_se,
3103 u32 max_rb_num_per_se)
3107 u32 disabled_rbs = 0;
3108 u32 enabled_rbs = 0;
3110 for (i = 0; i < se_num; i++) {
3111 for (j = 0; j < sh_per_se; j++) {
3112 cik_select_se_sh(rdev, i, j);
3113 data = cik_get_rb_disabled(rdev, max_rb_num_per_se, sh_per_se);
3114 if (rdev->family == CHIP_HAWAII)
3115 disabled_rbs |= data << ((i * sh_per_se + j) * HAWAII_RB_BITMAP_WIDTH_PER_SH);
3117 disabled_rbs |= data << ((i * sh_per_se + j) * CIK_RB_BITMAP_WIDTH_PER_SH);
3120 cik_select_se_sh(rdev, 0xffffffff, 0xffffffff);
3123 for (i = 0; i < max_rb_num_per_se * se_num; i++) {
3124 if (!(disabled_rbs & mask))
3125 enabled_rbs |= mask;
3129 rdev->config.cik.backend_enable_mask = enabled_rbs;
3131 for (i = 0; i < se_num; i++) {
3132 cik_select_se_sh(rdev, i, 0xffffffff);
3134 for (j = 0; j < sh_per_se; j++) {
3135 switch (enabled_rbs & 3) {
3138 data |= PKR_MAP(RASTER_CONFIG_RB_MAP_3);
3140 data |= PKR_MAP(RASTER_CONFIG_RB_MAP_0);
3143 data |= (RASTER_CONFIG_RB_MAP_0 << (i * sh_per_se + j) * 2);
3146 data |= (RASTER_CONFIG_RB_MAP_3 << (i * sh_per_se + j) * 2);
3150 data |= (RASTER_CONFIG_RB_MAP_2 << (i * sh_per_se + j) * 2);
3155 WREG32(PA_SC_RASTER_CONFIG, data);
3157 cik_select_se_sh(rdev, 0xffffffff, 0xffffffff);
3161 * cik_gpu_init - setup the 3D engine
3163 * @rdev: radeon_device pointer
3165 * Configures the 3D engine and tiling configuration
3166 * registers so that the 3D engine is usable.
3168 static void cik_gpu_init(struct radeon_device *rdev)
3170 u32 gb_addr_config = RREG32(GB_ADDR_CONFIG);
3172 u32 hdp_host_path_cntl;
3176 switch (rdev->family) {
3178 rdev->config.cik.max_shader_engines = 2;
3179 rdev->config.cik.max_tile_pipes = 4;
3180 rdev->config.cik.max_cu_per_sh = 7;
3181 rdev->config.cik.max_sh_per_se = 1;
3182 rdev->config.cik.max_backends_per_se = 2;
3183 rdev->config.cik.max_texture_channel_caches = 4;
3184 rdev->config.cik.max_gprs = 256;
3185 rdev->config.cik.max_gs_threads = 32;
3186 rdev->config.cik.max_hw_contexts = 8;
3188 rdev->config.cik.sc_prim_fifo_size_frontend = 0x20;
3189 rdev->config.cik.sc_prim_fifo_size_backend = 0x100;
3190 rdev->config.cik.sc_hiz_tile_fifo_size = 0x30;
3191 rdev->config.cik.sc_earlyz_tile_fifo_size = 0x130;
3192 gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN;
3195 rdev->config.cik.max_shader_engines = 4;
3196 rdev->config.cik.max_tile_pipes = 16;
3197 rdev->config.cik.max_cu_per_sh = 11;
3198 rdev->config.cik.max_sh_per_se = 1;
3199 rdev->config.cik.max_backends_per_se = 4;
3200 rdev->config.cik.max_texture_channel_caches = 16;
3201 rdev->config.cik.max_gprs = 256;
3202 rdev->config.cik.max_gs_threads = 32;
3203 rdev->config.cik.max_hw_contexts = 8;
3205 rdev->config.cik.sc_prim_fifo_size_frontend = 0x20;
3206 rdev->config.cik.sc_prim_fifo_size_backend = 0x100;
3207 rdev->config.cik.sc_hiz_tile_fifo_size = 0x30;
3208 rdev->config.cik.sc_earlyz_tile_fifo_size = 0x130;
3209 gb_addr_config = HAWAII_GB_ADDR_CONFIG_GOLDEN;
3212 rdev->config.cik.max_shader_engines = 1;
3213 rdev->config.cik.max_tile_pipes = 4;
3214 rdev->config.cik.max_cu_per_sh = 8;
3215 rdev->config.cik.max_backends_per_se = 2;
3216 rdev->config.cik.max_sh_per_se = 1;
3217 rdev->config.cik.max_texture_channel_caches = 4;
3218 rdev->config.cik.max_gprs = 256;
3219 rdev->config.cik.max_gs_threads = 16;
3220 rdev->config.cik.max_hw_contexts = 8;
3222 rdev->config.cik.sc_prim_fifo_size_frontend = 0x20;
3223 rdev->config.cik.sc_prim_fifo_size_backend = 0x100;
3224 rdev->config.cik.sc_hiz_tile_fifo_size = 0x30;
3225 rdev->config.cik.sc_earlyz_tile_fifo_size = 0x130;
3226 gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN;
3231 rdev->config.cik.max_shader_engines = 1;
3232 rdev->config.cik.max_tile_pipes = 2;
3233 rdev->config.cik.max_cu_per_sh = 2;
3234 rdev->config.cik.max_sh_per_se = 1;
3235 rdev->config.cik.max_backends_per_se = 1;
3236 rdev->config.cik.max_texture_channel_caches = 2;
3237 rdev->config.cik.max_gprs = 256;
3238 rdev->config.cik.max_gs_threads = 16;
3239 rdev->config.cik.max_hw_contexts = 8;
3241 rdev->config.cik.sc_prim_fifo_size_frontend = 0x20;
3242 rdev->config.cik.sc_prim_fifo_size_backend = 0x100;
3243 rdev->config.cik.sc_hiz_tile_fifo_size = 0x30;
3244 rdev->config.cik.sc_earlyz_tile_fifo_size = 0x130;
3245 gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN;
3249 /* Initialize HDP */
3250 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
3251 WREG32((0x2c14 + j), 0x00000000);
3252 WREG32((0x2c18 + j), 0x00000000);
3253 WREG32((0x2c1c + j), 0x00000000);
3254 WREG32((0x2c20 + j), 0x00000000);
3255 WREG32((0x2c24 + j), 0x00000000);
3258 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
3259 WREG32(SRBM_INT_CNTL, 0x1);
3260 WREG32(SRBM_INT_ACK, 0x1);
3262 WREG32(BIF_FB_EN, FB_READ_EN | FB_WRITE_EN);
3264 RREG32(MC_SHARED_CHMAP);
3265 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
3267 rdev->config.cik.num_tile_pipes = rdev->config.cik.max_tile_pipes;
3268 rdev->config.cik.mem_max_burst_length_bytes = 256;
3269 tmp = (mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT;
3270 rdev->config.cik.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
3271 if (rdev->config.cik.mem_row_size_in_kb > 4)
3272 rdev->config.cik.mem_row_size_in_kb = 4;
3273 /* XXX use MC settings? */
3274 rdev->config.cik.shader_engine_tile_size = 32;
3275 rdev->config.cik.num_gpus = 1;
3276 rdev->config.cik.multi_gpu_tile_size = 64;
3278 /* fix up row size */
3279 gb_addr_config &= ~ROW_SIZE_MASK;
3280 switch (rdev->config.cik.mem_row_size_in_kb) {
3283 gb_addr_config |= ROW_SIZE(0);
3286 gb_addr_config |= ROW_SIZE(1);
3289 gb_addr_config |= ROW_SIZE(2);
3293 /* setup tiling info dword. gb_addr_config is not adequate since it does
3294 * not have bank info, so create a custom tiling dword.
3295 * bits 3:0 num_pipes
3296 * bits 7:4 num_banks
3297 * bits 11:8 group_size
3298 * bits 15:12 row_size
3300 rdev->config.cik.tile_config = 0;
3301 switch (rdev->config.cik.num_tile_pipes) {
3303 rdev->config.cik.tile_config |= (0 << 0);
3306 rdev->config.cik.tile_config |= (1 << 0);
3309 rdev->config.cik.tile_config |= (2 << 0);
3313 /* XXX what about 12? */
3314 rdev->config.cik.tile_config |= (3 << 0);
3317 rdev->config.cik.tile_config |=
3318 ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) << 4;
3319 rdev->config.cik.tile_config |=
3320 ((gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT) << 8;
3321 rdev->config.cik.tile_config |=
3322 ((gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT) << 12;
3324 WREG32(GB_ADDR_CONFIG, gb_addr_config);
3325 WREG32(HDP_ADDR_CONFIG, gb_addr_config);
3326 WREG32(DMIF_ADDR_CALC, gb_addr_config);
3327 WREG32(SDMA0_TILING_CONFIG + SDMA0_REGISTER_OFFSET, gb_addr_config & 0x70);
3328 WREG32(SDMA0_TILING_CONFIG + SDMA1_REGISTER_OFFSET, gb_addr_config & 0x70);
3329 WREG32(UVD_UDEC_ADDR_CONFIG, gb_addr_config);
3330 WREG32(UVD_UDEC_DB_ADDR_CONFIG, gb_addr_config);
3331 WREG32(UVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config);
3333 cik_tiling_mode_table_init(rdev);
3335 cik_setup_rb(rdev, rdev->config.cik.max_shader_engines,
3336 rdev->config.cik.max_sh_per_se,
3337 rdev->config.cik.max_backends_per_se);
3339 rdev->config.cik.active_cus = 0;
3340 for (i = 0; i < rdev->config.cik.max_shader_engines; i++) {
3341 for (j = 0; j < rdev->config.cik.max_sh_per_se; j++) {
3342 rdev->config.cik.active_cus +=
3343 hweight32(cik_get_cu_active_bitmap(rdev, i, j));
3347 /* set HW defaults for 3D engine */
3348 WREG32(CP_MEQ_THRESHOLDS, MEQ1_START(0x30) | MEQ2_START(0x60));
3350 WREG32(SX_DEBUG_1, 0x20);
3352 WREG32(TA_CNTL_AUX, 0x00010000);
3354 tmp = RREG32(SPI_CONFIG_CNTL);
3356 WREG32(SPI_CONFIG_CNTL, tmp);
3358 WREG32(SQ_CONFIG, 1);
3360 WREG32(DB_DEBUG, 0);
3362 tmp = RREG32(DB_DEBUG2) & ~0xf00fffff;
3364 WREG32(DB_DEBUG2, tmp);
3366 tmp = RREG32(DB_DEBUG3) & ~0x0002021c;
3368 WREG32(DB_DEBUG3, tmp);
3370 tmp = RREG32(CB_HW_CONTROL) & ~0x00010000;
3372 WREG32(CB_HW_CONTROL, tmp);
3374 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));
3376 WREG32(PA_SC_FIFO_SIZE, (SC_FRONTEND_PRIM_FIFO_SIZE(rdev->config.cik.sc_prim_fifo_size_frontend) |
3377 SC_BACKEND_PRIM_FIFO_SIZE(rdev->config.cik.sc_prim_fifo_size_backend) |
3378 SC_HIZ_TILE_FIFO_SIZE(rdev->config.cik.sc_hiz_tile_fifo_size) |
3379 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.cik.sc_earlyz_tile_fifo_size)));
3381 WREG32(VGT_NUM_INSTANCES, 1);
3383 WREG32(CP_PERFMON_CNTL, 0);
3385 WREG32(SQ_CONFIG, 0);
3387 WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
3388 FORCE_EOV_MAX_REZ_CNT(255)));
3390 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC) |
3391 AUTO_INVLD_EN(ES_AND_GS_AUTO));
3393 WREG32(VGT_GS_VERTEX_REUSE, 16);
3394 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
3396 tmp = RREG32(HDP_MISC_CNTL);
3397 tmp |= HDP_FLUSH_INVALIDATE_CACHE;
3398 WREG32(HDP_MISC_CNTL, tmp);
3400 hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
3401 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
3403 WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));
3404 WREG32(PA_SC_ENHANCE, ENABLE_PA_SC_OUT_OF_ORDER);
3410 * GPU scratch registers helpers function.
3413 * cik_scratch_init - setup driver info for CP scratch regs
3415 * @rdev: radeon_device pointer
3417 * Set up the number and offset of the CP scratch registers.
3418 * NOTE: use of CP scratch registers is a legacy inferface and
3419 * is not used by default on newer asics (r6xx+). On newer asics,
3420 * memory buffers are used for fences rather than scratch regs.
3422 static void cik_scratch_init(struct radeon_device *rdev)
3426 rdev->scratch.num_reg = 7;
3427 rdev->scratch.reg_base = SCRATCH_REG0;
3428 for (i = 0; i < rdev->scratch.num_reg; i++) {
3429 rdev->scratch.free[i] = true;
3430 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);
3435 * cik_ring_test - basic gfx ring test
3437 * @rdev: radeon_device pointer
3438 * @ring: radeon_ring structure holding ring information
3440 * Allocate a scratch register and write to it using the gfx ring (CIK).
3441 * Provides a basic gfx ring test to verify that the ring is working.
3442 * Used by cik_cp_gfx_resume();
3443 * Returns 0 on success, error on failure.
3445 int cik_ring_test(struct radeon_device *rdev, struct radeon_ring *ring)
3452 r = radeon_scratch_get(rdev, &scratch);
3454 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
3457 WREG32(scratch, 0xCAFEDEAD);
3458 r = radeon_ring_lock(rdev, ring, 3);
3460 DRM_ERROR("radeon: cp failed to lock ring %d (%d).\n", ring->idx, r);
3461 radeon_scratch_free(rdev, scratch);
3464 radeon_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
3465 radeon_ring_write(ring, ((scratch - PACKET3_SET_UCONFIG_REG_START) >> 2));
3466 radeon_ring_write(ring, 0xDEADBEEF);
3467 radeon_ring_unlock_commit(rdev, ring, false);
3469 for (i = 0; i < rdev->usec_timeout; i++) {
3470 tmp = RREG32(scratch);
3471 if (tmp == 0xDEADBEEF)
3475 if (i < rdev->usec_timeout) {
3476 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
3478 DRM_ERROR("radeon: ring %d test failed (scratch(0x%04X)=0x%08X)\n",
3479 ring->idx, scratch, tmp);
3482 radeon_scratch_free(rdev, scratch);
3487 * cik_hdp_flush_cp_ring_emit - emit an hdp flush on the cp
3489 * @rdev: radeon_device pointer
3490 * @ridx: radeon ring index
3492 * Emits an hdp flush on the cp.
3494 static void cik_hdp_flush_cp_ring_emit(struct radeon_device *rdev,
3497 struct radeon_ring *ring = &rdev->ring[ridx];
3500 switch (ring->idx) {
3501 case CAYMAN_RING_TYPE_CP1_INDEX:
3502 case CAYMAN_RING_TYPE_CP2_INDEX:
3506 ref_and_mask = CP2 << ring->pipe;
3509 ref_and_mask = CP6 << ring->pipe;
3515 case RADEON_RING_TYPE_GFX_INDEX:
3520 radeon_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
3521 radeon_ring_write(ring, (WAIT_REG_MEM_OPERATION(1) | /* write, wait, write */
3522 WAIT_REG_MEM_FUNCTION(3) | /* == */
3523 WAIT_REG_MEM_ENGINE(1))); /* pfp */
3524 radeon_ring_write(ring, GPU_HDP_FLUSH_REQ >> 2);
3525 radeon_ring_write(ring, GPU_HDP_FLUSH_DONE >> 2);
3526 radeon_ring_write(ring, ref_and_mask);
3527 radeon_ring_write(ring, ref_and_mask);
3528 radeon_ring_write(ring, 0x20); /* poll interval */
3532 * cik_fence_gfx_ring_emit - emit a fence on the gfx ring
3534 * @rdev: radeon_device pointer
3535 * @fence: radeon fence object
3537 * Emits a fence sequnce number on the gfx ring and flushes
3540 void cik_fence_gfx_ring_emit(struct radeon_device *rdev,
3541 struct radeon_fence *fence)
3543 struct radeon_ring *ring = &rdev->ring[fence->ring];
3544 u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
3546 /* Workaround for cache flush problems. First send a dummy EOP
3547 * event down the pipe with seq one below.
3549 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
3550 radeon_ring_write(ring, (EOP_TCL1_ACTION_EN |
3552 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
3554 radeon_ring_write(ring, addr & 0xfffffffc);
3555 radeon_ring_write(ring, (upper_32_bits(addr) & 0xffff) |
3556 DATA_SEL(1) | INT_SEL(0));
3557 radeon_ring_write(ring, fence->seq - 1);
3558 radeon_ring_write(ring, 0);
3560 /* Then send the real EOP event down the pipe. */
3561 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
3562 radeon_ring_write(ring, (EOP_TCL1_ACTION_EN |
3564 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
3566 radeon_ring_write(ring, addr & 0xfffffffc);
3567 radeon_ring_write(ring, (upper_32_bits(addr) & 0xffff) | DATA_SEL(1) | INT_SEL(2));
3568 radeon_ring_write(ring, fence->seq);
3569 radeon_ring_write(ring, 0);
3573 * cik_fence_compute_ring_emit - emit a fence on the compute ring
3575 * @rdev: radeon_device pointer
3576 * @fence: radeon fence object
3578 * Emits a fence sequnce number on the compute ring and flushes
3581 void cik_fence_compute_ring_emit(struct radeon_device *rdev,
3582 struct radeon_fence *fence)
3584 struct radeon_ring *ring = &rdev->ring[fence->ring];
3585 u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
3587 /* RELEASE_MEM - flush caches, send int */
3588 radeon_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 5));
3589 radeon_ring_write(ring, (EOP_TCL1_ACTION_EN |
3591 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
3593 radeon_ring_write(ring, DATA_SEL(1) | INT_SEL(2));
3594 radeon_ring_write(ring, addr & 0xfffffffc);
3595 radeon_ring_write(ring, upper_32_bits(addr));
3596 radeon_ring_write(ring, fence->seq);
3597 radeon_ring_write(ring, 0);
3601 * cik_semaphore_ring_emit - emit a semaphore on the CP ring
3603 * @rdev: radeon_device pointer
3604 * @ring: radeon ring buffer object
3605 * @semaphore: radeon semaphore object
3606 * @emit_wait: Is this a sempahore wait?
3608 * Emits a semaphore signal/wait packet to the CP ring and prevents the PFP
3609 * from running ahead of semaphore waits.
3611 bool cik_semaphore_ring_emit(struct radeon_device *rdev,
3612 struct radeon_ring *ring,
3613 struct radeon_semaphore *semaphore,
3616 uint64_t addr = semaphore->gpu_addr;
3617 unsigned sel = emit_wait ? PACKET3_SEM_SEL_WAIT : PACKET3_SEM_SEL_SIGNAL;
3619 radeon_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 1));
3620 radeon_ring_write(ring, lower_32_bits(addr));
3621 radeon_ring_write(ring, (upper_32_bits(addr) & 0xffff) | sel);
3623 if (emit_wait && ring->idx == RADEON_RING_TYPE_GFX_INDEX) {
3624 /* Prevent the PFP from running ahead of the semaphore wait */
3625 radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
3626 radeon_ring_write(ring, 0x0);
3633 * cik_copy_cpdma - copy pages using the CP DMA engine
3635 * @rdev: radeon_device pointer
3636 * @src_offset: src GPU address
3637 * @dst_offset: dst GPU address
3638 * @num_gpu_pages: number of GPU pages to xfer
3639 * @resv: reservation object to sync to
3641 * Copy GPU paging using the CP DMA engine (CIK+).
3642 * Used by the radeon ttm implementation to move pages if
3643 * registered as the asic copy callback.
3645 struct radeon_fence *cik_copy_cpdma(struct radeon_device *rdev,
3646 uint64_t src_offset, uint64_t dst_offset,
3647 unsigned num_gpu_pages,
3648 struct dma_resv *resv)
3650 struct radeon_fence *fence;
3651 struct radeon_sync sync;
3652 int ring_index = rdev->asic->copy.blit_ring_index;
3653 struct radeon_ring *ring = &rdev->ring[ring_index];
3654 u32 size_in_bytes, cur_size_in_bytes, control;
3658 radeon_sync_create(&sync);
3660 size_in_bytes = (num_gpu_pages << RADEON_GPU_PAGE_SHIFT);
3661 num_loops = DIV_ROUND_UP(size_in_bytes, 0x1fffff);
3662 r = radeon_ring_lock(rdev, ring, num_loops * 7 + 18);
3664 DRM_ERROR("radeon: moving bo (%d).\n", r);
3665 radeon_sync_free(rdev, &sync, NULL);
3669 radeon_sync_resv(rdev, &sync, resv, false);
3670 radeon_sync_rings(rdev, &sync, ring->idx);
3672 for (i = 0; i < num_loops; i++) {
3673 cur_size_in_bytes = size_in_bytes;
3674 if (cur_size_in_bytes > 0x1fffff)
3675 cur_size_in_bytes = 0x1fffff;
3676 size_in_bytes -= cur_size_in_bytes;
3678 if (size_in_bytes == 0)
3679 control |= PACKET3_DMA_DATA_CP_SYNC;
3680 radeon_ring_write(ring, PACKET3(PACKET3_DMA_DATA, 5));
3681 radeon_ring_write(ring, control);
3682 radeon_ring_write(ring, lower_32_bits(src_offset));
3683 radeon_ring_write(ring, upper_32_bits(src_offset));
3684 radeon_ring_write(ring, lower_32_bits(dst_offset));
3685 radeon_ring_write(ring, upper_32_bits(dst_offset));
3686 radeon_ring_write(ring, cur_size_in_bytes);
3687 src_offset += cur_size_in_bytes;
3688 dst_offset += cur_size_in_bytes;
3691 r = radeon_fence_emit(rdev, &fence, ring->idx);
3693 radeon_ring_unlock_undo(rdev, ring);
3694 radeon_sync_free(rdev, &sync, NULL);
3698 radeon_ring_unlock_commit(rdev, ring, false);
3699 radeon_sync_free(rdev, &sync, fence);
3708 * cik_ring_ib_execute - emit an IB (Indirect Buffer) on the gfx ring
3710 * @rdev: radeon_device pointer
3711 * @ib: radeon indirect buffer object
3713 * Emits a DE (drawing engine) or CE (constant engine) IB
3714 * on the gfx ring. IBs are usually generated by userspace
3715 * acceleration drivers and submitted to the kernel for
3716 * scheduling on the ring. This function schedules the IB
3717 * on the gfx ring for execution by the GPU.
3719 void cik_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
3721 struct radeon_ring *ring = &rdev->ring[ib->ring];
3722 unsigned vm_id = ib->vm ? ib->vm->ids[ib->ring].id : 0;
3723 u32 header, control = INDIRECT_BUFFER_VALID;
3725 if (ib->is_const_ib) {
3726 /* set switch buffer packet before const IB */
3727 radeon_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
3728 radeon_ring_write(ring, 0);
3730 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
3733 if (ring->rptr_save_reg) {
3734 next_rptr = ring->wptr + 3 + 4;
3735 radeon_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
3736 radeon_ring_write(ring, ((ring->rptr_save_reg -
3737 PACKET3_SET_UCONFIG_REG_START) >> 2));
3738 radeon_ring_write(ring, next_rptr);
3739 } else if (rdev->wb.enabled) {
3740 next_rptr = ring->wptr + 5 + 4;
3741 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3742 radeon_ring_write(ring, WRITE_DATA_DST_SEL(1));
3743 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
3744 radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr));
3745 radeon_ring_write(ring, next_rptr);
3748 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
3751 control |= ib->length_dw | (vm_id << 24);
3753 radeon_ring_write(ring, header);
3754 radeon_ring_write(ring, (ib->gpu_addr & 0xFFFFFFFC));
3755 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
3756 radeon_ring_write(ring, control);
3760 * cik_ib_test - basic gfx ring IB test
3762 * @rdev: radeon_device pointer
3763 * @ring: radeon_ring structure holding ring information
3765 * Allocate an IB and execute it on the gfx ring (CIK).
3766 * Provides a basic gfx ring test to verify that IBs are working.
3767 * Returns 0 on success, error on failure.
3769 int cik_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
3771 struct radeon_ib ib;
3777 r = radeon_scratch_get(rdev, &scratch);
3779 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
3782 WREG32(scratch, 0xCAFEDEAD);
3783 r = radeon_ib_get(rdev, ring->idx, &ib, NULL, 256);
3785 DRM_ERROR("radeon: failed to get ib (%d).\n", r);
3786 radeon_scratch_free(rdev, scratch);
3789 ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1);
3790 ib.ptr[1] = ((scratch - PACKET3_SET_UCONFIG_REG_START) >> 2);
3791 ib.ptr[2] = 0xDEADBEEF;
3793 r = radeon_ib_schedule(rdev, &ib, NULL, false);
3795 radeon_scratch_free(rdev, scratch);
3796 radeon_ib_free(rdev, &ib);
3797 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
3800 r = radeon_fence_wait_timeout(ib.fence, false, usecs_to_jiffies(
3801 RADEON_USEC_IB_TEST_TIMEOUT));
3803 DRM_ERROR("radeon: fence wait failed (%d).\n", r);
3804 radeon_scratch_free(rdev, scratch);
3805 radeon_ib_free(rdev, &ib);
3807 } else if (r == 0) {
3808 DRM_ERROR("radeon: fence wait timed out.\n");
3809 radeon_scratch_free(rdev, scratch);
3810 radeon_ib_free(rdev, &ib);
3814 for (i = 0; i < rdev->usec_timeout; i++) {
3815 tmp = RREG32(scratch);
3816 if (tmp == 0xDEADBEEF)
3820 if (i < rdev->usec_timeout) {
3821 DRM_INFO("ib test on ring %d succeeded in %u usecs\n", ib.fence->ring, i);
3823 DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n",
3827 radeon_scratch_free(rdev, scratch);
3828 radeon_ib_free(rdev, &ib);
3834 * On CIK, gfx and compute now have independant command processors.
3837 * Gfx consists of a single ring and can process both gfx jobs and
3838 * compute jobs. The gfx CP consists of three microengines (ME):
3839 * PFP - Pre-Fetch Parser
3841 * CE - Constant Engine
3842 * The PFP and ME make up what is considered the Drawing Engine (DE).
3843 * The CE is an asynchronous engine used for updating buffer desciptors
3844 * used by the DE so that they can be loaded into cache in parallel
3845 * while the DE is processing state update packets.
3848 * The compute CP consists of two microengines (ME):
3849 * MEC1 - Compute MicroEngine 1
3850 * MEC2 - Compute MicroEngine 2
3851 * Each MEC supports 4 compute pipes and each pipe supports 8 queues.
3852 * The queues are exposed to userspace and are programmed directly
3853 * by the compute runtime.
3856 * cik_cp_gfx_enable - enable/disable the gfx CP MEs
3858 * @rdev: radeon_device pointer
3859 * @enable: enable or disable the MEs
3861 * Halts or unhalts the gfx MEs.
3863 static void cik_cp_gfx_enable(struct radeon_device *rdev, bool enable)
3866 WREG32(CP_ME_CNTL, 0);
3868 if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX)
3869 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
3870 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT));
3871 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
3877 * cik_cp_gfx_load_microcode - load the gfx CP ME ucode
3879 * @rdev: radeon_device pointer
3881 * Loads the gfx PFP, ME, and CE ucode.
3882 * Returns 0 for success, -EINVAL if the ucode is not available.
3884 static int cik_cp_gfx_load_microcode(struct radeon_device *rdev)
3888 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->ce_fw)
3891 cik_cp_gfx_enable(rdev, false);
3894 const struct gfx_firmware_header_v1_0 *pfp_hdr =
3895 (const struct gfx_firmware_header_v1_0 *)rdev->pfp_fw->data;
3896 const struct gfx_firmware_header_v1_0 *ce_hdr =
3897 (const struct gfx_firmware_header_v1_0 *)rdev->ce_fw->data;
3898 const struct gfx_firmware_header_v1_0 *me_hdr =
3899 (const struct gfx_firmware_header_v1_0 *)rdev->me_fw->data;
3900 const __le32 *fw_data;
3903 radeon_ucode_print_gfx_hdr(&pfp_hdr->header);
3904 radeon_ucode_print_gfx_hdr(&ce_hdr->header);
3905 radeon_ucode_print_gfx_hdr(&me_hdr->header);
3908 fw_data = (const __le32 *)
3909 (rdev->pfp_fw->data + le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
3910 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4;
3911 WREG32(CP_PFP_UCODE_ADDR, 0);
3912 for (i = 0; i < fw_size; i++)
3913 WREG32(CP_PFP_UCODE_DATA, le32_to_cpup(fw_data++));
3914 WREG32(CP_PFP_UCODE_ADDR, le32_to_cpu(pfp_hdr->header.ucode_version));
3917 fw_data = (const __le32 *)
3918 (rdev->ce_fw->data + le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
3919 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4;
3920 WREG32(CP_CE_UCODE_ADDR, 0);
3921 for (i = 0; i < fw_size; i++)
3922 WREG32(CP_CE_UCODE_DATA, le32_to_cpup(fw_data++));
3923 WREG32(CP_CE_UCODE_ADDR, le32_to_cpu(ce_hdr->header.ucode_version));
3926 fw_data = (const __be32 *)
3927 (rdev->me_fw->data + le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
3928 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4;
3929 WREG32(CP_ME_RAM_WADDR, 0);
3930 for (i = 0; i < fw_size; i++)
3931 WREG32(CP_ME_RAM_DATA, le32_to_cpup(fw_data++));
3932 WREG32(CP_ME_RAM_WADDR, le32_to_cpu(me_hdr->header.ucode_version));
3933 WREG32(CP_ME_RAM_RADDR, le32_to_cpu(me_hdr->header.ucode_version));
3935 const __be32 *fw_data;
3938 fw_data = (const __be32 *)rdev->pfp_fw->data;
3939 WREG32(CP_PFP_UCODE_ADDR, 0);
3940 for (i = 0; i < CIK_PFP_UCODE_SIZE; i++)
3941 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
3942 WREG32(CP_PFP_UCODE_ADDR, 0);
3945 fw_data = (const __be32 *)rdev->ce_fw->data;
3946 WREG32(CP_CE_UCODE_ADDR, 0);
3947 for (i = 0; i < CIK_CE_UCODE_SIZE; i++)
3948 WREG32(CP_CE_UCODE_DATA, be32_to_cpup(fw_data++));
3949 WREG32(CP_CE_UCODE_ADDR, 0);
3952 fw_data = (const __be32 *)rdev->me_fw->data;
3953 WREG32(CP_ME_RAM_WADDR, 0);
3954 for (i = 0; i < CIK_ME_UCODE_SIZE; i++)
3955 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
3956 WREG32(CP_ME_RAM_WADDR, 0);
3963 * cik_cp_gfx_start - start the gfx ring
3965 * @rdev: radeon_device pointer
3967 * Enables the ring and loads the clear state context and other
3968 * packets required to init the ring.
3969 * Returns 0 for success, error for failure.
3971 static int cik_cp_gfx_start(struct radeon_device *rdev)
3973 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
3977 WREG32(CP_MAX_CONTEXT, rdev->config.cik.max_hw_contexts - 1);
3978 WREG32(CP_ENDIAN_SWAP, 0);
3979 WREG32(CP_DEVICE_ID, 1);
3981 cik_cp_gfx_enable(rdev, true);
3983 r = radeon_ring_lock(rdev, ring, cik_default_size + 17);
3985 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
3989 /* init the CE partitions. CE only used for gfx on CIK */
3990 radeon_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
3991 radeon_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
3992 radeon_ring_write(ring, 0x8000);
3993 radeon_ring_write(ring, 0x8000);
3995 /* setup clear context state */
3996 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
3997 radeon_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
3999 radeon_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
4000 radeon_ring_write(ring, 0x80000000);
4001 radeon_ring_write(ring, 0x80000000);
4003 for (i = 0; i < cik_default_size; i++)
4004 radeon_ring_write(ring, cik_default_state[i]);
4006 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
4007 radeon_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
4009 /* set clear context state */
4010 radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
4011 radeon_ring_write(ring, 0);
4013 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
4014 radeon_ring_write(ring, 0x00000316);
4015 radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
4016 radeon_ring_write(ring, 0x00000010); /* VGT_OUT_DEALLOC_CNTL */
4018 radeon_ring_unlock_commit(rdev, ring, false);
4024 * cik_cp_gfx_fini - stop the gfx ring
4026 * @rdev: radeon_device pointer
4028 * Stop the gfx ring and tear down the driver ring
4031 static void cik_cp_gfx_fini(struct radeon_device *rdev)
4033 cik_cp_gfx_enable(rdev, false);
4034 radeon_ring_fini(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
4038 * cik_cp_gfx_resume - setup the gfx ring buffer registers
4040 * @rdev: radeon_device pointer
4042 * Program the location and size of the gfx ring buffer
4043 * and test it to make sure it's working.
4044 * Returns 0 for success, error for failure.
4046 static int cik_cp_gfx_resume(struct radeon_device *rdev)
4048 struct radeon_ring *ring;
4054 WREG32(CP_SEM_WAIT_TIMER, 0x0);
4055 if (rdev->family != CHIP_HAWAII)
4056 WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);
4058 /* Set the write pointer delay */
4059 WREG32(CP_RB_WPTR_DELAY, 0);
4061 /* set the RB to use vmid 0 */
4062 WREG32(CP_RB_VMID, 0);
4064 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
4066 /* ring 0 - compute and gfx */
4067 /* Set ring buffer size */
4068 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
4069 rb_bufsz = order_base_2(ring->ring_size / 8);
4070 tmp = (order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
4072 tmp |= BUF_SWAP_32BIT;
4074 WREG32(CP_RB0_CNTL, tmp);
4076 /* Initialize the ring buffer's read and write pointers */
4077 WREG32(CP_RB0_CNTL, tmp | RB_RPTR_WR_ENA);
4079 WREG32(CP_RB0_WPTR, ring->wptr);
4081 /* set the wb address wether it's enabled or not */
4082 WREG32(CP_RB0_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC);
4083 WREG32(CP_RB0_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
4085 /* scratch register shadowing is no longer supported */
4086 WREG32(SCRATCH_UMSK, 0);
4088 if (!rdev->wb.enabled)
4089 tmp |= RB_NO_UPDATE;
4092 WREG32(CP_RB0_CNTL, tmp);
4094 rb_addr = ring->gpu_addr >> 8;
4095 WREG32(CP_RB0_BASE, rb_addr);
4096 WREG32(CP_RB0_BASE_HI, upper_32_bits(rb_addr));
4098 /* start the ring */
4099 cik_cp_gfx_start(rdev);
4100 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = true;
4101 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
4103 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
4107 if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX)
4108 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
4113 u32 cik_gfx_get_rptr(struct radeon_device *rdev,
4114 struct radeon_ring *ring)
4118 if (rdev->wb.enabled)
4119 rptr = rdev->wb.wb[ring->rptr_offs/4];
4121 rptr = RREG32(CP_RB0_RPTR);
4126 u32 cik_gfx_get_wptr(struct radeon_device *rdev,
4127 struct radeon_ring *ring)
4129 return RREG32(CP_RB0_WPTR);
4132 void cik_gfx_set_wptr(struct radeon_device *rdev,
4133 struct radeon_ring *ring)
4135 WREG32(CP_RB0_WPTR, ring->wptr);
4136 (void)RREG32(CP_RB0_WPTR);
4139 u32 cik_compute_get_rptr(struct radeon_device *rdev,
4140 struct radeon_ring *ring)
4144 if (rdev->wb.enabled) {
4145 rptr = rdev->wb.wb[ring->rptr_offs/4];
4147 mutex_lock(&rdev->srbm_mutex);
4148 cik_srbm_select(rdev, ring->me, ring->pipe, ring->queue, 0);
4149 rptr = RREG32(CP_HQD_PQ_RPTR);
4150 cik_srbm_select(rdev, 0, 0, 0, 0);
4151 mutex_unlock(&rdev->srbm_mutex);
4157 u32 cik_compute_get_wptr(struct radeon_device *rdev,
4158 struct radeon_ring *ring)
4162 if (rdev->wb.enabled) {
4163 /* XXX check if swapping is necessary on BE */
4164 wptr = rdev->wb.wb[ring->wptr_offs/4];
4166 mutex_lock(&rdev->srbm_mutex);
4167 cik_srbm_select(rdev, ring->me, ring->pipe, ring->queue, 0);
4168 wptr = RREG32(CP_HQD_PQ_WPTR);
4169 cik_srbm_select(rdev, 0, 0, 0, 0);
4170 mutex_unlock(&rdev->srbm_mutex);
4176 void cik_compute_set_wptr(struct radeon_device *rdev,
4177 struct radeon_ring *ring)
4179 /* XXX check if swapping is necessary on BE */
4180 rdev->wb.wb[ring->wptr_offs/4] = ring->wptr;
4181 WDOORBELL32(ring->doorbell_index, ring->wptr);
4184 static void cik_compute_stop(struct radeon_device *rdev,
4185 struct radeon_ring *ring)
4189 cik_srbm_select(rdev, ring->me, ring->pipe, ring->queue, 0);
4190 /* Disable wptr polling. */
4191 tmp = RREG32(CP_PQ_WPTR_POLL_CNTL);
4192 tmp &= ~WPTR_POLL_EN;
4193 WREG32(CP_PQ_WPTR_POLL_CNTL, tmp);
4195 if (RREG32(CP_HQD_ACTIVE) & 1) {
4196 WREG32(CP_HQD_DEQUEUE_REQUEST, 1);
4197 for (j = 0; j < rdev->usec_timeout; j++) {
4198 if (!(RREG32(CP_HQD_ACTIVE) & 1))
4202 WREG32(CP_HQD_DEQUEUE_REQUEST, 0);
4203 WREG32(CP_HQD_PQ_RPTR, 0);
4204 WREG32(CP_HQD_PQ_WPTR, 0);
4206 cik_srbm_select(rdev, 0, 0, 0, 0);
4210 * cik_cp_compute_enable - enable/disable the compute CP MEs
4212 * @rdev: radeon_device pointer
4213 * @enable: enable or disable the MEs
4215 * Halts or unhalts the compute MEs.
4217 static void cik_cp_compute_enable(struct radeon_device *rdev, bool enable)
4220 WREG32(CP_MEC_CNTL, 0);
4223 * To make hibernation reliable we need to clear compute ring
4224 * configuration before halting the compute ring.
4226 mutex_lock(&rdev->srbm_mutex);
4227 cik_compute_stop(rdev,&rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX]);
4228 cik_compute_stop(rdev,&rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX]);
4229 mutex_unlock(&rdev->srbm_mutex);
4231 WREG32(CP_MEC_CNTL, (MEC_ME1_HALT | MEC_ME2_HALT));
4232 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;
4233 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;
4239 * cik_cp_compute_load_microcode - load the compute CP ME ucode
4241 * @rdev: radeon_device pointer
4243 * Loads the compute MEC1&2 ucode.
4244 * Returns 0 for success, -EINVAL if the ucode is not available.
4246 static int cik_cp_compute_load_microcode(struct radeon_device *rdev)
4253 cik_cp_compute_enable(rdev, false);
4256 const struct gfx_firmware_header_v1_0 *mec_hdr =
4257 (const struct gfx_firmware_header_v1_0 *)rdev->mec_fw->data;
4258 const __le32 *fw_data;
4261 radeon_ucode_print_gfx_hdr(&mec_hdr->header);
4264 fw_data = (const __le32 *)
4265 (rdev->mec_fw->data + le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
4266 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes) / 4;
4267 WREG32(CP_MEC_ME1_UCODE_ADDR, 0);
4268 for (i = 0; i < fw_size; i++)
4269 WREG32(CP_MEC_ME1_UCODE_DATA, le32_to_cpup(fw_data++));
4270 WREG32(CP_MEC_ME1_UCODE_ADDR, le32_to_cpu(mec_hdr->header.ucode_version));
4273 if (rdev->family == CHIP_KAVERI) {
4274 const struct gfx_firmware_header_v1_0 *mec2_hdr =
4275 (const struct gfx_firmware_header_v1_0 *)rdev->mec2_fw->data;
4277 fw_data = (const __le32 *)
4278 (rdev->mec2_fw->data +
4279 le32_to_cpu(mec2_hdr->header.ucode_array_offset_bytes));
4280 fw_size = le32_to_cpu(mec2_hdr->header.ucode_size_bytes) / 4;
4281 WREG32(CP_MEC_ME2_UCODE_ADDR, 0);
4282 for (i = 0; i < fw_size; i++)
4283 WREG32(CP_MEC_ME2_UCODE_DATA, le32_to_cpup(fw_data++));
4284 WREG32(CP_MEC_ME2_UCODE_ADDR, le32_to_cpu(mec2_hdr->header.ucode_version));
4287 const __be32 *fw_data;
4290 fw_data = (const __be32 *)rdev->mec_fw->data;
4291 WREG32(CP_MEC_ME1_UCODE_ADDR, 0);
4292 for (i = 0; i < CIK_MEC_UCODE_SIZE; i++)
4293 WREG32(CP_MEC_ME1_UCODE_DATA, be32_to_cpup(fw_data++));
4294 WREG32(CP_MEC_ME1_UCODE_ADDR, 0);
4296 if (rdev->family == CHIP_KAVERI) {
4298 fw_data = (const __be32 *)rdev->mec_fw->data;
4299 WREG32(CP_MEC_ME2_UCODE_ADDR, 0);
4300 for (i = 0; i < CIK_MEC_UCODE_SIZE; i++)
4301 WREG32(CP_MEC_ME2_UCODE_DATA, be32_to_cpup(fw_data++));
4302 WREG32(CP_MEC_ME2_UCODE_ADDR, 0);
4310 * cik_cp_compute_start - start the compute queues
4312 * @rdev: radeon_device pointer
4314 * Enable the compute queues.
4315 * Returns 0 for success, error for failure.
4317 static int cik_cp_compute_start(struct radeon_device *rdev)
4319 cik_cp_compute_enable(rdev, true);
4325 * cik_cp_compute_fini - stop the compute queues
4327 * @rdev: radeon_device pointer
4329 * Stop the compute queues and tear down the driver queue
4332 static void cik_cp_compute_fini(struct radeon_device *rdev)
4336 cik_cp_compute_enable(rdev, false);
4338 for (i = 0; i < 2; i++) {
4340 idx = CAYMAN_RING_TYPE_CP1_INDEX;
4342 idx = CAYMAN_RING_TYPE_CP2_INDEX;
4344 if (rdev->ring[idx].mqd_obj) {
4345 r = radeon_bo_reserve(rdev->ring[idx].mqd_obj, false);
4346 if (unlikely(r != 0))
4347 dev_warn(rdev->dev, "(%d) reserve MQD bo failed\n", r);
4349 radeon_bo_unpin(rdev->ring[idx].mqd_obj);
4350 radeon_bo_unreserve(rdev->ring[idx].mqd_obj);
4352 radeon_bo_unref(&rdev->ring[idx].mqd_obj);
4353 rdev->ring[idx].mqd_obj = NULL;
4358 static void cik_mec_fini(struct radeon_device *rdev)
4362 if (rdev->mec.hpd_eop_obj) {
4363 r = radeon_bo_reserve(rdev->mec.hpd_eop_obj, false);
4364 if (unlikely(r != 0))
4365 dev_warn(rdev->dev, "(%d) reserve HPD EOP bo failed\n", r);
4366 radeon_bo_unpin(rdev->mec.hpd_eop_obj);
4367 radeon_bo_unreserve(rdev->mec.hpd_eop_obj);
4369 radeon_bo_unref(&rdev->mec.hpd_eop_obj);
4370 rdev->mec.hpd_eop_obj = NULL;
4374 #define MEC_HPD_SIZE 2048
4376 static int cik_mec_init(struct radeon_device *rdev)
4382 * KV: 2 MEC, 4 Pipes/MEC, 8 Queues/Pipe - 64 Queues total
4383 * CI/KB: 1 MEC, 4 Pipes/MEC, 8 Queues/Pipe - 32 Queues total
4385 if (rdev->family == CHIP_KAVERI)
4386 rdev->mec.num_mec = 2;
4388 rdev->mec.num_mec = 1;
4389 rdev->mec.num_pipe = 4;
4390 rdev->mec.num_queue = rdev->mec.num_mec * rdev->mec.num_pipe * 8;
4392 if (rdev->mec.hpd_eop_obj == NULL) {
4393 r = radeon_bo_create(rdev,
4394 rdev->mec.num_mec *rdev->mec.num_pipe * MEC_HPD_SIZE * 2,
4396 RADEON_GEM_DOMAIN_GTT, 0, NULL, NULL,
4397 &rdev->mec.hpd_eop_obj);
4399 dev_warn(rdev->dev, "(%d) create HDP EOP bo failed\n", r);
4404 r = radeon_bo_reserve(rdev->mec.hpd_eop_obj, false);
4405 if (unlikely(r != 0)) {
4409 r = radeon_bo_pin(rdev->mec.hpd_eop_obj, RADEON_GEM_DOMAIN_GTT,
4410 &rdev->mec.hpd_eop_gpu_addr);
4412 dev_warn(rdev->dev, "(%d) pin HDP EOP bo failed\n", r);
4416 r = radeon_bo_kmap(rdev->mec.hpd_eop_obj, (void **)&hpd);
4418 dev_warn(rdev->dev, "(%d) map HDP EOP bo failed\n", r);
4423 /* clear memory. Not sure if this is required or not */
4424 memset(hpd, 0, rdev->mec.num_mec *rdev->mec.num_pipe * MEC_HPD_SIZE * 2);
4426 radeon_bo_kunmap(rdev->mec.hpd_eop_obj);
4427 radeon_bo_unreserve(rdev->mec.hpd_eop_obj);
4432 struct hqd_registers
4434 u32 cp_mqd_base_addr;
4435 u32 cp_mqd_base_addr_hi;
4438 u32 cp_hqd_persistent_state;
4439 u32 cp_hqd_pipe_priority;
4440 u32 cp_hqd_queue_priority;
4443 u32 cp_hqd_pq_base_hi;
4445 u32 cp_hqd_pq_rptr_report_addr;
4446 u32 cp_hqd_pq_rptr_report_addr_hi;
4447 u32 cp_hqd_pq_wptr_poll_addr;
4448 u32 cp_hqd_pq_wptr_poll_addr_hi;
4449 u32 cp_hqd_pq_doorbell_control;
4451 u32 cp_hqd_pq_control;
4452 u32 cp_hqd_ib_base_addr;
4453 u32 cp_hqd_ib_base_addr_hi;
4455 u32 cp_hqd_ib_control;
4456 u32 cp_hqd_iq_timer;
4458 u32 cp_hqd_dequeue_request;
4459 u32 cp_hqd_dma_offload;
4460 u32 cp_hqd_sema_cmd;
4461 u32 cp_hqd_msg_type;
4462 u32 cp_hqd_atomic0_preop_lo;
4463 u32 cp_hqd_atomic0_preop_hi;
4464 u32 cp_hqd_atomic1_preop_lo;
4465 u32 cp_hqd_atomic1_preop_hi;
4466 u32 cp_hqd_hq_scheduler0;
4467 u32 cp_hqd_hq_scheduler1;
4474 u32 dispatch_initiator;
4478 u32 pipeline_stat_enable;
4479 u32 perf_counter_enable;
4485 u32 resource_limits;
4486 u32 static_thread_mgmt01[2];
4488 u32 static_thread_mgmt23[2];
4490 u32 thread_trace_enable;
4493 u32 vgtcs_invoke_count[2];
4494 struct hqd_registers queue_state;
4496 u32 interrupt_queue[64];
4500 * cik_cp_compute_resume - setup the compute queue registers
4502 * @rdev: radeon_device pointer
4504 * Program the compute queues and test them to make sure they
4506 * Returns 0 for success, error for failure.
4508 static int cik_cp_compute_resume(struct radeon_device *rdev)
4512 bool use_doorbell = true;
4518 struct bonaire_mqd *mqd;
4520 r = cik_cp_compute_start(rdev);
4524 /* fix up chicken bits */
4525 tmp = RREG32(CP_CPF_DEBUG);
4527 WREG32(CP_CPF_DEBUG, tmp);
4529 /* init the pipes */
4530 mutex_lock(&rdev->srbm_mutex);
4532 for (i = 0; i < (rdev->mec.num_pipe * rdev->mec.num_mec); ++i) {
4533 int me = (i < 4) ? 1 : 2;
4534 int pipe = (i < 4) ? i : (i - 4);
4536 cik_srbm_select(rdev, me, pipe, 0, 0);
4538 eop_gpu_addr = rdev->mec.hpd_eop_gpu_addr + (i * MEC_HPD_SIZE * 2) ;
4539 /* write the EOP addr */
4540 WREG32(CP_HPD_EOP_BASE_ADDR, eop_gpu_addr >> 8);
4541 WREG32(CP_HPD_EOP_BASE_ADDR_HI, upper_32_bits(eop_gpu_addr) >> 8);
4543 /* set the VMID assigned */
4544 WREG32(CP_HPD_EOP_VMID, 0);
4546 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
4547 tmp = RREG32(CP_HPD_EOP_CONTROL);
4548 tmp &= ~EOP_SIZE_MASK;
4549 tmp |= order_base_2(MEC_HPD_SIZE / 8);
4550 WREG32(CP_HPD_EOP_CONTROL, tmp);
4553 cik_srbm_select(rdev, 0, 0, 0, 0);
4554 mutex_unlock(&rdev->srbm_mutex);
4556 /* init the queues. Just two for now. */
4557 for (i = 0; i < 2; i++) {
4559 idx = CAYMAN_RING_TYPE_CP1_INDEX;
4561 idx = CAYMAN_RING_TYPE_CP2_INDEX;
4563 if (rdev->ring[idx].mqd_obj == NULL) {
4564 r = radeon_bo_create(rdev,
4565 sizeof(struct bonaire_mqd),
4567 RADEON_GEM_DOMAIN_GTT, 0, NULL,
4568 NULL, &rdev->ring[idx].mqd_obj);
4570 dev_warn(rdev->dev, "(%d) create MQD bo failed\n", r);
4575 r = radeon_bo_reserve(rdev->ring[idx].mqd_obj, false);
4576 if (unlikely(r != 0)) {
4577 cik_cp_compute_fini(rdev);
4580 r = radeon_bo_pin(rdev->ring[idx].mqd_obj, RADEON_GEM_DOMAIN_GTT,
4583 dev_warn(rdev->dev, "(%d) pin MQD bo failed\n", r);
4584 cik_cp_compute_fini(rdev);
4587 r = radeon_bo_kmap(rdev->ring[idx].mqd_obj, (void **)&buf);
4589 dev_warn(rdev->dev, "(%d) map MQD bo failed\n", r);
4590 cik_cp_compute_fini(rdev);
4594 /* init the mqd struct */
4595 memset(buf, 0, sizeof(struct bonaire_mqd));
4597 mqd = (struct bonaire_mqd *)buf;
4598 mqd->header = 0xC0310800;
4599 mqd->static_thread_mgmt01[0] = 0xffffffff;
4600 mqd->static_thread_mgmt01[1] = 0xffffffff;
4601 mqd->static_thread_mgmt23[0] = 0xffffffff;
4602 mqd->static_thread_mgmt23[1] = 0xffffffff;
4604 mutex_lock(&rdev->srbm_mutex);
4605 cik_srbm_select(rdev, rdev->ring[idx].me,
4606 rdev->ring[idx].pipe,
4607 rdev->ring[idx].queue, 0);
4609 /* disable wptr polling */
4610 tmp = RREG32(CP_PQ_WPTR_POLL_CNTL);
4611 tmp &= ~WPTR_POLL_EN;
4612 WREG32(CP_PQ_WPTR_POLL_CNTL, tmp);
4614 /* enable doorbell? */
4615 mqd->queue_state.cp_hqd_pq_doorbell_control =
4616 RREG32(CP_HQD_PQ_DOORBELL_CONTROL);
4618 mqd->queue_state.cp_hqd_pq_doorbell_control |= DOORBELL_EN;
4620 mqd->queue_state.cp_hqd_pq_doorbell_control &= ~DOORBELL_EN;
4621 WREG32(CP_HQD_PQ_DOORBELL_CONTROL,
4622 mqd->queue_state.cp_hqd_pq_doorbell_control);
4624 /* disable the queue if it's active */
4625 mqd->queue_state.cp_hqd_dequeue_request = 0;
4626 mqd->queue_state.cp_hqd_pq_rptr = 0;
4627 mqd->queue_state.cp_hqd_pq_wptr= 0;
4628 if (RREG32(CP_HQD_ACTIVE) & 1) {
4629 WREG32(CP_HQD_DEQUEUE_REQUEST, 1);
4630 for (j = 0; j < rdev->usec_timeout; j++) {
4631 if (!(RREG32(CP_HQD_ACTIVE) & 1))
4635 WREG32(CP_HQD_DEQUEUE_REQUEST, mqd->queue_state.cp_hqd_dequeue_request);
4636 WREG32(CP_HQD_PQ_RPTR, mqd->queue_state.cp_hqd_pq_rptr);
4637 WREG32(CP_HQD_PQ_WPTR, mqd->queue_state.cp_hqd_pq_wptr);
4640 /* set the pointer to the MQD */
4641 mqd->queue_state.cp_mqd_base_addr = mqd_gpu_addr & 0xfffffffc;
4642 mqd->queue_state.cp_mqd_base_addr_hi = upper_32_bits(mqd_gpu_addr);
4643 WREG32(CP_MQD_BASE_ADDR, mqd->queue_state.cp_mqd_base_addr);
4644 WREG32(CP_MQD_BASE_ADDR_HI, mqd->queue_state.cp_mqd_base_addr_hi);
4645 /* set MQD vmid to 0 */
4646 mqd->queue_state.cp_mqd_control = RREG32(CP_MQD_CONTROL);
4647 mqd->queue_state.cp_mqd_control &= ~MQD_VMID_MASK;
4648 WREG32(CP_MQD_CONTROL, mqd->queue_state.cp_mqd_control);
4650 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
4651 hqd_gpu_addr = rdev->ring[idx].gpu_addr >> 8;
4652 mqd->queue_state.cp_hqd_pq_base = hqd_gpu_addr;
4653 mqd->queue_state.cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
4654 WREG32(CP_HQD_PQ_BASE, mqd->queue_state.cp_hqd_pq_base);
4655 WREG32(CP_HQD_PQ_BASE_HI, mqd->queue_state.cp_hqd_pq_base_hi);
4657 /* set up the HQD, this is similar to CP_RB0_CNTL */
4658 mqd->queue_state.cp_hqd_pq_control = RREG32(CP_HQD_PQ_CONTROL);
4659 mqd->queue_state.cp_hqd_pq_control &=
4660 ~(QUEUE_SIZE_MASK | RPTR_BLOCK_SIZE_MASK);
4662 mqd->queue_state.cp_hqd_pq_control |=
4663 order_base_2(rdev->ring[idx].ring_size / 8);
4664 mqd->queue_state.cp_hqd_pq_control |=
4665 (order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8);
4667 mqd->queue_state.cp_hqd_pq_control |= BUF_SWAP_32BIT;
4669 mqd->queue_state.cp_hqd_pq_control &=
4670 ~(UNORD_DISPATCH | ROQ_PQ_IB_FLIP | PQ_VOLATILE);
4671 mqd->queue_state.cp_hqd_pq_control |=
4672 PRIV_STATE | KMD_QUEUE; /* assuming kernel queue control */
4673 WREG32(CP_HQD_PQ_CONTROL, mqd->queue_state.cp_hqd_pq_control);
4675 /* only used if CP_PQ_WPTR_POLL_CNTL.WPTR_POLL_EN=1 */
4677 wb_gpu_addr = rdev->wb.gpu_addr + CIK_WB_CP1_WPTR_OFFSET;
4679 wb_gpu_addr = rdev->wb.gpu_addr + CIK_WB_CP2_WPTR_OFFSET;
4680 mqd->queue_state.cp_hqd_pq_wptr_poll_addr = wb_gpu_addr & 0xfffffffc;
4681 mqd->queue_state.cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
4682 WREG32(CP_HQD_PQ_WPTR_POLL_ADDR, mqd->queue_state.cp_hqd_pq_wptr_poll_addr);
4683 WREG32(CP_HQD_PQ_WPTR_POLL_ADDR_HI,
4684 mqd->queue_state.cp_hqd_pq_wptr_poll_addr_hi);
4686 /* set the wb address wether it's enabled or not */
4688 wb_gpu_addr = rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET;
4690 wb_gpu_addr = rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET;
4691 mqd->queue_state.cp_hqd_pq_rptr_report_addr = wb_gpu_addr & 0xfffffffc;
4692 mqd->queue_state.cp_hqd_pq_rptr_report_addr_hi =
4693 upper_32_bits(wb_gpu_addr) & 0xffff;
4694 WREG32(CP_HQD_PQ_RPTR_REPORT_ADDR,
4695 mqd->queue_state.cp_hqd_pq_rptr_report_addr);
4696 WREG32(CP_HQD_PQ_RPTR_REPORT_ADDR_HI,
4697 mqd->queue_state.cp_hqd_pq_rptr_report_addr_hi);
4699 /* enable the doorbell if requested */
4701 mqd->queue_state.cp_hqd_pq_doorbell_control =
4702 RREG32(CP_HQD_PQ_DOORBELL_CONTROL);
4703 mqd->queue_state.cp_hqd_pq_doorbell_control &= ~DOORBELL_OFFSET_MASK;
4704 mqd->queue_state.cp_hqd_pq_doorbell_control |=
4705 DOORBELL_OFFSET(rdev->ring[idx].doorbell_index);
4706 mqd->queue_state.cp_hqd_pq_doorbell_control |= DOORBELL_EN;
4707 mqd->queue_state.cp_hqd_pq_doorbell_control &=
4708 ~(DOORBELL_SOURCE | DOORBELL_HIT);
4711 mqd->queue_state.cp_hqd_pq_doorbell_control = 0;
4713 WREG32(CP_HQD_PQ_DOORBELL_CONTROL,
4714 mqd->queue_state.cp_hqd_pq_doorbell_control);
4716 /* read and write pointers, similar to CP_RB0_WPTR/_RPTR */
4717 rdev->ring[idx].wptr = 0;
4718 mqd->queue_state.cp_hqd_pq_wptr = rdev->ring[idx].wptr;
4719 WREG32(CP_HQD_PQ_WPTR, mqd->queue_state.cp_hqd_pq_wptr);
4720 mqd->queue_state.cp_hqd_pq_rptr = RREG32(CP_HQD_PQ_RPTR);
4722 /* set the vmid for the queue */
4723 mqd->queue_state.cp_hqd_vmid = 0;
4724 WREG32(CP_HQD_VMID, mqd->queue_state.cp_hqd_vmid);
4726 /* activate the queue */
4727 mqd->queue_state.cp_hqd_active = 1;
4728 WREG32(CP_HQD_ACTIVE, mqd->queue_state.cp_hqd_active);
4730 cik_srbm_select(rdev, 0, 0, 0, 0);
4731 mutex_unlock(&rdev->srbm_mutex);
4733 radeon_bo_kunmap(rdev->ring[idx].mqd_obj);
4734 radeon_bo_unreserve(rdev->ring[idx].mqd_obj);
4736 rdev->ring[idx].ready = true;
4737 r = radeon_ring_test(rdev, idx, &rdev->ring[idx]);
4739 rdev->ring[idx].ready = false;
4745 static void cik_cp_enable(struct radeon_device *rdev, bool enable)
4747 cik_cp_gfx_enable(rdev, enable);
4748 cik_cp_compute_enable(rdev, enable);
4751 static int cik_cp_load_microcode(struct radeon_device *rdev)
4755 r = cik_cp_gfx_load_microcode(rdev);
4758 r = cik_cp_compute_load_microcode(rdev);
4765 static void cik_cp_fini(struct radeon_device *rdev)
4767 cik_cp_gfx_fini(rdev);
4768 cik_cp_compute_fini(rdev);
4771 static int cik_cp_resume(struct radeon_device *rdev)
4775 cik_enable_gui_idle_interrupt(rdev, false);
4777 r = cik_cp_load_microcode(rdev);
4781 r = cik_cp_gfx_resume(rdev);
4784 r = cik_cp_compute_resume(rdev);
4788 cik_enable_gui_idle_interrupt(rdev, true);
4793 static void cik_print_gpu_status_regs(struct radeon_device *rdev)
4795 dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n",
4796 RREG32(GRBM_STATUS));
4797 dev_info(rdev->dev, " GRBM_STATUS2=0x%08X\n",
4798 RREG32(GRBM_STATUS2));
4799 dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n",
4800 RREG32(GRBM_STATUS_SE0));
4801 dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n",
4802 RREG32(GRBM_STATUS_SE1));
4803 dev_info(rdev->dev, " GRBM_STATUS_SE2=0x%08X\n",
4804 RREG32(GRBM_STATUS_SE2));
4805 dev_info(rdev->dev, " GRBM_STATUS_SE3=0x%08X\n",
4806 RREG32(GRBM_STATUS_SE3));
4807 dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n",
4808 RREG32(SRBM_STATUS));
4809 dev_info(rdev->dev, " SRBM_STATUS2=0x%08X\n",
4810 RREG32(SRBM_STATUS2));
4811 dev_info(rdev->dev, " SDMA0_STATUS_REG = 0x%08X\n",
4812 RREG32(SDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET));
4813 dev_info(rdev->dev, " SDMA1_STATUS_REG = 0x%08X\n",
4814 RREG32(SDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET));
4815 dev_info(rdev->dev, " CP_STAT = 0x%08x\n", RREG32(CP_STAT));
4816 dev_info(rdev->dev, " CP_STALLED_STAT1 = 0x%08x\n",
4817 RREG32(CP_STALLED_STAT1));
4818 dev_info(rdev->dev, " CP_STALLED_STAT2 = 0x%08x\n",
4819 RREG32(CP_STALLED_STAT2));
4820 dev_info(rdev->dev, " CP_STALLED_STAT3 = 0x%08x\n",
4821 RREG32(CP_STALLED_STAT3));
4822 dev_info(rdev->dev, " CP_CPF_BUSY_STAT = 0x%08x\n",
4823 RREG32(CP_CPF_BUSY_STAT));
4824 dev_info(rdev->dev, " CP_CPF_STALLED_STAT1 = 0x%08x\n",
4825 RREG32(CP_CPF_STALLED_STAT1));
4826 dev_info(rdev->dev, " CP_CPF_STATUS = 0x%08x\n", RREG32(CP_CPF_STATUS));
4827 dev_info(rdev->dev, " CP_CPC_BUSY_STAT = 0x%08x\n", RREG32(CP_CPC_BUSY_STAT));
4828 dev_info(rdev->dev, " CP_CPC_STALLED_STAT1 = 0x%08x\n",
4829 RREG32(CP_CPC_STALLED_STAT1));
4830 dev_info(rdev->dev, " CP_CPC_STATUS = 0x%08x\n", RREG32(CP_CPC_STATUS));
4834 * cik_gpu_check_soft_reset - check which blocks are busy
4836 * @rdev: radeon_device pointer
4838 * Check which blocks are busy and return the relevant reset
4839 * mask to be used by cik_gpu_soft_reset().
4840 * Returns a mask of the blocks to be reset.
4842 u32 cik_gpu_check_soft_reset(struct radeon_device *rdev)
4848 tmp = RREG32(GRBM_STATUS);
4849 if (tmp & (PA_BUSY | SC_BUSY |
4850 BCI_BUSY | SX_BUSY |
4851 TA_BUSY | VGT_BUSY |
4853 GDS_BUSY | SPI_BUSY |
4854 IA_BUSY | IA_BUSY_NO_DMA))
4855 reset_mask |= RADEON_RESET_GFX;
4857 if (tmp & (CP_BUSY | CP_COHERENCY_BUSY))
4858 reset_mask |= RADEON_RESET_CP;
4861 tmp = RREG32(GRBM_STATUS2);
4863 reset_mask |= RADEON_RESET_RLC;
4865 /* SDMA0_STATUS_REG */
4866 tmp = RREG32(SDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET);
4867 if (!(tmp & SDMA_IDLE))
4868 reset_mask |= RADEON_RESET_DMA;
4870 /* SDMA1_STATUS_REG */
4871 tmp = RREG32(SDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET);
4872 if (!(tmp & SDMA_IDLE))
4873 reset_mask |= RADEON_RESET_DMA1;
4876 tmp = RREG32(SRBM_STATUS2);
4877 if (tmp & SDMA_BUSY)
4878 reset_mask |= RADEON_RESET_DMA;
4880 if (tmp & SDMA1_BUSY)
4881 reset_mask |= RADEON_RESET_DMA1;
4884 tmp = RREG32(SRBM_STATUS);
4887 reset_mask |= RADEON_RESET_IH;
4890 reset_mask |= RADEON_RESET_SEM;
4892 if (tmp & GRBM_RQ_PENDING)
4893 reset_mask |= RADEON_RESET_GRBM;
4896 reset_mask |= RADEON_RESET_VMC;
4898 if (tmp & (MCB_BUSY | MCB_NON_DISPLAY_BUSY |
4899 MCC_BUSY | MCD_BUSY))
4900 reset_mask |= RADEON_RESET_MC;
4902 if (evergreen_is_display_hung(rdev))
4903 reset_mask |= RADEON_RESET_DISPLAY;
4905 /* Skip MC reset as it's mostly likely not hung, just busy */
4906 if (reset_mask & RADEON_RESET_MC) {
4907 DRM_DEBUG("MC busy: 0x%08X, clearing.\n", reset_mask);
4908 reset_mask &= ~RADEON_RESET_MC;
4915 * cik_gpu_soft_reset - soft reset GPU
4917 * @rdev: radeon_device pointer
4918 * @reset_mask: mask of which blocks to reset
4920 * Soft reset the blocks specified in @reset_mask.
4922 static void cik_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)
4924 struct evergreen_mc_save save;
4925 u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
4928 if (reset_mask == 0)
4931 dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask);
4933 cik_print_gpu_status_regs(rdev);
4934 dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
4935 RREG32(VM_CONTEXT1_PROTECTION_FAULT_ADDR));
4936 dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
4937 RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS));
4946 /* Disable GFX parsing/prefetching */
4947 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT);
4949 /* Disable MEC parsing/prefetching */
4950 WREG32(CP_MEC_CNTL, MEC_ME1_HALT | MEC_ME2_HALT);
4952 if (reset_mask & RADEON_RESET_DMA) {
4954 tmp = RREG32(SDMA0_ME_CNTL + SDMA0_REGISTER_OFFSET);
4956 WREG32(SDMA0_ME_CNTL + SDMA0_REGISTER_OFFSET, tmp);
4958 if (reset_mask & RADEON_RESET_DMA1) {
4960 tmp = RREG32(SDMA0_ME_CNTL + SDMA1_REGISTER_OFFSET);
4962 WREG32(SDMA0_ME_CNTL + SDMA1_REGISTER_OFFSET, tmp);
4965 evergreen_mc_stop(rdev, &save);
4966 if (evergreen_mc_wait_for_idle(rdev)) {
4967 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
4970 if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE | RADEON_RESET_CP))
4971 grbm_soft_reset = SOFT_RESET_CP | SOFT_RESET_GFX;
4973 if (reset_mask & RADEON_RESET_CP) {
4974 grbm_soft_reset |= SOFT_RESET_CP;
4976 srbm_soft_reset |= SOFT_RESET_GRBM;
4979 if (reset_mask & RADEON_RESET_DMA)
4980 srbm_soft_reset |= SOFT_RESET_SDMA;
4982 if (reset_mask & RADEON_RESET_DMA1)
4983 srbm_soft_reset |= SOFT_RESET_SDMA1;
4985 if (reset_mask & RADEON_RESET_DISPLAY)
4986 srbm_soft_reset |= SOFT_RESET_DC;
4988 if (reset_mask & RADEON_RESET_RLC)
4989 grbm_soft_reset |= SOFT_RESET_RLC;
4991 if (reset_mask & RADEON_RESET_SEM)
4992 srbm_soft_reset |= SOFT_RESET_SEM;
4994 if (reset_mask & RADEON_RESET_IH)
4995 srbm_soft_reset |= SOFT_RESET_IH;
4997 if (reset_mask & RADEON_RESET_GRBM)
4998 srbm_soft_reset |= SOFT_RESET_GRBM;
5000 if (reset_mask & RADEON_RESET_VMC)
5001 srbm_soft_reset |= SOFT_RESET_VMC;
5003 if (!(rdev->flags & RADEON_IS_IGP)) {
5004 if (reset_mask & RADEON_RESET_MC)
5005 srbm_soft_reset |= SOFT_RESET_MC;
5008 if (grbm_soft_reset) {
5009 tmp = RREG32(GRBM_SOFT_RESET);
5010 tmp |= grbm_soft_reset;
5011 dev_info(rdev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
5012 WREG32(GRBM_SOFT_RESET, tmp);
5013 tmp = RREG32(GRBM_SOFT_RESET);
5017 tmp &= ~grbm_soft_reset;
5018 WREG32(GRBM_SOFT_RESET, tmp);
5019 tmp = RREG32(GRBM_SOFT_RESET);
5022 if (srbm_soft_reset) {
5023 tmp = RREG32(SRBM_SOFT_RESET);
5024 tmp |= srbm_soft_reset;
5025 dev_info(rdev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
5026 WREG32(SRBM_SOFT_RESET, tmp);
5027 tmp = RREG32(SRBM_SOFT_RESET);
5031 tmp &= ~srbm_soft_reset;
5032 WREG32(SRBM_SOFT_RESET, tmp);
5033 tmp = RREG32(SRBM_SOFT_RESET);
5036 /* Wait a little for things to settle down */
5039 evergreen_mc_resume(rdev, &save);
5042 cik_print_gpu_status_regs(rdev);
5045 struct kv_reset_save_regs {
5046 u32 gmcon_reng_execute;
5051 static void kv_save_regs_for_reset(struct radeon_device *rdev,
5052 struct kv_reset_save_regs *save)
5054 save->gmcon_reng_execute = RREG32(GMCON_RENG_EXECUTE);
5055 save->gmcon_misc = RREG32(GMCON_MISC);
5056 save->gmcon_misc3 = RREG32(GMCON_MISC3);
5058 WREG32(GMCON_RENG_EXECUTE, save->gmcon_reng_execute & ~RENG_EXECUTE_ON_PWR_UP);
5059 WREG32(GMCON_MISC, save->gmcon_misc & ~(RENG_EXECUTE_ON_REG_UPDATE |
5060 STCTRL_STUTTER_EN));
5063 static void kv_restore_regs_for_reset(struct radeon_device *rdev,
5064 struct kv_reset_save_regs *save)
5068 WREG32(GMCON_PGFSM_WRITE, 0);
5069 WREG32(GMCON_PGFSM_CONFIG, 0x200010ff);
5071 for (i = 0; i < 5; i++)
5072 WREG32(GMCON_PGFSM_WRITE, 0);
5074 WREG32(GMCON_PGFSM_WRITE, 0);
5075 WREG32(GMCON_PGFSM_CONFIG, 0x300010ff);
5077 for (i = 0; i < 5; i++)
5078 WREG32(GMCON_PGFSM_WRITE, 0);
5080 WREG32(GMCON_PGFSM_WRITE, 0x210000);
5081 WREG32(GMCON_PGFSM_CONFIG, 0xa00010ff);
5083 for (i = 0; i < 5; i++)
5084 WREG32(GMCON_PGFSM_WRITE, 0);
5086 WREG32(GMCON_PGFSM_WRITE, 0x21003);
5087 WREG32(GMCON_PGFSM_CONFIG, 0xb00010ff);
5089 for (i = 0; i < 5; i++)
5090 WREG32(GMCON_PGFSM_WRITE, 0);
5092 WREG32(GMCON_PGFSM_WRITE, 0x2b00);
5093 WREG32(GMCON_PGFSM_CONFIG, 0xc00010ff);
5095 for (i = 0; i < 5; i++)
5096 WREG32(GMCON_PGFSM_WRITE, 0);
5098 WREG32(GMCON_PGFSM_WRITE, 0);
5099 WREG32(GMCON_PGFSM_CONFIG, 0xd00010ff);
5101 for (i = 0; i < 5; i++)
5102 WREG32(GMCON_PGFSM_WRITE, 0);
5104 WREG32(GMCON_PGFSM_WRITE, 0x420000);
5105 WREG32(GMCON_PGFSM_CONFIG, 0x100010ff);
5107 for (i = 0; i < 5; i++)
5108 WREG32(GMCON_PGFSM_WRITE, 0);
5110 WREG32(GMCON_PGFSM_WRITE, 0x120202);
5111 WREG32(GMCON_PGFSM_CONFIG, 0x500010ff);
5113 for (i = 0; i < 5; i++)
5114 WREG32(GMCON_PGFSM_WRITE, 0);
5116 WREG32(GMCON_PGFSM_WRITE, 0x3e3e36);
5117 WREG32(GMCON_PGFSM_CONFIG, 0x600010ff);
5119 for (i = 0; i < 5; i++)
5120 WREG32(GMCON_PGFSM_WRITE, 0);
5122 WREG32(GMCON_PGFSM_WRITE, 0x373f3e);
5123 WREG32(GMCON_PGFSM_CONFIG, 0x700010ff);
5125 for (i = 0; i < 5; i++)
5126 WREG32(GMCON_PGFSM_WRITE, 0);
5128 WREG32(GMCON_PGFSM_WRITE, 0x3e1332);
5129 WREG32(GMCON_PGFSM_CONFIG, 0xe00010ff);
5131 WREG32(GMCON_MISC3, save->gmcon_misc3);
5132 WREG32(GMCON_MISC, save->gmcon_misc);
5133 WREG32(GMCON_RENG_EXECUTE, save->gmcon_reng_execute);
5136 static void cik_gpu_pci_config_reset(struct radeon_device *rdev)
5138 struct evergreen_mc_save save;
5139 struct kv_reset_save_regs kv_save = { 0 };
5142 dev_info(rdev->dev, "GPU pci config reset\n");
5150 /* Disable GFX parsing/prefetching */
5151 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT);
5153 /* Disable MEC parsing/prefetching */
5154 WREG32(CP_MEC_CNTL, MEC_ME1_HALT | MEC_ME2_HALT);
5157 tmp = RREG32(SDMA0_ME_CNTL + SDMA0_REGISTER_OFFSET);
5159 WREG32(SDMA0_ME_CNTL + SDMA0_REGISTER_OFFSET, tmp);
5161 tmp = RREG32(SDMA0_ME_CNTL + SDMA1_REGISTER_OFFSET);
5163 WREG32(SDMA0_ME_CNTL + SDMA1_REGISTER_OFFSET, tmp);
5164 /* XXX other engines? */
5166 /* halt the rlc, disable cp internal ints */
5171 /* disable mem access */
5172 evergreen_mc_stop(rdev, &save);
5173 if (evergreen_mc_wait_for_idle(rdev)) {
5174 dev_warn(rdev->dev, "Wait for MC idle timed out !\n");
5177 if (rdev->flags & RADEON_IS_IGP)
5178 kv_save_regs_for_reset(rdev, &kv_save);
5181 pci_clear_master(rdev->pdev);
5183 radeon_pci_config_reset(rdev);
5187 /* wait for asic to come out of reset */
5188 for (i = 0; i < rdev->usec_timeout; i++) {
5189 if (RREG32(CONFIG_MEMSIZE) != 0xffffffff)
5194 /* does asic init need to be run first??? */
5195 if (rdev->flags & RADEON_IS_IGP)
5196 kv_restore_regs_for_reset(rdev, &kv_save);
5200 * cik_asic_reset - soft reset GPU
5202 * @rdev: radeon_device pointer
5203 * @hard: force hard reset
5205 * Look up which blocks are hung and attempt
5207 * Returns 0 for success.
5209 int cik_asic_reset(struct radeon_device *rdev, bool hard)
5214 cik_gpu_pci_config_reset(rdev);
5218 reset_mask = cik_gpu_check_soft_reset(rdev);
5221 r600_set_bios_scratch_engine_hung(rdev, true);
5223 /* try soft reset */
5224 cik_gpu_soft_reset(rdev, reset_mask);
5226 reset_mask = cik_gpu_check_soft_reset(rdev);
5228 /* try pci config reset */
5229 if (reset_mask && radeon_hard_reset)
5230 cik_gpu_pci_config_reset(rdev);
5232 reset_mask = cik_gpu_check_soft_reset(rdev);
5235 r600_set_bios_scratch_engine_hung(rdev, false);
5241 * cik_gfx_is_lockup - check if the 3D engine is locked up
5243 * @rdev: radeon_device pointer
5244 * @ring: radeon_ring structure holding ring information
5246 * Check if the 3D engine is locked up (CIK).
5247 * Returns true if the engine is locked, false if not.
5249 bool cik_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
5251 u32 reset_mask = cik_gpu_check_soft_reset(rdev);
5253 if (!(reset_mask & (RADEON_RESET_GFX |
5254 RADEON_RESET_COMPUTE |
5255 RADEON_RESET_CP))) {
5256 radeon_ring_lockup_update(rdev, ring);
5259 return radeon_ring_test_lockup(rdev, ring);
5264 * cik_mc_program - program the GPU memory controller
5266 * @rdev: radeon_device pointer
5268 * Set the location of vram, gart, and AGP in the GPU's
5269 * physical address space (CIK).
5271 static void cik_mc_program(struct radeon_device *rdev)
5273 struct evergreen_mc_save save;
5277 /* Initialize HDP */
5278 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
5279 WREG32((0x2c14 + j), 0x00000000);
5280 WREG32((0x2c18 + j), 0x00000000);
5281 WREG32((0x2c1c + j), 0x00000000);
5282 WREG32((0x2c20 + j), 0x00000000);
5283 WREG32((0x2c24 + j), 0x00000000);
5285 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
5287 evergreen_mc_stop(rdev, &save);
5288 if (radeon_mc_wait_for_idle(rdev)) {
5289 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
5291 /* Lockout access through VGA aperture*/
5292 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
5293 /* Update configuration */
5294 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
5295 rdev->mc.vram_start >> 12);
5296 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
5297 rdev->mc.vram_end >> 12);
5298 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,
5299 rdev->vram_scratch.gpu_addr >> 12);
5300 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
5301 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
5302 WREG32(MC_VM_FB_LOCATION, tmp);
5303 /* XXX double check these! */
5304 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
5305 WREG32(HDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));
5306 WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
5307 WREG32(MC_VM_AGP_BASE, 0);
5308 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
5309 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
5310 if (radeon_mc_wait_for_idle(rdev)) {
5311 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
5313 evergreen_mc_resume(rdev, &save);
5314 /* we need to own VRAM, so turn off the VGA renderer here
5315 * to stop it overwriting our objects */
5316 rv515_vga_render_disable(rdev);
5320 * cik_mc_init - initialize the memory controller driver params
5322 * @rdev: radeon_device pointer
5324 * Look up the amount of vram, vram width, and decide how to place
5325 * vram and gart within the GPU's physical address space (CIK).
5326 * Returns 0 for success.
5328 static int cik_mc_init(struct radeon_device *rdev)
5331 int chansize, numchan;
5333 /* Get VRAM informations */
5334 rdev->mc.vram_is_ddr = true;
5335 tmp = RREG32(MC_ARB_RAMCFG);
5336 if (tmp & CHANSIZE_MASK) {
5341 tmp = RREG32(MC_SHARED_CHMAP);
5342 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
5372 rdev->mc.vram_width = numchan * chansize;
5373 /* Could aper size report 0 ? */
5374 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
5375 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
5376 /* size in MB on si */
5377 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024ULL * 1024ULL;
5378 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024ULL * 1024ULL;
5379 rdev->mc.visible_vram_size = rdev->mc.aper_size;
5380 si_vram_gtt_location(rdev, &rdev->mc);
5381 radeon_update_bandwidth_info(rdev);
5388 * VMID 0 is the physical GPU addresses as used by the kernel.
5389 * VMIDs 1-15 are used for userspace clients and are handled
5390 * by the radeon vm/hsa code.
5393 * cik_pcie_gart_tlb_flush - gart tlb flush callback
5395 * @rdev: radeon_device pointer
5397 * Flush the TLB for the VMID 0 page table (CIK).
5399 void cik_pcie_gart_tlb_flush(struct radeon_device *rdev)
5401 /* flush hdp cache */
5402 WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0);
5404 /* bits 0-15 are the VM contexts0-15 */
5405 WREG32(VM_INVALIDATE_REQUEST, 0x1);
5409 * cik_pcie_gart_enable - gart enable
5411 * @rdev: radeon_device pointer
5413 * This sets up the TLBs, programs the page tables for VMID0,
5414 * sets up the hw for VMIDs 1-15 which are allocated on
5415 * demand, and sets up the global locations for the LDS, GDS,
5416 * and GPUVM for FSA64 clients (CIK).
5417 * Returns 0 for success, errors for failure.
5419 static int cik_pcie_gart_enable(struct radeon_device *rdev)
5423 if (rdev->gart.robj == NULL) {
5424 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
5427 r = radeon_gart_table_vram_pin(rdev);
5430 /* Setup TLB control */
5431 WREG32(MC_VM_MX_L1_TLB_CNTL,
5434 ENABLE_L1_FRAGMENT_PROCESSING |
5435 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
5436 ENABLE_ADVANCED_DRIVER_MODEL |
5437 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU);
5438 /* Setup L2 cache */
5439 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE |
5440 ENABLE_L2_FRAGMENT_PROCESSING |
5441 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
5442 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE |
5443 EFFECTIVE_L2_QUEUE_SIZE(7) |
5444 CONTEXT1_IDENTITY_ACCESS_MODE(1));
5445 WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE);
5446 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |
5448 L2_CACHE_BIGK_FRAGMENT_SIZE(4));
5449 /* setup context0 */
5450 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
5451 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
5452 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
5453 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
5454 (u32)(rdev->dummy_page.addr >> 12));
5455 WREG32(VM_CONTEXT0_CNTL2, 0);
5456 WREG32(VM_CONTEXT0_CNTL, (ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
5457 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT));
5463 /* restore context1-15 */
5464 /* set vm size, must be a multiple of 4 */
5465 WREG32(VM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);
5466 WREG32(VM_CONTEXT1_PAGE_TABLE_END_ADDR, rdev->vm_manager.max_pfn - 1);
5467 for (i = 1; i < 16; i++) {
5469 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2),
5470 rdev->vm_manager.saved_table_addr[i]);
5472 WREG32(VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((i - 8) << 2),
5473 rdev->vm_manager.saved_table_addr[i]);
5476 /* enable context1-15 */
5477 WREG32(VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
5478 (u32)(rdev->dummy_page.addr >> 12));
5479 WREG32(VM_CONTEXT1_CNTL2, 4);
5480 WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(1) |
5481 PAGE_TABLE_BLOCK_SIZE(radeon_vm_block_size - 9) |
5482 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT |
5483 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT |
5484 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT |
5485 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT |
5486 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT |
5487 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT |
5488 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT |
5489 VALID_PROTECTION_FAULT_ENABLE_DEFAULT |
5490 READ_PROTECTION_FAULT_ENABLE_INTERRUPT |
5491 READ_PROTECTION_FAULT_ENABLE_DEFAULT |
5492 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT |
5493 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT);
5495 if (rdev->family == CHIP_KAVERI) {
5496 u32 tmp = RREG32(CHUB_CONTROL);
5498 WREG32(CHUB_CONTROL, tmp);
5501 /* XXX SH_MEM regs */
5502 /* where to put LDS, scratch, GPUVM in FSA64 space */
5503 mutex_lock(&rdev->srbm_mutex);
5504 for (i = 0; i < 16; i++) {
5505 cik_srbm_select(rdev, 0, 0, 0, i);
5506 /* CP and shaders */
5507 WREG32(SH_MEM_CONFIG, SH_MEM_CONFIG_GFX_DEFAULT);
5508 WREG32(SH_MEM_APE1_BASE, 1);
5509 WREG32(SH_MEM_APE1_LIMIT, 0);
5510 WREG32(SH_MEM_BASES, 0);
5512 WREG32(SDMA0_GFX_VIRTUAL_ADDR + SDMA0_REGISTER_OFFSET, 0);
5513 WREG32(SDMA0_GFX_APE1_CNTL + SDMA0_REGISTER_OFFSET, 0);
5514 WREG32(SDMA0_GFX_VIRTUAL_ADDR + SDMA1_REGISTER_OFFSET, 0);
5515 WREG32(SDMA0_GFX_APE1_CNTL + SDMA1_REGISTER_OFFSET, 0);
5516 /* XXX SDMA RLC - todo */
5518 cik_srbm_select(rdev, 0, 0, 0, 0);
5519 mutex_unlock(&rdev->srbm_mutex);
5521 cik_pcie_gart_tlb_flush(rdev);
5522 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
5523 (unsigned)(rdev->mc.gtt_size >> 20),
5524 (unsigned long long)rdev->gart.table_addr);
5525 rdev->gart.ready = true;
5530 * cik_pcie_gart_disable - gart disable
5532 * @rdev: radeon_device pointer
5534 * This disables all VM page table (CIK).
5536 static void cik_pcie_gart_disable(struct radeon_device *rdev)
5540 for (i = 1; i < 16; ++i) {
5543 reg = VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2);
5545 reg = VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((i - 8) << 2);
5546 rdev->vm_manager.saved_table_addr[i] = RREG32(reg);
5549 /* Disable all tables */
5550 WREG32(VM_CONTEXT0_CNTL, 0);
5551 WREG32(VM_CONTEXT1_CNTL, 0);
5552 /* Setup TLB control */
5553 WREG32(MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE_NOT_IN_SYS |
5554 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU);
5555 /* Setup L2 cache */
5557 ENABLE_L2_FRAGMENT_PROCESSING |
5558 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
5559 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE |
5560 EFFECTIVE_L2_QUEUE_SIZE(7) |
5561 CONTEXT1_IDENTITY_ACCESS_MODE(1));
5562 WREG32(VM_L2_CNTL2, 0);
5563 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |
5564 L2_CACHE_BIGK_FRAGMENT_SIZE(6));
5565 radeon_gart_table_vram_unpin(rdev);
5569 * cik_pcie_gart_fini - vm fini callback
5571 * @rdev: radeon_device pointer
5573 * Tears down the driver GART/VM setup (CIK).
5575 static void cik_pcie_gart_fini(struct radeon_device *rdev)
5577 cik_pcie_gart_disable(rdev);
5578 radeon_gart_table_vram_free(rdev);
5579 radeon_gart_fini(rdev);
5584 * cik_ib_parse - vm ib_parse callback
5586 * @rdev: radeon_device pointer
5587 * @ib: indirect buffer pointer
5589 * CIK uses hw IB checking so this is a nop (CIK).
5591 int cik_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib)
5598 * VMID 0 is the physical GPU addresses as used by the kernel.
5599 * VMIDs 1-15 are used for userspace clients and are handled
5600 * by the radeon vm/hsa code.
5603 * cik_vm_init - cik vm init callback
5605 * @rdev: radeon_device pointer
5607 * Inits cik specific vm parameters (number of VMs, base of vram for
5608 * VMIDs 1-15) (CIK).
5609 * Returns 0 for success.
5611 int cik_vm_init(struct radeon_device *rdev)
5615 * VMID 0 is reserved for System
5616 * radeon graphics/compute will use VMIDs 1-15
5618 rdev->vm_manager.nvm = 16;
5619 /* base offset of vram pages */
5620 if (rdev->flags & RADEON_IS_IGP) {
5621 u64 tmp = RREG32(MC_VM_FB_OFFSET);
5623 rdev->vm_manager.vram_base_offset = tmp;
5625 rdev->vm_manager.vram_base_offset = 0;
5631 * cik_vm_fini - cik vm fini callback
5633 * @rdev: radeon_device pointer
5635 * Tear down any asic specific VM setup (CIK).
5637 void cik_vm_fini(struct radeon_device *rdev)
5642 * cik_vm_decode_fault - print human readable fault info
5644 * @rdev: radeon_device pointer
5645 * @status: VM_CONTEXT1_PROTECTION_FAULT_STATUS register value
5646 * @addr: VM_CONTEXT1_PROTECTION_FAULT_ADDR register value
5647 * @mc_client: VM_CONTEXT1_PROTECTION_FAULT_MCCLIENT register value
5649 * Print human readable fault information (CIK).
5651 static void cik_vm_decode_fault(struct radeon_device *rdev,
5652 u32 status, u32 addr, u32 mc_client)
5655 u32 vmid = (status & FAULT_VMID_MASK) >> FAULT_VMID_SHIFT;
5656 u32 protections = (status & PROTECTIONS_MASK) >> PROTECTIONS_SHIFT;
5657 char block[5] = { mc_client >> 24, (mc_client >> 16) & 0xff,
5658 (mc_client >> 8) & 0xff, mc_client & 0xff, 0 };
5660 if (rdev->family == CHIP_HAWAII)
5661 mc_id = (status & HAWAII_MEMORY_CLIENT_ID_MASK) >> MEMORY_CLIENT_ID_SHIFT;
5663 mc_id = (status & MEMORY_CLIENT_ID_MASK) >> MEMORY_CLIENT_ID_SHIFT;
5665 printk("VM fault (0x%02x, vmid %d) at page %u, %s from '%s' (0x%08x) (%d)\n",
5666 protections, vmid, addr,
5667 (status & MEMORY_CLIENT_RW_MASK) ? "write" : "read",
5668 block, mc_client, mc_id);
5672 * cik_vm_flush - cik vm flush using the CP
5674 * Update the page table base and flush the VM TLB
5675 * using the CP (CIK).
5677 void cik_vm_flush(struct radeon_device *rdev, struct radeon_ring *ring,
5678 unsigned vm_id, uint64_t pd_addr)
5680 int usepfp = (ring->idx == RADEON_RING_TYPE_GFX_INDEX);
5682 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
5683 radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) |
5684 WRITE_DATA_DST_SEL(0)));
5686 radeon_ring_write(ring,
5687 (VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm_id << 2)) >> 2);
5689 radeon_ring_write(ring,
5690 (VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((vm_id - 8) << 2)) >> 2);
5692 radeon_ring_write(ring, 0);
5693 radeon_ring_write(ring, pd_addr >> 12);
5695 /* update SH_MEM_* regs */
5696 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
5697 radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) |
5698 WRITE_DATA_DST_SEL(0)));
5699 radeon_ring_write(ring, SRBM_GFX_CNTL >> 2);
5700 radeon_ring_write(ring, 0);
5701 radeon_ring_write(ring, VMID(vm_id));
5703 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 6));
5704 radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) |
5705 WRITE_DATA_DST_SEL(0)));
5706 radeon_ring_write(ring, SH_MEM_BASES >> 2);
5707 radeon_ring_write(ring, 0);
5709 radeon_ring_write(ring, 0); /* SH_MEM_BASES */
5710 radeon_ring_write(ring, SH_MEM_CONFIG_GFX_DEFAULT); /* SH_MEM_CONFIG */
5711 radeon_ring_write(ring, 1); /* SH_MEM_APE1_BASE */
5712 radeon_ring_write(ring, 0); /* SH_MEM_APE1_LIMIT */
5714 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
5715 radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) |
5716 WRITE_DATA_DST_SEL(0)));
5717 radeon_ring_write(ring, SRBM_GFX_CNTL >> 2);
5718 radeon_ring_write(ring, 0);
5719 radeon_ring_write(ring, VMID(0));
5722 cik_hdp_flush_cp_ring_emit(rdev, ring->idx);
5724 /* bits 0-15 are the VM contexts0-15 */
5725 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
5726 radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) |
5727 WRITE_DATA_DST_SEL(0)));
5728 radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2);
5729 radeon_ring_write(ring, 0);
5730 radeon_ring_write(ring, 1 << vm_id);
5732 /* wait for the invalidate to complete */
5733 radeon_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
5734 radeon_ring_write(ring, (WAIT_REG_MEM_OPERATION(0) | /* wait */
5735 WAIT_REG_MEM_FUNCTION(0) | /* always */
5736 WAIT_REG_MEM_ENGINE(0))); /* me */
5737 radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2);
5738 radeon_ring_write(ring, 0);
5739 radeon_ring_write(ring, 0); /* ref */
5740 radeon_ring_write(ring, 0); /* mask */
5741 radeon_ring_write(ring, 0x20); /* poll interval */
5743 /* compute doesn't have PFP */
5745 /* sync PFP to ME, otherwise we might get invalid PFP reads */
5746 radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
5747 radeon_ring_write(ring, 0x0);
5753 * The RLC is a multi-purpose microengine that handles a
5754 * variety of functions, the most important of which is
5755 * the interrupt controller.
5757 static void cik_enable_gui_idle_interrupt(struct radeon_device *rdev,
5760 u32 tmp = RREG32(CP_INT_CNTL_RING0);
5763 tmp |= (CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
5765 tmp &= ~(CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
5766 WREG32(CP_INT_CNTL_RING0, tmp);
5769 static void cik_enable_lbpw(struct radeon_device *rdev, bool enable)
5773 tmp = RREG32(RLC_LB_CNTL);
5775 tmp |= LOAD_BALANCE_ENABLE;
5777 tmp &= ~LOAD_BALANCE_ENABLE;
5778 WREG32(RLC_LB_CNTL, tmp);
5781 static void cik_wait_for_rlc_serdes(struct radeon_device *rdev)
5786 for (i = 0; i < rdev->config.cik.max_shader_engines; i++) {
5787 for (j = 0; j < rdev->config.cik.max_sh_per_se; j++) {
5788 cik_select_se_sh(rdev, i, j);
5789 for (k = 0; k < rdev->usec_timeout; k++) {
5790 if (RREG32(RLC_SERDES_CU_MASTER_BUSY) == 0)
5796 cik_select_se_sh(rdev, 0xffffffff, 0xffffffff);
5798 mask = SE_MASTER_BUSY_MASK | GC_MASTER_BUSY | TC0_MASTER_BUSY | TC1_MASTER_BUSY;
5799 for (k = 0; k < rdev->usec_timeout; k++) {
5800 if ((RREG32(RLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0)
5806 static void cik_update_rlc(struct radeon_device *rdev, u32 rlc)
5810 tmp = RREG32(RLC_CNTL);
5812 WREG32(RLC_CNTL, rlc);
5815 static u32 cik_halt_rlc(struct radeon_device *rdev)
5819 orig = data = RREG32(RLC_CNTL);
5821 if (data & RLC_ENABLE) {
5824 data &= ~RLC_ENABLE;
5825 WREG32(RLC_CNTL, data);
5827 for (i = 0; i < rdev->usec_timeout; i++) {
5828 if ((RREG32(RLC_GPM_STAT) & RLC_GPM_BUSY) == 0)
5833 cik_wait_for_rlc_serdes(rdev);
5839 void cik_enter_rlc_safe_mode(struct radeon_device *rdev)
5843 tmp = REQ | MESSAGE(MSG_ENTER_RLC_SAFE_MODE);
5844 WREG32(RLC_GPR_REG2, tmp);
5846 mask = GFX_POWER_STATUS | GFX_CLOCK_STATUS;
5847 for (i = 0; i < rdev->usec_timeout; i++) {
5848 if ((RREG32(RLC_GPM_STAT) & mask) == mask)
5853 for (i = 0; i < rdev->usec_timeout; i++) {
5854 if ((RREG32(RLC_GPR_REG2) & REQ) == 0)
5860 void cik_exit_rlc_safe_mode(struct radeon_device *rdev)
5864 tmp = REQ | MESSAGE(MSG_EXIT_RLC_SAFE_MODE);
5865 WREG32(RLC_GPR_REG2, tmp);
5869 * cik_rlc_stop - stop the RLC ME
5871 * @rdev: radeon_device pointer
5873 * Halt the RLC ME (MicroEngine) (CIK).
5875 static void cik_rlc_stop(struct radeon_device *rdev)
5877 WREG32(RLC_CNTL, 0);
5879 cik_enable_gui_idle_interrupt(rdev, false);
5881 cik_wait_for_rlc_serdes(rdev);
5885 * cik_rlc_start - start the RLC ME
5887 * @rdev: radeon_device pointer
5889 * Unhalt the RLC ME (MicroEngine) (CIK).
5891 static void cik_rlc_start(struct radeon_device *rdev)
5893 WREG32(RLC_CNTL, RLC_ENABLE);
5895 cik_enable_gui_idle_interrupt(rdev, true);
5901 * cik_rlc_resume - setup the RLC hw
5903 * @rdev: radeon_device pointer
5905 * Initialize the RLC registers, load the ucode,
5906 * and start the RLC (CIK).
5907 * Returns 0 for success, -EINVAL if the ucode is not available.
5909 static int cik_rlc_resume(struct radeon_device *rdev)
5919 tmp = RREG32(RLC_CGCG_CGLS_CTRL) & 0xfffffffc;
5920 WREG32(RLC_CGCG_CGLS_CTRL, tmp);
5928 WREG32(RLC_LB_CNTR_INIT, 0);
5929 WREG32(RLC_LB_CNTR_MAX, 0x00008000);
5931 cik_select_se_sh(rdev, 0xffffffff, 0xffffffff);
5932 WREG32(RLC_LB_INIT_CU_MASK, 0xffffffff);
5933 WREG32(RLC_LB_PARAMS, 0x00600408);
5934 WREG32(RLC_LB_CNTL, 0x80000004);
5936 WREG32(RLC_MC_CNTL, 0);
5937 WREG32(RLC_UCODE_CNTL, 0);
5940 const struct rlc_firmware_header_v1_0 *hdr =
5941 (const struct rlc_firmware_header_v1_0 *)rdev->rlc_fw->data;
5942 const __le32 *fw_data = (const __le32 *)
5943 (rdev->rlc_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
5945 radeon_ucode_print_rlc_hdr(&hdr->header);
5947 size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
5948 WREG32(RLC_GPM_UCODE_ADDR, 0);
5949 for (i = 0; i < size; i++)
5950 WREG32(RLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++));
5951 WREG32(RLC_GPM_UCODE_ADDR, le32_to_cpu(hdr->header.ucode_version));
5953 const __be32 *fw_data;
5955 switch (rdev->family) {
5959 size = BONAIRE_RLC_UCODE_SIZE;
5962 size = KV_RLC_UCODE_SIZE;
5965 size = KB_RLC_UCODE_SIZE;
5968 size = ML_RLC_UCODE_SIZE;
5972 fw_data = (const __be32 *)rdev->rlc_fw->data;
5973 WREG32(RLC_GPM_UCODE_ADDR, 0);
5974 for (i = 0; i < size; i++)
5975 WREG32(RLC_GPM_UCODE_DATA, be32_to_cpup(fw_data++));
5976 WREG32(RLC_GPM_UCODE_ADDR, 0);
5979 /* XXX - find out what chips support lbpw */
5980 cik_enable_lbpw(rdev, false);
5982 if (rdev->family == CHIP_BONAIRE)
5983 WREG32(RLC_DRIVER_DMA_STATUS, 0);
5985 cik_rlc_start(rdev);
5990 static void cik_enable_cgcg(struct radeon_device *rdev, bool enable)
5992 u32 data, orig, tmp, tmp2;
5994 orig = data = RREG32(RLC_CGCG_CGLS_CTRL);
5996 if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_GFX_CGCG)) {
5997 cik_enable_gui_idle_interrupt(rdev, true);
5999 tmp = cik_halt_rlc(rdev);
6001 cik_select_se_sh(rdev, 0xffffffff, 0xffffffff);
6002 WREG32(RLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff);
6003 WREG32(RLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff);
6004 tmp2 = BPM_ADDR_MASK | CGCG_OVERRIDE_0 | CGLS_ENABLE;
6005 WREG32(RLC_SERDES_WR_CTRL, tmp2);
6007 cik_update_rlc(rdev, tmp);
6009 data |= CGCG_EN | CGLS_EN;
6011 cik_enable_gui_idle_interrupt(rdev, false);
6013 RREG32(CB_CGTT_SCLK_CTRL);
6014 RREG32(CB_CGTT_SCLK_CTRL);
6015 RREG32(CB_CGTT_SCLK_CTRL);
6016 RREG32(CB_CGTT_SCLK_CTRL);
6018 data &= ~(CGCG_EN | CGLS_EN);
6022 WREG32(RLC_CGCG_CGLS_CTRL, data);
6026 static void cik_enable_mgcg(struct radeon_device *rdev, bool enable)
6028 u32 data, orig, tmp = 0;
6030 if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_GFX_MGCG)) {
6031 if (rdev->cg_flags & RADEON_CG_SUPPORT_GFX_MGLS) {
6032 if (rdev->cg_flags & RADEON_CG_SUPPORT_GFX_CP_LS) {
6033 orig = data = RREG32(CP_MEM_SLP_CNTL);
6034 data |= CP_MEM_LS_EN;
6036 WREG32(CP_MEM_SLP_CNTL, data);
6040 orig = data = RREG32(RLC_CGTT_MGCG_OVERRIDE);
6044 WREG32(RLC_CGTT_MGCG_OVERRIDE, data);
6046 tmp = cik_halt_rlc(rdev);
6048 cik_select_se_sh(rdev, 0xffffffff, 0xffffffff);
6049 WREG32(RLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff);
6050 WREG32(RLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff);
6051 data = BPM_ADDR_MASK | MGCG_OVERRIDE_0;
6052 WREG32(RLC_SERDES_WR_CTRL, data);
6054 cik_update_rlc(rdev, tmp);
6056 if (rdev->cg_flags & RADEON_CG_SUPPORT_GFX_CGTS) {
6057 orig = data = RREG32(CGTS_SM_CTRL_REG);
6058 data &= ~SM_MODE_MASK;
6059 data |= SM_MODE(0x2);
6060 data |= SM_MODE_ENABLE;
6061 data &= ~CGTS_OVERRIDE;
6062 if ((rdev->cg_flags & RADEON_CG_SUPPORT_GFX_MGLS) &&
6063 (rdev->cg_flags & RADEON_CG_SUPPORT_GFX_CGTS_LS))
6064 data &= ~CGTS_LS_OVERRIDE;
6065 data &= ~ON_MONITOR_ADD_MASK;
6066 data |= ON_MONITOR_ADD_EN;
6067 data |= ON_MONITOR_ADD(0x96);
6069 WREG32(CGTS_SM_CTRL_REG, data);
6072 orig = data = RREG32(RLC_CGTT_MGCG_OVERRIDE);
6075 WREG32(RLC_CGTT_MGCG_OVERRIDE, data);
6077 data = RREG32(RLC_MEM_SLP_CNTL);
6078 if (data & RLC_MEM_LS_EN) {
6079 data &= ~RLC_MEM_LS_EN;
6080 WREG32(RLC_MEM_SLP_CNTL, data);
6083 data = RREG32(CP_MEM_SLP_CNTL);
6084 if (data & CP_MEM_LS_EN) {
6085 data &= ~CP_MEM_LS_EN;
6086 WREG32(CP_MEM_SLP_CNTL, data);
6089 orig = data = RREG32(CGTS_SM_CTRL_REG);
6090 data |= CGTS_OVERRIDE | CGTS_LS_OVERRIDE;
6092 WREG32(CGTS_SM_CTRL_REG, data);
6094 tmp = cik_halt_rlc(rdev);
6096 cik_select_se_sh(rdev, 0xffffffff, 0xffffffff);
6097 WREG32(RLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff);
6098 WREG32(RLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff);
6099 data = BPM_ADDR_MASK | MGCG_OVERRIDE_1;
6100 WREG32(RLC_SERDES_WR_CTRL, data);
6102 cik_update_rlc(rdev, tmp);
6106 static const u32 mc_cg_registers[] =
6119 static void cik_enable_mc_ls(struct radeon_device *rdev,
6125 for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) {
6126 orig = data = RREG32(mc_cg_registers[i]);
6127 if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_MC_LS))
6128 data |= MC_LS_ENABLE;
6130 data &= ~MC_LS_ENABLE;
6132 WREG32(mc_cg_registers[i], data);
6136 static void cik_enable_mc_mgcg(struct radeon_device *rdev,
6142 for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) {
6143 orig = data = RREG32(mc_cg_registers[i]);
6144 if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_MC_MGCG))
6145 data |= MC_CG_ENABLE;
6147 data &= ~MC_CG_ENABLE;
6149 WREG32(mc_cg_registers[i], data);
6153 static void cik_enable_sdma_mgcg(struct radeon_device *rdev,
6158 if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_SDMA_MGCG)) {
6159 WREG32(SDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, 0x00000100);
6160 WREG32(SDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, 0x00000100);
6162 orig = data = RREG32(SDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET);
6165 WREG32(SDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, data);
6167 orig = data = RREG32(SDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET);
6170 WREG32(SDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, data);
6174 static void cik_enable_sdma_mgls(struct radeon_device *rdev,
6179 if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_SDMA_LS)) {
6180 orig = data = RREG32(SDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET);
6183 WREG32(SDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET, data);
6185 orig = data = RREG32(SDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET);
6188 WREG32(SDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data);
6190 orig = data = RREG32(SDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET);
6193 WREG32(SDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET, data);
6195 orig = data = RREG32(SDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET);
6198 WREG32(SDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data);
6202 static void cik_enable_uvd_mgcg(struct radeon_device *rdev,
6207 if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_UVD_MGCG)) {
6208 data = RREG32_UVD_CTX(UVD_CGC_MEM_CTRL);
6210 WREG32_UVD_CTX(UVD_CGC_MEM_CTRL, data);
6212 orig = data = RREG32(UVD_CGC_CTRL);
6215 WREG32(UVD_CGC_CTRL, data);
6217 data = RREG32_UVD_CTX(UVD_CGC_MEM_CTRL);
6219 WREG32_UVD_CTX(UVD_CGC_MEM_CTRL, data);
6221 orig = data = RREG32(UVD_CGC_CTRL);
6224 WREG32(UVD_CGC_CTRL, data);
6228 static void cik_enable_bif_mgls(struct radeon_device *rdev,
6233 orig = data = RREG32_PCIE_PORT(PCIE_CNTL2);
6235 if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_BIF_LS))
6236 data |= SLV_MEM_LS_EN | MST_MEM_LS_EN |
6237 REPLAY_MEM_LS_EN | SLV_MEM_AGGRESSIVE_LS_EN;
6239 data &= ~(SLV_MEM_LS_EN | MST_MEM_LS_EN |
6240 REPLAY_MEM_LS_EN | SLV_MEM_AGGRESSIVE_LS_EN);
6243 WREG32_PCIE_PORT(PCIE_CNTL2, data);
6246 static void cik_enable_hdp_mgcg(struct radeon_device *rdev,
6251 orig = data = RREG32(HDP_HOST_PATH_CNTL);
6253 if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_HDP_MGCG))
6254 data &= ~CLOCK_GATING_DIS;
6256 data |= CLOCK_GATING_DIS;
6259 WREG32(HDP_HOST_PATH_CNTL, data);
6262 static void cik_enable_hdp_ls(struct radeon_device *rdev,
6267 orig = data = RREG32(HDP_MEM_POWER_LS);
6269 if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_HDP_LS))
6270 data |= HDP_LS_ENABLE;
6272 data &= ~HDP_LS_ENABLE;
6275 WREG32(HDP_MEM_POWER_LS, data);
6278 void cik_update_cg(struct radeon_device *rdev,
6279 u32 block, bool enable)
6282 if (block & RADEON_CG_BLOCK_GFX) {
6283 cik_enable_gui_idle_interrupt(rdev, false);
6284 /* order matters! */
6286 cik_enable_mgcg(rdev, true);
6287 cik_enable_cgcg(rdev, true);
6289 cik_enable_cgcg(rdev, false);
6290 cik_enable_mgcg(rdev, false);
6292 cik_enable_gui_idle_interrupt(rdev, true);
6295 if (block & RADEON_CG_BLOCK_MC) {
6296 if (!(rdev->flags & RADEON_IS_IGP)) {
6297 cik_enable_mc_mgcg(rdev, enable);
6298 cik_enable_mc_ls(rdev, enable);
6302 if (block & RADEON_CG_BLOCK_SDMA) {
6303 cik_enable_sdma_mgcg(rdev, enable);
6304 cik_enable_sdma_mgls(rdev, enable);
6307 if (block & RADEON_CG_BLOCK_BIF) {
6308 cik_enable_bif_mgls(rdev, enable);
6311 if (block & RADEON_CG_BLOCK_UVD) {
6313 cik_enable_uvd_mgcg(rdev, enable);
6316 if (block & RADEON_CG_BLOCK_HDP) {
6317 cik_enable_hdp_mgcg(rdev, enable);
6318 cik_enable_hdp_ls(rdev, enable);
6321 if (block & RADEON_CG_BLOCK_VCE) {
6322 vce_v2_0_enable_mgcg(rdev, enable);
6326 static void cik_init_cg(struct radeon_device *rdev)
6329 cik_update_cg(rdev, RADEON_CG_BLOCK_GFX, true);
6332 si_init_uvd_internal_cg(rdev);
6334 cik_update_cg(rdev, (RADEON_CG_BLOCK_MC |
6335 RADEON_CG_BLOCK_SDMA |
6336 RADEON_CG_BLOCK_BIF |
6337 RADEON_CG_BLOCK_UVD |
6338 RADEON_CG_BLOCK_HDP), true);
6341 static void cik_fini_cg(struct radeon_device *rdev)
6343 cik_update_cg(rdev, (RADEON_CG_BLOCK_MC |
6344 RADEON_CG_BLOCK_SDMA |
6345 RADEON_CG_BLOCK_BIF |
6346 RADEON_CG_BLOCK_UVD |
6347 RADEON_CG_BLOCK_HDP), false);
6349 cik_update_cg(rdev, RADEON_CG_BLOCK_GFX, false);
6352 static void cik_enable_sck_slowdown_on_pu(struct radeon_device *rdev,
6357 orig = data = RREG32(RLC_PG_CNTL);
6358 if (enable && (rdev->pg_flags & RADEON_PG_SUPPORT_RLC_SMU_HS))
6359 data |= SMU_CLK_SLOWDOWN_ON_PU_ENABLE;
6361 data &= ~SMU_CLK_SLOWDOWN_ON_PU_ENABLE;
6363 WREG32(RLC_PG_CNTL, data);
6366 static void cik_enable_sck_slowdown_on_pd(struct radeon_device *rdev,
6371 orig = data = RREG32(RLC_PG_CNTL);
6372 if (enable && (rdev->pg_flags & RADEON_PG_SUPPORT_RLC_SMU_HS))
6373 data |= SMU_CLK_SLOWDOWN_ON_PD_ENABLE;
6375 data &= ~SMU_CLK_SLOWDOWN_ON_PD_ENABLE;
6377 WREG32(RLC_PG_CNTL, data);
6380 static void cik_enable_cp_pg(struct radeon_device *rdev, bool enable)
6384 orig = data = RREG32(RLC_PG_CNTL);
6385 if (enable && (rdev->pg_flags & RADEON_PG_SUPPORT_CP))
6386 data &= ~DISABLE_CP_PG;
6388 data |= DISABLE_CP_PG;
6390 WREG32(RLC_PG_CNTL, data);
6393 static void cik_enable_gds_pg(struct radeon_device *rdev, bool enable)
6397 orig = data = RREG32(RLC_PG_CNTL);
6398 if (enable && (rdev->pg_flags & RADEON_PG_SUPPORT_GDS))
6399 data &= ~DISABLE_GDS_PG;
6401 data |= DISABLE_GDS_PG;
6403 WREG32(RLC_PG_CNTL, data);
6406 #define CP_ME_TABLE_SIZE 96
6407 #define CP_ME_TABLE_OFFSET 2048
6408 #define CP_MEC_TABLE_OFFSET 4096
6410 void cik_init_cp_pg_table(struct radeon_device *rdev)
6412 volatile u32 *dst_ptr;
6413 int me, i, max_me = 4;
6415 u32 table_offset, table_size;
6417 if (rdev->family == CHIP_KAVERI)
6420 if (rdev->rlc.cp_table_ptr == NULL)
6423 /* write the cp table buffer */
6424 dst_ptr = rdev->rlc.cp_table_ptr;
6425 for (me = 0; me < max_me; me++) {
6427 const __le32 *fw_data;
6428 const struct gfx_firmware_header_v1_0 *hdr;
6431 hdr = (const struct gfx_firmware_header_v1_0 *)rdev->ce_fw->data;
6432 fw_data = (const __le32 *)
6433 (rdev->ce_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
6434 table_offset = le32_to_cpu(hdr->jt_offset);
6435 table_size = le32_to_cpu(hdr->jt_size);
6436 } else if (me == 1) {
6437 hdr = (const struct gfx_firmware_header_v1_0 *)rdev->pfp_fw->data;
6438 fw_data = (const __le32 *)
6439 (rdev->pfp_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
6440 table_offset = le32_to_cpu(hdr->jt_offset);
6441 table_size = le32_to_cpu(hdr->jt_size);
6442 } else if (me == 2) {
6443 hdr = (const struct gfx_firmware_header_v1_0 *)rdev->me_fw->data;
6444 fw_data = (const __le32 *)
6445 (rdev->me_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
6446 table_offset = le32_to_cpu(hdr->jt_offset);
6447 table_size = le32_to_cpu(hdr->jt_size);
6448 } else if (me == 3) {
6449 hdr = (const struct gfx_firmware_header_v1_0 *)rdev->mec_fw->data;
6450 fw_data = (const __le32 *)
6451 (rdev->mec_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
6452 table_offset = le32_to_cpu(hdr->jt_offset);
6453 table_size = le32_to_cpu(hdr->jt_size);
6455 hdr = (const struct gfx_firmware_header_v1_0 *)rdev->mec2_fw->data;
6456 fw_data = (const __le32 *)
6457 (rdev->mec2_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
6458 table_offset = le32_to_cpu(hdr->jt_offset);
6459 table_size = le32_to_cpu(hdr->jt_size);
6462 for (i = 0; i < table_size; i ++) {
6463 dst_ptr[bo_offset + i] =
6464 cpu_to_le32(le32_to_cpu(fw_data[table_offset + i]));
6466 bo_offset += table_size;
6468 const __be32 *fw_data;
6469 table_size = CP_ME_TABLE_SIZE;
6472 fw_data = (const __be32 *)rdev->ce_fw->data;
6473 table_offset = CP_ME_TABLE_OFFSET;
6474 } else if (me == 1) {
6475 fw_data = (const __be32 *)rdev->pfp_fw->data;
6476 table_offset = CP_ME_TABLE_OFFSET;
6477 } else if (me == 2) {
6478 fw_data = (const __be32 *)rdev->me_fw->data;
6479 table_offset = CP_ME_TABLE_OFFSET;
6481 fw_data = (const __be32 *)rdev->mec_fw->data;
6482 table_offset = CP_MEC_TABLE_OFFSET;
6485 for (i = 0; i < table_size; i ++) {
6486 dst_ptr[bo_offset + i] =
6487 cpu_to_le32(be32_to_cpu(fw_data[table_offset + i]));
6489 bo_offset += table_size;
6494 static void cik_enable_gfx_cgpg(struct radeon_device *rdev,
6499 if (enable && (rdev->pg_flags & RADEON_PG_SUPPORT_GFX_PG)) {
6500 orig = data = RREG32(RLC_PG_CNTL);
6501 data |= GFX_PG_ENABLE;
6503 WREG32(RLC_PG_CNTL, data);
6505 orig = data = RREG32(RLC_AUTO_PG_CTRL);
6508 WREG32(RLC_AUTO_PG_CTRL, data);
6510 orig = data = RREG32(RLC_PG_CNTL);
6511 data &= ~GFX_PG_ENABLE;
6513 WREG32(RLC_PG_CNTL, data);
6515 orig = data = RREG32(RLC_AUTO_PG_CTRL);
6516 data &= ~AUTO_PG_EN;
6518 WREG32(RLC_AUTO_PG_CTRL, data);
6520 data = RREG32(DB_RENDER_CONTROL);
6524 static u32 cik_get_cu_active_bitmap(struct radeon_device *rdev, u32 se, u32 sh)
6526 u32 mask = 0, tmp, tmp1;
6529 cik_select_se_sh(rdev, se, sh);
6530 tmp = RREG32(CC_GC_SHADER_ARRAY_CONFIG);
6531 tmp1 = RREG32(GC_USER_SHADER_ARRAY_CONFIG);
6532 cik_select_se_sh(rdev, 0xffffffff, 0xffffffff);
6539 for (i = 0; i < rdev->config.cik.max_cu_per_sh; i ++) {
6544 return (~tmp) & mask;
6547 static void cik_init_ao_cu_mask(struct radeon_device *rdev)
6549 u32 i, j, k, active_cu_number = 0;
6550 u32 mask, counter, cu_bitmap;
6553 for (i = 0; i < rdev->config.cik.max_shader_engines; i++) {
6554 for (j = 0; j < rdev->config.cik.max_sh_per_se; j++) {
6558 for (k = 0; k < rdev->config.cik.max_cu_per_sh; k ++) {
6559 if (cik_get_cu_active_bitmap(rdev, i, j) & mask) {
6567 active_cu_number += counter;
6568 tmp |= (cu_bitmap << (i * 16 + j * 8));
6572 WREG32(RLC_PG_AO_CU_MASK, tmp);
6574 tmp = RREG32(RLC_MAX_PG_CU);
6575 tmp &= ~MAX_PU_CU_MASK;
6576 tmp |= MAX_PU_CU(active_cu_number);
6577 WREG32(RLC_MAX_PG_CU, tmp);
6580 static void cik_enable_gfx_static_mgpg(struct radeon_device *rdev,
6585 orig = data = RREG32(RLC_PG_CNTL);
6586 if (enable && (rdev->pg_flags & RADEON_PG_SUPPORT_GFX_SMG))
6587 data |= STATIC_PER_CU_PG_ENABLE;
6589 data &= ~STATIC_PER_CU_PG_ENABLE;
6591 WREG32(RLC_PG_CNTL, data);
6594 static void cik_enable_gfx_dynamic_mgpg(struct radeon_device *rdev,
6599 orig = data = RREG32(RLC_PG_CNTL);
6600 if (enable && (rdev->pg_flags & RADEON_PG_SUPPORT_GFX_DMG))
6601 data |= DYN_PER_CU_PG_ENABLE;
6603 data &= ~DYN_PER_CU_PG_ENABLE;
6605 WREG32(RLC_PG_CNTL, data);
6608 #define RLC_SAVE_AND_RESTORE_STARTING_OFFSET 0x90
6609 #define RLC_CLEAR_STATE_DESCRIPTOR_OFFSET 0x3D
6611 static void cik_init_gfx_cgpg(struct radeon_device *rdev)
6616 if (rdev->rlc.cs_data) {
6617 WREG32(RLC_GPM_SCRATCH_ADDR, RLC_CLEAR_STATE_DESCRIPTOR_OFFSET);
6618 WREG32(RLC_GPM_SCRATCH_DATA, upper_32_bits(rdev->rlc.clear_state_gpu_addr));
6619 WREG32(RLC_GPM_SCRATCH_DATA, lower_32_bits(rdev->rlc.clear_state_gpu_addr));
6620 WREG32(RLC_GPM_SCRATCH_DATA, rdev->rlc.clear_state_size);
6622 WREG32(RLC_GPM_SCRATCH_ADDR, RLC_CLEAR_STATE_DESCRIPTOR_OFFSET);
6623 for (i = 0; i < 3; i++)
6624 WREG32(RLC_GPM_SCRATCH_DATA, 0);
6626 if (rdev->rlc.reg_list) {
6627 WREG32(RLC_GPM_SCRATCH_ADDR, RLC_SAVE_AND_RESTORE_STARTING_OFFSET);
6628 for (i = 0; i < rdev->rlc.reg_list_size; i++)
6629 WREG32(RLC_GPM_SCRATCH_DATA, rdev->rlc.reg_list[i]);
6632 orig = data = RREG32(RLC_PG_CNTL);
6635 WREG32(RLC_PG_CNTL, data);
6637 WREG32(RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8);
6638 WREG32(RLC_CP_TABLE_RESTORE, rdev->rlc.cp_table_gpu_addr >> 8);
6640 data = RREG32(CP_RB_WPTR_POLL_CNTL);
6641 data &= ~IDLE_POLL_COUNT_MASK;
6642 data |= IDLE_POLL_COUNT(0x60);
6643 WREG32(CP_RB_WPTR_POLL_CNTL, data);
6646 WREG32(RLC_PG_DELAY, data);
6648 data = RREG32(RLC_PG_DELAY_2);
6651 WREG32(RLC_PG_DELAY_2, data);
6653 data = RREG32(RLC_AUTO_PG_CTRL);
6654 data &= ~GRBM_REG_SGIT_MASK;
6655 data |= GRBM_REG_SGIT(0x700);
6656 WREG32(RLC_AUTO_PG_CTRL, data);
6660 static void cik_update_gfx_pg(struct radeon_device *rdev, bool enable)
6662 cik_enable_gfx_cgpg(rdev, enable);
6663 cik_enable_gfx_static_mgpg(rdev, enable);
6664 cik_enable_gfx_dynamic_mgpg(rdev, enable);
6667 u32 cik_get_csb_size(struct radeon_device *rdev)
6670 const struct cs_section_def *sect = NULL;
6671 const struct cs_extent_def *ext = NULL;
6673 if (rdev->rlc.cs_data == NULL)
6676 /* begin clear state */
6678 /* context control state */
6681 for (sect = rdev->rlc.cs_data; sect->section != NULL; ++sect) {
6682 for (ext = sect->section; ext->extent != NULL; ++ext) {
6683 if (sect->id == SECT_CONTEXT)
6684 count += 2 + ext->reg_count;
6689 /* pa_sc_raster_config/pa_sc_raster_config1 */
6691 /* end clear state */
6699 void cik_get_csb_buffer(struct radeon_device *rdev, volatile u32 *buffer)
6702 const struct cs_section_def *sect = NULL;
6703 const struct cs_extent_def *ext = NULL;
6705 if (rdev->rlc.cs_data == NULL)
6710 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
6711 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
6713 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
6714 buffer[count++] = cpu_to_le32(0x80000000);
6715 buffer[count++] = cpu_to_le32(0x80000000);
6717 for (sect = rdev->rlc.cs_data; sect->section != NULL; ++sect) {
6718 for (ext = sect->section; ext->extent != NULL; ++ext) {
6719 if (sect->id == SECT_CONTEXT) {
6721 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
6722 buffer[count++] = cpu_to_le32(ext->reg_index - 0xa000);
6723 for (i = 0; i < ext->reg_count; i++)
6724 buffer[count++] = cpu_to_le32(ext->extent[i]);
6731 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 2));
6732 buffer[count++] = cpu_to_le32(PA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);
6733 switch (rdev->family) {
6735 buffer[count++] = cpu_to_le32(0x16000012);
6736 buffer[count++] = cpu_to_le32(0x00000000);
6739 buffer[count++] = cpu_to_le32(0x00000000); /* XXX */
6740 buffer[count++] = cpu_to_le32(0x00000000);
6744 buffer[count++] = cpu_to_le32(0x00000000); /* XXX */
6745 buffer[count++] = cpu_to_le32(0x00000000);
6748 buffer[count++] = cpu_to_le32(0x3a00161a);
6749 buffer[count++] = cpu_to_le32(0x0000002e);
6752 buffer[count++] = cpu_to_le32(0x00000000);
6753 buffer[count++] = cpu_to_le32(0x00000000);
6757 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
6758 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
6760 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
6761 buffer[count++] = cpu_to_le32(0);
6764 static void cik_init_pg(struct radeon_device *rdev)
6766 if (rdev->pg_flags) {
6767 cik_enable_sck_slowdown_on_pu(rdev, true);
6768 cik_enable_sck_slowdown_on_pd(rdev, true);
6769 if (rdev->pg_flags & RADEON_PG_SUPPORT_GFX_PG) {
6770 cik_init_gfx_cgpg(rdev);
6771 cik_enable_cp_pg(rdev, true);
6772 cik_enable_gds_pg(rdev, true);
6774 cik_init_ao_cu_mask(rdev);
6775 cik_update_gfx_pg(rdev, true);
6779 static void cik_fini_pg(struct radeon_device *rdev)
6781 if (rdev->pg_flags) {
6782 cik_update_gfx_pg(rdev, false);
6783 if (rdev->pg_flags & RADEON_PG_SUPPORT_GFX_PG) {
6784 cik_enable_cp_pg(rdev, false);
6785 cik_enable_gds_pg(rdev, false);
6792 * Starting with r6xx, interrupts are handled via a ring buffer.
6793 * Ring buffers are areas of GPU accessible memory that the GPU
6794 * writes interrupt vectors into and the host reads vectors out of.
6795 * There is a rptr (read pointer) that determines where the
6796 * host is currently reading, and a wptr (write pointer)
6797 * which determines where the GPU has written. When the
6798 * pointers are equal, the ring is idle. When the GPU
6799 * writes vectors to the ring buffer, it increments the
6800 * wptr. When there is an interrupt, the host then starts
6801 * fetching commands and processing them until the pointers are
6802 * equal again at which point it updates the rptr.
6806 * cik_enable_interrupts - Enable the interrupt ring buffer
6808 * @rdev: radeon_device pointer
6810 * Enable the interrupt ring buffer (CIK).
6812 static void cik_enable_interrupts(struct radeon_device *rdev)
6814 u32 ih_cntl = RREG32(IH_CNTL);
6815 u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
6817 ih_cntl |= ENABLE_INTR;
6818 ih_rb_cntl |= IH_RB_ENABLE;
6819 WREG32(IH_CNTL, ih_cntl);
6820 WREG32(IH_RB_CNTL, ih_rb_cntl);
6821 rdev->ih.enabled = true;
6825 * cik_disable_interrupts - Disable the interrupt ring buffer
6827 * @rdev: radeon_device pointer
6829 * Disable the interrupt ring buffer (CIK).
6831 static void cik_disable_interrupts(struct radeon_device *rdev)
6833 u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
6834 u32 ih_cntl = RREG32(IH_CNTL);
6836 ih_rb_cntl &= ~IH_RB_ENABLE;
6837 ih_cntl &= ~ENABLE_INTR;
6838 WREG32(IH_RB_CNTL, ih_rb_cntl);
6839 WREG32(IH_CNTL, ih_cntl);
6840 /* set rptr, wptr to 0 */
6841 WREG32(IH_RB_RPTR, 0);
6842 WREG32(IH_RB_WPTR, 0);
6843 rdev->ih.enabled = false;
6848 * cik_disable_interrupt_state - Disable all interrupt sources
6850 * @rdev: radeon_device pointer
6852 * Clear all interrupt enable bits used by the driver (CIK).
6854 static void cik_disable_interrupt_state(struct radeon_device *rdev)
6859 tmp = RREG32(CP_INT_CNTL_RING0) &
6860 (CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
6861 WREG32(CP_INT_CNTL_RING0, tmp);
6863 tmp = RREG32(SDMA0_CNTL + SDMA0_REGISTER_OFFSET) & ~TRAP_ENABLE;
6864 WREG32(SDMA0_CNTL + SDMA0_REGISTER_OFFSET, tmp);
6865 tmp = RREG32(SDMA0_CNTL + SDMA1_REGISTER_OFFSET) & ~TRAP_ENABLE;
6866 WREG32(SDMA0_CNTL + SDMA1_REGISTER_OFFSET, tmp);
6867 /* compute queues */
6868 WREG32(CP_ME1_PIPE0_INT_CNTL, 0);
6869 WREG32(CP_ME1_PIPE1_INT_CNTL, 0);
6870 WREG32(CP_ME1_PIPE2_INT_CNTL, 0);
6871 WREG32(CP_ME1_PIPE3_INT_CNTL, 0);
6872 WREG32(CP_ME2_PIPE0_INT_CNTL, 0);
6873 WREG32(CP_ME2_PIPE1_INT_CNTL, 0);
6874 WREG32(CP_ME2_PIPE2_INT_CNTL, 0);
6875 WREG32(CP_ME2_PIPE3_INT_CNTL, 0);
6877 WREG32(GRBM_INT_CNTL, 0);
6879 WREG32(SRBM_INT_CNTL, 0);
6880 /* vline/vblank, etc. */
6881 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
6882 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
6883 if (rdev->num_crtc >= 4) {
6884 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
6885 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
6887 if (rdev->num_crtc >= 6) {
6888 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
6889 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
6892 if (rdev->num_crtc >= 2) {
6893 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
6894 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
6896 if (rdev->num_crtc >= 4) {
6897 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
6898 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
6900 if (rdev->num_crtc >= 6) {
6901 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
6902 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
6906 WREG32(DAC_AUTODETECT_INT_CONTROL, 0);
6908 /* digital hotplug */
6909 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
6910 WREG32(DC_HPD1_INT_CONTROL, tmp);
6911 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
6912 WREG32(DC_HPD2_INT_CONTROL, tmp);
6913 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
6914 WREG32(DC_HPD3_INT_CONTROL, tmp);
6915 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
6916 WREG32(DC_HPD4_INT_CONTROL, tmp);
6917 tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
6918 WREG32(DC_HPD5_INT_CONTROL, tmp);
6919 tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
6920 WREG32(DC_HPD6_INT_CONTROL, tmp);
6925 * cik_irq_init - init and enable the interrupt ring
6927 * @rdev: radeon_device pointer
6929 * Allocate a ring buffer for the interrupt controller,
6930 * enable the RLC, disable interrupts, enable the IH
6931 * ring buffer and enable it (CIK).
6932 * Called at device load and reume.
6933 * Returns 0 for success, errors for failure.
6935 static int cik_irq_init(struct radeon_device *rdev)
6939 u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
6942 ret = r600_ih_ring_alloc(rdev);
6947 cik_disable_interrupts(rdev);
6950 ret = cik_rlc_resume(rdev);
6952 r600_ih_ring_fini(rdev);
6956 /* setup interrupt control */
6957 /* set dummy read address to dummy page address */
6958 WREG32(INTERRUPT_CNTL2, rdev->dummy_page.addr >> 8);
6959 interrupt_cntl = RREG32(INTERRUPT_CNTL);
6960 /* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled without msi
6961 * IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_EN
6963 interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE;
6964 /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */
6965 interrupt_cntl &= ~IH_REQ_NONSNOOP_EN;
6966 WREG32(INTERRUPT_CNTL, interrupt_cntl);
6968 WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8);
6969 rb_bufsz = order_base_2(rdev->ih.ring_size / 4);
6971 ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE |
6972 IH_WPTR_OVERFLOW_CLEAR |
6975 if (rdev->wb.enabled)
6976 ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE;
6978 /* set the writeback address whether it's enabled or not */
6979 WREG32(IH_RB_WPTR_ADDR_LO, (rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFFFFFFFC);
6980 WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF);
6982 WREG32(IH_RB_CNTL, ih_rb_cntl);
6984 /* set rptr, wptr to 0 */
6985 WREG32(IH_RB_RPTR, 0);
6986 WREG32(IH_RB_WPTR, 0);
6988 /* Default settings for IH_CNTL (disabled at first) */
6989 ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10) | MC_VMID(0);
6990 /* RPTR_REARM only works if msi's are enabled */
6991 if (rdev->msi_enabled)
6992 ih_cntl |= RPTR_REARM;
6993 WREG32(IH_CNTL, ih_cntl);
6995 /* force the active interrupt state to all disabled */
6996 cik_disable_interrupt_state(rdev);
6998 pci_set_master(rdev->pdev);
7001 cik_enable_interrupts(rdev);
7007 * cik_irq_set - enable/disable interrupt sources
7009 * @rdev: radeon_device pointer
7011 * Enable interrupt sources on the GPU (vblanks, hpd,
7013 * Returns 0 for success, errors for failure.
7015 int cik_irq_set(struct radeon_device *rdev)
7018 u32 cp_m1p0, cp_m1p1, cp_m1p2, cp_m1p3;
7019 u32 cp_m2p0, cp_m2p1, cp_m2p2, cp_m2p3;
7020 u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0;
7021 u32 hpd1, hpd2, hpd3, hpd4, hpd5, hpd6;
7022 u32 grbm_int_cntl = 0;
7023 u32 dma_cntl, dma_cntl1;
7025 if (!rdev->irq.installed) {
7026 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
7029 /* don't enable anything if the ih is disabled */
7030 if (!rdev->ih.enabled) {
7031 cik_disable_interrupts(rdev);
7032 /* force the active interrupt state to all disabled */
7033 cik_disable_interrupt_state(rdev);
7037 cp_int_cntl = RREG32(CP_INT_CNTL_RING0) &
7038 (CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
7039 cp_int_cntl |= PRIV_INSTR_INT_ENABLE | PRIV_REG_INT_ENABLE;
7041 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN);
7042 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN);
7043 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN);
7044 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN);
7045 hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN);
7046 hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN);
7048 dma_cntl = RREG32(SDMA0_CNTL + SDMA0_REGISTER_OFFSET) & ~TRAP_ENABLE;
7049 dma_cntl1 = RREG32(SDMA0_CNTL + SDMA1_REGISTER_OFFSET) & ~TRAP_ENABLE;
7051 cp_m1p0 = RREG32(CP_ME1_PIPE0_INT_CNTL) & ~TIME_STAMP_INT_ENABLE;
7052 cp_m1p1 = RREG32(CP_ME1_PIPE1_INT_CNTL) & ~TIME_STAMP_INT_ENABLE;
7053 cp_m1p2 = RREG32(CP_ME1_PIPE2_INT_CNTL) & ~TIME_STAMP_INT_ENABLE;
7054 cp_m1p3 = RREG32(CP_ME1_PIPE3_INT_CNTL) & ~TIME_STAMP_INT_ENABLE;
7055 cp_m2p0 = RREG32(CP_ME2_PIPE0_INT_CNTL) & ~TIME_STAMP_INT_ENABLE;
7056 cp_m2p1 = RREG32(CP_ME2_PIPE1_INT_CNTL) & ~TIME_STAMP_INT_ENABLE;
7057 cp_m2p2 = RREG32(CP_ME2_PIPE2_INT_CNTL) & ~TIME_STAMP_INT_ENABLE;
7058 cp_m2p3 = RREG32(CP_ME2_PIPE3_INT_CNTL) & ~TIME_STAMP_INT_ENABLE;
7060 /* enable CP interrupts on all rings */
7061 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
7062 DRM_DEBUG("cik_irq_set: sw int gfx\n");
7063 cp_int_cntl |= TIME_STAMP_INT_ENABLE;
7065 if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_CP1_INDEX])) {
7066 struct radeon_ring *ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX];
7067 DRM_DEBUG("si_irq_set: sw int cp1\n");
7068 if (ring->me == 1) {
7069 switch (ring->pipe) {
7071 cp_m1p0 |= TIME_STAMP_INT_ENABLE;
7074 cp_m1p1 |= TIME_STAMP_INT_ENABLE;
7077 cp_m1p2 |= TIME_STAMP_INT_ENABLE;
7080 cp_m1p2 |= TIME_STAMP_INT_ENABLE;
7083 DRM_DEBUG("si_irq_set: sw int cp1 invalid pipe %d\n", ring->pipe);
7086 } else if (ring->me == 2) {
7087 switch (ring->pipe) {
7089 cp_m2p0 |= TIME_STAMP_INT_ENABLE;
7092 cp_m2p1 |= TIME_STAMP_INT_ENABLE;
7095 cp_m2p2 |= TIME_STAMP_INT_ENABLE;
7098 cp_m2p2 |= TIME_STAMP_INT_ENABLE;
7101 DRM_DEBUG("si_irq_set: sw int cp1 invalid pipe %d\n", ring->pipe);
7105 DRM_DEBUG("si_irq_set: sw int cp1 invalid me %d\n", ring->me);
7108 if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_CP2_INDEX])) {
7109 struct radeon_ring *ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX];
7110 DRM_DEBUG("si_irq_set: sw int cp2\n");
7111 if (ring->me == 1) {
7112 switch (ring->pipe) {
7114 cp_m1p0 |= TIME_STAMP_INT_ENABLE;
7117 cp_m1p1 |= TIME_STAMP_INT_ENABLE;
7120 cp_m1p2 |= TIME_STAMP_INT_ENABLE;
7123 cp_m1p2 |= TIME_STAMP_INT_ENABLE;
7126 DRM_DEBUG("si_irq_set: sw int cp2 invalid pipe %d\n", ring->pipe);
7129 } else if (ring->me == 2) {
7130 switch (ring->pipe) {
7132 cp_m2p0 |= TIME_STAMP_INT_ENABLE;
7135 cp_m2p1 |= TIME_STAMP_INT_ENABLE;
7138 cp_m2p2 |= TIME_STAMP_INT_ENABLE;
7141 cp_m2p2 |= TIME_STAMP_INT_ENABLE;
7144 DRM_DEBUG("si_irq_set: sw int cp2 invalid pipe %d\n", ring->pipe);
7148 DRM_DEBUG("si_irq_set: sw int cp2 invalid me %d\n", ring->me);
7152 if (atomic_read(&rdev->irq.ring_int[R600_RING_TYPE_DMA_INDEX])) {
7153 DRM_DEBUG("cik_irq_set: sw int dma\n");
7154 dma_cntl |= TRAP_ENABLE;
7157 if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_DMA1_INDEX])) {
7158 DRM_DEBUG("cik_irq_set: sw int dma1\n");
7159 dma_cntl1 |= TRAP_ENABLE;
7162 if (rdev->irq.crtc_vblank_int[0] ||
7163 atomic_read(&rdev->irq.pflip[0])) {
7164 DRM_DEBUG("cik_irq_set: vblank 0\n");
7165 crtc1 |= VBLANK_INTERRUPT_MASK;
7167 if (rdev->irq.crtc_vblank_int[1] ||
7168 atomic_read(&rdev->irq.pflip[1])) {
7169 DRM_DEBUG("cik_irq_set: vblank 1\n");
7170 crtc2 |= VBLANK_INTERRUPT_MASK;
7172 if (rdev->irq.crtc_vblank_int[2] ||
7173 atomic_read(&rdev->irq.pflip[2])) {
7174 DRM_DEBUG("cik_irq_set: vblank 2\n");
7175 crtc3 |= VBLANK_INTERRUPT_MASK;
7177 if (rdev->irq.crtc_vblank_int[3] ||
7178 atomic_read(&rdev->irq.pflip[3])) {
7179 DRM_DEBUG("cik_irq_set: vblank 3\n");
7180 crtc4 |= VBLANK_INTERRUPT_MASK;
7182 if (rdev->irq.crtc_vblank_int[4] ||
7183 atomic_read(&rdev->irq.pflip[4])) {
7184 DRM_DEBUG("cik_irq_set: vblank 4\n");
7185 crtc5 |= VBLANK_INTERRUPT_MASK;
7187 if (rdev->irq.crtc_vblank_int[5] ||
7188 atomic_read(&rdev->irq.pflip[5])) {
7189 DRM_DEBUG("cik_irq_set: vblank 5\n");
7190 crtc6 |= VBLANK_INTERRUPT_MASK;
7192 if (rdev->irq.hpd[0]) {
7193 DRM_DEBUG("cik_irq_set: hpd 1\n");
7194 hpd1 |= DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN;
7196 if (rdev->irq.hpd[1]) {
7197 DRM_DEBUG("cik_irq_set: hpd 2\n");
7198 hpd2 |= DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN;
7200 if (rdev->irq.hpd[2]) {
7201 DRM_DEBUG("cik_irq_set: hpd 3\n");
7202 hpd3 |= DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN;
7204 if (rdev->irq.hpd[3]) {
7205 DRM_DEBUG("cik_irq_set: hpd 4\n");
7206 hpd4 |= DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN;
7208 if (rdev->irq.hpd[4]) {
7209 DRM_DEBUG("cik_irq_set: hpd 5\n");
7210 hpd5 |= DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN;
7212 if (rdev->irq.hpd[5]) {
7213 DRM_DEBUG("cik_irq_set: hpd 6\n");
7214 hpd6 |= DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN;
7217 WREG32(CP_INT_CNTL_RING0, cp_int_cntl);
7219 WREG32(SDMA0_CNTL + SDMA0_REGISTER_OFFSET, dma_cntl);
7220 WREG32(SDMA0_CNTL + SDMA1_REGISTER_OFFSET, dma_cntl1);
7222 WREG32(CP_ME1_PIPE0_INT_CNTL, cp_m1p0);
7223 WREG32(CP_ME1_PIPE1_INT_CNTL, cp_m1p1);
7224 WREG32(CP_ME1_PIPE2_INT_CNTL, cp_m1p2);
7225 WREG32(CP_ME1_PIPE3_INT_CNTL, cp_m1p3);
7226 WREG32(CP_ME2_PIPE0_INT_CNTL, cp_m2p0);
7227 WREG32(CP_ME2_PIPE1_INT_CNTL, cp_m2p1);
7228 WREG32(CP_ME2_PIPE2_INT_CNTL, cp_m2p2);
7229 WREG32(CP_ME2_PIPE3_INT_CNTL, cp_m2p3);
7231 WREG32(GRBM_INT_CNTL, grbm_int_cntl);
7233 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1);
7234 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2);
7235 if (rdev->num_crtc >= 4) {
7236 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, crtc3);
7237 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, crtc4);
7239 if (rdev->num_crtc >= 6) {
7240 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, crtc5);
7241 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6);
7244 if (rdev->num_crtc >= 2) {
7245 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET,
7246 GRPH_PFLIP_INT_MASK);
7247 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET,
7248 GRPH_PFLIP_INT_MASK);
7250 if (rdev->num_crtc >= 4) {
7251 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET,
7252 GRPH_PFLIP_INT_MASK);
7253 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET,
7254 GRPH_PFLIP_INT_MASK);
7256 if (rdev->num_crtc >= 6) {
7257 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET,
7258 GRPH_PFLIP_INT_MASK);
7259 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET,
7260 GRPH_PFLIP_INT_MASK);
7263 WREG32(DC_HPD1_INT_CONTROL, hpd1);
7264 WREG32(DC_HPD2_INT_CONTROL, hpd2);
7265 WREG32(DC_HPD3_INT_CONTROL, hpd3);
7266 WREG32(DC_HPD4_INT_CONTROL, hpd4);
7267 WREG32(DC_HPD5_INT_CONTROL, hpd5);
7268 WREG32(DC_HPD6_INT_CONTROL, hpd6);
7271 RREG32(SRBM_STATUS);
7277 * cik_irq_ack - ack interrupt sources
7279 * @rdev: radeon_device pointer
7281 * Ack interrupt sources on the GPU (vblanks, hpd,
7282 * etc.) (CIK). Certain interrupts sources are sw
7283 * generated and do not require an explicit ack.
7285 static inline void cik_irq_ack(struct radeon_device *rdev)
7289 rdev->irq.stat_regs.cik.disp_int = RREG32(DISP_INTERRUPT_STATUS);
7290 rdev->irq.stat_regs.cik.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
7291 rdev->irq.stat_regs.cik.disp_int_cont2 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE2);
7292 rdev->irq.stat_regs.cik.disp_int_cont3 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE3);
7293 rdev->irq.stat_regs.cik.disp_int_cont4 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE4);
7294 rdev->irq.stat_regs.cik.disp_int_cont5 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE5);
7295 rdev->irq.stat_regs.cik.disp_int_cont6 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE6);
7297 rdev->irq.stat_regs.cik.d1grph_int = RREG32(GRPH_INT_STATUS +
7298 EVERGREEN_CRTC0_REGISTER_OFFSET);
7299 rdev->irq.stat_regs.cik.d2grph_int = RREG32(GRPH_INT_STATUS +
7300 EVERGREEN_CRTC1_REGISTER_OFFSET);
7301 if (rdev->num_crtc >= 4) {
7302 rdev->irq.stat_regs.cik.d3grph_int = RREG32(GRPH_INT_STATUS +
7303 EVERGREEN_CRTC2_REGISTER_OFFSET);
7304 rdev->irq.stat_regs.cik.d4grph_int = RREG32(GRPH_INT_STATUS +
7305 EVERGREEN_CRTC3_REGISTER_OFFSET);
7307 if (rdev->num_crtc >= 6) {
7308 rdev->irq.stat_regs.cik.d5grph_int = RREG32(GRPH_INT_STATUS +
7309 EVERGREEN_CRTC4_REGISTER_OFFSET);
7310 rdev->irq.stat_regs.cik.d6grph_int = RREG32(GRPH_INT_STATUS +
7311 EVERGREEN_CRTC5_REGISTER_OFFSET);
7314 if (rdev->irq.stat_regs.cik.d1grph_int & GRPH_PFLIP_INT_OCCURRED)
7315 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET,
7316 GRPH_PFLIP_INT_CLEAR);
7317 if (rdev->irq.stat_regs.cik.d2grph_int & GRPH_PFLIP_INT_OCCURRED)
7318 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET,
7319 GRPH_PFLIP_INT_CLEAR);
7320 if (rdev->irq.stat_regs.cik.disp_int & LB_D1_VBLANK_INTERRUPT)
7321 WREG32(LB_VBLANK_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VBLANK_ACK);
7322 if (rdev->irq.stat_regs.cik.disp_int & LB_D1_VLINE_INTERRUPT)
7323 WREG32(LB_VLINE_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VLINE_ACK);
7324 if (rdev->irq.stat_regs.cik.disp_int_cont & LB_D2_VBLANK_INTERRUPT)
7325 WREG32(LB_VBLANK_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VBLANK_ACK);
7326 if (rdev->irq.stat_regs.cik.disp_int_cont & LB_D2_VLINE_INTERRUPT)
7327 WREG32(LB_VLINE_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VLINE_ACK);
7329 if (rdev->num_crtc >= 4) {
7330 if (rdev->irq.stat_regs.cik.d3grph_int & GRPH_PFLIP_INT_OCCURRED)
7331 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET,
7332 GRPH_PFLIP_INT_CLEAR);
7333 if (rdev->irq.stat_regs.cik.d4grph_int & GRPH_PFLIP_INT_OCCURRED)
7334 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET,
7335 GRPH_PFLIP_INT_CLEAR);
7336 if (rdev->irq.stat_regs.cik.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT)
7337 WREG32(LB_VBLANK_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VBLANK_ACK);
7338 if (rdev->irq.stat_regs.cik.disp_int_cont2 & LB_D3_VLINE_INTERRUPT)
7339 WREG32(LB_VLINE_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VLINE_ACK);
7340 if (rdev->irq.stat_regs.cik.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT)
7341 WREG32(LB_VBLANK_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VBLANK_ACK);
7342 if (rdev->irq.stat_regs.cik.disp_int_cont3 & LB_D4_VLINE_INTERRUPT)
7343 WREG32(LB_VLINE_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VLINE_ACK);
7346 if (rdev->num_crtc >= 6) {
7347 if (rdev->irq.stat_regs.cik.d5grph_int & GRPH_PFLIP_INT_OCCURRED)
7348 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET,
7349 GRPH_PFLIP_INT_CLEAR);
7350 if (rdev->irq.stat_regs.cik.d6grph_int & GRPH_PFLIP_INT_OCCURRED)
7351 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET,
7352 GRPH_PFLIP_INT_CLEAR);
7353 if (rdev->irq.stat_regs.cik.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT)
7354 WREG32(LB_VBLANK_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VBLANK_ACK);
7355 if (rdev->irq.stat_regs.cik.disp_int_cont4 & LB_D5_VLINE_INTERRUPT)
7356 WREG32(LB_VLINE_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VLINE_ACK);
7357 if (rdev->irq.stat_regs.cik.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT)
7358 WREG32(LB_VBLANK_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VBLANK_ACK);
7359 if (rdev->irq.stat_regs.cik.disp_int_cont5 & LB_D6_VLINE_INTERRUPT)
7360 WREG32(LB_VLINE_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VLINE_ACK);
7363 if (rdev->irq.stat_regs.cik.disp_int & DC_HPD1_INTERRUPT) {
7364 tmp = RREG32(DC_HPD1_INT_CONTROL);
7365 tmp |= DC_HPDx_INT_ACK;
7366 WREG32(DC_HPD1_INT_CONTROL, tmp);
7368 if (rdev->irq.stat_regs.cik.disp_int_cont & DC_HPD2_INTERRUPT) {
7369 tmp = RREG32(DC_HPD2_INT_CONTROL);
7370 tmp |= DC_HPDx_INT_ACK;
7371 WREG32(DC_HPD2_INT_CONTROL, tmp);
7373 if (rdev->irq.stat_regs.cik.disp_int_cont2 & DC_HPD3_INTERRUPT) {
7374 tmp = RREG32(DC_HPD3_INT_CONTROL);
7375 tmp |= DC_HPDx_INT_ACK;
7376 WREG32(DC_HPD3_INT_CONTROL, tmp);
7378 if (rdev->irq.stat_regs.cik.disp_int_cont3 & DC_HPD4_INTERRUPT) {
7379 tmp = RREG32(DC_HPD4_INT_CONTROL);
7380 tmp |= DC_HPDx_INT_ACK;
7381 WREG32(DC_HPD4_INT_CONTROL, tmp);
7383 if (rdev->irq.stat_regs.cik.disp_int_cont4 & DC_HPD5_INTERRUPT) {
7384 tmp = RREG32(DC_HPD5_INT_CONTROL);
7385 tmp |= DC_HPDx_INT_ACK;
7386 WREG32(DC_HPD5_INT_CONTROL, tmp);
7388 if (rdev->irq.stat_regs.cik.disp_int_cont5 & DC_HPD6_INTERRUPT) {
7389 tmp = RREG32(DC_HPD6_INT_CONTROL);
7390 tmp |= DC_HPDx_INT_ACK;
7391 WREG32(DC_HPD6_INT_CONTROL, tmp);
7393 if (rdev->irq.stat_regs.cik.disp_int & DC_HPD1_RX_INTERRUPT) {
7394 tmp = RREG32(DC_HPD1_INT_CONTROL);
7395 tmp |= DC_HPDx_RX_INT_ACK;
7396 WREG32(DC_HPD1_INT_CONTROL, tmp);
7398 if (rdev->irq.stat_regs.cik.disp_int_cont & DC_HPD2_RX_INTERRUPT) {
7399 tmp = RREG32(DC_HPD2_INT_CONTROL);
7400 tmp |= DC_HPDx_RX_INT_ACK;
7401 WREG32(DC_HPD2_INT_CONTROL, tmp);
7403 if (rdev->irq.stat_regs.cik.disp_int_cont2 & DC_HPD3_RX_INTERRUPT) {
7404 tmp = RREG32(DC_HPD3_INT_CONTROL);
7405 tmp |= DC_HPDx_RX_INT_ACK;
7406 WREG32(DC_HPD3_INT_CONTROL, tmp);
7408 if (rdev->irq.stat_regs.cik.disp_int_cont3 & DC_HPD4_RX_INTERRUPT) {
7409 tmp = RREG32(DC_HPD4_INT_CONTROL);
7410 tmp |= DC_HPDx_RX_INT_ACK;
7411 WREG32(DC_HPD4_INT_CONTROL, tmp);
7413 if (rdev->irq.stat_regs.cik.disp_int_cont4 & DC_HPD5_RX_INTERRUPT) {
7414 tmp = RREG32(DC_HPD5_INT_CONTROL);
7415 tmp |= DC_HPDx_RX_INT_ACK;
7416 WREG32(DC_HPD5_INT_CONTROL, tmp);
7418 if (rdev->irq.stat_regs.cik.disp_int_cont5 & DC_HPD6_RX_INTERRUPT) {
7419 tmp = RREG32(DC_HPD6_INT_CONTROL);
7420 tmp |= DC_HPDx_RX_INT_ACK;
7421 WREG32(DC_HPD6_INT_CONTROL, tmp);
7426 * cik_irq_disable - disable interrupts
7428 * @rdev: radeon_device pointer
7430 * Disable interrupts on the hw (CIK).
7432 static void cik_irq_disable(struct radeon_device *rdev)
7434 cik_disable_interrupts(rdev);
7435 /* Wait and acknowledge irq */
7438 cik_disable_interrupt_state(rdev);
7442 * cik_irq_suspend - disable interrupts for suspend
7444 * @rdev: radeon_device pointer
7446 * Disable interrupts and stop the RLC (CIK).
7449 static void cik_irq_suspend(struct radeon_device *rdev)
7451 cik_irq_disable(rdev);
7456 * cik_irq_fini - tear down interrupt support
7458 * @rdev: radeon_device pointer
7460 * Disable interrupts on the hw and free the IH ring
7462 * Used for driver unload.
7464 static void cik_irq_fini(struct radeon_device *rdev)
7466 cik_irq_suspend(rdev);
7467 r600_ih_ring_fini(rdev);
7471 * cik_get_ih_wptr - get the IH ring buffer wptr
7473 * @rdev: radeon_device pointer
7475 * Get the IH ring buffer wptr from either the register
7476 * or the writeback memory buffer (CIK). Also check for
7477 * ring buffer overflow and deal with it.
7478 * Used by cik_irq_process().
7479 * Returns the value of the wptr.
7481 static inline u32 cik_get_ih_wptr(struct radeon_device *rdev)
7485 if (rdev->wb.enabled)
7486 wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]);
7488 wptr = RREG32(IH_RB_WPTR);
7490 if (wptr & RB_OVERFLOW) {
7491 wptr &= ~RB_OVERFLOW;
7492 /* When a ring buffer overflow happen start parsing interrupt
7493 * from the last not overwritten vector (wptr + 16). Hopefully
7494 * this should allow us to catchup.
7496 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n",
7497 wptr, rdev->ih.rptr, (wptr + 16) & rdev->ih.ptr_mask);
7498 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
7499 tmp = RREG32(IH_RB_CNTL);
7500 tmp |= IH_WPTR_OVERFLOW_CLEAR;
7501 WREG32(IH_RB_CNTL, tmp);
7503 return (wptr & rdev->ih.ptr_mask);
7507 * Each IV ring entry is 128 bits:
7508 * [7:0] - interrupt source id
7510 * [59:32] - interrupt source data
7511 * [63:60] - reserved
7514 * ME_ID [1:0], PIPE_ID[1:0], QUEUE_ID[2:0]
7515 * QUEUE_ID - for compute, which of the 8 queues owned by the dispatcher
7516 * - for gfx, hw shader state (0=PS...5=LS, 6=CS)
7517 * ME_ID - 0 = gfx, 1 = first 4 CS pipes, 2 = second 4 CS pipes
7518 * PIPE_ID - ME0 0=3D
7519 * - ME1&2 compute dispatcher (4 pipes each)
7521 * INSTANCE_ID [1:0], QUEUE_ID[1:0]
7522 * INSTANCE_ID - 0 = sdma0, 1 = sdma1
7523 * QUEUE_ID - 0 = gfx, 1 = rlc0, 2 = rlc1
7526 * [127:96] - reserved
7529 * cik_irq_process - interrupt handler
7531 * @rdev: radeon_device pointer
7533 * Interrupt hander (CIK). Walk the IH ring,
7534 * ack interrupts and schedule work to handle
7536 * Returns irq process return code.
7538 int cik_irq_process(struct radeon_device *rdev)
7540 struct radeon_ring *cp1_ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX];
7541 struct radeon_ring *cp2_ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX];
7544 u32 src_id, src_data, ring_id;
7545 u8 me_id, pipe_id, queue_id;
7547 bool queue_hotplug = false;
7548 bool queue_dp = false;
7549 bool queue_reset = false;
7550 u32 addr, status, mc_client;
7551 bool queue_thermal = false;
7553 if (!rdev->ih.enabled || rdev->shutdown)
7556 wptr = cik_get_ih_wptr(rdev);
7559 /* is somebody else already processing irqs? */
7560 if (atomic_xchg(&rdev->ih.lock, 1))
7563 rptr = rdev->ih.rptr;
7564 DRM_DEBUG("cik_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
7566 /* Order reading of wptr vs. reading of IH ring data */
7569 /* display interrupts */
7572 while (rptr != wptr) {
7573 /* wptr/rptr are in bytes! */
7574 ring_index = rptr / 4;
7576 src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff;
7577 src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff;
7578 ring_id = le32_to_cpu(rdev->ih.ring[ring_index + 2]) & 0xff;
7581 case 1: /* D1 vblank/vline */
7583 case 0: /* D1 vblank */
7584 if (!(rdev->irq.stat_regs.cik.disp_int & LB_D1_VBLANK_INTERRUPT))
7585 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
7587 if (rdev->irq.crtc_vblank_int[0]) {
7588 drm_handle_vblank(rdev->ddev, 0);
7589 rdev->pm.vblank_sync = true;
7590 wake_up(&rdev->irq.vblank_queue);
7592 if (atomic_read(&rdev->irq.pflip[0]))
7593 radeon_crtc_handle_vblank(rdev, 0);
7594 rdev->irq.stat_regs.cik.disp_int &= ~LB_D1_VBLANK_INTERRUPT;
7595 DRM_DEBUG("IH: D1 vblank\n");
7598 case 1: /* D1 vline */
7599 if (!(rdev->irq.stat_regs.cik.disp_int & LB_D1_VLINE_INTERRUPT))
7600 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
7602 rdev->irq.stat_regs.cik.disp_int &= ~LB_D1_VLINE_INTERRUPT;
7603 DRM_DEBUG("IH: D1 vline\n");
7607 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
7611 case 2: /* D2 vblank/vline */
7613 case 0: /* D2 vblank */
7614 if (!(rdev->irq.stat_regs.cik.disp_int_cont & LB_D2_VBLANK_INTERRUPT))
7615 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
7617 if (rdev->irq.crtc_vblank_int[1]) {
7618 drm_handle_vblank(rdev->ddev, 1);
7619 rdev->pm.vblank_sync = true;
7620 wake_up(&rdev->irq.vblank_queue);
7622 if (atomic_read(&rdev->irq.pflip[1]))
7623 radeon_crtc_handle_vblank(rdev, 1);
7624 rdev->irq.stat_regs.cik.disp_int_cont &= ~LB_D2_VBLANK_INTERRUPT;
7625 DRM_DEBUG("IH: D2 vblank\n");
7628 case 1: /* D2 vline */
7629 if (!(rdev->irq.stat_regs.cik.disp_int_cont & LB_D2_VLINE_INTERRUPT))
7630 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
7632 rdev->irq.stat_regs.cik.disp_int_cont &= ~LB_D2_VLINE_INTERRUPT;
7633 DRM_DEBUG("IH: D2 vline\n");
7637 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
7641 case 3: /* D3 vblank/vline */
7643 case 0: /* D3 vblank */
7644 if (!(rdev->irq.stat_regs.cik.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT))
7645 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
7647 if (rdev->irq.crtc_vblank_int[2]) {
7648 drm_handle_vblank(rdev->ddev, 2);
7649 rdev->pm.vblank_sync = true;
7650 wake_up(&rdev->irq.vblank_queue);
7652 if (atomic_read(&rdev->irq.pflip[2]))
7653 radeon_crtc_handle_vblank(rdev, 2);
7654 rdev->irq.stat_regs.cik.disp_int_cont2 &= ~LB_D3_VBLANK_INTERRUPT;
7655 DRM_DEBUG("IH: D3 vblank\n");
7658 case 1: /* D3 vline */
7659 if (!(rdev->irq.stat_regs.cik.disp_int_cont2 & LB_D3_VLINE_INTERRUPT))
7660 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
7662 rdev->irq.stat_regs.cik.disp_int_cont2 &= ~LB_D3_VLINE_INTERRUPT;
7663 DRM_DEBUG("IH: D3 vline\n");
7667 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
7671 case 4: /* D4 vblank/vline */
7673 case 0: /* D4 vblank */
7674 if (!(rdev->irq.stat_regs.cik.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT))
7675 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
7677 if (rdev->irq.crtc_vblank_int[3]) {
7678 drm_handle_vblank(rdev->ddev, 3);
7679 rdev->pm.vblank_sync = true;
7680 wake_up(&rdev->irq.vblank_queue);
7682 if (atomic_read(&rdev->irq.pflip[3]))
7683 radeon_crtc_handle_vblank(rdev, 3);
7684 rdev->irq.stat_regs.cik.disp_int_cont3 &= ~LB_D4_VBLANK_INTERRUPT;
7685 DRM_DEBUG("IH: D4 vblank\n");
7688 case 1: /* D4 vline */
7689 if (!(rdev->irq.stat_regs.cik.disp_int_cont3 & LB_D4_VLINE_INTERRUPT))
7690 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
7692 rdev->irq.stat_regs.cik.disp_int_cont3 &= ~LB_D4_VLINE_INTERRUPT;
7693 DRM_DEBUG("IH: D4 vline\n");
7697 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
7701 case 5: /* D5 vblank/vline */
7703 case 0: /* D5 vblank */
7704 if (!(rdev->irq.stat_regs.cik.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT))
7705 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
7707 if (rdev->irq.crtc_vblank_int[4]) {
7708 drm_handle_vblank(rdev->ddev, 4);
7709 rdev->pm.vblank_sync = true;
7710 wake_up(&rdev->irq.vblank_queue);
7712 if (atomic_read(&rdev->irq.pflip[4]))
7713 radeon_crtc_handle_vblank(rdev, 4);
7714 rdev->irq.stat_regs.cik.disp_int_cont4 &= ~LB_D5_VBLANK_INTERRUPT;
7715 DRM_DEBUG("IH: D5 vblank\n");
7718 case 1: /* D5 vline */
7719 if (!(rdev->irq.stat_regs.cik.disp_int_cont4 & LB_D5_VLINE_INTERRUPT))
7720 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
7722 rdev->irq.stat_regs.cik.disp_int_cont4 &= ~LB_D5_VLINE_INTERRUPT;
7723 DRM_DEBUG("IH: D5 vline\n");
7727 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
7731 case 6: /* D6 vblank/vline */
7733 case 0: /* D6 vblank */
7734 if (!(rdev->irq.stat_regs.cik.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT))
7735 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
7737 if (rdev->irq.crtc_vblank_int[5]) {
7738 drm_handle_vblank(rdev->ddev, 5);
7739 rdev->pm.vblank_sync = true;
7740 wake_up(&rdev->irq.vblank_queue);
7742 if (atomic_read(&rdev->irq.pflip[5]))
7743 radeon_crtc_handle_vblank(rdev, 5);
7744 rdev->irq.stat_regs.cik.disp_int_cont5 &= ~LB_D6_VBLANK_INTERRUPT;
7745 DRM_DEBUG("IH: D6 vblank\n");
7748 case 1: /* D6 vline */
7749 if (!(rdev->irq.stat_regs.cik.disp_int_cont5 & LB_D6_VLINE_INTERRUPT))
7750 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
7752 rdev->irq.stat_regs.cik.disp_int_cont5 &= ~LB_D6_VLINE_INTERRUPT;
7753 DRM_DEBUG("IH: D6 vline\n");
7757 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
7761 case 8: /* D1 page flip */
7762 case 10: /* D2 page flip */
7763 case 12: /* D3 page flip */
7764 case 14: /* D4 page flip */
7765 case 16: /* D5 page flip */
7766 case 18: /* D6 page flip */
7767 DRM_DEBUG("IH: D%d flip\n", ((src_id - 8) >> 1) + 1);
7768 if (radeon_use_pflipirq > 0)
7769 radeon_crtc_handle_flip(rdev, (src_id - 8) >> 1);
7771 case 42: /* HPD hotplug */
7774 if (!(rdev->irq.stat_regs.cik.disp_int & DC_HPD1_INTERRUPT))
7775 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
7777 rdev->irq.stat_regs.cik.disp_int &= ~DC_HPD1_INTERRUPT;
7778 queue_hotplug = true;
7779 DRM_DEBUG("IH: HPD1\n");
7783 if (!(rdev->irq.stat_regs.cik.disp_int_cont & DC_HPD2_INTERRUPT))
7784 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
7786 rdev->irq.stat_regs.cik.disp_int_cont &= ~DC_HPD2_INTERRUPT;
7787 queue_hotplug = true;
7788 DRM_DEBUG("IH: HPD2\n");
7792 if (!(rdev->irq.stat_regs.cik.disp_int_cont2 & DC_HPD3_INTERRUPT))
7793 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
7795 rdev->irq.stat_regs.cik.disp_int_cont2 &= ~DC_HPD3_INTERRUPT;
7796 queue_hotplug = true;
7797 DRM_DEBUG("IH: HPD3\n");
7801 if (!(rdev->irq.stat_regs.cik.disp_int_cont3 & DC_HPD4_INTERRUPT))
7802 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
7804 rdev->irq.stat_regs.cik.disp_int_cont3 &= ~DC_HPD4_INTERRUPT;
7805 queue_hotplug = true;
7806 DRM_DEBUG("IH: HPD4\n");
7810 if (!(rdev->irq.stat_regs.cik.disp_int_cont4 & DC_HPD5_INTERRUPT))
7811 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
7813 rdev->irq.stat_regs.cik.disp_int_cont4 &= ~DC_HPD5_INTERRUPT;
7814 queue_hotplug = true;
7815 DRM_DEBUG("IH: HPD5\n");
7819 if (!(rdev->irq.stat_regs.cik.disp_int_cont5 & DC_HPD6_INTERRUPT))
7820 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
7822 rdev->irq.stat_regs.cik.disp_int_cont5 &= ~DC_HPD6_INTERRUPT;
7823 queue_hotplug = true;
7824 DRM_DEBUG("IH: HPD6\n");
7828 if (!(rdev->irq.stat_regs.cik.disp_int & DC_HPD1_RX_INTERRUPT))
7829 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
7831 rdev->irq.stat_regs.cik.disp_int &= ~DC_HPD1_RX_INTERRUPT;
7833 DRM_DEBUG("IH: HPD_RX 1\n");
7837 if (!(rdev->irq.stat_regs.cik.disp_int_cont & DC_HPD2_RX_INTERRUPT))
7838 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
7840 rdev->irq.stat_regs.cik.disp_int_cont &= ~DC_HPD2_RX_INTERRUPT;
7842 DRM_DEBUG("IH: HPD_RX 2\n");
7846 if (!(rdev->irq.stat_regs.cik.disp_int_cont2 & DC_HPD3_RX_INTERRUPT))
7847 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
7849 rdev->irq.stat_regs.cik.disp_int_cont2 &= ~DC_HPD3_RX_INTERRUPT;
7851 DRM_DEBUG("IH: HPD_RX 3\n");
7855 if (!(rdev->irq.stat_regs.cik.disp_int_cont3 & DC_HPD4_RX_INTERRUPT))
7856 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
7858 rdev->irq.stat_regs.cik.disp_int_cont3 &= ~DC_HPD4_RX_INTERRUPT;
7860 DRM_DEBUG("IH: HPD_RX 4\n");
7864 if (!(rdev->irq.stat_regs.cik.disp_int_cont4 & DC_HPD5_RX_INTERRUPT))
7865 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
7867 rdev->irq.stat_regs.cik.disp_int_cont4 &= ~DC_HPD5_RX_INTERRUPT;
7869 DRM_DEBUG("IH: HPD_RX 5\n");
7873 if (!(rdev->irq.stat_regs.cik.disp_int_cont5 & DC_HPD6_RX_INTERRUPT))
7874 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
7876 rdev->irq.stat_regs.cik.disp_int_cont5 &= ~DC_HPD6_RX_INTERRUPT;
7878 DRM_DEBUG("IH: HPD_RX 6\n");
7882 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
7887 DRM_ERROR("SRBM_READ_ERROR: 0x%x\n", RREG32(SRBM_READ_ERROR));
7888 WREG32(SRBM_INT_ACK, 0x1);
7891 DRM_DEBUG("IH: UVD int: 0x%08x\n", src_data);
7892 radeon_fence_process(rdev, R600_RING_TYPE_UVD_INDEX);
7896 addr = RREG32(VM_CONTEXT1_PROTECTION_FAULT_ADDR);
7897 status = RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS);
7898 mc_client = RREG32(VM_CONTEXT1_PROTECTION_FAULT_MCCLIENT);
7899 /* reset addr and status */
7900 WREG32_P(VM_CONTEXT1_CNTL2, 1, ~1);
7901 if (addr == 0x0 && status == 0x0)
7903 dev_err(rdev->dev, "GPU fault detected: %d 0x%08x\n", src_id, src_data);
7904 dev_err(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
7906 dev_err(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
7908 cik_vm_decode_fault(rdev, status, addr, mc_client);
7911 DRM_DEBUG("IH: VCE int: 0x%08x\n", src_data);
7914 radeon_fence_process(rdev, TN_RING_TYPE_VCE1_INDEX);
7917 radeon_fence_process(rdev, TN_RING_TYPE_VCE2_INDEX);
7920 DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data);
7924 case 176: /* GFX RB CP_INT */
7925 case 177: /* GFX IB CP_INT */
7926 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
7928 case 181: /* CP EOP event */
7929 DRM_DEBUG("IH: CP EOP\n");
7930 /* XXX check the bitfield order! */
7931 me_id = (ring_id & 0x60) >> 5;
7932 pipe_id = (ring_id & 0x18) >> 3;
7933 queue_id = (ring_id & 0x7) >> 0;
7936 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
7940 if ((cp1_ring->me == me_id) & (cp1_ring->pipe == pipe_id))
7941 radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP1_INDEX);
7942 if ((cp2_ring->me == me_id) & (cp2_ring->pipe == pipe_id))
7943 radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP2_INDEX);
7947 case 184: /* CP Privileged reg access */
7948 DRM_ERROR("Illegal register access in command stream\n");
7949 /* XXX check the bitfield order! */
7950 me_id = (ring_id & 0x60) >> 5;
7953 /* This results in a full GPU reset, but all we need to do is soft
7954 * reset the CP for gfx
7968 case 185: /* CP Privileged inst */
7969 DRM_ERROR("Illegal instruction in command stream\n");
7970 /* XXX check the bitfield order! */
7971 me_id = (ring_id & 0x60) >> 5;
7974 /* This results in a full GPU reset, but all we need to do is soft
7975 * reset the CP for gfx
7989 case 224: /* SDMA trap event */
7990 /* XXX check the bitfield order! */
7991 me_id = (ring_id & 0x3) >> 0;
7992 queue_id = (ring_id & 0xc) >> 2;
7993 DRM_DEBUG("IH: SDMA trap\n");
7998 radeon_fence_process(rdev, R600_RING_TYPE_DMA_INDEX);
8011 radeon_fence_process(rdev, CAYMAN_RING_TYPE_DMA1_INDEX);
8023 case 230: /* thermal low to high */
8024 DRM_DEBUG("IH: thermal low to high\n");
8025 rdev->pm.dpm.thermal.high_to_low = false;
8026 queue_thermal = true;
8028 case 231: /* thermal high to low */
8029 DRM_DEBUG("IH: thermal high to low\n");
8030 rdev->pm.dpm.thermal.high_to_low = true;
8031 queue_thermal = true;
8033 case 233: /* GUI IDLE */
8034 DRM_DEBUG("IH: GUI idle\n");
8036 case 241: /* SDMA Privileged inst */
8037 case 247: /* SDMA Privileged inst */
8038 DRM_ERROR("Illegal instruction in SDMA command stream\n");
8039 /* XXX check the bitfield order! */
8040 me_id = (ring_id & 0x3) >> 0;
8041 queue_id = (ring_id & 0xc) >> 2;
8076 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
8080 /* wptr/rptr are in bytes! */
8082 rptr &= rdev->ih.ptr_mask;
8083 WREG32(IH_RB_RPTR, rptr);
8086 schedule_work(&rdev->dp_work);
8088 schedule_delayed_work(&rdev->hotplug_work, 0);
8090 rdev->needs_reset = true;
8091 wake_up_all(&rdev->fence_queue);
8094 schedule_work(&rdev->pm.dpm.thermal.work);
8095 rdev->ih.rptr = rptr;
8096 atomic_set(&rdev->ih.lock, 0);
8098 /* make sure wptr hasn't changed while processing */
8099 wptr = cik_get_ih_wptr(rdev);
8107 * startup/shutdown callbacks
8109 static void cik_uvd_init(struct radeon_device *rdev)
8116 r = radeon_uvd_init(rdev);
8118 dev_err(rdev->dev, "failed UVD (%d) init.\n", r);
8120 * At this point rdev->uvd.vcpu_bo is NULL which trickles down
8121 * to early fails cik_uvd_start() and thus nothing happens
8122 * there. So it is pointless to try to go through that code
8123 * hence why we disable uvd here.
8125 rdev->has_uvd = false;
8128 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_obj = NULL;
8129 r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_UVD_INDEX], 4096);
8132 static void cik_uvd_start(struct radeon_device *rdev)
8139 r = radeon_uvd_resume(rdev);
8141 dev_err(rdev->dev, "failed UVD resume (%d).\n", r);
8144 r = uvd_v4_2_resume(rdev);
8146 dev_err(rdev->dev, "failed UVD 4.2 resume (%d).\n", r);
8149 r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_UVD_INDEX);
8151 dev_err(rdev->dev, "failed initializing UVD fences (%d).\n", r);
8157 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0;
8160 static void cik_uvd_resume(struct radeon_device *rdev)
8162 struct radeon_ring *ring;
8165 if (!rdev->has_uvd || !rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size)
8168 ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];
8169 r = radeon_ring_init(rdev, ring, ring->ring_size, 0, PACKET0(UVD_NO_OP, 0));
8171 dev_err(rdev->dev, "failed initializing UVD ring (%d).\n", r);
8174 r = uvd_v1_0_init(rdev);
8176 dev_err(rdev->dev, "failed initializing UVD (%d).\n", r);
8181 static void cik_vce_init(struct radeon_device *rdev)
8188 r = radeon_vce_init(rdev);
8190 dev_err(rdev->dev, "failed VCE (%d) init.\n", r);
8192 * At this point rdev->vce.vcpu_bo is NULL which trickles down
8193 * to early fails cik_vce_start() and thus nothing happens
8194 * there. So it is pointless to try to go through that code
8195 * hence why we disable vce here.
8197 rdev->has_vce = false;
8200 rdev->ring[TN_RING_TYPE_VCE1_INDEX].ring_obj = NULL;
8201 r600_ring_init(rdev, &rdev->ring[TN_RING_TYPE_VCE1_INDEX], 4096);
8202 rdev->ring[TN_RING_TYPE_VCE2_INDEX].ring_obj = NULL;
8203 r600_ring_init(rdev, &rdev->ring[TN_RING_TYPE_VCE2_INDEX], 4096);
8206 static void cik_vce_start(struct radeon_device *rdev)
8213 r = radeon_vce_resume(rdev);
8215 dev_err(rdev->dev, "failed VCE resume (%d).\n", r);
8218 r = vce_v2_0_resume(rdev);
8220 dev_err(rdev->dev, "failed VCE resume (%d).\n", r);
8223 r = radeon_fence_driver_start_ring(rdev, TN_RING_TYPE_VCE1_INDEX);
8225 dev_err(rdev->dev, "failed initializing VCE1 fences (%d).\n", r);
8228 r = radeon_fence_driver_start_ring(rdev, TN_RING_TYPE_VCE2_INDEX);
8230 dev_err(rdev->dev, "failed initializing VCE2 fences (%d).\n", r);
8236 rdev->ring[TN_RING_TYPE_VCE1_INDEX].ring_size = 0;
8237 rdev->ring[TN_RING_TYPE_VCE2_INDEX].ring_size = 0;
8240 static void cik_vce_resume(struct radeon_device *rdev)
8242 struct radeon_ring *ring;
8245 if (!rdev->has_vce || !rdev->ring[TN_RING_TYPE_VCE1_INDEX].ring_size)
8248 ring = &rdev->ring[TN_RING_TYPE_VCE1_INDEX];
8249 r = radeon_ring_init(rdev, ring, ring->ring_size, 0, VCE_CMD_NO_OP);
8251 dev_err(rdev->dev, "failed initializing VCE1 ring (%d).\n", r);
8254 ring = &rdev->ring[TN_RING_TYPE_VCE2_INDEX];
8255 r = radeon_ring_init(rdev, ring, ring->ring_size, 0, VCE_CMD_NO_OP);
8257 dev_err(rdev->dev, "failed initializing VCE1 ring (%d).\n", r);
8260 r = vce_v1_0_init(rdev);
8262 dev_err(rdev->dev, "failed initializing VCE (%d).\n", r);
8268 * cik_startup - program the asic to a functional state
8270 * @rdev: radeon_device pointer
8272 * Programs the asic to a functional state (CIK).
8273 * Called by cik_init() and cik_resume().
8274 * Returns 0 for success, error for failure.
8276 static int cik_startup(struct radeon_device *rdev)
8278 struct radeon_ring *ring;
8282 /* enable pcie gen2/3 link */
8283 cik_pcie_gen3_enable(rdev);
8285 cik_program_aspm(rdev);
8287 /* scratch needs to be initialized before MC */
8288 r = r600_vram_scratch_init(rdev);
8292 cik_mc_program(rdev);
8294 if (!(rdev->flags & RADEON_IS_IGP) && !rdev->pm.dpm_enabled) {
8295 r = ci_mc_load_microcode(rdev);
8297 DRM_ERROR("Failed to load MC firmware!\n");
8302 r = cik_pcie_gart_enable(rdev);
8307 /* allocate rlc buffers */
8308 if (rdev->flags & RADEON_IS_IGP) {
8309 if (rdev->family == CHIP_KAVERI) {
8310 rdev->rlc.reg_list = spectre_rlc_save_restore_register_list;
8311 rdev->rlc.reg_list_size =
8312 (u32)ARRAY_SIZE(spectre_rlc_save_restore_register_list);
8314 rdev->rlc.reg_list = kalindi_rlc_save_restore_register_list;
8315 rdev->rlc.reg_list_size =
8316 (u32)ARRAY_SIZE(kalindi_rlc_save_restore_register_list);
8319 rdev->rlc.cs_data = ci_cs_data;
8320 rdev->rlc.cp_table_size = ALIGN(CP_ME_TABLE_SIZE * 5 * 4, 2048); /* CP JT */
8321 rdev->rlc.cp_table_size += 64 * 1024; /* GDS */
8322 r = sumo_rlc_init(rdev);
8324 DRM_ERROR("Failed to init rlc BOs!\n");
8328 /* allocate wb buffer */
8329 r = radeon_wb_init(rdev);
8333 /* allocate mec buffers */
8334 r = cik_mec_init(rdev);
8336 DRM_ERROR("Failed to init MEC BOs!\n");
8340 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
8342 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
8346 r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP1_INDEX);
8348 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
8352 r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP2_INDEX);
8354 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
8358 r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_DMA_INDEX);
8360 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r);
8364 r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_DMA1_INDEX);
8366 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r);
8370 cik_uvd_start(rdev);
8371 cik_vce_start(rdev);
8374 if (!rdev->irq.installed) {
8375 r = radeon_irq_kms_init(rdev);
8380 r = cik_irq_init(rdev);
8382 DRM_ERROR("radeon: IH init failed (%d).\n", r);
8383 radeon_irq_kms_fini(rdev);
8388 if (rdev->family == CHIP_HAWAII) {
8390 nop = PACKET3(PACKET3_NOP, 0x3FFF);
8392 nop = RADEON_CP_PACKET2;
8394 nop = PACKET3(PACKET3_NOP, 0x3FFF);
8397 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
8398 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
8403 /* set up the compute queues */
8404 /* type-2 packets are deprecated on MEC, use type-3 instead */
8405 ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX];
8406 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP1_RPTR_OFFSET,
8410 ring->me = 1; /* first MEC */
8411 ring->pipe = 0; /* first pipe */
8412 ring->queue = 0; /* first queue */
8413 ring->wptr_offs = CIK_WB_CP1_WPTR_OFFSET;
8415 /* type-2 packets are deprecated on MEC, use type-3 instead */
8416 ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX];
8417 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP2_RPTR_OFFSET,
8421 /* dGPU only have 1 MEC */
8422 ring->me = 1; /* first MEC */
8423 ring->pipe = 0; /* first pipe */
8424 ring->queue = 1; /* second queue */
8425 ring->wptr_offs = CIK_WB_CP2_WPTR_OFFSET;
8427 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
8428 r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET,
8429 SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0));
8433 ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX];
8434 r = radeon_ring_init(rdev, ring, ring->ring_size, CAYMAN_WB_DMA1_RPTR_OFFSET,
8435 SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0));
8439 r = cik_cp_resume(rdev);
8443 r = cik_sdma_resume(rdev);
8447 cik_uvd_resume(rdev);
8448 cik_vce_resume(rdev);
8450 r = radeon_ib_pool_init(rdev);
8452 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
8456 r = radeon_vm_manager_init(rdev);
8458 dev_err(rdev->dev, "vm manager initialization failed (%d).\n", r);
8462 r = radeon_audio_init(rdev);
8470 * cik_resume - resume the asic to a functional state
8472 * @rdev: radeon_device pointer
8474 * Programs the asic to a functional state (CIK).
8476 * Returns 0 for success, error for failure.
8478 int cik_resume(struct radeon_device *rdev)
8483 atom_asic_init(rdev->mode_info.atom_context);
8485 /* init golden registers */
8486 cik_init_golden_registers(rdev);
8488 if (rdev->pm.pm_method == PM_METHOD_DPM)
8489 radeon_pm_resume(rdev);
8491 rdev->accel_working = true;
8492 r = cik_startup(rdev);
8494 DRM_ERROR("cik startup failed on resume\n");
8495 rdev->accel_working = false;
8504 * cik_suspend - suspend the asic
8506 * @rdev: radeon_device pointer
8508 * Bring the chip into a state suitable for suspend (CIK).
8509 * Called at suspend.
8510 * Returns 0 for success.
8512 int cik_suspend(struct radeon_device *rdev)
8514 radeon_pm_suspend(rdev);
8515 radeon_audio_fini(rdev);
8516 radeon_vm_manager_fini(rdev);
8517 cik_cp_enable(rdev, false);
8518 cik_sdma_enable(rdev, false);
8519 if (rdev->has_uvd) {
8520 uvd_v1_0_fini(rdev);
8521 radeon_uvd_suspend(rdev);
8524 radeon_vce_suspend(rdev);
8527 cik_irq_suspend(rdev);
8528 radeon_wb_disable(rdev);
8529 cik_pcie_gart_disable(rdev);
8533 /* Plan is to move initialization in that function and use
8534 * helper function so that radeon_device_init pretty much
8535 * do nothing more than calling asic specific function. This
8536 * should also allow to remove a bunch of callback function
8540 * cik_init - asic specific driver and hw init
8542 * @rdev: radeon_device pointer
8544 * Setup asic specific driver variables and program the hw
8545 * to a functional state (CIK).
8546 * Called at driver startup.
8547 * Returns 0 for success, errors for failure.
8549 int cik_init(struct radeon_device *rdev)
8551 struct radeon_ring *ring;
8555 if (!radeon_get_bios(rdev)) {
8556 if (ASIC_IS_AVIVO(rdev))
8559 /* Must be an ATOMBIOS */
8560 if (!rdev->is_atom_bios) {
8561 dev_err(rdev->dev, "Expecting atombios for cayman GPU\n");
8564 r = radeon_atombios_init(rdev);
8568 /* Post card if necessary */
8569 if (!radeon_card_posted(rdev)) {
8571 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
8574 DRM_INFO("GPU not posted. posting now...\n");
8575 atom_asic_init(rdev->mode_info.atom_context);
8577 /* init golden registers */
8578 cik_init_golden_registers(rdev);
8579 /* Initialize scratch registers */
8580 cik_scratch_init(rdev);
8581 /* Initialize surface registers */
8582 radeon_surface_init(rdev);
8583 /* Initialize clocks */
8584 radeon_get_clock_info(rdev->ddev);
8587 radeon_fence_driver_init(rdev);
8589 /* initialize memory controller */
8590 r = cik_mc_init(rdev);
8593 /* Memory manager */
8594 r = radeon_bo_init(rdev);
8598 if (rdev->flags & RADEON_IS_IGP) {
8599 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->ce_fw ||
8600 !rdev->mec_fw || !rdev->sdma_fw || !rdev->rlc_fw) {
8601 r = cik_init_microcode(rdev);
8603 DRM_ERROR("Failed to load firmware!\n");
8608 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->ce_fw ||
8609 !rdev->mec_fw || !rdev->sdma_fw || !rdev->rlc_fw ||
8611 r = cik_init_microcode(rdev);
8613 DRM_ERROR("Failed to load firmware!\n");
8619 /* Initialize power management */
8620 radeon_pm_init(rdev);
8622 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
8623 ring->ring_obj = NULL;
8624 r600_ring_init(rdev, ring, 1024 * 1024);
8626 ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX];
8627 ring->ring_obj = NULL;
8628 r600_ring_init(rdev, ring, 1024 * 1024);
8629 r = radeon_doorbell_get(rdev, &ring->doorbell_index);
8633 ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX];
8634 ring->ring_obj = NULL;
8635 r600_ring_init(rdev, ring, 1024 * 1024);
8636 r = radeon_doorbell_get(rdev, &ring->doorbell_index);
8640 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
8641 ring->ring_obj = NULL;
8642 r600_ring_init(rdev, ring, 256 * 1024);
8644 ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX];
8645 ring->ring_obj = NULL;
8646 r600_ring_init(rdev, ring, 256 * 1024);
8651 rdev->ih.ring_obj = NULL;
8652 r600_ih_ring_init(rdev, 64 * 1024);
8654 r = r600_pcie_gart_init(rdev);
8658 rdev->accel_working = true;
8659 r = cik_startup(rdev);
8661 dev_err(rdev->dev, "disabling GPU acceleration\n");
8663 cik_sdma_fini(rdev);
8665 sumo_rlc_fini(rdev);
8667 radeon_wb_fini(rdev);
8668 radeon_ib_pool_fini(rdev);
8669 radeon_vm_manager_fini(rdev);
8670 radeon_irq_kms_fini(rdev);
8671 cik_pcie_gart_fini(rdev);
8672 rdev->accel_working = false;
8675 /* Don't start up if the MC ucode is missing.
8676 * The default clocks and voltages before the MC ucode
8677 * is loaded are not suffient for advanced operations.
8679 if (!rdev->mc_fw && !(rdev->flags & RADEON_IS_IGP)) {
8680 DRM_ERROR("radeon: MC ucode required for NI+.\n");
8688 * cik_fini - asic specific driver and hw fini
8690 * @rdev: radeon_device pointer
8692 * Tear down the asic specific driver variables and program the hw
8693 * to an idle state (CIK).
8694 * Called at driver unload.
8696 void cik_fini(struct radeon_device *rdev)
8698 radeon_pm_fini(rdev);
8700 cik_sdma_fini(rdev);
8704 sumo_rlc_fini(rdev);
8706 radeon_wb_fini(rdev);
8707 radeon_vm_manager_fini(rdev);
8708 radeon_ib_pool_fini(rdev);
8709 radeon_irq_kms_fini(rdev);
8710 uvd_v1_0_fini(rdev);
8711 radeon_uvd_fini(rdev);
8712 radeon_vce_fini(rdev);
8713 cik_pcie_gart_fini(rdev);
8714 r600_vram_scratch_fini(rdev);
8715 radeon_gem_fini(rdev);
8716 radeon_fence_driver_fini(rdev);
8717 radeon_bo_fini(rdev);
8718 radeon_atombios_fini(rdev);
8723 void dce8_program_fmt(struct drm_encoder *encoder)
8725 struct drm_device *dev = encoder->dev;
8726 struct radeon_device *rdev = dev->dev_private;
8727 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
8728 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
8729 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
8732 enum radeon_connector_dither dither = RADEON_FMT_DITHER_DISABLE;
8735 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
8736 bpc = radeon_get_monitor_bpc(connector);
8737 dither = radeon_connector->dither;
8740 /* LVDS/eDP FMT is set up by atom */
8741 if (radeon_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
8744 /* not needed for analog */
8745 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) ||
8746 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2))
8754 if (dither == RADEON_FMT_DITHER_ENABLE)
8755 /* XXX sort out optimal dither settings */
8756 tmp |= (FMT_FRAME_RANDOM_ENABLE | FMT_HIGHPASS_RANDOM_ENABLE |
8757 FMT_SPATIAL_DITHER_EN | FMT_SPATIAL_DITHER_DEPTH(0));
8759 tmp |= (FMT_TRUNCATE_EN | FMT_TRUNCATE_DEPTH(0));
8762 if (dither == RADEON_FMT_DITHER_ENABLE)
8763 /* XXX sort out optimal dither settings */
8764 tmp |= (FMT_FRAME_RANDOM_ENABLE | FMT_HIGHPASS_RANDOM_ENABLE |
8765 FMT_RGB_RANDOM_ENABLE |
8766 FMT_SPATIAL_DITHER_EN | FMT_SPATIAL_DITHER_DEPTH(1));
8768 tmp |= (FMT_TRUNCATE_EN | FMT_TRUNCATE_DEPTH(1));
8771 if (dither == RADEON_FMT_DITHER_ENABLE)
8772 /* XXX sort out optimal dither settings */
8773 tmp |= (FMT_FRAME_RANDOM_ENABLE | FMT_HIGHPASS_RANDOM_ENABLE |
8774 FMT_RGB_RANDOM_ENABLE |
8775 FMT_SPATIAL_DITHER_EN | FMT_SPATIAL_DITHER_DEPTH(2));
8777 tmp |= (FMT_TRUNCATE_EN | FMT_TRUNCATE_DEPTH(2));
8784 WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp);
8787 /* display watermark setup */
8789 * dce8_line_buffer_adjust - Set up the line buffer
8791 * @rdev: radeon_device pointer
8792 * @radeon_crtc: the selected display controller
8793 * @mode: the current display mode on the selected display
8796 * Setup up the line buffer allocation for
8797 * the selected display controller (CIK).
8798 * Returns the line buffer size in pixels.
8800 static u32 dce8_line_buffer_adjust(struct radeon_device *rdev,
8801 struct radeon_crtc *radeon_crtc,
8802 struct drm_display_mode *mode)
8804 u32 tmp, buffer_alloc, i;
8805 u32 pipe_offset = radeon_crtc->crtc_id * 0x20;
8808 * There are 6 line buffers, one for each display controllers.
8809 * There are 3 partitions per LB. Select the number of partitions
8810 * to enable based on the display width. For display widths larger
8811 * than 4096, you need use to use 2 display controllers and combine
8812 * them using the stereo blender.
8814 if (radeon_crtc->base.enabled && mode) {
8815 if (mode->crtc_hdisplay < 1920) {
8818 } else if (mode->crtc_hdisplay < 2560) {
8821 } else if (mode->crtc_hdisplay < 4096) {
8823 buffer_alloc = (rdev->flags & RADEON_IS_IGP) ? 2 : 4;
8825 DRM_DEBUG_KMS("Mode too big for LB!\n");
8827 buffer_alloc = (rdev->flags & RADEON_IS_IGP) ? 2 : 4;
8834 WREG32(LB_MEMORY_CTRL + radeon_crtc->crtc_offset,
8835 LB_MEMORY_CONFIG(tmp) | LB_MEMORY_SIZE(0x6B0));
8837 WREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset,
8838 DMIF_BUFFERS_ALLOCATED(buffer_alloc));
8839 for (i = 0; i < rdev->usec_timeout; i++) {
8840 if (RREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset) &
8841 DMIF_BUFFERS_ALLOCATED_COMPLETED)
8846 if (radeon_crtc->base.enabled && mode) {
8858 /* controller not enabled, so no lb used */
8863 * cik_get_number_of_dram_channels - get the number of dram channels
8865 * @rdev: radeon_device pointer
8867 * Look up the number of video ram channels (CIK).
8868 * Used for display watermark bandwidth calculations
8869 * Returns the number of dram channels
8871 static u32 cik_get_number_of_dram_channels(struct radeon_device *rdev)
8873 u32 tmp = RREG32(MC_SHARED_CHMAP);
8875 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
8898 struct dce8_wm_params {
8899 u32 dram_channels; /* number of dram channels */
8900 u32 yclk; /* bandwidth per dram data pin in kHz */
8901 u32 sclk; /* engine clock in kHz */
8902 u32 disp_clk; /* display clock in kHz */
8903 u32 src_width; /* viewport width */
8904 u32 active_time; /* active display time in ns */
8905 u32 blank_time; /* blank time in ns */
8906 bool interlaced; /* mode is interlaced */
8907 fixed20_12 vsc; /* vertical scale ratio */
8908 u32 num_heads; /* number of active crtcs */
8909 u32 bytes_per_pixel; /* bytes per pixel display + overlay */
8910 u32 lb_size; /* line buffer allocated to pipe */
8911 u32 vtaps; /* vertical scaler taps */
8915 * dce8_dram_bandwidth - get the dram bandwidth
8917 * @wm: watermark calculation data
8919 * Calculate the raw dram bandwidth (CIK).
8920 * Used for display watermark bandwidth calculations
8921 * Returns the dram bandwidth in MBytes/s
8923 static u32 dce8_dram_bandwidth(struct dce8_wm_params *wm)
8925 /* Calculate raw DRAM Bandwidth */
8926 fixed20_12 dram_efficiency; /* 0.7 */
8927 fixed20_12 yclk, dram_channels, bandwidth;
8930 a.full = dfixed_const(1000);
8931 yclk.full = dfixed_const(wm->yclk);
8932 yclk.full = dfixed_div(yclk, a);
8933 dram_channels.full = dfixed_const(wm->dram_channels * 4);
8934 a.full = dfixed_const(10);
8935 dram_efficiency.full = dfixed_const(7);
8936 dram_efficiency.full = dfixed_div(dram_efficiency, a);
8937 bandwidth.full = dfixed_mul(dram_channels, yclk);
8938 bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
8940 return dfixed_trunc(bandwidth);
8944 * dce8_dram_bandwidth_for_display - get the dram bandwidth for display
8946 * @wm: watermark calculation data
8948 * Calculate the dram bandwidth used for display (CIK).
8949 * Used for display watermark bandwidth calculations
8950 * Returns the dram bandwidth for display in MBytes/s
8952 static u32 dce8_dram_bandwidth_for_display(struct dce8_wm_params *wm)
8954 /* Calculate DRAM Bandwidth and the part allocated to display. */
8955 fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
8956 fixed20_12 yclk, dram_channels, bandwidth;
8959 a.full = dfixed_const(1000);
8960 yclk.full = dfixed_const(wm->yclk);
8961 yclk.full = dfixed_div(yclk, a);
8962 dram_channels.full = dfixed_const(wm->dram_channels * 4);
8963 a.full = dfixed_const(10);
8964 disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
8965 disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
8966 bandwidth.full = dfixed_mul(dram_channels, yclk);
8967 bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
8969 return dfixed_trunc(bandwidth);
8973 * dce8_data_return_bandwidth - get the data return bandwidth
8975 * @wm: watermark calculation data
8977 * Calculate the data return bandwidth used for display (CIK).
8978 * Used for display watermark bandwidth calculations
8979 * Returns the data return bandwidth in MBytes/s
8981 static u32 dce8_data_return_bandwidth(struct dce8_wm_params *wm)
8983 /* Calculate the display Data return Bandwidth */
8984 fixed20_12 return_efficiency; /* 0.8 */
8985 fixed20_12 sclk, bandwidth;
8988 a.full = dfixed_const(1000);
8989 sclk.full = dfixed_const(wm->sclk);
8990 sclk.full = dfixed_div(sclk, a);
8991 a.full = dfixed_const(10);
8992 return_efficiency.full = dfixed_const(8);
8993 return_efficiency.full = dfixed_div(return_efficiency, a);
8994 a.full = dfixed_const(32);
8995 bandwidth.full = dfixed_mul(a, sclk);
8996 bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
8998 return dfixed_trunc(bandwidth);
9002 * dce8_dmif_request_bandwidth - get the dmif bandwidth
9004 * @wm: watermark calculation data
9006 * Calculate the dmif bandwidth used for display (CIK).
9007 * Used for display watermark bandwidth calculations
9008 * Returns the dmif bandwidth in MBytes/s
9010 static u32 dce8_dmif_request_bandwidth(struct dce8_wm_params *wm)
9012 /* Calculate the DMIF Request Bandwidth */
9013 fixed20_12 disp_clk_request_efficiency; /* 0.8 */
9014 fixed20_12 disp_clk, bandwidth;
9017 a.full = dfixed_const(1000);
9018 disp_clk.full = dfixed_const(wm->disp_clk);
9019 disp_clk.full = dfixed_div(disp_clk, a);
9020 a.full = dfixed_const(32);
9021 b.full = dfixed_mul(a, disp_clk);
9023 a.full = dfixed_const(10);
9024 disp_clk_request_efficiency.full = dfixed_const(8);
9025 disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
9027 bandwidth.full = dfixed_mul(b, disp_clk_request_efficiency);
9029 return dfixed_trunc(bandwidth);
9033 * dce8_available_bandwidth - get the min available bandwidth
9035 * @wm: watermark calculation data
9037 * Calculate the min available bandwidth used for display (CIK).
9038 * Used for display watermark bandwidth calculations
9039 * Returns the min available bandwidth in MBytes/s
9041 static u32 dce8_available_bandwidth(struct dce8_wm_params *wm)
9043 /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
9044 u32 dram_bandwidth = dce8_dram_bandwidth(wm);
9045 u32 data_return_bandwidth = dce8_data_return_bandwidth(wm);
9046 u32 dmif_req_bandwidth = dce8_dmif_request_bandwidth(wm);
9048 return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
9052 * dce8_average_bandwidth - get the average available bandwidth
9054 * @wm: watermark calculation data
9056 * Calculate the average available bandwidth used for display (CIK).
9057 * Used for display watermark bandwidth calculations
9058 * Returns the average available bandwidth in MBytes/s
9060 static u32 dce8_average_bandwidth(struct dce8_wm_params *wm)
9062 /* Calculate the display mode Average Bandwidth
9063 * DisplayMode should contain the source and destination dimensions,
9067 fixed20_12 line_time;
9068 fixed20_12 src_width;
9069 fixed20_12 bandwidth;
9072 a.full = dfixed_const(1000);
9073 line_time.full = dfixed_const(wm->active_time + wm->blank_time);
9074 line_time.full = dfixed_div(line_time, a);
9075 bpp.full = dfixed_const(wm->bytes_per_pixel);
9076 src_width.full = dfixed_const(wm->src_width);
9077 bandwidth.full = dfixed_mul(src_width, bpp);
9078 bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
9079 bandwidth.full = dfixed_div(bandwidth, line_time);
9081 return dfixed_trunc(bandwidth);
9085 * dce8_latency_watermark - get the latency watermark
9087 * @wm: watermark calculation data
9089 * Calculate the latency watermark (CIK).
9090 * Used for display watermark bandwidth calculations
9091 * Returns the latency watermark in ns
9093 static u32 dce8_latency_watermark(struct dce8_wm_params *wm)
9095 /* First calculate the latency in ns */
9096 u32 mc_latency = 2000; /* 2000 ns. */
9097 u32 available_bandwidth = dce8_available_bandwidth(wm);
9098 u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
9099 u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
9100 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
9101 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
9102 (wm->num_heads * cursor_line_pair_return_time);
9103 u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
9104 u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
9105 u32 tmp, dmif_size = 12288;
9108 if (wm->num_heads == 0)
9111 a.full = dfixed_const(2);
9112 b.full = dfixed_const(1);
9113 if ((wm->vsc.full > a.full) ||
9114 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
9116 ((wm->vsc.full >= a.full) && wm->interlaced))
9117 max_src_lines_per_dst_line = 4;
9119 max_src_lines_per_dst_line = 2;
9121 a.full = dfixed_const(available_bandwidth);
9122 b.full = dfixed_const(wm->num_heads);
9123 a.full = dfixed_div(a, b);
9124 tmp = div_u64((u64) dmif_size * (u64) wm->disp_clk, mc_latency + 512);
9125 tmp = min(dfixed_trunc(a), tmp);
9127 lb_fill_bw = min(tmp, wm->disp_clk * wm->bytes_per_pixel / 1000);
9129 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
9130 b.full = dfixed_const(1000);
9131 c.full = dfixed_const(lb_fill_bw);
9132 b.full = dfixed_div(c, b);
9133 a.full = dfixed_div(a, b);
9134 line_fill_time = dfixed_trunc(a);
9136 if (line_fill_time < wm->active_time)
9139 return latency + (line_fill_time - wm->active_time);
9144 * dce8_average_bandwidth_vs_dram_bandwidth_for_display - check
9145 * average and available dram bandwidth
9147 * @wm: watermark calculation data
9149 * Check if the display average bandwidth fits in the display
9150 * dram bandwidth (CIK).
9151 * Used for display watermark bandwidth calculations
9152 * Returns true if the display fits, false if not.
9154 static bool dce8_average_bandwidth_vs_dram_bandwidth_for_display(struct dce8_wm_params *wm)
9156 if (dce8_average_bandwidth(wm) <=
9157 (dce8_dram_bandwidth_for_display(wm) / wm->num_heads))
9164 * dce8_average_bandwidth_vs_available_bandwidth - check
9165 * average and available bandwidth
9167 * @wm: watermark calculation data
9169 * Check if the display average bandwidth fits in the display
9170 * available bandwidth (CIK).
9171 * Used for display watermark bandwidth calculations
9172 * Returns true if the display fits, false if not.
9174 static bool dce8_average_bandwidth_vs_available_bandwidth(struct dce8_wm_params *wm)
9176 if (dce8_average_bandwidth(wm) <=
9177 (dce8_available_bandwidth(wm) / wm->num_heads))
9184 * dce8_check_latency_hiding - check latency hiding
9186 * @wm: watermark calculation data
9188 * Check latency hiding (CIK).
9189 * Used for display watermark bandwidth calculations
9190 * Returns true if the display fits, false if not.
9192 static bool dce8_check_latency_hiding(struct dce8_wm_params *wm)
9194 u32 lb_partitions = wm->lb_size / wm->src_width;
9195 u32 line_time = wm->active_time + wm->blank_time;
9196 u32 latency_tolerant_lines;
9200 a.full = dfixed_const(1);
9201 if (wm->vsc.full > a.full)
9202 latency_tolerant_lines = 1;
9204 if (lb_partitions <= (wm->vtaps + 1))
9205 latency_tolerant_lines = 1;
9207 latency_tolerant_lines = 2;
9210 latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
9212 if (dce8_latency_watermark(wm) <= latency_hiding)
9219 * dce8_program_watermarks - program display watermarks
9221 * @rdev: radeon_device pointer
9222 * @radeon_crtc: the selected display controller
9223 * @lb_size: line buffer size
9224 * @num_heads: number of display controllers in use
9226 * Calculate and program the display watermarks for the
9227 * selected display controller (CIK).
9229 static void dce8_program_watermarks(struct radeon_device *rdev,
9230 struct radeon_crtc *radeon_crtc,
9231 u32 lb_size, u32 num_heads)
9233 struct drm_display_mode *mode = &radeon_crtc->base.mode;
9234 struct dce8_wm_params wm_low, wm_high;
9237 u32 latency_watermark_a = 0, latency_watermark_b = 0;
9240 if (radeon_crtc->base.enabled && num_heads && mode) {
9241 active_time = (u32) div_u64((u64)mode->crtc_hdisplay * 1000000,
9243 line_time = (u32) div_u64((u64)mode->crtc_htotal * 1000000,
9245 line_time = min(line_time, (u32)65535);
9247 /* watermark for high clocks */
9248 if ((rdev->pm.pm_method == PM_METHOD_DPM) &&
9249 rdev->pm.dpm_enabled) {
9251 radeon_dpm_get_mclk(rdev, false) * 10;
9253 radeon_dpm_get_sclk(rdev, false) * 10;
9255 wm_high.yclk = rdev->pm.current_mclk * 10;
9256 wm_high.sclk = rdev->pm.current_sclk * 10;
9259 wm_high.disp_clk = mode->clock;
9260 wm_high.src_width = mode->crtc_hdisplay;
9261 wm_high.active_time = active_time;
9262 wm_high.blank_time = line_time - wm_high.active_time;
9263 wm_high.interlaced = false;
9264 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
9265 wm_high.interlaced = true;
9266 wm_high.vsc = radeon_crtc->vsc;
9268 if (radeon_crtc->rmx_type != RMX_OFF)
9270 wm_high.bytes_per_pixel = 4; /* XXX: get this from fb config */
9271 wm_high.lb_size = lb_size;
9272 wm_high.dram_channels = cik_get_number_of_dram_channels(rdev);
9273 wm_high.num_heads = num_heads;
9275 /* set for high clocks */
9276 latency_watermark_a = min(dce8_latency_watermark(&wm_high), (u32)65535);
9278 /* possibly force display priority to high */
9279 /* should really do this at mode validation time... */
9280 if (!dce8_average_bandwidth_vs_dram_bandwidth_for_display(&wm_high) ||
9281 !dce8_average_bandwidth_vs_available_bandwidth(&wm_high) ||
9282 !dce8_check_latency_hiding(&wm_high) ||
9283 (rdev->disp_priority == 2)) {
9284 DRM_DEBUG_KMS("force priority to high\n");
9287 /* watermark for low clocks */
9288 if ((rdev->pm.pm_method == PM_METHOD_DPM) &&
9289 rdev->pm.dpm_enabled) {
9291 radeon_dpm_get_mclk(rdev, true) * 10;
9293 radeon_dpm_get_sclk(rdev, true) * 10;
9295 wm_low.yclk = rdev->pm.current_mclk * 10;
9296 wm_low.sclk = rdev->pm.current_sclk * 10;
9299 wm_low.disp_clk = mode->clock;
9300 wm_low.src_width = mode->crtc_hdisplay;
9301 wm_low.active_time = active_time;
9302 wm_low.blank_time = line_time - wm_low.active_time;
9303 wm_low.interlaced = false;
9304 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
9305 wm_low.interlaced = true;
9306 wm_low.vsc = radeon_crtc->vsc;
9308 if (radeon_crtc->rmx_type != RMX_OFF)
9310 wm_low.bytes_per_pixel = 4; /* XXX: get this from fb config */
9311 wm_low.lb_size = lb_size;
9312 wm_low.dram_channels = cik_get_number_of_dram_channels(rdev);
9313 wm_low.num_heads = num_heads;
9315 /* set for low clocks */
9316 latency_watermark_b = min(dce8_latency_watermark(&wm_low), (u32)65535);
9318 /* possibly force display priority to high */
9319 /* should really do this at mode validation time... */
9320 if (!dce8_average_bandwidth_vs_dram_bandwidth_for_display(&wm_low) ||
9321 !dce8_average_bandwidth_vs_available_bandwidth(&wm_low) ||
9322 !dce8_check_latency_hiding(&wm_low) ||
9323 (rdev->disp_priority == 2)) {
9324 DRM_DEBUG_KMS("force priority to high\n");
9327 /* Save number of lines the linebuffer leads before the scanout */
9328 radeon_crtc->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay);
9332 wm_mask = RREG32(DPG_WATERMARK_MASK_CONTROL + radeon_crtc->crtc_offset);
9334 tmp &= ~LATENCY_WATERMARK_MASK(3);
9335 tmp |= LATENCY_WATERMARK_MASK(1);
9336 WREG32(DPG_WATERMARK_MASK_CONTROL + radeon_crtc->crtc_offset, tmp);
9337 WREG32(DPG_PIPE_LATENCY_CONTROL + radeon_crtc->crtc_offset,
9338 (LATENCY_LOW_WATERMARK(latency_watermark_a) |
9339 LATENCY_HIGH_WATERMARK(line_time)));
9341 tmp = RREG32(DPG_WATERMARK_MASK_CONTROL + radeon_crtc->crtc_offset);
9342 tmp &= ~LATENCY_WATERMARK_MASK(3);
9343 tmp |= LATENCY_WATERMARK_MASK(2);
9344 WREG32(DPG_WATERMARK_MASK_CONTROL + radeon_crtc->crtc_offset, tmp);
9345 WREG32(DPG_PIPE_LATENCY_CONTROL + radeon_crtc->crtc_offset,
9346 (LATENCY_LOW_WATERMARK(latency_watermark_b) |
9347 LATENCY_HIGH_WATERMARK(line_time)));
9348 /* restore original selection */
9349 WREG32(DPG_WATERMARK_MASK_CONTROL + radeon_crtc->crtc_offset, wm_mask);
9351 /* save values for DPM */
9352 radeon_crtc->line_time = line_time;
9353 radeon_crtc->wm_high = latency_watermark_a;
9354 radeon_crtc->wm_low = latency_watermark_b;
9358 * dce8_bandwidth_update - program display watermarks
9360 * @rdev: radeon_device pointer
9362 * Calculate and program the display watermarks and line
9363 * buffer allocation (CIK).
9365 void dce8_bandwidth_update(struct radeon_device *rdev)
9367 struct drm_display_mode *mode = NULL;
9368 u32 num_heads = 0, lb_size;
9371 if (!rdev->mode_info.mode_config_initialized)
9374 radeon_update_display_priority(rdev);
9376 for (i = 0; i < rdev->num_crtc; i++) {
9377 if (rdev->mode_info.crtcs[i]->base.enabled)
9380 for (i = 0; i < rdev->num_crtc; i++) {
9381 mode = &rdev->mode_info.crtcs[i]->base.mode;
9382 lb_size = dce8_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i], mode);
9383 dce8_program_watermarks(rdev, rdev->mode_info.crtcs[i], lb_size, num_heads);
9388 * cik_get_gpu_clock_counter - return GPU clock counter snapshot
9390 * @rdev: radeon_device pointer
9392 * Fetches a GPU clock counter snapshot (SI).
9393 * Returns the 64 bit clock counter snapshot.
9395 uint64_t cik_get_gpu_clock_counter(struct radeon_device *rdev)
9399 mutex_lock(&rdev->gpu_clock_mutex);
9400 WREG32(RLC_CAPTURE_GPU_CLOCK_COUNT, 1);
9401 clock = (uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_LSB) |
9402 ((uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
9403 mutex_unlock(&rdev->gpu_clock_mutex);
9407 static int cik_set_uvd_clock(struct radeon_device *rdev, u32 clock,
9408 u32 cntl_reg, u32 status_reg)
9411 struct atom_clock_dividers dividers;
9414 r = radeon_atom_get_clock_dividers(rdev, COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
9415 clock, false, ÷rs);
9419 tmp = RREG32_SMC(cntl_reg);
9420 tmp &= ~(DCLK_DIR_CNTL_EN|DCLK_DIVIDER_MASK);
9421 tmp |= dividers.post_divider;
9422 WREG32_SMC(cntl_reg, tmp);
9424 for (i = 0; i < 100; i++) {
9425 if (RREG32_SMC(status_reg) & DCLK_STATUS)
9435 int cik_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)
9439 r = cik_set_uvd_clock(rdev, vclk, CG_VCLK_CNTL, CG_VCLK_STATUS);
9443 r = cik_set_uvd_clock(rdev, dclk, CG_DCLK_CNTL, CG_DCLK_STATUS);
9447 int cik_set_vce_clocks(struct radeon_device *rdev, u32 evclk, u32 ecclk)
9450 struct atom_clock_dividers dividers;
9453 r = radeon_atom_get_clock_dividers(rdev, COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
9454 ecclk, false, ÷rs);
9458 for (i = 0; i < 100; i++) {
9459 if (RREG32_SMC(CG_ECLK_STATUS) & ECLK_STATUS)
9466 tmp = RREG32_SMC(CG_ECLK_CNTL);
9467 tmp &= ~(ECLK_DIR_CNTL_EN|ECLK_DIVIDER_MASK);
9468 tmp |= dividers.post_divider;
9469 WREG32_SMC(CG_ECLK_CNTL, tmp);
9471 for (i = 0; i < 100; i++) {
9472 if (RREG32_SMC(CG_ECLK_STATUS) & ECLK_STATUS)
9482 static void cik_pcie_gen3_enable(struct radeon_device *rdev)
9484 struct pci_dev *root = rdev->pdev->bus->self;
9485 enum pci_bus_speed speed_cap;
9486 u32 speed_cntl, current_data_rate;
9490 if (pci_is_root_bus(rdev->pdev->bus))
9493 if (radeon_pcie_gen2 == 0)
9496 if (rdev->flags & RADEON_IS_IGP)
9499 if (!(rdev->flags & RADEON_IS_PCIE))
9502 speed_cap = pcie_get_speed_cap(root);
9503 if (speed_cap == PCI_SPEED_UNKNOWN)
9506 if ((speed_cap != PCIE_SPEED_8_0GT) &&
9507 (speed_cap != PCIE_SPEED_5_0GT))
9510 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
9511 current_data_rate = (speed_cntl & LC_CURRENT_DATA_RATE_MASK) >>
9512 LC_CURRENT_DATA_RATE_SHIFT;
9513 if (speed_cap == PCIE_SPEED_8_0GT) {
9514 if (current_data_rate == 2) {
9515 DRM_INFO("PCIE gen 3 link speeds already enabled\n");
9518 DRM_INFO("enabling PCIE gen 3 link speeds, disable with radeon.pcie_gen2=0\n");
9519 } else if (speed_cap == PCIE_SPEED_5_0GT) {
9520 if (current_data_rate == 1) {
9521 DRM_INFO("PCIE gen 2 link speeds already enabled\n");
9524 DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n");
9527 if (!pci_is_pcie(root) || !pci_is_pcie(rdev->pdev))
9530 if (speed_cap == PCIE_SPEED_8_0GT) {
9531 /* re-try equalization if gen3 is not already enabled */
9532 if (current_data_rate != 2) {
9533 u16 bridge_cfg, gpu_cfg;
9534 u16 bridge_cfg2, gpu_cfg2;
9535 u32 max_lw, current_lw, tmp;
9537 pcie_capability_read_word(root, PCI_EXP_LNKCTL,
9539 pcie_capability_read_word(rdev->pdev, PCI_EXP_LNKCTL,
9542 tmp16 = bridge_cfg | PCI_EXP_LNKCTL_HAWD;
9543 pcie_capability_write_word(root, PCI_EXP_LNKCTL, tmp16);
9545 tmp16 = gpu_cfg | PCI_EXP_LNKCTL_HAWD;
9546 pcie_capability_write_word(rdev->pdev, PCI_EXP_LNKCTL,
9549 tmp = RREG32_PCIE_PORT(PCIE_LC_STATUS1);
9550 max_lw = (tmp & LC_DETECTED_LINK_WIDTH_MASK) >> LC_DETECTED_LINK_WIDTH_SHIFT;
9551 current_lw = (tmp & LC_OPERATING_LINK_WIDTH_MASK) >> LC_OPERATING_LINK_WIDTH_SHIFT;
9553 if (current_lw < max_lw) {
9554 tmp = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
9555 if (tmp & LC_RENEGOTIATION_SUPPORT) {
9556 tmp &= ~(LC_LINK_WIDTH_MASK | LC_UPCONFIGURE_DIS);
9557 tmp |= (max_lw << LC_LINK_WIDTH_SHIFT);
9558 tmp |= LC_UPCONFIGURE_SUPPORT | LC_RENEGOTIATE_EN | LC_RECONFIG_NOW;
9559 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, tmp);
9563 for (i = 0; i < 10; i++) {
9565 pcie_capability_read_word(rdev->pdev,
9568 if (tmp16 & PCI_EXP_DEVSTA_TRPND)
9571 pcie_capability_read_word(root, PCI_EXP_LNKCTL,
9573 pcie_capability_read_word(rdev->pdev,
9577 pcie_capability_read_word(root, PCI_EXP_LNKCTL2,
9579 pcie_capability_read_word(rdev->pdev,
9583 tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);
9584 tmp |= LC_SET_QUIESCE;
9585 WREG32_PCIE_PORT(PCIE_LC_CNTL4, tmp);
9587 tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);
9589 WREG32_PCIE_PORT(PCIE_LC_CNTL4, tmp);
9594 pcie_capability_read_word(root, PCI_EXP_LNKCTL,
9596 tmp16 &= ~PCI_EXP_LNKCTL_HAWD;
9597 tmp16 |= (bridge_cfg & PCI_EXP_LNKCTL_HAWD);
9598 pcie_capability_write_word(root, PCI_EXP_LNKCTL,
9601 pcie_capability_read_word(rdev->pdev,
9604 tmp16 &= ~PCI_EXP_LNKCTL_HAWD;
9605 tmp16 |= (gpu_cfg & PCI_EXP_LNKCTL_HAWD);
9606 pcie_capability_write_word(rdev->pdev,
9611 pcie_capability_read_word(root, PCI_EXP_LNKCTL2,
9613 tmp16 &= ~(PCI_EXP_LNKCTL2_ENTER_COMP |
9614 PCI_EXP_LNKCTL2_TX_MARGIN);
9615 tmp16 |= (bridge_cfg2 &
9616 (PCI_EXP_LNKCTL2_ENTER_COMP |
9617 PCI_EXP_LNKCTL2_TX_MARGIN));
9618 pcie_capability_write_word(root,
9622 pcie_capability_read_word(rdev->pdev,
9625 tmp16 &= ~(PCI_EXP_LNKCTL2_ENTER_COMP |
9626 PCI_EXP_LNKCTL2_TX_MARGIN);
9627 tmp16 |= (gpu_cfg2 &
9628 (PCI_EXP_LNKCTL2_ENTER_COMP |
9629 PCI_EXP_LNKCTL2_TX_MARGIN));
9630 pcie_capability_write_word(rdev->pdev,
9634 tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);
9635 tmp &= ~LC_SET_QUIESCE;
9636 WREG32_PCIE_PORT(PCIE_LC_CNTL4, tmp);
9641 /* set the link speed */
9642 speed_cntl |= LC_FORCE_EN_SW_SPEED_CHANGE | LC_FORCE_DIS_HW_SPEED_CHANGE;
9643 speed_cntl &= ~LC_FORCE_DIS_SW_SPEED_CHANGE;
9644 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
9646 pcie_capability_read_word(rdev->pdev, PCI_EXP_LNKCTL2, &tmp16);
9647 tmp16 &= ~PCI_EXP_LNKCTL2_TLS;
9648 if (speed_cap == PCIE_SPEED_8_0GT)
9649 tmp16 |= PCI_EXP_LNKCTL2_TLS_8_0GT; /* gen3 */
9650 else if (speed_cap == PCIE_SPEED_5_0GT)
9651 tmp16 |= PCI_EXP_LNKCTL2_TLS_5_0GT; /* gen2 */
9653 tmp16 |= PCI_EXP_LNKCTL2_TLS_2_5GT; /* gen1 */
9654 pcie_capability_write_word(rdev->pdev, PCI_EXP_LNKCTL2, tmp16);
9656 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
9657 speed_cntl |= LC_INITIATE_LINK_SPEED_CHANGE;
9658 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
9660 for (i = 0; i < rdev->usec_timeout; i++) {
9661 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
9662 if ((speed_cntl & LC_INITIATE_LINK_SPEED_CHANGE) == 0)
9668 static void cik_program_aspm(struct radeon_device *rdev)
9671 bool disable_l0s = false, disable_l1 = false, disable_plloff_in_l1 = false;
9672 bool disable_clkreq = false;
9674 if (radeon_aspm == 0)
9677 /* XXX double check IGPs */
9678 if (rdev->flags & RADEON_IS_IGP)
9681 if (!(rdev->flags & RADEON_IS_PCIE))
9684 orig = data = RREG32_PCIE_PORT(PCIE_LC_N_FTS_CNTL);
9685 data &= ~LC_XMIT_N_FTS_MASK;
9686 data |= LC_XMIT_N_FTS(0x24) | LC_XMIT_N_FTS_OVERRIDE_EN;
9688 WREG32_PCIE_PORT(PCIE_LC_N_FTS_CNTL, data);
9690 orig = data = RREG32_PCIE_PORT(PCIE_LC_CNTL3);
9691 data |= LC_GO_TO_RECOVERY;
9693 WREG32_PCIE_PORT(PCIE_LC_CNTL3, data);
9695 orig = data = RREG32_PCIE_PORT(PCIE_P_CNTL);
9696 data |= P_IGNORE_EDB_ERR;
9698 WREG32_PCIE_PORT(PCIE_P_CNTL, data);
9700 orig = data = RREG32_PCIE_PORT(PCIE_LC_CNTL);
9701 data &= ~(LC_L0S_INACTIVITY_MASK | LC_L1_INACTIVITY_MASK);
9702 data |= LC_PMI_TO_L1_DIS;
9704 data |= LC_L0S_INACTIVITY(7);
9707 data |= LC_L1_INACTIVITY(7);
9708 data &= ~LC_PMI_TO_L1_DIS;
9710 WREG32_PCIE_PORT(PCIE_LC_CNTL, data);
9712 if (!disable_plloff_in_l1) {
9713 bool clk_req_support;
9715 orig = data = RREG32_PCIE_PORT(PB0_PIF_PWRDOWN_0);
9716 data &= ~(PLL_POWER_STATE_IN_OFF_0_MASK | PLL_POWER_STATE_IN_TXS2_0_MASK);
9717 data |= PLL_POWER_STATE_IN_OFF_0(7) | PLL_POWER_STATE_IN_TXS2_0(7);
9719 WREG32_PCIE_PORT(PB0_PIF_PWRDOWN_0, data);
9721 orig = data = RREG32_PCIE_PORT(PB0_PIF_PWRDOWN_1);
9722 data &= ~(PLL_POWER_STATE_IN_OFF_1_MASK | PLL_POWER_STATE_IN_TXS2_1_MASK);
9723 data |= PLL_POWER_STATE_IN_OFF_1(7) | PLL_POWER_STATE_IN_TXS2_1(7);
9725 WREG32_PCIE_PORT(PB0_PIF_PWRDOWN_1, data);
9727 orig = data = RREG32_PCIE_PORT(PB1_PIF_PWRDOWN_0);
9728 data &= ~(PLL_POWER_STATE_IN_OFF_0_MASK | PLL_POWER_STATE_IN_TXS2_0_MASK);
9729 data |= PLL_POWER_STATE_IN_OFF_0(7) | PLL_POWER_STATE_IN_TXS2_0(7);
9731 WREG32_PCIE_PORT(PB1_PIF_PWRDOWN_0, data);
9733 orig = data = RREG32_PCIE_PORT(PB1_PIF_PWRDOWN_1);
9734 data &= ~(PLL_POWER_STATE_IN_OFF_1_MASK | PLL_POWER_STATE_IN_TXS2_1_MASK);
9735 data |= PLL_POWER_STATE_IN_OFF_1(7) | PLL_POWER_STATE_IN_TXS2_1(7);
9737 WREG32_PCIE_PORT(PB1_PIF_PWRDOWN_1, data);
9739 orig = data = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
9740 data &= ~LC_DYN_LANES_PWR_STATE_MASK;
9741 data |= LC_DYN_LANES_PWR_STATE(3);
9743 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, data);
9745 if (!disable_clkreq &&
9746 !pci_is_root_bus(rdev->pdev->bus)) {
9747 struct pci_dev *root = rdev->pdev->bus->self;
9750 clk_req_support = false;
9751 pcie_capability_read_dword(root, PCI_EXP_LNKCAP, &lnkcap);
9752 if (lnkcap & PCI_EXP_LNKCAP_CLKPM)
9753 clk_req_support = true;
9755 clk_req_support = false;
9758 if (clk_req_support) {
9759 orig = data = RREG32_PCIE_PORT(PCIE_LC_CNTL2);
9760 data |= LC_ALLOW_PDWN_IN_L1 | LC_ALLOW_PDWN_IN_L23;
9762 WREG32_PCIE_PORT(PCIE_LC_CNTL2, data);
9764 orig = data = RREG32_SMC(THM_CLK_CNTL);
9765 data &= ~(CMON_CLK_SEL_MASK | TMON_CLK_SEL_MASK);
9766 data |= CMON_CLK_SEL(1) | TMON_CLK_SEL(1);
9768 WREG32_SMC(THM_CLK_CNTL, data);
9770 orig = data = RREG32_SMC(MISC_CLK_CTRL);
9771 data &= ~(DEEP_SLEEP_CLK_SEL_MASK | ZCLK_SEL_MASK);
9772 data |= DEEP_SLEEP_CLK_SEL(1) | ZCLK_SEL(1);
9774 WREG32_SMC(MISC_CLK_CTRL, data);
9776 orig = data = RREG32_SMC(CG_CLKPIN_CNTL);
9777 data &= ~BCLK_AS_XCLK;
9779 WREG32_SMC(CG_CLKPIN_CNTL, data);
9781 orig = data = RREG32_SMC(CG_CLKPIN_CNTL_2);
9782 data &= ~FORCE_BIF_REFCLK_EN;
9784 WREG32_SMC(CG_CLKPIN_CNTL_2, data);
9786 orig = data = RREG32_SMC(MPLL_BYPASSCLK_SEL);
9787 data &= ~MPLL_CLKOUT_SEL_MASK;
9788 data |= MPLL_CLKOUT_SEL(4);
9790 WREG32_SMC(MPLL_BYPASSCLK_SEL, data);
9795 WREG32_PCIE_PORT(PCIE_LC_CNTL, data);
9798 orig = data = RREG32_PCIE_PORT(PCIE_CNTL2);
9799 data |= SLV_MEM_LS_EN | MST_MEM_LS_EN | REPLAY_MEM_LS_EN;
9801 WREG32_PCIE_PORT(PCIE_CNTL2, data);
9804 data = RREG32_PCIE_PORT(PCIE_LC_N_FTS_CNTL);
9805 if((data & LC_N_FTS_MASK) == LC_N_FTS_MASK) {
9806 data = RREG32_PCIE_PORT(PCIE_LC_STATUS1);
9807 if ((data & LC_REVERSE_XMIT) && (data & LC_REVERSE_RCVR)) {
9808 orig = data = RREG32_PCIE_PORT(PCIE_LC_CNTL);
9809 data &= ~LC_L0S_INACTIVITY_MASK;
9811 WREG32_PCIE_PORT(PCIE_LC_CNTL, data);