2 * Copyright 2007-11 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
23 * Authors: Dave Airlie
27 #include "drm_crtc_helper.h"
28 #include "radeon_drm.h"
32 extern int atom_debug;
34 /* evil but including atombios.h is much worse */
35 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
36 struct drm_display_mode *mode);
39 static inline bool radeon_encoder_is_digital(struct drm_encoder *encoder)
41 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
42 switch (radeon_encoder->encoder_id) {
43 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
44 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
45 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
46 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
47 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
48 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
49 case ENCODER_OBJECT_ID_INTERNAL_DDI:
50 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
51 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
52 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
53 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
60 static bool radeon_atom_mode_fixup(struct drm_encoder *encoder,
61 struct drm_display_mode *mode,
62 struct drm_display_mode *adjusted_mode)
64 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
65 struct drm_device *dev = encoder->dev;
66 struct radeon_device *rdev = dev->dev_private;
68 /* set the active encoder to connector routing */
69 radeon_encoder_set_active_device(encoder);
70 drm_mode_set_crtcinfo(adjusted_mode, 0);
73 if ((mode->flags & DRM_MODE_FLAG_INTERLACE)
74 && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2)))
75 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2;
77 /* get the native mode for LVDS */
78 if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT))
79 radeon_panel_mode_fixup(encoder, adjusted_mode);
81 /* get the native mode for TV */
82 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) {
83 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
85 if (tv_dac->tv_std == TV_STD_NTSC ||
86 tv_dac->tv_std == TV_STD_NTSC_J ||
87 tv_dac->tv_std == TV_STD_PAL_M)
88 radeon_atom_get_tv_timings(rdev, 0, adjusted_mode);
90 radeon_atom_get_tv_timings(rdev, 1, adjusted_mode);
94 if (ASIC_IS_DCE3(rdev) &&
95 ((radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
96 (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE))) {
97 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
98 radeon_dp_set_link_config(connector, mode);
105 atombios_dac_setup(struct drm_encoder *encoder, int action)
107 struct drm_device *dev = encoder->dev;
108 struct radeon_device *rdev = dev->dev_private;
109 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
110 DAC_ENCODER_CONTROL_PS_ALLOCATION args;
112 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
114 memset(&args, 0, sizeof(args));
116 switch (radeon_encoder->encoder_id) {
117 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
118 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
119 index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl);
121 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
122 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
123 index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl);
127 args.ucAction = action;
129 if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT))
130 args.ucDacStandard = ATOM_DAC1_PS2;
131 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
132 args.ucDacStandard = ATOM_DAC1_CV;
134 switch (dac_info->tv_std) {
137 case TV_STD_SCART_PAL:
140 args.ucDacStandard = ATOM_DAC1_PAL;
146 args.ucDacStandard = ATOM_DAC1_NTSC;
150 args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
152 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
157 atombios_tv_setup(struct drm_encoder *encoder, int action)
159 struct drm_device *dev = encoder->dev;
160 struct radeon_device *rdev = dev->dev_private;
161 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
162 TV_ENCODER_CONTROL_PS_ALLOCATION args;
164 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
166 memset(&args, 0, sizeof(args));
168 index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl);
170 args.sTVEncoder.ucAction = action;
172 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
173 args.sTVEncoder.ucTvStandard = ATOM_TV_CV;
175 switch (dac_info->tv_std) {
177 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
180 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL;
183 args.sTVEncoder.ucTvStandard = ATOM_TV_PALM;
186 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60;
189 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ;
191 case TV_STD_SCART_PAL:
192 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */
195 args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM;
198 args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN;
201 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
206 args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
208 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
212 union dvo_encoder_control {
213 ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION ext_tmds;
214 DVO_ENCODER_CONTROL_PS_ALLOCATION dvo;
215 DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 dvo_v3;
219 atombios_dvo_setup(struct drm_encoder *encoder, int action)
221 struct drm_device *dev = encoder->dev;
222 struct radeon_device *rdev = dev->dev_private;
223 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
224 union dvo_encoder_control args;
225 int index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
228 memset(&args, 0, sizeof(args));
230 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
238 args.ext_tmds.sXTmdsEncoder.ucEnable = action;
240 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
241 args.ext_tmds.sXTmdsEncoder.ucMisc |= PANEL_ENCODER_MISC_DUAL;
243 args.ext_tmds.sXTmdsEncoder.ucMisc |= ATOM_PANEL_MISC_888RGB;
247 args.dvo.sDVOEncoder.ucAction = action;
248 args.dvo.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
249 /* DFP1, CRT1, TV1 depending on the type of port */
250 args.dvo.sDVOEncoder.ucDeviceType = ATOM_DEVICE_DFP1_INDEX;
252 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
253 args.dvo.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute |= PANEL_ENCODER_MISC_DUAL;
257 args.dvo_v3.ucAction = action;
258 args.dvo_v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
259 args.dvo_v3.ucDVOConfig = 0; /* XXX */
262 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
267 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
271 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
274 union lvds_encoder_control {
275 LVDS_ENCODER_CONTROL_PS_ALLOCATION v1;
276 LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2;
280 atombios_digital_setup(struct drm_encoder *encoder, int action)
282 struct drm_device *dev = encoder->dev;
283 struct radeon_device *rdev = dev->dev_private;
284 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
285 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
286 union lvds_encoder_control args;
288 int hdmi_detected = 0;
294 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
297 memset(&args, 0, sizeof(args));
299 switch (radeon_encoder->encoder_id) {
300 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
301 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
303 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
304 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
305 index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl);
307 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
308 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
309 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
311 index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl);
315 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
324 args.v1.ucAction = action;
326 args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
327 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
328 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
329 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
330 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
331 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
332 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
335 args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
336 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
337 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
338 /*if (pScrn->rgbBits == 8) */
339 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
345 args.v2.ucAction = action;
347 if (dig->coherent_mode)
348 args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT;
351 args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
352 args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
353 args.v2.ucTruncate = 0;
354 args.v2.ucSpatial = 0;
355 args.v2.ucTemporal = 0;
357 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
358 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
359 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
360 if (dig->lcd_misc & ATOM_PANEL_MISC_SPATIAL) {
361 args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN;
362 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
363 args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH;
365 if (dig->lcd_misc & ATOM_PANEL_MISC_TEMPORAL) {
366 args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN;
367 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
368 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH;
369 if (((dig->lcd_misc >> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT) & 0x3) == 2)
370 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4;
374 args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
375 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
376 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
380 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
385 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
389 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
393 atombios_get_encoder_mode(struct drm_encoder *encoder)
395 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
396 struct drm_connector *connector;
397 struct radeon_connector *radeon_connector;
398 struct radeon_connector_atom_dig *dig_connector;
400 /* dp bridges are always DP */
401 if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)
402 return ATOM_ENCODER_MODE_DP;
404 /* DVO is always DVO */
405 if (radeon_encoder->encoder_id == ATOM_ENCODER_MODE_DVO)
406 return ATOM_ENCODER_MODE_DVO;
408 connector = radeon_get_connector_for_encoder(encoder);
409 /* if we don't have an active device yet, just use one of
410 * the connectors tied to the encoder.
413 connector = radeon_get_connector_for_encoder_init(encoder);
414 radeon_connector = to_radeon_connector(connector);
416 switch (connector->connector_type) {
417 case DRM_MODE_CONNECTOR_DVII:
418 case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */
419 if (drm_detect_hdmi_monitor(radeon_connector->edid) &&
421 return ATOM_ENCODER_MODE_HDMI;
422 else if (radeon_connector->use_digital)
423 return ATOM_ENCODER_MODE_DVI;
425 return ATOM_ENCODER_MODE_CRT;
427 case DRM_MODE_CONNECTOR_DVID:
428 case DRM_MODE_CONNECTOR_HDMIA:
430 if (drm_detect_hdmi_monitor(radeon_connector->edid) &&
432 return ATOM_ENCODER_MODE_HDMI;
434 return ATOM_ENCODER_MODE_DVI;
436 case DRM_MODE_CONNECTOR_LVDS:
437 return ATOM_ENCODER_MODE_LVDS;
439 case DRM_MODE_CONNECTOR_DisplayPort:
440 dig_connector = radeon_connector->con_priv;
441 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
442 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP))
443 return ATOM_ENCODER_MODE_DP;
444 else if (drm_detect_hdmi_monitor(radeon_connector->edid) &&
446 return ATOM_ENCODER_MODE_HDMI;
448 return ATOM_ENCODER_MODE_DVI;
450 case DRM_MODE_CONNECTOR_eDP:
451 return ATOM_ENCODER_MODE_DP;
452 case DRM_MODE_CONNECTOR_DVIA:
453 case DRM_MODE_CONNECTOR_VGA:
454 return ATOM_ENCODER_MODE_CRT;
456 case DRM_MODE_CONNECTOR_Composite:
457 case DRM_MODE_CONNECTOR_SVIDEO:
458 case DRM_MODE_CONNECTOR_9PinDIN:
460 return ATOM_ENCODER_MODE_TV;
461 /*return ATOM_ENCODER_MODE_CV;*/
467 * DIG Encoder/Transmitter Setup
470 * - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA.
471 * Supports up to 3 digital outputs
472 * - 2 DIG encoder blocks.
473 * DIG1 can drive UNIPHY link A or link B
474 * DIG2 can drive UNIPHY link B or LVTMA
477 * - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B).
478 * Supports up to 5 digital outputs
479 * - 2 DIG encoder blocks.
480 * DIG1/2 can drive UNIPHY0/1/2 link A or link B
483 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
484 * Supports up to 6 digital outputs
485 * - 6 DIG encoder blocks.
486 * - DIG to PHY mapping is hardcoded
487 * DIG1 drives UNIPHY0 link A, A+B
488 * DIG2 drives UNIPHY0 link B
489 * DIG3 drives UNIPHY1 link A, A+B
490 * DIG4 drives UNIPHY1 link B
491 * DIG5 drives UNIPHY2 link A, A+B
492 * DIG6 drives UNIPHY2 link B
495 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
496 * Supports up to 6 digital outputs
497 * - 2 DIG encoder blocks.
499 * DIG1/2 can drive UNIPHY0/1/2 link A or link B
501 * DIG1 drives UNIPHY0/1/2 link A
502 * DIG2 drives UNIPHY0/1/2 link B
505 * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links)
507 * crtc0 -> dig2 -> LVTMA links A+B -> TMDS/HDMI
508 * crtc1 -> dig1 -> UNIPHY0 link B -> DP
509 * crtc0 -> dig1 -> UNIPHY2 link A -> LVDS
510 * crtc1 -> dig2 -> UNIPHY1 link B+A -> TMDS/HDMI
513 union dig_encoder_control {
514 DIG_ENCODER_CONTROL_PS_ALLOCATION v1;
515 DIG_ENCODER_CONTROL_PARAMETERS_V2 v2;
516 DIG_ENCODER_CONTROL_PARAMETERS_V3 v3;
517 DIG_ENCODER_CONTROL_PARAMETERS_V4 v4;
521 atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode)
523 struct drm_device *dev = encoder->dev;
524 struct radeon_device *rdev = dev->dev_private;
525 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
526 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
527 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
528 union dig_encoder_control args;
532 int dp_lane_count = 0;
533 int hpd_id = RADEON_HPD_NONE;
537 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
538 struct radeon_connector_atom_dig *dig_connector =
539 radeon_connector->con_priv;
541 dp_clock = dig_connector->dp_clock;
542 dp_lane_count = dig_connector->dp_lane_count;
543 hpd_id = radeon_connector->hpd.hpd;
544 /* bpc = connector->display_info.bpc; */
547 /* no dig encoder assigned */
548 if (dig->dig_encoder == -1)
551 memset(&args, 0, sizeof(args));
553 if (ASIC_IS_DCE4(rdev))
554 index = GetIndexIntoMasterTable(COMMAND, DIGxEncoderControl);
556 if (dig->dig_encoder)
557 index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl);
559 index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl);
562 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
569 args.v1.ucAction = action;
570 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
571 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
572 args.v3.ucPanelMode = panel_mode;
574 args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder);
576 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode))
577 args.v1.ucLaneNum = dp_lane_count;
578 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
579 args.v1.ucLaneNum = 8;
581 args.v1.ucLaneNum = 4;
583 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode) && (dp_clock == 270000))
584 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
585 switch (radeon_encoder->encoder_id) {
586 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
587 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1;
589 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
590 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
591 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2;
593 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
594 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3;
598 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB;
600 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA;
604 args.v3.ucAction = action;
605 args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
606 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
607 args.v3.ucPanelMode = panel_mode;
609 args.v3.ucEncoderMode = atombios_get_encoder_mode(encoder);
611 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode))
612 args.v3.ucLaneNum = dp_lane_count;
613 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
614 args.v3.ucLaneNum = 8;
616 args.v3.ucLaneNum = 4;
618 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode) && (dp_clock == 270000))
619 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
620 args.v3.acConfig.ucDigSel = dig->dig_encoder;
623 args.v3.ucBitPerColor = PANEL_BPC_UNDEFINE;
626 args.v3.ucBitPerColor = PANEL_6BIT_PER_COLOR;
630 args.v3.ucBitPerColor = PANEL_8BIT_PER_COLOR;
633 args.v3.ucBitPerColor = PANEL_10BIT_PER_COLOR;
636 args.v3.ucBitPerColor = PANEL_12BIT_PER_COLOR;
639 args.v3.ucBitPerColor = PANEL_16BIT_PER_COLOR;
644 args.v4.ucAction = action;
645 args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
646 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
647 args.v4.ucPanelMode = panel_mode;
649 args.v4.ucEncoderMode = atombios_get_encoder_mode(encoder);
651 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode))
652 args.v4.ucLaneNum = dp_lane_count;
653 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
654 args.v4.ucLaneNum = 8;
656 args.v4.ucLaneNum = 4;
658 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode)) {
659 if (dp_clock == 270000)
660 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ;
661 else if (dp_clock == 540000)
662 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ;
664 args.v4.acConfig.ucDigSel = dig->dig_encoder;
667 args.v4.ucBitPerColor = PANEL_BPC_UNDEFINE;
670 args.v4.ucBitPerColor = PANEL_6BIT_PER_COLOR;
674 args.v4.ucBitPerColor = PANEL_8BIT_PER_COLOR;
677 args.v4.ucBitPerColor = PANEL_10BIT_PER_COLOR;
680 args.v4.ucBitPerColor = PANEL_12BIT_PER_COLOR;
683 args.v4.ucBitPerColor = PANEL_16BIT_PER_COLOR;
686 if (hpd_id == RADEON_HPD_NONE)
687 args.v4.ucHPD_ID = 0;
689 args.v4.ucHPD_ID = hpd_id + 1;
692 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
697 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
701 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
705 union dig_transmitter_control {
706 DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1;
707 DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2;
708 DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3;
709 DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 v4;
710 DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5 v5;
714 atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set)
716 struct drm_device *dev = encoder->dev;
717 struct radeon_device *rdev = dev->dev_private;
718 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
719 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
720 struct drm_connector *connector;
721 union dig_transmitter_control args;
727 int dp_lane_count = 0;
728 int connector_object_id = 0;
729 int igp_lane_info = 0;
730 int dig_encoder = dig->dig_encoder;
731 int hpd_id = RADEON_HPD_NONE;
733 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
734 connector = radeon_get_connector_for_encoder_init(encoder);
735 /* just needed to avoid bailing in the encoder check. the encoder
736 * isn't used for init
740 connector = radeon_get_connector_for_encoder(encoder);
743 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
744 struct radeon_connector_atom_dig *dig_connector =
745 radeon_connector->con_priv;
747 hpd_id = radeon_connector->hpd.hpd;
748 dp_clock = dig_connector->dp_clock;
749 dp_lane_count = dig_connector->dp_lane_count;
750 connector_object_id =
751 (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
752 igp_lane_info = dig_connector->igp_lane_info;
756 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
757 pll_id = radeon_crtc->pll_id;
760 /* no dig encoder assigned */
761 if (dig_encoder == -1)
764 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)))
767 memset(&args, 0, sizeof(args));
769 switch (radeon_encoder->encoder_id) {
770 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
771 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
773 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
774 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
775 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
776 index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
778 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
779 index = GetIndexIntoMasterTable(COMMAND, LVTMATransmitterControl);
783 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
790 args.v1.ucAction = action;
791 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
792 args.v1.usInitInfo = cpu_to_le16(connector_object_id);
793 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
794 args.v1.asMode.ucLaneSel = lane_num;
795 args.v1.asMode.ucLaneSet = lane_set;
798 args.v1.usPixelClock =
799 cpu_to_le16(dp_clock / 10);
800 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
801 args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
803 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
806 args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL;
809 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER;
811 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER;
813 if ((rdev->flags & RADEON_IS_IGP) &&
814 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) {
816 !radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) {
817 if (igp_lane_info & 0x1)
818 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3;
819 else if (igp_lane_info & 0x2)
820 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7;
821 else if (igp_lane_info & 0x4)
822 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11;
823 else if (igp_lane_info & 0x8)
824 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15;
826 if (igp_lane_info & 0x3)
827 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7;
828 else if (igp_lane_info & 0xc)
829 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15;
834 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB;
836 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA;
839 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
840 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
841 if (dig->coherent_mode)
842 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
843 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
844 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK;
848 args.v2.ucAction = action;
849 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
850 args.v2.usInitInfo = cpu_to_le16(connector_object_id);
851 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
852 args.v2.asMode.ucLaneSel = lane_num;
853 args.v2.asMode.ucLaneSet = lane_set;
856 args.v2.usPixelClock =
857 cpu_to_le16(dp_clock / 10);
858 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
859 args.v2.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
861 args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
864 args.v2.acConfig.ucEncoderSel = dig_encoder;
866 args.v2.acConfig.ucLinkSel = 1;
868 switch (radeon_encoder->encoder_id) {
869 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
870 args.v2.acConfig.ucTransmitterSel = 0;
872 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
873 args.v2.acConfig.ucTransmitterSel = 1;
875 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
876 args.v2.acConfig.ucTransmitterSel = 2;
881 args.v2.acConfig.fCoherentMode = 1;
882 args.v2.acConfig.fDPConnector = 1;
883 } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
884 if (dig->coherent_mode)
885 args.v2.acConfig.fCoherentMode = 1;
886 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
887 args.v2.acConfig.fDualLinkConnector = 1;
891 args.v3.ucAction = action;
892 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
893 args.v3.usInitInfo = cpu_to_le16(connector_object_id);
894 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
895 args.v3.asMode.ucLaneSel = lane_num;
896 args.v3.asMode.ucLaneSet = lane_set;
899 args.v3.usPixelClock =
900 cpu_to_le16(dp_clock / 10);
901 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
902 args.v3.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
904 args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
908 args.v3.ucLaneNum = dp_lane_count;
909 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
910 args.v3.ucLaneNum = 8;
912 args.v3.ucLaneNum = 4;
915 args.v3.acConfig.ucLinkSel = 1;
917 args.v3.acConfig.ucEncoderSel = 1;
919 /* Select the PLL for the PHY
920 * DP PHY should be clocked from external src if there is
923 /* On DCE4, if there is an external clock, it generates the DP ref clock */
924 if (is_dp && rdev->clock.dp_extclk)
925 args.v3.acConfig.ucRefClkSource = 2; /* external src */
927 args.v3.acConfig.ucRefClkSource = pll_id;
929 switch (radeon_encoder->encoder_id) {
930 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
931 args.v3.acConfig.ucTransmitterSel = 0;
933 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
934 args.v3.acConfig.ucTransmitterSel = 1;
936 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
937 args.v3.acConfig.ucTransmitterSel = 2;
942 args.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */
943 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
944 if (dig->coherent_mode)
945 args.v3.acConfig.fCoherentMode = 1;
946 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
947 args.v3.acConfig.fDualLinkConnector = 1;
951 args.v4.ucAction = action;
952 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
953 args.v4.usInitInfo = cpu_to_le16(connector_object_id);
954 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
955 args.v4.asMode.ucLaneSel = lane_num;
956 args.v4.asMode.ucLaneSet = lane_set;
959 args.v4.usPixelClock =
960 cpu_to_le16(dp_clock / 10);
961 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
962 args.v4.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
964 args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
968 args.v4.ucLaneNum = dp_lane_count;
969 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
970 args.v4.ucLaneNum = 8;
972 args.v4.ucLaneNum = 4;
975 args.v4.acConfig.ucLinkSel = 1;
977 args.v4.acConfig.ucEncoderSel = 1;
979 /* Select the PLL for the PHY
980 * DP PHY should be clocked from external src if there is
983 /* On DCE5 DCPLL usually generates the DP ref clock */
985 if (rdev->clock.dp_extclk)
986 args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_EXTCLK;
988 args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_DCPLL;
990 args.v4.acConfig.ucRefClkSource = pll_id;
992 switch (radeon_encoder->encoder_id) {
993 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
994 args.v4.acConfig.ucTransmitterSel = 0;
996 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
997 args.v4.acConfig.ucTransmitterSel = 1;
999 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1000 args.v4.acConfig.ucTransmitterSel = 2;
1005 args.v4.acConfig.fCoherentMode = 1; /* DP requires coherent */
1006 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1007 if (dig->coherent_mode)
1008 args.v4.acConfig.fCoherentMode = 1;
1009 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1010 args.v4.acConfig.fDualLinkConnector = 1;
1014 args.v5.ucAction = action;
1016 args.v5.usSymClock = cpu_to_le16(dp_clock / 10);
1018 args.v5.usSymClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1020 switch (radeon_encoder->encoder_id) {
1021 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1023 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYB;
1025 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYA;
1027 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1029 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYD;
1031 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYC;
1033 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1035 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYF;
1037 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYE;
1041 args.v5.ucLaneNum = dp_lane_count;
1042 else if (radeon_encoder->pixel_clock > 165000)
1043 args.v5.ucLaneNum = 8;
1045 args.v5.ucLaneNum = 4;
1046 args.v5.ucConnObjId = connector_object_id;
1047 args.v5.ucDigMode = atombios_get_encoder_mode(encoder);
1049 if (is_dp && rdev->clock.dp_extclk)
1050 args.v5.asConfig.ucPhyClkSrcId = ENCODER_REFCLK_SRC_EXTCLK;
1052 args.v5.asConfig.ucPhyClkSrcId = pll_id;
1055 args.v5.asConfig.ucCoherentMode = 1; /* DP requires coherent */
1056 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1057 if (dig->coherent_mode)
1058 args.v5.asConfig.ucCoherentMode = 1;
1060 if (hpd_id == RADEON_HPD_NONE)
1061 args.v5.asConfig.ucHPDSel = 0;
1063 args.v5.asConfig.ucHPDSel = hpd_id + 1;
1064 args.v5.ucDigEncoderSel = 1 << dig_encoder;
1065 args.v5.ucDPLaneSet = lane_set;
1068 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1073 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1077 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1081 atombios_set_edp_panel_power(struct drm_connector *connector, int action)
1083 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1084 struct drm_device *dev = radeon_connector->base.dev;
1085 struct radeon_device *rdev = dev->dev_private;
1086 union dig_transmitter_control args;
1087 int index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
1090 if (connector->connector_type != DRM_MODE_CONNECTOR_eDP)
1093 if (!ASIC_IS_DCE4(rdev))
1096 if ((action != ATOM_TRANSMITTER_ACTION_POWER_ON) &&
1097 (action != ATOM_TRANSMITTER_ACTION_POWER_OFF))
1100 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1103 memset(&args, 0, sizeof(args));
1105 args.v1.ucAction = action;
1107 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1109 /* wait for the panel to power up */
1110 if (action == ATOM_TRANSMITTER_ACTION_POWER_ON) {
1113 for (i = 0; i < 300; i++) {
1114 if (radeon_hpd_sense(rdev, radeon_connector->hpd.hpd))
1124 union external_encoder_control {
1125 EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION v1;
1126 EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 v3;
1130 atombios_external_encoder_setup(struct drm_encoder *encoder,
1131 struct drm_encoder *ext_encoder,
1134 struct drm_device *dev = encoder->dev;
1135 struct radeon_device *rdev = dev->dev_private;
1136 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1137 struct radeon_encoder *ext_radeon_encoder = to_radeon_encoder(ext_encoder);
1138 union external_encoder_control args;
1139 struct drm_connector *connector;
1140 int index = GetIndexIntoMasterTable(COMMAND, ExternalEncoderControl);
1143 int dp_lane_count = 0;
1144 int connector_object_id = 0;
1145 u32 ext_enum = (ext_radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
1148 if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
1149 connector = radeon_get_connector_for_encoder_init(encoder);
1151 connector = radeon_get_connector_for_encoder(encoder);
1154 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1155 struct radeon_connector_atom_dig *dig_connector =
1156 radeon_connector->con_priv;
1158 dp_clock = dig_connector->dp_clock;
1159 dp_lane_count = dig_connector->dp_lane_count;
1160 connector_object_id =
1161 (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
1162 /* bpc = connector->display_info.bpc; */
1165 memset(&args, 0, sizeof(args));
1167 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1172 /* no params on frev 1 */
1178 args.v1.sDigEncoder.ucAction = action;
1179 args.v1.sDigEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1180 args.v1.sDigEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1182 if (ENCODER_MODE_IS_DP(args.v1.sDigEncoder.ucEncoderMode)) {
1183 if (dp_clock == 270000)
1184 args.v1.sDigEncoder.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
1185 args.v1.sDigEncoder.ucLaneNum = dp_lane_count;
1186 } else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1187 args.v1.sDigEncoder.ucLaneNum = 8;
1189 args.v1.sDigEncoder.ucLaneNum = 4;
1192 args.v3.sExtEncoder.ucAction = action;
1193 if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
1194 args.v3.sExtEncoder.usConnectorId = cpu_to_le16(connector_object_id);
1196 args.v3.sExtEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1197 args.v3.sExtEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1199 if (ENCODER_MODE_IS_DP(args.v3.sExtEncoder.ucEncoderMode)) {
1200 if (dp_clock == 270000)
1201 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
1202 else if (dp_clock == 540000)
1203 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ;
1204 args.v3.sExtEncoder.ucLaneNum = dp_lane_count;
1205 } else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1206 args.v3.sExtEncoder.ucLaneNum = 8;
1208 args.v3.sExtEncoder.ucLaneNum = 4;
1210 case GRAPH_OBJECT_ENUM_ID1:
1211 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER1;
1213 case GRAPH_OBJECT_ENUM_ID2:
1214 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER2;
1216 case GRAPH_OBJECT_ENUM_ID3:
1217 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER3;
1222 args.v3.sExtEncoder.ucBitPerColor = PANEL_BPC_UNDEFINE;
1225 args.v3.sExtEncoder.ucBitPerColor = PANEL_6BIT_PER_COLOR;
1229 args.v3.sExtEncoder.ucBitPerColor = PANEL_8BIT_PER_COLOR;
1232 args.v3.sExtEncoder.ucBitPerColor = PANEL_10BIT_PER_COLOR;
1235 args.v3.sExtEncoder.ucBitPerColor = PANEL_12BIT_PER_COLOR;
1238 args.v3.sExtEncoder.ucBitPerColor = PANEL_16BIT_PER_COLOR;
1243 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1248 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1251 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1255 atombios_yuv_setup(struct drm_encoder *encoder, bool enable)
1257 struct drm_device *dev = encoder->dev;
1258 struct radeon_device *rdev = dev->dev_private;
1259 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1260 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1261 ENABLE_YUV_PS_ALLOCATION args;
1262 int index = GetIndexIntoMasterTable(COMMAND, EnableYUV);
1265 memset(&args, 0, sizeof(args));
1267 if (rdev->family >= CHIP_R600)
1268 reg = R600_BIOS_3_SCRATCH;
1270 reg = RADEON_BIOS_3_SCRATCH;
1272 /* XXX: fix up scratch reg handling */
1274 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1275 WREG32(reg, (ATOM_S3_TV1_ACTIVE |
1276 (radeon_crtc->crtc_id << 18)));
1277 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1278 WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24)));
1283 args.ucEnable = ATOM_ENABLE;
1284 args.ucCRTC = radeon_crtc->crtc_id;
1286 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1292 radeon_atom_encoder_dpms_avivo(struct drm_encoder *encoder, int mode)
1294 struct drm_device *dev = encoder->dev;
1295 struct radeon_device *rdev = dev->dev_private;
1296 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1297 DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
1300 memset(&args, 0, sizeof(args));
1302 switch (radeon_encoder->encoder_id) {
1303 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1304 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1305 index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl);
1307 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1308 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1309 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1310 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1312 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1313 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1315 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1316 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1317 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1319 index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl);
1321 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1322 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1323 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1324 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1325 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1326 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1328 index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl);
1330 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1331 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1332 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1333 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1334 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1335 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1337 index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl);
1344 case DRM_MODE_DPMS_ON:
1345 args.ucAction = ATOM_ENABLE;
1346 /* workaround for DVOOutputControl on some RS690 systems */
1347 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DDI) {
1348 u32 reg = RREG32(RADEON_BIOS_3_SCRATCH);
1349 WREG32(RADEON_BIOS_3_SCRATCH, reg & ~ATOM_S3_DFP2I_ACTIVE);
1350 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1351 WREG32(RADEON_BIOS_3_SCRATCH, reg);
1353 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1354 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1355 args.ucAction = ATOM_LCD_BLON;
1356 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1359 case DRM_MODE_DPMS_STANDBY:
1360 case DRM_MODE_DPMS_SUSPEND:
1361 case DRM_MODE_DPMS_OFF:
1362 args.ucAction = ATOM_DISABLE;
1363 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1364 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1365 args.ucAction = ATOM_LCD_BLOFF;
1366 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1373 radeon_atom_encoder_dpms_dig(struct drm_encoder *encoder, int mode)
1375 struct drm_device *dev = encoder->dev;
1376 struct radeon_device *rdev = dev->dev_private;
1377 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1378 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1379 struct radeon_connector *radeon_connector = NULL;
1380 struct radeon_connector_atom_dig *radeon_dig_connector = NULL;
1383 radeon_connector = to_radeon_connector(connector);
1384 radeon_dig_connector = radeon_connector->con_priv;
1388 case DRM_MODE_DPMS_ON:
1389 /* some early dce3.2 boards have a bug in their transmitter control table */
1390 if ((rdev->family == CHIP_RV710) || (rdev->family == CHIP_RV730) ||
1391 ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev))
1392 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1394 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0);
1395 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
1396 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1397 atombios_set_edp_panel_power(connector,
1398 ATOM_TRANSMITTER_ACTION_POWER_ON);
1399 radeon_dig_connector->edp_on = true;
1401 radeon_dp_link_train(encoder, connector);
1402 if (ASIC_IS_DCE4(rdev))
1403 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON, 0);
1405 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1406 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0);
1408 case DRM_MODE_DPMS_STANDBY:
1409 case DRM_MODE_DPMS_SUSPEND:
1410 case DRM_MODE_DPMS_OFF:
1411 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev))
1412 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1414 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0);
1415 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
1416 if (ASIC_IS_DCE4(rdev))
1417 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0);
1418 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1419 atombios_set_edp_panel_power(connector,
1420 ATOM_TRANSMITTER_ACTION_POWER_OFF);
1421 radeon_dig_connector->edp_on = false;
1424 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1425 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0);
1431 radeon_atom_encoder_dpms_ext(struct drm_encoder *encoder,
1432 struct drm_encoder *ext_encoder,
1435 struct drm_device *dev = encoder->dev;
1436 struct radeon_device *rdev = dev->dev_private;
1439 case DRM_MODE_DPMS_ON:
1441 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)) {
1442 atombios_external_encoder_setup(encoder, ext_encoder,
1443 EXTERNAL_ENCODER_ACTION_V3_ENABLE_OUTPUT);
1444 atombios_external_encoder_setup(encoder, ext_encoder,
1445 EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING_OFF);
1447 atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE);
1449 case DRM_MODE_DPMS_STANDBY:
1450 case DRM_MODE_DPMS_SUSPEND:
1451 case DRM_MODE_DPMS_OFF:
1452 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)) {
1453 atombios_external_encoder_setup(encoder, ext_encoder,
1454 EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING);
1455 atombios_external_encoder_setup(encoder, ext_encoder,
1456 EXTERNAL_ENCODER_ACTION_V3_DISABLE_OUTPUT);
1458 atombios_external_encoder_setup(encoder, ext_encoder, ATOM_DISABLE);
1464 radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
1466 struct drm_device *dev = encoder->dev;
1467 struct radeon_device *rdev = dev->dev_private;
1468 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1469 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
1471 DRM_DEBUG_KMS("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n",
1472 radeon_encoder->encoder_id, mode, radeon_encoder->devices,
1473 radeon_encoder->active_device);
1474 switch (radeon_encoder->encoder_id) {
1475 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1476 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1477 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1478 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1479 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1480 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1481 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1482 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1483 radeon_atom_encoder_dpms_avivo(encoder, mode);
1485 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1486 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1487 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1488 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1489 radeon_atom_encoder_dpms_dig(encoder, mode);
1491 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1492 if (ASIC_IS_DCE5(rdev)) {
1494 case DRM_MODE_DPMS_ON:
1495 atombios_dvo_setup(encoder, ATOM_ENABLE);
1497 case DRM_MODE_DPMS_STANDBY:
1498 case DRM_MODE_DPMS_SUSPEND:
1499 case DRM_MODE_DPMS_OFF:
1500 atombios_dvo_setup(encoder, ATOM_DISABLE);
1503 } else if (ASIC_IS_DCE3(rdev))
1504 radeon_atom_encoder_dpms_dig(encoder, mode);
1506 radeon_atom_encoder_dpms_avivo(encoder, mode);
1508 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1509 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1510 if (ASIC_IS_DCE5(rdev)) {
1512 case DRM_MODE_DPMS_ON:
1513 atombios_dac_setup(encoder, ATOM_ENABLE);
1515 case DRM_MODE_DPMS_STANDBY:
1516 case DRM_MODE_DPMS_SUSPEND:
1517 case DRM_MODE_DPMS_OFF:
1518 atombios_dac_setup(encoder, ATOM_DISABLE);
1522 radeon_atom_encoder_dpms_avivo(encoder, mode);
1529 radeon_atom_encoder_dpms_ext(encoder, ext_encoder, mode);
1531 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
1535 union crtc_source_param {
1536 SELECT_CRTC_SOURCE_PS_ALLOCATION v1;
1537 SELECT_CRTC_SOURCE_PARAMETERS_V2 v2;
1541 atombios_set_encoder_crtc_source(struct drm_encoder *encoder)
1543 struct drm_device *dev = encoder->dev;
1544 struct radeon_device *rdev = dev->dev_private;
1545 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1546 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1547 union crtc_source_param args;
1548 int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source);
1550 struct radeon_encoder_atom_dig *dig;
1552 memset(&args, 0, sizeof(args));
1554 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1562 if (ASIC_IS_AVIVO(rdev))
1563 args.v1.ucCRTC = radeon_crtc->crtc_id;
1565 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) {
1566 args.v1.ucCRTC = radeon_crtc->crtc_id;
1568 args.v1.ucCRTC = radeon_crtc->crtc_id << 2;
1571 switch (radeon_encoder->encoder_id) {
1572 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1573 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1574 args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX;
1576 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1577 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1578 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT)
1579 args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX;
1581 args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX;
1583 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1584 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1585 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1586 args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX;
1588 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1589 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1590 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1591 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1592 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1593 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1595 args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX;
1597 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1598 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1599 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1600 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1601 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1602 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1604 args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX;
1609 args.v2.ucCRTC = radeon_crtc->crtc_id;
1610 if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE) {
1611 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1613 if (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)
1614 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS;
1615 else if (connector->connector_type == DRM_MODE_CONNECTOR_VGA)
1616 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_CRT;
1618 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1620 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1621 switch (radeon_encoder->encoder_id) {
1622 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1623 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1624 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1625 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1626 dig = radeon_encoder->enc_priv;
1627 switch (dig->dig_encoder) {
1629 args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
1632 args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
1635 args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID;
1638 args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID;
1641 args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID;
1644 args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID;
1648 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1649 args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID;
1651 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1652 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1653 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1654 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1655 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1657 args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID;
1659 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1660 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1661 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1662 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1663 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1665 args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID;
1672 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1676 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1678 /* update scratch regs with new routing */
1679 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
1683 atombios_apply_encoder_quirks(struct drm_encoder *encoder,
1684 struct drm_display_mode *mode)
1686 struct drm_device *dev = encoder->dev;
1687 struct radeon_device *rdev = dev->dev_private;
1688 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1689 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1691 /* Funky macbooks */
1692 if ((dev->pdev->device == 0x71C5) &&
1693 (dev->pdev->subsystem_vendor == 0x106b) &&
1694 (dev->pdev->subsystem_device == 0x0080)) {
1695 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
1696 uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL);
1698 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN;
1699 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN;
1701 WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control);
1705 /* set scaler clears this on some chips */
1706 if (ASIC_IS_AVIVO(rdev) &&
1707 (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)))) {
1708 if (ASIC_IS_DCE4(rdev)) {
1709 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1710 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset,
1711 EVERGREEN_INTERLEAVE_EN);
1713 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
1715 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1716 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
1717 AVIVO_D1MODE_INTERLEAVE_EN);
1719 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
1724 static int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder)
1726 struct drm_device *dev = encoder->dev;
1727 struct radeon_device *rdev = dev->dev_private;
1728 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1729 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1730 struct drm_encoder *test_encoder;
1731 struct radeon_encoder_atom_dig *dig;
1732 uint32_t dig_enc_in_use = 0;
1735 if (ASIC_IS_DCE4(rdev)) {
1736 dig = radeon_encoder->enc_priv;
1737 if (ASIC_IS_DCE41(rdev)) {
1738 /* ontario follows DCE4 */
1739 if (rdev->family == CHIP_PALM) {
1745 /* llano follows DCE3.2 */
1746 return radeon_crtc->crtc_id;
1748 switch (radeon_encoder->encoder_id) {
1749 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1755 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1761 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1771 /* on DCE32 and encoder can driver any block so just crtc id */
1772 if (ASIC_IS_DCE32(rdev)) {
1773 return radeon_crtc->crtc_id;
1776 /* on DCE3 - LVTMA can only be driven by DIGB */
1777 list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
1778 struct radeon_encoder *radeon_test_encoder;
1780 if (encoder == test_encoder)
1783 if (!radeon_encoder_is_digital(test_encoder))
1786 radeon_test_encoder = to_radeon_encoder(test_encoder);
1787 dig = radeon_test_encoder->enc_priv;
1789 if (dig->dig_encoder >= 0)
1790 dig_enc_in_use |= (1 << dig->dig_encoder);
1793 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA) {
1794 if (dig_enc_in_use & 0x2)
1795 DRM_ERROR("LVDS required digital encoder 2 but it was in use - stealing\n");
1798 if (!(dig_enc_in_use & 1))
1803 /* This only needs to be called once at startup */
1805 radeon_atom_encoder_init(struct radeon_device *rdev)
1807 struct drm_device *dev = rdev->ddev;
1808 struct drm_encoder *encoder;
1810 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1811 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1812 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
1814 switch (radeon_encoder->encoder_id) {
1815 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1816 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1817 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1818 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1819 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0);
1825 if (ext_encoder && (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)))
1826 atombios_external_encoder_setup(encoder, ext_encoder,
1827 EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT);
1832 radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
1833 struct drm_display_mode *mode,
1834 struct drm_display_mode *adjusted_mode)
1836 struct drm_device *dev = encoder->dev;
1837 struct radeon_device *rdev = dev->dev_private;
1838 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1839 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
1841 radeon_encoder->pixel_clock = adjusted_mode->clock;
1843 if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE4(rdev)) {
1844 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT))
1845 atombios_yuv_setup(encoder, true);
1847 atombios_yuv_setup(encoder, false);
1850 switch (radeon_encoder->encoder_id) {
1851 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1852 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1853 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1854 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1855 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE);
1857 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1858 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1859 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1860 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1861 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) {
1862 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1863 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
1866 dig->panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
1868 dig->panel_mode = radeon_dp_get_panel_mode(encoder, connector);
1870 /* setup and enable the encoder */
1871 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
1872 atombios_dig_encoder_setup(encoder,
1873 ATOM_ENCODER_CMD_SETUP_PANEL_MODE,
1875 } else if (ASIC_IS_DCE4(rdev)) {
1876 /* disable the transmitter */
1877 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1878 /* setup and enable the encoder */
1879 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
1881 /* enable the transmitter */
1882 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1884 /* disable the encoder and transmitter */
1885 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1886 atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0);
1888 /* setup and enable the encoder and transmitter */
1889 atombios_dig_encoder_setup(encoder, ATOM_ENABLE, 0);
1890 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0);
1891 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1894 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1895 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1896 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1897 atombios_dvo_setup(encoder, ATOM_ENABLE);
1899 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1900 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1901 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1902 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1903 atombios_dac_setup(encoder, ATOM_ENABLE);
1904 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) {
1905 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
1906 atombios_tv_setup(encoder, ATOM_ENABLE);
1908 atombios_tv_setup(encoder, ATOM_DISABLE);
1914 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev))
1915 atombios_external_encoder_setup(encoder, ext_encoder,
1916 EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP);
1918 atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE);
1921 atombios_apply_encoder_quirks(encoder, adjusted_mode);
1923 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
1924 r600_hdmi_enable(encoder);
1925 r600_hdmi_setmode(encoder, adjusted_mode);
1930 atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector)
1932 struct drm_device *dev = encoder->dev;
1933 struct radeon_device *rdev = dev->dev_private;
1934 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1935 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1937 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT |
1938 ATOM_DEVICE_CV_SUPPORT |
1939 ATOM_DEVICE_CRT_SUPPORT)) {
1940 DAC_LOAD_DETECTION_PS_ALLOCATION args;
1941 int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection);
1944 memset(&args, 0, sizeof(args));
1946 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1949 args.sDacload.ucMisc = 0;
1951 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) ||
1952 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1))
1953 args.sDacload.ucDacType = ATOM_DAC_A;
1955 args.sDacload.ucDacType = ATOM_DAC_B;
1957 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)
1958 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT);
1959 else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)
1960 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT);
1961 else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
1962 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT);
1964 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
1965 } else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
1966 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT);
1968 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
1971 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1978 static enum drm_connector_status
1979 radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
1981 struct drm_device *dev = encoder->dev;
1982 struct radeon_device *rdev = dev->dev_private;
1983 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1984 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1985 uint32_t bios_0_scratch;
1987 if (!atombios_dac_load_detect(encoder, connector)) {
1988 DRM_DEBUG_KMS("detect returned false \n");
1989 return connector_status_unknown;
1992 if (rdev->family >= CHIP_R600)
1993 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
1995 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
1997 DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
1998 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
1999 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
2000 return connector_status_connected;
2002 if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2003 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
2004 return connector_status_connected;
2006 if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2007 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
2008 return connector_status_connected;
2010 if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2011 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
2012 return connector_status_connected; /* CTV */
2013 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
2014 return connector_status_connected; /* STV */
2016 return connector_status_disconnected;
2019 static enum drm_connector_status
2020 radeon_atom_dig_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2022 struct drm_device *dev = encoder->dev;
2023 struct radeon_device *rdev = dev->dev_private;
2024 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2025 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2026 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
2029 if (!ASIC_IS_DCE4(rdev))
2030 return connector_status_unknown;
2033 return connector_status_unknown;
2035 if ((radeon_connector->devices & ATOM_DEVICE_CRT_SUPPORT) == 0)
2036 return connector_status_unknown;
2038 /* load detect on the dp bridge */
2039 atombios_external_encoder_setup(encoder, ext_encoder,
2040 EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION);
2042 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2044 DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
2045 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2046 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
2047 return connector_status_connected;
2049 if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2050 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
2051 return connector_status_connected;
2053 if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2054 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
2055 return connector_status_connected;
2057 if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2058 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
2059 return connector_status_connected; /* CTV */
2060 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
2061 return connector_status_connected; /* STV */
2063 return connector_status_disconnected;
2067 radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder)
2069 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
2072 /* ddc_setup on the dp bridge */
2073 atombios_external_encoder_setup(encoder, ext_encoder,
2074 EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP);
2078 static void radeon_atom_encoder_prepare(struct drm_encoder *encoder)
2080 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2081 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
2083 if ((radeon_encoder->active_device &
2084 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
2085 (radeon_encoder_get_dp_bridge_encoder_id(encoder) !=
2086 ENCODER_OBJECT_ID_NONE)) {
2087 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
2089 dig->dig_encoder = radeon_atom_pick_dig_encoder(encoder);
2092 radeon_atom_output_lock(encoder, true);
2093 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
2096 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2098 /* select the clock/data port if it uses a router */
2099 if (radeon_connector->router.cd_valid)
2100 radeon_router_select_cd_port(radeon_connector);
2102 /* turn eDP panel on for mode set */
2103 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
2104 atombios_set_edp_panel_power(connector,
2105 ATOM_TRANSMITTER_ACTION_POWER_ON);
2108 /* this is needed for the pll/ss setup to work correctly in some cases */
2109 atombios_set_encoder_crtc_source(encoder);
2112 static void radeon_atom_encoder_commit(struct drm_encoder *encoder)
2114 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
2115 radeon_atom_output_lock(encoder, false);
2118 static void radeon_atom_encoder_disable(struct drm_encoder *encoder)
2120 struct drm_device *dev = encoder->dev;
2121 struct radeon_device *rdev = dev->dev_private;
2122 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2123 struct radeon_encoder_atom_dig *dig;
2125 /* check for pre-DCE3 cards with shared encoders;
2126 * can't really use the links individually, so don't disable
2127 * the encoder if it's in use by another connector
2129 if (!ASIC_IS_DCE3(rdev)) {
2130 struct drm_encoder *other_encoder;
2131 struct radeon_encoder *other_radeon_encoder;
2133 list_for_each_entry(other_encoder, &dev->mode_config.encoder_list, head) {
2134 other_radeon_encoder = to_radeon_encoder(other_encoder);
2135 if ((radeon_encoder->encoder_id == other_radeon_encoder->encoder_id) &&
2136 drm_helper_encoder_in_use(other_encoder))
2141 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
2143 switch (radeon_encoder->encoder_id) {
2144 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2145 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2146 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2147 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2148 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_DISABLE);
2150 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2151 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2152 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2153 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2154 if (ASIC_IS_DCE4(rdev))
2155 /* disable the transmitter */
2156 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
2158 /* disable the encoder and transmitter */
2159 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
2160 atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0);
2163 case ENCODER_OBJECT_ID_INTERNAL_DDI:
2164 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2165 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2166 atombios_dvo_setup(encoder, ATOM_DISABLE);
2168 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2169 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2170 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2171 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2172 atombios_dac_setup(encoder, ATOM_DISABLE);
2173 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
2174 atombios_tv_setup(encoder, ATOM_DISABLE);
2179 if (radeon_encoder_is_digital(encoder)) {
2180 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
2181 r600_hdmi_disable(encoder);
2182 dig = radeon_encoder->enc_priv;
2183 dig->dig_encoder = -1;
2185 radeon_encoder->active_device = 0;
2188 /* these are handled by the primary encoders */
2189 static void radeon_atom_ext_prepare(struct drm_encoder *encoder)
2194 static void radeon_atom_ext_commit(struct drm_encoder *encoder)
2200 radeon_atom_ext_mode_set(struct drm_encoder *encoder,
2201 struct drm_display_mode *mode,
2202 struct drm_display_mode *adjusted_mode)
2207 static void radeon_atom_ext_disable(struct drm_encoder *encoder)
2213 radeon_atom_ext_dpms(struct drm_encoder *encoder, int mode)
2218 static bool radeon_atom_ext_mode_fixup(struct drm_encoder *encoder,
2219 struct drm_display_mode *mode,
2220 struct drm_display_mode *adjusted_mode)
2225 static const struct drm_encoder_helper_funcs radeon_atom_ext_helper_funcs = {
2226 .dpms = radeon_atom_ext_dpms,
2227 .mode_fixup = radeon_atom_ext_mode_fixup,
2228 .prepare = radeon_atom_ext_prepare,
2229 .mode_set = radeon_atom_ext_mode_set,
2230 .commit = radeon_atom_ext_commit,
2231 .disable = radeon_atom_ext_disable,
2232 /* no detect for TMDS/LVDS yet */
2235 static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = {
2236 .dpms = radeon_atom_encoder_dpms,
2237 .mode_fixup = radeon_atom_mode_fixup,
2238 .prepare = radeon_atom_encoder_prepare,
2239 .mode_set = radeon_atom_encoder_mode_set,
2240 .commit = radeon_atom_encoder_commit,
2241 .disable = radeon_atom_encoder_disable,
2242 .detect = radeon_atom_dig_detect,
2245 static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = {
2246 .dpms = radeon_atom_encoder_dpms,
2247 .mode_fixup = radeon_atom_mode_fixup,
2248 .prepare = radeon_atom_encoder_prepare,
2249 .mode_set = radeon_atom_encoder_mode_set,
2250 .commit = radeon_atom_encoder_commit,
2251 .detect = radeon_atom_dac_detect,
2254 void radeon_enc_destroy(struct drm_encoder *encoder)
2256 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2257 kfree(radeon_encoder->enc_priv);
2258 drm_encoder_cleanup(encoder);
2259 kfree(radeon_encoder);
2262 static const struct drm_encoder_funcs radeon_atom_enc_funcs = {
2263 .destroy = radeon_enc_destroy,
2266 struct radeon_encoder_atom_dac *
2267 radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder)
2269 struct drm_device *dev = radeon_encoder->base.dev;
2270 struct radeon_device *rdev = dev->dev_private;
2271 struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL);
2276 dac->tv_std = radeon_atombios_get_tv_info(rdev);
2280 struct radeon_encoder_atom_dig *
2281 radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder)
2283 int encoder_enum = (radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
2284 struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
2289 /* coherent mode by default */
2290 dig->coherent_mode = true;
2291 dig->dig_encoder = -1;
2293 if (encoder_enum == 2)
2302 radeon_add_atom_encoder(struct drm_device *dev,
2303 uint32_t encoder_enum,
2304 uint32_t supported_device,
2307 struct radeon_device *rdev = dev->dev_private;
2308 struct drm_encoder *encoder;
2309 struct radeon_encoder *radeon_encoder;
2311 /* see if we already added it */
2312 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2313 radeon_encoder = to_radeon_encoder(encoder);
2314 if (radeon_encoder->encoder_enum == encoder_enum) {
2315 radeon_encoder->devices |= supported_device;
2322 radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
2323 if (!radeon_encoder)
2326 encoder = &radeon_encoder->base;
2327 switch (rdev->num_crtc) {
2329 encoder->possible_crtcs = 0x1;
2333 encoder->possible_crtcs = 0x3;
2336 encoder->possible_crtcs = 0xf;
2339 encoder->possible_crtcs = 0x3f;
2343 radeon_encoder->enc_priv = NULL;
2345 radeon_encoder->encoder_enum = encoder_enum;
2346 radeon_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
2347 radeon_encoder->devices = supported_device;
2348 radeon_encoder->rmx_type = RMX_OFF;
2349 radeon_encoder->underscan_type = UNDERSCAN_OFF;
2350 radeon_encoder->is_ext_encoder = false;
2351 radeon_encoder->caps = caps;
2353 switch (radeon_encoder->encoder_id) {
2354 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2355 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2356 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2357 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2358 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2359 radeon_encoder->rmx_type = RMX_FULL;
2360 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2361 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
2363 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2364 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2366 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
2368 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2369 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2370 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
2371 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
2373 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2374 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2375 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2376 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TVDAC);
2377 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
2378 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
2380 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2381 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2382 case ENCODER_OBJECT_ID_INTERNAL_DDI:
2383 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2384 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2385 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2386 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2387 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2388 radeon_encoder->rmx_type = RMX_FULL;
2389 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2390 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
2391 } else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
2392 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2393 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2395 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2396 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2398 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
2400 case ENCODER_OBJECT_ID_SI170B:
2401 case ENCODER_OBJECT_ID_CH7303:
2402 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
2403 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
2404 case ENCODER_OBJECT_ID_TITFP513:
2405 case ENCODER_OBJECT_ID_VT1623:
2406 case ENCODER_OBJECT_ID_HDMI_SI1930:
2407 case ENCODER_OBJECT_ID_TRAVIS:
2408 case ENCODER_OBJECT_ID_NUTMEG:
2409 /* these are handled by the primary encoders */
2410 radeon_encoder->is_ext_encoder = true;
2411 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
2412 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2413 else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
2414 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2416 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2417 drm_encoder_helper_add(encoder, &radeon_atom_ext_helper_funcs);