2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
23 * Authors: Dave Airlie
28 #include <drm/radeon_drm.h>
32 #include "atom-bits.h"
33 #include <drm/drm_dp_helper.h>
35 /* move these to drm_dp_helper.c/h */
36 #define DP_LINK_CONFIGURATION_SIZE 9
37 #define DP_LINK_STATUS_SIZE 6
38 #define DP_DPCD_SIZE 8
40 static char *voltage_names[] = {
41 "0.4V", "0.6V", "0.8V", "1.2V"
43 static char *pre_emph_names[] = {
44 "0dB", "3.5dB", "6dB", "9.5dB"
47 /***** radeon AUX functions *****/
48 union aux_channel_transaction {
49 PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION v1;
50 PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2 v2;
53 static int radeon_process_aux_ch(struct radeon_i2c_chan *chan,
54 u8 *send, int send_bytes,
55 u8 *recv, int recv_size,
58 struct drm_device *dev = chan->dev;
59 struct radeon_device *rdev = dev->dev_private;
60 union aux_channel_transaction args;
61 int index = GetIndexIntoMasterTable(COMMAND, ProcessAuxChannelTransaction);
65 memset(&args, 0, sizeof(args));
67 base = (unsigned char *)(rdev->mode_info.atom_context->scratch + 1);
69 memcpy(base, send, send_bytes);
71 args.v1.lpAuxRequest = 0 + 4;
72 args.v1.lpDataOut = 16 + 4;
73 args.v1.ucDataOutLen = 0;
74 args.v1.ucChannelID = chan->rec.i2c_id;
75 args.v1.ucDelay = delay / 10;
76 if (ASIC_IS_DCE4(rdev))
77 args.v2.ucHPD_ID = chan->rec.hpd;
79 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
81 *ack = args.v1.ucReplyStatus;
84 if (args.v1.ucReplyStatus == 1) {
85 DRM_DEBUG_KMS("dp_aux_ch timeout\n");
90 if (args.v1.ucReplyStatus == 2) {
91 DRM_DEBUG_KMS("dp_aux_ch flags not zero\n");
96 if (args.v1.ucReplyStatus == 3) {
97 DRM_DEBUG_KMS("dp_aux_ch error\n");
101 recv_bytes = args.v1.ucDataOutLen;
102 if (recv_bytes > recv_size)
103 recv_bytes = recv_size;
105 if (recv && recv_size)
106 memcpy(recv, base + 16, recv_bytes);
111 static int radeon_dp_aux_native_write(struct radeon_connector *radeon_connector,
112 u16 address, u8 *send, u8 send_bytes, u8 delay)
114 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
117 int msg_bytes = send_bytes + 4;
125 msg[1] = address >> 8;
126 msg[2] = AUX_NATIVE_WRITE << 4;
127 msg[3] = (msg_bytes << 4) | (send_bytes - 1);
128 memcpy(&msg[4], send, send_bytes);
130 for (retry = 0; retry < 4; retry++) {
131 ret = radeon_process_aux_ch(dig_connector->dp_i2c_bus,
132 msg, msg_bytes, NULL, 0, delay, &ack);
137 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
139 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
148 static int radeon_dp_aux_native_read(struct radeon_connector *radeon_connector,
149 u16 address, u8 *recv, int recv_bytes, u8 delay)
151 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
159 msg[1] = address >> 8;
160 msg[2] = AUX_NATIVE_READ << 4;
161 msg[3] = (msg_bytes << 4) | (recv_bytes - 1);
163 for (retry = 0; retry < 4; retry++) {
164 ret = radeon_process_aux_ch(dig_connector->dp_i2c_bus,
165 msg, msg_bytes, recv, recv_bytes, delay, &ack);
170 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
172 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
183 static void radeon_write_dpcd_reg(struct radeon_connector *radeon_connector,
186 radeon_dp_aux_native_write(radeon_connector, reg, &val, 1, 0);
189 static u8 radeon_read_dpcd_reg(struct radeon_connector *radeon_connector,
194 radeon_dp_aux_native_read(radeon_connector, reg, &val, 1, 0);
199 int radeon_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
200 u8 write_byte, u8 *read_byte)
202 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
203 struct radeon_i2c_chan *auxch = (struct radeon_i2c_chan *)adapter;
204 u16 address = algo_data->address;
213 /* Set up the command byte */
214 if (mode & MODE_I2C_READ)
215 msg[2] = AUX_I2C_READ << 4;
217 msg[2] = AUX_I2C_WRITE << 4;
219 if (!(mode & MODE_I2C_STOP))
220 msg[2] |= AUX_I2C_MOT << 4;
223 msg[1] = address >> 8;
228 msg[3] = msg_bytes << 4;
233 msg[3] = msg_bytes << 4;
241 for (retry = 0; retry < 4; retry++) {
242 ret = radeon_process_aux_ch(auxch,
243 msg, msg_bytes, reply, reply_bytes, 0, &ack);
247 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
251 switch (ack & AUX_NATIVE_REPLY_MASK) {
252 case AUX_NATIVE_REPLY_ACK:
253 /* I2C-over-AUX Reply field is only valid
254 * when paired with AUX ACK.
257 case AUX_NATIVE_REPLY_NACK:
258 DRM_DEBUG_KMS("aux_ch native nack\n");
260 case AUX_NATIVE_REPLY_DEFER:
261 DRM_DEBUG_KMS("aux_ch native defer\n");
265 DRM_ERROR("aux_ch invalid native reply 0x%02x\n", ack);
269 switch (ack & AUX_I2C_REPLY_MASK) {
270 case AUX_I2C_REPLY_ACK:
271 if (mode == MODE_I2C_READ)
272 *read_byte = reply[0];
274 case AUX_I2C_REPLY_NACK:
275 DRM_DEBUG_KMS("aux_i2c nack\n");
277 case AUX_I2C_REPLY_DEFER:
278 DRM_DEBUG_KMS("aux_i2c defer\n");
282 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", ack);
287 DRM_DEBUG_KMS("aux i2c too many retries, giving up\n");
291 /***** general DP utility functions *****/
293 static u8 dp_link_status(u8 link_status[DP_LINK_STATUS_SIZE], int r)
295 return link_status[r - DP_LANE0_1_STATUS];
298 static u8 dp_get_lane_status(u8 link_status[DP_LINK_STATUS_SIZE],
301 int i = DP_LANE0_1_STATUS + (lane >> 1);
302 int s = (lane & 1) * 4;
303 u8 l = dp_link_status(link_status, i);
304 return (l >> s) & 0xf;
307 static bool dp_clock_recovery_ok(u8 link_status[DP_LINK_STATUS_SIZE],
313 for (lane = 0; lane < lane_count; lane++) {
314 lane_status = dp_get_lane_status(link_status, lane);
315 if ((lane_status & DP_LANE_CR_DONE) == 0)
321 static bool dp_channel_eq_ok(u8 link_status[DP_LINK_STATUS_SIZE],
328 lane_align = dp_link_status(link_status,
329 DP_LANE_ALIGN_STATUS_UPDATED);
330 if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
332 for (lane = 0; lane < lane_count; lane++) {
333 lane_status = dp_get_lane_status(link_status, lane);
334 if ((lane_status & DP_CHANNEL_EQ_BITS) != DP_CHANNEL_EQ_BITS)
340 static u8 dp_get_adjust_request_voltage(u8 link_status[DP_LINK_STATUS_SIZE],
344 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
345 int s = ((lane & 1) ?
346 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
347 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
348 u8 l = dp_link_status(link_status, i);
350 return ((l >> s) & 0x3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
353 static u8 dp_get_adjust_request_pre_emphasis(u8 link_status[DP_LINK_STATUS_SIZE],
356 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
357 int s = ((lane & 1) ?
358 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
359 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
360 u8 l = dp_link_status(link_status, i);
362 return ((l >> s) & 0x3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
365 #define DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_1200
366 #define DP_PRE_EMPHASIS_MAX DP_TRAIN_PRE_EMPHASIS_9_5
368 static void dp_get_adjust_train(u8 link_status[DP_LINK_STATUS_SIZE],
376 for (lane = 0; lane < lane_count; lane++) {
377 u8 this_v = dp_get_adjust_request_voltage(link_status, lane);
378 u8 this_p = dp_get_adjust_request_pre_emphasis(link_status, lane);
380 DRM_DEBUG_KMS("requested signal parameters: lane %d voltage %s pre_emph %s\n",
382 voltage_names[this_v >> DP_TRAIN_VOLTAGE_SWING_SHIFT],
383 pre_emph_names[this_p >> DP_TRAIN_PRE_EMPHASIS_SHIFT]);
391 if (v >= DP_VOLTAGE_MAX)
392 v |= DP_TRAIN_MAX_SWING_REACHED;
394 if (p >= DP_PRE_EMPHASIS_MAX)
395 p |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
397 DRM_DEBUG_KMS("using signal parameters: voltage %s pre_emph %s\n",
398 voltage_names[(v & DP_TRAIN_VOLTAGE_SWING_MASK) >> DP_TRAIN_VOLTAGE_SWING_SHIFT],
399 pre_emph_names[(p & DP_TRAIN_PRE_EMPHASIS_MASK) >> DP_TRAIN_PRE_EMPHASIS_SHIFT]);
401 for (lane = 0; lane < 4; lane++)
402 train_set[lane] = v | p;
405 /* convert bits per color to bits per pixel */
406 /* get bpc from the EDID */
407 static int convert_bpc_to_bpp(int bpc)
415 /* get the max pix clock supported by the link rate and lane num */
416 static int dp_get_max_dp_pix_clock(int link_rate,
420 return (link_rate * lane_num * 8) / bpp;
423 static int dp_get_max_link_rate(u8 dpcd[DP_DPCD_SIZE])
425 switch (dpcd[DP_MAX_LINK_RATE]) {
426 case DP_LINK_BW_1_62:
436 static u8 dp_get_max_lane_number(u8 dpcd[DP_DPCD_SIZE])
438 return dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK;
441 static u8 dp_get_dp_link_rate_coded(int link_rate)
446 return DP_LINK_BW_1_62;
448 return DP_LINK_BW_2_7;
450 return DP_LINK_BW_5_4;
454 /***** radeon specific DP functions *****/
456 /* First get the min lane# when low rate is used according to pixel clock
457 * (prefer low rate), second check max lane# supported by DP panel,
458 * if the max lane# < low rate lane# then use max lane# instead.
460 static int radeon_dp_get_dp_lane_number(struct drm_connector *connector,
461 u8 dpcd[DP_DPCD_SIZE],
464 int bpp = convert_bpc_to_bpp(radeon_get_monitor_bpc(connector));
465 int max_link_rate = dp_get_max_link_rate(dpcd);
466 int max_lane_num = dp_get_max_lane_number(dpcd);
468 int max_dp_pix_clock;
470 for (lane_num = 1; lane_num < max_lane_num; lane_num <<= 1) {
471 max_dp_pix_clock = dp_get_max_dp_pix_clock(max_link_rate, lane_num, bpp);
472 if (pix_clock <= max_dp_pix_clock)
479 static int radeon_dp_get_dp_link_clock(struct drm_connector *connector,
480 u8 dpcd[DP_DPCD_SIZE],
483 int bpp = convert_bpc_to_bpp(radeon_get_monitor_bpc(connector));
484 int lane_num, max_pix_clock;
486 if (radeon_connector_encoder_get_dp_bridge_encoder_id(connector) ==
487 ENCODER_OBJECT_ID_NUTMEG)
490 lane_num = radeon_dp_get_dp_lane_number(connector, dpcd, pix_clock);
491 max_pix_clock = dp_get_max_dp_pix_clock(162000, lane_num, bpp);
492 if (pix_clock <= max_pix_clock)
494 max_pix_clock = dp_get_max_dp_pix_clock(270000, lane_num, bpp);
495 if (pix_clock <= max_pix_clock)
497 if (radeon_connector_is_dp12_capable(connector)) {
498 max_pix_clock = dp_get_max_dp_pix_clock(540000, lane_num, bpp);
499 if (pix_clock <= max_pix_clock)
503 return dp_get_max_link_rate(dpcd);
506 static u8 radeon_dp_encoder_service(struct radeon_device *rdev,
507 int action, int dp_clock,
508 u8 ucconfig, u8 lane_num)
510 DP_ENCODER_SERVICE_PARAMETERS args;
511 int index = GetIndexIntoMasterTable(COMMAND, DPEncoderService);
513 memset(&args, 0, sizeof(args));
514 args.ucLinkClock = dp_clock / 10;
515 args.ucConfig = ucconfig;
516 args.ucAction = action;
517 args.ucLaneNum = lane_num;
520 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
521 return args.ucStatus;
524 u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector)
526 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
527 struct drm_device *dev = radeon_connector->base.dev;
528 struct radeon_device *rdev = dev->dev_private;
530 return radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_GET_SINK_TYPE, 0,
531 dig_connector->dp_i2c_bus->rec.i2c_id, 0);
534 static void radeon_dp_probe_oui(struct radeon_connector *radeon_connector)
536 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
539 if (!(dig_connector->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
542 if (radeon_dp_aux_native_read(radeon_connector, DP_SINK_OUI, buf, 3, 0))
543 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
544 buf[0], buf[1], buf[2]);
546 if (radeon_dp_aux_native_read(radeon_connector, DP_BRANCH_OUI, buf, 3, 0))
547 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
548 buf[0], buf[1], buf[2]);
551 bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector)
553 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
557 ret = radeon_dp_aux_native_read(radeon_connector, DP_DPCD_REV, msg, 8, 0);
559 memcpy(dig_connector->dpcd, msg, 8);
560 DRM_DEBUG_KMS("DPCD: ");
561 for (i = 0; i < 8; i++)
562 DRM_DEBUG_KMS("%02x ", msg[i]);
565 radeon_dp_probe_oui(radeon_connector);
569 dig_connector->dpcd[0] = 0;
573 int radeon_dp_get_panel_mode(struct drm_encoder *encoder,
574 struct drm_connector *connector)
576 struct drm_device *dev = encoder->dev;
577 struct radeon_device *rdev = dev->dev_private;
578 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
579 int panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
580 u16 dp_bridge = radeon_connector_encoder_get_dp_bridge_encoder_id(connector);
583 if (!ASIC_IS_DCE4(rdev))
586 if (dp_bridge != ENCODER_OBJECT_ID_NONE) {
587 /* DP bridge chips */
588 tmp = radeon_read_dpcd_reg(radeon_connector, DP_EDP_CONFIGURATION_CAP);
590 panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE;
591 else if ((dp_bridge == ENCODER_OBJECT_ID_NUTMEG) ||
592 (dp_bridge == ENCODER_OBJECT_ID_TRAVIS))
593 panel_mode = DP_PANEL_MODE_INTERNAL_DP1_MODE;
595 panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
596 } else if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
598 tmp = radeon_read_dpcd_reg(radeon_connector, DP_EDP_CONFIGURATION_CAP);
600 panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE;
606 void radeon_dp_set_link_config(struct drm_connector *connector,
607 const struct drm_display_mode *mode)
609 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
610 struct radeon_connector_atom_dig *dig_connector;
612 if (!radeon_connector->con_priv)
614 dig_connector = radeon_connector->con_priv;
616 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
617 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) {
618 dig_connector->dp_clock =
619 radeon_dp_get_dp_link_clock(connector, dig_connector->dpcd, mode->clock);
620 dig_connector->dp_lane_count =
621 radeon_dp_get_dp_lane_number(connector, dig_connector->dpcd, mode->clock);
625 int radeon_dp_mode_valid_helper(struct drm_connector *connector,
626 struct drm_display_mode *mode)
628 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
629 struct radeon_connector_atom_dig *dig_connector;
632 if (!radeon_connector->con_priv)
633 return MODE_CLOCK_HIGH;
634 dig_connector = radeon_connector->con_priv;
637 radeon_dp_get_dp_link_clock(connector, dig_connector->dpcd, mode->clock);
639 if ((dp_clock == 540000) &&
640 (!radeon_connector_is_dp12_capable(connector)))
641 return MODE_CLOCK_HIGH;
646 static bool radeon_dp_get_link_status(struct radeon_connector *radeon_connector,
647 u8 link_status[DP_LINK_STATUS_SIZE])
650 ret = radeon_dp_aux_native_read(radeon_connector, DP_LANE0_1_STATUS,
651 link_status, DP_LINK_STATUS_SIZE, 100);
656 DRM_DEBUG_KMS("link status %*ph\n", 6, link_status);
660 bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector)
662 u8 link_status[DP_LINK_STATUS_SIZE];
663 struct radeon_connector_atom_dig *dig = radeon_connector->con_priv;
665 if (!radeon_dp_get_link_status(radeon_connector, link_status))
667 if (dp_channel_eq_ok(link_status, dig->dp_lane_count))
672 struct radeon_dp_link_train_info {
673 struct radeon_device *rdev;
674 struct drm_encoder *encoder;
675 struct drm_connector *connector;
676 struct radeon_connector *radeon_connector;
684 u8 link_status[DP_LINK_STATUS_SIZE];
689 static void radeon_dp_update_vs_emph(struct radeon_dp_link_train_info *dp_info)
691 /* set the initial vs/emph on the source */
692 atombios_dig_transmitter_setup(dp_info->encoder,
693 ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH,
694 0, dp_info->train_set[0]); /* sets all lanes at once */
696 /* set the vs/emph on the sink */
697 radeon_dp_aux_native_write(dp_info->radeon_connector, DP_TRAINING_LANE0_SET,
698 dp_info->train_set, dp_info->dp_lane_count, 0);
701 static void radeon_dp_set_tp(struct radeon_dp_link_train_info *dp_info, int tp)
705 /* set training pattern on the source */
706 if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder) {
708 case DP_TRAINING_PATTERN_1:
709 rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1;
711 case DP_TRAINING_PATTERN_2:
712 rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2;
714 case DP_TRAINING_PATTERN_3:
715 rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3;
718 atombios_dig_encoder_setup(dp_info->encoder, rtp, 0);
721 case DP_TRAINING_PATTERN_1:
724 case DP_TRAINING_PATTERN_2:
728 radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_PATTERN_SEL,
729 dp_info->dp_clock, dp_info->enc_id, rtp);
732 /* enable training pattern on the sink */
733 radeon_write_dpcd_reg(dp_info->radeon_connector, DP_TRAINING_PATTERN_SET, tp);
736 static int radeon_dp_link_train_init(struct radeon_dp_link_train_info *dp_info)
738 struct radeon_encoder *radeon_encoder = to_radeon_encoder(dp_info->encoder);
739 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
742 /* power up the sink */
743 if (dp_info->dpcd[0] >= 0x11)
744 radeon_write_dpcd_reg(dp_info->radeon_connector,
745 DP_SET_POWER, DP_SET_POWER_D0);
747 /* possibly enable downspread on the sink */
748 if (dp_info->dpcd[3] & 0x1)
749 radeon_write_dpcd_reg(dp_info->radeon_connector,
750 DP_DOWNSPREAD_CTRL, DP_SPREAD_AMP_0_5);
752 radeon_write_dpcd_reg(dp_info->radeon_connector,
753 DP_DOWNSPREAD_CTRL, 0);
755 if ((dp_info->connector->connector_type == DRM_MODE_CONNECTOR_eDP) &&
756 (dig->panel_mode == DP_PANEL_MODE_INTERNAL_DP2_MODE)) {
757 radeon_write_dpcd_reg(dp_info->radeon_connector, DP_EDP_CONFIGURATION_SET, 1);
760 /* set the lane count on the sink */
761 tmp = dp_info->dp_lane_count;
762 if (dp_info->dpcd[DP_DPCD_REV] >= 0x11 &&
763 dp_info->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)
764 tmp |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
765 radeon_write_dpcd_reg(dp_info->radeon_connector, DP_LANE_COUNT_SET, tmp);
767 /* set the link rate on the sink */
768 tmp = dp_get_dp_link_rate_coded(dp_info->dp_clock);
769 radeon_write_dpcd_reg(dp_info->radeon_connector, DP_LINK_BW_SET, tmp);
771 /* start training on the source */
772 if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder)
773 atombios_dig_encoder_setup(dp_info->encoder,
774 ATOM_ENCODER_CMD_DP_LINK_TRAINING_START, 0);
776 radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_START,
777 dp_info->dp_clock, dp_info->enc_id, 0);
779 /* disable the training pattern on the sink */
780 radeon_write_dpcd_reg(dp_info->radeon_connector,
781 DP_TRAINING_PATTERN_SET,
782 DP_TRAINING_PATTERN_DISABLE);
787 static int radeon_dp_link_train_finish(struct radeon_dp_link_train_info *dp_info)
791 /* disable the training pattern on the sink */
792 radeon_write_dpcd_reg(dp_info->radeon_connector,
793 DP_TRAINING_PATTERN_SET,
794 DP_TRAINING_PATTERN_DISABLE);
796 /* disable the training pattern on the source */
797 if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder)
798 atombios_dig_encoder_setup(dp_info->encoder,
799 ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE, 0);
801 radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_COMPLETE,
802 dp_info->dp_clock, dp_info->enc_id, 0);
807 static int radeon_dp_link_train_cr(struct radeon_dp_link_train_info *dp_info)
813 radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_1);
814 memset(dp_info->train_set, 0, 4);
815 radeon_dp_update_vs_emph(dp_info);
819 /* clock recovery loop */
820 clock_recovery = false;
824 if (dp_info->rd_interval == 0)
827 mdelay(dp_info->rd_interval * 4);
829 if (!radeon_dp_get_link_status(dp_info->radeon_connector, dp_info->link_status)) {
830 DRM_ERROR("displayport link status failed\n");
834 if (dp_clock_recovery_ok(dp_info->link_status, dp_info->dp_lane_count)) {
835 clock_recovery = true;
839 for (i = 0; i < dp_info->dp_lane_count; i++) {
840 if ((dp_info->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
843 if (i == dp_info->dp_lane_count) {
844 DRM_ERROR("clock recovery reached max voltage\n");
848 if ((dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
850 if (dp_info->tries == 5) {
851 DRM_ERROR("clock recovery tried 5 times\n");
857 voltage = dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
859 /* Compute new train_set as requested by sink */
860 dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, dp_info->train_set);
862 radeon_dp_update_vs_emph(dp_info);
864 if (!clock_recovery) {
865 DRM_ERROR("clock recovery failed\n");
868 DRM_DEBUG_KMS("clock recovery at voltage %d pre-emphasis %d\n",
869 dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,
870 (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) >>
871 DP_TRAIN_PRE_EMPHASIS_SHIFT);
876 static int radeon_dp_link_train_ce(struct radeon_dp_link_train_info *dp_info)
880 if (dp_info->tp3_supported)
881 radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_3);
883 radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_2);
885 /* channel equalization loop */
889 if (dp_info->rd_interval == 0)
892 mdelay(dp_info->rd_interval * 4);
894 if (!radeon_dp_get_link_status(dp_info->radeon_connector, dp_info->link_status)) {
895 DRM_ERROR("displayport link status failed\n");
899 if (dp_channel_eq_ok(dp_info->link_status, dp_info->dp_lane_count)) {
905 if (dp_info->tries > 5) {
906 DRM_ERROR("channel eq failed: 5 tries\n");
910 /* Compute new train_set as requested by sink */
911 dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, dp_info->train_set);
913 radeon_dp_update_vs_emph(dp_info);
918 DRM_ERROR("channel eq failed\n");
921 DRM_DEBUG_KMS("channel eq at voltage %d pre-emphasis %d\n",
922 dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,
923 (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK)
924 >> DP_TRAIN_PRE_EMPHASIS_SHIFT);
929 void radeon_dp_link_train(struct drm_encoder *encoder,
930 struct drm_connector *connector)
932 struct drm_device *dev = encoder->dev;
933 struct radeon_device *rdev = dev->dev_private;
934 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
935 struct radeon_encoder_atom_dig *dig;
936 struct radeon_connector *radeon_connector;
937 struct radeon_connector_atom_dig *dig_connector;
938 struct radeon_dp_link_train_info dp_info;
942 if (!radeon_encoder->enc_priv)
944 dig = radeon_encoder->enc_priv;
946 radeon_connector = to_radeon_connector(connector);
947 if (!radeon_connector->con_priv)
949 dig_connector = radeon_connector->con_priv;
951 if ((dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_DISPLAYPORT) &&
952 (dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_eDP))
955 /* DPEncoderService newer than 1.1 can't program properly the
956 * training pattern. When facing such version use the
957 * DIGXEncoderControl (X== 1 | 2)
959 dp_info.use_dpencoder = true;
960 index = GetIndexIntoMasterTable(COMMAND, DPEncoderService);
961 if (atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) {
963 dp_info.use_dpencoder = false;
968 if (dig->dig_encoder)
969 dp_info.enc_id |= ATOM_DP_CONFIG_DIG2_ENCODER;
971 dp_info.enc_id |= ATOM_DP_CONFIG_DIG1_ENCODER;
973 dp_info.enc_id |= ATOM_DP_CONFIG_LINK_B;
975 dp_info.enc_id |= ATOM_DP_CONFIG_LINK_A;
977 dp_info.rd_interval = radeon_read_dpcd_reg(radeon_connector, DP_TRAINING_AUX_RD_INTERVAL);
978 tmp = radeon_read_dpcd_reg(radeon_connector, DP_MAX_LANE_COUNT);
979 if (ASIC_IS_DCE5(rdev) && (tmp & DP_TPS3_SUPPORTED))
980 dp_info.tp3_supported = true;
982 dp_info.tp3_supported = false;
984 memcpy(dp_info.dpcd, dig_connector->dpcd, 8);
986 dp_info.encoder = encoder;
987 dp_info.connector = connector;
988 dp_info.radeon_connector = radeon_connector;
989 dp_info.dp_lane_count = dig_connector->dp_lane_count;
990 dp_info.dp_clock = dig_connector->dp_clock;
992 if (radeon_dp_link_train_init(&dp_info))
994 if (radeon_dp_link_train_cr(&dp_info))
996 if (radeon_dp_link_train_ce(&dp_info))
999 if (radeon_dp_link_train_finish(&dp_info))