drivers/gpu/drm/radeon/atombios_crtc.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include <drm/drmP.h>
  27 #include <drm/drm_crtc_helper.h>
  28 #include <drm/radeon_drm.h>
  29 #include <drm/drm_fixed.h>
  30 #include "radeon.h"
  31 #include "atom.h"
  32 #include "atom-bits.h"
  33
  34 static void atombios_overscan_setup(struct drm_crtc *crtc,
  35                                     struct drm_display_mode *mode,
  36                                     struct drm_display_mode *adjusted_mode)
  37 {
  38         struct drm_device *dev = crtc->dev;
  39         struct radeon_device *rdev = dev->dev_private;
  40         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
  41         SET_CRTC_OVERSCAN_PS_ALLOCATION args;
  42         int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_OverScan);
  43         int a1, a2;
  44
  45         memset(&args, 0, sizeof(args));
  46
  47         args.ucCRTC = radeon_crtc->crtc_id;
  48
  49         switch (radeon_crtc->rmx_type) {
  50         case RMX_CENTER:
  51                 args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2);
  52                 args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2);
  53                 args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2);
  54                 args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2);
  55                 break;
  56         case RMX_ASPECT:
  57                 a1 = mode->crtc_vdisplay * adjusted_mode->crtc_hdisplay;
  58                 a2 = adjusted_mode->crtc_vdisplay * mode->crtc_hdisplay;
  59
  60                 if (a1 > a2) {
  61                         args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2);
  62                         args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2);
  63                 } else if (a2 > a1) {
  64                         args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2);
  65                         args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2);
  66                 }
  67                 break;
  68         case RMX_FULL:
  69         default:
  70                 args.usOverscanRight = cpu_to_le16(radeon_crtc->h_border);
  71                 args.usOverscanLeft = cpu_to_le16(radeon_crtc->h_border);
  72                 args.usOverscanBottom = cpu_to_le16(radeon_crtc->v_border);
  73                 args.usOverscanTop = cpu_to_le16(radeon_crtc->v_border);
  74                 break;
  75         }
  76         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
  77 }
  78
  79 static void atombios_scaler_setup(struct drm_crtc *crtc)
  80 {
  81         struct drm_device *dev = crtc->dev;
  82         struct radeon_device *rdev = dev->dev_private;
  83         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
  84         ENABLE_SCALER_PS_ALLOCATION args;
  85         int index = GetIndexIntoMasterTable(COMMAND, EnableScaler);
  86         struct radeon_encoder *radeon_encoder =
  87                 to_radeon_encoder(radeon_crtc->encoder);
  88         /* fixme - fill in enc_priv for atom dac */
  89         enum radeon_tv_std tv_std = TV_STD_NTSC;
  90         bool is_tv = false, is_cv = false;
  91
  92         if (!ASIC_IS_AVIVO(rdev) && radeon_crtc->crtc_id)
  93                 return;
  94
  95         if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) {
  96                 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
  97                 tv_std = tv_dac->tv_std;
  98                 is_tv = true;
  99         }
 100
 101         memset(&args, 0, sizeof(args));
 102
 103         args.ucScaler = radeon_crtc->crtc_id;
 104
 105         if (is_tv) {
 106                 switch (tv_std) {
 107                 case TV_STD_NTSC:
 108                 default:
 109                         args.ucTVStandard = ATOM_TV_NTSC;
 110                         break;
 111                 case TV_STD_PAL:
 112                         args.ucTVStandard = ATOM_TV_PAL;
 113                         break;
 114                 case TV_STD_PAL_M:
 115                         args.ucTVStandard = ATOM_TV_PALM;
 116                         break;
 117                 case TV_STD_PAL_60:
 118                         args.ucTVStandard = ATOM_TV_PAL60;
 119                         break;
 120                 case TV_STD_NTSC_J:
 121                         args.ucTVStandard = ATOM_TV_NTSCJ;
 122                         break;
 123                 case TV_STD_SCART_PAL:
 124                         args.ucTVStandard = ATOM_TV_PAL; /* ??? */
 125                         break;
 126                 case TV_STD_SECAM:
 127                         args.ucTVStandard = ATOM_TV_SECAM;
 128                         break;
 129                 case TV_STD_PAL_CN:
 130                         args.ucTVStandard = ATOM_TV_PALCN;
 131                         break;
 132                 }
 133                 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE;
 134         } else if (is_cv) {
 135                 args.ucTVStandard = ATOM_TV_CV;
 136                 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE;
 137         } else {
 138                 switch (radeon_crtc->rmx_type) {
 139                 case RMX_FULL:
 140                         args.ucEnable = ATOM_SCALER_EXPANSION;
 141                         break;
 142                 case RMX_CENTER:
 143                         args.ucEnable = ATOM_SCALER_CENTER;
 144                         break;
 145                 case RMX_ASPECT:
 146                         args.ucEnable = ATOM_SCALER_EXPANSION;
 147                         break;
 148                 default:
 149                         if (ASIC_IS_AVIVO(rdev))
 150                                 args.ucEnable = ATOM_SCALER_DISABLE;
 151                         else
 152                                 args.ucEnable = ATOM_SCALER_CENTER;
 153                         break;
 154                 }
 155         }
 156         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 157         if ((is_tv || is_cv)
 158             && rdev->family >= CHIP_RV515 && rdev->family <= CHIP_R580) {
 159                 atom_rv515_force_tv_scaler(rdev, radeon_crtc);
 160         }
 161 }
 162
 163 static void atombios_lock_crtc(struct drm_crtc *crtc, int lock)
 164 {
 165         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 166         struct drm_device *dev = crtc->dev;
 167         struct radeon_device *rdev = dev->dev_private;
 168         int index =
 169             GetIndexIntoMasterTable(COMMAND, UpdateCRTC_DoubleBufferRegisters);
 170         ENABLE_CRTC_PS_ALLOCATION args;
 171
 172         memset(&args, 0, sizeof(args));
 173
 174         args.ucCRTC = radeon_crtc->crtc_id;
 175         args.ucEnable = lock;
 176
 177         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 178 }
 179
 180 static void atombios_enable_crtc(struct drm_crtc *crtc, int state)
 181 {
 182         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 183         struct drm_device *dev = crtc->dev;
 184         struct radeon_device *rdev = dev->dev_private;
 185         int index = GetIndexIntoMasterTable(COMMAND, EnableCRTC);
 186         ENABLE_CRTC_PS_ALLOCATION args;
 187
 188         memset(&args, 0, sizeof(args));
 189
 190         args.ucCRTC = radeon_crtc->crtc_id;
 191         args.ucEnable = state;
 192
 193         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 194 }
 195
 196 static void atombios_enable_crtc_memreq(struct drm_crtc *crtc, int state)
 197 {
 198         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 199         struct drm_device *dev = crtc->dev;
 200         struct radeon_device *rdev = dev->dev_private;
 201         int index = GetIndexIntoMasterTable(COMMAND, EnableCRTCMemReq);
 202         ENABLE_CRTC_PS_ALLOCATION args;
 203
 204         memset(&args, 0, sizeof(args));
 205
 206         args.ucCRTC = radeon_crtc->crtc_id;
 207         args.ucEnable = state;
 208
 209         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 210 }
 211
 212 static void atombios_blank_crtc(struct drm_crtc *crtc, int state)
 213 {
 214         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 215         struct drm_device *dev = crtc->dev;
 216         struct radeon_device *rdev = dev->dev_private;
 217         int index = GetIndexIntoMasterTable(COMMAND, BlankCRTC);
 218         BLANK_CRTC_PS_ALLOCATION args;
 219
 220         memset(&args, 0, sizeof(args));
 221
 222         args.ucCRTC = radeon_crtc->crtc_id;
 223         args.ucBlanking = state;
 224
 225         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 226 }
 227
 228 static void atombios_powergate_crtc(struct drm_crtc *crtc, int state)
 229 {
 230         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 231         struct drm_device *dev = crtc->dev;
 232         struct radeon_device *rdev = dev->dev_private;
 233         int index = GetIndexIntoMasterTable(COMMAND, EnableDispPowerGating);
 234         ENABLE_DISP_POWER_GATING_PARAMETERS_V2_1 args;
 235
 236         memset(&args, 0, sizeof(args));
 237
 238         args.ucDispPipeId = radeon_crtc->crtc_id;
 239         args.ucEnable = state;
 240
 241         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 242 }
 243
 244 void atombios_crtc_dpms(struct drm_crtc *crtc, int mode)
 245 {
 246         struct drm_device *dev = crtc->dev;
 247         struct radeon_device *rdev = dev->dev_private;
 248         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 249
 250         switch (mode) {
 251         case DRM_MODE_DPMS_ON:
 252                 radeon_crtc->enabled = true;
 253                 /* adjust pm to dpms changes BEFORE enabling crtcs */
 254                 radeon_pm_compute_clocks(rdev);
 255                 if (ASIC_IS_DCE6(rdev) && !radeon_crtc->in_mode_set)
 256                         atombios_powergate_crtc(crtc, ATOM_DISABLE);
 257                 atombios_enable_crtc(crtc, ATOM_ENABLE);
 258                 if (ASIC_IS_DCE3(rdev) && !ASIC_IS_DCE6(rdev))
 259                         atombios_enable_crtc_memreq(crtc, ATOM_ENABLE);
 260                 atombios_blank_crtc(crtc, ATOM_DISABLE);
 261                 drm_vblank_post_modeset(dev, radeon_crtc->crtc_id);
 262                 radeon_crtc_load_lut(crtc);
 263                 break;
 264         case DRM_MODE_DPMS_STANDBY:
 265         case DRM_MODE_DPMS_SUSPEND:
 266         case DRM_MODE_DPMS_OFF:
 267                 drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id);
 268                 if (radeon_crtc->enabled)
 269                         atombios_blank_crtc(crtc, ATOM_ENABLE);
 270                 if (ASIC_IS_DCE3(rdev) && !ASIC_IS_DCE6(rdev))
 271                         atombios_enable_crtc_memreq(crtc, ATOM_DISABLE);
 272                 atombios_enable_crtc(crtc, ATOM_DISABLE);
 273                 radeon_crtc->enabled = false;
 274                 if (ASIC_IS_DCE6(rdev) && !radeon_crtc->in_mode_set)
 275                         atombios_powergate_crtc(crtc, ATOM_ENABLE);
 276                 /* adjust pm to dpms changes AFTER disabling crtcs */
 277                 radeon_pm_compute_clocks(rdev);
 278                 break;
 279         }
 280 }
 281
 282 static void
 283 atombios_set_crtc_dtd_timing(struct drm_crtc *crtc,
 284                              struct drm_display_mode *mode)
 285 {
 286         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 287         struct drm_device *dev = crtc->dev;
 288         struct radeon_device *rdev = dev->dev_private;
 289         SET_CRTC_USING_DTD_TIMING_PARAMETERS args;
 290         int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_UsingDTDTiming);
 291         u16 misc = 0;
 292
 293         memset(&args, 0, sizeof(args));
 294         args.usH_Size = cpu_to_le16(mode->crtc_hdisplay - (radeon_crtc->h_border * 2));
 295         args.usH_Blanking_Time =
 296                 cpu_to_le16(mode->crtc_hblank_end - mode->crtc_hdisplay + (radeon_crtc->h_border * 2));
 297         args.usV_Size = cpu_to_le16(mode->crtc_vdisplay - (radeon_crtc->v_border * 2));
 298         args.usV_Blanking_Time =
 299                 cpu_to_le16(mode->crtc_vblank_end - mode->crtc_vdisplay + (radeon_crtc->v_border * 2));
 300         args.usH_SyncOffset =
 301                 cpu_to_le16(mode->crtc_hsync_start - mode->crtc_hdisplay + radeon_crtc->h_border);
 302         args.usH_SyncWidth =
 303                 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start);
 304         args.usV_SyncOffset =
 305                 cpu_to_le16(mode->crtc_vsync_start - mode->crtc_vdisplay + radeon_crtc->v_border);
 306         args.usV_SyncWidth =
 307                 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start);
 308         args.ucH_Border = radeon_crtc->h_border;
 309         args.ucV_Border = radeon_crtc->v_border;
 310
 311         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
 312                 misc |= ATOM_VSYNC_POLARITY;
 313         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
 314                 misc |= ATOM_HSYNC_POLARITY;
 315         if (mode->flags & DRM_MODE_FLAG_CSYNC)
 316                 misc |= ATOM_COMPOSITESYNC;
 317         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
 318                 misc |= ATOM_INTERLACE;
 319         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
 320                 misc |= ATOM_DOUBLE_CLOCK_MODE;
 321
 322         args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
 323         args.ucCRTC = radeon_crtc->crtc_id;
 324
 325         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 326 }
 327
 328 static void atombios_crtc_set_timing(struct drm_crtc *crtc,
 329                                      struct drm_display_mode *mode)
 330 {
 331         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 332         struct drm_device *dev = crtc->dev;
 333         struct radeon_device *rdev = dev->dev_private;
 334         SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION args;
 335         int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_Timing);
 336         u16 misc = 0;
 337
 338         memset(&args, 0, sizeof(args));
 339         args.usH_Total = cpu_to_le16(mode->crtc_htotal);
 340         args.usH_Disp = cpu_to_le16(mode->crtc_hdisplay);
 341         args.usH_SyncStart = cpu_to_le16(mode->crtc_hsync_start);
 342         args.usH_SyncWidth =
 343                 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start);
 344         args.usV_Total = cpu_to_le16(mode->crtc_vtotal);
 345         args.usV_Disp = cpu_to_le16(mode->crtc_vdisplay);
 346         args.usV_SyncStart = cpu_to_le16(mode->crtc_vsync_start);
 347         args.usV_SyncWidth =
 348                 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start);
 349
 350         args.ucOverscanRight = radeon_crtc->h_border;
 351         args.ucOverscanLeft = radeon_crtc->h_border;
 352         args.ucOverscanBottom = radeon_crtc->v_border;
 353         args.ucOverscanTop = radeon_crtc->v_border;
 354
 355         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
 356                 misc |= ATOM_VSYNC_POLARITY;
 357         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
 358                 misc |= ATOM_HSYNC_POLARITY;
 359         if (mode->flags & DRM_MODE_FLAG_CSYNC)
 360                 misc |= ATOM_COMPOSITESYNC;
 361         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
 362                 misc |= ATOM_INTERLACE;
 363         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
 364                 misc |= ATOM_DOUBLE_CLOCK_MODE;
 365
 366         args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
 367         args.ucCRTC = radeon_crtc->crtc_id;
 368
 369         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 370 }
 371
 372 static void atombios_disable_ss(struct radeon_device *rdev, int pll_id)
 373 {
 374         u32 ss_cntl;
 375
 376         if (ASIC_IS_DCE4(rdev)) {
 377                 switch (pll_id) {
 378                 case ATOM_PPLL1:
 379                         ss_cntl = RREG32(EVERGREEN_P1PLL_SS_CNTL);
 380                         ss_cntl &= ~EVERGREEN_PxPLL_SS_EN;
 381                         WREG32(EVERGREEN_P1PLL_SS_CNTL, ss_cntl);
 382                         break;
 383                 case ATOM_PPLL2:
 384                         ss_cntl = RREG32(EVERGREEN_P2PLL_SS_CNTL);
 385                         ss_cntl &= ~EVERGREEN_PxPLL_SS_EN;
 386                         WREG32(EVERGREEN_P2PLL_SS_CNTL, ss_cntl);
 387                         break;
 388                 case ATOM_DCPLL:
 389                 case ATOM_PPLL_INVALID:
 390                         return;
 391                 }
 392         } else if (ASIC_IS_AVIVO(rdev)) {
 393                 switch (pll_id) {
 394                 case ATOM_PPLL1:
 395                         ss_cntl = RREG32(AVIVO_P1PLL_INT_SS_CNTL);
 396                         ss_cntl &= ~1;
 397                         WREG32(AVIVO_P1PLL_INT_SS_CNTL, ss_cntl);
 398                         break;
 399                 case ATOM_PPLL2:
 400                         ss_cntl = RREG32(AVIVO_P2PLL_INT_SS_CNTL);
 401                         ss_cntl &= ~1;
 402                         WREG32(AVIVO_P2PLL_INT_SS_CNTL, ss_cntl);
 403                         break;
 404                 case ATOM_DCPLL:
 405                 case ATOM_PPLL_INVALID:
 406                         return;
 407                 }
 408         }
 409 }
 410
 411
 412 union atom_enable_ss {
 413         ENABLE_LVDS_SS_PARAMETERS lvds_ss;
 414         ENABLE_LVDS_SS_PARAMETERS_V2 lvds_ss_2;
 415         ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION v1;
 416         ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2 v2;
 417         ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3 v3;
 418 };
 419
 420 static void atombios_crtc_program_ss(struct radeon_device *rdev,
 421                                      int enable,
 422                                      int pll_id,
 423                                      int crtc_id,
 424                                      struct radeon_atom_ss *ss)
 425 {
 426         unsigned i;
 427         int index = GetIndexIntoMasterTable(COMMAND, EnableSpreadSpectrumOnPPLL);
 428         union atom_enable_ss args;
 429
 430         if (!enable) {
 431                 for (i = 0; i < rdev->num_crtc; i++) {
 432                         if (rdev->mode_info.crtcs[i] &&
 433                             rdev->mode_info.crtcs[i]->enabled &&
 434                             i != crtc_id &&
 435                             pll_id == rdev->mode_info.crtcs[i]->pll_id) {
 436                                 /* one other crtc is using this pll don't turn
 437                                  * off spread spectrum as it might turn off
 438                                  * display on active crtc
 439                                  */
 440                                 return;
 441                         }
 442                 }
 443         }
 444
 445         memset(&args, 0, sizeof(args));
 446
 447         if (ASIC_IS_DCE5(rdev)) {
 448                 args.v3.usSpreadSpectrumAmountFrac = cpu_to_le16(0);
 449                 args.v3.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
 450                 switch (pll_id) {
 451                 case ATOM_PPLL1:
 452                         args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P1PLL;
 453                         break;
 454                 case ATOM_PPLL2:
 455                         args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P2PLL;
 456                         break;
 457                 case ATOM_DCPLL:
 458                         args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_DCPLL;
 459                         break;
 460                 case ATOM_PPLL_INVALID:
 461                         return;
 462                 }
 463                 args.v3.usSpreadSpectrumAmount = cpu_to_le16(ss->amount);
 464                 args.v3.usSpreadSpectrumStep = cpu_to_le16(ss->step);
 465                 args.v3.ucEnable = enable;
 466                 if ((ss->percentage == 0) || (ss->type & ATOM_EXTERNAL_SS_MASK) || ASIC_IS_DCE61(rdev))
 467                         args.v3.ucEnable = ATOM_DISABLE;
 468         } else if (ASIC_IS_DCE4(rdev)) {
 469                 args.v2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
 470                 args.v2.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
 471                 switch (pll_id) {
 472                 case ATOM_PPLL1:
 473                         args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_P1PLL;
 474                         break;
 475                 case ATOM_PPLL2:
 476                         args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_P2PLL;
 477                         break;
 478                 case ATOM_DCPLL:
 479                         args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_DCPLL;
 480                         break;
 481                 case ATOM_PPLL_INVALID:
 482                         return;
 483                 }
 484                 args.v2.usSpreadSpectrumAmount = cpu_to_le16(ss->amount);
 485                 args.v2.usSpreadSpectrumStep = cpu_to_le16(ss->step);
 486                 args.v2.ucEnable = enable;
 487                 if ((ss->percentage == 0) || (ss->type & ATOM_EXTERNAL_SS_MASK) || ASIC_IS_DCE41(rdev))
 488                         args.v2.ucEnable = ATOM_DISABLE;
 489         } else if (ASIC_IS_DCE3(rdev)) {
 490                 args.v1.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
 491                 args.v1.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
 492                 args.v1.ucSpreadSpectrumStep = ss->step;
 493                 args.v1.ucSpreadSpectrumDelay = ss->delay;
 494                 args.v1.ucSpreadSpectrumRange = ss->range;
 495                 args.v1.ucPpll = pll_id;
 496                 args.v1.ucEnable = enable;
 497         } else if (ASIC_IS_AVIVO(rdev)) {
 498                 if ((enable == ATOM_DISABLE) || (ss->percentage == 0) ||
 499                     (ss->type & ATOM_EXTERNAL_SS_MASK)) {
 500                         atombios_disable_ss(rdev, pll_id);
 501                         return;
 502                 }
 503                 args.lvds_ss_2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
 504                 args.lvds_ss_2.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
 505                 args.lvds_ss_2.ucSpreadSpectrumStep = ss->step;
 506                 args.lvds_ss_2.ucSpreadSpectrumDelay = ss->delay;
 507                 args.lvds_ss_2.ucSpreadSpectrumRange = ss->range;
 508                 args.lvds_ss_2.ucEnable = enable;
 509         } else {
 510                 if ((enable == ATOM_DISABLE) || (ss->percentage == 0) ||
 511                     (ss->type & ATOM_EXTERNAL_SS_MASK)) {
 512                         atombios_disable_ss(rdev, pll_id);
 513                         return;
 514                 }
 515                 args.lvds_ss.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
 516                 args.lvds_ss.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
 517                 args.lvds_ss.ucSpreadSpectrumStepSize_Delay = (ss->step & 3) << 2;
 518                 args.lvds_ss.ucSpreadSpectrumStepSize_Delay |= (ss->delay & 7) << 4;
 519                 args.lvds_ss.ucEnable = enable;
 520         }
 521         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 522 }
 523
 524 union adjust_pixel_clock {
 525         ADJUST_DISPLAY_PLL_PS_ALLOCATION v1;
 526         ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3 v3;
 527 };
 528
 529 static u32 atombios_adjust_pll(struct drm_crtc *crtc,
 530                                struct drm_display_mode *mode)
 531 {
 532         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 533         struct drm_device *dev = crtc->dev;
 534         struct radeon_device *rdev = dev->dev_private;
 535         struct drm_encoder *encoder = radeon_crtc->encoder;
 536         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 537         struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
 538         u32 adjusted_clock = mode->clock;
 539         int encoder_mode = atombios_get_encoder_mode(encoder);
 540         u32 dp_clock = mode->clock;
 541         int bpc = radeon_get_monitor_bpc(connector);
 542         bool is_duallink = radeon_dig_monitor_is_duallink(encoder, mode->clock);
 543
 544         /* reset the pll flags */
 545         radeon_crtc->pll_flags = 0;
 546
 547         if (ASIC_IS_AVIVO(rdev)) {
 548                 if ((rdev->family == CHIP_RS600) ||
 549                     (rdev->family == CHIP_RS690) ||
 550                     (rdev->family == CHIP_RS740))
 551                         radeon_crtc->pll_flags |= (/*RADEON_PLL_USE_FRAC_FB_DIV |*/
 552                                 RADEON_PLL_PREFER_CLOSEST_LOWER);
 553
 554                 if (ASIC_IS_DCE32(rdev) && mode->clock > 200000)        /* range limits??? */
 555                         radeon_crtc->pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
 556                 else
 557                         radeon_crtc->pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
 558
 559                 if (rdev->family < CHIP_RV770)
 560                         radeon_crtc->pll_flags |= RADEON_PLL_PREFER_MINM_OVER_MAXP;
 561                 /* use frac fb div on APUs */
 562                 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev))
 563                         radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
 564                 if (ASIC_IS_DCE32(rdev) && mode->clock > 165000)
 565                         radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
 566         } else {
 567                 radeon_crtc->pll_flags |= RADEON_PLL_LEGACY;
 568
 569                 if (mode->clock > 200000)       /* range limits??? */
 570                         radeon_crtc->pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
 571                 else
 572                         radeon_crtc->pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
 573         }
 574
 575         if ((radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) ||
 576             (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)) {
 577                 if (connector) {
 578                         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 579                         struct radeon_connector_atom_dig *dig_connector =
 580                                 radeon_connector->con_priv;
 581
 582                         dp_clock = dig_connector->dp_clock;
 583                 }
 584         }
 585
 586         /* use recommended ref_div for ss */
 587         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
 588                 if (radeon_crtc->ss_enabled) {
 589                         if (radeon_crtc->ss.refdiv) {
 590                                 radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV;
 591                                 radeon_crtc->pll_reference_div = radeon_crtc->ss.refdiv;
 592                                 if (ASIC_IS_AVIVO(rdev))
 593                                         radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
 594                         }
 595                 }
 596         }
 597
 598         if (ASIC_IS_AVIVO(rdev)) {
 599                 /* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */
 600                 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1)
 601                         adjusted_clock = mode->clock * 2;
 602                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
 603                         radeon_crtc->pll_flags |= RADEON_PLL_PREFER_CLOSEST_LOWER;
 604                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
 605                         radeon_crtc->pll_flags |= RADEON_PLL_IS_LCD;
 606         } else {
 607                 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC)
 608                         radeon_crtc->pll_flags |= RADEON_PLL_NO_ODD_POST_DIV;
 609                 if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS)
 610                         radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV;
 611         }
 612
 613         /* DCE3+ has an AdjustDisplayPll that will adjust the pixel clock
 614          * accordingly based on the encoder/transmitter to work around
 615          * special hw requirements.
 616          */
 617         if (ASIC_IS_DCE3(rdev)) {
 618                 union adjust_pixel_clock args;
 619                 u8 frev, crev;
 620                 int index;
 621
 622                 index = GetIndexIntoMasterTable(COMMAND, AdjustDisplayPll);
 623                 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
 624                                            &crev))
 625                         return adjusted_clock;
 626
 627                 memset(&args, 0, sizeof(args));
 628
 629                 switch (frev) {
 630                 case 1:
 631                         switch (crev) {
 632                         case 1:
 633                         case 2:
 634                                 args.v1.usPixelClock = cpu_to_le16(mode->clock / 10);
 635                                 args.v1.ucTransmitterID = radeon_encoder->encoder_id;
 636                                 args.v1.ucEncodeMode = encoder_mode;
 637                                 if (radeon_crtc->ss_enabled && radeon_crtc->ss.percentage)
 638                                         args.v1.ucConfig |=
 639                                                 ADJUST_DISPLAY_CONFIG_SS_ENABLE;
 640
 641                                 atom_execute_table(rdev->mode_info.atom_context,
 642                                                    index, (uint32_t *)&args);
 643                                 adjusted_clock = le16_to_cpu(args.v1.usPixelClock) * 10;
 644                                 break;
 645                         case 3:
 646                                 args.v3.sInput.usPixelClock = cpu_to_le16(mode->clock / 10);
 647                                 args.v3.sInput.ucTransmitterID = radeon_encoder->encoder_id;
 648                                 args.v3.sInput.ucEncodeMode = encoder_mode;
 649                                 args.v3.sInput.ucDispPllConfig = 0;
 650                                 if (radeon_crtc->ss_enabled && radeon_crtc->ss.percentage)
 651                                         args.v3.sInput.ucDispPllConfig |=
 652                                                 DISPPLL_CONFIG_SS_ENABLE;
 653                                 if (ENCODER_MODE_IS_DP(encoder_mode)) {
 654                                         args.v3.sInput.ucDispPllConfig |=
 655                                                 DISPPLL_CONFIG_COHERENT_MODE;
 656                                         /* 16200 or 27000 */
 657                                         args.v3.sInput.usPixelClock = cpu_to_le16(dp_clock / 10);
 658                                 } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
 659                                         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 660                                         if (encoder_mode == ATOM_ENCODER_MODE_HDMI)
 661                                                 /* deep color support */
 662                                                 args.v3.sInput.usPixelClock =
 663                                                         cpu_to_le16((mode->clock * bpc / 8) / 10);
 664                                         if (dig->coherent_mode)
 665                                                 args.v3.sInput.ucDispPllConfig |=
 666                                                         DISPPLL_CONFIG_COHERENT_MODE;
 667                                         if (is_duallink)
 668                                                 args.v3.sInput.ucDispPllConfig |=
 669                                                         DISPPLL_CONFIG_DUAL_LINK;
 670                                 }
 671                                 if (radeon_encoder_get_dp_bridge_encoder_id(encoder) !=
 672                                     ENCODER_OBJECT_ID_NONE)
 673                                         args.v3.sInput.ucExtTransmitterID =
 674                                                 radeon_encoder_get_dp_bridge_encoder_id(encoder);
 675                                 else
 676                                         args.v3.sInput.ucExtTransmitterID = 0;
 677
 678                                 atom_execute_table(rdev->mode_info.atom_context,
 679                                                    index, (uint32_t *)&args);
 680                                 adjusted_clock = le32_to_cpu(args.v3.sOutput.ulDispPllFreq) * 10;
 681                                 if (args.v3.sOutput.ucRefDiv) {
 682                                         radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
 683                                         radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV;
 684                                         radeon_crtc->pll_reference_div = args.v3.sOutput.ucRefDiv;
 685                                 }
 686                                 if (args.v3.sOutput.ucPostDiv) {
 687                                         radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
 688                                         radeon_crtc->pll_flags |= RADEON_PLL_USE_POST_DIV;
 689                                         radeon_crtc->pll_post_div = args.v3.sOutput.ucPostDiv;
 690                                 }
 691                                 break;
 692                         default:
 693                                 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
 694                                 return adjusted_clock;
 695                         }
 696                         break;
 697                 default:
 698                         DRM_ERROR("Unknown table version %d %d\n", frev, crev);
 699                         return adjusted_clock;
 700                 }
 701         }
 702         return adjusted_clock;
 703 }
 704
 705 union set_pixel_clock {
 706         SET_PIXEL_CLOCK_PS_ALLOCATION base;
 707         PIXEL_CLOCK_PARAMETERS v1;
 708         PIXEL_CLOCK_PARAMETERS_V2 v2;
 709         PIXEL_CLOCK_PARAMETERS_V3 v3;
 710         PIXEL_CLOCK_PARAMETERS_V5 v5;
 711         PIXEL_CLOCK_PARAMETERS_V6 v6;
 712 };
 713
 714 /* on DCE5, make sure the voltage is high enough to support the
 715  * required disp clk.
 716  */
 717 static void atombios_crtc_set_disp_eng_pll(struct radeon_device *rdev,
 718                                     u32 dispclk)
 719 {
 720         u8 frev, crev;
 721         int index;
 722         union set_pixel_clock args;
 723
 724         memset(&args, 0, sizeof(args));
 725
 726         index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
 727         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
 728                                    &crev))
 729                 return;
 730
 731         switch (frev) {
 732         case 1:
 733                 switch (crev) {
 734                 case 5:
 735                         /* if the default dcpll clock is specified,
 736                          * SetPixelClock provides the dividers
 737                          */
 738                         args.v5.ucCRTC = ATOM_CRTC_INVALID;
 739                         args.v5.usPixelClock = cpu_to_le16(dispclk);
 740                         args.v5.ucPpll = ATOM_DCPLL;
 741                         break;
 742                 case 6:
 743                         /* if the default dcpll clock is specified,
 744                          * SetPixelClock provides the dividers
 745                          */
 746                         args.v6.ulDispEngClkFreq = cpu_to_le32(dispclk);
 747                         if (ASIC_IS_DCE61(rdev))
 748                                 args.v6.ucPpll = ATOM_EXT_PLL1;
 749                         else if (ASIC_IS_DCE6(rdev))
 750                                 args.v6.ucPpll = ATOM_PPLL0;
 751                         else
 752                                 args.v6.ucPpll = ATOM_DCPLL;
 753                         break;
 754                 default:
 755                         DRM_ERROR("Unknown table version %d %d\n", frev, crev);
 756                         return;
 757                 }
 758                 break;
 759         default:
 760                 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
 761                 return;
 762         }
 763         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 764 }
 765
 766 static void atombios_crtc_program_pll(struct drm_crtc *crtc,
 767                                       u32 crtc_id,
 768                                       int pll_id,
 769                                       u32 encoder_mode,
 770                                       u32 encoder_id,
 771                                       u32 clock,
 772                                       u32 ref_div,
 773                                       u32 fb_div,
 774                                       u32 frac_fb_div,
 775                                       u32 post_div,
 776                                       int bpc,
 777                                       bool ss_enabled,
 778                                       struct radeon_atom_ss *ss)
 779 {
 780         struct drm_device *dev = crtc->dev;
 781         struct radeon_device *rdev = dev->dev_private;
 782         u8 frev, crev;
 783         int index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
 784         union set_pixel_clock args;
 785
 786         memset(&args, 0, sizeof(args));
 787
 788         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
 789                                    &crev))
 790                 return;
 791
 792         switch (frev) {
 793         case 1:
 794                 switch (crev) {
 795                 case 1:
 796                         if (clock == ATOM_DISABLE)
 797                                 return;
 798                         args.v1.usPixelClock = cpu_to_le16(clock / 10);
 799                         args.v1.usRefDiv = cpu_to_le16(ref_div);
 800                         args.v1.usFbDiv = cpu_to_le16(fb_div);
 801                         args.v1.ucFracFbDiv = frac_fb_div;
 802                         args.v1.ucPostDiv = post_div;
 803                         args.v1.ucPpll = pll_id;
 804                         args.v1.ucCRTC = crtc_id;
 805                         args.v1.ucRefDivSrc = 1;
 806                         break;
 807                 case 2:
 808                         args.v2.usPixelClock = cpu_to_le16(clock / 10);
 809                         args.v2.usRefDiv = cpu_to_le16(ref_div);
 810                         args.v2.usFbDiv = cpu_to_le16(fb_div);
 811                         args.v2.ucFracFbDiv = frac_fb_div;
 812                         args.v2.ucPostDiv = post_div;
 813                         args.v2.ucPpll = pll_id;
 814                         args.v2.ucCRTC = crtc_id;
 815                         args.v2.ucRefDivSrc = 1;
 816                         break;
 817                 case 3:
 818                         args.v3.usPixelClock = cpu_to_le16(clock / 10);
 819                         args.v3.usRefDiv = cpu_to_le16(ref_div);
 820                         args.v3.usFbDiv = cpu_to_le16(fb_div);
 821                         args.v3.ucFracFbDiv = frac_fb_div;
 822                         args.v3.ucPostDiv = post_div;
 823                         args.v3.ucPpll = pll_id;
 824                         if (crtc_id == ATOM_CRTC2)
 825                                 args.v3.ucMiscInfo = PIXEL_CLOCK_MISC_CRTC_SEL_CRTC2;
 826                         else
 827                                 args.v3.ucMiscInfo = PIXEL_CLOCK_MISC_CRTC_SEL_CRTC1;
 828                         if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))
 829                                 args.v3.ucMiscInfo |= PIXEL_CLOCK_MISC_REF_DIV_SRC;
 830                         args.v3.ucTransmitterId = encoder_id;
 831                         args.v3.ucEncoderMode = encoder_mode;
 832                         break;
 833                 case 5:
 834                         args.v5.ucCRTC = crtc_id;
 835                         args.v5.usPixelClock = cpu_to_le16(clock / 10);
 836                         args.v5.ucRefDiv = ref_div;
 837                         args.v5.usFbDiv = cpu_to_le16(fb_div);
 838                         args.v5.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000);
 839                         args.v5.ucPostDiv = post_div;
 840                         args.v5.ucMiscInfo = 0; /* HDMI depth, etc. */
 841                         if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))
 842                                 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_REF_DIV_SRC;
 843                         switch (bpc) {
 844                         case 8:
 845                         default:
 846                                 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_24BPP;
 847                                 break;
 848                         case 10:
 849                                 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_30BPP;
 850                                 break;
 851                         }
 852                         args.v5.ucTransmitterID = encoder_id;
 853                         args.v5.ucEncoderMode = encoder_mode;
 854                         args.v5.ucPpll = pll_id;
 855                         break;
 856                 case 6:
 857                         args.v6.ulDispEngClkFreq = cpu_to_le32(crtc_id << 24 | clock / 10);
 858                         args.v6.ucRefDiv = ref_div;
 859                         args.v6.usFbDiv = cpu_to_le16(fb_div);
 860                         args.v6.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000);
 861                         args.v6.ucPostDiv = post_div;
 862                         args.v6.ucMiscInfo = 0; /* HDMI depth, etc. */
 863                         if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))
 864                                 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_REF_DIV_SRC;
 865                         switch (bpc) {
 866                         case 8:
 867                         default:
 868                                 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_24BPP;
 869                                 break;
 870                         case 10:
 871                                 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_30BPP;
 872                                 break;
 873                         case 12:
 874                                 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_36BPP;
 875                                 break;
 876                         case 16:
 877                                 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_48BPP;
 878                                 break;
 879                         }
 880                         args.v6.ucTransmitterID = encoder_id;
 881                         args.v6.ucEncoderMode = encoder_mode;
 882                         args.v6.ucPpll = pll_id;
 883                         break;
 884                 default:
 885                         DRM_ERROR("Unknown table version %d %d\n", frev, crev);
 886                         return;
 887                 }
 888                 break;
 889         default:
 890                 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
 891                 return;
 892         }
 893
 894         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 895 }
 896
 897 static bool atombios_crtc_prepare_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
 898 {
 899         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 900         struct drm_device *dev = crtc->dev;
 901         struct radeon_device *rdev = dev->dev_private;
 902         struct radeon_encoder *radeon_encoder =
 903                 to_radeon_encoder(radeon_crtc->encoder);
 904         int encoder_mode = atombios_get_encoder_mode(radeon_crtc->encoder);
 905
 906         radeon_crtc->bpc = 8;
 907         radeon_crtc->ss_enabled = false;
 908
 909         if ((radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) ||
 910             (radeon_encoder_get_dp_bridge_encoder_id(radeon_crtc->encoder) != ENCODER_OBJECT_ID_NONE)) {
 911                 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 912                 struct drm_connector *connector =
 913                         radeon_get_connector_for_encoder(radeon_crtc->encoder);
 914                 struct radeon_connector *radeon_connector =
 915                         to_radeon_connector(connector);
 916                 struct radeon_connector_atom_dig *dig_connector =
 917                         radeon_connector->con_priv;
 918                 int dp_clock;
 919                 radeon_crtc->bpc = radeon_get_monitor_bpc(connector);
 920
 921                 switch (encoder_mode) {
 922                 case ATOM_ENCODER_MODE_DP_MST:
 923                 case ATOM_ENCODER_MODE_DP:
 924                         /* DP/eDP */
 925                         dp_clock = dig_connector->dp_clock / 10;
 926                         if (ASIC_IS_DCE4(rdev))
 927                                 radeon_crtc->ss_enabled =
 928                                         radeon_atombios_get_asic_ss_info(rdev, &radeon_crtc->ss,
 929                                                                          ASIC_INTERNAL_SS_ON_DP,
 930                                                                          dp_clock);
 931                         else {
 932                                 if (dp_clock == 16200) {
 933                                         radeon_crtc->ss_enabled =
 934                                                 radeon_atombios_get_ppll_ss_info(rdev,
 935                                                                                  &radeon_crtc->ss,
 936                                                                                  ATOM_DP_SS_ID2);
 937                                         if (!radeon_crtc->ss_enabled)
 938                                                 radeon_crtc->ss_enabled =
 939                                                         radeon_atombios_get_ppll_ss_info(rdev,
 940                                                                                          &radeon_crtc->ss,
 941                                                                                          ATOM_DP_SS_ID1);
 942                                 } else
 943                                         radeon_crtc->ss_enabled =
 944                                                 radeon_atombios_get_ppll_ss_info(rdev,
 945                                                                                  &radeon_crtc->ss,
 946                                                                                  ATOM_DP_SS_ID1);
 947                         }
 948                         break;
 949                 case ATOM_ENCODER_MODE_LVDS:
 950                         if (ASIC_IS_DCE4(rdev))
 951                                 radeon_crtc->ss_enabled =
 952                                         radeon_atombios_get_asic_ss_info(rdev,
 953                                                                          &radeon_crtc->ss,
 954                                                                          dig->lcd_ss_id,
 955                                                                          mode->clock / 10);
 956                         else
 957                                 radeon_crtc->ss_enabled =
 958                                         radeon_atombios_get_ppll_ss_info(rdev,
 959                                                                          &radeon_crtc->ss,
 960                                                                          dig->lcd_ss_id);
 961                         break;
 962                 case ATOM_ENCODER_MODE_DVI:
 963                         if (ASIC_IS_DCE4(rdev))
 964                                 radeon_crtc->ss_enabled =
 965                                         radeon_atombios_get_asic_ss_info(rdev,
 966                                                                          &radeon_crtc->ss,
 967                                                                          ASIC_INTERNAL_SS_ON_TMDS,
 968                                                                          mode->clock / 10);
 969                         break;
 970                 case ATOM_ENCODER_MODE_HDMI:
 971                         if (ASIC_IS_DCE4(rdev))
 972                                 radeon_crtc->ss_enabled =
 973                                         radeon_atombios_get_asic_ss_info(rdev,
 974                                                                          &radeon_crtc->ss,
 975                                                                          ASIC_INTERNAL_SS_ON_HDMI,
 976                                                                          mode->clock / 10);
 977                         break;
 978                 default:
 979                         break;
 980                 }
 981         }
 982
 983         /* adjust pixel clock as needed */
 984         radeon_crtc->adjusted_clock = atombios_adjust_pll(crtc, mode);
 985
 986         return true;
 987 }
 988
 989 static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
 990 {
 991         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 992         struct drm_device *dev = crtc->dev;
 993         struct radeon_device *rdev = dev->dev_private;
 994         struct radeon_encoder *radeon_encoder =
 995                 to_radeon_encoder(radeon_crtc->encoder);
 996         u32 pll_clock = mode->clock;
 997         u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0;
 998         struct radeon_pll *pll;
 999         int encoder_mode = atombios_get_encoder_mode(radeon_crtc->encoder);
1000
1001         switch (radeon_crtc->pll_id) {
1002         case ATOM_PPLL1:
1003                 pll = &rdev->clock.p1pll;
1004                 break;
1005         case ATOM_PPLL2:
1006                 pll = &rdev->clock.p2pll;
1007                 break;
1008         case ATOM_DCPLL:
1009         case ATOM_PPLL_INVALID:
1010         default:
1011                 pll = &rdev->clock.dcpll;
1012                 break;
1013         }
1014
1015         /* update pll params */
1016         pll->flags = radeon_crtc->pll_flags;
1017         pll->reference_div = radeon_crtc->pll_reference_div;
1018         pll->post_div = radeon_crtc->pll_post_div;
1019
1020         if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1021                 /* TV seems to prefer the legacy algo on some boards */
1022                 radeon_compute_pll_legacy(pll, radeon_crtc->adjusted_clock, &pll_clock,
1023                                           &fb_div, &frac_fb_div, &ref_div, &post_div);
1024         else if (ASIC_IS_AVIVO(rdev))
1025                 radeon_compute_pll_avivo(pll, radeon_crtc->adjusted_clock, &pll_clock,
1026                                          &fb_div, &frac_fb_div, &ref_div, &post_div);
1027         else
1028                 radeon_compute_pll_legacy(pll, radeon_crtc->adjusted_clock, &pll_clock,
1029                                           &fb_div, &frac_fb_div, &ref_div, &post_div);
1030
1031         atombios_crtc_program_ss(rdev, ATOM_DISABLE, radeon_crtc->pll_id,
1032                                  radeon_crtc->crtc_id, &radeon_crtc->ss);
1033
1034         atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
1035                                   encoder_mode, radeon_encoder->encoder_id, mode->clock,
1036                                   ref_div, fb_div, frac_fb_div, post_div,
1037                                   radeon_crtc->bpc, radeon_crtc->ss_enabled, &radeon_crtc->ss);
1038
1039         if (radeon_crtc->ss_enabled) {
1040                 /* calculate ss amount and step size */
1041                 if (ASIC_IS_DCE4(rdev)) {
1042                         u32 step_size;
1043                         u32 amount = (((fb_div * 10) + frac_fb_div) * radeon_crtc->ss.percentage) / 10000;
1044                         radeon_crtc->ss.amount = (amount / 10) & ATOM_PPLL_SS_AMOUNT_V2_FBDIV_MASK;
1045                         radeon_crtc->ss.amount |= ((amount - (amount / 10)) << ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT) &
1046                                 ATOM_PPLL_SS_AMOUNT_V2_NFRAC_MASK;
1047                         if (radeon_crtc->ss.type & ATOM_PPLL_SS_TYPE_V2_CENTRE_SPREAD)
1048                                 step_size = (4 * amount * ref_div * (radeon_crtc->ss.rate * 2048)) /
1049                                         (125 * 25 * pll->reference_freq / 100);
1050                         else
1051                                 step_size = (2 * amount * ref_div * (radeon_crtc->ss.rate * 2048)) /
1052                                         (125 * 25 * pll->reference_freq / 100);
1053                         radeon_crtc->ss.step = step_size;
1054                 }
1055
1056                 atombios_crtc_program_ss(rdev, ATOM_ENABLE, radeon_crtc->pll_id,
1057                                          radeon_crtc->crtc_id, &radeon_crtc->ss);
1058         }
1059 }
1060
1061 static int dce4_crtc_do_set_base(struct drm_crtc *crtc,
1062                                  struct drm_framebuffer *fb,
1063                                  int x, int y, int atomic)
1064 {
1065         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1066         struct drm_device *dev = crtc->dev;
1067         struct radeon_device *rdev = dev->dev_private;
1068         struct radeon_framebuffer *radeon_fb;
1069         struct drm_framebuffer *target_fb;
1070         struct drm_gem_object *obj;
1071         struct radeon_bo *rbo;
1072         uint64_t fb_location;
1073         uint32_t fb_format, fb_pitch_pixels, tiling_flags;
1074         unsigned bankw, bankh, mtaspect, tile_split;
1075         u32 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_NONE);
1076         u32 tmp, viewport_w, viewport_h;
1077         int r;
1078
1079         /* no fb bound */
1080         if (!atomic && !crtc->fb) {
1081                 DRM_DEBUG_KMS("No FB bound\n");
1082                 return 0;
1083         }
1084
1085         if (atomic) {
1086                 radeon_fb = to_radeon_framebuffer(fb);
1087                 target_fb = fb;
1088         }
1089         else {
1090                 radeon_fb = to_radeon_framebuffer(crtc->fb);
1091                 target_fb = crtc->fb;
1092         }
1093
1094         /* If atomic, assume fb object is pinned & idle & fenced and
1095          * just update base pointers
1096          */
1097         obj = radeon_fb->obj;
1098         rbo = gem_to_radeon_bo(obj);
1099         r = radeon_bo_reserve(rbo, false);
1100         if (unlikely(r != 0))
1101                 return r;
1102
1103         if (atomic)
1104                 fb_location = radeon_bo_gpu_offset(rbo);
1105         else {
1106                 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location);
1107                 if (unlikely(r != 0)) {
1108                         radeon_bo_unreserve(rbo);
1109                         return -EINVAL;
1110                 }
1111         }
1112
1113         radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
1114         radeon_bo_unreserve(rbo);
1115
1116         switch (target_fb->bits_per_pixel) {
1117         case 8:
1118                 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_8BPP) |
1119                              EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_INDEXED));
1120                 break;
1121         case 15:
1122                 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
1123                              EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB1555));
1124                 break;
1125         case 16:
1126                 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
1127                              EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB565));
1128 #ifdef __BIG_ENDIAN
1129                 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16);
1130 #endif
1131                 break;
1132         case 24:
1133         case 32:
1134                 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) |
1135                              EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB8888));
1136 #ifdef __BIG_ENDIAN
1137                 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32);
1138 #endif
1139                 break;
1140         default:
1141                 DRM_ERROR("Unsupported screen depth %d\n",
1142                           target_fb->bits_per_pixel);
1143                 return -EINVAL;
1144         }
1145
1146         if (tiling_flags & RADEON_TILING_MACRO) {
1147                 if (rdev->family >= CHIP_TAHITI)
1148                         tmp = rdev->config.si.tile_config;
1149                 else if (rdev->family >= CHIP_CAYMAN)
1150                         tmp = rdev->config.cayman.tile_config;
1151                 else
1152                         tmp = rdev->config.evergreen.tile_config;
1153
1154                 switch ((tmp & 0xf0) >> 4) {
1155                 case 0: /* 4 banks */
1156                         fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_4_BANK);
1157                         break;
1158                 case 1: /* 8 banks */
1159                 default:
1160                         fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_8_BANK);
1161                         break;
1162                 case 2: /* 16 banks */
1163                         fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_16_BANK);
1164                         break;
1165                 }
1166
1167                 fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_2D_TILED_THIN1);
1168
1169                 evergreen_tiling_fields(tiling_flags, &bankw, &bankh, &mtaspect, &tile_split);
1170                 fb_format |= EVERGREEN_GRPH_TILE_SPLIT(tile_split);
1171                 fb_format |= EVERGREEN_GRPH_BANK_WIDTH(bankw);
1172                 fb_format |= EVERGREEN_GRPH_BANK_HEIGHT(bankh);
1173                 fb_format |= EVERGREEN_GRPH_MACRO_TILE_ASPECT(mtaspect);
1174         } else if (tiling_flags & RADEON_TILING_MICRO)
1175                 fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_1D_TILED_THIN1);
1176
1177         if ((rdev->family == CHIP_TAHITI) ||
1178             (rdev->family == CHIP_PITCAIRN))
1179                 fb_format |= SI_GRPH_PIPE_CONFIG(SI_ADDR_SURF_P8_32x32_8x16);
1180         else if (rdev->family == CHIP_VERDE)
1181                 fb_format |= SI_GRPH_PIPE_CONFIG(SI_ADDR_SURF_P4_8x16);
1182
1183         switch (radeon_crtc->crtc_id) {
1184         case 0:
1185                 WREG32(AVIVO_D1VGA_CONTROL, 0);
1186                 break;
1187         case 1:
1188                 WREG32(AVIVO_D2VGA_CONTROL, 0);
1189                 break;
1190         case 2:
1191                 WREG32(EVERGREEN_D3VGA_CONTROL, 0);
1192                 break;
1193         case 3:
1194                 WREG32(EVERGREEN_D4VGA_CONTROL, 0);
1195                 break;
1196         case 4:
1197                 WREG32(EVERGREEN_D5VGA_CONTROL, 0);
1198                 break;
1199         case 5:
1200                 WREG32(EVERGREEN_D6VGA_CONTROL, 0);
1201                 break;
1202         default:
1203                 break;
1204         }
1205
1206         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
1207                upper_32_bits(fb_location));
1208         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
1209                upper_32_bits(fb_location));
1210         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
1211                (u32)fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK);
1212         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
1213                (u32) fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK);
1214         WREG32(EVERGREEN_GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
1215         WREG32(EVERGREEN_GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap);
1216
1217         WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
1218         WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
1219         WREG32(EVERGREEN_GRPH_X_START + radeon_crtc->crtc_offset, 0);
1220         WREG32(EVERGREEN_GRPH_Y_START + radeon_crtc->crtc_offset, 0);
1221         WREG32(EVERGREEN_GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width);
1222         WREG32(EVERGREEN_GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height);
1223
1224         fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8);
1225         WREG32(EVERGREEN_GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
1226         WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
1227
1228         WREG32(EVERGREEN_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
1229                target_fb->height);
1230         x &= ~3;
1231         y &= ~1;
1232         WREG32(EVERGREEN_VIEWPORT_START + radeon_crtc->crtc_offset,
1233                (x << 16) | y);
1234         viewport_w = crtc->mode.hdisplay;
1235         viewport_h = (crtc->mode.vdisplay + 1) & ~1;
1236         WREG32(EVERGREEN_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
1237                (viewport_w << 16) | viewport_h);
1238
1239         /* pageflip setup */
1240         /* make sure flip is at vb rather than hb */
1241         tmp = RREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset);
1242         tmp &= ~EVERGREEN_GRPH_SURFACE_UPDATE_H_RETRACE_EN;
1243         WREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, tmp);
1244
1245         /* set pageflip to happen anywhere in vblank interval */
1246         WREG32(EVERGREEN_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 0);
1247
1248         if (!atomic && fb && fb != crtc->fb) {
1249                 radeon_fb = to_radeon_framebuffer(fb);
1250                 rbo = gem_to_radeon_bo(radeon_fb->obj);
1251                 r = radeon_bo_reserve(rbo, false);
1252                 if (unlikely(r != 0))
1253                         return r;
1254                 radeon_bo_unpin(rbo);
1255                 radeon_bo_unreserve(rbo);
1256         }
1257
1258         /* Bytes per pixel may have changed */
1259         radeon_bandwidth_update(rdev);
1260
1261         return 0;
1262 }
1263
1264 static int avivo_crtc_do_set_base(struct drm_crtc *crtc,
1265                                   struct drm_framebuffer *fb,
1266                                   int x, int y, int atomic)
1267 {
1268         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1269         struct drm_device *dev = crtc->dev;
1270         struct radeon_device *rdev = dev->dev_private;
1271         struct radeon_framebuffer *radeon_fb;
1272         struct drm_gem_object *obj;
1273         struct radeon_bo *rbo;
1274         struct drm_framebuffer *target_fb;
1275         uint64_t fb_location;
1276         uint32_t fb_format, fb_pitch_pixels, tiling_flags;
1277         u32 fb_swap = R600_D1GRPH_SWAP_ENDIAN_NONE;
1278         u32 tmp, viewport_w, viewport_h;
1279         int r;
1280
1281         /* no fb bound */
1282         if (!atomic && !crtc->fb) {
1283                 DRM_DEBUG_KMS("No FB bound\n");
1284                 return 0;
1285         }
1286
1287         if (atomic) {
1288                 radeon_fb = to_radeon_framebuffer(fb);
1289                 target_fb = fb;
1290         }
1291         else {
1292                 radeon_fb = to_radeon_framebuffer(crtc->fb);
1293                 target_fb = crtc->fb;
1294         }
1295
1296         obj = radeon_fb->obj;
1297         rbo = gem_to_radeon_bo(obj);
1298         r = radeon_bo_reserve(rbo, false);
1299         if (unlikely(r != 0))
1300                 return r;
1301
1302         /* If atomic, assume fb object is pinned & idle & fenced and
1303          * just update base pointers
1304          */
1305         if (atomic)
1306                 fb_location = radeon_bo_gpu_offset(rbo);
1307         else {
1308                 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location);
1309                 if (unlikely(r != 0)) {
1310                         radeon_bo_unreserve(rbo);
1311                         return -EINVAL;
1312                 }
1313         }
1314         radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
1315         radeon_bo_unreserve(rbo);
1316
1317         switch (target_fb->bits_per_pixel) {
1318         case 8:
1319                 fb_format =
1320                     AVIVO_D1GRPH_CONTROL_DEPTH_8BPP |
1321                     AVIVO_D1GRPH_CONTROL_8BPP_INDEXED;
1322                 break;
1323         case 15:
1324                 fb_format =
1325                     AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
1326                     AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555;
1327                 break;
1328         case 16:
1329                 fb_format =
1330                     AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
1331                     AVIVO_D1GRPH_CONTROL_16BPP_RGB565;
1332 #ifdef __BIG_ENDIAN
1333                 fb_swap = R600_D1GRPH_SWAP_ENDIAN_16BIT;
1334 #endif
1335                 break;
1336         case 24:
1337         case 32:
1338                 fb_format =
1339                     AVIVO_D1GRPH_CONTROL_DEPTH_32BPP |
1340                     AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888;
1341 #ifdef __BIG_ENDIAN
1342                 fb_swap = R600_D1GRPH_SWAP_ENDIAN_32BIT;
1343 #endif
1344                 break;
1345         default:
1346                 DRM_ERROR("Unsupported screen depth %d\n",
1347                           target_fb->bits_per_pixel);
1348                 return -EINVAL;
1349         }
1350
1351         if (rdev->family >= CHIP_R600) {
1352                 if (tiling_flags & RADEON_TILING_MACRO)
1353                         fb_format |= R600_D1GRPH_ARRAY_MODE_2D_TILED_THIN1;
1354                 else if (tiling_flags & RADEON_TILING_MICRO)
1355                         fb_format |= R600_D1GRPH_ARRAY_MODE_1D_TILED_THIN1;
1356         } else {
1357                 if (tiling_flags & RADEON_TILING_MACRO)
1358                         fb_format |= AVIVO_D1GRPH_MACRO_ADDRESS_MODE;
1359
1360                 if (tiling_flags & RADEON_TILING_MICRO)
1361                         fb_format |= AVIVO_D1GRPH_TILED;
1362         }
1363
1364         if (radeon_crtc->crtc_id == 0)
1365                 WREG32(AVIVO_D1VGA_CONTROL, 0);
1366         else
1367                 WREG32(AVIVO_D2VGA_CONTROL, 0);
1368
1369         if (rdev->family >= CHIP_RV770) {
1370                 if (radeon_crtc->crtc_id) {
1371                         WREG32(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1372                         WREG32(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1373                 } else {
1374                         WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1375                         WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1376                 }
1377         }
1378         WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
1379                (u32) fb_location);
1380         WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS +
1381                radeon_crtc->crtc_offset, (u32) fb_location);
1382         WREG32(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
1383         if (rdev->family >= CHIP_R600)
1384                 WREG32(R600_D1GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap);
1385
1386         WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
1387         WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
1388         WREG32(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, 0);
1389         WREG32(AVIVO_D1GRPH_Y_START + radeon_crtc->crtc_offset, 0);
1390         WREG32(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width);
1391         WREG32(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height);
1392
1393         fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8);
1394         WREG32(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
1395         WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
1396
1397         WREG32(AVIVO_D1MODE_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
1398                target_fb->height);
1399         x &= ~3;
1400         y &= ~1;
1401         WREG32(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset,
1402                (x << 16) | y);
1403         viewport_w = crtc->mode.hdisplay;
1404         viewport_h = (crtc->mode.vdisplay + 1) & ~1;
1405         WREG32(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
1406                (viewport_w << 16) | viewport_h);
1407
1408         /* pageflip setup */
1409         /* make sure flip is at vb rather than hb */
1410         tmp = RREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset);
1411         tmp &= ~AVIVO_D1GRPH_SURFACE_UPDATE_H_RETRACE_EN;
1412         WREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, tmp);
1413
1414         /* set pageflip to happen anywhere in vblank interval */
1415         WREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 0);
1416
1417         if (!atomic && fb && fb != crtc->fb) {
1418                 radeon_fb = to_radeon_framebuffer(fb);
1419                 rbo = gem_to_radeon_bo(radeon_fb->obj);
1420                 r = radeon_bo_reserve(rbo, false);
1421                 if (unlikely(r != 0))
1422                         return r;
1423                 radeon_bo_unpin(rbo);
1424                 radeon_bo_unreserve(rbo);
1425         }
1426
1427         /* Bytes per pixel may have changed */
1428         radeon_bandwidth_update(rdev);
1429
1430         return 0;
1431 }
1432
1433 int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
1434                            struct drm_framebuffer *old_fb)
1435 {
1436         struct drm_device *dev = crtc->dev;
1437         struct radeon_device *rdev = dev->dev_private;
1438
1439         if (ASIC_IS_DCE4(rdev))
1440                 return dce4_crtc_do_set_base(crtc, old_fb, x, y, 0);
1441         else if (ASIC_IS_AVIVO(rdev))
1442                 return avivo_crtc_do_set_base(crtc, old_fb, x, y, 0);
1443         else
1444                 return radeon_crtc_do_set_base(crtc, old_fb, x, y, 0);
1445 }
1446
1447 int atombios_crtc_set_base_atomic(struct drm_crtc *crtc,
1448                                   struct drm_framebuffer *fb,
1449                                   int x, int y, enum mode_set_atomic state)
1450 {
1451        struct drm_device *dev = crtc->dev;
1452        struct radeon_device *rdev = dev->dev_private;
1453
1454         if (ASIC_IS_DCE4(rdev))
1455                 return dce4_crtc_do_set_base(crtc, fb, x, y, 1);
1456         else if (ASIC_IS_AVIVO(rdev))
1457                 return avivo_crtc_do_set_base(crtc, fb, x, y, 1);
1458         else
1459                 return radeon_crtc_do_set_base(crtc, fb, x, y, 1);
1460 }
1461
1462 /* properly set additional regs when using atombios */
1463 static void radeon_legacy_atom_fixup(struct drm_crtc *crtc)
1464 {
1465         struct drm_device *dev = crtc->dev;
1466         struct radeon_device *rdev = dev->dev_private;
1467         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1468         u32 disp_merge_cntl;
1469
1470         switch (radeon_crtc->crtc_id) {
1471         case 0:
1472                 disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL);
1473                 disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN;
1474                 WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl);
1475                 break;
1476         case 1:
1477                 disp_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL);
1478                 disp_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN;
1479                 WREG32(RADEON_DISP2_MERGE_CNTL, disp_merge_cntl);
1480                 WREG32(RADEON_FP_H2_SYNC_STRT_WID,   RREG32(RADEON_CRTC2_H_SYNC_STRT_WID));
1481                 WREG32(RADEON_FP_V2_SYNC_STRT_WID,   RREG32(RADEON_CRTC2_V_SYNC_STRT_WID));
1482                 break;
1483         }
1484 }
1485
1486 /**
1487  * radeon_get_pll_use_mask - look up a mask of which pplls are in use
1488  *
1489  * @crtc: drm crtc
1490  *
1491  * Returns the mask of which PPLLs (Pixel PLLs) are in use.
1492  */
1493 static u32 radeon_get_pll_use_mask(struct drm_crtc *crtc)
1494 {
1495         struct drm_device *dev = crtc->dev;
1496         struct drm_crtc *test_crtc;
1497         struct radeon_crtc *test_radeon_crtc;
1498         u32 pll_in_use = 0;
1499
1500         list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) {
1501                 if (crtc == test_crtc)
1502                         continue;
1503
1504                 test_radeon_crtc = to_radeon_crtc(test_crtc);
1505                 if (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID)
1506                         pll_in_use |= (1 << test_radeon_crtc->pll_id);
1507         }
1508         return pll_in_use;
1509 }
1510
1511 /**
1512  * radeon_get_shared_dp_ppll - return the PPLL used by another crtc for DP
1513  *
1514  * @crtc: drm crtc
1515  *
1516  * Returns the PPLL (Pixel PLL) used by another crtc/encoder which is
1517  * also in DP mode.  For DP, a single PPLL can be used for all DP
1518  * crtcs/encoders.
1519  */
1520 static int radeon_get_shared_dp_ppll(struct drm_crtc *crtc)
1521 {
1522         struct drm_device *dev = crtc->dev;
1523         struct drm_crtc *test_crtc;
1524         struct radeon_crtc *test_radeon_crtc;
1525
1526         list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) {
1527                 if (crtc == test_crtc)
1528                         continue;
1529                 test_radeon_crtc = to_radeon_crtc(test_crtc);
1530                 if (test_radeon_crtc->encoder &&
1531                     ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_radeon_crtc->encoder))) {
1532                         /* for DP use the same PLL for all */
1533                         if (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID)
1534                                 return test_radeon_crtc->pll_id;
1535                 }
1536         }
1537         return ATOM_PPLL_INVALID;
1538 }
1539
1540 /**
1541  * radeon_get_shared_nondp_ppll - return the PPLL used by another non-DP crtc
1542  *
1543  * @crtc: drm crtc
1544  * @encoder: drm encoder
1545  *
1546  * Returns the PPLL (Pixel PLL) used by another non-DP crtc/encoder which can
1547  * be shared (i.e., same clock).
1548  */
1549 static int radeon_get_shared_nondp_ppll(struct drm_crtc *crtc)
1550 {
1551         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1552         struct drm_device *dev = crtc->dev;
1553         struct drm_crtc *test_crtc;
1554         struct radeon_crtc *test_radeon_crtc;
1555         u32 adjusted_clock, test_adjusted_clock;
1556
1557         adjusted_clock = radeon_crtc->adjusted_clock;
1558
1559         if (adjusted_clock == 0)
1560                 return ATOM_PPLL_INVALID;
1561
1562         list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) {
1563                 if (crtc == test_crtc)
1564                         continue;
1565                 test_radeon_crtc = to_radeon_crtc(test_crtc);
1566                 if (test_radeon_crtc->encoder &&
1567                     !ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_radeon_crtc->encoder))) {
1568                         /* check if we are already driving this connector with another crtc */
1569                         if (test_radeon_crtc->connector == radeon_crtc->connector) {
1570                                 /* if we are, return that pll */
1571                                 if (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID)
1572                                         return test_radeon_crtc->pll_id;
1573                         }
1574                         /* for non-DP check the clock */
1575                         test_adjusted_clock = test_radeon_crtc->adjusted_clock;
1576                         if ((crtc->mode.clock == test_crtc->mode.clock) &&
1577                             (adjusted_clock == test_adjusted_clock) &&
1578                             (radeon_crtc->ss_enabled == test_radeon_crtc->ss_enabled) &&
1579                             (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID))
1580                                 return test_radeon_crtc->pll_id;
1581                 }
1582         }
1583         return ATOM_PPLL_INVALID;
1584 }
1585
1586 /**
1587  * radeon_atom_pick_pll - Allocate a PPLL for use by the crtc.
1588  *
1589  * @crtc: drm crtc
1590  *
1591  * Returns the PPLL (Pixel PLL) to be used by the crtc.  For DP monitors
1592  * a single PPLL can be used for all DP crtcs/encoders.  For non-DP
1593  * monitors a dedicated PPLL must be used.  If a particular board has
1594  * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming
1595  * as there is no need to program the PLL itself.  If we are not able to
1596  * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to
1597  * avoid messing up an existing monitor.
1598  *
1599  * Asic specific PLL information
1600  *
1601  * DCE 6.1
1602  * - PPLL2 is only available to UNIPHYA (both DP and non-DP)
1603  * - PPLL0, PPLL1 are available for UNIPHYB/C/D/E/F (both DP and non-DP)
1604  *
1605  * DCE 6.0
1606  * - PPLL0 is available to all UNIPHY (DP only)
1607  * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
1608  *
1609  * DCE 5.0
1610  * - DCPLL is available to all UNIPHY (DP only)
1611  * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
1612  *
1613  * DCE 3.0/4.0/4.1
1614  * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
1615  *
1616  */
1617 static int radeon_atom_pick_pll(struct drm_crtc *crtc)
1618 {
1619         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1620         struct drm_device *dev = crtc->dev;
1621         struct radeon_device *rdev = dev->dev_private;
1622         struct radeon_encoder *radeon_encoder =
1623                 to_radeon_encoder(radeon_crtc->encoder);
1624         u32 pll_in_use;
1625         int pll;
1626
1627         if (ASIC_IS_DCE61(rdev)) {
1628                 struct radeon_encoder_atom_dig *dig =
1629                         radeon_encoder->enc_priv;
1630
1631                 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY) &&
1632                     (dig->linkb == false))
1633                         /* UNIPHY A uses PPLL2 */
1634                         return ATOM_PPLL2;
1635                 else if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) {
1636                         /* UNIPHY B/C/D/E/F */
1637                         if (rdev->clock.dp_extclk)
1638                                 /* skip PPLL programming if using ext clock */
1639                                 return ATOM_PPLL_INVALID;
1640                         else {
1641                                 /* use the same PPLL for all DP monitors */
1642                                 pll = radeon_get_shared_dp_ppll(crtc);
1643                                 if (pll != ATOM_PPLL_INVALID)
1644                                         return pll;
1645                         }
1646                 } else {
1647                         /* use the same PPLL for all monitors with the same clock */
1648                         pll = radeon_get_shared_nondp_ppll(crtc);
1649                         if (pll != ATOM_PPLL_INVALID)
1650                                 return pll;
1651                 }
1652                 /* UNIPHY B/C/D/E/F */
1653                 pll_in_use = radeon_get_pll_use_mask(crtc);
1654                 if (!(pll_in_use & (1 << ATOM_PPLL0)))
1655                         return ATOM_PPLL0;
1656                 if (!(pll_in_use & (1 << ATOM_PPLL1)))
1657                         return ATOM_PPLL1;
1658                 DRM_ERROR("unable to allocate a PPLL\n");
1659                 return ATOM_PPLL_INVALID;
1660         } else if (ASIC_IS_DCE4(rdev)) {
1661                 /* in DP mode, the DP ref clock can come from PPLL, DCPLL, or ext clock,
1662                  * depending on the asic:
1663                  * DCE4: PPLL or ext clock
1664                  * DCE5: PPLL, DCPLL, or ext clock
1665                  * DCE6: PPLL, PPLL0, or ext clock
1666                  *
1667                  * Setting ATOM_PPLL_INVALID will cause SetPixelClock to skip
1668                  * PPLL/DCPLL programming and only program the DP DTO for the
1669                  * crtc virtual pixel clock.
1670                  */
1671                 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) {
1672                         if (rdev->clock.dp_extclk)
1673                                 /* skip PPLL programming if using ext clock */
1674                                 return ATOM_PPLL_INVALID;
1675                         else if (ASIC_IS_DCE6(rdev))
1676                                 /* use PPLL0 for all DP */
1677                                 return ATOM_PPLL0;
1678                         else if (ASIC_IS_DCE5(rdev))
1679                                 /* use DCPLL for all DP */
1680                                 return ATOM_DCPLL;
1681                         else {
1682                                 /* use the same PPLL for all DP monitors */
1683                                 pll = radeon_get_shared_dp_ppll(crtc);
1684                                 if (pll != ATOM_PPLL_INVALID)
1685                                         return pll;
1686                         }
1687                 } else {
1688                         /* use the same PPLL for all monitors with the same clock */
1689                         pll = radeon_get_shared_nondp_ppll(crtc);
1690                         if (pll != ATOM_PPLL_INVALID)
1691                                 return pll;
1692                 }
1693                 /* all other cases */
1694                 pll_in_use = radeon_get_pll_use_mask(crtc);
1695                 if (!(pll_in_use & (1 << ATOM_PPLL1)))
1696                         return ATOM_PPLL1;
1697                 if (!(pll_in_use & (1 << ATOM_PPLL2)))
1698                         return ATOM_PPLL2;
1699                 DRM_ERROR("unable to allocate a PPLL\n");
1700                 return ATOM_PPLL_INVALID;
1701         } else {
1702                 /* on pre-R5xx asics, the crtc to pll mapping is hardcoded */
1703                 /* some atombios (observed in some DCE2/DCE3) code have a bug,
1704                  * the matching btw pll and crtc is done through
1705                  * PCLK_CRTC[1|2]_CNTL (0x480/0x484) but atombios code use the
1706                  * pll (1 or 2) to select which register to write. ie if using
1707                  * pll1 it will use PCLK_CRTC1_CNTL (0x480) and if using pll2
1708                  * it will use PCLK_CRTC2_CNTL (0x484), it then use crtc id to
1709                  * choose which value to write. Which is reverse order from
1710                  * register logic. So only case that works is when pllid is
1711                  * same as crtcid or when both pll and crtc are enabled and
1712                  * both use same clock.
1713                  *
1714                  * So just return crtc id as if crtc and pll were hard linked
1715                  * together even if they aren't
1716                  */
1717                 return radeon_crtc->crtc_id;
1718         }
1719 }
1720
1721 void radeon_atom_disp_eng_pll_init(struct radeon_device *rdev)
1722 {
1723         /* always set DCPLL */
1724         if (ASIC_IS_DCE6(rdev))
1725                 atombios_crtc_set_disp_eng_pll(rdev, rdev->clock.default_dispclk);
1726         else if (ASIC_IS_DCE4(rdev)) {
1727                 struct radeon_atom_ss ss;
1728                 bool ss_enabled = radeon_atombios_get_asic_ss_info(rdev, &ss,
1729                                                                    ASIC_INTERNAL_SS_ON_DCPLL,
1730                                                                    rdev->clock.default_dispclk);
1731                 if (ss_enabled)
1732                         atombios_crtc_program_ss(rdev, ATOM_DISABLE, ATOM_DCPLL, -1, &ss);
1733                 /* XXX: DCE5, make sure voltage, dispclk is high enough */
1734                 atombios_crtc_set_disp_eng_pll(rdev, rdev->clock.default_dispclk);
1735                 if (ss_enabled)
1736                         atombios_crtc_program_ss(rdev, ATOM_ENABLE, ATOM_DCPLL, -1, &ss);
1737         }
1738
1739 }
1740
1741 int atombios_crtc_mode_set(struct drm_crtc *crtc,
1742                            struct drm_display_mode *mode,
1743                            struct drm_display_mode *adjusted_mode,
1744                            int x, int y, struct drm_framebuffer *old_fb)
1745 {
1746         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1747         struct drm_device *dev = crtc->dev;
1748         struct radeon_device *rdev = dev->dev_private;
1749         struct radeon_encoder *radeon_encoder =
1750                 to_radeon_encoder(radeon_crtc->encoder);
1751         bool is_tvcv = false;
1752
1753         if (radeon_encoder->active_device &
1754             (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
1755                 is_tvcv = true;
1756
1757         atombios_crtc_set_pll(crtc, adjusted_mode);
1758
1759         if (ASIC_IS_DCE4(rdev))
1760                 atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
1761         else if (ASIC_IS_AVIVO(rdev)) {
1762                 if (is_tvcv)
1763                         atombios_crtc_set_timing(crtc, adjusted_mode);
1764                 else
1765                         atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
1766         } else {
1767                 atombios_crtc_set_timing(crtc, adjusted_mode);
1768                 if (radeon_crtc->crtc_id == 0)
1769                         atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
1770                 radeon_legacy_atom_fixup(crtc);
1771         }
1772         atombios_crtc_set_base(crtc, x, y, old_fb);
1773         atombios_overscan_setup(crtc, mode, adjusted_mode);
1774         atombios_scaler_setup(crtc);
1775         return 0;
1776 }
1777
1778 static bool atombios_crtc_mode_fixup(struct drm_crtc *crtc,
1779                                      const struct drm_display_mode *mode,
1780                                      struct drm_display_mode *adjusted_mode)
1781 {
1782         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1783         struct drm_device *dev = crtc->dev;
1784         struct drm_encoder *encoder;
1785
1786         /* assign the encoder to the radeon crtc to avoid repeated lookups later */
1787         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1788                 if (encoder->crtc == crtc) {
1789                         radeon_crtc->encoder = encoder;
1790                         radeon_crtc->connector = radeon_get_connector_for_encoder(encoder);
1791                         break;
1792                 }
1793         }
1794         if ((radeon_crtc->encoder == NULL) || (radeon_crtc->connector == NULL)) {
1795                 radeon_crtc->encoder = NULL;
1796                 radeon_crtc->connector = NULL;
1797                 return false;
1798         }
1799         if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
1800                 return false;
1801         if (!atombios_crtc_prepare_pll(crtc, adjusted_mode))
1802                 return false;
1803         /* pick pll */
1804         radeon_crtc->pll_id = radeon_atom_pick_pll(crtc);
1805         /* if we can't get a PPLL for a non-DP encoder, fail */
1806         if ((radeon_crtc->pll_id == ATOM_PPLL_INVALID) &&
1807             !ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder)))
1808                 return false;
1809
1810         return true;
1811 }
1812
1813 static void atombios_crtc_prepare(struct drm_crtc *crtc)
1814 {
1815         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1816         struct drm_device *dev = crtc->dev;
1817         struct radeon_device *rdev = dev->dev_private;
1818
1819         radeon_crtc->in_mode_set = true;
1820
1821         /* disable crtc pair power gating before programming */
1822         if (ASIC_IS_DCE6(rdev))
1823                 atombios_powergate_crtc(crtc, ATOM_DISABLE);
1824
1825         atombios_lock_crtc(crtc, ATOM_ENABLE);
1826         atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
1827 }
1828
1829 static void atombios_crtc_commit(struct drm_crtc *crtc)
1830 {
1831         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1832
1833         atombios_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
1834         atombios_lock_crtc(crtc, ATOM_DISABLE);
1835         radeon_crtc->in_mode_set = false;
1836 }
1837
1838 static void atombios_crtc_disable(struct drm_crtc *crtc)
1839 {
1840         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1841         struct drm_device *dev = crtc->dev;
1842         struct radeon_device *rdev = dev->dev_private;
1843         struct radeon_atom_ss ss;
1844         int i;
1845
1846         atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
1847
1848         for (i = 0; i < rdev->num_crtc; i++) {
1849                 if (rdev->mode_info.crtcs[i] &&
1850                     rdev->mode_info.crtcs[i]->enabled &&
1851                     i != radeon_crtc->crtc_id &&
1852                     radeon_crtc->pll_id == rdev->mode_info.crtcs[i]->pll_id) {
1853                         /* one other crtc is using this pll don't turn
1854                          * off the pll
1855                          */
1856                         goto done;
1857                 }
1858         }
1859
1860         switch (radeon_crtc->pll_id) {
1861         case ATOM_PPLL1:
1862         case ATOM_PPLL2:
1863                 /* disable the ppll */
1864                 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
1865                                           0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
1866                 break;
1867         case ATOM_PPLL0:
1868                 /* disable the ppll */
1869                 if (ASIC_IS_DCE61(rdev))
1870                         atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
1871                                                   0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
1872                 break;
1873         default:
1874                 break;
1875         }
1876 done:
1877         radeon_crtc->pll_id = ATOM_PPLL_INVALID;
1878         radeon_crtc->adjusted_clock = 0;
1879         radeon_crtc->encoder = NULL;
1880         radeon_crtc->connector = NULL;
1881 }
1882
1883 static const struct drm_crtc_helper_funcs atombios_helper_funcs = {
1884         .dpms = atombios_crtc_dpms,
1885         .mode_fixup = atombios_crtc_mode_fixup,
1886         .mode_set = atombios_crtc_mode_set,
1887         .mode_set_base = atombios_crtc_set_base,
1888         .mode_set_base_atomic = atombios_crtc_set_base_atomic,
1889         .prepare = atombios_crtc_prepare,
1890         .commit = atombios_crtc_commit,
1891         .load_lut = radeon_crtc_load_lut,
1892         .disable = atombios_crtc_disable,
1893 };
1894
1895 void radeon_atombios_init_crtc(struct drm_device *dev,
1896                                struct radeon_crtc *radeon_crtc)
1897 {
1898         struct radeon_device *rdev = dev->dev_private;
1899
1900         if (ASIC_IS_DCE4(rdev)) {
1901                 switch (radeon_crtc->crtc_id) {
1902                 case 0:
1903                 default:
1904                         radeon_crtc->crtc_offset = EVERGREEN_CRTC0_REGISTER_OFFSET;
1905                         break;
1906                 case 1:
1907                         radeon_crtc->crtc_offset = EVERGREEN_CRTC1_REGISTER_OFFSET;
1908                         break;
1909                 case 2:
1910                         radeon_crtc->crtc_offset = EVERGREEN_CRTC2_REGISTER_OFFSET;
1911                         break;
1912                 case 3:
1913                         radeon_crtc->crtc_offset = EVERGREEN_CRTC3_REGISTER_OFFSET;
1914                         break;
1915                 case 4:
1916                         radeon_crtc->crtc_offset = EVERGREEN_CRTC4_REGISTER_OFFSET;
1917                         break;
1918                 case 5:
1919                         radeon_crtc->crtc_offset = EVERGREEN_CRTC5_REGISTER_OFFSET;
1920                         break;
1921                 }
1922         } else {
1923                 if (radeon_crtc->crtc_id == 1)
1924                         radeon_crtc->crtc_offset =
1925                                 AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL;
1926                 else
1927                         radeon_crtc->crtc_offset = 0;
1928         }
1929         radeon_crtc->pll_id = ATOM_PPLL_INVALID;
1930         radeon_crtc->adjusted_clock = 0;
1931         radeon_crtc->encoder = NULL;
1932         radeon_crtc->connector = NULL;
1933         drm_crtc_helper_add(&radeon_crtc->base, &atombios_helper_funcs);
1934 }