drivers/gpu/drm/radeon/atombios_crtc.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include <drm/drmP.h>
  27 #include <drm/drm_crtc_helper.h>
  28 #include <drm/radeon_drm.h>
  29 #include <drm/drm_fixed.h>
  30 #include "radeon.h"
  31 #include "atom.h"
  32 #include "atom-bits.h"
  33
  34 static void atombios_overscan_setup(struct drm_crtc *crtc,
  35                                     struct drm_display_mode *mode,
  36                                     struct drm_display_mode *adjusted_mode)
  37 {
  38         struct drm_device *dev = crtc->dev;
  39         struct radeon_device *rdev = dev->dev_private;
  40         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
  41         SET_CRTC_OVERSCAN_PS_ALLOCATION args;
  42         int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_OverScan);
  43         int a1, a2;
  44
  45         memset(&args, 0, sizeof(args));
  46
  47         args.ucCRTC = radeon_crtc->crtc_id;
  48
  49         switch (radeon_crtc->rmx_type) {
  50         case RMX_CENTER:
  51                 args.usOverscanTop = (adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2;
  52                 args.usOverscanBottom = (adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2;
  53                 args.usOverscanLeft = (adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2;
  54                 args.usOverscanRight = (adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2;
  55                 break;
  56         case RMX_ASPECT:
  57                 a1 = mode->crtc_vdisplay * adjusted_mode->crtc_hdisplay;
  58                 a2 = adjusted_mode->crtc_vdisplay * mode->crtc_hdisplay;
  59
  60                 if (a1 > a2) {
  61                         args.usOverscanLeft = (adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2;
  62                         args.usOverscanRight = (adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2;
  63                 } else if (a2 > a1) {
  64                         args.usOverscanLeft = (adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2;
  65                         args.usOverscanRight = (adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2;
  66                 }
  67                 break;
  68         case RMX_FULL:
  69         default:
  70                 args.usOverscanRight = radeon_crtc->h_border;
  71                 args.usOverscanLeft = radeon_crtc->h_border;
  72                 args.usOverscanBottom = radeon_crtc->v_border;
  73                 args.usOverscanTop = radeon_crtc->v_border;
  74                 break;
  75         }
  76         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
  77 }
  78
  79 static void atombios_scaler_setup(struct drm_crtc *crtc)
  80 {
  81         struct drm_device *dev = crtc->dev;
  82         struct radeon_device *rdev = dev->dev_private;
  83         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
  84         ENABLE_SCALER_PS_ALLOCATION args;
  85         int index = GetIndexIntoMasterTable(COMMAND, EnableScaler);
  86
  87         /* fixme - fill in enc_priv for atom dac */
  88         enum radeon_tv_std tv_std = TV_STD_NTSC;
  89         bool is_tv = false, is_cv = false;
  90         struct drm_encoder *encoder;
  91
  92         if (!ASIC_IS_AVIVO(rdev) && radeon_crtc->crtc_id)
  93                 return;
  94
  95         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
  96                 /* find tv std */
  97                 if (encoder->crtc == crtc) {
  98                         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  99                         if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) {
 100                                 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
 101                                 tv_std = tv_dac->tv_std;
 102                                 is_tv = true;
 103                         }
 104                 }
 105         }
 106
 107         memset(&args, 0, sizeof(args));
 108
 109         args.ucScaler = radeon_crtc->crtc_id;
 110
 111         if (is_tv) {
 112                 switch (tv_std) {
 113                 case TV_STD_NTSC:
 114                 default:
 115                         args.ucTVStandard = ATOM_TV_NTSC;
 116                         break;
 117                 case TV_STD_PAL:
 118                         args.ucTVStandard = ATOM_TV_PAL;
 119                         break;
 120                 case TV_STD_PAL_M:
 121                         args.ucTVStandard = ATOM_TV_PALM;
 122                         break;
 123                 case TV_STD_PAL_60:
 124                         args.ucTVStandard = ATOM_TV_PAL60;
 125                         break;
 126                 case TV_STD_NTSC_J:
 127                         args.ucTVStandard = ATOM_TV_NTSCJ;
 128                         break;
 129                 case TV_STD_SCART_PAL:
 130                         args.ucTVStandard = ATOM_TV_PAL; /* ??? */
 131                         break;
 132                 case TV_STD_SECAM:
 133                         args.ucTVStandard = ATOM_TV_SECAM;
 134                         break;
 135                 case TV_STD_PAL_CN:
 136                         args.ucTVStandard = ATOM_TV_PALCN;
 137                         break;
 138                 }
 139                 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE;
 140         } else if (is_cv) {
 141                 args.ucTVStandard = ATOM_TV_CV;
 142                 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE;
 143         } else {
 144                 switch (radeon_crtc->rmx_type) {
 145                 case RMX_FULL:
 146                         args.ucEnable = ATOM_SCALER_EXPANSION;
 147                         break;
 148                 case RMX_CENTER:
 149                         args.ucEnable = ATOM_SCALER_CENTER;
 150                         break;
 151                 case RMX_ASPECT:
 152                         args.ucEnable = ATOM_SCALER_EXPANSION;
 153                         break;
 154                 default:
 155                         if (ASIC_IS_AVIVO(rdev))
 156                                 args.ucEnable = ATOM_SCALER_DISABLE;
 157                         else
 158                                 args.ucEnable = ATOM_SCALER_CENTER;
 159                         break;
 160                 }
 161         }
 162         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 163         if ((is_tv || is_cv)
 164             && rdev->family >= CHIP_RV515 && rdev->family <= CHIP_R580) {
 165                 atom_rv515_force_tv_scaler(rdev, radeon_crtc);
 166         }
 167 }
 168
 169 static void atombios_lock_crtc(struct drm_crtc *crtc, int lock)
 170 {
 171         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 172         struct drm_device *dev = crtc->dev;
 173         struct radeon_device *rdev = dev->dev_private;
 174         int index =
 175             GetIndexIntoMasterTable(COMMAND, UpdateCRTC_DoubleBufferRegisters);
 176         ENABLE_CRTC_PS_ALLOCATION args;
 177
 178         memset(&args, 0, sizeof(args));
 179
 180         args.ucCRTC = radeon_crtc->crtc_id;
 181         args.ucEnable = lock;
 182
 183         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 184 }
 185
 186 static void atombios_enable_crtc(struct drm_crtc *crtc, int state)
 187 {
 188         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 189         struct drm_device *dev = crtc->dev;
 190         struct radeon_device *rdev = dev->dev_private;
 191         int index = GetIndexIntoMasterTable(COMMAND, EnableCRTC);
 192         ENABLE_CRTC_PS_ALLOCATION args;
 193
 194         memset(&args, 0, sizeof(args));
 195
 196         args.ucCRTC = radeon_crtc->crtc_id;
 197         args.ucEnable = state;
 198
 199         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 200 }
 201
 202 static void atombios_enable_crtc_memreq(struct drm_crtc *crtc, int state)
 203 {
 204         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 205         struct drm_device *dev = crtc->dev;
 206         struct radeon_device *rdev = dev->dev_private;
 207         int index = GetIndexIntoMasterTable(COMMAND, EnableCRTCMemReq);
 208         ENABLE_CRTC_PS_ALLOCATION args;
 209
 210         memset(&args, 0, sizeof(args));
 211
 212         args.ucCRTC = radeon_crtc->crtc_id;
 213         args.ucEnable = state;
 214
 215         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 216 }
 217
 218 static void atombios_blank_crtc(struct drm_crtc *crtc, int state)
 219 {
 220         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 221         struct drm_device *dev = crtc->dev;
 222         struct radeon_device *rdev = dev->dev_private;
 223         int index = GetIndexIntoMasterTable(COMMAND, BlankCRTC);
 224         BLANK_CRTC_PS_ALLOCATION args;
 225
 226         memset(&args, 0, sizeof(args));
 227
 228         args.ucCRTC = radeon_crtc->crtc_id;
 229         args.ucBlanking = state;
 230
 231         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 232 }
 233
 234 void atombios_crtc_dpms(struct drm_crtc *crtc, int mode)
 235 {
 236         struct drm_device *dev = crtc->dev;
 237         struct radeon_device *rdev = dev->dev_private;
 238         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 239
 240         switch (mode) {
 241         case DRM_MODE_DPMS_ON:
 242                 radeon_crtc->enabled = true;
 243                 /* adjust pm to dpms changes BEFORE enabling crtcs */
 244                 radeon_pm_compute_clocks(rdev);
 245                 atombios_enable_crtc(crtc, ATOM_ENABLE);
 246                 if (ASIC_IS_DCE3(rdev))
 247                         atombios_enable_crtc_memreq(crtc, ATOM_ENABLE);
 248                 atombios_blank_crtc(crtc, ATOM_DISABLE);
 249                 drm_vblank_post_modeset(dev, radeon_crtc->crtc_id);
 250                 radeon_crtc_load_lut(crtc);
 251                 break;
 252         case DRM_MODE_DPMS_STANDBY:
 253         case DRM_MODE_DPMS_SUSPEND:
 254         case DRM_MODE_DPMS_OFF:
 255                 drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id);
 256                 if (radeon_crtc->enabled)
 257                         atombios_blank_crtc(crtc, ATOM_ENABLE);
 258                 if (ASIC_IS_DCE3(rdev))
 259                         atombios_enable_crtc_memreq(crtc, ATOM_DISABLE);
 260                 atombios_enable_crtc(crtc, ATOM_DISABLE);
 261                 radeon_crtc->enabled = false;
 262                 /* adjust pm to dpms changes AFTER disabling crtcs */
 263                 radeon_pm_compute_clocks(rdev);
 264                 break;
 265         }
 266 }
 267
 268 static void
 269 atombios_set_crtc_dtd_timing(struct drm_crtc *crtc,
 270                              struct drm_display_mode *mode)
 271 {
 272         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 273         struct drm_device *dev = crtc->dev;
 274         struct radeon_device *rdev = dev->dev_private;
 275         SET_CRTC_USING_DTD_TIMING_PARAMETERS args;
 276         int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_UsingDTDTiming);
 277         u16 misc = 0;
 278
 279         memset(&args, 0, sizeof(args));
 280         args.usH_Size = cpu_to_le16(mode->crtc_hdisplay - (radeon_crtc->h_border * 2));
 281         args.usH_Blanking_Time =
 282                 cpu_to_le16(mode->crtc_hblank_end - mode->crtc_hdisplay + (radeon_crtc->h_border * 2));
 283         args.usV_Size = cpu_to_le16(mode->crtc_vdisplay - (radeon_crtc->v_border * 2));
 284         args.usV_Blanking_Time =
 285                 cpu_to_le16(mode->crtc_vblank_end - mode->crtc_vdisplay + (radeon_crtc->v_border * 2));
 286         args.usH_SyncOffset =
 287                 cpu_to_le16(mode->crtc_hsync_start - mode->crtc_hdisplay + radeon_crtc->h_border);
 288         args.usH_SyncWidth =
 289                 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start);
 290         args.usV_SyncOffset =
 291                 cpu_to_le16(mode->crtc_vsync_start - mode->crtc_vdisplay + radeon_crtc->v_border);
 292         args.usV_SyncWidth =
 293                 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start);
 294         args.ucH_Border = radeon_crtc->h_border;
 295         args.ucV_Border = radeon_crtc->v_border;
 296
 297         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
 298                 misc |= ATOM_VSYNC_POLARITY;
 299         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
 300                 misc |= ATOM_HSYNC_POLARITY;
 301         if (mode->flags & DRM_MODE_FLAG_CSYNC)
 302                 misc |= ATOM_COMPOSITESYNC;
 303         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
 304                 misc |= ATOM_INTERLACE;
 305         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
 306                 misc |= ATOM_DOUBLE_CLOCK_MODE;
 307
 308         args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
 309         args.ucCRTC = radeon_crtc->crtc_id;
 310
 311         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 312 }
 313
 314 static void atombios_crtc_set_timing(struct drm_crtc *crtc,
 315                                      struct drm_display_mode *mode)
 316 {
 317         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 318         struct drm_device *dev = crtc->dev;
 319         struct radeon_device *rdev = dev->dev_private;
 320         SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION args;
 321         int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_Timing);
 322         u16 misc = 0;
 323
 324         memset(&args, 0, sizeof(args));
 325         args.usH_Total = cpu_to_le16(mode->crtc_htotal);
 326         args.usH_Disp = cpu_to_le16(mode->crtc_hdisplay);
 327         args.usH_SyncStart = cpu_to_le16(mode->crtc_hsync_start);
 328         args.usH_SyncWidth =
 329                 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start);
 330         args.usV_Total = cpu_to_le16(mode->crtc_vtotal);
 331         args.usV_Disp = cpu_to_le16(mode->crtc_vdisplay);
 332         args.usV_SyncStart = cpu_to_le16(mode->crtc_vsync_start);
 333         args.usV_SyncWidth =
 334                 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start);
 335
 336         args.ucOverscanRight = radeon_crtc->h_border;
 337         args.ucOverscanLeft = radeon_crtc->h_border;
 338         args.ucOverscanBottom = radeon_crtc->v_border;
 339         args.ucOverscanTop = radeon_crtc->v_border;
 340
 341         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
 342                 misc |= ATOM_VSYNC_POLARITY;
 343         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
 344                 misc |= ATOM_HSYNC_POLARITY;
 345         if (mode->flags & DRM_MODE_FLAG_CSYNC)
 346                 misc |= ATOM_COMPOSITESYNC;
 347         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
 348                 misc |= ATOM_INTERLACE;
 349         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
 350                 misc |= ATOM_DOUBLE_CLOCK_MODE;
 351
 352         args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
 353         args.ucCRTC = radeon_crtc->crtc_id;
 354
 355         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 356 }
 357
 358 static void atombios_disable_ss(struct drm_crtc *crtc)
 359 {
 360         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 361         struct drm_device *dev = crtc->dev;
 362         struct radeon_device *rdev = dev->dev_private;
 363         u32 ss_cntl;
 364
 365         if (ASIC_IS_DCE4(rdev)) {
 366                 switch (radeon_crtc->pll_id) {
 367                 case ATOM_PPLL1:
 368                         ss_cntl = RREG32(EVERGREEN_P1PLL_SS_CNTL);
 369                         ss_cntl &= ~EVERGREEN_PxPLL_SS_EN;
 370                         WREG32(EVERGREEN_P1PLL_SS_CNTL, ss_cntl);
 371                         break;
 372                 case ATOM_PPLL2:
 373                         ss_cntl = RREG32(EVERGREEN_P2PLL_SS_CNTL);
 374                         ss_cntl &= ~EVERGREEN_PxPLL_SS_EN;
 375                         WREG32(EVERGREEN_P2PLL_SS_CNTL, ss_cntl);
 376                         break;
 377                 case ATOM_DCPLL:
 378                 case ATOM_PPLL_INVALID:
 379                         return;
 380                 }
 381         } else if (ASIC_IS_AVIVO(rdev)) {
 382                 switch (radeon_crtc->pll_id) {
 383                 case ATOM_PPLL1:
 384                         ss_cntl = RREG32(AVIVO_P1PLL_INT_SS_CNTL);
 385                         ss_cntl &= ~1;
 386                         WREG32(AVIVO_P1PLL_INT_SS_CNTL, ss_cntl);
 387                         break;
 388                 case ATOM_PPLL2:
 389                         ss_cntl = RREG32(AVIVO_P2PLL_INT_SS_CNTL);
 390                         ss_cntl &= ~1;
 391                         WREG32(AVIVO_P2PLL_INT_SS_CNTL, ss_cntl);
 392                         break;
 393                 case ATOM_DCPLL:
 394                 case ATOM_PPLL_INVALID:
 395                         return;
 396                 }
 397         }
 398 }
 399
 400
 401 union atom_enable_ss {
 402         ENABLE_LVDS_SS_PARAMETERS legacy;
 403         ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION v1;
 404 };
 405
 406 static void atombios_enable_ss(struct drm_crtc *crtc)
 407 {
 408         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 409         struct drm_device *dev = crtc->dev;
 410         struct radeon_device *rdev = dev->dev_private;
 411         struct drm_encoder *encoder = NULL;
 412         struct radeon_encoder *radeon_encoder = NULL;
 413         struct radeon_encoder_atom_dig *dig = NULL;
 414         int index = GetIndexIntoMasterTable(COMMAND, EnableSpreadSpectrumOnPPLL);
 415         union atom_enable_ss args;
 416         uint16_t percentage = 0;
 417         uint8_t type = 0, step = 0, delay = 0, range = 0;
 418
 419         /* XXX add ss support for DCE4 */
 420         if (ASIC_IS_DCE4(rdev))
 421                 return;
 422
 423         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 424                 if (encoder->crtc == crtc) {
 425                         radeon_encoder = to_radeon_encoder(encoder);
 426                         /* only enable spread spectrum on LVDS */
 427                         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
 428                                 dig = radeon_encoder->enc_priv;
 429                                 if (dig && dig->ss) {
 430                                         percentage = dig->ss->percentage;
 431                                         type = dig->ss->type;
 432                                         step = dig->ss->step;
 433                                         delay = dig->ss->delay;
 434                                         range = dig->ss->range;
 435                                 } else
 436                                         return;
 437                         } else
 438                                 return;
 439                         break;
 440                 }
 441         }
 442
 443         if (!radeon_encoder)
 444                 return;
 445
 446         memset(&args, 0, sizeof(args));
 447         if (ASIC_IS_AVIVO(rdev)) {
 448                 args.v1.usSpreadSpectrumPercentage = cpu_to_le16(percentage);
 449                 args.v1.ucSpreadSpectrumType = type;
 450                 args.v1.ucSpreadSpectrumStep = step;
 451                 args.v1.ucSpreadSpectrumDelay = delay;
 452                 args.v1.ucSpreadSpectrumRange = range;
 453                 args.v1.ucPpll = radeon_crtc->crtc_id ? ATOM_PPLL2 : ATOM_PPLL1;
 454                 args.v1.ucEnable = ATOM_ENABLE;
 455         } else {
 456                 args.legacy.usSpreadSpectrumPercentage = cpu_to_le16(percentage);
 457                 args.legacy.ucSpreadSpectrumType = type;
 458                 args.legacy.ucSpreadSpectrumStepSize_Delay = (step & 3) << 2;
 459                 args.legacy.ucSpreadSpectrumStepSize_Delay |= (delay & 7) << 4;
 460                 args.legacy.ucEnable = ATOM_ENABLE;
 461         }
 462         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 463 }
 464
 465 union adjust_pixel_clock {
 466         ADJUST_DISPLAY_PLL_PS_ALLOCATION v1;
 467         ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3 v3;
 468 };
 469
 470 static u32 atombios_adjust_pll(struct drm_crtc *crtc,
 471                                struct drm_display_mode *mode,
 472                                struct radeon_pll *pll)
 473 {
 474         struct drm_device *dev = crtc->dev;
 475         struct radeon_device *rdev = dev->dev_private;
 476         struct drm_encoder *encoder = NULL;
 477         struct radeon_encoder *radeon_encoder = NULL;
 478         u32 adjusted_clock = mode->clock;
 479         int encoder_mode = 0;
 480         u32 dp_clock = mode->clock;
 481         int bpc = 8;
 482
 483         /* reset the pll flags */
 484         pll->flags = 0;
 485
 486         /* select the PLL algo */
 487         if (ASIC_IS_AVIVO(rdev)) {
 488                 if (radeon_new_pll == 0)
 489                         pll->algo = PLL_ALGO_LEGACY;
 490                 else
 491                         pll->algo = PLL_ALGO_NEW;
 492         } else {
 493                 if (radeon_new_pll == 1)
 494                         pll->algo = PLL_ALGO_NEW;
 495                 else
 496                         pll->algo = PLL_ALGO_LEGACY;
 497         }
 498
 499         if (ASIC_IS_AVIVO(rdev)) {
 500                 if ((rdev->family == CHIP_RS600) ||
 501                     (rdev->family == CHIP_RS690) ||
 502                     (rdev->family == CHIP_RS740))
 503                         pll->flags |= (/*RADEON_PLL_USE_FRAC_FB_DIV |*/
 504                                        RADEON_PLL_PREFER_CLOSEST_LOWER);
 505
 506                 if (ASIC_IS_DCE32(rdev) && mode->clock > 200000)        /* range limits??? */
 507                         pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
 508                 else
 509                         pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
 510         } else {
 511                 pll->flags |= RADEON_PLL_LEGACY;
 512
 513                 if (mode->clock > 200000)       /* range limits??? */
 514                         pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
 515                 else
 516                         pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
 517
 518         }
 519
 520         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 521                 if (encoder->crtc == crtc) {
 522                         radeon_encoder = to_radeon_encoder(encoder);
 523                         encoder_mode = atombios_get_encoder_mode(encoder);
 524                         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) {
 525                                 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
 526                                 if (connector) {
 527                                         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 528                                         struct radeon_connector_atom_dig *dig_connector =
 529                                                 radeon_connector->con_priv;
 530
 531                                         dp_clock = dig_connector->dp_clock;
 532                                 }
 533                         }
 534
 535                         if (ASIC_IS_AVIVO(rdev)) {
 536                                 /* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */
 537                                 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1)
 538                                         adjusted_clock = mode->clock * 2;
 539                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) {
 540                                         pll->algo = PLL_ALGO_LEGACY;
 541                                         pll->flags |= RADEON_PLL_PREFER_CLOSEST_LOWER;
 542                                 }
 543                                 /* There is some evidence (often anecdotal) that RV515/RV620 LVDS
 544                                  * (on some boards at least) prefers the legacy algo.  I'm not
 545                                  * sure whether this should handled generically or on a
 546                                  * case-by-case quirk basis.  Both algos should work fine in the
 547                                  * majority of cases.
 548                                  */
 549                                 if ((radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT)) &&
 550                                     ((rdev->family == CHIP_RV515) ||
 551                                      (rdev->family == CHIP_RV620))) {
 552                                         /* allow the user to overrride just in case */
 553                                         if (radeon_new_pll == 1)
 554                                                 pll->algo = PLL_ALGO_NEW;
 555                                         else
 556                                                 pll->algo = PLL_ALGO_LEGACY;
 557                                 }
 558                         } else {
 559                                 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC)
 560                                         pll->flags |= RADEON_PLL_NO_ODD_POST_DIV;
 561                                 if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS)
 562                                         pll->flags |= RADEON_PLL_USE_REF_DIV;
 563                         }
 564                         break;
 565                 }
 566         }
 567
 568         /* DCE3+ has an AdjustDisplayPll that will adjust the pixel clock
 569          * accordingly based on the encoder/transmitter to work around
 570          * special hw requirements.
 571          */
 572         if (ASIC_IS_DCE3(rdev)) {
 573                 union adjust_pixel_clock args;
 574                 u8 frev, crev;
 575                 int index;
 576
 577                 index = GetIndexIntoMasterTable(COMMAND, AdjustDisplayPll);
 578                 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
 579                                            &crev))
 580                         return adjusted_clock;
 581
 582                 memset(&args, 0, sizeof(args));
 583
 584                 switch (frev) {
 585                 case 1:
 586                         switch (crev) {
 587                         case 1:
 588                         case 2:
 589                                 args.v1.usPixelClock = cpu_to_le16(mode->clock / 10);
 590                                 args.v1.ucTransmitterID = radeon_encoder->encoder_id;
 591                                 args.v1.ucEncodeMode = encoder_mode;
 592                                 if (encoder_mode == ATOM_ENCODER_MODE_DP) {
 593                                         /* may want to enable SS on DP eventually */
 594                                         /* args.v1.ucConfig |=
 595                                            ADJUST_DISPLAY_CONFIG_SS_ENABLE;*/
 596                                 } else if (encoder_mode == ATOM_ENCODER_MODE_LVDS) {
 597                                         args.v1.ucConfig |=
 598                                                 ADJUST_DISPLAY_CONFIG_SS_ENABLE;
 599                                 }
 600
 601                                 atom_execute_table(rdev->mode_info.atom_context,
 602                                                    index, (uint32_t *)&args);
 603                                 adjusted_clock = le16_to_cpu(args.v1.usPixelClock) * 10;
 604                                 break;
 605                         case 3:
 606                                 args.v3.sInput.usPixelClock = cpu_to_le16(mode->clock / 10);
 607                                 args.v3.sInput.ucTransmitterID = radeon_encoder->encoder_id;
 608                                 args.v3.sInput.ucEncodeMode = encoder_mode;
 609                                 args.v3.sInput.ucDispPllConfig = 0;
 610                                 if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
 611                                         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 612
 613                                         if (encoder_mode == ATOM_ENCODER_MODE_DP) {
 614                                                 /* may want to enable SS on DP/eDP eventually */
 615                                                 /*args.v3.sInput.ucDispPllConfig |=
 616                                                   DISPPLL_CONFIG_SS_ENABLE;*/
 617                                                 args.v3.sInput.ucDispPllConfig |=
 618                                                         DISPPLL_CONFIG_COHERENT_MODE;
 619                                                 /* 16200 or 27000 */
 620                                                 args.v3.sInput.usPixelClock = cpu_to_le16(dp_clock / 10);
 621                                         } else {
 622                                                 if (encoder_mode == ATOM_ENCODER_MODE_HDMI) {
 623                                                         /* deep color support */
 624                                                         args.v3.sInput.usPixelClock =
 625                                                                 cpu_to_le16((mode->clock * bpc / 8) / 10);
 626                                                 }
 627                                                 if (dig->coherent_mode)
 628                                                         args.v3.sInput.ucDispPllConfig |=
 629                                                                 DISPPLL_CONFIG_COHERENT_MODE;
 630                                                 if (mode->clock > 165000)
 631                                                         args.v3.sInput.ucDispPllConfig |=
 632                                                                 DISPPLL_CONFIG_DUAL_LINK;
 633                                         }
 634                                 } else if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
 635                                         if (encoder_mode == ATOM_ENCODER_MODE_DP) {
 636                                                 /* may want to enable SS on DP/eDP eventually */
 637                                                 /*args.v3.sInput.ucDispPllConfig |=
 638                                                   DISPPLL_CONFIG_SS_ENABLE;*/
 639                                                 args.v3.sInput.ucDispPllConfig |=
 640                                                         DISPPLL_CONFIG_COHERENT_MODE;
 641                                                 /* 16200 or 27000 */
 642                                                 args.v3.sInput.usPixelClock = cpu_to_le16(dp_clock / 10);
 643                                         } else if (encoder_mode == ATOM_ENCODER_MODE_LVDS) {
 644                                                 /* want to enable SS on LVDS eventually */
 645                                                 /*args.v3.sInput.ucDispPllConfig |=
 646                                                   DISPPLL_CONFIG_SS_ENABLE;*/
 647                                         } else {
 648                                                 if (mode->clock > 165000)
 649                                                         args.v3.sInput.ucDispPllConfig |=
 650                                                                 DISPPLL_CONFIG_DUAL_LINK;
 651                                         }
 652                                 }
 653                                 atom_execute_table(rdev->mode_info.atom_context,
 654                                                    index, (uint32_t *)&args);
 655                                 adjusted_clock = le32_to_cpu(args.v3.sOutput.ulDispPllFreq) * 10;
 656                                 if (args.v3.sOutput.ucRefDiv) {
 657                                         pll->flags |= RADEON_PLL_USE_REF_DIV;
 658                                         pll->reference_div = args.v3.sOutput.ucRefDiv;
 659                                 }
 660                                 if (args.v3.sOutput.ucPostDiv) {
 661                                         pll->flags |= RADEON_PLL_USE_POST_DIV;
 662                                         pll->post_div = args.v3.sOutput.ucPostDiv;
 663                                 }
 664                                 break;
 665                         default:
 666                                 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
 667                                 return adjusted_clock;
 668                         }
 669                         break;
 670                 default:
 671                         DRM_ERROR("Unknown table version %d %d\n", frev, crev);
 672                         return adjusted_clock;
 673                 }
 674         }
 675         return adjusted_clock;
 676 }
 677
 678 union set_pixel_clock {
 679         SET_PIXEL_CLOCK_PS_ALLOCATION base;
 680         PIXEL_CLOCK_PARAMETERS v1;
 681         PIXEL_CLOCK_PARAMETERS_V2 v2;
 682         PIXEL_CLOCK_PARAMETERS_V3 v3;
 683         PIXEL_CLOCK_PARAMETERS_V5 v5;
 684 };
 685
 686 static void atombios_crtc_set_dcpll(struct drm_crtc *crtc)
 687 {
 688         struct drm_device *dev = crtc->dev;
 689         struct radeon_device *rdev = dev->dev_private;
 690         u8 frev, crev;
 691         int index;
 692         union set_pixel_clock args;
 693
 694         memset(&args, 0, sizeof(args));
 695
 696         index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
 697         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
 698                                    &crev))
 699                 return;
 700
 701         switch (frev) {
 702         case 1:
 703                 switch (crev) {
 704                 case 5:
 705                         /* if the default dcpll clock is specified,
 706                          * SetPixelClock provides the dividers
 707                          */
 708                         args.v5.ucCRTC = ATOM_CRTC_INVALID;
 709                         args.v5.usPixelClock = rdev->clock.default_dispclk;
 710                         args.v5.ucPpll = ATOM_DCPLL;
 711                         break;
 712                 default:
 713                         DRM_ERROR("Unknown table version %d %d\n", frev, crev);
 714                         return;
 715                 }
 716                 break;
 717         default:
 718                 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
 719                 return;
 720         }
 721         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 722 }
 723
 724 static void atombios_crtc_program_pll(struct drm_crtc *crtc,
 725                                       int crtc_id,
 726                                       int pll_id,
 727                                       u32 encoder_mode,
 728                                       u32 encoder_id,
 729                                       u32 clock,
 730                                       u32 ref_div,
 731                                       u32 fb_div,
 732                                       u32 frac_fb_div,
 733                                       u32 post_div)
 734 {
 735         struct drm_device *dev = crtc->dev;
 736         struct radeon_device *rdev = dev->dev_private;
 737         u8 frev, crev;
 738         int index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
 739         union set_pixel_clock args;
 740
 741         memset(&args, 0, sizeof(args));
 742
 743         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
 744                                    &crev))
 745                 return;
 746
 747         switch (frev) {
 748         case 1:
 749                 switch (crev) {
 750                 case 1:
 751                         if (clock == ATOM_DISABLE)
 752                                 return;
 753                         args.v1.usPixelClock = cpu_to_le16(clock / 10);
 754                         args.v1.usRefDiv = cpu_to_le16(ref_div);
 755                         args.v1.usFbDiv = cpu_to_le16(fb_div);
 756                         args.v1.ucFracFbDiv = frac_fb_div;
 757                         args.v1.ucPostDiv = post_div;
 758                         args.v1.ucPpll = pll_id;
 759                         args.v1.ucCRTC = crtc_id;
 760                         args.v1.ucRefDivSrc = 1;
 761                         break;
 762                 case 2:
 763                         args.v2.usPixelClock = cpu_to_le16(clock / 10);
 764                         args.v2.usRefDiv = cpu_to_le16(ref_div);
 765                         args.v2.usFbDiv = cpu_to_le16(fb_div);
 766                         args.v2.ucFracFbDiv = frac_fb_div;
 767                         args.v2.ucPostDiv = post_div;
 768                         args.v2.ucPpll = pll_id;
 769                         args.v2.ucCRTC = crtc_id;
 770                         args.v2.ucRefDivSrc = 1;
 771                         break;
 772                 case 3:
 773                         args.v3.usPixelClock = cpu_to_le16(clock / 10);
 774                         args.v3.usRefDiv = cpu_to_le16(ref_div);
 775                         args.v3.usFbDiv = cpu_to_le16(fb_div);
 776                         args.v3.ucFracFbDiv = frac_fb_div;
 777                         args.v3.ucPostDiv = post_div;
 778                         args.v3.ucPpll = pll_id;
 779                         args.v3.ucMiscInfo = (pll_id << 2);
 780                         args.v3.ucTransmitterId = encoder_id;
 781                         args.v3.ucEncoderMode = encoder_mode;
 782                         break;
 783                 case 5:
 784                         args.v5.ucCRTC = crtc_id;
 785                         args.v5.usPixelClock = cpu_to_le16(clock / 10);
 786                         args.v5.ucRefDiv = ref_div;
 787                         args.v5.usFbDiv = cpu_to_le16(fb_div);
 788                         args.v5.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000);
 789                         args.v5.ucPostDiv = post_div;
 790                         args.v5.ucMiscInfo = 0; /* HDMI depth, etc. */
 791                         args.v5.ucTransmitterID = encoder_id;
 792                         args.v5.ucEncoderMode = encoder_mode;
 793                         args.v5.ucPpll = pll_id;
 794                         break;
 795                 default:
 796                         DRM_ERROR("Unknown table version %d %d\n", frev, crev);
 797                         return;
 798                 }
 799                 break;
 800         default:
 801                 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
 802                 return;
 803         }
 804
 805         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 806 }
 807
 808 static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
 809 {
 810         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 811         struct drm_device *dev = crtc->dev;
 812         struct radeon_device *rdev = dev->dev_private;
 813         struct drm_encoder *encoder = NULL;
 814         struct radeon_encoder *radeon_encoder = NULL;
 815         u32 pll_clock = mode->clock;
 816         u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0;
 817         struct radeon_pll *pll;
 818         u32 adjusted_clock;
 819         int encoder_mode = 0;
 820
 821         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 822                 if (encoder->crtc == crtc) {
 823                         radeon_encoder = to_radeon_encoder(encoder);
 824                         encoder_mode = atombios_get_encoder_mode(encoder);
 825                         break;
 826                 }
 827         }
 828
 829         if (!radeon_encoder)
 830                 return;
 831
 832         switch (radeon_crtc->pll_id) {
 833         case ATOM_PPLL1:
 834                 pll = &rdev->clock.p1pll;
 835                 break;
 836         case ATOM_PPLL2:
 837                 pll = &rdev->clock.p2pll;
 838                 break;
 839         case ATOM_DCPLL:
 840         case ATOM_PPLL_INVALID:
 841         default:
 842                 pll = &rdev->clock.dcpll;
 843                 break;
 844         }
 845
 846         /* adjust pixel clock as needed */
 847         adjusted_clock = atombios_adjust_pll(crtc, mode, pll);
 848
 849         radeon_compute_pll(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div,
 850                            &ref_div, &post_div);
 851
 852         atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
 853                                   encoder_mode, radeon_encoder->encoder_id, mode->clock,
 854                                   ref_div, fb_div, frac_fb_div, post_div);
 855
 856 }
 857
 858 static int evergreen_crtc_set_base(struct drm_crtc *crtc, int x, int y,
 859                                    struct drm_framebuffer *old_fb)
 860 {
 861         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 862         struct drm_device *dev = crtc->dev;
 863         struct radeon_device *rdev = dev->dev_private;
 864         struct radeon_framebuffer *radeon_fb;
 865         struct drm_gem_object *obj;
 866         struct radeon_bo *rbo;
 867         uint64_t fb_location;
 868         uint32_t fb_format, fb_pitch_pixels, tiling_flags;
 869         int r;
 870
 871         /* no fb bound */
 872         if (!crtc->fb) {
 873                 DRM_DEBUG_KMS("No FB bound\n");
 874                 return 0;
 875         }
 876
 877         radeon_fb = to_radeon_framebuffer(crtc->fb);
 878
 879         /* Pin framebuffer & get tilling informations */
 880         obj = radeon_fb->obj;
 881         rbo = obj->driver_private;
 882         r = radeon_bo_reserve(rbo, false);
 883         if (unlikely(r != 0))
 884                 return r;
 885         r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location);
 886         if (unlikely(r != 0)) {
 887                 radeon_bo_unreserve(rbo);
 888                 return -EINVAL;
 889         }
 890         radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
 891         radeon_bo_unreserve(rbo);
 892
 893         switch (crtc->fb->bits_per_pixel) {
 894         case 8:
 895                 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_8BPP) |
 896                              EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_INDEXED));
 897                 break;
 898         case 15:
 899                 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
 900                              EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB1555));
 901                 break;
 902         case 16:
 903                 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
 904                              EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB565));
 905                 break;
 906         case 24:
 907         case 32:
 908                 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) |
 909                              EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB8888));
 910                 break;
 911         default:
 912                 DRM_ERROR("Unsupported screen depth %d\n",
 913                           crtc->fb->bits_per_pixel);
 914                 return -EINVAL;
 915         }
 916
 917         if (tiling_flags & RADEON_TILING_MACRO)
 918                 fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_2D_TILED_THIN1);
 919         else if (tiling_flags & RADEON_TILING_MICRO)
 920                 fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_1D_TILED_THIN1);
 921
 922         switch (radeon_crtc->crtc_id) {
 923         case 0:
 924                 WREG32(AVIVO_D1VGA_CONTROL, 0);
 925                 break;
 926         case 1:
 927                 WREG32(AVIVO_D2VGA_CONTROL, 0);
 928                 break;
 929         case 2:
 930                 WREG32(EVERGREEN_D3VGA_CONTROL, 0);
 931                 break;
 932         case 3:
 933                 WREG32(EVERGREEN_D4VGA_CONTROL, 0);
 934                 break;
 935         case 4:
 936                 WREG32(EVERGREEN_D5VGA_CONTROL, 0);
 937                 break;
 938         case 5:
 939                 WREG32(EVERGREEN_D6VGA_CONTROL, 0);
 940                 break;
 941         default:
 942                 break;
 943         }
 944
 945         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
 946                upper_32_bits(fb_location));
 947         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
 948                upper_32_bits(fb_location));
 949         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
 950                (u32)fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK);
 951         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
 952                (u32) fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK);
 953         WREG32(EVERGREEN_GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
 954
 955         WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
 956         WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
 957         WREG32(EVERGREEN_GRPH_X_START + radeon_crtc->crtc_offset, 0);
 958         WREG32(EVERGREEN_GRPH_Y_START + radeon_crtc->crtc_offset, 0);
 959         WREG32(EVERGREEN_GRPH_X_END + radeon_crtc->crtc_offset, crtc->fb->width);
 960         WREG32(EVERGREEN_GRPH_Y_END + radeon_crtc->crtc_offset, crtc->fb->height);
 961
 962         fb_pitch_pixels = crtc->fb->pitch / (crtc->fb->bits_per_pixel / 8);
 963         WREG32(EVERGREEN_GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
 964         WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
 965
 966         WREG32(EVERGREEN_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
 967                crtc->mode.vdisplay);
 968         x &= ~3;
 969         y &= ~1;
 970         WREG32(EVERGREEN_VIEWPORT_START + radeon_crtc->crtc_offset,
 971                (x << 16) | y);
 972         WREG32(EVERGREEN_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
 973                (crtc->mode.hdisplay << 16) | crtc->mode.vdisplay);
 974
 975         if (crtc->mode.flags & DRM_MODE_FLAG_INTERLACE)
 976                 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset,
 977                        EVERGREEN_INTERLEAVE_EN);
 978         else
 979                 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
 980
 981         if (old_fb && old_fb != crtc->fb) {
 982                 radeon_fb = to_radeon_framebuffer(old_fb);
 983                 rbo = radeon_fb->obj->driver_private;
 984                 r = radeon_bo_reserve(rbo, false);
 985                 if (unlikely(r != 0))
 986                         return r;
 987                 radeon_bo_unpin(rbo);
 988                 radeon_bo_unreserve(rbo);
 989         }
 990
 991         /* Bytes per pixel may have changed */
 992         radeon_bandwidth_update(rdev);
 993
 994         return 0;
 995 }
 996
 997 static int avivo_crtc_set_base(struct drm_crtc *crtc, int x, int y,
 998                                struct drm_framebuffer *old_fb)
 999 {
1000         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1001         struct drm_device *dev = crtc->dev;
1002         struct radeon_device *rdev = dev->dev_private;
1003         struct radeon_framebuffer *radeon_fb;
1004         struct drm_gem_object *obj;
1005         struct radeon_bo *rbo;
1006         uint64_t fb_location;
1007         uint32_t fb_format, fb_pitch_pixels, tiling_flags;
1008         int r;
1009
1010         /* no fb bound */
1011         if (!crtc->fb) {
1012                 DRM_DEBUG_KMS("No FB bound\n");
1013                 return 0;
1014         }
1015
1016         radeon_fb = to_radeon_framebuffer(crtc->fb);
1017
1018         /* Pin framebuffer & get tilling informations */
1019         obj = radeon_fb->obj;
1020         rbo = obj->driver_private;
1021         r = radeon_bo_reserve(rbo, false);
1022         if (unlikely(r != 0))
1023                 return r;
1024         r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location);
1025         if (unlikely(r != 0)) {
1026                 radeon_bo_unreserve(rbo);
1027                 return -EINVAL;
1028         }
1029         radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
1030         radeon_bo_unreserve(rbo);
1031
1032         switch (crtc->fb->bits_per_pixel) {
1033         case 8:
1034                 fb_format =
1035                     AVIVO_D1GRPH_CONTROL_DEPTH_8BPP |
1036                     AVIVO_D1GRPH_CONTROL_8BPP_INDEXED;
1037                 break;
1038         case 15:
1039                 fb_format =
1040                     AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
1041                     AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555;
1042                 break;
1043         case 16:
1044                 fb_format =
1045                     AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
1046                     AVIVO_D1GRPH_CONTROL_16BPP_RGB565;
1047                 break;
1048         case 24:
1049         case 32:
1050                 fb_format =
1051                     AVIVO_D1GRPH_CONTROL_DEPTH_32BPP |
1052                     AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888;
1053                 break;
1054         default:
1055                 DRM_ERROR("Unsupported screen depth %d\n",
1056                           crtc->fb->bits_per_pixel);
1057                 return -EINVAL;
1058         }
1059
1060         if (rdev->family >= CHIP_R600) {
1061                 if (tiling_flags & RADEON_TILING_MACRO)
1062                         fb_format |= R600_D1GRPH_ARRAY_MODE_2D_TILED_THIN1;
1063                 else if (tiling_flags & RADEON_TILING_MICRO)
1064                         fb_format |= R600_D1GRPH_ARRAY_MODE_1D_TILED_THIN1;
1065         } else {
1066                 if (tiling_flags & RADEON_TILING_MACRO)
1067                         fb_format |= AVIVO_D1GRPH_MACRO_ADDRESS_MODE;
1068
1069                 if (tiling_flags & RADEON_TILING_MICRO)
1070                         fb_format |= AVIVO_D1GRPH_TILED;
1071         }
1072
1073         if (radeon_crtc->crtc_id == 0)
1074                 WREG32(AVIVO_D1VGA_CONTROL, 0);
1075         else
1076                 WREG32(AVIVO_D2VGA_CONTROL, 0);
1077
1078         if (rdev->family >= CHIP_RV770) {
1079                 if (radeon_crtc->crtc_id) {
1080                         WREG32(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1081                         WREG32(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1082                 } else {
1083                         WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1084                         WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1085                 }
1086         }
1087         WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
1088                (u32) fb_location);
1089         WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS +
1090                radeon_crtc->crtc_offset, (u32) fb_location);
1091         WREG32(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
1092
1093         WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
1094         WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
1095         WREG32(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, 0);
1096         WREG32(AVIVO_D1GRPH_Y_START + radeon_crtc->crtc_offset, 0);
1097         WREG32(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, crtc->fb->width);
1098         WREG32(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, crtc->fb->height);
1099
1100         fb_pitch_pixels = crtc->fb->pitch / (crtc->fb->bits_per_pixel / 8);
1101         WREG32(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
1102         WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
1103
1104         WREG32(AVIVO_D1MODE_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
1105                crtc->mode.vdisplay);
1106         x &= ~3;
1107         y &= ~1;
1108         WREG32(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset,
1109                (x << 16) | y);
1110         WREG32(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
1111                (crtc->mode.hdisplay << 16) | crtc->mode.vdisplay);
1112
1113         if (crtc->mode.flags & DRM_MODE_FLAG_INTERLACE)
1114                 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
1115                        AVIVO_D1MODE_INTERLEAVE_EN);
1116         else
1117                 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
1118
1119         if (old_fb && old_fb != crtc->fb) {
1120                 radeon_fb = to_radeon_framebuffer(old_fb);
1121                 rbo = radeon_fb->obj->driver_private;
1122                 r = radeon_bo_reserve(rbo, false);
1123                 if (unlikely(r != 0))
1124                         return r;
1125                 radeon_bo_unpin(rbo);
1126                 radeon_bo_unreserve(rbo);
1127         }
1128
1129         /* Bytes per pixel may have changed */
1130         radeon_bandwidth_update(rdev);
1131
1132         return 0;
1133 }
1134
1135 int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
1136                            struct drm_framebuffer *old_fb)
1137 {
1138         struct drm_device *dev = crtc->dev;
1139         struct radeon_device *rdev = dev->dev_private;
1140
1141         if (ASIC_IS_DCE4(rdev))
1142                 return evergreen_crtc_set_base(crtc, x, y, old_fb);
1143         else if (ASIC_IS_AVIVO(rdev))
1144                 return avivo_crtc_set_base(crtc, x, y, old_fb);
1145         else
1146                 return radeon_crtc_set_base(crtc, x, y, old_fb);
1147 }
1148
1149 /* properly set additional regs when using atombios */
1150 static void radeon_legacy_atom_fixup(struct drm_crtc *crtc)
1151 {
1152         struct drm_device *dev = crtc->dev;
1153         struct radeon_device *rdev = dev->dev_private;
1154         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1155         u32 disp_merge_cntl;
1156
1157         switch (radeon_crtc->crtc_id) {
1158         case 0:
1159                 disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL);
1160                 disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN;
1161                 WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl);
1162                 break;
1163         case 1:
1164                 disp_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL);
1165                 disp_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN;
1166                 WREG32(RADEON_DISP2_MERGE_CNTL, disp_merge_cntl);
1167                 WREG32(RADEON_FP_H2_SYNC_STRT_WID,   RREG32(RADEON_CRTC2_H_SYNC_STRT_WID));
1168                 WREG32(RADEON_FP_V2_SYNC_STRT_WID,   RREG32(RADEON_CRTC2_V_SYNC_STRT_WID));
1169                 break;
1170         }
1171 }
1172
1173 static int radeon_atom_pick_pll(struct drm_crtc *crtc)
1174 {
1175         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1176         struct drm_device *dev = crtc->dev;
1177         struct radeon_device *rdev = dev->dev_private;
1178         struct drm_encoder *test_encoder;
1179         struct drm_crtc *test_crtc;
1180         uint32_t pll_in_use = 0;
1181
1182         if (ASIC_IS_DCE4(rdev)) {
1183                 /* if crtc is driving DP and we have an ext clock, use that */
1184                 list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
1185                         if (test_encoder->crtc && (test_encoder->crtc == crtc)) {
1186                                 if (atombios_get_encoder_mode(test_encoder) == ATOM_ENCODER_MODE_DP) {
1187                                         if (rdev->clock.dp_extclk)
1188                                                 return ATOM_PPLL_INVALID;
1189                                 }
1190                         }
1191                 }
1192
1193                 /* otherwise, pick one of the plls */
1194                 list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) {
1195                         struct radeon_crtc *radeon_test_crtc;
1196
1197                         if (crtc == test_crtc)
1198                                 continue;
1199
1200                         radeon_test_crtc = to_radeon_crtc(test_crtc);
1201                         if ((radeon_test_crtc->pll_id >= ATOM_PPLL1) &&
1202                             (radeon_test_crtc->pll_id <= ATOM_PPLL2))
1203                                 pll_in_use |= (1 << radeon_test_crtc->pll_id);
1204                 }
1205                 if (!(pll_in_use & 1))
1206                         return ATOM_PPLL1;
1207                 return ATOM_PPLL2;
1208         } else
1209                 return radeon_crtc->crtc_id;
1210
1211 }
1212
1213 int atombios_crtc_mode_set(struct drm_crtc *crtc,
1214                            struct drm_display_mode *mode,
1215                            struct drm_display_mode *adjusted_mode,
1216                            int x, int y, struct drm_framebuffer *old_fb)
1217 {
1218         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1219         struct drm_device *dev = crtc->dev;
1220         struct radeon_device *rdev = dev->dev_private;
1221         struct drm_encoder *encoder;
1222         bool is_tvcv = false;
1223
1224         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1225                 /* find tv std */
1226                 if (encoder->crtc == crtc) {
1227                         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1228                         if (radeon_encoder->active_device &
1229                             (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
1230                                 is_tvcv = true;
1231                 }
1232         }
1233
1234         atombios_disable_ss(crtc);
1235         /* always set DCPLL */
1236         if (ASIC_IS_DCE4(rdev))
1237                 atombios_crtc_set_dcpll(crtc);
1238         atombios_crtc_set_pll(crtc, adjusted_mode);
1239         atombios_enable_ss(crtc);
1240
1241         if (ASIC_IS_DCE4(rdev))
1242                 atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
1243         else if (ASIC_IS_AVIVO(rdev)) {
1244                 if (is_tvcv)
1245                         atombios_crtc_set_timing(crtc, adjusted_mode);
1246                 else
1247                         atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
1248         } else {
1249                 atombios_crtc_set_timing(crtc, adjusted_mode);
1250                 if (radeon_crtc->crtc_id == 0)
1251                         atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
1252                 radeon_legacy_atom_fixup(crtc);
1253         }
1254         atombios_crtc_set_base(crtc, x, y, old_fb);
1255         atombios_overscan_setup(crtc, mode, adjusted_mode);
1256         atombios_scaler_setup(crtc);
1257         return 0;
1258 }
1259
1260 static bool atombios_crtc_mode_fixup(struct drm_crtc *crtc,
1261                                      struct drm_display_mode *mode,
1262                                      struct drm_display_mode *adjusted_mode)
1263 {
1264         struct drm_device *dev = crtc->dev;
1265         struct radeon_device *rdev = dev->dev_private;
1266
1267         /* adjust pm to upcoming mode change */
1268         radeon_pm_compute_clocks(rdev);
1269
1270         if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
1271                 return false;
1272         return true;
1273 }
1274
1275 static void atombios_crtc_prepare(struct drm_crtc *crtc)
1276 {
1277         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1278
1279         /* pick pll */
1280         radeon_crtc->pll_id = radeon_atom_pick_pll(crtc);
1281
1282         atombios_lock_crtc(crtc, ATOM_ENABLE);
1283         atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
1284 }
1285
1286 static void atombios_crtc_commit(struct drm_crtc *crtc)
1287 {
1288         atombios_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
1289         atombios_lock_crtc(crtc, ATOM_DISABLE);
1290 }
1291
1292 static void atombios_crtc_disable(struct drm_crtc *crtc)
1293 {
1294         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1295         atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
1296
1297         switch (radeon_crtc->pll_id) {
1298         case ATOM_PPLL1:
1299         case ATOM_PPLL2:
1300                 /* disable the ppll */
1301                 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
1302                                           0, 0, ATOM_DISABLE, 0, 0, 0, 0);
1303                 break;
1304         default:
1305                 break;
1306         }
1307         radeon_crtc->pll_id = -1;
1308 }
1309
1310 static const struct drm_crtc_helper_funcs atombios_helper_funcs = {
1311         .dpms = atombios_crtc_dpms,
1312         .mode_fixup = atombios_crtc_mode_fixup,
1313         .mode_set = atombios_crtc_mode_set,
1314         .mode_set_base = atombios_crtc_set_base,
1315         .prepare = atombios_crtc_prepare,
1316         .commit = atombios_crtc_commit,
1317         .load_lut = radeon_crtc_load_lut,
1318         .disable = atombios_crtc_disable,
1319 };
1320
1321 void radeon_atombios_init_crtc(struct drm_device *dev,
1322                                struct radeon_crtc *radeon_crtc)
1323 {
1324         struct radeon_device *rdev = dev->dev_private;
1325
1326         if (ASIC_IS_DCE4(rdev)) {
1327                 switch (radeon_crtc->crtc_id) {
1328                 case 0:
1329                 default:
1330                         radeon_crtc->crtc_offset = EVERGREEN_CRTC0_REGISTER_OFFSET;
1331                         break;
1332                 case 1:
1333                         radeon_crtc->crtc_offset = EVERGREEN_CRTC1_REGISTER_OFFSET;
1334                         break;
1335                 case 2:
1336                         radeon_crtc->crtc_offset = EVERGREEN_CRTC2_REGISTER_OFFSET;
1337                         break;
1338                 case 3:
1339                         radeon_crtc->crtc_offset = EVERGREEN_CRTC3_REGISTER_OFFSET;
1340                         break;
1341                 case 4:
1342                         radeon_crtc->crtc_offset = EVERGREEN_CRTC4_REGISTER_OFFSET;
1343                         break;
1344                 case 5:
1345                         radeon_crtc->crtc_offset = EVERGREEN_CRTC5_REGISTER_OFFSET;
1346                         break;
1347                 }
1348         } else {
1349                 if (radeon_crtc->crtc_id == 1)
1350                         radeon_crtc->crtc_offset =
1351                                 AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL;
1352                 else
1353                         radeon_crtc->crtc_offset = 0;
1354         }
1355         radeon_crtc->pll_id = -1;
1356         drm_crtc_helper_add(&radeon_crtc->base, &atombios_helper_funcs);
1357 }