drivers/gpu/drm/radeon/atombios_crtc.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include <drm/drmP.h>
  27 #include <drm/drm_crtc_helper.h>
  28 #include <drm/radeon_drm.h>
  29 #include <drm/drm_fixed.h>
  30 #include "radeon.h"
  31 #include "atom.h"
  32 #include "atom-bits.h"
  33
  34 static void atombios_overscan_setup(struct drm_crtc *crtc,
  35                                     struct drm_display_mode *mode,
  36                                     struct drm_display_mode *adjusted_mode)
  37 {
  38         struct drm_device *dev = crtc->dev;
  39         struct radeon_device *rdev = dev->dev_private;
  40         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
  41         SET_CRTC_OVERSCAN_PS_ALLOCATION args;
  42         int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_OverScan);
  43         int a1, a2;
  44
  45         memset(&args, 0, sizeof(args));
  46
  47         args.ucCRTC = radeon_crtc->crtc_id;
  48
  49         switch (radeon_crtc->rmx_type) {
  50         case RMX_CENTER:
  51                 args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2);
  52                 args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2);
  53                 args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2);
  54                 args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2);
  55                 break;
  56         case RMX_ASPECT:
  57                 a1 = mode->crtc_vdisplay * adjusted_mode->crtc_hdisplay;
  58                 a2 = adjusted_mode->crtc_vdisplay * mode->crtc_hdisplay;
  59
  60                 if (a1 > a2) {
  61                         args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2);
  62                         args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2);
  63                 } else if (a2 > a1) {
  64                         args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2);
  65                         args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2);
  66                 }
  67                 break;
  68         case RMX_FULL:
  69         default:
  70                 args.usOverscanRight = cpu_to_le16(radeon_crtc->h_border);
  71                 args.usOverscanLeft = cpu_to_le16(radeon_crtc->h_border);
  72                 args.usOverscanBottom = cpu_to_le16(radeon_crtc->v_border);
  73                 args.usOverscanTop = cpu_to_le16(radeon_crtc->v_border);
  74                 break;
  75         }
  76         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
  77 }
  78
  79 static void atombios_scaler_setup(struct drm_crtc *crtc)
  80 {
  81         struct drm_device *dev = crtc->dev;
  82         struct radeon_device *rdev = dev->dev_private;
  83         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
  84         ENABLE_SCALER_PS_ALLOCATION args;
  85         int index = GetIndexIntoMasterTable(COMMAND, EnableScaler);
  86
  87         /* fixme - fill in enc_priv for atom dac */
  88         enum radeon_tv_std tv_std = TV_STD_NTSC;
  89         bool is_tv = false, is_cv = false;
  90         struct drm_encoder *encoder;
  91
  92         if (!ASIC_IS_AVIVO(rdev) && radeon_crtc->crtc_id)
  93                 return;
  94
  95         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
  96                 /* find tv std */
  97                 if (encoder->crtc == crtc) {
  98                         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  99                         if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) {
 100                                 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
 101                                 tv_std = tv_dac->tv_std;
 102                                 is_tv = true;
 103                         }
 104                 }
 105         }
 106
 107         memset(&args, 0, sizeof(args));
 108
 109         args.ucScaler = radeon_crtc->crtc_id;
 110
 111         if (is_tv) {
 112                 switch (tv_std) {
 113                 case TV_STD_NTSC:
 114                 default:
 115                         args.ucTVStandard = ATOM_TV_NTSC;
 116                         break;
 117                 case TV_STD_PAL:
 118                         args.ucTVStandard = ATOM_TV_PAL;
 119                         break;
 120                 case TV_STD_PAL_M:
 121                         args.ucTVStandard = ATOM_TV_PALM;
 122                         break;
 123                 case TV_STD_PAL_60:
 124                         args.ucTVStandard = ATOM_TV_PAL60;
 125                         break;
 126                 case TV_STD_NTSC_J:
 127                         args.ucTVStandard = ATOM_TV_NTSCJ;
 128                         break;
 129                 case TV_STD_SCART_PAL:
 130                         args.ucTVStandard = ATOM_TV_PAL; /* ??? */
 131                         break;
 132                 case TV_STD_SECAM:
 133                         args.ucTVStandard = ATOM_TV_SECAM;
 134                         break;
 135                 case TV_STD_PAL_CN:
 136                         args.ucTVStandard = ATOM_TV_PALCN;
 137                         break;
 138                 }
 139                 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE;
 140         } else if (is_cv) {
 141                 args.ucTVStandard = ATOM_TV_CV;
 142                 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE;
 143         } else {
 144                 switch (radeon_crtc->rmx_type) {
 145                 case RMX_FULL:
 146                         args.ucEnable = ATOM_SCALER_EXPANSION;
 147                         break;
 148                 case RMX_CENTER:
 149                         args.ucEnable = ATOM_SCALER_CENTER;
 150                         break;
 151                 case RMX_ASPECT:
 152                         args.ucEnable = ATOM_SCALER_EXPANSION;
 153                         break;
 154                 default:
 155                         if (ASIC_IS_AVIVO(rdev))
 156                                 args.ucEnable = ATOM_SCALER_DISABLE;
 157                         else
 158                                 args.ucEnable = ATOM_SCALER_CENTER;
 159                         break;
 160                 }
 161         }
 162         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 163         if ((is_tv || is_cv)
 164             && rdev->family >= CHIP_RV515 && rdev->family <= CHIP_R580) {
 165                 atom_rv515_force_tv_scaler(rdev, radeon_crtc);
 166         }
 167 }
 168
 169 static void atombios_lock_crtc(struct drm_crtc *crtc, int lock)
 170 {
 171         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 172         struct drm_device *dev = crtc->dev;
 173         struct radeon_device *rdev = dev->dev_private;
 174         int index =
 175             GetIndexIntoMasterTable(COMMAND, UpdateCRTC_DoubleBufferRegisters);
 176         ENABLE_CRTC_PS_ALLOCATION args;
 177
 178         memset(&args, 0, sizeof(args));
 179
 180         args.ucCRTC = radeon_crtc->crtc_id;
 181         args.ucEnable = lock;
 182
 183         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 184 }
 185
 186 static void atombios_enable_crtc(struct drm_crtc *crtc, int state)
 187 {
 188         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 189         struct drm_device *dev = crtc->dev;
 190         struct radeon_device *rdev = dev->dev_private;
 191         int index = GetIndexIntoMasterTable(COMMAND, EnableCRTC);
 192         ENABLE_CRTC_PS_ALLOCATION args;
 193
 194         memset(&args, 0, sizeof(args));
 195
 196         args.ucCRTC = radeon_crtc->crtc_id;
 197         args.ucEnable = state;
 198
 199         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 200 }
 201
 202 static void atombios_enable_crtc_memreq(struct drm_crtc *crtc, int state)
 203 {
 204         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 205         struct drm_device *dev = crtc->dev;
 206         struct radeon_device *rdev = dev->dev_private;
 207         int index = GetIndexIntoMasterTable(COMMAND, EnableCRTCMemReq);
 208         ENABLE_CRTC_PS_ALLOCATION args;
 209
 210         memset(&args, 0, sizeof(args));
 211
 212         args.ucCRTC = radeon_crtc->crtc_id;
 213         args.ucEnable = state;
 214
 215         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 216 }
 217
 218 static void atombios_blank_crtc(struct drm_crtc *crtc, int state)
 219 {
 220         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 221         struct drm_device *dev = crtc->dev;
 222         struct radeon_device *rdev = dev->dev_private;
 223         int index = GetIndexIntoMasterTable(COMMAND, BlankCRTC);
 224         BLANK_CRTC_PS_ALLOCATION args;
 225
 226         memset(&args, 0, sizeof(args));
 227
 228         args.ucCRTC = radeon_crtc->crtc_id;
 229         args.ucBlanking = state;
 230
 231         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 232 }
 233
 234 static void atombios_powergate_crtc(struct drm_crtc *crtc, int state)
 235 {
 236         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 237         struct drm_device *dev = crtc->dev;
 238         struct radeon_device *rdev = dev->dev_private;
 239         int index = GetIndexIntoMasterTable(COMMAND, EnableDispPowerGating);
 240         ENABLE_DISP_POWER_GATING_PARAMETERS_V2_1 args;
 241
 242         memset(&args, 0, sizeof(args));
 243
 244         args.ucDispPipeId = radeon_crtc->crtc_id;
 245         args.ucEnable = state;
 246
 247         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 248 }
 249
 250 void atombios_crtc_dpms(struct drm_crtc *crtc, int mode)
 251 {
 252         struct drm_device *dev = crtc->dev;
 253         struct radeon_device *rdev = dev->dev_private;
 254         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 255
 256         switch (mode) {
 257         case DRM_MODE_DPMS_ON:
 258                 radeon_crtc->enabled = true;
 259                 /* adjust pm to dpms changes BEFORE enabling crtcs */
 260                 radeon_pm_compute_clocks(rdev);
 261                 if (ASIC_IS_DCE6(rdev) && !radeon_crtc->in_mode_set)
 262                         atombios_powergate_crtc(crtc, ATOM_DISABLE);
 263                 atombios_enable_crtc(crtc, ATOM_ENABLE);
 264                 if (ASIC_IS_DCE3(rdev) && !ASIC_IS_DCE6(rdev))
 265                         atombios_enable_crtc_memreq(crtc, ATOM_ENABLE);
 266                 atombios_blank_crtc(crtc, ATOM_DISABLE);
 267                 drm_vblank_post_modeset(dev, radeon_crtc->crtc_id);
 268                 radeon_crtc_load_lut(crtc);
 269                 break;
 270         case DRM_MODE_DPMS_STANDBY:
 271         case DRM_MODE_DPMS_SUSPEND:
 272         case DRM_MODE_DPMS_OFF:
 273                 drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id);
 274                 if (radeon_crtc->enabled)
 275                         atombios_blank_crtc(crtc, ATOM_ENABLE);
 276                 if (ASIC_IS_DCE3(rdev) && !ASIC_IS_DCE6(rdev))
 277                         atombios_enable_crtc_memreq(crtc, ATOM_DISABLE);
 278                 atombios_enable_crtc(crtc, ATOM_DISABLE);
 279                 radeon_crtc->enabled = false;
 280                 if (ASIC_IS_DCE6(rdev) && !radeon_crtc->in_mode_set)
 281                         atombios_powergate_crtc(crtc, ATOM_ENABLE);
 282                 /* adjust pm to dpms changes AFTER disabling crtcs */
 283                 radeon_pm_compute_clocks(rdev);
 284                 break;
 285         }
 286 }
 287
 288 static void
 289 atombios_set_crtc_dtd_timing(struct drm_crtc *crtc,
 290                              struct drm_display_mode *mode)
 291 {
 292         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 293         struct drm_device *dev = crtc->dev;
 294         struct radeon_device *rdev = dev->dev_private;
 295         SET_CRTC_USING_DTD_TIMING_PARAMETERS args;
 296         int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_UsingDTDTiming);
 297         u16 misc = 0;
 298
 299         memset(&args, 0, sizeof(args));
 300         args.usH_Size = cpu_to_le16(mode->crtc_hdisplay - (radeon_crtc->h_border * 2));
 301         args.usH_Blanking_Time =
 302                 cpu_to_le16(mode->crtc_hblank_end - mode->crtc_hdisplay + (radeon_crtc->h_border * 2));
 303         args.usV_Size = cpu_to_le16(mode->crtc_vdisplay - (radeon_crtc->v_border * 2));
 304         args.usV_Blanking_Time =
 305                 cpu_to_le16(mode->crtc_vblank_end - mode->crtc_vdisplay + (radeon_crtc->v_border * 2));
 306         args.usH_SyncOffset =
 307                 cpu_to_le16(mode->crtc_hsync_start - mode->crtc_hdisplay + radeon_crtc->h_border);
 308         args.usH_SyncWidth =
 309                 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start);
 310         args.usV_SyncOffset =
 311                 cpu_to_le16(mode->crtc_vsync_start - mode->crtc_vdisplay + radeon_crtc->v_border);
 312         args.usV_SyncWidth =
 313                 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start);
 314         args.ucH_Border = radeon_crtc->h_border;
 315         args.ucV_Border = radeon_crtc->v_border;
 316
 317         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
 318                 misc |= ATOM_VSYNC_POLARITY;
 319         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
 320                 misc |= ATOM_HSYNC_POLARITY;
 321         if (mode->flags & DRM_MODE_FLAG_CSYNC)
 322                 misc |= ATOM_COMPOSITESYNC;
 323         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
 324                 misc |= ATOM_INTERLACE;
 325         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
 326                 misc |= ATOM_DOUBLE_CLOCK_MODE;
 327
 328         args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
 329         args.ucCRTC = radeon_crtc->crtc_id;
 330
 331         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 332 }
 333
 334 static void atombios_crtc_set_timing(struct drm_crtc *crtc,
 335                                      struct drm_display_mode *mode)
 336 {
 337         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 338         struct drm_device *dev = crtc->dev;
 339         struct radeon_device *rdev = dev->dev_private;
 340         SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION args;
 341         int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_Timing);
 342         u16 misc = 0;
 343
 344         memset(&args, 0, sizeof(args));
 345         args.usH_Total = cpu_to_le16(mode->crtc_htotal);
 346         args.usH_Disp = cpu_to_le16(mode->crtc_hdisplay);
 347         args.usH_SyncStart = cpu_to_le16(mode->crtc_hsync_start);
 348         args.usH_SyncWidth =
 349                 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start);
 350         args.usV_Total = cpu_to_le16(mode->crtc_vtotal);
 351         args.usV_Disp = cpu_to_le16(mode->crtc_vdisplay);
 352         args.usV_SyncStart = cpu_to_le16(mode->crtc_vsync_start);
 353         args.usV_SyncWidth =
 354                 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start);
 355
 356         args.ucOverscanRight = radeon_crtc->h_border;
 357         args.ucOverscanLeft = radeon_crtc->h_border;
 358         args.ucOverscanBottom = radeon_crtc->v_border;
 359         args.ucOverscanTop = radeon_crtc->v_border;
 360
 361         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
 362                 misc |= ATOM_VSYNC_POLARITY;
 363         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
 364                 misc |= ATOM_HSYNC_POLARITY;
 365         if (mode->flags & DRM_MODE_FLAG_CSYNC)
 366                 misc |= ATOM_COMPOSITESYNC;
 367         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
 368                 misc |= ATOM_INTERLACE;
 369         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
 370                 misc |= ATOM_DOUBLE_CLOCK_MODE;
 371
 372         args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
 373         args.ucCRTC = radeon_crtc->crtc_id;
 374
 375         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 376 }
 377
 378 static void atombios_disable_ss(struct radeon_device *rdev, int pll_id)
 379 {
 380         u32 ss_cntl;
 381
 382         if (ASIC_IS_DCE4(rdev)) {
 383                 switch (pll_id) {
 384                 case ATOM_PPLL1:
 385                         ss_cntl = RREG32(EVERGREEN_P1PLL_SS_CNTL);
 386                         ss_cntl &= ~EVERGREEN_PxPLL_SS_EN;
 387                         WREG32(EVERGREEN_P1PLL_SS_CNTL, ss_cntl);
 388                         break;
 389                 case ATOM_PPLL2:
 390                         ss_cntl = RREG32(EVERGREEN_P2PLL_SS_CNTL);
 391                         ss_cntl &= ~EVERGREEN_PxPLL_SS_EN;
 392                         WREG32(EVERGREEN_P2PLL_SS_CNTL, ss_cntl);
 393                         break;
 394                 case ATOM_DCPLL:
 395                 case ATOM_PPLL_INVALID:
 396                         return;
 397                 }
 398         } else if (ASIC_IS_AVIVO(rdev)) {
 399                 switch (pll_id) {
 400                 case ATOM_PPLL1:
 401                         ss_cntl = RREG32(AVIVO_P1PLL_INT_SS_CNTL);
 402                         ss_cntl &= ~1;
 403                         WREG32(AVIVO_P1PLL_INT_SS_CNTL, ss_cntl);
 404                         break;
 405                 case ATOM_PPLL2:
 406                         ss_cntl = RREG32(AVIVO_P2PLL_INT_SS_CNTL);
 407                         ss_cntl &= ~1;
 408                         WREG32(AVIVO_P2PLL_INT_SS_CNTL, ss_cntl);
 409                         break;
 410                 case ATOM_DCPLL:
 411                 case ATOM_PPLL_INVALID:
 412                         return;
 413                 }
 414         }
 415 }
 416
 417
 418 union atom_enable_ss {
 419         ENABLE_LVDS_SS_PARAMETERS lvds_ss;
 420         ENABLE_LVDS_SS_PARAMETERS_V2 lvds_ss_2;
 421         ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION v1;
 422         ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2 v2;
 423         ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3 v3;
 424 };
 425
 426 static void atombios_crtc_program_ss(struct radeon_device *rdev,
 427                                      int enable,
 428                                      int pll_id,
 429                                      int crtc_id,
 430                                      struct radeon_atom_ss *ss)
 431 {
 432         unsigned i;
 433         int index = GetIndexIntoMasterTable(COMMAND, EnableSpreadSpectrumOnPPLL);
 434         union atom_enable_ss args;
 435
 436         if (!enable) {
 437                 for (i = 0; i < rdev->num_crtc; i++) {
 438                         if (rdev->mode_info.crtcs[i] &&
 439                             rdev->mode_info.crtcs[i]->enabled &&
 440                             i != crtc_id &&
 441                             pll_id == rdev->mode_info.crtcs[i]->pll_id) {
 442                                 /* one other crtc is using this pll don't turn
 443                                  * off spread spectrum as it might turn off
 444                                  * display on active crtc
 445                                  */
 446                                 return;
 447                         }
 448                 }
 449         }
 450
 451         memset(&args, 0, sizeof(args));
 452
 453         if (ASIC_IS_DCE5(rdev)) {
 454                 args.v3.usSpreadSpectrumAmountFrac = cpu_to_le16(0);
 455                 args.v3.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
 456                 switch (pll_id) {
 457                 case ATOM_PPLL1:
 458                         args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P1PLL;
 459                         break;
 460                 case ATOM_PPLL2:
 461                         args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P2PLL;
 462                         break;
 463                 case ATOM_DCPLL:
 464                         args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_DCPLL;
 465                         break;
 466                 case ATOM_PPLL_INVALID:
 467                         return;
 468                 }
 469                 args.v3.usSpreadSpectrumAmount = cpu_to_le16(ss->amount);
 470                 args.v3.usSpreadSpectrumStep = cpu_to_le16(ss->step);
 471                 args.v3.ucEnable = enable;
 472                 if ((ss->percentage == 0) || (ss->type & ATOM_EXTERNAL_SS_MASK) || ASIC_IS_DCE61(rdev))
 473                         args.v3.ucEnable = ATOM_DISABLE;
 474         } else if (ASIC_IS_DCE4(rdev)) {
 475                 args.v2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
 476                 args.v2.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
 477                 switch (pll_id) {
 478                 case ATOM_PPLL1:
 479                         args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_P1PLL;
 480                         break;
 481                 case ATOM_PPLL2:
 482                         args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_P2PLL;
 483                         break;
 484                 case ATOM_DCPLL:
 485                         args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_DCPLL;
 486                         break;
 487                 case ATOM_PPLL_INVALID:
 488                         return;
 489                 }
 490                 args.v2.usSpreadSpectrumAmount = cpu_to_le16(ss->amount);
 491                 args.v2.usSpreadSpectrumStep = cpu_to_le16(ss->step);
 492                 args.v2.ucEnable = enable;
 493                 if ((ss->percentage == 0) || (ss->type & ATOM_EXTERNAL_SS_MASK) || ASIC_IS_DCE41(rdev))
 494                         args.v2.ucEnable = ATOM_DISABLE;
 495         } else if (ASIC_IS_DCE3(rdev)) {
 496                 args.v1.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
 497                 args.v1.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
 498                 args.v1.ucSpreadSpectrumStep = ss->step;
 499                 args.v1.ucSpreadSpectrumDelay = ss->delay;
 500                 args.v1.ucSpreadSpectrumRange = ss->range;
 501                 args.v1.ucPpll = pll_id;
 502                 args.v1.ucEnable = enable;
 503         } else if (ASIC_IS_AVIVO(rdev)) {
 504                 if ((enable == ATOM_DISABLE) || (ss->percentage == 0) ||
 505                     (ss->type & ATOM_EXTERNAL_SS_MASK)) {
 506                         atombios_disable_ss(rdev, pll_id);
 507                         return;
 508                 }
 509                 args.lvds_ss_2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
 510                 args.lvds_ss_2.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
 511                 args.lvds_ss_2.ucSpreadSpectrumStep = ss->step;
 512                 args.lvds_ss_2.ucSpreadSpectrumDelay = ss->delay;
 513                 args.lvds_ss_2.ucSpreadSpectrumRange = ss->range;
 514                 args.lvds_ss_2.ucEnable = enable;
 515         } else {
 516                 if ((enable == ATOM_DISABLE) || (ss->percentage == 0) ||
 517                     (ss->type & ATOM_EXTERNAL_SS_MASK)) {
 518                         atombios_disable_ss(rdev, pll_id);
 519                         return;
 520                 }
 521                 args.lvds_ss.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
 522                 args.lvds_ss.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
 523                 args.lvds_ss.ucSpreadSpectrumStepSize_Delay = (ss->step & 3) << 2;
 524                 args.lvds_ss.ucSpreadSpectrumStepSize_Delay |= (ss->delay & 7) << 4;
 525                 args.lvds_ss.ucEnable = enable;
 526         }
 527         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 528 }
 529
 530 union adjust_pixel_clock {
 531         ADJUST_DISPLAY_PLL_PS_ALLOCATION v1;
 532         ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3 v3;
 533 };
 534
 535 static u32 atombios_adjust_pll(struct drm_crtc *crtc,
 536                                struct drm_display_mode *mode,
 537                                struct radeon_pll *pll,
 538                                bool ss_enabled,
 539                                struct radeon_atom_ss *ss)
 540 {
 541         struct drm_device *dev = crtc->dev;
 542         struct radeon_device *rdev = dev->dev_private;
 543         struct drm_encoder *encoder = NULL;
 544         struct radeon_encoder *radeon_encoder = NULL;
 545         struct drm_connector *connector = NULL;
 546         u32 adjusted_clock = mode->clock;
 547         int encoder_mode = 0;
 548         u32 dp_clock = mode->clock;
 549         int bpc = 8;
 550         bool is_duallink = false;
 551
 552         /* reset the pll flags */
 553         pll->flags = 0;
 554
 555         if (ASIC_IS_AVIVO(rdev)) {
 556                 if ((rdev->family == CHIP_RS600) ||
 557                     (rdev->family == CHIP_RS690) ||
 558                     (rdev->family == CHIP_RS740))
 559                         pll->flags |= (/*RADEON_PLL_USE_FRAC_FB_DIV |*/
 560                                        RADEON_PLL_PREFER_CLOSEST_LOWER);
 561
 562                 if (ASIC_IS_DCE32(rdev) && mode->clock > 200000)        /* range limits??? */
 563                         pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
 564                 else
 565                         pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
 566
 567                 if (rdev->family < CHIP_RV770)
 568                         pll->flags |= RADEON_PLL_PREFER_MINM_OVER_MAXP;
 569                 /* use frac fb div on APUs */
 570                 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev))
 571                         pll->flags |= RADEON_PLL_USE_FRAC_FB_DIV;
 572         } else {
 573                 pll->flags |= RADEON_PLL_LEGACY;
 574
 575                 if (mode->clock > 200000)       /* range limits??? */
 576                         pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
 577                 else
 578                         pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
 579         }
 580
 581         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 582                 if (encoder->crtc == crtc) {
 583                         radeon_encoder = to_radeon_encoder(encoder);
 584                         connector = radeon_get_connector_for_encoder(encoder);
 585                         bpc = radeon_get_monitor_bpc(connector);
 586                         encoder_mode = atombios_get_encoder_mode(encoder);
 587                         is_duallink = radeon_dig_monitor_is_duallink(encoder, mode->clock);
 588                         if ((radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) ||
 589                             (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)) {
 590                                 if (connector) {
 591                                         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 592                                         struct radeon_connector_atom_dig *dig_connector =
 593                                                 radeon_connector->con_priv;
 594
 595                                         dp_clock = dig_connector->dp_clock;
 596                                 }
 597                         }
 598
 599                         /* use recommended ref_div for ss */
 600                         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
 601                                 if (ss_enabled) {
 602                                         if (ss->refdiv) {
 603                                                 pll->flags |= RADEON_PLL_USE_REF_DIV;
 604                                                 pll->reference_div = ss->refdiv;
 605                                                 if (ASIC_IS_AVIVO(rdev))
 606                                                         pll->flags |= RADEON_PLL_USE_FRAC_FB_DIV;
 607                                         }
 608                                 }
 609                         }
 610
 611                         if (ASIC_IS_AVIVO(rdev)) {
 612                                 /* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */
 613                                 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1)
 614                                         adjusted_clock = mode->clock * 2;
 615                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
 616                                         pll->flags |= RADEON_PLL_PREFER_CLOSEST_LOWER;
 617                                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
 618                                         pll->flags |= RADEON_PLL_IS_LCD;
 619                         } else {
 620                                 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC)
 621                                         pll->flags |= RADEON_PLL_NO_ODD_POST_DIV;
 622                                 if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS)
 623                                         pll->flags |= RADEON_PLL_USE_REF_DIV;
 624                         }
 625                         break;
 626                 }
 627         }
 628
 629         /* DCE3+ has an AdjustDisplayPll that will adjust the pixel clock
 630          * accordingly based on the encoder/transmitter to work around
 631          * special hw requirements.
 632          */
 633         if (ASIC_IS_DCE3(rdev)) {
 634                 union adjust_pixel_clock args;
 635                 u8 frev, crev;
 636                 int index;
 637
 638                 index = GetIndexIntoMasterTable(COMMAND, AdjustDisplayPll);
 639                 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
 640                                            &crev))
 641                         return adjusted_clock;
 642
 643                 memset(&args, 0, sizeof(args));
 644
 645                 switch (frev) {
 646                 case 1:
 647                         switch (crev) {
 648                         case 1:
 649                         case 2:
 650                                 args.v1.usPixelClock = cpu_to_le16(mode->clock / 10);
 651                                 args.v1.ucTransmitterID = radeon_encoder->encoder_id;
 652                                 args.v1.ucEncodeMode = encoder_mode;
 653                                 if (ss_enabled && ss->percentage)
 654                                         args.v1.ucConfig |=
 655                                                 ADJUST_DISPLAY_CONFIG_SS_ENABLE;
 656
 657                                 atom_execute_table(rdev->mode_info.atom_context,
 658                                                    index, (uint32_t *)&args);
 659                                 adjusted_clock = le16_to_cpu(args.v1.usPixelClock) * 10;
 660                                 break;
 661                         case 3:
 662                                 args.v3.sInput.usPixelClock = cpu_to_le16(mode->clock / 10);
 663                                 args.v3.sInput.ucTransmitterID = radeon_encoder->encoder_id;
 664                                 args.v3.sInput.ucEncodeMode = encoder_mode;
 665                                 args.v3.sInput.ucDispPllConfig = 0;
 666                                 if (ss_enabled && ss->percentage)
 667                                         args.v3.sInput.ucDispPllConfig |=
 668                                                 DISPPLL_CONFIG_SS_ENABLE;
 669                                 if (ENCODER_MODE_IS_DP(encoder_mode)) {
 670                                         args.v3.sInput.ucDispPllConfig |=
 671                                                 DISPPLL_CONFIG_COHERENT_MODE;
 672                                         /* 16200 or 27000 */
 673                                         args.v3.sInput.usPixelClock = cpu_to_le16(dp_clock / 10);
 674                                 } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
 675                                         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 676                                         if (encoder_mode == ATOM_ENCODER_MODE_HDMI)
 677                                                 /* deep color support */
 678                                                 args.v3.sInput.usPixelClock =
 679                                                         cpu_to_le16((mode->clock * bpc / 8) / 10);
 680                                         if (dig->coherent_mode)
 681                                                 args.v3.sInput.ucDispPllConfig |=
 682                                                         DISPPLL_CONFIG_COHERENT_MODE;
 683                                         if (is_duallink)
 684                                                 args.v3.sInput.ucDispPllConfig |=
 685                                                         DISPPLL_CONFIG_DUAL_LINK;
 686                                 }
 687                                 if (radeon_encoder_get_dp_bridge_encoder_id(encoder) !=
 688                                     ENCODER_OBJECT_ID_NONE)
 689                                         args.v3.sInput.ucExtTransmitterID =
 690                                                 radeon_encoder_get_dp_bridge_encoder_id(encoder);
 691                                 else
 692                                         args.v3.sInput.ucExtTransmitterID = 0;
 693
 694                                 atom_execute_table(rdev->mode_info.atom_context,
 695                                                    index, (uint32_t *)&args);
 696                                 adjusted_clock = le32_to_cpu(args.v3.sOutput.ulDispPllFreq) * 10;
 697                                 if (args.v3.sOutput.ucRefDiv) {
 698                                         pll->flags |= RADEON_PLL_USE_FRAC_FB_DIV;
 699                                         pll->flags |= RADEON_PLL_USE_REF_DIV;
 700                                         pll->reference_div = args.v3.sOutput.ucRefDiv;
 701                                 }
 702                                 if (args.v3.sOutput.ucPostDiv) {
 703                                         pll->flags |= RADEON_PLL_USE_FRAC_FB_DIV;
 704                                         pll->flags |= RADEON_PLL_USE_POST_DIV;
 705                                         pll->post_div = args.v3.sOutput.ucPostDiv;
 706                                 }
 707                                 break;
 708                         default:
 709                                 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
 710                                 return adjusted_clock;
 711                         }
 712                         break;
 713                 default:
 714                         DRM_ERROR("Unknown table version %d %d\n", frev, crev);
 715                         return adjusted_clock;
 716                 }
 717         }
 718         return adjusted_clock;
 719 }
 720
 721 union set_pixel_clock {
 722         SET_PIXEL_CLOCK_PS_ALLOCATION base;
 723         PIXEL_CLOCK_PARAMETERS v1;
 724         PIXEL_CLOCK_PARAMETERS_V2 v2;
 725         PIXEL_CLOCK_PARAMETERS_V3 v3;
 726         PIXEL_CLOCK_PARAMETERS_V5 v5;
 727         PIXEL_CLOCK_PARAMETERS_V6 v6;
 728 };
 729
 730 /* on DCE5, make sure the voltage is high enough to support the
 731  * required disp clk.
 732  */
 733 static void atombios_crtc_set_disp_eng_pll(struct radeon_device *rdev,
 734                                     u32 dispclk)
 735 {
 736         u8 frev, crev;
 737         int index;
 738         union set_pixel_clock args;
 739
 740         memset(&args, 0, sizeof(args));
 741
 742         index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
 743         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
 744                                    &crev))
 745                 return;
 746
 747         switch (frev) {
 748         case 1:
 749                 switch (crev) {
 750                 case 5:
 751                         /* if the default dcpll clock is specified,
 752                          * SetPixelClock provides the dividers
 753                          */
 754                         args.v5.ucCRTC = ATOM_CRTC_INVALID;
 755                         args.v5.usPixelClock = cpu_to_le16(dispclk);
 756                         args.v5.ucPpll = ATOM_DCPLL;
 757                         break;
 758                 case 6:
 759                         /* if the default dcpll clock is specified,
 760                          * SetPixelClock provides the dividers
 761                          */
 762                         args.v6.ulDispEngClkFreq = cpu_to_le32(dispclk);
 763                         if (ASIC_IS_DCE61(rdev))
 764                                 args.v6.ucPpll = ATOM_EXT_PLL1;
 765                         else if (ASIC_IS_DCE6(rdev))
 766                                 args.v6.ucPpll = ATOM_PPLL0;
 767                         else
 768                                 args.v6.ucPpll = ATOM_DCPLL;
 769                         break;
 770                 default:
 771                         DRM_ERROR("Unknown table version %d %d\n", frev, crev);
 772                         return;
 773                 }
 774                 break;
 775         default:
 776                 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
 777                 return;
 778         }
 779         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 780 }
 781
 782 static void atombios_crtc_program_pll(struct drm_crtc *crtc,
 783                                       u32 crtc_id,
 784                                       int pll_id,
 785                                       u32 encoder_mode,
 786                                       u32 encoder_id,
 787                                       u32 clock,
 788                                       u32 ref_div,
 789                                       u32 fb_div,
 790                                       u32 frac_fb_div,
 791                                       u32 post_div,
 792                                       int bpc,
 793                                       bool ss_enabled,
 794                                       struct radeon_atom_ss *ss)
 795 {
 796         struct drm_device *dev = crtc->dev;
 797         struct radeon_device *rdev = dev->dev_private;
 798         u8 frev, crev;
 799         int index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
 800         union set_pixel_clock args;
 801
 802         memset(&args, 0, sizeof(args));
 803
 804         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
 805                                    &crev))
 806                 return;
 807
 808         switch (frev) {
 809         case 1:
 810                 switch (crev) {
 811                 case 1:
 812                         if (clock == ATOM_DISABLE)
 813                                 return;
 814                         args.v1.usPixelClock = cpu_to_le16(clock / 10);
 815                         args.v1.usRefDiv = cpu_to_le16(ref_div);
 816                         args.v1.usFbDiv = cpu_to_le16(fb_div);
 817                         args.v1.ucFracFbDiv = frac_fb_div;
 818                         args.v1.ucPostDiv = post_div;
 819                         args.v1.ucPpll = pll_id;
 820                         args.v1.ucCRTC = crtc_id;
 821                         args.v1.ucRefDivSrc = 1;
 822                         break;
 823                 case 2:
 824                         args.v2.usPixelClock = cpu_to_le16(clock / 10);
 825                         args.v2.usRefDiv = cpu_to_le16(ref_div);
 826                         args.v2.usFbDiv = cpu_to_le16(fb_div);
 827                         args.v2.ucFracFbDiv = frac_fb_div;
 828                         args.v2.ucPostDiv = post_div;
 829                         args.v2.ucPpll = pll_id;
 830                         args.v2.ucCRTC = crtc_id;
 831                         args.v2.ucRefDivSrc = 1;
 832                         break;
 833                 case 3:
 834                         args.v3.usPixelClock = cpu_to_le16(clock / 10);
 835                         args.v3.usRefDiv = cpu_to_le16(ref_div);
 836                         args.v3.usFbDiv = cpu_to_le16(fb_div);
 837                         args.v3.ucFracFbDiv = frac_fb_div;
 838                         args.v3.ucPostDiv = post_div;
 839                         args.v3.ucPpll = pll_id;
 840                         if (crtc_id == ATOM_CRTC2)
 841                                 args.v3.ucMiscInfo = PIXEL_CLOCK_MISC_CRTC_SEL_CRTC2;
 842                         else
 843                                 args.v3.ucMiscInfo = PIXEL_CLOCK_MISC_CRTC_SEL_CRTC1;
 844                         if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))
 845                                 args.v3.ucMiscInfo |= PIXEL_CLOCK_MISC_REF_DIV_SRC;
 846                         args.v3.ucTransmitterId = encoder_id;
 847                         args.v3.ucEncoderMode = encoder_mode;
 848                         break;
 849                 case 5:
 850                         args.v5.ucCRTC = crtc_id;
 851                         args.v5.usPixelClock = cpu_to_le16(clock / 10);
 852                         args.v5.ucRefDiv = ref_div;
 853                         args.v5.usFbDiv = cpu_to_le16(fb_div);
 854                         args.v5.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000);
 855                         args.v5.ucPostDiv = post_div;
 856                         args.v5.ucMiscInfo = 0; /* HDMI depth, etc. */
 857                         if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))
 858                                 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_REF_DIV_SRC;
 859                         switch (bpc) {
 860                         case 8:
 861                         default:
 862                                 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_24BPP;
 863                                 break;
 864                         case 10:
 865                                 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_30BPP;
 866                                 break;
 867                         }
 868                         args.v5.ucTransmitterID = encoder_id;
 869                         args.v5.ucEncoderMode = encoder_mode;
 870                         args.v5.ucPpll = pll_id;
 871                         break;
 872                 case 6:
 873                         args.v6.ulDispEngClkFreq = cpu_to_le32(crtc_id << 24 | clock / 10);
 874                         args.v6.ucRefDiv = ref_div;
 875                         args.v6.usFbDiv = cpu_to_le16(fb_div);
 876                         args.v6.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000);
 877                         args.v6.ucPostDiv = post_div;
 878                         args.v6.ucMiscInfo = 0; /* HDMI depth, etc. */
 879                         if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))
 880                                 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_REF_DIV_SRC;
 881                         switch (bpc) {
 882                         case 8:
 883                         default:
 884                                 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_24BPP;
 885                                 break;
 886                         case 10:
 887                                 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_30BPP;
 888                                 break;
 889                         case 12:
 890                                 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_36BPP;
 891                                 break;
 892                         case 16:
 893                                 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_48BPP;
 894                                 break;
 895                         }
 896                         args.v6.ucTransmitterID = encoder_id;
 897                         args.v6.ucEncoderMode = encoder_mode;
 898                         args.v6.ucPpll = pll_id;
 899                         break;
 900                 default:
 901                         DRM_ERROR("Unknown table version %d %d\n", frev, crev);
 902                         return;
 903                 }
 904                 break;
 905         default:
 906                 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
 907                 return;
 908         }
 909
 910         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 911 }
 912
 913 static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
 914 {
 915         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 916         struct drm_device *dev = crtc->dev;
 917         struct radeon_device *rdev = dev->dev_private;
 918         struct drm_encoder *encoder = NULL;
 919         struct radeon_encoder *radeon_encoder = NULL;
 920         u32 pll_clock = mode->clock;
 921         u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0;
 922         struct radeon_pll *pll;
 923         u32 adjusted_clock;
 924         int encoder_mode = 0;
 925         struct radeon_atom_ss ss;
 926         bool ss_enabled = false;
 927         int bpc = 8;
 928
 929         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 930                 if (encoder->crtc == crtc) {
 931                         radeon_encoder = to_radeon_encoder(encoder);
 932                         encoder_mode = atombios_get_encoder_mode(encoder);
 933                         break;
 934                 }
 935         }
 936
 937         if (!radeon_encoder)
 938                 return;
 939
 940         switch (radeon_crtc->pll_id) {
 941         case ATOM_PPLL1:
 942                 pll = &rdev->clock.p1pll;
 943                 break;
 944         case ATOM_PPLL2:
 945                 pll = &rdev->clock.p2pll;
 946                 break;
 947         case ATOM_DCPLL:
 948         case ATOM_PPLL_INVALID:
 949         default:
 950                 pll = &rdev->clock.dcpll;
 951                 break;
 952         }
 953
 954         if ((radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) ||
 955             (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)) {
 956                 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 957                 struct drm_connector *connector =
 958                         radeon_get_connector_for_encoder(encoder);
 959                 struct radeon_connector *radeon_connector =
 960                         to_radeon_connector(connector);
 961                 struct radeon_connector_atom_dig *dig_connector =
 962                         radeon_connector->con_priv;
 963                 int dp_clock;
 964                 bpc = radeon_get_monitor_bpc(connector);
 965
 966                 switch (encoder_mode) {
 967                 case ATOM_ENCODER_MODE_DP_MST:
 968                 case ATOM_ENCODER_MODE_DP:
 969                         /* DP/eDP */
 970                         dp_clock = dig_connector->dp_clock / 10;
 971                         if (ASIC_IS_DCE4(rdev))
 972                                 ss_enabled =
 973                                         radeon_atombios_get_asic_ss_info(rdev, &ss,
 974                                                                          ASIC_INTERNAL_SS_ON_DP,
 975                                                                          dp_clock);
 976                         else {
 977                                 if (dp_clock == 16200) {
 978                                         ss_enabled =
 979                                                 radeon_atombios_get_ppll_ss_info(rdev, &ss,
 980                                                                                  ATOM_DP_SS_ID2);
 981                                         if (!ss_enabled)
 982                                                 ss_enabled =
 983                                                         radeon_atombios_get_ppll_ss_info(rdev, &ss,
 984                                                                                          ATOM_DP_SS_ID1);
 985                                 } else
 986                                         ss_enabled =
 987                                                 radeon_atombios_get_ppll_ss_info(rdev, &ss,
 988                                                                                  ATOM_DP_SS_ID1);
 989                         }
 990                         break;
 991                 case ATOM_ENCODER_MODE_LVDS:
 992                         if (ASIC_IS_DCE4(rdev))
 993                                 ss_enabled = radeon_atombios_get_asic_ss_info(rdev, &ss,
 994                                                                               dig->lcd_ss_id,
 995                                                                               mode->clock / 10);
 996                         else
 997                                 ss_enabled = radeon_atombios_get_ppll_ss_info(rdev, &ss,
 998                                                                               dig->lcd_ss_id);
 999                         break;
1000                 case ATOM_ENCODER_MODE_DVI:
1001                         if (ASIC_IS_DCE4(rdev))
1002                                 ss_enabled =
1003                                         radeon_atombios_get_asic_ss_info(rdev, &ss,
1004                                                                          ASIC_INTERNAL_SS_ON_TMDS,
1005                                                                          mode->clock / 10);
1006                         break;
1007                 case ATOM_ENCODER_MODE_HDMI:
1008                         if (ASIC_IS_DCE4(rdev))
1009                                 ss_enabled =
1010                                         radeon_atombios_get_asic_ss_info(rdev, &ss,
1011                                                                          ASIC_INTERNAL_SS_ON_HDMI,
1012                                                                          mode->clock / 10);
1013                         break;
1014                 default:
1015                         break;
1016                 }
1017         }
1018
1019         /* adjust pixel clock as needed */
1020         adjusted_clock = atombios_adjust_pll(crtc, mode, pll, ss_enabled, &ss);
1021
1022         if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1023                 /* TV seems to prefer the legacy algo on some boards */
1024                 radeon_compute_pll_legacy(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div,
1025                                           &ref_div, &post_div);
1026         else if (ASIC_IS_AVIVO(rdev))
1027                 radeon_compute_pll_avivo(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div,
1028                                          &ref_div, &post_div);
1029         else
1030                 radeon_compute_pll_legacy(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div,
1031                                           &ref_div, &post_div);
1032
1033         atombios_crtc_program_ss(rdev, ATOM_DISABLE, radeon_crtc->pll_id, radeon_crtc->crtc_id, &ss);
1034
1035         atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
1036                                   encoder_mode, radeon_encoder->encoder_id, mode->clock,
1037                                   ref_div, fb_div, frac_fb_div, post_div, bpc, ss_enabled, &ss);
1038
1039         if (ss_enabled) {
1040                 /* calculate ss amount and step size */
1041                 if (ASIC_IS_DCE4(rdev)) {
1042                         u32 step_size;
1043                         u32 amount = (((fb_div * 10) + frac_fb_div) * ss.percentage) / 10000;
1044                         ss.amount = (amount / 10) & ATOM_PPLL_SS_AMOUNT_V2_FBDIV_MASK;
1045                         ss.amount |= ((amount - (amount / 10)) << ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT) &
1046                                 ATOM_PPLL_SS_AMOUNT_V2_NFRAC_MASK;
1047                         if (ss.type & ATOM_PPLL_SS_TYPE_V2_CENTRE_SPREAD)
1048                                 step_size = (4 * amount * ref_div * (ss.rate * 2048)) /
1049                                         (125 * 25 * pll->reference_freq / 100);
1050                         else
1051                                 step_size = (2 * amount * ref_div * (ss.rate * 2048)) /
1052                                         (125 * 25 * pll->reference_freq / 100);
1053                         ss.step = step_size;
1054                 }
1055
1056                 atombios_crtc_program_ss(rdev, ATOM_ENABLE, radeon_crtc->pll_id, radeon_crtc->crtc_id, &ss);
1057         }
1058 }
1059
1060 static int dce4_crtc_do_set_base(struct drm_crtc *crtc,
1061                                  struct drm_framebuffer *fb,
1062                                  int x, int y, int atomic)
1063 {
1064         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1065         struct drm_device *dev = crtc->dev;
1066         struct radeon_device *rdev = dev->dev_private;
1067         struct radeon_framebuffer *radeon_fb;
1068         struct drm_framebuffer *target_fb;
1069         struct drm_gem_object *obj;
1070         struct radeon_bo *rbo;
1071         uint64_t fb_location;
1072         uint32_t fb_format, fb_pitch_pixels, tiling_flags;
1073         unsigned bankw, bankh, mtaspect, tile_split;
1074         u32 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_NONE);
1075         u32 tmp, viewport_w, viewport_h;
1076         int r;
1077
1078         /* no fb bound */
1079         if (!atomic && !crtc->fb) {
1080                 DRM_DEBUG_KMS("No FB bound\n");
1081                 return 0;
1082         }
1083
1084         if (atomic) {
1085                 radeon_fb = to_radeon_framebuffer(fb);
1086                 target_fb = fb;
1087         }
1088         else {
1089                 radeon_fb = to_radeon_framebuffer(crtc->fb);
1090                 target_fb = crtc->fb;
1091         }
1092
1093         /* If atomic, assume fb object is pinned & idle & fenced and
1094          * just update base pointers
1095          */
1096         obj = radeon_fb->obj;
1097         rbo = gem_to_radeon_bo(obj);
1098         r = radeon_bo_reserve(rbo, false);
1099         if (unlikely(r != 0))
1100                 return r;
1101
1102         if (atomic)
1103                 fb_location = radeon_bo_gpu_offset(rbo);
1104         else {
1105                 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location);
1106                 if (unlikely(r != 0)) {
1107                         radeon_bo_unreserve(rbo);
1108                         return -EINVAL;
1109                 }
1110         }
1111
1112         radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
1113         radeon_bo_unreserve(rbo);
1114
1115         switch (target_fb->bits_per_pixel) {
1116         case 8:
1117                 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_8BPP) |
1118                              EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_INDEXED));
1119                 break;
1120         case 15:
1121                 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
1122                              EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB1555));
1123                 break;
1124         case 16:
1125                 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
1126                              EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB565));
1127 #ifdef __BIG_ENDIAN
1128                 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16);
1129 #endif
1130                 break;
1131         case 24:
1132         case 32:
1133                 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) |
1134                              EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB8888));
1135 #ifdef __BIG_ENDIAN
1136                 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32);
1137 #endif
1138                 break;
1139         default:
1140                 DRM_ERROR("Unsupported screen depth %d\n",
1141                           target_fb->bits_per_pixel);
1142                 return -EINVAL;
1143         }
1144
1145         if (tiling_flags & RADEON_TILING_MACRO) {
1146                 if (rdev->family >= CHIP_TAHITI)
1147                         tmp = rdev->config.si.tile_config;
1148                 else if (rdev->family >= CHIP_CAYMAN)
1149                         tmp = rdev->config.cayman.tile_config;
1150                 else
1151                         tmp = rdev->config.evergreen.tile_config;
1152
1153                 switch ((tmp & 0xf0) >> 4) {
1154                 case 0: /* 4 banks */
1155                         fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_4_BANK);
1156                         break;
1157                 case 1: /* 8 banks */
1158                 default:
1159                         fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_8_BANK);
1160                         break;
1161                 case 2: /* 16 banks */
1162                         fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_16_BANK);
1163                         break;
1164                 }
1165
1166                 fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_2D_TILED_THIN1);
1167
1168                 evergreen_tiling_fields(tiling_flags, &bankw, &bankh, &mtaspect, &tile_split);
1169                 fb_format |= EVERGREEN_GRPH_TILE_SPLIT(tile_split);
1170                 fb_format |= EVERGREEN_GRPH_BANK_WIDTH(bankw);
1171                 fb_format |= EVERGREEN_GRPH_BANK_HEIGHT(bankh);
1172                 fb_format |= EVERGREEN_GRPH_MACRO_TILE_ASPECT(mtaspect);
1173         } else if (tiling_flags & RADEON_TILING_MICRO)
1174                 fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_1D_TILED_THIN1);
1175
1176         if ((rdev->family == CHIP_TAHITI) ||
1177             (rdev->family == CHIP_PITCAIRN))
1178                 fb_format |= SI_GRPH_PIPE_CONFIG(SI_ADDR_SURF_P8_32x32_8x16);
1179         else if (rdev->family == CHIP_VERDE)
1180                 fb_format |= SI_GRPH_PIPE_CONFIG(SI_ADDR_SURF_P4_8x16);
1181
1182         switch (radeon_crtc->crtc_id) {
1183         case 0:
1184                 WREG32(AVIVO_D1VGA_CONTROL, 0);
1185                 break;
1186         case 1:
1187                 WREG32(AVIVO_D2VGA_CONTROL, 0);
1188                 break;
1189         case 2:
1190                 WREG32(EVERGREEN_D3VGA_CONTROL, 0);
1191                 break;
1192         case 3:
1193                 WREG32(EVERGREEN_D4VGA_CONTROL, 0);
1194                 break;
1195         case 4:
1196                 WREG32(EVERGREEN_D5VGA_CONTROL, 0);
1197                 break;
1198         case 5:
1199                 WREG32(EVERGREEN_D6VGA_CONTROL, 0);
1200                 break;
1201         default:
1202                 break;
1203         }
1204
1205         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
1206                upper_32_bits(fb_location));
1207         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
1208                upper_32_bits(fb_location));
1209         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
1210                (u32)fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK);
1211         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
1212                (u32) fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK);
1213         WREG32(EVERGREEN_GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
1214         WREG32(EVERGREEN_GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap);
1215
1216         WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
1217         WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
1218         WREG32(EVERGREEN_GRPH_X_START + radeon_crtc->crtc_offset, 0);
1219         WREG32(EVERGREEN_GRPH_Y_START + radeon_crtc->crtc_offset, 0);
1220         WREG32(EVERGREEN_GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width);
1221         WREG32(EVERGREEN_GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height);
1222
1223         fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8);
1224         WREG32(EVERGREEN_GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
1225         WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
1226
1227         WREG32(EVERGREEN_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
1228                target_fb->height);
1229         x &= ~3;
1230         y &= ~1;
1231         WREG32(EVERGREEN_VIEWPORT_START + radeon_crtc->crtc_offset,
1232                (x << 16) | y);
1233         viewport_w = crtc->mode.hdisplay;
1234         viewport_h = (crtc->mode.vdisplay + 1) & ~1;
1235         WREG32(EVERGREEN_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
1236                (viewport_w << 16) | viewport_h);
1237
1238         /* pageflip setup */
1239         /* make sure flip is at vb rather than hb */
1240         tmp = RREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset);
1241         tmp &= ~EVERGREEN_GRPH_SURFACE_UPDATE_H_RETRACE_EN;
1242         WREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, tmp);
1243
1244         /* set pageflip to happen anywhere in vblank interval */
1245         WREG32(EVERGREEN_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 0);
1246
1247         if (!atomic && fb && fb != crtc->fb) {
1248                 radeon_fb = to_radeon_framebuffer(fb);
1249                 rbo = gem_to_radeon_bo(radeon_fb->obj);
1250                 r = radeon_bo_reserve(rbo, false);
1251                 if (unlikely(r != 0))
1252                         return r;
1253                 radeon_bo_unpin(rbo);
1254                 radeon_bo_unreserve(rbo);
1255         }
1256
1257         /* Bytes per pixel may have changed */
1258         radeon_bandwidth_update(rdev);
1259
1260         return 0;
1261 }
1262
1263 static int avivo_crtc_do_set_base(struct drm_crtc *crtc,
1264                                   struct drm_framebuffer *fb,
1265                                   int x, int y, int atomic)
1266 {
1267         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1268         struct drm_device *dev = crtc->dev;
1269         struct radeon_device *rdev = dev->dev_private;
1270         struct radeon_framebuffer *radeon_fb;
1271         struct drm_gem_object *obj;
1272         struct radeon_bo *rbo;
1273         struct drm_framebuffer *target_fb;
1274         uint64_t fb_location;
1275         uint32_t fb_format, fb_pitch_pixels, tiling_flags;
1276         u32 fb_swap = R600_D1GRPH_SWAP_ENDIAN_NONE;
1277         u32 tmp, viewport_w, viewport_h;
1278         int r;
1279
1280         /* no fb bound */
1281         if (!atomic && !crtc->fb) {
1282                 DRM_DEBUG_KMS("No FB bound\n");
1283                 return 0;
1284         }
1285
1286         if (atomic) {
1287                 radeon_fb = to_radeon_framebuffer(fb);
1288                 target_fb = fb;
1289         }
1290         else {
1291                 radeon_fb = to_radeon_framebuffer(crtc->fb);
1292                 target_fb = crtc->fb;
1293         }
1294
1295         obj = radeon_fb->obj;
1296         rbo = gem_to_radeon_bo(obj);
1297         r = radeon_bo_reserve(rbo, false);
1298         if (unlikely(r != 0))
1299                 return r;
1300
1301         /* If atomic, assume fb object is pinned & idle & fenced and
1302          * just update base pointers
1303          */
1304         if (atomic)
1305                 fb_location = radeon_bo_gpu_offset(rbo);
1306         else {
1307                 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location);
1308                 if (unlikely(r != 0)) {
1309                         radeon_bo_unreserve(rbo);
1310                         return -EINVAL;
1311                 }
1312         }
1313         radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
1314         radeon_bo_unreserve(rbo);
1315
1316         switch (target_fb->bits_per_pixel) {
1317         case 8:
1318                 fb_format =
1319                     AVIVO_D1GRPH_CONTROL_DEPTH_8BPP |
1320                     AVIVO_D1GRPH_CONTROL_8BPP_INDEXED;
1321                 break;
1322         case 15:
1323                 fb_format =
1324                     AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
1325                     AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555;
1326                 break;
1327         case 16:
1328                 fb_format =
1329                     AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
1330                     AVIVO_D1GRPH_CONTROL_16BPP_RGB565;
1331 #ifdef __BIG_ENDIAN
1332                 fb_swap = R600_D1GRPH_SWAP_ENDIAN_16BIT;
1333 #endif
1334                 break;
1335         case 24:
1336         case 32:
1337                 fb_format =
1338                     AVIVO_D1GRPH_CONTROL_DEPTH_32BPP |
1339                     AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888;
1340 #ifdef __BIG_ENDIAN
1341                 fb_swap = R600_D1GRPH_SWAP_ENDIAN_32BIT;
1342 #endif
1343                 break;
1344         default:
1345                 DRM_ERROR("Unsupported screen depth %d\n",
1346                           target_fb->bits_per_pixel);
1347                 return -EINVAL;
1348         }
1349
1350         if (rdev->family >= CHIP_R600) {
1351                 if (tiling_flags & RADEON_TILING_MACRO)
1352                         fb_format |= R600_D1GRPH_ARRAY_MODE_2D_TILED_THIN1;
1353                 else if (tiling_flags & RADEON_TILING_MICRO)
1354                         fb_format |= R600_D1GRPH_ARRAY_MODE_1D_TILED_THIN1;
1355         } else {
1356                 if (tiling_flags & RADEON_TILING_MACRO)
1357                         fb_format |= AVIVO_D1GRPH_MACRO_ADDRESS_MODE;
1358
1359                 if (tiling_flags & RADEON_TILING_MICRO)
1360                         fb_format |= AVIVO_D1GRPH_TILED;
1361         }
1362
1363         if (radeon_crtc->crtc_id == 0)
1364                 WREG32(AVIVO_D1VGA_CONTROL, 0);
1365         else
1366                 WREG32(AVIVO_D2VGA_CONTROL, 0);
1367
1368         if (rdev->family >= CHIP_RV770) {
1369                 if (radeon_crtc->crtc_id) {
1370                         WREG32(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1371                         WREG32(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1372                 } else {
1373                         WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1374                         WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1375                 }
1376         }
1377         WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
1378                (u32) fb_location);
1379         WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS +
1380                radeon_crtc->crtc_offset, (u32) fb_location);
1381         WREG32(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
1382         if (rdev->family >= CHIP_R600)
1383                 WREG32(R600_D1GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap);
1384
1385         WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
1386         WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
1387         WREG32(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, 0);
1388         WREG32(AVIVO_D1GRPH_Y_START + radeon_crtc->crtc_offset, 0);
1389         WREG32(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width);
1390         WREG32(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height);
1391
1392         fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8);
1393         WREG32(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
1394         WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
1395
1396         WREG32(AVIVO_D1MODE_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
1397                target_fb->height);
1398         x &= ~3;
1399         y &= ~1;
1400         WREG32(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset,
1401                (x << 16) | y);
1402         viewport_w = crtc->mode.hdisplay;
1403         viewport_h = (crtc->mode.vdisplay + 1) & ~1;
1404         WREG32(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
1405                (viewport_w << 16) | viewport_h);
1406
1407         /* pageflip setup */
1408         /* make sure flip is at vb rather than hb */
1409         tmp = RREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset);
1410         tmp &= ~AVIVO_D1GRPH_SURFACE_UPDATE_H_RETRACE_EN;
1411         WREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, tmp);
1412
1413         /* set pageflip to happen anywhere in vblank interval */
1414         WREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 0);
1415
1416         if (!atomic && fb && fb != crtc->fb) {
1417                 radeon_fb = to_radeon_framebuffer(fb);
1418                 rbo = gem_to_radeon_bo(radeon_fb->obj);
1419                 r = radeon_bo_reserve(rbo, false);
1420                 if (unlikely(r != 0))
1421                         return r;
1422                 radeon_bo_unpin(rbo);
1423                 radeon_bo_unreserve(rbo);
1424         }
1425
1426         /* Bytes per pixel may have changed */
1427         radeon_bandwidth_update(rdev);
1428
1429         return 0;
1430 }
1431
1432 int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
1433                            struct drm_framebuffer *old_fb)
1434 {
1435         struct drm_device *dev = crtc->dev;
1436         struct radeon_device *rdev = dev->dev_private;
1437
1438         if (ASIC_IS_DCE4(rdev))
1439                 return dce4_crtc_do_set_base(crtc, old_fb, x, y, 0);
1440         else if (ASIC_IS_AVIVO(rdev))
1441                 return avivo_crtc_do_set_base(crtc, old_fb, x, y, 0);
1442         else
1443                 return radeon_crtc_do_set_base(crtc, old_fb, x, y, 0);
1444 }
1445
1446 int atombios_crtc_set_base_atomic(struct drm_crtc *crtc,
1447                                   struct drm_framebuffer *fb,
1448                                   int x, int y, enum mode_set_atomic state)
1449 {
1450        struct drm_device *dev = crtc->dev;
1451        struct radeon_device *rdev = dev->dev_private;
1452
1453         if (ASIC_IS_DCE4(rdev))
1454                 return dce4_crtc_do_set_base(crtc, fb, x, y, 1);
1455         else if (ASIC_IS_AVIVO(rdev))
1456                 return avivo_crtc_do_set_base(crtc, fb, x, y, 1);
1457         else
1458                 return radeon_crtc_do_set_base(crtc, fb, x, y, 1);
1459 }
1460
1461 /* properly set additional regs when using atombios */
1462 static void radeon_legacy_atom_fixup(struct drm_crtc *crtc)
1463 {
1464         struct drm_device *dev = crtc->dev;
1465         struct radeon_device *rdev = dev->dev_private;
1466         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1467         u32 disp_merge_cntl;
1468
1469         switch (radeon_crtc->crtc_id) {
1470         case 0:
1471                 disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL);
1472                 disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN;
1473                 WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl);
1474                 break;
1475         case 1:
1476                 disp_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL);
1477                 disp_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN;
1478                 WREG32(RADEON_DISP2_MERGE_CNTL, disp_merge_cntl);
1479                 WREG32(RADEON_FP_H2_SYNC_STRT_WID,   RREG32(RADEON_CRTC2_H_SYNC_STRT_WID));
1480                 WREG32(RADEON_FP_V2_SYNC_STRT_WID,   RREG32(RADEON_CRTC2_V_SYNC_STRT_WID));
1481                 break;
1482         }
1483 }
1484
1485 /**
1486  * radeon_get_pll_use_mask - look up a mask of which pplls are in use
1487  *
1488  * @crtc: drm crtc
1489  *
1490  * Returns the mask of which PPLLs (Pixel PLLs) are in use.
1491  */
1492 static u32 radeon_get_pll_use_mask(struct drm_crtc *crtc)
1493 {
1494         struct drm_device *dev = crtc->dev;
1495         struct drm_crtc *test_crtc;
1496         struct radeon_crtc *radeon_test_crtc;
1497         u32 pll_in_use = 0;
1498
1499         list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) {
1500                 if (crtc == test_crtc)
1501                         continue;
1502
1503                 radeon_test_crtc = to_radeon_crtc(test_crtc);
1504                 if (radeon_test_crtc->pll_id != ATOM_PPLL_INVALID)
1505                         pll_in_use |= (1 << radeon_test_crtc->pll_id);
1506         }
1507         return pll_in_use;
1508 }
1509
1510 /**
1511  * radeon_get_shared_dp_ppll - return the PPLL used by another crtc for DP
1512  *
1513  * @crtc: drm crtc
1514  *
1515  * Returns the PPLL (Pixel PLL) used by another crtc/encoder which is
1516  * also in DP mode.  For DP, a single PPLL can be used for all DP
1517  * crtcs/encoders.
1518  */
1519 static int radeon_get_shared_dp_ppll(struct drm_crtc *crtc)
1520 {
1521         struct drm_device *dev = crtc->dev;
1522         struct drm_encoder *test_encoder;
1523         struct radeon_crtc *radeon_test_crtc;
1524
1525         list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
1526                 if (test_encoder->crtc && (test_encoder->crtc != crtc)) {
1527                         if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_encoder))) {
1528                                 /* for DP use the same PLL for all */
1529                                 radeon_test_crtc = to_radeon_crtc(test_encoder->crtc);
1530                                 if (radeon_test_crtc->pll_id != ATOM_PPLL_INVALID)
1531                                         return radeon_test_crtc->pll_id;
1532                         }
1533                 }
1534         }
1535         return ATOM_PPLL_INVALID;
1536 }
1537
1538 /**
1539  * radeon_get_shared_nondp_ppll - return the PPLL used by another non-DP crtc
1540  *
1541  * @crtc: drm crtc
1542  * @encoder: drm encoder
1543  *
1544  * Returns the PPLL (Pixel PLL) used by another non-DP crtc/encoder which can
1545  * be shared (i.e., same clock).
1546  */
1547 static int radeon_get_shared_nondp_ppll(struct drm_crtc *crtc,
1548                                         struct drm_encoder *encoder)
1549 {
1550         struct drm_device *dev = crtc->dev;
1551         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1552         struct drm_encoder *test_encoder;
1553         struct radeon_crtc *radeon_test_crtc;
1554         struct radeon_encoder *test_radeon_encoder;
1555         u32 target_clock, test_clock;
1556
1557         if (radeon_encoder->native_mode.clock)
1558                 target_clock = radeon_encoder->native_mode.clock;
1559         else
1560                 target_clock = crtc->mode.clock;
1561
1562         list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
1563                 if (test_encoder->crtc && (test_encoder->crtc != crtc)) {
1564                         if (!ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_encoder))) {
1565                                 test_radeon_encoder = to_radeon_encoder(test_encoder);
1566                                 radeon_test_crtc = to_radeon_crtc(test_encoder->crtc);
1567                                 /* for non-DP check the clock */
1568                                 if (test_radeon_encoder->native_mode.clock)
1569                                         test_clock = test_radeon_encoder->native_mode.clock;
1570                                 else
1571                                         test_clock = test_encoder->crtc->mode.clock;
1572                                 if ((target_clock == test_clock) &&
1573                                     (radeon_test_crtc->pll_id != ATOM_PPLL_INVALID))
1574                                         return radeon_test_crtc->pll_id;
1575                         }
1576                 }
1577         }
1578         return ATOM_PPLL_INVALID;
1579 }
1580
1581 /**
1582  * radeon_atom_pick_pll - Allocate a PPLL for use by the crtc.
1583  *
1584  * @crtc: drm crtc
1585  *
1586  * Returns the PPLL (Pixel PLL) to be used by the crtc.  For DP monitors
1587  * a single PPLL can be used for all DP crtcs/encoders.  For non-DP
1588  * monitors a dedicated PPLL must be used.  If a particular board has
1589  * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming
1590  * as there is no need to program the PLL itself.  If we are not able to
1591  * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to
1592  * avoid messing up an existing monitor.
1593  *
1594  * Asic specific PLL information
1595  *
1596  * DCE 6.1
1597  * - PPLL2 is only available to UNIPHYA (both DP and non-DP)
1598  * - PPLL0, PPLL1 are available for UNIPHYB/C/D/E/F (both DP and non-DP)
1599  *
1600  * DCE 6.0
1601  * - PPLL0 is available to all UNIPHY (DP only)
1602  * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
1603  *
1604  * DCE 5.0
1605  * - DCPLL is available to all UNIPHY (DP only)
1606  * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
1607  *
1608  * DCE 3.0/4.0/4.1
1609  * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
1610  *
1611  */
1612 static int radeon_atom_pick_pll(struct drm_crtc *crtc)
1613 {
1614         struct drm_device *dev = crtc->dev;
1615         struct radeon_device *rdev = dev->dev_private;
1616         struct drm_encoder *test_encoder;
1617         u32 pll_in_use;
1618         int pll;
1619
1620         if (ASIC_IS_DCE61(rdev)) {
1621                 list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
1622                         if (test_encoder->crtc && (test_encoder->crtc == crtc)) {
1623                                 struct radeon_encoder *test_radeon_encoder =
1624                                         to_radeon_encoder(test_encoder);
1625                                 struct radeon_encoder_atom_dig *dig =
1626                                         test_radeon_encoder->enc_priv;
1627
1628                                 if ((test_radeon_encoder->encoder_id ==
1629                                      ENCODER_OBJECT_ID_INTERNAL_UNIPHY) &&
1630                                     (dig->linkb == false))
1631                                         /* UNIPHY A uses PPLL2 */
1632                                         return ATOM_PPLL2;
1633                                 else if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_encoder))) {
1634                                         /* UNIPHY B/C/D/E/F */
1635                                         if (rdev->clock.dp_extclk)
1636                                                 /* skip PPLL programming if using ext clock */
1637                                                 return ATOM_PPLL_INVALID;
1638                                         else {
1639                                                 /* use the same PPLL for all DP monitors */
1640                                                 pll = radeon_get_shared_dp_ppll(crtc);
1641                                                 if (pll != ATOM_PPLL_INVALID)
1642                                                         return pll;
1643                                         }
1644                                 } else {
1645                                         /* use the same PPLL for all monitors with the same clock */
1646                                         pll = radeon_get_shared_nondp_ppll(crtc, test_encoder);
1647                                         if (pll != ATOM_PPLL_INVALID)
1648                                                 return pll;
1649                                 }
1650                                 break;
1651                         }
1652                 }
1653                 /* UNIPHY B/C/D/E/F */
1654                 pll_in_use = radeon_get_pll_use_mask(crtc);
1655                 if (!(pll_in_use & (1 << ATOM_PPLL0)))
1656                         return ATOM_PPLL0;
1657                 if (!(pll_in_use & (1 << ATOM_PPLL1)))
1658                         return ATOM_PPLL1;
1659                 DRM_ERROR("unable to allocate a PPLL\n");
1660                 return ATOM_PPLL_INVALID;
1661         } else if (ASIC_IS_DCE4(rdev)) {
1662                 list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
1663                         if (test_encoder->crtc && (test_encoder->crtc == crtc)) {
1664                                 /* in DP mode, the DP ref clock can come from PPLL, DCPLL, or ext clock,
1665                                  * depending on the asic:
1666                                  * DCE4: PPLL or ext clock
1667                                  * DCE5: PPLL, DCPLL, or ext clock
1668                                  * DCE6: PPLL, PPLL0, or ext clock
1669                                  *
1670                                  * Setting ATOM_PPLL_INVALID will cause SetPixelClock to skip
1671                                  * PPLL/DCPLL programming and only program the DP DTO for the
1672                                  * crtc virtual pixel clock.
1673                                  */
1674                                 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_encoder))) {
1675                                         if (rdev->clock.dp_extclk)
1676                                                 /* skip PPLL programming if using ext clock */
1677                                                 return ATOM_PPLL_INVALID;
1678                                         else if (ASIC_IS_DCE6(rdev))
1679                                                 /* use PPLL0 for all DP */
1680                                                 return ATOM_PPLL0;
1681                                         else if (ASIC_IS_DCE5(rdev))
1682                                                 /* use DCPLL for all DP */
1683                                                 return ATOM_DCPLL;
1684                                         else {
1685                                                 /* use the same PPLL for all DP monitors */
1686                                                 pll = radeon_get_shared_dp_ppll(crtc);
1687                                                 if (pll != ATOM_PPLL_INVALID)
1688                                                         return pll;
1689                                         }
1690                                 } else {
1691                                         /* use the same PPLL for all monitors with the same clock */
1692                                         pll = radeon_get_shared_nondp_ppll(crtc, test_encoder);
1693                                         if (pll != ATOM_PPLL_INVALID)
1694                                                 return pll;
1695                                 }
1696                                 break;
1697                         }
1698                 }
1699                 /* all other cases */
1700                 pll_in_use = radeon_get_pll_use_mask(crtc);
1701                 if (!(pll_in_use & (1 << ATOM_PPLL2)))
1702                         return ATOM_PPLL2;
1703                 if (!(pll_in_use & (1 << ATOM_PPLL1)))
1704                         return ATOM_PPLL1;
1705                 DRM_ERROR("unable to allocate a PPLL\n");
1706                 return ATOM_PPLL_INVALID;
1707         } else {
1708                 /* on pre-R5xx asics, the crtc to pll mapping is hardcoded */
1709                 if (!ASIC_IS_AVIVO(rdev)) {
1710                         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1711                         return radeon_crtc->crtc_id;
1712                 }
1713                 list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
1714                         if (test_encoder->crtc && (test_encoder->crtc == crtc)) {
1715                                 /* in DP mode, the DP ref clock can come from either PPLL
1716                                  * depending on the asic:
1717                                  * DCE3: PPLL1 or PPLL2
1718                                  */
1719                                 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_encoder))) {
1720                                         /* use the same PPLL for all DP monitors */
1721                                         pll = radeon_get_shared_dp_ppll(crtc);
1722                                         if (pll != ATOM_PPLL_INVALID)
1723                                                 return pll;
1724                                 } else {
1725                                         /* use the same PPLL for all monitors with the same clock */
1726                                         pll = radeon_get_shared_nondp_ppll(crtc, test_encoder);
1727                                         if (pll != ATOM_PPLL_INVALID)
1728                                                 return pll;
1729                                 }
1730                                 break;
1731                         }
1732                 }
1733                 /* all other cases */
1734                 pll_in_use = radeon_get_pll_use_mask(crtc);
1735                 if (!(pll_in_use & (1 << ATOM_PPLL2)))
1736                         return ATOM_PPLL2;
1737                 if (!(pll_in_use & (1 << ATOM_PPLL1)))
1738                         return ATOM_PPLL1;
1739                 DRM_ERROR("unable to allocate a PPLL\n");
1740                 return ATOM_PPLL_INVALID;
1741         }
1742 }
1743
1744 void radeon_atom_disp_eng_pll_init(struct radeon_device *rdev)
1745 {
1746         /* always set DCPLL */
1747         if (ASIC_IS_DCE6(rdev))
1748                 atombios_crtc_set_disp_eng_pll(rdev, rdev->clock.default_dispclk);
1749         else if (ASIC_IS_DCE4(rdev)) {
1750                 struct radeon_atom_ss ss;
1751                 bool ss_enabled = radeon_atombios_get_asic_ss_info(rdev, &ss,
1752                                                                    ASIC_INTERNAL_SS_ON_DCPLL,
1753                                                                    rdev->clock.default_dispclk);
1754                 if (ss_enabled)
1755                         atombios_crtc_program_ss(rdev, ATOM_DISABLE, ATOM_DCPLL, -1, &ss);
1756                 /* XXX: DCE5, make sure voltage, dispclk is high enough */
1757                 atombios_crtc_set_disp_eng_pll(rdev, rdev->clock.default_dispclk);
1758                 if (ss_enabled)
1759                         atombios_crtc_program_ss(rdev, ATOM_ENABLE, ATOM_DCPLL, -1, &ss);
1760         }
1761
1762 }
1763
1764 int atombios_crtc_mode_set(struct drm_crtc *crtc,
1765                            struct drm_display_mode *mode,
1766                            struct drm_display_mode *adjusted_mode,
1767                            int x, int y, struct drm_framebuffer *old_fb)
1768 {
1769         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1770         struct drm_device *dev = crtc->dev;
1771         struct radeon_device *rdev = dev->dev_private;
1772         struct drm_encoder *encoder;
1773         bool is_tvcv = false;
1774
1775         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1776                 /* find tv std */
1777                 if (encoder->crtc == crtc) {
1778                         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1779                         if (radeon_encoder->active_device &
1780                             (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
1781                                 is_tvcv = true;
1782                 }
1783         }
1784
1785         atombios_crtc_set_pll(crtc, adjusted_mode);
1786
1787         if (ASIC_IS_DCE4(rdev))
1788                 atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
1789         else if (ASIC_IS_AVIVO(rdev)) {
1790                 if (is_tvcv)
1791                         atombios_crtc_set_timing(crtc, adjusted_mode);
1792                 else
1793                         atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
1794         } else {
1795                 atombios_crtc_set_timing(crtc, adjusted_mode);
1796                 if (radeon_crtc->crtc_id == 0)
1797                         atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
1798                 radeon_legacy_atom_fixup(crtc);
1799         }
1800         atombios_crtc_set_base(crtc, x, y, old_fb);
1801         atombios_overscan_setup(crtc, mode, adjusted_mode);
1802         atombios_scaler_setup(crtc);
1803         return 0;
1804 }
1805
1806 static bool atombios_crtc_mode_fixup(struct drm_crtc *crtc,
1807                                      const struct drm_display_mode *mode,
1808                                      struct drm_display_mode *adjusted_mode)
1809 {
1810         if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
1811                 return false;
1812         return true;
1813 }
1814
1815 static void atombios_crtc_prepare(struct drm_crtc *crtc)
1816 {
1817         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1818         struct drm_device *dev = crtc->dev;
1819         struct radeon_device *rdev = dev->dev_private;
1820
1821         radeon_crtc->in_mode_set = true;
1822         /* pick pll */
1823         radeon_crtc->pll_id = radeon_atom_pick_pll(crtc);
1824
1825         /* disable crtc pair power gating before programming */
1826         if (ASIC_IS_DCE6(rdev))
1827                 atombios_powergate_crtc(crtc, ATOM_DISABLE);
1828
1829         atombios_lock_crtc(crtc, ATOM_ENABLE);
1830         atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
1831 }
1832
1833 static void atombios_crtc_commit(struct drm_crtc *crtc)
1834 {
1835         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1836
1837         atombios_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
1838         atombios_lock_crtc(crtc, ATOM_DISABLE);
1839         radeon_crtc->in_mode_set = false;
1840 }
1841
1842 static void atombios_crtc_disable(struct drm_crtc *crtc)
1843 {
1844         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1845         struct drm_device *dev = crtc->dev;
1846         struct radeon_device *rdev = dev->dev_private;
1847         struct radeon_atom_ss ss;
1848         int i;
1849
1850         atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
1851
1852         for (i = 0; i < rdev->num_crtc; i++) {
1853                 if (rdev->mode_info.crtcs[i] &&
1854                     rdev->mode_info.crtcs[i]->enabled &&
1855                     i != radeon_crtc->crtc_id &&
1856                     radeon_crtc->pll_id == rdev->mode_info.crtcs[i]->pll_id) {
1857                         /* one other crtc is using this pll don't turn
1858                          * off the pll
1859                          */
1860                         goto done;
1861                 }
1862         }
1863
1864         switch (radeon_crtc->pll_id) {
1865         case ATOM_PPLL1:
1866         case ATOM_PPLL2:
1867                 /* disable the ppll */
1868                 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
1869                                           0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
1870                 break;
1871         case ATOM_PPLL0:
1872                 /* disable the ppll */
1873                 if (ASIC_IS_DCE61(rdev))
1874                         atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
1875                                                   0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
1876                 break;
1877         default:
1878                 break;
1879         }
1880 done:
1881         radeon_crtc->pll_id = ATOM_PPLL_INVALID;
1882 }
1883
1884 static const struct drm_crtc_helper_funcs atombios_helper_funcs = {
1885         .dpms = atombios_crtc_dpms,
1886         .mode_fixup = atombios_crtc_mode_fixup,
1887         .mode_set = atombios_crtc_mode_set,
1888         .mode_set_base = atombios_crtc_set_base,
1889         .mode_set_base_atomic = atombios_crtc_set_base_atomic,
1890         .prepare = atombios_crtc_prepare,
1891         .commit = atombios_crtc_commit,
1892         .load_lut = radeon_crtc_load_lut,
1893         .disable = atombios_crtc_disable,
1894 };
1895
1896 void radeon_atombios_init_crtc(struct drm_device *dev,
1897                                struct radeon_crtc *radeon_crtc)
1898 {
1899         struct radeon_device *rdev = dev->dev_private;
1900
1901         if (ASIC_IS_DCE4(rdev)) {
1902                 switch (radeon_crtc->crtc_id) {
1903                 case 0:
1904                 default:
1905                         radeon_crtc->crtc_offset = EVERGREEN_CRTC0_REGISTER_OFFSET;
1906                         break;
1907                 case 1:
1908                         radeon_crtc->crtc_offset = EVERGREEN_CRTC1_REGISTER_OFFSET;
1909                         break;
1910                 case 2:
1911                         radeon_crtc->crtc_offset = EVERGREEN_CRTC2_REGISTER_OFFSET;
1912                         break;
1913                 case 3:
1914                         radeon_crtc->crtc_offset = EVERGREEN_CRTC3_REGISTER_OFFSET;
1915                         break;
1916                 case 4:
1917                         radeon_crtc->crtc_offset = EVERGREEN_CRTC4_REGISTER_OFFSET;
1918                         break;
1919                 case 5:
1920                         radeon_crtc->crtc_offset = EVERGREEN_CRTC5_REGISTER_OFFSET;
1921                         break;
1922                 }
1923         } else {
1924                 if (radeon_crtc->crtc_id == 1)
1925                         radeon_crtc->crtc_offset =
1926                                 AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL;
1927                 else
1928                         radeon_crtc->crtc_offset = 0;
1929         }
1930         radeon_crtc->pll_id = ATOM_PPLL_INVALID;
1931         drm_crtc_helper_add(&radeon_crtc->base, &atombios_helper_funcs);
1932 }