1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright 2018 Marty E. Plummer <hanetzer@startmail.com> */
3 /* Copyright 2019 Linaro, Ltd, Rob Herring <robh@kernel.org> */
6 #include <linux/reset.h>
7 #include <linux/platform_device.h>
8 #include <linux/pm_runtime.h>
9 #include <linux/regulator/consumer.h>
11 #include "panfrost_device.h"
12 #include "panfrost_devfreq.h"
13 #include "panfrost_features.h"
14 #include "panfrost_gpu.h"
15 #include "panfrost_job.h"
16 #include "panfrost_mmu.h"
18 static int panfrost_reset_init(struct panfrost_device *pfdev)
22 pfdev->rstc = devm_reset_control_array_get(pfdev->dev, false, true);
23 if (IS_ERR(pfdev->rstc)) {
24 dev_err(pfdev->dev, "get reset failed %ld\n", PTR_ERR(pfdev->rstc));
25 return PTR_ERR(pfdev->rstc);
28 err = reset_control_deassert(pfdev->rstc);
35 static void panfrost_reset_fini(struct panfrost_device *pfdev)
37 reset_control_assert(pfdev->rstc);
40 static int panfrost_clk_init(struct panfrost_device *pfdev)
45 pfdev->clock = devm_clk_get(pfdev->dev, NULL);
46 if (IS_ERR(pfdev->clock)) {
47 dev_err(pfdev->dev, "get clock failed %ld\n", PTR_ERR(pfdev->clock));
48 return PTR_ERR(pfdev->clock);
51 rate = clk_get_rate(pfdev->clock);
52 dev_info(pfdev->dev, "clock rate = %lu\n", rate);
54 err = clk_prepare_enable(pfdev->clock);
61 static void panfrost_clk_fini(struct panfrost_device *pfdev)
63 clk_disable_unprepare(pfdev->clock);
66 static int panfrost_regulator_init(struct panfrost_device *pfdev)
70 pfdev->regulator = devm_regulator_get_optional(pfdev->dev, "mali");
71 if (IS_ERR(pfdev->regulator)) {
72 ret = PTR_ERR(pfdev->regulator);
73 pfdev->regulator = NULL;
76 dev_err(pfdev->dev, "failed to get regulator: %d\n", ret);
80 ret = regulator_enable(pfdev->regulator);
82 dev_err(pfdev->dev, "failed to enable regulator: %d\n", ret);
89 static void panfrost_regulator_fini(struct panfrost_device *pfdev)
92 regulator_disable(pfdev->regulator);
95 int panfrost_device_init(struct panfrost_device *pfdev)
100 mutex_init(&pfdev->sched_lock);
101 mutex_init(&pfdev->reset_lock);
102 INIT_LIST_HEAD(&pfdev->scheduled_jobs);
104 spin_lock_init(&pfdev->hwaccess_lock);
106 err = panfrost_clk_init(pfdev);
108 dev_err(pfdev->dev, "clk init failed %d\n", err);
112 err = panfrost_regulator_init(pfdev);
114 dev_err(pfdev->dev, "regulator init failed %d\n", err);
118 err = panfrost_reset_init(pfdev);
120 dev_err(pfdev->dev, "reset init failed %d\n", err);
124 res = platform_get_resource(pfdev->pdev, IORESOURCE_MEM, 0);
125 pfdev->iomem = devm_ioremap_resource(pfdev->dev, res);
126 if (IS_ERR(pfdev->iomem)) {
127 dev_err(pfdev->dev, "failed to ioremap iomem\n");
128 err = PTR_ERR(pfdev->iomem);
132 err = panfrost_gpu_init(pfdev);
136 err = panfrost_mmu_init(pfdev);
140 err = panfrost_job_init(pfdev);
144 /* runtime PM will wake us up later */
145 panfrost_gpu_power_off(pfdev);
147 pm_runtime_set_active(pfdev->dev);
148 pm_runtime_get_sync(pfdev->dev);
149 pm_runtime_mark_last_busy(pfdev->dev);
150 pm_runtime_put_autosuspend(pfdev->dev);
154 panfrost_mmu_fini(pfdev);
156 panfrost_gpu_fini(pfdev);
158 panfrost_reset_fini(pfdev);
160 panfrost_regulator_fini(pfdev);
162 panfrost_clk_fini(pfdev);
166 void panfrost_device_fini(struct panfrost_device *pfdev)
168 panfrost_regulator_fini(pfdev);
169 panfrost_clk_fini(pfdev);
172 const char *panfrost_exception_name(struct panfrost_device *pfdev, u32 exception_code)
174 switch (exception_code) {
175 /* Non-Fault Status code */
176 case 0x00: return "NOT_STARTED/IDLE/OK";
177 case 0x01: return "DONE";
178 case 0x02: return "INTERRUPTED";
179 case 0x03: return "STOPPED";
180 case 0x04: return "TERMINATED";
181 case 0x08: return "ACTIVE";
183 case 0x40: return "JOB_CONFIG_FAULT";
184 case 0x41: return "JOB_POWER_FAULT";
185 case 0x42: return "JOB_READ_FAULT";
186 case 0x43: return "JOB_WRITE_FAULT";
187 case 0x44: return "JOB_AFFINITY_FAULT";
188 case 0x48: return "JOB_BUS_FAULT";
189 case 0x50: return "INSTR_INVALID_PC";
190 case 0x51: return "INSTR_INVALID_ENC";
191 case 0x52: return "INSTR_TYPE_MISMATCH";
192 case 0x53: return "INSTR_OPERAND_FAULT";
193 case 0x54: return "INSTR_TLS_FAULT";
194 case 0x55: return "INSTR_BARRIER_FAULT";
195 case 0x56: return "INSTR_ALIGN_FAULT";
196 case 0x58: return "DATA_INVALID_FAULT";
197 case 0x59: return "TILE_RANGE_FAULT";
198 case 0x5A: return "ADDR_RANGE_FAULT";
199 case 0x60: return "OUT_OF_MEMORY";
201 case 0x80: return "DELAYED_BUS_FAULT";
202 case 0x88: return "SHAREABILITY_FAULT";
204 case 0xC1: return "TRANSLATION_FAULT_LEVEL1";
205 case 0xC2: return "TRANSLATION_FAULT_LEVEL2";
206 case 0xC3: return "TRANSLATION_FAULT_LEVEL3";
207 case 0xC4: return "TRANSLATION_FAULT_LEVEL4";
208 case 0xC8: return "PERMISSION_FAULT";
209 case 0xC9 ... 0xCF: return "PERMISSION_FAULT";
210 case 0xD1: return "TRANSTAB_BUS_FAULT_LEVEL1";
211 case 0xD2: return "TRANSTAB_BUS_FAULT_LEVEL2";
212 case 0xD3: return "TRANSTAB_BUS_FAULT_LEVEL3";
213 case 0xD4: return "TRANSTAB_BUS_FAULT_LEVEL4";
214 case 0xD8: return "ACCESS_FLAG";
215 case 0xD9 ... 0xDF: return "ACCESS_FLAG";
216 case 0xE0 ... 0xE7: return "ADDRESS_SIZE_FAULT";
217 case 0xE8 ... 0xEF: return "MEMORY_ATTRIBUTES_FAULT";
224 int panfrost_device_resume(struct device *dev)
226 struct platform_device *pdev = to_platform_device(dev);
227 struct panfrost_device *pfdev = platform_get_drvdata(pdev);
229 panfrost_gpu_soft_reset(pfdev);
231 /* TODO: Re-enable all other address spaces */
232 panfrost_gpu_power_on(pfdev);
233 panfrost_mmu_enable(pfdev, 0);
234 panfrost_job_enable_interrupts(pfdev);
235 panfrost_devfreq_resume(pfdev);
240 int panfrost_device_suspend(struct device *dev)
242 struct platform_device *pdev = to_platform_device(dev);
243 struct panfrost_device *pfdev = platform_get_drvdata(pdev);
245 if (!panfrost_job_is_idle(pfdev))
248 panfrost_devfreq_suspend(pfdev);
249 panfrost_gpu_power_off(pfdev);