drivers/gpu/drm/panel/panel-sitronix-st7701.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2019, Amarula Solutions.
   4  * Author: Jagan Teki <jagan@amarulasolutions.com>
   5  */
   6
   7 #include <drm/drm_mipi_dsi.h>
   8 #include <drm/drm_modes.h>
   9 #include <drm/drm_panel.h>
  10 #include <drm/drm_print.h>
  11
  12 #include <linux/gpio/consumer.h>
  13 #include <linux/delay.h>
  14 #include <linux/media-bus-format.h>
  15 #include <linux/module.h>
  16 #include <linux/of_device.h>
  17 #include <linux/regulator/consumer.h>
  18 #include <linux/spi/spi.h>
  19
  20 #include <video/mipi_display.h>
  21
  22 #define SPI_DATA_FLAG                   0x100
  23
  24 /* Command2 BKx selection command */
  25 #define DSI_CMD2BKX_SEL                 0xFF
  26
  27 /* Command2, BK0 commands */
  28 #define DSI_CMD2_BK0_PVGAMCTRL          0xB0 /* Positive Voltage Gamma Control */
  29 #define DSI_CMD2_BK0_NVGAMCTRL          0xB1 /* Negative Voltage Gamma Control */
  30 #define DSI_CMD2_BK0_LNESET             0xC0 /* Display Line setting */
  31 #define DSI_CMD2_BK0_PORCTRL            0xC1 /* Porch control */
  32 #define DSI_CMD2_BK0_INVSEL             0xC2 /* Inversion selection, Frame Rate Control */
  33
  34 /* Command2, BK1 commands */
  35 #define DSI_CMD2_BK1_VRHS               0xB0 /* Vop amplitude setting */
  36 #define DSI_CMD2_BK1_VCOM               0xB1 /* VCOM amplitude setting */
  37 #define DSI_CMD2_BK1_VGHSS              0xB2 /* VGH Voltage setting */
  38 #define DSI_CMD2_BK1_TESTCMD            0xB3 /* TEST Command Setting */
  39 #define DSI_CMD2_BK1_VGLS               0xB5 /* VGL Voltage setting */
  40 #define DSI_CMD2_BK1_PWCTLR1            0xB7 /* Power Control 1 */
  41 #define DSI_CMD2_BK1_PWCTLR2            0xB8 /* Power Control 2 */
  42 #define DSI_CMD2_BK1_SPD1               0xC1 /* Source pre_drive timing set1 */
  43 #define DSI_CMD2_BK1_SPD2               0xC2 /* Source EQ2 Setting */
  44 #define DSI_CMD2_BK1_MIPISET1           0xD0 /* MIPI Setting 1 */
  45
  46 /*
  47  * Command2 with BK function selection.
  48  *
  49  * BIT[4, 0]: [CN2, BKXSEL]
  50  * 10 = CMD2BK0, Command2 BK0
  51  * 11 = CMD2BK1, Command2 BK1
  52  * 00 = Command2 disable
  53  */
  54 #define DSI_CMD2BK3_SEL                 0x13
  55 #define DSI_CMD2BK1_SEL                 0x11
  56 #define DSI_CMD2BK0_SEL                 0x10
  57 #define DSI_CMD2BKX_SEL_NONE            0x00
  58 #define SPI_CMD2BK3_SEL                 (SPI_DATA_FLAG | DSI_CMD2BK3_SEL)
  59 #define SPI_CMD2BK1_SEL                 (SPI_DATA_FLAG | DSI_CMD2BK1_SEL)
  60 #define SPI_CMD2BK0_SEL                 (SPI_DATA_FLAG | DSI_CMD2BK0_SEL)
  61 #define SPI_CMD2BKX_SEL_NONE            (SPI_DATA_FLAG | DSI_CMD2BKX_SEL_NONE)
  62
  63 /* Command2, BK0 bytes */
  64 #define DSI_LINESET_LINE                0x69
  65 #define DSI_LINESET_LDE_EN              BIT(7)
  66 #define DSI_LINESET_LINEDELTA           GENMASK(1, 0)
  67 #define DSI_CMD2_BK0_LNESET_B1          DSI_LINESET_LINEDELTA
  68 #define DSI_CMD2_BK0_LNESET_B0          (DSI_LINESET_LDE_EN | DSI_LINESET_LINE)
  69 #define DSI_INVSEL_DEFAULT              GENMASK(5, 4)
  70 #define DSI_INVSEL_NLINV                GENMASK(2, 0)
  71 #define DSI_INVSEL_RTNI                 GENMASK(2, 1)
  72 #define DSI_CMD2_BK0_INVSEL_B1          DSI_INVSEL_RTNI
  73 #define DSI_CMD2_BK0_INVSEL_B0          (DSI_INVSEL_DEFAULT | DSI_INVSEL_NLINV)
  74 #define DSI_CMD2_BK0_PORCTRL_B0(m)      ((m)->vtotal - (m)->vsync_end)
  75 #define DSI_CMD2_BK0_PORCTRL_B1(m)      ((m)->vsync_start - (m)->vdisplay)
  76
  77 /* Command2, BK1 bytes */
  78 #define DSI_CMD2_BK1_VRHA_SET           0x45
  79 #define DSI_CMD2_BK1_VCOM_SET           0x13
  80 #define DSI_CMD2_BK1_VGHSS_SET          GENMASK(2, 0)
  81 #define DSI_CMD2_BK1_TESTCMD_VAL        BIT(7)
  82 #define DSI_VGLS_DEFAULT                BIT(6)
  83 #define DSI_VGLS_SEL                    GENMASK(2, 0)
  84 #define DSI_CMD2_BK1_VGLS_SET           (DSI_VGLS_DEFAULT | DSI_VGLS_SEL)
  85 #define DSI_PWCTLR1_AP                  BIT(7) /* Gamma OP bias, max */
  86 #define DSI_PWCTLR1_APIS                BIT(2) /* Source OP input bias, min */
  87 #define DSI_PWCTLR1_APOS                BIT(0) /* Source OP output bias, min */
  88 #define DSI_CMD2_BK1_PWCTLR1_SET        (DSI_PWCTLR1_AP | DSI_PWCTLR1_APIS | \
  89                                         DSI_PWCTLR1_APOS)
  90 #define DSI_PWCTLR2_AVDD                BIT(5) /* AVDD 6.6v */
  91 #define DSI_PWCTLR2_AVCL                0x0    /* AVCL -4.4v */
  92 #define DSI_CMD2_BK1_PWCTLR2_SET        (DSI_PWCTLR2_AVDD | DSI_PWCTLR2_AVCL)
  93 #define DSI_SPD1_T2D                    BIT(3)
  94 #define DSI_CMD2_BK1_SPD1_SET           (GENMASK(6, 4) | DSI_SPD1_T2D)
  95 #define DSI_CMD2_BK1_SPD2_SET           DSI_CMD2_BK1_SPD1_SET
  96 #define DSI_MIPISET1_EOT_EN             BIT(3)
  97 #define DSI_CMD2_BK1_MIPISET1_SET       (BIT(7) | DSI_MIPISET1_EOT_EN)
  98
  99 struct st7701;
 100
 101 enum st7701_ctrl_if {
 102         ST7701_CTRL_DSI,
 103         ST7701_CTRL_SPI,
 104 };
 105
 106 struct st7701_panel_desc {
 107         const struct drm_display_mode *mode;
 108         unsigned int lanes;
 109         unsigned long flags;
 110         enum mipi_dsi_pixel_format format;
 111         u32 mediabus_format;
 112         const char *const *supply_names;
 113         unsigned int num_supplies;
 114         unsigned int panel_sleep_delay;
 115         void (*init_sequence)(struct st7701 *st7701);
 116         unsigned int conn_type;
 117         enum st7701_ctrl_if interface;
 118         u32 bus_flags;
 119 };
 120
 121 struct st7701 {
 122         struct drm_panel panel;
 123         struct mipi_dsi_device *dsi;
 124         struct spi_device *spi;
 125         const struct device *dev;
 126
 127         const struct st7701_panel_desc *desc;
 128
 129         struct regulator_bulk_data *supplies;
 130         struct gpio_desc *reset;
 131         unsigned int sleep_delay;
 132 };
 133
 134 static inline struct st7701 *panel_to_st7701(struct drm_panel *panel)
 135 {
 136         return container_of(panel, struct st7701, panel);
 137 }
 138
 139 static inline int st7701_dsi_write(struct st7701 *st7701, const void *seq,
 140                                    size_t len)
 141 {
 142         return mipi_dsi_dcs_write_buffer(st7701->dsi, seq, len);
 143 }
 144
 145 #define ST7701_DSI(st7701, seq...)                              \
 146         {                                                       \
 147                 const u8 d[] = { seq };                         \
 148                 st7701_dsi_write(st7701, d, ARRAY_SIZE(d));     \
 149         }
 150
 151 #define ST7701_SPI(st7701, seq...)                              \
 152         {                                                       \
 153                 const u16 d[] = { seq };                        \
 154                 struct spi_transfer xfer = { };                 \
 155                 struct spi_message spi;                         \
 156                                                                 \
 157                 spi_message_init(&spi);                         \
 158                                                                 \
 159                 xfer.tx_buf = d;                                \
 160                 xfer.bits_per_word = 9;                         \
 161                 xfer.len = sizeof(u16) * ARRAY_SIZE(d);         \
 162                                                                 \
 163                 spi_message_add_tail(&xfer, &spi);              \
 164                 spi_sync((st7701)->spi, &spi);                  \
 165         }
 166
 167 static void ts8550b_init_sequence(struct st7701 *st7701)
 168 {
 169         const struct drm_display_mode *mode = st7701->desc->mode;
 170
 171         ST7701_DSI(st7701, MIPI_DCS_SOFT_RESET, 0x00);
 172
 173         /* We need to wait 5ms before sending new commands */
 174         msleep(5);
 175
 176         ST7701_DSI(st7701, MIPI_DCS_EXIT_SLEEP_MODE, 0x00);
 177
 178         msleep(st7701->sleep_delay);
 179
 180         /* Command2, BK0 */
 181         ST7701_DSI(st7701, DSI_CMD2BKX_SEL,
 182                    0x77, 0x01, 0x00, 0x00, DSI_CMD2BK0_SEL);
 183         ST7701_DSI(st7701, DSI_CMD2_BK0_PVGAMCTRL, 0x00, 0x0E, 0x15, 0x0F,
 184                    0x11, 0x08, 0x08, 0x08, 0x08, 0x23, 0x04, 0x13, 0x12,
 185                    0x2B, 0x34, 0x1F);
 186         ST7701_DSI(st7701, DSI_CMD2_BK0_NVGAMCTRL, 0x00, 0x0E, 0x95, 0x0F,
 187                    0x13, 0x07, 0x09, 0x08, 0x08, 0x22, 0x04, 0x10, 0x0E,
 188                    0x2C, 0x34, 0x1F);
 189         ST7701_DSI(st7701, DSI_CMD2_BK0_LNESET,
 190                    DSI_CMD2_BK0_LNESET_B0, DSI_CMD2_BK0_LNESET_B1);
 191         ST7701_DSI(st7701, DSI_CMD2_BK0_PORCTRL,
 192                    DSI_CMD2_BK0_PORCTRL_B0(mode),
 193                    DSI_CMD2_BK0_PORCTRL_B1(mode));
 194         ST7701_DSI(st7701, DSI_CMD2_BK0_INVSEL,
 195                    DSI_CMD2_BK0_INVSEL_B0, DSI_CMD2_BK0_INVSEL_B1);
 196
 197         /* Command2, BK1 */
 198         ST7701_DSI(st7701, DSI_CMD2BKX_SEL,
 199                         0x77, 0x01, 0x00, 0x00, DSI_CMD2BK1_SEL);
 200         ST7701_DSI(st7701, DSI_CMD2_BK1_VRHS, DSI_CMD2_BK1_VRHA_SET);
 201         ST7701_DSI(st7701, DSI_CMD2_BK1_VCOM, DSI_CMD2_BK1_VCOM_SET);
 202         ST7701_DSI(st7701, DSI_CMD2_BK1_VGHSS, DSI_CMD2_BK1_VGHSS_SET);
 203         ST7701_DSI(st7701, DSI_CMD2_BK1_TESTCMD, DSI_CMD2_BK1_TESTCMD_VAL);
 204         ST7701_DSI(st7701, DSI_CMD2_BK1_VGLS, DSI_CMD2_BK1_VGLS_SET);
 205         ST7701_DSI(st7701, DSI_CMD2_BK1_PWCTLR1, DSI_CMD2_BK1_PWCTLR1_SET);
 206         ST7701_DSI(st7701, DSI_CMD2_BK1_PWCTLR2, DSI_CMD2_BK1_PWCTLR2_SET);
 207         ST7701_DSI(st7701, DSI_CMD2_BK1_SPD1, DSI_CMD2_BK1_SPD1_SET);
 208         ST7701_DSI(st7701, DSI_CMD2_BK1_SPD2, DSI_CMD2_BK1_SPD2_SET);
 209         ST7701_DSI(st7701, DSI_CMD2_BK1_MIPISET1, DSI_CMD2_BK1_MIPISET1_SET);
 210
 211         /**
 212          * ST7701_SPEC_V1.2 is unable to provide enough information above this
 213          * specific command sequence, so grab the same from vendor BSP driver.
 214          */
 215         ST7701_DSI(st7701, 0xE0, 0x00, 0x00, 0x02);
 216         ST7701_DSI(st7701, 0xE1, 0x0B, 0x00, 0x0D, 0x00, 0x0C, 0x00, 0x0E,
 217                    0x00, 0x00, 0x44, 0x44);
 218         ST7701_DSI(st7701, 0xE2, 0x33, 0x33, 0x44, 0x44, 0x64, 0x00, 0x66,
 219                    0x00, 0x65, 0x00, 0x67, 0x00, 0x00);
 220         ST7701_DSI(st7701, 0xE3, 0x00, 0x00, 0x33, 0x33);
 221         ST7701_DSI(st7701, 0xE4, 0x44, 0x44);
 222         ST7701_DSI(st7701, 0xE5, 0x0C, 0x78, 0x3C, 0xA0, 0x0E, 0x78, 0x3C,
 223                    0xA0, 0x10, 0x78, 0x3C, 0xA0, 0x12, 0x78, 0x3C, 0xA0);
 224         ST7701_DSI(st7701, 0xE6, 0x00, 0x00, 0x33, 0x33);
 225         ST7701_DSI(st7701, 0xE7, 0x44, 0x44);
 226         ST7701_DSI(st7701, 0xE8, 0x0D, 0x78, 0x3C, 0xA0, 0x0F, 0x78, 0x3C,
 227                    0xA0, 0x11, 0x78, 0x3C, 0xA0, 0x13, 0x78, 0x3C, 0xA0);
 228         ST7701_DSI(st7701, 0xEB, 0x02, 0x02, 0x39, 0x39, 0xEE, 0x44, 0x00);
 229         ST7701_DSI(st7701, 0xEC, 0x00, 0x00);
 230         ST7701_DSI(st7701, 0xED, 0xFF, 0xF1, 0x04, 0x56, 0x72, 0x3F, 0xFF,
 231                    0xFF, 0xFF, 0xFF, 0xF3, 0x27, 0x65, 0x40, 0x1F, 0xFF);
 232
 233         /* disable Command2 */
 234         ST7701_DSI(st7701, DSI_CMD2BKX_SEL,
 235                    0x77, 0x01, 0x00, 0x00, DSI_CMD2BKX_SEL_NONE);
 236 }
 237
 238 static void txw210001b0_init_sequence(struct st7701 *st7701)
 239 {
 240         ST7701_SPI(st7701, MIPI_DCS_SOFT_RESET);
 241
 242         usleep_range(5000, 7000);
 243
 244         ST7701_SPI(st7701, DSI_CMD2BKX_SEL,
 245                    0x177, 0x101, 0x100, 0x100, SPI_CMD2BK0_SEL);
 246
 247         ST7701_SPI(st7701, DSI_CMD2_BK0_LNESET, 0x13B, 0x100);
 248
 249         ST7701_SPI(st7701, DSI_CMD2_BK0_PORCTRL, 0x10B, 0x102);
 250
 251         ST7701_SPI(st7701, DSI_CMD2_BK0_INVSEL, 0x100, 0x102);
 252
 253         ST7701_SPI(st7701, 0xCC, 0x110);
 254
 255         /*
 256          * Gamma option B:
 257          * Positive Voltage Gamma Control
 258          */
 259         ST7701_SPI(st7701, DSI_CMD2_BK0_PVGAMCTRL,
 260                    0x102, 0x113, 0x11B, 0x10D, 0x110, 0x105, 0x108, 0x107,
 261                    0x107, 0x124, 0x104, 0x111, 0x10E, 0x12C, 0x133, 0x11D);
 262
 263         /* Negative Voltage Gamma Control */
 264         ST7701_SPI(st7701, DSI_CMD2_BK0_NVGAMCTRL,
 265                    0x105, 0x113, 0x11B, 0x10D, 0x111, 0x105, 0x108, 0x107,
 266                    0x107, 0x124, 0x104, 0x111, 0x10E, 0x12C, 0x133, 0x11D);
 267
 268         ST7701_SPI(st7701, DSI_CMD2BKX_SEL,
 269                    0x177, 0x101, 0x100, 0x100, SPI_CMD2BK1_SEL);
 270
 271         ST7701_SPI(st7701, DSI_CMD2_BK1_VRHS, 0x15D);
 272
 273         ST7701_SPI(st7701, DSI_CMD2_BK1_VCOM, 0x143);
 274
 275         ST7701_SPI(st7701, DSI_CMD2_BK1_VGHSS, 0x181);
 276
 277         ST7701_SPI(st7701, DSI_CMD2_BK1_TESTCMD, 0x180);
 278
 279         ST7701_SPI(st7701, DSI_CMD2_BK1_VGLS, 0x143);
 280
 281         ST7701_SPI(st7701, DSI_CMD2_BK1_PWCTLR1, 0x185);
 282
 283         ST7701_SPI(st7701, DSI_CMD2_BK1_PWCTLR2, 0x120);
 284
 285         ST7701_SPI(st7701, DSI_CMD2_BK1_SPD1, 0x178);
 286
 287         ST7701_SPI(st7701, DSI_CMD2_BK1_SPD2, 0x178);
 288
 289         ST7701_SPI(st7701, DSI_CMD2_BK1_MIPISET1, 0x188);
 290
 291         ST7701_SPI(st7701, 0xE0, 0x100, 0x100, 0x102);
 292
 293         ST7701_SPI(st7701, 0xE1,
 294                    0x103, 0x1A0, 0x100, 0x100, 0x104, 0x1A0, 0x100, 0x100,
 295                    0x100, 0x120, 0x120);
 296
 297         ST7701_SPI(st7701, 0xE2,
 298                    0x100, 0x100, 0x100, 0x100, 0x100, 0x100, 0x100, 0x100,
 299                    0x100, 0x100, 0x100, 0x100, 0x100);
 300
 301         ST7701_SPI(st7701, 0xE3, 0x100, 0x100, 0x111, 0x100);
 302
 303         ST7701_SPI(st7701, 0xE4, 0x122, 0x100);
 304
 305         ST7701_SPI(st7701, 0xE5,
 306                    0x105, 0x1EC, 0x1A0, 0x1A0, 0x107, 0x1EE, 0x1A0, 0x1A0,
 307                    0x100, 0x100, 0x100, 0x100, 0x100, 0x100, 0x100, 0x100);
 308
 309         ST7701_SPI(st7701, 0xE6, 0x100, 0x100, 0x111, 0x100);
 310
 311         ST7701_SPI(st7701, 0xE7, 0x122, 0x100);
 312
 313         ST7701_SPI(st7701, 0xE8,
 314                    0x106, 0x1ED, 0x1A0, 0x1A0, 0x108, 0x1EF, 0x1A0, 0x1A0,
 315                    0x100, 0x100, 0x100, 0x100, 0x100, 0x100, 0x100, 0x100);
 316
 317         ST7701_SPI(st7701, 0xEB,
 318                    0x100, 0x100, 0x140, 0x140, 0x100, 0x100, 0x100);
 319
 320         ST7701_SPI(st7701, 0xED,
 321                    0x1FF, 0x1FF, 0x1FF, 0x1BA, 0x10A, 0x1BF, 0x145, 0x1FF,
 322                    0x1FF, 0x154, 0x1FB, 0x1A0, 0x1AB, 0x1FF, 0x1FF, 0x1FF);
 323
 324         ST7701_SPI(st7701, 0xEF, 0x110, 0x10D, 0x104, 0x108, 0x13F, 0x11F);
 325
 326         ST7701_SPI(st7701, DSI_CMD2BKX_SEL,
 327                    0x177, 0x101, 0x100, 0x100, SPI_CMD2BK3_SEL);
 328
 329         ST7701_SPI(st7701, 0xEF, 0x108);
 330
 331         ST7701_SPI(st7701, DSI_CMD2BKX_SEL,
 332                    0x177, 0x101, 0x100, 0x100, SPI_CMD2BKX_SEL_NONE);
 333
 334         ST7701_SPI(st7701, 0xCD, 0x108);  /* RGB format COLCTRL */
 335
 336         ST7701_SPI(st7701, 0x36, 0x108); /* MadCtl */
 337
 338         ST7701_SPI(st7701, 0x3A, 0x166);  /* Colmod */
 339
 340         ST7701_SPI(st7701, MIPI_DCS_EXIT_SLEEP_MODE);
 341 }
 342
 343 static int st7701_prepare(struct drm_panel *panel)
 344 {
 345         struct st7701 *st7701 = panel_to_st7701(panel);
 346         int ret;
 347
 348         gpiod_set_value(st7701->reset, 0);
 349
 350         ret = regulator_bulk_enable(st7701->desc->num_supplies,
 351                                     st7701->supplies);
 352         if (ret < 0)
 353                 return ret;
 354         msleep(20);
 355
 356         gpiod_set_value(st7701->reset, 1);
 357         msleep(150);
 358
 359         st7701->desc->init_sequence(st7701);
 360
 361         return 0;
 362 }
 363
 364 static int st7701_enable(struct drm_panel *panel)
 365 {
 366         struct st7701 *st7701 = panel_to_st7701(panel);
 367
 368         switch (st7701->desc->interface) {
 369         case ST7701_CTRL_DSI:
 370                 ST7701_DSI(st7701, MIPI_DCS_SET_DISPLAY_ON, 0x00);
 371                 break;
 372         case ST7701_CTRL_SPI:
 373                 ST7701_SPI(st7701, MIPI_DCS_SET_DISPLAY_ON);
 374                 msleep(30);
 375                 break;
 376         }
 377
 378         return 0;
 379 }
 380
 381 static int st7701_disable(struct drm_panel *panel)
 382 {
 383         struct st7701 *st7701 = panel_to_st7701(panel);
 384
 385         switch (st7701->desc->interface) {
 386         case ST7701_CTRL_DSI:
 387                 ST7701_DSI(st7701, MIPI_DCS_SET_DISPLAY_OFF, 0x00);
 388                 break;
 389         case ST7701_CTRL_SPI:
 390                 ST7701_SPI(st7701, MIPI_DCS_SET_DISPLAY_OFF);
 391                 break;
 392         }
 393
 394         return 0;
 395 }
 396
 397 static int st7701_unprepare(struct drm_panel *panel)
 398 {
 399         struct st7701 *st7701 = panel_to_st7701(panel);
 400
 401         switch (st7701->desc->interface) {
 402         case ST7701_CTRL_DSI:
 403                 ST7701_DSI(st7701, MIPI_DCS_ENTER_SLEEP_MODE, 0x00);
 404                 break;
 405         case ST7701_CTRL_SPI:
 406                 ST7701_SPI(st7701, MIPI_DCS_ENTER_SLEEP_MODE);
 407                 break;
 408         }
 409
 410         msleep(st7701->sleep_delay);
 411
 412         gpiod_set_value(st7701->reset, 0);
 413
 414         /**
 415          * During the Resetting period, the display will be blanked
 416          * (The display is entering blanking sequence, which maximum
 417          * time is 120 ms, when Reset Starts in Sleep Out –mode. The
 418          * display remains the blank state in Sleep In –mode.) and
 419          * then return to Default condition for Hardware Reset.
 420          *
 421          * So we need wait sleep_delay time to make sure reset completed.
 422          */
 423         msleep(st7701->sleep_delay);
 424
 425         regulator_bulk_disable(st7701->desc->num_supplies, st7701->supplies);
 426
 427         return 0;
 428 }
 429
 430 static int st7701_get_modes(struct drm_panel *panel,
 431                             struct drm_connector *connector)
 432 {
 433         struct st7701 *st7701 = panel_to_st7701(panel);
 434         const struct drm_display_mode *desc_mode = st7701->desc->mode;
 435         struct drm_display_mode *mode;
 436
 437         mode = drm_mode_duplicate(connector->dev, desc_mode);
 438         if (!mode) {
 439                 dev_err(st7701->dev, "failed to add mode %ux%u@%u\n",
 440                         desc_mode->hdisplay, desc_mode->vdisplay,
 441                         drm_mode_vrefresh(desc_mode));
 442                 return -ENOMEM;
 443         }
 444
 445         drm_mode_set_name(mode);
 446         drm_mode_probed_add(connector, mode);
 447
 448         if (st7701->desc->mediabus_format)
 449                 drm_display_info_set_bus_formats(&connector->display_info,
 450                                                  &st7701->desc->mediabus_format,
 451                                                  1);
 452         connector->display_info.bus_flags = 0;
 453
 454         connector->display_info.width_mm = desc_mode->width_mm;
 455         connector->display_info.height_mm = desc_mode->height_mm;
 456
 457         if (st7701->desc->bus_flags)
 458                 connector->display_info.bus_flags = st7701->desc->bus_flags;
 459
 460         return 1;
 461 }
 462
 463 static const struct drm_panel_funcs st7701_funcs = {
 464         .disable        = st7701_disable,
 465         .unprepare      = st7701_unprepare,
 466         .prepare        = st7701_prepare,
 467         .enable         = st7701_enable,
 468         .get_modes      = st7701_get_modes,
 469 };
 470
 471 static const struct drm_display_mode ts8550b_mode = {
 472         .clock          = 27500,
 473
 474         .hdisplay       = 480,
 475         .hsync_start    = 480 + 38,
 476         .hsync_end      = 480 + 38 + 12,
 477         .htotal         = 480 + 38 + 12 + 12,
 478
 479         .vdisplay       = 854,
 480         .vsync_start    = 854 + 18,
 481         .vsync_end      = 854 + 18 + 8,
 482         .vtotal         = 854 + 18 + 8 + 4,
 483
 484         .width_mm       = 69,
 485         .height_mm      = 139,
 486
 487         .type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,
 488 };
 489
 490 static const char * const ts8550b_supply_names[] = {
 491         "VCC",
 492         "IOVCC",
 493 };
 494
 495 static const struct st7701_panel_desc ts8550b_desc = {
 496         .mode = &ts8550b_mode,
 497         .lanes = 2,
 498         .flags = MIPI_DSI_MODE_VIDEO,
 499         .format = MIPI_DSI_FMT_RGB888,
 500         .supply_names = ts8550b_supply_names,
 501         .num_supplies = ARRAY_SIZE(ts8550b_supply_names),
 502         .panel_sleep_delay = 80, /* panel need extra 80ms for sleep out cmd */
 503         .init_sequence = ts8550b_init_sequence,
 504         .conn_type = DRM_MODE_CONNECTOR_DSI,
 505         .interface = ST7701_CTRL_DSI,
 506 };
 507
 508 static const struct drm_display_mode txw210001b0_mode = {
 509         .clock          = 19200,
 510
 511         .hdisplay       = 480,
 512         .hsync_start    = 480 + 10,
 513         .hsync_end      = 480 + 10 + 16,
 514         .htotal         = 480 + 10 + 16 + 56,
 515
 516         .vdisplay       = 480,
 517         .vsync_start    = 480 + 15,
 518         .vsync_end      = 480 + 15 + 60,
 519         .vtotal         = 480 + 15 + 60 + 15,
 520
 521         .width_mm       = 53,
 522         .height_mm      = 53,
 523         .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
 524
 525         .type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,
 526 };
 527
 528 static const struct st7701_panel_desc txw210001b0_desc = {
 529         .mode = &txw210001b0_mode,
 530         .mediabus_format = MEDIA_BUS_FMT_RGB888_1X24,
 531         .supply_names = ts8550b_supply_names,
 532         .num_supplies = ARRAY_SIZE(ts8550b_supply_names),
 533         .init_sequence = txw210001b0_init_sequence,
 534         .conn_type = DRM_MODE_CONNECTOR_DPI,
 535         .interface = ST7701_CTRL_SPI,
 536         .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
 537 };
 538
 539 static const struct st7701_panel_desc hyperpixel2r_desc = {
 540         .mode = &txw210001b0_mode,
 541         .mediabus_format = MEDIA_BUS_FMT_RGB666_1X24_CPADHI,
 542         .supply_names = ts8550b_supply_names,
 543         .num_supplies = ARRAY_SIZE(ts8550b_supply_names),
 544         .init_sequence = txw210001b0_init_sequence,
 545         .conn_type = DRM_MODE_CONNECTOR_DPI,
 546         .interface = ST7701_CTRL_SPI,
 547         .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
 548 };
 549
 550 static int st7701_probe(struct device *dev, struct st7701 **ret_st7701)
 551 {
 552         const struct st7701_panel_desc *desc;
 553         struct st7701 *st7701;
 554         int ret, i;
 555
 556         st7701 = devm_kzalloc(dev, sizeof(*st7701), GFP_KERNEL);
 557         if (!st7701)
 558                 return -ENOMEM;
 559
 560         desc = of_device_get_match_data(dev);
 561         if (!desc)
 562                 return -EINVAL;
 563
 564         st7701->supplies = devm_kcalloc(dev, desc->num_supplies,
 565                                         sizeof(*st7701->supplies),
 566                                         GFP_KERNEL);
 567         if (!st7701->supplies)
 568                 return -ENOMEM;
 569
 570         for (i = 0; i < desc->num_supplies; i++)
 571                 st7701->supplies[i].supply = desc->supply_names[i];
 572
 573         ret = devm_regulator_bulk_get(dev, desc->num_supplies,
 574                                       st7701->supplies);
 575         if (ret < 0)
 576                 return ret;
 577
 578         st7701->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
 579         if (IS_ERR(st7701->reset)) {
 580                 dev_err(dev, "Couldn't get our reset GPIO\n");
 581                 return PTR_ERR(st7701->reset);
 582         }
 583
 584         drm_panel_init(&st7701->panel, dev, &st7701_funcs,
 585                        desc->conn_type);
 586
 587         /**
 588          * Once sleep out has been issued, ST7701 IC required to wait 120ms
 589          * before initiating new commands.
 590          *
 591          * On top of that some panels might need an extra delay to wait, so
 592          * add panel specific delay for those cases. As now this panel specific
 593          * delay information is referenced from those panel BSP driver, example
 594          * ts8550b and there is no valid documentation for that.
 595          */
 596         st7701->sleep_delay = 120 + desc->panel_sleep_delay;
 597
 598         ret = drm_panel_of_backlight(&st7701->panel);
 599         if (ret)
 600                 return ret;
 601
 602         drm_panel_add(&st7701->panel);
 603
 604         st7701->desc = desc;
 605         st7701->dev = dev;
 606
 607         *ret_st7701 = st7701;
 608
 609         return 0;
 610 }
 611
 612 static int st7701_dsi_probe(struct mipi_dsi_device *dsi)
 613 {
 614         struct st7701 *st7701;
 615         int ret;
 616
 617         ret = st7701_probe(&dsi->dev, &st7701);
 618
 619         if (ret)
 620                 return ret;
 621
 622         dsi->mode_flags = st7701->desc->flags;
 623         dsi->format = st7701->desc->format;
 624         dsi->lanes = st7701->desc->lanes;
 625
 626         mipi_dsi_set_drvdata(dsi, st7701);
 627         st7701->dsi = dsi;
 628
 629         return mipi_dsi_attach(dsi);
 630 }
 631
 632 static int st7701_dsi_remove(struct mipi_dsi_device *dsi)
 633 {
 634         struct st7701 *st7701 = mipi_dsi_get_drvdata(dsi);
 635
 636         mipi_dsi_detach(dsi);
 637         drm_panel_remove(&st7701->panel);
 638
 639         return 0;
 640 }
 641
 642 static const struct of_device_id st7701_dsi_of_match[] = {
 643         { .compatible = "techstar,ts8550b", .data = &ts8550b_desc },
 644         { }
 645 };
 646 MODULE_DEVICE_TABLE(of, st7701_dsi_of_match);
 647
 648 static struct mipi_dsi_driver st7701_dsi_driver = {
 649         .probe          = st7701_dsi_probe,
 650         .remove         = st7701_dsi_remove,
 651         .driver = {
 652                 .name           = "st7701",
 653                 .of_match_table = st7701_dsi_of_match,
 654         },
 655 };
 656
 657 /* SPI display  probe */
 658 static const struct of_device_id st7701_spi_of_match[] = {
 659         {       .compatible = "txw,txw210001b0",
 660                 .data = &txw210001b0_desc,
 661         }, {
 662                 .compatible = "pimoroni,hyperpixel2round",
 663                 .data = &hyperpixel2r_desc,
 664         }, {
 665                 /* sentinel */
 666         }
 667 };
 668 MODULE_DEVICE_TABLE(of, st7701_spi_of_match);
 669
 670 static int st7701_spi_probe(struct spi_device *spi)
 671 {
 672         struct st7701 *st7701;
 673         int ret;
 674
 675         spi->mode = SPI_MODE_3;
 676         spi->bits_per_word = 9;
 677         ret = spi_setup(spi);
 678         if (ret < 0) {
 679                 dev_err(&spi->dev, "failed to setup SPI: %d\n", ret);
 680                 return ret;
 681         }
 682
 683         ret = st7701_probe(&spi->dev, &st7701);
 684
 685         if (ret)
 686                 return ret;
 687
 688         spi_set_drvdata(spi, st7701);
 689         st7701->spi = spi;
 690
 691         return 0;
 692 }
 693
 694 static int st7701_spi_remove(struct spi_device *spi)
 695 {
 696         struct st7701 *ctx = spi_get_drvdata(spi);
 697
 698         drm_panel_remove(&ctx->panel);
 699
 700         return 0;
 701 }
 702
 703 static const struct spi_device_id st7701_spi_ids[] = {
 704         { "txw210001b0", 0 },
 705         { "hyperpixel2round", 0 },
 706         { /* sentinel */ }
 707 };
 708 MODULE_DEVICE_TABLE(spi, st7701_spi_ids);
 709
 710 static struct spi_driver st7701_spi_driver = {
 711         .probe = st7701_spi_probe,
 712         .remove = st7701_spi_remove,
 713         .driver = {
 714                 .name = "st7701",
 715                 .of_match_table = st7701_spi_of_match,
 716         },
 717         .id_table = st7701_spi_ids,
 718 };
 719
 720 static int __init panel_st7701_init(void)
 721 {
 722         int err;
 723
 724         err = spi_register_driver(&st7701_spi_driver);
 725         if (err < 0)
 726                 return err;
 727
 728         if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) {
 729                 err = mipi_dsi_driver_register(&st7701_dsi_driver);
 730                 if (err < 0)
 731                         goto err_did_spi_register;
 732         }
 733
 734         return 0;
 735
 736 err_did_spi_register:
 737         spi_unregister_driver(&st7701_spi_driver);
 738
 739         return err;
 740 }
 741 module_init(panel_st7701_init);
 742
 743 static void __exit panel_st7701_exit(void)
 744 {
 745         if (IS_ENABLED(CONFIG_DRM_MIPI_DSI))
 746                 mipi_dsi_driver_unregister(&st7701_dsi_driver);
 747
 748         spi_unregister_driver(&st7701_spi_driver);
 749 }
 750 module_exit(panel_st7701_exit);
 751
 752 MODULE_AUTHOR("Jagan Teki <jagan@amarulasolutions.com>");
 753 MODULE_DESCRIPTION("Sitronix ST7701 LCD Panel Driver");
 754 MODULE_LICENSE("GPL");