2 * Copyright (C) 2013, NVIDIA Corporation. All rights reserved.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sub license,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the
12 * next paragraph) shall be included in all copies or substantial portions
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 #include <linux/delay.h>
25 #include <linux/gpio/consumer.h>
26 #include <linux/module.h>
27 #include <linux/of_platform.h>
28 #include <linux/platform_device.h>
29 #include <linux/pm_runtime.h>
30 #include <linux/regulator/consumer.h>
32 #include <video/display_timing.h>
33 #include <video/of_display_timing.h>
34 #include <video/videomode.h>
36 #include <drm/drm_crtc.h>
37 #include <drm/drm_device.h>
38 #include <drm/drm_mipi_dsi.h>
39 #include <drm/drm_panel.h>
42 * struct panel_desc - Describes a simple panel.
46 * @modes: Pointer to array of fixed modes appropriate for this panel.
48 * If only one mode then this can just be the address of the mode.
49 * NOTE: cannot be used with "timings" and also if this is specified
50 * then you cannot override the mode in the device tree.
52 const struct drm_display_mode *modes;
54 /** @num_modes: Number of elements in modes array. */
55 unsigned int num_modes;
58 * @timings: Pointer to array of display timings
60 * NOTE: cannot be used with "modes" and also these will be used to
61 * validate a device tree override if one is present.
63 const struct display_timing *timings;
65 /** @num_timings: Number of elements in timings array. */
66 unsigned int num_timings;
68 /** @bpc: Bits per color. */
71 /** @size: Structure containing the physical size of this panel. */
74 * @size.width: Width (in mm) of the active display area.
79 * @size.height: Height (in mm) of the active display area.
84 /** @delay: Structure containing various delay values for this panel. */
87 * @delay.prepare: Time for the panel to become ready.
89 * The time (in milliseconds) that it takes for the panel to
90 * become ready and start receiving video data
95 * @delay.enable: Time for the panel to display a valid frame.
97 * The time (in milliseconds) that it takes for the panel to
98 * display the first valid frame after starting to receive
104 * @delay.disable: Time for the panel to turn the display off.
106 * The time (in milliseconds) that it takes for the panel to
107 * turn the display off (no content is visible).
109 unsigned int disable;
112 * @delay.unprepare: Time to power down completely.
114 * The time (in milliseconds) that it takes for the panel
115 * to power itself down completely.
117 * This time is used to prevent a future "prepare" from
118 * starting until at least this many milliseconds has passed.
119 * If at prepare time less time has passed since unprepare
120 * finished, the driver waits for the remaining time.
122 unsigned int unprepare;
125 /** @bus_format: See MEDIA_BUS_FMT_... defines. */
128 /** @bus_flags: See DRM_BUS_FLAG_... defines. */
131 /** @connector_type: LVDS, eDP, DSI, DPI, etc. */
135 struct panel_simple {
136 struct drm_panel base;
141 ktime_t prepared_time;
142 ktime_t unprepared_time;
144 const struct panel_desc *desc;
146 struct regulator *supply;
147 struct i2c_adapter *ddc;
149 struct gpio_desc *enable_gpio;
153 struct drm_display_mode override_mode;
155 enum drm_panel_orientation orientation;
158 static inline struct panel_simple *to_panel_simple(struct drm_panel *panel)
160 return container_of(panel, struct panel_simple, base);
163 static unsigned int panel_simple_get_timings_modes(struct panel_simple *panel,
164 struct drm_connector *connector)
166 struct drm_display_mode *mode;
167 unsigned int i, num = 0;
169 for (i = 0; i < panel->desc->num_timings; i++) {
170 const struct display_timing *dt = &panel->desc->timings[i];
173 videomode_from_timing(dt, &vm);
174 mode = drm_mode_create(connector->dev);
176 dev_err(panel->base.dev, "failed to add mode %ux%u\n",
177 dt->hactive.typ, dt->vactive.typ);
181 drm_display_mode_from_videomode(&vm, mode);
183 mode->type |= DRM_MODE_TYPE_DRIVER;
185 if (panel->desc->num_timings == 1)
186 mode->type |= DRM_MODE_TYPE_PREFERRED;
188 drm_mode_probed_add(connector, mode);
195 static unsigned int panel_simple_get_display_modes(struct panel_simple *panel,
196 struct drm_connector *connector)
198 struct drm_display_mode *mode;
199 unsigned int i, num = 0;
201 for (i = 0; i < panel->desc->num_modes; i++) {
202 const struct drm_display_mode *m = &panel->desc->modes[i];
204 mode = drm_mode_duplicate(connector->dev, m);
206 dev_err(panel->base.dev, "failed to add mode %ux%u@%u\n",
207 m->hdisplay, m->vdisplay,
208 drm_mode_vrefresh(m));
212 mode->type |= DRM_MODE_TYPE_DRIVER;
214 if (panel->desc->num_modes == 1)
215 mode->type |= DRM_MODE_TYPE_PREFERRED;
217 drm_mode_set_name(mode);
219 drm_mode_probed_add(connector, mode);
226 static int panel_simple_get_non_edid_modes(struct panel_simple *panel,
227 struct drm_connector *connector)
229 struct drm_display_mode *mode;
230 bool has_override = panel->override_mode.type;
231 unsigned int num = 0;
237 mode = drm_mode_duplicate(connector->dev,
238 &panel->override_mode);
240 drm_mode_probed_add(connector, mode);
243 dev_err(panel->base.dev, "failed to add override mode\n");
247 /* Only add timings if override was not there or failed to validate */
248 if (num == 0 && panel->desc->num_timings)
249 num = panel_simple_get_timings_modes(panel, connector);
252 * Only add fixed modes if timings/override added no mode.
254 * We should only ever have either the display timings specified
255 * or a fixed mode. Anything else is rather bogus.
257 WARN_ON(panel->desc->num_timings && panel->desc->num_modes);
259 num = panel_simple_get_display_modes(panel, connector);
261 connector->display_info.bpc = panel->desc->bpc;
262 connector->display_info.width_mm = panel->desc->size.width;
263 connector->display_info.height_mm = panel->desc->size.height;
264 if (panel->desc->bus_format)
265 drm_display_info_set_bus_formats(&connector->display_info,
266 &panel->desc->bus_format, 1);
267 connector->display_info.bus_flags = panel->desc->bus_flags;
272 static void panel_simple_wait(ktime_t start_ktime, unsigned int min_ms)
274 ktime_t now_ktime, min_ktime;
279 min_ktime = ktime_add(start_ktime, ms_to_ktime(min_ms));
280 now_ktime = ktime_get();
282 if (ktime_before(now_ktime, min_ktime))
283 msleep(ktime_to_ms(ktime_sub(min_ktime, now_ktime)) + 1);
286 static int panel_simple_disable(struct drm_panel *panel)
288 struct panel_simple *p = to_panel_simple(panel);
293 if (p->desc->delay.disable)
294 msleep(p->desc->delay.disable);
301 static int panel_simple_suspend(struct device *dev)
303 struct panel_simple *p = dev_get_drvdata(dev);
305 gpiod_set_value_cansleep(p->enable_gpio, 0);
306 regulator_disable(p->supply);
307 p->unprepared_time = ktime_get();
315 static int panel_simple_unprepare(struct drm_panel *panel)
317 struct panel_simple *p = to_panel_simple(panel);
320 /* Unpreparing when already unprepared is a no-op */
324 pm_runtime_mark_last_busy(panel->dev);
325 ret = pm_runtime_put_autosuspend(panel->dev);
333 static int panel_simple_resume(struct device *dev)
335 struct panel_simple *p = dev_get_drvdata(dev);
338 panel_simple_wait(p->unprepared_time, p->desc->delay.unprepare);
340 err = regulator_enable(p->supply);
342 dev_err(dev, "failed to enable supply: %d\n", err);
346 gpiod_set_value_cansleep(p->enable_gpio, 1);
348 if (p->desc->delay.prepare)
349 msleep(p->desc->delay.prepare);
351 p->prepared_time = ktime_get();
356 static int panel_simple_prepare(struct drm_panel *panel)
358 struct panel_simple *p = to_panel_simple(panel);
361 /* Preparing when already prepared is a no-op */
365 ret = pm_runtime_get_sync(panel->dev);
367 pm_runtime_put_autosuspend(panel->dev);
376 static int panel_simple_enable(struct drm_panel *panel)
378 struct panel_simple *p = to_panel_simple(panel);
383 if (p->desc->delay.enable)
384 msleep(p->desc->delay.enable);
391 static int panel_simple_get_modes(struct drm_panel *panel,
392 struct drm_connector *connector)
394 struct panel_simple *p = to_panel_simple(panel);
397 /* probe EDID if a DDC bus is available */
399 pm_runtime_get_sync(panel->dev);
402 p->edid = drm_get_edid(connector, p->ddc);
405 num += drm_add_edid_modes(connector, p->edid);
407 pm_runtime_mark_last_busy(panel->dev);
408 pm_runtime_put_autosuspend(panel->dev);
411 /* add hard-coded panel modes */
412 num += panel_simple_get_non_edid_modes(p, connector);
414 /* set up connector's "panel orientation" property */
415 drm_connector_set_panel_orientation(connector, p->orientation);
420 static int panel_simple_get_timings(struct drm_panel *panel,
421 unsigned int num_timings,
422 struct display_timing *timings)
424 struct panel_simple *p = to_panel_simple(panel);
427 if (p->desc->num_timings < num_timings)
428 num_timings = p->desc->num_timings;
431 for (i = 0; i < num_timings; i++)
432 timings[i] = p->desc->timings[i];
434 return p->desc->num_timings;
437 static const struct drm_panel_funcs panel_simple_funcs = {
438 .disable = panel_simple_disable,
439 .unprepare = panel_simple_unprepare,
440 .prepare = panel_simple_prepare,
441 .enable = panel_simple_enable,
442 .get_modes = panel_simple_get_modes,
443 .get_timings = panel_simple_get_timings,
446 static struct panel_desc panel_dpi;
448 static int panel_dpi_probe(struct device *dev,
449 struct panel_simple *panel)
451 struct display_timing *timing;
452 const struct device_node *np;
453 struct panel_desc *desc;
454 unsigned int bus_flags;
459 desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL);
463 timing = devm_kzalloc(dev, sizeof(*timing), GFP_KERNEL);
467 ret = of_get_display_timing(np, "panel-timing", timing);
469 dev_err(dev, "%pOF: no panel-timing node found for \"panel-dpi\" binding\n",
474 desc->timings = timing;
475 desc->num_timings = 1;
477 of_property_read_u32(np, "width-mm", &desc->size.width);
478 of_property_read_u32(np, "height-mm", &desc->size.height);
480 /* Extract bus_flags from display_timing */
482 vm.flags = timing->flags;
483 drm_bus_flags_from_videomode(&vm, &bus_flags);
484 desc->bus_flags = bus_flags;
486 /* We do not know the connector for the DT node, so guess it */
487 desc->connector_type = DRM_MODE_CONNECTOR_DPI;
494 #define PANEL_SIMPLE_BOUNDS_CHECK(to_check, bounds, field) \
495 (to_check->field.typ >= bounds->field.min && \
496 to_check->field.typ <= bounds->field.max)
497 static void panel_simple_parse_panel_timing_node(struct device *dev,
498 struct panel_simple *panel,
499 const struct display_timing *ot)
501 const struct panel_desc *desc = panel->desc;
505 if (WARN_ON(desc->num_modes)) {
506 dev_err(dev, "Reject override mode: panel has a fixed mode\n");
509 if (WARN_ON(!desc->num_timings)) {
510 dev_err(dev, "Reject override mode: no timings specified\n");
514 for (i = 0; i < panel->desc->num_timings; i++) {
515 const struct display_timing *dt = &panel->desc->timings[i];
517 if (!PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hactive) ||
518 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hfront_porch) ||
519 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hback_porch) ||
520 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hsync_len) ||
521 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vactive) ||
522 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vfront_porch) ||
523 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vback_porch) ||
524 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vsync_len))
527 if (ot->flags != dt->flags)
530 videomode_from_timing(ot, &vm);
531 drm_display_mode_from_videomode(&vm, &panel->override_mode);
532 panel->override_mode.type |= DRM_MODE_TYPE_DRIVER |
533 DRM_MODE_TYPE_PREFERRED;
537 if (WARN_ON(!panel->override_mode.type))
538 dev_err(dev, "Reject override mode: No display_timing found\n");
541 static int panel_simple_probe(struct device *dev, const struct panel_desc *desc)
543 struct panel_simple *panel;
544 struct display_timing dt;
545 struct device_node *ddc;
550 panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL);
554 panel->enabled = false;
555 panel->prepared_time = 0;
558 panel->supply = devm_regulator_get(dev, "power");
559 if (IS_ERR(panel->supply))
560 return PTR_ERR(panel->supply);
562 panel->enable_gpio = devm_gpiod_get_optional(dev, "enable",
564 if (IS_ERR(panel->enable_gpio)) {
565 err = PTR_ERR(panel->enable_gpio);
566 if (err != -EPROBE_DEFER)
567 dev_err(dev, "failed to request GPIO: %d\n", err);
571 err = of_drm_get_panel_orientation(dev->of_node, &panel->orientation);
573 dev_err(dev, "%pOF: failed to get orientation %d\n", dev->of_node, err);
577 ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0);
579 panel->ddc = of_find_i2c_adapter_by_node(ddc);
583 return -EPROBE_DEFER;
586 if (desc == &panel_dpi) {
587 /* Handle the generic panel-dpi binding */
588 err = panel_dpi_probe(dev, panel);
593 if (!of_get_display_timing(dev->of_node, "panel-timing", &dt))
594 panel_simple_parse_panel_timing_node(dev, panel, &dt);
597 connector_type = desc->connector_type;
598 /* Catch common mistakes for panels. */
599 switch (connector_type) {
601 dev_warn(dev, "Specify missing connector_type\n");
602 connector_type = DRM_MODE_CONNECTOR_DPI;
604 case DRM_MODE_CONNECTOR_LVDS:
605 WARN_ON(desc->bus_flags &
606 ~(DRM_BUS_FLAG_DE_LOW |
607 DRM_BUS_FLAG_DE_HIGH |
608 DRM_BUS_FLAG_DATA_MSB_TO_LSB |
609 DRM_BUS_FLAG_DATA_LSB_TO_MSB));
610 WARN_ON(desc->bus_format != MEDIA_BUS_FMT_RGB666_1X7X3_SPWG &&
611 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_SPWG &&
612 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA);
613 WARN_ON(desc->bus_format == MEDIA_BUS_FMT_RGB666_1X7X3_SPWG &&
615 WARN_ON((desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_SPWG ||
616 desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA) &&
619 case DRM_MODE_CONNECTOR_eDP:
620 dev_warn(dev, "eDP panels moved to panel-edp\n");
623 case DRM_MODE_CONNECTOR_DSI:
624 if (desc->bpc != 6 && desc->bpc != 8)
625 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc);
627 case DRM_MODE_CONNECTOR_DPI:
628 bus_flags = DRM_BUS_FLAG_DE_LOW |
629 DRM_BUS_FLAG_DE_HIGH |
630 DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE |
631 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
632 DRM_BUS_FLAG_DATA_MSB_TO_LSB |
633 DRM_BUS_FLAG_DATA_LSB_TO_MSB |
634 DRM_BUS_FLAG_SYNC_SAMPLE_POSEDGE |
635 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE;
636 if (desc->bus_flags & ~bus_flags)
637 dev_warn(dev, "Unexpected bus_flags(%d)\n", desc->bus_flags & ~bus_flags);
638 if (!(desc->bus_flags & bus_flags))
639 dev_warn(dev, "Specify missing bus_flags\n");
640 if (desc->bus_format == 0)
641 dev_warn(dev, "Specify missing bus_format\n");
642 if (desc->bpc != 6 && desc->bpc != 8)
643 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc);
646 dev_warn(dev, "Specify a valid connector_type: %d\n", desc->connector_type);
647 connector_type = DRM_MODE_CONNECTOR_DPI;
651 dev_set_drvdata(dev, panel);
654 * We use runtime PM for prepare / unprepare since those power the panel
655 * on and off and those can be very slow operations. This is important
656 * to optimize powering the panel on briefly to read the EDID before
657 * fully enabling the panel.
659 pm_runtime_enable(dev);
660 pm_runtime_set_autosuspend_delay(dev, 1000);
661 pm_runtime_use_autosuspend(dev);
663 drm_panel_init(&panel->base, dev, &panel_simple_funcs, connector_type);
665 err = drm_panel_of_backlight(&panel->base);
667 goto disable_pm_runtime;
669 drm_panel_add(&panel->base);
674 pm_runtime_dont_use_autosuspend(dev);
675 pm_runtime_disable(dev);
678 put_device(&panel->ddc->dev);
683 static int panel_simple_remove(struct device *dev)
685 struct panel_simple *panel = dev_get_drvdata(dev);
687 drm_panel_remove(&panel->base);
688 drm_panel_disable(&panel->base);
689 drm_panel_unprepare(&panel->base);
691 pm_runtime_dont_use_autosuspend(dev);
692 pm_runtime_disable(dev);
694 put_device(&panel->ddc->dev);
699 static void panel_simple_shutdown(struct device *dev)
701 struct panel_simple *panel = dev_get_drvdata(dev);
703 drm_panel_disable(&panel->base);
704 drm_panel_unprepare(&panel->base);
707 static const struct drm_display_mode ampire_am_1280800n3tzqw_t00h_mode = {
710 .hsync_start = 1280 + 40,
711 .hsync_end = 1280 + 40 + 80,
712 .htotal = 1280 + 40 + 80 + 40,
714 .vsync_start = 800 + 3,
715 .vsync_end = 800 + 3 + 10,
716 .vtotal = 800 + 3 + 10 + 10,
717 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
720 static const struct panel_desc ampire_am_1280800n3tzqw_t00h = {
721 .modes = &ire_am_1280800n3tzqw_t00h_mode,
728 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
729 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
730 .connector_type = DRM_MODE_CONNECTOR_LVDS,
733 static const struct drm_display_mode ampire_am_480272h3tmqw_t01h_mode = {
736 .hsync_start = 480 + 2,
737 .hsync_end = 480 + 2 + 41,
738 .htotal = 480 + 2 + 41 + 2,
740 .vsync_start = 272 + 2,
741 .vsync_end = 272 + 2 + 10,
742 .vtotal = 272 + 2 + 10 + 2,
743 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
746 static const struct panel_desc ampire_am_480272h3tmqw_t01h = {
747 .modes = &ire_am_480272h3tmqw_t01h_mode,
754 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
757 static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = {
760 .hsync_start = 800 + 0,
761 .hsync_end = 800 + 0 + 255,
762 .htotal = 800 + 0 + 255 + 0,
764 .vsync_start = 480 + 2,
765 .vsync_end = 480 + 2 + 45,
766 .vtotal = 480 + 2 + 45 + 0,
767 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
770 static const struct panel_desc ampire_am800480r3tmqwa1h = {
771 .modes = &ire_am800480r3tmqwa1h_mode,
778 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
781 static const struct display_timing santek_st0700i5y_rbslw_f_timing = {
782 .pixelclock = { 26400000, 33300000, 46800000 },
783 .hactive = { 800, 800, 800 },
784 .hfront_porch = { 16, 210, 354 },
785 .hback_porch = { 45, 36, 6 },
786 .hsync_len = { 1, 10, 40 },
787 .vactive = { 480, 480, 480 },
788 .vfront_porch = { 7, 22, 147 },
789 .vback_porch = { 22, 13, 3 },
790 .vsync_len = { 1, 10, 20 },
791 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
792 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE
795 static const struct panel_desc armadeus_st0700_adapt = {
796 .timings = &santek_st0700i5y_rbslw_f_timing,
803 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
804 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
807 static const struct drm_display_mode auo_b101aw03_mode = {
810 .hsync_start = 1024 + 156,
811 .hsync_end = 1024 + 156 + 8,
812 .htotal = 1024 + 156 + 8 + 156,
814 .vsync_start = 600 + 16,
815 .vsync_end = 600 + 16 + 6,
816 .vtotal = 600 + 16 + 6 + 16,
819 static const struct panel_desc auo_b101aw03 = {
820 .modes = &auo_b101aw03_mode,
827 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
828 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
829 .connector_type = DRM_MODE_CONNECTOR_LVDS,
832 static const struct drm_display_mode auo_b101xtn01_mode = {
835 .hsync_start = 1366 + 20,
836 .hsync_end = 1366 + 20 + 70,
837 .htotal = 1366 + 20 + 70,
839 .vsync_start = 768 + 14,
840 .vsync_end = 768 + 14 + 42,
841 .vtotal = 768 + 14 + 42,
842 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
845 static const struct panel_desc auo_b101xtn01 = {
846 .modes = &auo_b101xtn01_mode,
855 static const struct display_timing auo_g070vvn01_timings = {
856 .pixelclock = { 33300000, 34209000, 45000000 },
857 .hactive = { 800, 800, 800 },
858 .hfront_porch = { 20, 40, 200 },
859 .hback_porch = { 87, 40, 1 },
860 .hsync_len = { 1, 48, 87 },
861 .vactive = { 480, 480, 480 },
862 .vfront_porch = { 5, 13, 200 },
863 .vback_porch = { 31, 31, 29 },
864 .vsync_len = { 1, 1, 3 },
867 static const struct panel_desc auo_g070vvn01 = {
868 .timings = &auo_g070vvn01_timings,
883 static const struct drm_display_mode auo_g101evn010_mode = {
886 .hsync_start = 1280 + 82,
887 .hsync_end = 1280 + 82 + 2,
888 .htotal = 1280 + 82 + 2 + 84,
890 .vsync_start = 800 + 8,
891 .vsync_end = 800 + 8 + 2,
892 .vtotal = 800 + 8 + 2 + 6,
895 static const struct panel_desc auo_g101evn010 = {
896 .modes = &auo_g101evn010_mode,
903 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
904 .connector_type = DRM_MODE_CONNECTOR_LVDS,
907 static const struct drm_display_mode auo_g104sn02_mode = {
910 .hsync_start = 800 + 40,
911 .hsync_end = 800 + 40 + 216,
912 .htotal = 800 + 40 + 216 + 128,
914 .vsync_start = 600 + 10,
915 .vsync_end = 600 + 10 + 35,
916 .vtotal = 600 + 10 + 35 + 2,
919 static const struct panel_desc auo_g104sn02 = {
920 .modes = &auo_g104sn02_mode,
927 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
928 .connector_type = DRM_MODE_CONNECTOR_LVDS,
931 static const struct drm_display_mode auo_g121ean01_mode = {
934 .hsync_start = 1280 + 58,
935 .hsync_end = 1280 + 58 + 8,
936 .htotal = 1280 + 58 + 8 + 70,
938 .vsync_start = 800 + 6,
939 .vsync_end = 800 + 6 + 4,
940 .vtotal = 800 + 6 + 4 + 10,
943 static const struct panel_desc auo_g121ean01 = {
944 .modes = &auo_g121ean01_mode,
951 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
952 .connector_type = DRM_MODE_CONNECTOR_LVDS,
955 static const struct display_timing auo_g133han01_timings = {
956 .pixelclock = { 134000000, 141200000, 149000000 },
957 .hactive = { 1920, 1920, 1920 },
958 .hfront_porch = { 39, 58, 77 },
959 .hback_porch = { 59, 88, 117 },
960 .hsync_len = { 28, 42, 56 },
961 .vactive = { 1080, 1080, 1080 },
962 .vfront_porch = { 3, 8, 11 },
963 .vback_porch = { 5, 14, 19 },
964 .vsync_len = { 4, 14, 19 },
967 static const struct panel_desc auo_g133han01 = {
968 .timings = &auo_g133han01_timings,
981 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
982 .connector_type = DRM_MODE_CONNECTOR_LVDS,
985 static const struct drm_display_mode auo_g156xtn01_mode = {
988 .hsync_start = 1366 + 33,
989 .hsync_end = 1366 + 33 + 67,
992 .vsync_start = 768 + 4,
993 .vsync_end = 768 + 4 + 4,
997 static const struct panel_desc auo_g156xtn01 = {
998 .modes = &auo_g156xtn01_mode,
1005 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1006 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1009 static const struct display_timing auo_g185han01_timings = {
1010 .pixelclock = { 120000000, 144000000, 175000000 },
1011 .hactive = { 1920, 1920, 1920 },
1012 .hfront_porch = { 36, 120, 148 },
1013 .hback_porch = { 24, 88, 108 },
1014 .hsync_len = { 20, 48, 64 },
1015 .vactive = { 1080, 1080, 1080 },
1016 .vfront_porch = { 6, 10, 40 },
1017 .vback_porch = { 2, 5, 20 },
1018 .vsync_len = { 2, 5, 20 },
1021 static const struct panel_desc auo_g185han01 = {
1022 .timings = &auo_g185han01_timings,
1035 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1036 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1039 static const struct display_timing auo_g190ean01_timings = {
1040 .pixelclock = { 90000000, 108000000, 135000000 },
1041 .hactive = { 1280, 1280, 1280 },
1042 .hfront_porch = { 126, 184, 1266 },
1043 .hback_porch = { 84, 122, 844 },
1044 .hsync_len = { 70, 102, 704 },
1045 .vactive = { 1024, 1024, 1024 },
1046 .vfront_porch = { 4, 26, 76 },
1047 .vback_porch = { 2, 8, 25 },
1048 .vsync_len = { 2, 8, 25 },
1051 static const struct panel_desc auo_g190ean01 = {
1052 .timings = &auo_g190ean01_timings,
1065 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1066 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1069 static const struct display_timing auo_p320hvn03_timings = {
1070 .pixelclock = { 106000000, 148500000, 164000000 },
1071 .hactive = { 1920, 1920, 1920 },
1072 .hfront_porch = { 25, 50, 130 },
1073 .hback_porch = { 25, 50, 130 },
1074 .hsync_len = { 20, 40, 105 },
1075 .vactive = { 1080, 1080, 1080 },
1076 .vfront_porch = { 8, 17, 150 },
1077 .vback_porch = { 8, 17, 150 },
1078 .vsync_len = { 4, 11, 100 },
1081 static const struct panel_desc auo_p320hvn03 = {
1082 .timings = &auo_p320hvn03_timings,
1094 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1095 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1098 static const struct drm_display_mode auo_t215hvn01_mode = {
1101 .hsync_start = 1920 + 88,
1102 .hsync_end = 1920 + 88 + 44,
1103 .htotal = 1920 + 88 + 44 + 148,
1105 .vsync_start = 1080 + 4,
1106 .vsync_end = 1080 + 4 + 5,
1107 .vtotal = 1080 + 4 + 5 + 36,
1110 static const struct panel_desc auo_t215hvn01 = {
1111 .modes = &auo_t215hvn01_mode,
1124 static const struct drm_display_mode avic_tm070ddh03_mode = {
1127 .hsync_start = 1024 + 160,
1128 .hsync_end = 1024 + 160 + 4,
1129 .htotal = 1024 + 160 + 4 + 156,
1131 .vsync_start = 600 + 17,
1132 .vsync_end = 600 + 17 + 1,
1133 .vtotal = 600 + 17 + 1 + 17,
1136 static const struct panel_desc avic_tm070ddh03 = {
1137 .modes = &avic_tm070ddh03_mode,
1151 static const struct drm_display_mode bananapi_s070wv20_ct16_mode = {
1154 .hsync_start = 800 + 40,
1155 .hsync_end = 800 + 40 + 48,
1156 .htotal = 800 + 40 + 48 + 40,
1158 .vsync_start = 480 + 13,
1159 .vsync_end = 480 + 13 + 3,
1160 .vtotal = 480 + 13 + 3 + 29,
1163 static const struct panel_desc bananapi_s070wv20_ct16 = {
1164 .modes = &bananapi_s070wv20_ct16_mode,
1173 static const struct drm_display_mode boe_hv070wsa_mode = {
1176 .hsync_start = 1024 + 30,
1177 .hsync_end = 1024 + 30 + 30,
1178 .htotal = 1024 + 30 + 30 + 30,
1180 .vsync_start = 600 + 10,
1181 .vsync_end = 600 + 10 + 10,
1182 .vtotal = 600 + 10 + 10 + 10,
1185 static const struct panel_desc boe_hv070wsa = {
1186 .modes = &boe_hv070wsa_mode,
1193 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1194 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1195 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1198 static const struct drm_display_mode cdtech_s043wq26h_ct7_mode = {
1201 .hsync_start = 480 + 5,
1202 .hsync_end = 480 + 5 + 5,
1203 .htotal = 480 + 5 + 5 + 40,
1205 .vsync_start = 272 + 8,
1206 .vsync_end = 272 + 8 + 8,
1207 .vtotal = 272 + 8 + 8 + 8,
1208 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1211 static const struct panel_desc cdtech_s043wq26h_ct7 = {
1212 .modes = &cdtech_s043wq26h_ct7_mode,
1219 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1222 /* S070PWS19HP-FC21 2017/04/22 */
1223 static const struct drm_display_mode cdtech_s070pws19hp_fc21_mode = {
1226 .hsync_start = 1024 + 160,
1227 .hsync_end = 1024 + 160 + 20,
1228 .htotal = 1024 + 160 + 20 + 140,
1230 .vsync_start = 600 + 12,
1231 .vsync_end = 600 + 12 + 3,
1232 .vtotal = 600 + 12 + 3 + 20,
1233 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1236 static const struct panel_desc cdtech_s070pws19hp_fc21 = {
1237 .modes = &cdtech_s070pws19hp_fc21_mode,
1244 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1245 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
1246 .connector_type = DRM_MODE_CONNECTOR_DPI,
1249 /* S070SWV29HG-DC44 2017/09/21 */
1250 static const struct drm_display_mode cdtech_s070swv29hg_dc44_mode = {
1253 .hsync_start = 800 + 210,
1254 .hsync_end = 800 + 210 + 2,
1255 .htotal = 800 + 210 + 2 + 44,
1257 .vsync_start = 480 + 22,
1258 .vsync_end = 480 + 22 + 2,
1259 .vtotal = 480 + 22 + 2 + 21,
1260 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1263 static const struct panel_desc cdtech_s070swv29hg_dc44 = {
1264 .modes = &cdtech_s070swv29hg_dc44_mode,
1271 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1272 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
1273 .connector_type = DRM_MODE_CONNECTOR_DPI,
1276 static const struct drm_display_mode cdtech_s070wv95_ct16_mode = {
1279 .hsync_start = 800 + 40,
1280 .hsync_end = 800 + 40 + 40,
1281 .htotal = 800 + 40 + 40 + 48,
1283 .vsync_start = 480 + 29,
1284 .vsync_end = 480 + 29 + 13,
1285 .vtotal = 480 + 29 + 13 + 3,
1286 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1289 static const struct panel_desc cdtech_s070wv95_ct16 = {
1290 .modes = &cdtech_s070wv95_ct16_mode,
1299 static const struct display_timing chefree_ch101olhlwh_002_timing = {
1300 .pixelclock = { 68900000, 71100000, 73400000 },
1301 .hactive = { 1280, 1280, 1280 },
1302 .hfront_porch = { 65, 80, 95 },
1303 .hback_porch = { 64, 79, 94 },
1304 .hsync_len = { 1, 1, 1 },
1305 .vactive = { 800, 800, 800 },
1306 .vfront_porch = { 7, 11, 14 },
1307 .vback_porch = { 7, 11, 14 },
1308 .vsync_len = { 1, 1, 1 },
1309 .flags = DISPLAY_FLAGS_DE_HIGH,
1312 static const struct panel_desc chefree_ch101olhlwh_002 = {
1313 .timings = &chefree_ch101olhlwh_002_timing,
1324 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1325 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1326 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1329 static const struct drm_display_mode chunghwa_claa070wp03xg_mode = {
1332 .hsync_start = 800 + 49,
1333 .hsync_end = 800 + 49 + 33,
1334 .htotal = 800 + 49 + 33 + 17,
1336 .vsync_start = 1280 + 1,
1337 .vsync_end = 1280 + 1 + 7,
1338 .vtotal = 1280 + 1 + 7 + 15,
1339 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1342 static const struct panel_desc chunghwa_claa070wp03xg = {
1343 .modes = &chunghwa_claa070wp03xg_mode,
1350 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1351 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1352 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1355 static const struct drm_display_mode chunghwa_claa101wa01a_mode = {
1358 .hsync_start = 1366 + 58,
1359 .hsync_end = 1366 + 58 + 58,
1360 .htotal = 1366 + 58 + 58 + 58,
1362 .vsync_start = 768 + 4,
1363 .vsync_end = 768 + 4 + 4,
1364 .vtotal = 768 + 4 + 4 + 4,
1367 static const struct panel_desc chunghwa_claa101wa01a = {
1368 .modes = &chunghwa_claa101wa01a_mode,
1375 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1376 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1377 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1380 static const struct drm_display_mode chunghwa_claa101wb01_mode = {
1383 .hsync_start = 1366 + 48,
1384 .hsync_end = 1366 + 48 + 32,
1385 .htotal = 1366 + 48 + 32 + 20,
1387 .vsync_start = 768 + 16,
1388 .vsync_end = 768 + 16 + 8,
1389 .vtotal = 768 + 16 + 8 + 16,
1392 static const struct panel_desc chunghwa_claa101wb01 = {
1393 .modes = &chunghwa_claa101wb01_mode,
1400 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1401 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1402 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1405 static const struct drm_display_mode dataimage_scf0700c48ggu18_mode = {
1408 .hsync_start = 800 + 40,
1409 .hsync_end = 800 + 40 + 128,
1410 .htotal = 800 + 40 + 128 + 88,
1412 .vsync_start = 480 + 10,
1413 .vsync_end = 480 + 10 + 2,
1414 .vtotal = 480 + 10 + 2 + 33,
1415 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1418 static const struct panel_desc dataimage_scf0700c48ggu18 = {
1419 .modes = &dataimage_scf0700c48ggu18_mode,
1426 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1427 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1430 static const struct display_timing dlc_dlc0700yzg_1_timing = {
1431 .pixelclock = { 45000000, 51200000, 57000000 },
1432 .hactive = { 1024, 1024, 1024 },
1433 .hfront_porch = { 100, 106, 113 },
1434 .hback_porch = { 100, 106, 113 },
1435 .hsync_len = { 100, 108, 114 },
1436 .vactive = { 600, 600, 600 },
1437 .vfront_porch = { 8, 11, 15 },
1438 .vback_porch = { 8, 11, 15 },
1439 .vsync_len = { 9, 13, 15 },
1440 .flags = DISPLAY_FLAGS_DE_HIGH,
1443 static const struct panel_desc dlc_dlc0700yzg_1 = {
1444 .timings = &dlc_dlc0700yzg_1_timing,
1456 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1457 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1460 static const struct display_timing dlc_dlc1010gig_timing = {
1461 .pixelclock = { 68900000, 71100000, 73400000 },
1462 .hactive = { 1280, 1280, 1280 },
1463 .hfront_porch = { 43, 53, 63 },
1464 .hback_porch = { 43, 53, 63 },
1465 .hsync_len = { 44, 54, 64 },
1466 .vactive = { 800, 800, 800 },
1467 .vfront_porch = { 5, 8, 11 },
1468 .vback_porch = { 5, 8, 11 },
1469 .vsync_len = { 5, 7, 11 },
1470 .flags = DISPLAY_FLAGS_DE_HIGH,
1473 static const struct panel_desc dlc_dlc1010gig = {
1474 .timings = &dlc_dlc1010gig_timing,
1487 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1488 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1491 static const struct drm_display_mode edt_et035012dm6_mode = {
1494 .hsync_start = 320 + 20,
1495 .hsync_end = 320 + 20 + 30,
1496 .htotal = 320 + 20 + 68,
1498 .vsync_start = 240 + 4,
1499 .vsync_end = 240 + 4 + 4,
1500 .vtotal = 240 + 4 + 4 + 14,
1501 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1504 static const struct panel_desc edt_et035012dm6 = {
1505 .modes = &edt_et035012dm6_mode,
1512 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1513 .bus_flags = DRM_BUS_FLAG_DE_LOW | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
1516 static const struct drm_display_mode edt_etm0350g0dh6_mode = {
1519 .hsync_start = 320 + 20,
1520 .hsync_end = 320 + 20 + 68,
1521 .htotal = 320 + 20 + 68,
1523 .vsync_start = 240 + 4,
1524 .vsync_end = 240 + 4 + 18,
1525 .vtotal = 240 + 4 + 18,
1526 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1529 static const struct panel_desc edt_etm0350g0dh6 = {
1530 .modes = &edt_etm0350g0dh6_mode,
1537 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1538 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
1539 .connector_type = DRM_MODE_CONNECTOR_DPI,
1542 static const struct drm_display_mode edt_etm043080dh6gp_mode = {
1545 .hsync_start = 480 + 8,
1546 .hsync_end = 480 + 8 + 4,
1547 .htotal = 480 + 8 + 4 + 41,
1550 * IWG22M: Y resolution changed for "dc_linuxfb" module crashing while
1555 .vsync_start = 288 + 2,
1556 .vsync_end = 288 + 2 + 4,
1557 .vtotal = 288 + 2 + 4 + 10,
1560 static const struct panel_desc edt_etm043080dh6gp = {
1561 .modes = &edt_etm043080dh6gp_mode,
1568 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1569 .connector_type = DRM_MODE_CONNECTOR_DPI,
1572 static const struct drm_display_mode edt_etm0430g0dh6_mode = {
1575 .hsync_start = 480 + 2,
1576 .hsync_end = 480 + 2 + 41,
1577 .htotal = 480 + 2 + 41 + 2,
1579 .vsync_start = 272 + 2,
1580 .vsync_end = 272 + 2 + 10,
1581 .vtotal = 272 + 2 + 10 + 2,
1582 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1585 static const struct panel_desc edt_etm0430g0dh6 = {
1586 .modes = &edt_etm0430g0dh6_mode,
1593 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1594 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
1595 .connector_type = DRM_MODE_CONNECTOR_DPI,
1598 static const struct drm_display_mode edt_et057090dhu_mode = {
1601 .hsync_start = 640 + 16,
1602 .hsync_end = 640 + 16 + 30,
1603 .htotal = 640 + 16 + 30 + 114,
1605 .vsync_start = 480 + 10,
1606 .vsync_end = 480 + 10 + 3,
1607 .vtotal = 480 + 10 + 3 + 32,
1608 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1611 static const struct panel_desc edt_et057090dhu = {
1612 .modes = &edt_et057090dhu_mode,
1619 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1620 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
1621 .connector_type = DRM_MODE_CONNECTOR_DPI,
1624 static const struct drm_display_mode edt_etm0700g0dh6_mode = {
1627 .hsync_start = 800 + 40,
1628 .hsync_end = 800 + 40 + 128,
1629 .htotal = 800 + 40 + 128 + 88,
1631 .vsync_start = 480 + 10,
1632 .vsync_end = 480 + 10 + 2,
1633 .vtotal = 480 + 10 + 2 + 33,
1634 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1637 static const struct panel_desc edt_etm0700g0dh6 = {
1638 .modes = &edt_etm0700g0dh6_mode,
1645 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1646 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
1647 .connector_type = DRM_MODE_CONNECTOR_DPI,
1650 static const struct panel_desc edt_etm0700g0bdh6 = {
1651 .modes = &edt_etm0700g0dh6_mode,
1658 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1659 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1660 .connector_type = DRM_MODE_CONNECTOR_DPI,
1663 static const struct drm_display_mode edt_etmv570g2dhu_mode = {
1667 .hsync_end = 640 + 16,
1668 .htotal = 640 + 16 + 30 + 114,
1670 .vsync_start = 480 + 10,
1671 .vsync_end = 480 + 10 + 3,
1672 .vtotal = 480 + 10 + 3 + 35,
1673 .flags = DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_PHSYNC,
1676 static const struct panel_desc edt_etmv570g2dhu = {
1677 .modes = &edt_etmv570g2dhu_mode,
1684 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1685 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
1686 .connector_type = DRM_MODE_CONNECTOR_DPI,
1689 static const struct display_timing eink_vb3300_kca_timing = {
1690 .pixelclock = { 40000000, 40000000, 40000000 },
1691 .hactive = { 334, 334, 334 },
1692 .hfront_porch = { 1, 1, 1 },
1693 .hback_porch = { 1, 1, 1 },
1694 .hsync_len = { 1, 1, 1 },
1695 .vactive = { 1405, 1405, 1405 },
1696 .vfront_porch = { 1, 1, 1 },
1697 .vback_porch = { 1, 1, 1 },
1698 .vsync_len = { 1, 1, 1 },
1699 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
1700 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE,
1703 static const struct panel_desc eink_vb3300_kca = {
1704 .timings = &eink_vb3300_kca_timing,
1711 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1712 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1713 .connector_type = DRM_MODE_CONNECTOR_DPI,
1716 static const struct display_timing evervision_vgg804821_timing = {
1717 .pixelclock = { 27600000, 33300000, 50000000 },
1718 .hactive = { 800, 800, 800 },
1719 .hfront_porch = { 40, 66, 70 },
1720 .hback_porch = { 40, 67, 70 },
1721 .hsync_len = { 40, 67, 70 },
1722 .vactive = { 480, 480, 480 },
1723 .vfront_porch = { 6, 10, 10 },
1724 .vback_porch = { 7, 11, 11 },
1725 .vsync_len = { 7, 11, 11 },
1726 .flags = DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH |
1727 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE |
1728 DISPLAY_FLAGS_SYNC_NEGEDGE,
1731 static const struct panel_desc evervision_vgg804821 = {
1732 .timings = &evervision_vgg804821_timing,
1739 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1740 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
1743 static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = {
1746 .hsync_start = 800 + 168,
1747 .hsync_end = 800 + 168 + 64,
1748 .htotal = 800 + 168 + 64 + 88,
1750 .vsync_start = 480 + 37,
1751 .vsync_end = 480 + 37 + 2,
1752 .vtotal = 480 + 37 + 2 + 8,
1755 static const struct panel_desc foxlink_fl500wvr00_a0t = {
1756 .modes = &foxlink_fl500wvr00_a0t_mode,
1763 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1766 static const struct drm_display_mode frida_frd350h54004_modes[] = {
1770 .hsync_start = 320 + 44,
1771 .hsync_end = 320 + 44 + 16,
1772 .htotal = 320 + 44 + 16 + 20,
1774 .vsync_start = 240 + 2,
1775 .vsync_end = 240 + 2 + 6,
1776 .vtotal = 240 + 2 + 6 + 2,
1777 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1782 .hsync_start = 320 + 56,
1783 .hsync_end = 320 + 56 + 16,
1784 .htotal = 320 + 56 + 16 + 40,
1786 .vsync_start = 240 + 2,
1787 .vsync_end = 240 + 2 + 6,
1788 .vtotal = 240 + 2 + 6 + 2,
1789 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1793 static const struct panel_desc frida_frd350h54004 = {
1794 .modes = frida_frd350h54004_modes,
1795 .num_modes = ARRAY_SIZE(frida_frd350h54004_modes),
1801 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1802 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
1803 .connector_type = DRM_MODE_CONNECTOR_DPI,
1806 static const struct drm_display_mode friendlyarm_hd702e_mode = {
1809 .hsync_start = 800 + 20,
1810 .hsync_end = 800 + 20 + 24,
1811 .htotal = 800 + 20 + 24 + 20,
1813 .vsync_start = 1280 + 4,
1814 .vsync_end = 1280 + 4 + 8,
1815 .vtotal = 1280 + 4 + 8 + 4,
1816 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1819 static const struct panel_desc friendlyarm_hd702e = {
1820 .modes = &friendlyarm_hd702e_mode,
1828 static const struct drm_display_mode giantplus_gpg482739qs5_mode = {
1831 .hsync_start = 480 + 5,
1832 .hsync_end = 480 + 5 + 1,
1833 .htotal = 480 + 5 + 1 + 40,
1835 .vsync_start = 272 + 8,
1836 .vsync_end = 272 + 8 + 1,
1837 .vtotal = 272 + 8 + 1 + 8,
1840 static const struct panel_desc giantplus_gpg482739qs5 = {
1841 .modes = &giantplus_gpg482739qs5_mode,
1848 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1851 static const struct display_timing giantplus_gpm940b0_timing = {
1852 .pixelclock = { 13500000, 27000000, 27500000 },
1853 .hactive = { 320, 320, 320 },
1854 .hfront_porch = { 14, 686, 718 },
1855 .hback_porch = { 50, 70, 255 },
1856 .hsync_len = { 1, 1, 1 },
1857 .vactive = { 240, 240, 240 },
1858 .vfront_porch = { 1, 1, 179 },
1859 .vback_porch = { 1, 21, 31 },
1860 .vsync_len = { 1, 1, 6 },
1861 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
1864 static const struct panel_desc giantplus_gpm940b0 = {
1865 .timings = &giantplus_gpm940b0_timing,
1872 .bus_format = MEDIA_BUS_FMT_RGB888_3X8,
1873 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
1876 static const struct display_timing hannstar_hsd070pww1_timing = {
1877 .pixelclock = { 64300000, 71100000, 82000000 },
1878 .hactive = { 1280, 1280, 1280 },
1879 .hfront_porch = { 1, 1, 10 },
1880 .hback_porch = { 1, 1, 10 },
1882 * According to the data sheet, the minimum horizontal blanking interval
1883 * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the
1884 * minimum working horizontal blanking interval to be 60 clocks.
1886 .hsync_len = { 58, 158, 661 },
1887 .vactive = { 800, 800, 800 },
1888 .vfront_porch = { 1, 1, 10 },
1889 .vback_porch = { 1, 1, 10 },
1890 .vsync_len = { 1, 21, 203 },
1891 .flags = DISPLAY_FLAGS_DE_HIGH,
1894 static const struct panel_desc hannstar_hsd070pww1 = {
1895 .timings = &hannstar_hsd070pww1_timing,
1902 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1903 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1906 static const struct display_timing hannstar_hsd100pxn1_timing = {
1907 .pixelclock = { 55000000, 65000000, 75000000 },
1908 .hactive = { 1024, 1024, 1024 },
1909 .hfront_porch = { 40, 40, 40 },
1910 .hback_porch = { 220, 220, 220 },
1911 .hsync_len = { 20, 60, 100 },
1912 .vactive = { 768, 768, 768 },
1913 .vfront_porch = { 7, 7, 7 },
1914 .vback_porch = { 21, 21, 21 },
1915 .vsync_len = { 10, 10, 10 },
1916 .flags = DISPLAY_FLAGS_DE_HIGH,
1919 static const struct panel_desc hannstar_hsd100pxn1 = {
1920 .timings = &hannstar_hsd100pxn1_timing,
1927 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1928 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1931 static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = {
1934 .hsync_start = 800 + 85,
1935 .hsync_end = 800 + 85 + 86,
1936 .htotal = 800 + 85 + 86 + 85,
1938 .vsync_start = 480 + 16,
1939 .vsync_end = 480 + 16 + 13,
1940 .vtotal = 480 + 16 + 13 + 16,
1943 static const struct panel_desc hitachi_tx23d38vm0caa = {
1944 .modes = &hitachi_tx23d38vm0caa_mode,
1957 static const struct drm_display_mode innolux_at043tn24_mode = {
1960 .hsync_start = 480 + 2,
1961 .hsync_end = 480 + 2 + 41,
1962 .htotal = 480 + 2 + 41 + 2,
1964 .vsync_start = 272 + 2,
1965 .vsync_end = 272 + 2 + 10,
1966 .vtotal = 272 + 2 + 10 + 2,
1967 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1970 static const struct panel_desc innolux_at043tn24 = {
1971 .modes = &innolux_at043tn24_mode,
1978 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1979 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1982 static const struct drm_display_mode innolux_at070tn92_mode = {
1985 .hsync_start = 800 + 210,
1986 .hsync_end = 800 + 210 + 20,
1987 .htotal = 800 + 210 + 20 + 46,
1989 .vsync_start = 480 + 22,
1990 .vsync_end = 480 + 22 + 10,
1991 .vtotal = 480 + 22 + 23 + 10,
1994 static const struct panel_desc innolux_at070tn92 = {
1995 .modes = &innolux_at070tn92_mode,
2001 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2004 static const struct display_timing innolux_g070y2_l01_timing = {
2005 .pixelclock = { 28000000, 29500000, 32000000 },
2006 .hactive = { 800, 800, 800 },
2007 .hfront_porch = { 61, 91, 141 },
2008 .hback_porch = { 60, 90, 140 },
2009 .hsync_len = { 12, 12, 12 },
2010 .vactive = { 480, 480, 480 },
2011 .vfront_porch = { 4, 9, 30 },
2012 .vback_porch = { 4, 8, 28 },
2013 .vsync_len = { 2, 2, 2 },
2014 .flags = DISPLAY_FLAGS_DE_HIGH,
2017 static const struct panel_desc innolux_g070y2_l01 = {
2018 .timings = &innolux_g070y2_l01_timing,
2031 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2032 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2035 static const struct drm_display_mode innolux_g070y2_t02_mode = {
2038 .hsync_start = 800 + 210,
2039 .hsync_end = 800 + 210 + 20,
2040 .htotal = 800 + 210 + 20 + 46,
2042 .vsync_start = 480 + 22,
2043 .vsync_end = 480 + 22 + 10,
2044 .vtotal = 480 + 22 + 23 + 10,
2047 static const struct panel_desc innolux_g070y2_t02 = {
2048 .modes = &innolux_g070y2_t02_mode,
2055 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2056 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
2057 .connector_type = DRM_MODE_CONNECTOR_DPI,
2060 static const struct display_timing innolux_g101ice_l01_timing = {
2061 .pixelclock = { 60400000, 71100000, 74700000 },
2062 .hactive = { 1280, 1280, 1280 },
2063 .hfront_porch = { 41, 80, 100 },
2064 .hback_porch = { 40, 79, 99 },
2065 .hsync_len = { 1, 1, 1 },
2066 .vactive = { 800, 800, 800 },
2067 .vfront_porch = { 5, 11, 14 },
2068 .vback_porch = { 4, 11, 14 },
2069 .vsync_len = { 1, 1, 1 },
2070 .flags = DISPLAY_FLAGS_DE_HIGH,
2073 static const struct panel_desc innolux_g101ice_l01 = {
2074 .timings = &innolux_g101ice_l01_timing,
2085 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2086 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2089 static const struct display_timing innolux_g121i1_l01_timing = {
2090 .pixelclock = { 67450000, 71000000, 74550000 },
2091 .hactive = { 1280, 1280, 1280 },
2092 .hfront_porch = { 40, 80, 160 },
2093 .hback_porch = { 39, 79, 159 },
2094 .hsync_len = { 1, 1, 1 },
2095 .vactive = { 800, 800, 800 },
2096 .vfront_porch = { 5, 11, 100 },
2097 .vback_porch = { 4, 11, 99 },
2098 .vsync_len = { 1, 1, 1 },
2101 static const struct panel_desc innolux_g121i1_l01 = {
2102 .timings = &innolux_g121i1_l01_timing,
2113 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2114 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2117 static const struct drm_display_mode innolux_g121x1_l03_mode = {
2120 .hsync_start = 1024 + 0,
2121 .hsync_end = 1024 + 1,
2122 .htotal = 1024 + 0 + 1 + 320,
2124 .vsync_start = 768 + 38,
2125 .vsync_end = 768 + 38 + 1,
2126 .vtotal = 768 + 38 + 1 + 0,
2127 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
2130 static const struct panel_desc innolux_g121x1_l03 = {
2131 .modes = &innolux_g121x1_l03_mode,
2145 static const struct drm_display_mode innolux_n156bge_l21_mode = {
2148 .hsync_start = 1366 + 16,
2149 .hsync_end = 1366 + 16 + 34,
2150 .htotal = 1366 + 16 + 34 + 50,
2152 .vsync_start = 768 + 2,
2153 .vsync_end = 768 + 2 + 6,
2154 .vtotal = 768 + 2 + 6 + 12,
2157 static const struct panel_desc innolux_n156bge_l21 = {
2158 .modes = &innolux_n156bge_l21_mode,
2165 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2166 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2167 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2170 static const struct drm_display_mode innolux_zj070na_01p_mode = {
2173 .hsync_start = 1024 + 128,
2174 .hsync_end = 1024 + 128 + 64,
2175 .htotal = 1024 + 128 + 64 + 128,
2177 .vsync_start = 600 + 16,
2178 .vsync_end = 600 + 16 + 4,
2179 .vtotal = 600 + 16 + 4 + 16,
2182 static const struct panel_desc innolux_zj070na_01p = {
2183 .modes = &innolux_zj070na_01p_mode,
2192 static const struct display_timing koe_tx14d24vm1bpa_timing = {
2193 .pixelclock = { 5580000, 5850000, 6200000 },
2194 .hactive = { 320, 320, 320 },
2195 .hfront_porch = { 30, 30, 30 },
2196 .hback_porch = { 30, 30, 30 },
2197 .hsync_len = { 1, 5, 17 },
2198 .vactive = { 240, 240, 240 },
2199 .vfront_porch = { 6, 6, 6 },
2200 .vback_porch = { 5, 5, 5 },
2201 .vsync_len = { 1, 2, 11 },
2202 .flags = DISPLAY_FLAGS_DE_HIGH,
2205 static const struct panel_desc koe_tx14d24vm1bpa = {
2206 .timings = &koe_tx14d24vm1bpa_timing,
2215 static const struct display_timing koe_tx26d202vm0bwa_timing = {
2216 .pixelclock = { 151820000, 156720000, 159780000 },
2217 .hactive = { 1920, 1920, 1920 },
2218 .hfront_porch = { 105, 130, 142 },
2219 .hback_porch = { 45, 70, 82 },
2220 .hsync_len = { 30, 30, 30 },
2221 .vactive = { 1200, 1200, 1200},
2222 .vfront_porch = { 3, 5, 10 },
2223 .vback_porch = { 2, 5, 10 },
2224 .vsync_len = { 5, 5, 5 },
2227 static const struct panel_desc koe_tx26d202vm0bwa = {
2228 .timings = &koe_tx26d202vm0bwa_timing,
2241 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2242 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2243 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2246 static const struct display_timing koe_tx31d200vm0baa_timing = {
2247 .pixelclock = { 39600000, 43200000, 48000000 },
2248 .hactive = { 1280, 1280, 1280 },
2249 .hfront_porch = { 16, 36, 56 },
2250 .hback_porch = { 16, 36, 56 },
2251 .hsync_len = { 8, 8, 8 },
2252 .vactive = { 480, 480, 480 },
2253 .vfront_porch = { 6, 21, 33 },
2254 .vback_porch = { 6, 21, 33 },
2255 .vsync_len = { 8, 8, 8 },
2256 .flags = DISPLAY_FLAGS_DE_HIGH,
2259 static const struct panel_desc koe_tx31d200vm0baa = {
2260 .timings = &koe_tx31d200vm0baa_timing,
2267 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2268 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2271 static const struct display_timing kyo_tcg121xglp_timing = {
2272 .pixelclock = { 52000000, 65000000, 71000000 },
2273 .hactive = { 1024, 1024, 1024 },
2274 .hfront_porch = { 2, 2, 2 },
2275 .hback_porch = { 2, 2, 2 },
2276 .hsync_len = { 86, 124, 244 },
2277 .vactive = { 768, 768, 768 },
2278 .vfront_porch = { 2, 2, 2 },
2279 .vback_porch = { 2, 2, 2 },
2280 .vsync_len = { 6, 34, 73 },
2281 .flags = DISPLAY_FLAGS_DE_HIGH,
2284 static const struct panel_desc kyo_tcg121xglp = {
2285 .timings = &kyo_tcg121xglp_timing,
2292 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2293 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2296 static const struct drm_display_mode lemaker_bl035_rgb_002_mode = {
2299 .hsync_start = 320 + 20,
2300 .hsync_end = 320 + 20 + 30,
2301 .htotal = 320 + 20 + 30 + 38,
2303 .vsync_start = 240 + 4,
2304 .vsync_end = 240 + 4 + 3,
2305 .vtotal = 240 + 4 + 3 + 15,
2308 static const struct panel_desc lemaker_bl035_rgb_002 = {
2309 .modes = &lemaker_bl035_rgb_002_mode,
2315 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2316 .bus_flags = DRM_BUS_FLAG_DE_LOW,
2319 static const struct drm_display_mode lg_lb070wv8_mode = {
2322 .hsync_start = 800 + 88,
2323 .hsync_end = 800 + 88 + 80,
2324 .htotal = 800 + 88 + 80 + 88,
2326 .vsync_start = 480 + 10,
2327 .vsync_end = 480 + 10 + 25,
2328 .vtotal = 480 + 10 + 25 + 10,
2331 static const struct panel_desc lg_lb070wv8 = {
2332 .modes = &lg_lb070wv8_mode,
2339 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2340 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2343 static const struct display_timing logictechno_lt161010_2nh_timing = {
2344 .pixelclock = { 26400000, 33300000, 46800000 },
2345 .hactive = { 800, 800, 800 },
2346 .hfront_porch = { 16, 210, 354 },
2347 .hback_porch = { 46, 46, 46 },
2348 .hsync_len = { 1, 20, 40 },
2349 .vactive = { 480, 480, 480 },
2350 .vfront_porch = { 7, 22, 147 },
2351 .vback_porch = { 23, 23, 23 },
2352 .vsync_len = { 1, 10, 20 },
2353 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
2354 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
2355 DISPLAY_FLAGS_SYNC_POSEDGE,
2358 static const struct panel_desc logictechno_lt161010_2nh = {
2359 .timings = &logictechno_lt161010_2nh_timing,
2365 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2366 .bus_flags = DRM_BUS_FLAG_DE_HIGH |
2367 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
2368 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
2369 .connector_type = DRM_MODE_CONNECTOR_DPI,
2372 static const struct display_timing logictechno_lt170410_2whc_timing = {
2373 .pixelclock = { 68900000, 71100000, 73400000 },
2374 .hactive = { 1280, 1280, 1280 },
2375 .hfront_porch = { 23, 60, 71 },
2376 .hback_porch = { 23, 60, 71 },
2377 .hsync_len = { 15, 40, 47 },
2378 .vactive = { 800, 800, 800 },
2379 .vfront_porch = { 5, 7, 10 },
2380 .vback_porch = { 5, 7, 10 },
2381 .vsync_len = { 6, 9, 12 },
2382 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
2383 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
2384 DISPLAY_FLAGS_SYNC_POSEDGE,
2387 static const struct panel_desc logictechno_lt170410_2whc = {
2388 .timings = &logictechno_lt170410_2whc_timing,
2394 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2395 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2396 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2399 static const struct drm_display_mode logictechno_lttd800480070_l2rt_mode = {
2402 .hsync_start = 800 + 112,
2403 .hsync_end = 800 + 112 + 3,
2404 .htotal = 800 + 112 + 3 + 85,
2406 .vsync_start = 480 + 38,
2407 .vsync_end = 480 + 38 + 3,
2408 .vtotal = 480 + 38 + 3 + 29,
2409 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2412 static const struct panel_desc logictechno_lttd800480070_l2rt = {
2413 .modes = &logictechno_lttd800480070_l2rt_mode,
2426 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2427 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
2428 .connector_type = DRM_MODE_CONNECTOR_DPI,
2431 static const struct drm_display_mode logictechno_lttd800480070_l6wh_rt_mode = {
2434 .hsync_start = 800 + 154,
2435 .hsync_end = 800 + 154 + 3,
2436 .htotal = 800 + 154 + 3 + 43,
2438 .vsync_start = 480 + 47,
2439 .vsync_end = 480 + 47 + 3,
2440 .vtotal = 480 + 47 + 3 + 20,
2441 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2444 static const struct panel_desc logictechno_lttd800480070_l6wh_rt = {
2445 .modes = &logictechno_lttd800480070_l6wh_rt_mode,
2458 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2459 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
2460 .connector_type = DRM_MODE_CONNECTOR_DPI,
2463 static const struct drm_display_mode logicpd_type_28_mode = {
2466 .hsync_start = 480 + 3,
2467 .hsync_end = 480 + 3 + 42,
2468 .htotal = 480 + 3 + 42 + 2,
2471 .vsync_start = 272 + 2,
2472 .vsync_end = 272 + 2 + 11,
2473 .vtotal = 272 + 2 + 11 + 3,
2474 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
2477 static const struct panel_desc logicpd_type_28 = {
2478 .modes = &logicpd_type_28_mode,
2491 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2492 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE |
2493 DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE,
2494 .connector_type = DRM_MODE_CONNECTOR_DPI,
2497 static const struct drm_display_mode mitsubishi_aa070mc01_mode = {
2500 .hsync_start = 800 + 0,
2501 .hsync_end = 800 + 1,
2502 .htotal = 800 + 0 + 1 + 160,
2504 .vsync_start = 480 + 0,
2505 .vsync_end = 480 + 48 + 1,
2506 .vtotal = 480 + 48 + 1 + 0,
2507 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
2510 static const struct panel_desc mitsubishi_aa070mc01 = {
2511 .modes = &mitsubishi_aa070mc01_mode,
2524 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2525 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2526 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2529 static const struct display_timing multi_inno_mi1010ait_1cp_timing = {
2530 .pixelclock = { 68900000, 70000000, 73400000 },
2531 .hactive = { 1280, 1280, 1280 },
2532 .hfront_porch = { 30, 60, 71 },
2533 .hback_porch = { 30, 60, 71 },
2534 .hsync_len = { 10, 10, 48 },
2535 .vactive = { 800, 800, 800 },
2536 .vfront_porch = { 5, 10, 10 },
2537 .vback_porch = { 5, 10, 10 },
2538 .vsync_len = { 5, 6, 13 },
2539 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
2540 DISPLAY_FLAGS_DE_HIGH,
2543 static const struct panel_desc multi_inno_mi1010ait_1cp = {
2544 .timings = &multi_inno_mi1010ait_1cp_timing,
2555 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2556 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2557 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2560 static const struct display_timing nec_nl12880bc20_05_timing = {
2561 .pixelclock = { 67000000, 71000000, 75000000 },
2562 .hactive = { 1280, 1280, 1280 },
2563 .hfront_porch = { 2, 30, 30 },
2564 .hback_porch = { 6, 100, 100 },
2565 .hsync_len = { 2, 30, 30 },
2566 .vactive = { 800, 800, 800 },
2567 .vfront_porch = { 5, 5, 5 },
2568 .vback_porch = { 11, 11, 11 },
2569 .vsync_len = { 7, 7, 7 },
2572 static const struct panel_desc nec_nl12880bc20_05 = {
2573 .timings = &nec_nl12880bc20_05_timing,
2584 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2585 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2588 static const struct drm_display_mode nec_nl4827hc19_05b_mode = {
2591 .hsync_start = 480 + 2,
2592 .hsync_end = 480 + 2 + 41,
2593 .htotal = 480 + 2 + 41 + 2,
2595 .vsync_start = 272 + 2,
2596 .vsync_end = 272 + 2 + 4,
2597 .vtotal = 272 + 2 + 4 + 2,
2598 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2601 static const struct panel_desc nec_nl4827hc19_05b = {
2602 .modes = &nec_nl4827hc19_05b_mode,
2609 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2610 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
2613 static const struct drm_display_mode netron_dy_e231732_mode = {
2616 .hsync_start = 1024 + 160,
2617 .hsync_end = 1024 + 160 + 70,
2618 .htotal = 1024 + 160 + 70 + 90,
2620 .vsync_start = 600 + 127,
2621 .vsync_end = 600 + 127 + 20,
2622 .vtotal = 600 + 127 + 20 + 3,
2625 static const struct panel_desc netron_dy_e231732 = {
2626 .modes = &netron_dy_e231732_mode,
2632 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2635 static const struct drm_display_mode newhaven_nhd_43_480272ef_atxl_mode = {
2638 .hsync_start = 480 + 2,
2639 .hsync_end = 480 + 2 + 41,
2640 .htotal = 480 + 2 + 41 + 2,
2642 .vsync_start = 272 + 2,
2643 .vsync_end = 272 + 2 + 10,
2644 .vtotal = 272 + 2 + 10 + 2,
2645 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2648 static const struct panel_desc newhaven_nhd_43_480272ef_atxl = {
2649 .modes = &newhaven_nhd_43_480272ef_atxl_mode,
2656 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2657 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE |
2658 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
2659 .connector_type = DRM_MODE_CONNECTOR_DPI,
2662 static const struct display_timing nlt_nl192108ac18_02d_timing = {
2663 .pixelclock = { 130000000, 148350000, 163000000 },
2664 .hactive = { 1920, 1920, 1920 },
2665 .hfront_porch = { 80, 100, 100 },
2666 .hback_porch = { 100, 120, 120 },
2667 .hsync_len = { 50, 60, 60 },
2668 .vactive = { 1080, 1080, 1080 },
2669 .vfront_porch = { 12, 30, 30 },
2670 .vback_porch = { 4, 10, 10 },
2671 .vsync_len = { 4, 5, 5 },
2674 static const struct panel_desc nlt_nl192108ac18_02d = {
2675 .timings = &nlt_nl192108ac18_02d_timing,
2685 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2686 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2689 static const struct drm_display_mode nvd_9128_mode = {
2692 .hsync_start = 800 + 130,
2693 .hsync_end = 800 + 130 + 98,
2694 .htotal = 800 + 0 + 130 + 98,
2696 .vsync_start = 480 + 10,
2697 .vsync_end = 480 + 10 + 50,
2698 .vtotal = 480 + 0 + 10 + 50,
2701 static const struct panel_desc nvd_9128 = {
2702 .modes = &nvd_9128_mode,
2709 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2710 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2713 static const struct display_timing okaya_rs800480t_7x0gp_timing = {
2714 .pixelclock = { 30000000, 30000000, 40000000 },
2715 .hactive = { 800, 800, 800 },
2716 .hfront_porch = { 40, 40, 40 },
2717 .hback_porch = { 40, 40, 40 },
2718 .hsync_len = { 1, 48, 48 },
2719 .vactive = { 480, 480, 480 },
2720 .vfront_porch = { 13, 13, 13 },
2721 .vback_porch = { 29, 29, 29 },
2722 .vsync_len = { 3, 3, 3 },
2723 .flags = DISPLAY_FLAGS_DE_HIGH,
2726 static const struct panel_desc okaya_rs800480t_7x0gp = {
2727 .timings = &okaya_rs800480t_7x0gp_timing,
2740 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2743 static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode = {
2746 .hsync_start = 480 + 5,
2747 .hsync_end = 480 + 5 + 30,
2748 .htotal = 480 + 5 + 30 + 10,
2750 .vsync_start = 272 + 8,
2751 .vsync_end = 272 + 8 + 5,
2752 .vtotal = 272 + 8 + 5 + 3,
2755 static const struct panel_desc olimex_lcd_olinuxino_43ts = {
2756 .modes = &olimex_lcd_olinuxino_43ts_mode,
2762 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2766 * 800x480 CVT. The panel appears to be quite accepting, at least as far as
2767 * pixel clocks, but this is the timing that was being used in the Adafruit
2768 * installation instructions.
2770 static const struct drm_display_mode ontat_yx700wv03_mode = {
2780 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2785 * https://www.adafruit.com/images/product-files/2406/c3163.pdf
2787 static const struct panel_desc ontat_yx700wv03 = {
2788 .modes = &ontat_yx700wv03_mode,
2795 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2798 static const struct drm_display_mode ortustech_com37h3m_mode = {
2801 .hsync_start = 480 + 40,
2802 .hsync_end = 480 + 40 + 10,
2803 .htotal = 480 + 40 + 10 + 40,
2805 .vsync_start = 640 + 4,
2806 .vsync_end = 640 + 4 + 2,
2807 .vtotal = 640 + 4 + 2 + 4,
2808 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2811 static const struct panel_desc ortustech_com37h3m = {
2812 .modes = &ortustech_com37h3m_mode,
2816 .width = 56, /* 56.16mm */
2817 .height = 75, /* 74.88mm */
2819 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2820 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
2821 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
2824 static const struct drm_display_mode ortustech_com43h4m85ulc_mode = {
2827 .hsync_start = 480 + 10,
2828 .hsync_end = 480 + 10 + 10,
2829 .htotal = 480 + 10 + 10 + 15,
2831 .vsync_start = 800 + 3,
2832 .vsync_end = 800 + 3 + 3,
2833 .vtotal = 800 + 3 + 3 + 3,
2836 static const struct panel_desc ortustech_com43h4m85ulc = {
2837 .modes = &ortustech_com43h4m85ulc_mode,
2844 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2845 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
2846 .connector_type = DRM_MODE_CONNECTOR_DPI,
2849 static const struct drm_display_mode osddisplays_osd070t1718_19ts_mode = {
2852 .hsync_start = 800 + 210,
2853 .hsync_end = 800 + 210 + 30,
2854 .htotal = 800 + 210 + 30 + 16,
2856 .vsync_start = 480 + 22,
2857 .vsync_end = 480 + 22 + 13,
2858 .vtotal = 480 + 22 + 13 + 10,
2859 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2862 static const struct panel_desc osddisplays_osd070t1718_19ts = {
2863 .modes = &osddisplays_osd070t1718_19ts_mode,
2870 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2871 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE |
2872 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
2873 .connector_type = DRM_MODE_CONNECTOR_DPI,
2876 static const struct drm_display_mode pda_91_00156_a0_mode = {
2879 .hsync_start = 800 + 1,
2880 .hsync_end = 800 + 1 + 64,
2881 .htotal = 800 + 1 + 64 + 64,
2883 .vsync_start = 480 + 1,
2884 .vsync_end = 480 + 1 + 23,
2885 .vtotal = 480 + 1 + 23 + 22,
2888 static const struct panel_desc pda_91_00156_a0 = {
2889 .modes = &pda_91_00156_a0_mode,
2895 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2898 static const struct drm_display_mode powertip_ph800480t013_idf02_mode = {
2901 .hsync_start = 800 + 54,
2902 .hsync_end = 800 + 54 + 2,
2903 .htotal = 800 + 54 + 2 + 44,
2905 .vsync_start = 480 + 49,
2906 .vsync_end = 480 + 49 + 2,
2907 .vtotal = 480 + 49 + 2 + 22,
2910 static const struct panel_desc powertip_ph800480t013_idf02 = {
2911 .modes = &powertip_ph800480t013_idf02_mode,
2917 .bus_flags = DRM_BUS_FLAG_DE_HIGH |
2918 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
2919 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
2920 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2921 .connector_type = DRM_MODE_CONNECTOR_DPI,
2924 static const struct drm_display_mode qd43003c0_40_mode = {
2927 .hsync_start = 480 + 8,
2928 .hsync_end = 480 + 8 + 4,
2929 .htotal = 480 + 8 + 4 + 39,
2931 .vsync_start = 272 + 4,
2932 .vsync_end = 272 + 4 + 10,
2933 .vtotal = 272 + 4 + 10 + 2,
2936 static const struct panel_desc qd43003c0_40 = {
2937 .modes = &qd43003c0_40_mode,
2944 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2947 static const struct drm_display_mode qishenglong_gopher2b_lcd_modes[] = {
2951 .hsync_start = 480 + 77,
2952 .hsync_end = 480 + 77 + 41,
2953 .htotal = 480 + 77 + 41 + 2,
2955 .vsync_start = 272 + 16,
2956 .vsync_end = 272 + 16 + 10,
2957 .vtotal = 272 + 16 + 10 + 2,
2958 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2963 .hsync_start = 480 + 17,
2964 .hsync_end = 480 + 17 + 41,
2965 .htotal = 480 + 17 + 41 + 2,
2967 .vsync_start = 272 + 116,
2968 .vsync_end = 272 + 116 + 10,
2969 .vtotal = 272 + 116 + 10 + 2,
2970 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2974 static const struct panel_desc qishenglong_gopher2b_lcd = {
2975 .modes = qishenglong_gopher2b_lcd_modes,
2976 .num_modes = ARRAY_SIZE(qishenglong_gopher2b_lcd_modes),
2982 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2983 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
2984 .connector_type = DRM_MODE_CONNECTOR_DPI,
2987 static const struct display_timing rocktech_rk070er9427_timing = {
2988 .pixelclock = { 26400000, 33300000, 46800000 },
2989 .hactive = { 800, 800, 800 },
2990 .hfront_porch = { 16, 210, 354 },
2991 .hback_porch = { 46, 46, 46 },
2992 .hsync_len = { 1, 1, 1 },
2993 .vactive = { 480, 480, 480 },
2994 .vfront_porch = { 7, 22, 147 },
2995 .vback_porch = { 23, 23, 23 },
2996 .vsync_len = { 1, 1, 1 },
2997 .flags = DISPLAY_FLAGS_DE_HIGH,
3000 static const struct panel_desc rocktech_rk070er9427 = {
3001 .timings = &rocktech_rk070er9427_timing,
3014 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3017 static const struct drm_display_mode rocktech_rk101ii01d_ct_mode = {
3020 .hsync_start = 1280 + 48,
3021 .hsync_end = 1280 + 48 + 32,
3022 .htotal = 1280 + 48 + 32 + 80,
3024 .vsync_start = 800 + 2,
3025 .vsync_end = 800 + 2 + 5,
3026 .vtotal = 800 + 2 + 5 + 16,
3029 static const struct panel_desc rocktech_rk101ii01d_ct = {
3030 .modes = &rocktech_rk101ii01d_ct_mode,
3040 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
3041 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3042 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3045 static const struct drm_display_mode samsung_ltn101nt05_mode = {
3048 .hsync_start = 1024 + 24,
3049 .hsync_end = 1024 + 24 + 136,
3050 .htotal = 1024 + 24 + 136 + 160,
3052 .vsync_start = 600 + 3,
3053 .vsync_end = 600 + 3 + 6,
3054 .vtotal = 600 + 3 + 6 + 61,
3057 static const struct panel_desc samsung_ltn101nt05 = {
3058 .modes = &samsung_ltn101nt05_mode,
3065 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
3066 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
3067 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3070 static const struct display_timing satoz_sat050at40h12r2_timing = {
3071 .pixelclock = {33300000, 33300000, 50000000},
3072 .hactive = {800, 800, 800},
3073 .hfront_porch = {16, 210, 354},
3074 .hback_porch = {46, 46, 46},
3075 .hsync_len = {1, 1, 40},
3076 .vactive = {480, 480, 480},
3077 .vfront_porch = {7, 22, 147},
3078 .vback_porch = {23, 23, 23},
3079 .vsync_len = {1, 1, 20},
3082 static const struct panel_desc satoz_sat050at40h12r2 = {
3083 .timings = &satoz_sat050at40h12r2_timing,
3090 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3091 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3094 static const struct drm_display_mode sharp_lq070y3dg3b_mode = {
3097 .hsync_start = 800 + 64,
3098 .hsync_end = 800 + 64 + 128,
3099 .htotal = 800 + 64 + 128 + 64,
3101 .vsync_start = 480 + 8,
3102 .vsync_end = 480 + 8 + 2,
3103 .vtotal = 480 + 8 + 2 + 35,
3104 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE,
3107 static const struct panel_desc sharp_lq070y3dg3b = {
3108 .modes = &sharp_lq070y3dg3b_mode,
3112 .width = 152, /* 152.4mm */
3113 .height = 91, /* 91.4mm */
3115 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3116 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
3117 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
3120 static const struct drm_display_mode sharp_lq035q7db03_mode = {
3123 .hsync_start = 240 + 16,
3124 .hsync_end = 240 + 16 + 7,
3125 .htotal = 240 + 16 + 7 + 5,
3127 .vsync_start = 320 + 9,
3128 .vsync_end = 320 + 9 + 1,
3129 .vtotal = 320 + 9 + 1 + 7,
3132 static const struct panel_desc sharp_lq035q7db03 = {
3133 .modes = &sharp_lq035q7db03_mode,
3140 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3143 static const struct display_timing sharp_lq101k1ly04_timing = {
3144 .pixelclock = { 60000000, 65000000, 80000000 },
3145 .hactive = { 1280, 1280, 1280 },
3146 .hfront_porch = { 20, 20, 20 },
3147 .hback_porch = { 20, 20, 20 },
3148 .hsync_len = { 10, 10, 10 },
3149 .vactive = { 800, 800, 800 },
3150 .vfront_porch = { 4, 4, 4 },
3151 .vback_porch = { 4, 4, 4 },
3152 .vsync_len = { 4, 4, 4 },
3153 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE,
3156 static const struct panel_desc sharp_lq101k1ly04 = {
3157 .timings = &sharp_lq101k1ly04_timing,
3164 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
3165 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3168 static const struct drm_display_mode sharp_ls020b1dd01d_modes[] = {
3172 .hsync_start = 240 + 58,
3173 .hsync_end = 240 + 58 + 1,
3174 .htotal = 240 + 58 + 1 + 1,
3176 .vsync_start = 160 + 24,
3177 .vsync_end = 160 + 24 + 10,
3178 .vtotal = 160 + 24 + 10 + 6,
3179 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC,
3184 .hsync_start = 240 + 8,
3185 .hsync_end = 240 + 8 + 1,
3186 .htotal = 240 + 8 + 1 + 1,
3188 .vsync_start = 160 + 24,
3189 .vsync_end = 160 + 24 + 10,
3190 .vtotal = 160 + 24 + 10 + 6,
3191 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC,
3195 static const struct panel_desc sharp_ls020b1dd01d = {
3196 .modes = sharp_ls020b1dd01d_modes,
3197 .num_modes = ARRAY_SIZE(sharp_ls020b1dd01d_modes),
3203 .bus_format = MEDIA_BUS_FMT_RGB565_1X16,
3204 .bus_flags = DRM_BUS_FLAG_DE_HIGH
3205 | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE
3206 | DRM_BUS_FLAG_SHARP_SIGNALS,
3209 static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = {
3212 .hsync_start = 800 + 1,
3213 .hsync_end = 800 + 1 + 64,
3214 .htotal = 800 + 1 + 64 + 64,
3216 .vsync_start = 480 + 1,
3217 .vsync_end = 480 + 1 + 23,
3218 .vtotal = 480 + 1 + 23 + 22,
3221 static const struct panel_desc shelly_sca07010_bfn_lnn = {
3222 .modes = &shelly_sca07010_bfn_lnn_mode,
3228 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3231 static const struct drm_display_mode starry_kr070pe2t_mode = {
3234 .hsync_start = 800 + 209,
3235 .hsync_end = 800 + 209 + 1,
3236 .htotal = 800 + 209 + 1 + 45,
3238 .vsync_start = 480 + 22,
3239 .vsync_end = 480 + 22 + 1,
3240 .vtotal = 480 + 22 + 1 + 22,
3243 static const struct panel_desc starry_kr070pe2t = {
3244 .modes = &starry_kr070pe2t_mode,
3251 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3252 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
3253 .connector_type = DRM_MODE_CONNECTOR_DPI,
3256 static const struct display_timing tsd_tst043015cmhx_timing = {
3257 .pixelclock = { 5000000, 9000000, 12000000 },
3258 .hactive = { 480, 480, 480 },
3259 .hfront_porch = { 4, 5, 65 },
3260 .hback_porch = { 36, 40, 255 },
3261 .hsync_len = { 1, 1, 1 },
3262 .vactive = { 272, 272, 272 },
3263 .vfront_porch = { 2, 8, 97 },
3264 .vback_porch = { 3, 8, 31 },
3265 .vsync_len = { 1, 1, 1 },
3267 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
3268 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE,
3271 static const struct panel_desc tsd_tst043015cmhx = {
3272 .timings = &tsd_tst043015cmhx_timing,
3279 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3280 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
3283 static const struct drm_display_mode tfc_s9700rtwv43tr_01b_mode = {
3286 .hsync_start = 800 + 39,
3287 .hsync_end = 800 + 39 + 47,
3288 .htotal = 800 + 39 + 47 + 39,
3290 .vsync_start = 480 + 13,
3291 .vsync_end = 480 + 13 + 2,
3292 .vtotal = 480 + 13 + 2 + 29,
3295 static const struct panel_desc tfc_s9700rtwv43tr_01b = {
3296 .modes = &tfc_s9700rtwv43tr_01b_mode,
3303 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3304 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
3307 static const struct display_timing tianma_tm070jdhg30_timing = {
3308 .pixelclock = { 62600000, 68200000, 78100000 },
3309 .hactive = { 1280, 1280, 1280 },
3310 .hfront_porch = { 15, 64, 159 },
3311 .hback_porch = { 5, 5, 5 },
3312 .hsync_len = { 1, 1, 256 },
3313 .vactive = { 800, 800, 800 },
3314 .vfront_porch = { 3, 40, 99 },
3315 .vback_porch = { 2, 2, 2 },
3316 .vsync_len = { 1, 1, 128 },
3317 .flags = DISPLAY_FLAGS_DE_HIGH,
3320 static const struct panel_desc tianma_tm070jdhg30 = {
3321 .timings = &tianma_tm070jdhg30_timing,
3328 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3329 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3332 static const struct panel_desc tianma_tm070jvhg33 = {
3333 .timings = &tianma_tm070jdhg30_timing,
3340 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3341 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3344 static const struct display_timing tianma_tm070rvhg71_timing = {
3345 .pixelclock = { 27700000, 29200000, 39600000 },
3346 .hactive = { 800, 800, 800 },
3347 .hfront_porch = { 12, 40, 212 },
3348 .hback_porch = { 88, 88, 88 },
3349 .hsync_len = { 1, 1, 40 },
3350 .vactive = { 480, 480, 480 },
3351 .vfront_porch = { 1, 13, 88 },
3352 .vback_porch = { 32, 32, 32 },
3353 .vsync_len = { 1, 1, 3 },
3354 .flags = DISPLAY_FLAGS_DE_HIGH,
3357 static const struct panel_desc tianma_tm070rvhg71 = {
3358 .timings = &tianma_tm070rvhg71_timing,
3365 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3366 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3369 static const struct drm_display_mode ti_nspire_cx_lcd_mode[] = {
3373 .hsync_start = 320 + 50,
3374 .hsync_end = 320 + 50 + 6,
3375 .htotal = 320 + 50 + 6 + 38,
3377 .vsync_start = 240 + 3,
3378 .vsync_end = 240 + 3 + 1,
3379 .vtotal = 240 + 3 + 1 + 17,
3380 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3384 static const struct panel_desc ti_nspire_cx_lcd_panel = {
3385 .modes = ti_nspire_cx_lcd_mode,
3392 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3393 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
3396 static const struct drm_display_mode ti_nspire_classic_lcd_mode[] = {
3400 .hsync_start = 320 + 6,
3401 .hsync_end = 320 + 6 + 6,
3402 .htotal = 320 + 6 + 6 + 6,
3404 .vsync_start = 240 + 0,
3405 .vsync_end = 240 + 0 + 1,
3406 .vtotal = 240 + 0 + 1 + 0,
3407 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
3411 static const struct panel_desc ti_nspire_classic_lcd_panel = {
3412 .modes = ti_nspire_classic_lcd_mode,
3414 /* The grayscale panel has 8 bit for the color .. Y (black) */
3420 /* This is the grayscale bus format */
3421 .bus_format = MEDIA_BUS_FMT_Y8_1X8,
3422 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
3425 static const struct drm_display_mode toshiba_lt089ac29000_mode = {
3428 .hsync_start = 1280 + 192,
3429 .hsync_end = 1280 + 192 + 128,
3430 .htotal = 1280 + 192 + 128 + 64,
3432 .vsync_start = 768 + 20,
3433 .vsync_end = 768 + 20 + 7,
3434 .vtotal = 768 + 20 + 7 + 3,
3437 static const struct panel_desc toshiba_lt089ac29000 = {
3438 .modes = &toshiba_lt089ac29000_mode,
3444 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
3445 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
3446 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3449 static const struct drm_display_mode tpk_f07a_0102_mode = {
3452 .hsync_start = 800 + 40,
3453 .hsync_end = 800 + 40 + 128,
3454 .htotal = 800 + 40 + 128 + 88,
3456 .vsync_start = 480 + 10,
3457 .vsync_end = 480 + 10 + 2,
3458 .vtotal = 480 + 10 + 2 + 33,
3461 static const struct panel_desc tpk_f07a_0102 = {
3462 .modes = &tpk_f07a_0102_mode,
3468 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
3471 static const struct drm_display_mode tpk_f10a_0102_mode = {
3474 .hsync_start = 1024 + 176,
3475 .hsync_end = 1024 + 176 + 5,
3476 .htotal = 1024 + 176 + 5 + 88,
3478 .vsync_start = 600 + 20,
3479 .vsync_end = 600 + 20 + 5,
3480 .vtotal = 600 + 20 + 5 + 25,
3483 static const struct panel_desc tpk_f10a_0102 = {
3484 .modes = &tpk_f10a_0102_mode,
3492 static const struct display_timing urt_umsh_8596md_timing = {
3493 .pixelclock = { 33260000, 33260000, 33260000 },
3494 .hactive = { 800, 800, 800 },
3495 .hfront_porch = { 41, 41, 41 },
3496 .hback_porch = { 216 - 128, 216 - 128, 216 - 128 },
3497 .hsync_len = { 71, 128, 128 },
3498 .vactive = { 480, 480, 480 },
3499 .vfront_porch = { 10, 10, 10 },
3500 .vback_porch = { 35 - 2, 35 - 2, 35 - 2 },
3501 .vsync_len = { 2, 2, 2 },
3502 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE |
3503 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
3506 static const struct panel_desc urt_umsh_8596md_lvds = {
3507 .timings = &urt_umsh_8596md_timing,
3514 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
3515 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3518 static const struct panel_desc urt_umsh_8596md_parallel = {
3519 .timings = &urt_umsh_8596md_timing,
3526 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3529 static const struct drm_display_mode vivax_tpc9150_panel_mode = {
3532 .hsync_start = 1024 + 160,
3533 .hsync_end = 1024 + 160 + 100,
3534 .htotal = 1024 + 160 + 100 + 60,
3536 .vsync_start = 600 + 12,
3537 .vsync_end = 600 + 12 + 10,
3538 .vtotal = 600 + 12 + 10 + 13,
3541 static const struct panel_desc vivax_tpc9150_panel = {
3542 .modes = &vivax_tpc9150_panel_mode,
3549 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
3550 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
3551 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3554 static const struct drm_display_mode vl050_8048nt_c01_mode = {
3557 .hsync_start = 800 + 210,
3558 .hsync_end = 800 + 210 + 20,
3559 .htotal = 800 + 210 + 20 + 46,
3561 .vsync_start = 480 + 22,
3562 .vsync_end = 480 + 22 + 10,
3563 .vtotal = 480 + 22 + 10 + 23,
3564 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
3567 static const struct panel_desc vl050_8048nt_c01 = {
3568 .modes = &vl050_8048nt_c01_mode,
3575 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3576 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
3579 static const struct drm_display_mode winstar_wf35ltiacd_mode = {
3582 .hsync_start = 320 + 20,
3583 .hsync_end = 320 + 20 + 30,
3584 .htotal = 320 + 20 + 30 + 38,
3586 .vsync_start = 240 + 4,
3587 .vsync_end = 240 + 4 + 3,
3588 .vtotal = 240 + 4 + 3 + 15,
3589 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3592 static const struct panel_desc winstar_wf35ltiacd = {
3593 .modes = &winstar_wf35ltiacd_mode,
3600 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3603 static const struct drm_display_mode yes_optoelectronics_ytc700tlag_05_201c_mode = {
3606 .hsync_start = 1024 + 100,
3607 .hsync_end = 1024 + 100 + 100,
3608 .htotal = 1024 + 100 + 100 + 120,
3610 .vsync_start = 600 + 10,
3611 .vsync_end = 600 + 10 + 10,
3612 .vtotal = 600 + 10 + 10 + 15,
3613 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
3616 static const struct panel_desc yes_optoelectronics_ytc700tlag_05_201c = {
3617 .modes = &yes_optoelectronics_ytc700tlag_05_201c_mode,
3624 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
3625 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3626 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3629 static const struct drm_display_mode arm_rtsm_mode[] = {
3633 .hsync_start = 1024 + 24,
3634 .hsync_end = 1024 + 24 + 136,
3635 .htotal = 1024 + 24 + 136 + 160,
3637 .vsync_start = 768 + 3,
3638 .vsync_end = 768 + 3 + 6,
3639 .vtotal = 768 + 3 + 6 + 29,
3640 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3644 static const struct panel_desc arm_rtsm = {
3645 .modes = arm_rtsm_mode,
3652 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3655 static const struct of_device_id platform_of_match[] = {
3657 .compatible = "ampire,am-1280800n3tzqw-t00h",
3658 .data = &ire_am_1280800n3tzqw_t00h,
3660 .compatible = "ampire,am-480272h3tmqw-t01h",
3661 .data = &ire_am_480272h3tmqw_t01h,
3663 .compatible = "ampire,am800480r3tmqwa1h",
3664 .data = &ire_am800480r3tmqwa1h,
3666 .compatible = "arm,rtsm-display",
3669 .compatible = "armadeus,st0700-adapt",
3670 .data = &armadeus_st0700_adapt,
3672 .compatible = "auo,b101aw03",
3673 .data = &auo_b101aw03,
3675 .compatible = "auo,b101xtn01",
3676 .data = &auo_b101xtn01,
3678 .compatible = "auo,g070vvn01",
3679 .data = &auo_g070vvn01,
3681 .compatible = "auo,g101evn010",
3682 .data = &auo_g101evn010,
3684 .compatible = "auo,g104sn02",
3685 .data = &auo_g104sn02,
3687 .compatible = "auo,g121ean01",
3688 .data = &auo_g121ean01,
3690 .compatible = "auo,g133han01",
3691 .data = &auo_g133han01,
3693 .compatible = "auo,g156xtn01",
3694 .data = &auo_g156xtn01,
3696 .compatible = "auo,g185han01",
3697 .data = &auo_g185han01,
3699 .compatible = "auo,g190ean01",
3700 .data = &auo_g190ean01,
3702 .compatible = "auo,p320hvn03",
3703 .data = &auo_p320hvn03,
3705 .compatible = "auo,t215hvn01",
3706 .data = &auo_t215hvn01,
3708 .compatible = "avic,tm070ddh03",
3709 .data = &avic_tm070ddh03,
3711 .compatible = "bananapi,s070wv20-ct16",
3712 .data = &bananapi_s070wv20_ct16,
3714 .compatible = "boe,hv070wsa-100",
3715 .data = &boe_hv070wsa
3717 .compatible = "cdtech,s043wq26h-ct7",
3718 .data = &cdtech_s043wq26h_ct7,
3720 .compatible = "cdtech,s070pws19hp-fc21",
3721 .data = &cdtech_s070pws19hp_fc21,
3723 .compatible = "cdtech,s070swv29hg-dc44",
3724 .data = &cdtech_s070swv29hg_dc44,
3726 .compatible = "cdtech,s070wv95-ct16",
3727 .data = &cdtech_s070wv95_ct16,
3729 .compatible = "chefree,ch101olhlwh-002",
3730 .data = &chefree_ch101olhlwh_002,
3732 .compatible = "chunghwa,claa070wp03xg",
3733 .data = &chunghwa_claa070wp03xg,
3735 .compatible = "chunghwa,claa101wa01a",
3736 .data = &chunghwa_claa101wa01a
3738 .compatible = "chunghwa,claa101wb01",
3739 .data = &chunghwa_claa101wb01
3741 .compatible = "dataimage,scf0700c48ggu18",
3742 .data = &dataimage_scf0700c48ggu18,
3744 .compatible = "dlc,dlc0700yzg-1",
3745 .data = &dlc_dlc0700yzg_1,
3747 .compatible = "dlc,dlc1010gig",
3748 .data = &dlc_dlc1010gig,
3750 .compatible = "edt,et035012dm6",
3751 .data = &edt_et035012dm6,
3753 .compatible = "edt,etm0350g0dh6",
3754 .data = &edt_etm0350g0dh6,
3756 .compatible = "edt,etm043080dh6gp",
3757 .data = &edt_etm043080dh6gp,
3759 .compatible = "edt,etm0430g0dh6",
3760 .data = &edt_etm0430g0dh6,
3762 .compatible = "edt,et057090dhu",
3763 .data = &edt_et057090dhu,
3765 .compatible = "edt,et070080dh6",
3766 .data = &edt_etm0700g0dh6,
3768 .compatible = "edt,etm0700g0dh6",
3769 .data = &edt_etm0700g0dh6,
3771 .compatible = "edt,etm0700g0bdh6",
3772 .data = &edt_etm0700g0bdh6,
3774 .compatible = "edt,etm0700g0edh6",
3775 .data = &edt_etm0700g0bdh6,
3777 .compatible = "edt,etmv570g2dhu",
3778 .data = &edt_etmv570g2dhu,
3780 .compatible = "eink,vb3300-kca",
3781 .data = &eink_vb3300_kca,
3783 .compatible = "evervision,vgg804821",
3784 .data = &evervision_vgg804821,
3786 .compatible = "foxlink,fl500wvr00-a0t",
3787 .data = &foxlink_fl500wvr00_a0t,
3789 .compatible = "frida,frd350h54004",
3790 .data = &frida_frd350h54004,
3792 .compatible = "friendlyarm,hd702e",
3793 .data = &friendlyarm_hd702e,
3795 .compatible = "giantplus,gpg482739qs5",
3796 .data = &giantplus_gpg482739qs5
3798 .compatible = "giantplus,gpm940b0",
3799 .data = &giantplus_gpm940b0,
3801 .compatible = "hannstar,hsd070pww1",
3802 .data = &hannstar_hsd070pww1,
3804 .compatible = "hannstar,hsd100pxn1",
3805 .data = &hannstar_hsd100pxn1,
3807 .compatible = "hit,tx23d38vm0caa",
3808 .data = &hitachi_tx23d38vm0caa
3810 .compatible = "innolux,at043tn24",
3811 .data = &innolux_at043tn24,
3813 .compatible = "innolux,at070tn92",
3814 .data = &innolux_at070tn92,
3816 .compatible = "innolux,g070y2-l01",
3817 .data = &innolux_g070y2_l01,
3819 .compatible = "innolux,g070y2-t02",
3820 .data = &innolux_g070y2_t02,
3822 .compatible = "innolux,g101ice-l01",
3823 .data = &innolux_g101ice_l01
3825 .compatible = "innolux,g121i1-l01",
3826 .data = &innolux_g121i1_l01
3828 .compatible = "innolux,g121x1-l03",
3829 .data = &innolux_g121x1_l03,
3831 .compatible = "innolux,n156bge-l21",
3832 .data = &innolux_n156bge_l21,
3834 .compatible = "innolux,zj070na-01p",
3835 .data = &innolux_zj070na_01p,
3837 .compatible = "koe,tx14d24vm1bpa",
3838 .data = &koe_tx14d24vm1bpa,
3840 .compatible = "koe,tx26d202vm0bwa",
3841 .data = &koe_tx26d202vm0bwa,
3843 .compatible = "koe,tx31d200vm0baa",
3844 .data = &koe_tx31d200vm0baa,
3846 .compatible = "kyo,tcg121xglp",
3847 .data = &kyo_tcg121xglp,
3849 .compatible = "lemaker,bl035-rgb-002",
3850 .data = &lemaker_bl035_rgb_002,
3852 .compatible = "lg,lb070wv8",
3853 .data = &lg_lb070wv8,
3855 .compatible = "logicpd,type28",
3856 .data = &logicpd_type_28,
3858 .compatible = "logictechno,lt161010-2nhc",
3859 .data = &logictechno_lt161010_2nh,
3861 .compatible = "logictechno,lt161010-2nhr",
3862 .data = &logictechno_lt161010_2nh,
3864 .compatible = "logictechno,lt170410-2whc",
3865 .data = &logictechno_lt170410_2whc,
3867 .compatible = "logictechno,lttd800480070-l2rt",
3868 .data = &logictechno_lttd800480070_l2rt,
3870 .compatible = "logictechno,lttd800480070-l6wh-rt",
3871 .data = &logictechno_lttd800480070_l6wh_rt,
3873 .compatible = "mitsubishi,aa070mc01-ca1",
3874 .data = &mitsubishi_aa070mc01,
3876 .compatible = "multi-inno,mi1010ait-1cp",
3877 .data = &multi_inno_mi1010ait_1cp,
3879 .compatible = "nec,nl12880bc20-05",
3880 .data = &nec_nl12880bc20_05,
3882 .compatible = "nec,nl4827hc19-05b",
3883 .data = &nec_nl4827hc19_05b,
3885 .compatible = "netron-dy,e231732",
3886 .data = &netron_dy_e231732,
3888 .compatible = "newhaven,nhd-4.3-480272ef-atxl",
3889 .data = &newhaven_nhd_43_480272ef_atxl,
3891 .compatible = "nlt,nl192108ac18-02d",
3892 .data = &nlt_nl192108ac18_02d,
3894 .compatible = "nvd,9128",
3897 .compatible = "okaya,rs800480t-7x0gp",
3898 .data = &okaya_rs800480t_7x0gp,
3900 .compatible = "olimex,lcd-olinuxino-43-ts",
3901 .data = &olimex_lcd_olinuxino_43ts,
3903 .compatible = "ontat,yx700wv03",
3904 .data = &ontat_yx700wv03,
3906 .compatible = "ortustech,com37h3m05dtc",
3907 .data = &ortustech_com37h3m,
3909 .compatible = "ortustech,com37h3m99dtc",
3910 .data = &ortustech_com37h3m,
3912 .compatible = "ortustech,com43h4m85ulc",
3913 .data = &ortustech_com43h4m85ulc,
3915 .compatible = "osddisplays,osd070t1718-19ts",
3916 .data = &osddisplays_osd070t1718_19ts,
3918 .compatible = "pda,91-00156-a0",
3919 .data = &pda_91_00156_a0,
3921 .compatible = "powertip,ph800480t013-idf02",
3922 .data = &powertip_ph800480t013_idf02,
3924 .compatible = "qiaodian,qd43003c0-40",
3925 .data = &qd43003c0_40,
3927 .compatible = "qishenglong,gopher2b-lcd",
3928 .data = &qishenglong_gopher2b_lcd,
3930 .compatible = "rocktech,rk070er9427",
3931 .data = &rocktech_rk070er9427,
3933 .compatible = "rocktech,rk101ii01d-ct",
3934 .data = &rocktech_rk101ii01d_ct,
3936 .compatible = "samsung,ltn101nt05",
3937 .data = &samsung_ltn101nt05,
3939 .compatible = "satoz,sat050at40h12r2",
3940 .data = &satoz_sat050at40h12r2,
3942 .compatible = "sharp,lq035q7db03",
3943 .data = &sharp_lq035q7db03,
3945 .compatible = "sharp,lq070y3dg3b",
3946 .data = &sharp_lq070y3dg3b,
3948 .compatible = "sharp,lq101k1ly04",
3949 .data = &sharp_lq101k1ly04,
3951 .compatible = "sharp,ls020b1dd01d",
3952 .data = &sharp_ls020b1dd01d,
3954 .compatible = "shelly,sca07010-bfn-lnn",
3955 .data = &shelly_sca07010_bfn_lnn,
3957 .compatible = "starry,kr070pe2t",
3958 .data = &starry_kr070pe2t,
3960 .compatible = "team-source-display,tst043015cmhx",
3961 .data = &tsd_tst043015cmhx,
3963 .compatible = "tfc,s9700rtwv43tr-01b",
3964 .data = &tfc_s9700rtwv43tr_01b,
3966 .compatible = "tianma,tm070jdhg30",
3967 .data = &tianma_tm070jdhg30,
3969 .compatible = "tianma,tm070jvhg33",
3970 .data = &tianma_tm070jvhg33,
3972 .compatible = "tianma,tm070rvhg71",
3973 .data = &tianma_tm070rvhg71,
3975 .compatible = "ti,nspire-cx-lcd-panel",
3976 .data = &ti_nspire_cx_lcd_panel,
3978 .compatible = "ti,nspire-classic-lcd-panel",
3979 .data = &ti_nspire_classic_lcd_panel,
3981 .compatible = "toshiba,lt089ac29000",
3982 .data = &toshiba_lt089ac29000,
3984 .compatible = "tpk,f07a-0102",
3985 .data = &tpk_f07a_0102,
3987 .compatible = "tpk,f10a-0102",
3988 .data = &tpk_f10a_0102,
3990 .compatible = "urt,umsh-8596md-t",
3991 .data = &urt_umsh_8596md_parallel,
3993 .compatible = "urt,umsh-8596md-1t",
3994 .data = &urt_umsh_8596md_parallel,
3996 .compatible = "urt,umsh-8596md-7t",
3997 .data = &urt_umsh_8596md_parallel,
3999 .compatible = "urt,umsh-8596md-11t",
4000 .data = &urt_umsh_8596md_lvds,
4002 .compatible = "urt,umsh-8596md-19t",
4003 .data = &urt_umsh_8596md_lvds,
4005 .compatible = "urt,umsh-8596md-20t",
4006 .data = &urt_umsh_8596md_parallel,
4008 .compatible = "vivax,tpc9150-panel",
4009 .data = &vivax_tpc9150_panel,
4011 .compatible = "vxt,vl050-8048nt-c01",
4012 .data = &vl050_8048nt_c01,
4014 .compatible = "winstar,wf35ltiacd",
4015 .data = &winstar_wf35ltiacd,
4017 .compatible = "yes-optoelectronics,ytc700tlag-05-201c",
4018 .data = &yes_optoelectronics_ytc700tlag_05_201c,
4020 /* Must be the last entry */
4021 .compatible = "panel-dpi",
4027 MODULE_DEVICE_TABLE(of, platform_of_match);
4029 static int panel_simple_platform_probe(struct platform_device *pdev)
4031 const struct of_device_id *id;
4033 id = of_match_node(platform_of_match, pdev->dev.of_node);
4037 return panel_simple_probe(&pdev->dev, id->data);
4040 static int panel_simple_platform_remove(struct platform_device *pdev)
4042 return panel_simple_remove(&pdev->dev);
4045 static void panel_simple_platform_shutdown(struct platform_device *pdev)
4047 panel_simple_shutdown(&pdev->dev);
4050 static const struct dev_pm_ops panel_simple_pm_ops = {
4051 SET_RUNTIME_PM_OPS(panel_simple_suspend, panel_simple_resume, NULL)
4052 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
4053 pm_runtime_force_resume)
4056 static struct platform_driver panel_simple_platform_driver = {
4058 .name = "panel-simple",
4059 .of_match_table = platform_of_match,
4060 .pm = &panel_simple_pm_ops,
4062 .probe = panel_simple_platform_probe,
4063 .remove = panel_simple_platform_remove,
4064 .shutdown = panel_simple_platform_shutdown,
4067 struct panel_desc_dsi {
4068 struct panel_desc desc;
4070 unsigned long flags;
4071 enum mipi_dsi_pixel_format format;
4075 static const struct drm_display_mode auo_b080uan01_mode = {
4078 .hsync_start = 1200 + 62,
4079 .hsync_end = 1200 + 62 + 4,
4080 .htotal = 1200 + 62 + 4 + 62,
4082 .vsync_start = 1920 + 9,
4083 .vsync_end = 1920 + 9 + 2,
4084 .vtotal = 1920 + 9 + 2 + 8,
4087 static const struct panel_desc_dsi auo_b080uan01 = {
4089 .modes = &auo_b080uan01_mode,
4096 .connector_type = DRM_MODE_CONNECTOR_DSI,
4098 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
4099 .format = MIPI_DSI_FMT_RGB888,
4103 static const struct drm_display_mode boe_tv080wum_nl0_mode = {
4106 .hsync_start = 1200 + 120,
4107 .hsync_end = 1200 + 120 + 20,
4108 .htotal = 1200 + 120 + 20 + 21,
4110 .vsync_start = 1920 + 21,
4111 .vsync_end = 1920 + 21 + 3,
4112 .vtotal = 1920 + 21 + 3 + 18,
4113 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
4116 static const struct panel_desc_dsi boe_tv080wum_nl0 = {
4118 .modes = &boe_tv080wum_nl0_mode,
4124 .connector_type = DRM_MODE_CONNECTOR_DSI,
4126 .flags = MIPI_DSI_MODE_VIDEO |
4127 MIPI_DSI_MODE_VIDEO_BURST |
4128 MIPI_DSI_MODE_VIDEO_SYNC_PULSE,
4129 .format = MIPI_DSI_FMT_RGB888,
4133 static const struct drm_display_mode lg_ld070wx3_sl01_mode = {
4136 .hsync_start = 800 + 32,
4137 .hsync_end = 800 + 32 + 1,
4138 .htotal = 800 + 32 + 1 + 57,
4140 .vsync_start = 1280 + 28,
4141 .vsync_end = 1280 + 28 + 1,
4142 .vtotal = 1280 + 28 + 1 + 14,
4145 static const struct panel_desc_dsi lg_ld070wx3_sl01 = {
4147 .modes = &lg_ld070wx3_sl01_mode,
4154 .connector_type = DRM_MODE_CONNECTOR_DSI,
4156 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
4157 .format = MIPI_DSI_FMT_RGB888,
4161 static const struct drm_display_mode lg_lh500wx1_sd03_mode = {
4164 .hsync_start = 720 + 12,
4165 .hsync_end = 720 + 12 + 4,
4166 .htotal = 720 + 12 + 4 + 112,
4168 .vsync_start = 1280 + 8,
4169 .vsync_end = 1280 + 8 + 4,
4170 .vtotal = 1280 + 8 + 4 + 12,
4173 static const struct panel_desc_dsi lg_lh500wx1_sd03 = {
4175 .modes = &lg_lh500wx1_sd03_mode,
4182 .connector_type = DRM_MODE_CONNECTOR_DSI,
4184 .flags = MIPI_DSI_MODE_VIDEO,
4185 .format = MIPI_DSI_FMT_RGB888,
4189 static const struct drm_display_mode panasonic_vvx10f004b00_mode = {
4192 .hsync_start = 1920 + 154,
4193 .hsync_end = 1920 + 154 + 16,
4194 .htotal = 1920 + 154 + 16 + 32,
4196 .vsync_start = 1200 + 17,
4197 .vsync_end = 1200 + 17 + 2,
4198 .vtotal = 1200 + 17 + 2 + 16,
4201 static const struct panel_desc_dsi panasonic_vvx10f004b00 = {
4203 .modes = &panasonic_vvx10f004b00_mode,
4210 .connector_type = DRM_MODE_CONNECTOR_DSI,
4212 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
4213 MIPI_DSI_CLOCK_NON_CONTINUOUS,
4214 .format = MIPI_DSI_FMT_RGB888,
4218 static const struct drm_display_mode lg_acx467akm_7_mode = {
4221 .hsync_start = 1080 + 2,
4222 .hsync_end = 1080 + 2 + 2,
4223 .htotal = 1080 + 2 + 2 + 2,
4225 .vsync_start = 1920 + 2,
4226 .vsync_end = 1920 + 2 + 2,
4227 .vtotal = 1920 + 2 + 2 + 2,
4230 static const struct panel_desc_dsi lg_acx467akm_7 = {
4232 .modes = &lg_acx467akm_7_mode,
4239 .connector_type = DRM_MODE_CONNECTOR_DSI,
4242 .format = MIPI_DSI_FMT_RGB888,
4246 static const struct drm_display_mode osd101t2045_53ts_mode = {
4249 .hsync_start = 1920 + 112,
4250 .hsync_end = 1920 + 112 + 16,
4251 .htotal = 1920 + 112 + 16 + 32,
4253 .vsync_start = 1200 + 16,
4254 .vsync_end = 1200 + 16 + 2,
4255 .vtotal = 1200 + 16 + 2 + 16,
4256 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
4259 static const struct panel_desc_dsi osd101t2045_53ts = {
4261 .modes = &osd101t2045_53ts_mode,
4268 .connector_type = DRM_MODE_CONNECTOR_DSI,
4270 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
4271 MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
4272 MIPI_DSI_MODE_NO_EOT_PACKET,
4273 .format = MIPI_DSI_FMT_RGB888,
4277 static const struct of_device_id dsi_of_match[] = {
4279 .compatible = "auo,b080uan01",
4280 .data = &auo_b080uan01
4282 .compatible = "boe,tv080wum-nl0",
4283 .data = &boe_tv080wum_nl0
4285 .compatible = "lg,ld070wx3-sl01",
4286 .data = &lg_ld070wx3_sl01
4288 .compatible = "lg,lh500wx1-sd03",
4289 .data = &lg_lh500wx1_sd03
4291 .compatible = "panasonic,vvx10f004b00",
4292 .data = &panasonic_vvx10f004b00
4294 .compatible = "lg,acx467akm-7",
4295 .data = &lg_acx467akm_7
4297 .compatible = "osddisplays,osd101t2045-53ts",
4298 .data = &osd101t2045_53ts
4303 MODULE_DEVICE_TABLE(of, dsi_of_match);
4305 static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi)
4307 const struct panel_desc_dsi *desc;
4308 const struct of_device_id *id;
4311 id = of_match_node(dsi_of_match, dsi->dev.of_node);
4317 err = panel_simple_probe(&dsi->dev, &desc->desc);
4321 dsi->mode_flags = desc->flags;
4322 dsi->format = desc->format;
4323 dsi->lanes = desc->lanes;
4325 err = mipi_dsi_attach(dsi);
4327 struct panel_simple *panel = mipi_dsi_get_drvdata(dsi);
4329 drm_panel_remove(&panel->base);
4335 static int panel_simple_dsi_remove(struct mipi_dsi_device *dsi)
4339 err = mipi_dsi_detach(dsi);
4341 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err);
4343 return panel_simple_remove(&dsi->dev);
4346 static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi)
4348 panel_simple_shutdown(&dsi->dev);
4351 static struct mipi_dsi_driver panel_simple_dsi_driver = {
4353 .name = "panel-simple-dsi",
4354 .of_match_table = dsi_of_match,
4355 .pm = &panel_simple_pm_ops,
4357 .probe = panel_simple_dsi_probe,
4358 .remove = panel_simple_dsi_remove,
4359 .shutdown = panel_simple_dsi_shutdown,
4362 static int __init panel_simple_init(void)
4366 err = platform_driver_register(&panel_simple_platform_driver);
4370 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) {
4371 err = mipi_dsi_driver_register(&panel_simple_dsi_driver);
4373 goto err_did_platform_register;
4378 err_did_platform_register:
4379 platform_driver_unregister(&panel_simple_platform_driver);
4383 module_init(panel_simple_init);
4385 static void __exit panel_simple_exit(void)
4387 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI))
4388 mipi_dsi_driver_unregister(&panel_simple_dsi_driver);
4390 platform_driver_unregister(&panel_simple_platform_driver);
4392 module_exit(panel_simple_exit);
4394 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
4395 MODULE_DESCRIPTION("DRM Driver for Simple Panels");
4396 MODULE_LICENSE("GPL and additional rights");