2 * Copyright (C) 2013, NVIDIA Corporation. All rights reserved.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sub license,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the
12 * next paragraph) shall be included in all copies or substantial portions
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 #include <linux/delay.h>
25 #include <linux/gpio/consumer.h>
26 #include <linux/i2c.h>
27 #include <linux/media-bus-format.h>
28 #include <linux/module.h>
29 #include <linux/of_platform.h>
30 #include <linux/platform_device.h>
31 #include <linux/pm_runtime.h>
32 #include <linux/regulator/consumer.h>
34 #include <video/display_timing.h>
35 #include <video/of_display_timing.h>
36 #include <video/videomode.h>
38 #include <drm/drm_crtc.h>
39 #include <drm/drm_device.h>
40 #include <drm/drm_edid.h>
41 #include <drm/drm_mipi_dsi.h>
42 #include <drm/drm_panel.h>
45 * struct panel_desc - Describes a simple panel.
49 * @modes: Pointer to array of fixed modes appropriate for this panel.
51 * If only one mode then this can just be the address of the mode.
52 * NOTE: cannot be used with "timings" and also if this is specified
53 * then you cannot override the mode in the device tree.
55 const struct drm_display_mode *modes;
57 /** @num_modes: Number of elements in modes array. */
58 unsigned int num_modes;
61 * @timings: Pointer to array of display timings
63 * NOTE: cannot be used with "modes" and also these will be used to
64 * validate a device tree override if one is present.
66 const struct display_timing *timings;
68 /** @num_timings: Number of elements in timings array. */
69 unsigned int num_timings;
71 /** @bpc: Bits per color. */
74 /** @size: Structure containing the physical size of this panel. */
77 * @size.width: Width (in mm) of the active display area.
82 * @size.height: Height (in mm) of the active display area.
87 /** @delay: Structure containing various delay values for this panel. */
90 * @delay.prepare: Time for the panel to become ready.
92 * The time (in milliseconds) that it takes for the panel to
93 * become ready and start receiving video data
98 * @delay.enable: Time for the panel to display a valid frame.
100 * The time (in milliseconds) that it takes for the panel to
101 * display the first valid frame after starting to receive
107 * @delay.disable: Time for the panel to turn the display off.
109 * The time (in milliseconds) that it takes for the panel to
110 * turn the display off (no content is visible).
112 unsigned int disable;
115 * @delay.unprepare: Time to power down completely.
117 * The time (in milliseconds) that it takes for the panel
118 * to power itself down completely.
120 * This time is used to prevent a future "prepare" from
121 * starting until at least this many milliseconds has passed.
122 * If at prepare time less time has passed since unprepare
123 * finished, the driver waits for the remaining time.
125 unsigned int unprepare;
128 /** @bus_format: See MEDIA_BUS_FMT_... defines. */
131 /** @bus_flags: See DRM_BUS_FLAG_... defines. */
134 /** @connector_type: LVDS, eDP, DSI, DPI, etc. */
138 struct panel_simple {
139 struct drm_panel base;
144 ktime_t unprepared_time;
146 const struct panel_desc *desc;
148 struct regulator *supply;
149 struct i2c_adapter *ddc;
151 struct gpio_desc *enable_gpio;
155 struct drm_display_mode override_mode;
158 static inline struct panel_simple *to_panel_simple(struct drm_panel *panel)
160 return container_of(panel, struct panel_simple, base);
163 static unsigned int panel_simple_get_timings_modes(struct panel_simple *panel,
164 struct drm_connector *connector)
166 struct drm_display_mode *mode;
167 unsigned int i, num = 0;
169 for (i = 0; i < panel->desc->num_timings; i++) {
170 const struct display_timing *dt = &panel->desc->timings[i];
173 videomode_from_timing(dt, &vm);
174 mode = drm_mode_create(connector->dev);
176 dev_err(panel->base.dev, "failed to add mode %ux%u\n",
177 dt->hactive.typ, dt->vactive.typ);
181 drm_display_mode_from_videomode(&vm, mode);
183 mode->type |= DRM_MODE_TYPE_DRIVER;
185 if (panel->desc->num_timings == 1)
186 mode->type |= DRM_MODE_TYPE_PREFERRED;
188 drm_mode_probed_add(connector, mode);
195 static unsigned int panel_simple_get_display_modes(struct panel_simple *panel,
196 struct drm_connector *connector)
198 struct drm_display_mode *mode;
199 unsigned int i, num = 0;
201 for (i = 0; i < panel->desc->num_modes; i++) {
202 const struct drm_display_mode *m = &panel->desc->modes[i];
204 mode = drm_mode_duplicate(connector->dev, m);
206 dev_err(panel->base.dev, "failed to add mode %ux%u@%u\n",
207 m->hdisplay, m->vdisplay,
208 drm_mode_vrefresh(m));
212 mode->type |= DRM_MODE_TYPE_DRIVER;
214 if (panel->desc->num_modes == 1)
215 mode->type |= DRM_MODE_TYPE_PREFERRED;
217 drm_mode_set_name(mode);
219 drm_mode_probed_add(connector, mode);
226 static int panel_simple_get_non_edid_modes(struct panel_simple *panel,
227 struct drm_connector *connector)
229 struct drm_display_mode *mode;
230 bool has_override = panel->override_mode.type;
231 unsigned int num = 0;
237 mode = drm_mode_duplicate(connector->dev,
238 &panel->override_mode);
240 drm_mode_probed_add(connector, mode);
243 dev_err(panel->base.dev, "failed to add override mode\n");
247 /* Only add timings if override was not there or failed to validate */
248 if (num == 0 && panel->desc->num_timings)
249 num = panel_simple_get_timings_modes(panel, connector);
252 * Only add fixed modes if timings/override added no mode.
254 * We should only ever have either the display timings specified
255 * or a fixed mode. Anything else is rather bogus.
257 WARN_ON(panel->desc->num_timings && panel->desc->num_modes);
259 num = panel_simple_get_display_modes(panel, connector);
261 connector->display_info.bpc = panel->desc->bpc;
262 connector->display_info.width_mm = panel->desc->size.width;
263 connector->display_info.height_mm = panel->desc->size.height;
264 if (panel->desc->bus_format)
265 drm_display_info_set_bus_formats(&connector->display_info,
266 &panel->desc->bus_format, 1);
267 connector->display_info.bus_flags = panel->desc->bus_flags;
272 static void panel_simple_wait(ktime_t start_ktime, unsigned int min_ms)
274 ktime_t now_ktime, min_ktime;
279 min_ktime = ktime_add(start_ktime, ms_to_ktime(min_ms));
280 now_ktime = ktime_get_boottime();
282 if (ktime_before(now_ktime, min_ktime))
283 msleep(ktime_to_ms(ktime_sub(min_ktime, now_ktime)) + 1);
286 static int panel_simple_disable(struct drm_panel *panel)
288 struct panel_simple *p = to_panel_simple(panel);
293 if (p->desc->delay.disable)
294 msleep(p->desc->delay.disable);
301 static int panel_simple_suspend(struct device *dev)
303 struct panel_simple *p = dev_get_drvdata(dev);
305 gpiod_set_value_cansleep(p->enable_gpio, 0);
306 regulator_disable(p->supply);
307 p->unprepared_time = ktime_get_boottime();
315 static int panel_simple_unprepare(struct drm_panel *panel)
317 struct panel_simple *p = to_panel_simple(panel);
320 /* Unpreparing when already unprepared is a no-op */
324 pm_runtime_mark_last_busy(panel->dev);
325 ret = pm_runtime_put_autosuspend(panel->dev);
333 static int panel_simple_resume(struct device *dev)
335 struct panel_simple *p = dev_get_drvdata(dev);
338 panel_simple_wait(p->unprepared_time, p->desc->delay.unprepare);
340 err = regulator_enable(p->supply);
342 dev_err(dev, "failed to enable supply: %d\n", err);
346 gpiod_set_value_cansleep(p->enable_gpio, 1);
348 if (p->desc->delay.prepare)
349 msleep(p->desc->delay.prepare);
354 static int panel_simple_prepare(struct drm_panel *panel)
356 struct panel_simple *p = to_panel_simple(panel);
359 /* Preparing when already prepared is a no-op */
363 ret = pm_runtime_get_sync(panel->dev);
365 pm_runtime_put_autosuspend(panel->dev);
374 static int panel_simple_enable(struct drm_panel *panel)
376 struct panel_simple *p = to_panel_simple(panel);
381 if (p->desc->delay.enable)
382 msleep(p->desc->delay.enable);
389 static int panel_simple_get_modes(struct drm_panel *panel,
390 struct drm_connector *connector)
392 struct panel_simple *p = to_panel_simple(panel);
395 /* probe EDID if a DDC bus is available */
397 pm_runtime_get_sync(panel->dev);
400 p->edid = drm_get_edid(connector, p->ddc);
403 num += drm_add_edid_modes(connector, p->edid);
405 pm_runtime_mark_last_busy(panel->dev);
406 pm_runtime_put_autosuspend(panel->dev);
409 /* add hard-coded panel modes */
410 num += panel_simple_get_non_edid_modes(p, connector);
415 static int panel_simple_get_timings(struct drm_panel *panel,
416 unsigned int num_timings,
417 struct display_timing *timings)
419 struct panel_simple *p = to_panel_simple(panel);
422 if (p->desc->num_timings < num_timings)
423 num_timings = p->desc->num_timings;
426 for (i = 0; i < num_timings; i++)
427 timings[i] = p->desc->timings[i];
429 return p->desc->num_timings;
432 static enum drm_panel_orientation panel_simple_get_orientation(struct drm_panel *panel)
434 //struct panel_simple *p = to_panel_simple(panel);
436 return DRM_MODE_PANEL_ORIENTATION_UNKNOWN;
439 static const struct drm_panel_funcs panel_simple_funcs = {
440 .disable = panel_simple_disable,
441 .unprepare = panel_simple_unprepare,
442 .prepare = panel_simple_prepare,
443 .enable = panel_simple_enable,
444 .get_modes = panel_simple_get_modes,
445 .get_orientation = panel_simple_get_orientation,
446 .get_timings = panel_simple_get_timings,
449 static struct panel_desc panel_dpi;
451 static int panel_dpi_probe(struct device *dev,
452 struct panel_simple *panel)
454 struct display_timing *timing;
455 const struct device_node *np;
456 struct panel_desc *desc;
457 unsigned int bus_flags;
462 desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL);
466 timing = devm_kzalloc(dev, sizeof(*timing), GFP_KERNEL);
470 ret = of_get_display_timing(np, "panel-timing", timing);
472 dev_err(dev, "%pOF: no panel-timing node found for \"panel-dpi\" binding\n",
477 desc->timings = timing;
478 desc->num_timings = 1;
480 of_property_read_u32(np, "width-mm", &desc->size.width);
481 of_property_read_u32(np, "height-mm", &desc->size.height);
482 of_property_read_u32(np, "bus-format", &desc->bus_format);
484 /* Extract bus_flags from display_timing */
486 vm.flags = timing->flags;
487 drm_bus_flags_from_videomode(&vm, &bus_flags);
488 desc->bus_flags = bus_flags;
490 /* We do not know the connector for the DT node, so guess it */
491 desc->connector_type = DRM_MODE_CONNECTOR_DPI;
492 /* Likewise for the bit depth. */
500 #define PANEL_SIMPLE_BOUNDS_CHECK(to_check, bounds, field) \
501 (to_check->field.typ >= bounds->field.min && \
502 to_check->field.typ <= bounds->field.max)
503 static void panel_simple_parse_panel_timing_node(struct device *dev,
504 struct panel_simple *panel,
505 const struct display_timing *ot)
507 const struct panel_desc *desc = panel->desc;
511 if (WARN_ON(desc->num_modes)) {
512 dev_err(dev, "Reject override mode: panel has a fixed mode\n");
515 if (WARN_ON(!desc->num_timings)) {
516 dev_err(dev, "Reject override mode: no timings specified\n");
520 for (i = 0; i < panel->desc->num_timings; i++) {
521 const struct display_timing *dt = &panel->desc->timings[i];
523 if (!PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hactive) ||
524 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hfront_porch) ||
525 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hback_porch) ||
526 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hsync_len) ||
527 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vactive) ||
528 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vfront_porch) ||
529 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vback_porch) ||
530 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vsync_len))
533 if (ot->flags != dt->flags)
536 videomode_from_timing(ot, &vm);
537 drm_display_mode_from_videomode(&vm, &panel->override_mode);
538 panel->override_mode.type |= DRM_MODE_TYPE_DRIVER |
539 DRM_MODE_TYPE_PREFERRED;
543 if (WARN_ON(!panel->override_mode.type))
544 dev_err(dev, "Reject override mode: No display_timing found\n");
547 static int panel_simple_probe(struct device *dev, const struct panel_desc *desc)
549 struct panel_simple *panel;
550 struct display_timing dt;
551 struct device_node *ddc;
556 panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL);
560 panel->enabled = false;
563 panel->supply = devm_regulator_get(dev, "power");
564 if (IS_ERR(panel->supply))
565 return PTR_ERR(panel->supply);
567 panel->enable_gpio = devm_gpiod_get_optional(dev, "enable",
569 if (IS_ERR(panel->enable_gpio))
570 return dev_err_probe(dev, PTR_ERR(panel->enable_gpio),
571 "failed to request GPIO\n");
573 ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0);
575 panel->ddc = of_find_i2c_adapter_by_node(ddc);
579 return -EPROBE_DEFER;
582 if (desc == &panel_dpi) {
583 /* Handle the generic panel-dpi binding */
584 err = panel_dpi_probe(dev, panel);
589 if (!of_get_display_timing(dev->of_node, "panel-timing", &dt))
590 panel_simple_parse_panel_timing_node(dev, panel, &dt);
593 connector_type = desc->connector_type;
594 /* Catch common mistakes for panels. */
595 switch (connector_type) {
597 dev_warn(dev, "Specify missing connector_type\n");
598 connector_type = DRM_MODE_CONNECTOR_DPI;
600 case DRM_MODE_CONNECTOR_LVDS:
601 WARN_ON(desc->bus_flags &
602 ~(DRM_BUS_FLAG_DE_LOW |
603 DRM_BUS_FLAG_DE_HIGH |
604 DRM_BUS_FLAG_DATA_MSB_TO_LSB |
605 DRM_BUS_FLAG_DATA_LSB_TO_MSB));
606 WARN_ON(desc->bus_format != MEDIA_BUS_FMT_RGB666_1X7X3_SPWG &&
607 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_SPWG &&
608 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA);
609 WARN_ON(desc->bus_format == MEDIA_BUS_FMT_RGB666_1X7X3_SPWG &&
611 WARN_ON((desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_SPWG ||
612 desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA) &&
615 case DRM_MODE_CONNECTOR_eDP:
616 dev_warn(dev, "eDP panels moved to panel-edp\n");
619 case DRM_MODE_CONNECTOR_DSI:
620 if (desc->bpc != 6 && desc->bpc != 8)
621 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc);
623 case DRM_MODE_CONNECTOR_DPI:
624 bus_flags = DRM_BUS_FLAG_DE_LOW |
625 DRM_BUS_FLAG_DE_HIGH |
626 DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE |
627 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
628 DRM_BUS_FLAG_DATA_MSB_TO_LSB |
629 DRM_BUS_FLAG_DATA_LSB_TO_MSB |
630 DRM_BUS_FLAG_SYNC_SAMPLE_POSEDGE |
631 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE;
632 if (desc->bus_flags & ~bus_flags)
633 dev_warn(dev, "Unexpected bus_flags(%d)\n", desc->bus_flags & ~bus_flags);
634 if (!(desc->bus_flags & bus_flags))
635 dev_warn(dev, "Specify missing bus_flags\n");
636 if (desc->bus_format == 0)
637 dev_warn(dev, "Specify missing bus_format\n");
638 if (desc->bpc != 6 && desc->bpc != 8)
639 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc);
642 dev_warn(dev, "Specify a valid connector_type: %d\n", desc->connector_type);
643 connector_type = DRM_MODE_CONNECTOR_DPI;
647 dev_set_drvdata(dev, panel);
650 * We use runtime PM for prepare / unprepare since those power the panel
651 * on and off and those can be very slow operations. This is important
652 * to optimize powering the panel on briefly to read the EDID before
653 * fully enabling the panel.
655 pm_runtime_enable(dev);
656 pm_runtime_set_autosuspend_delay(dev, 1000);
657 pm_runtime_use_autosuspend(dev);
659 drm_panel_init(&panel->base, dev, &panel_simple_funcs, connector_type);
661 err = drm_panel_of_backlight(&panel->base);
663 dev_err_probe(dev, err, "Could not find backlight\n");
664 goto disable_pm_runtime;
667 drm_panel_add(&panel->base);
672 pm_runtime_dont_use_autosuspend(dev);
673 pm_runtime_disable(dev);
676 put_device(&panel->ddc->dev);
681 static void panel_simple_remove(struct device *dev)
683 struct panel_simple *panel = dev_get_drvdata(dev);
685 drm_panel_remove(&panel->base);
686 drm_panel_disable(&panel->base);
687 drm_panel_unprepare(&panel->base);
689 pm_runtime_dont_use_autosuspend(dev);
690 pm_runtime_disable(dev);
692 put_device(&panel->ddc->dev);
695 static void panel_simple_shutdown(struct device *dev)
697 struct panel_simple *panel = dev_get_drvdata(dev);
699 drm_panel_disable(&panel->base);
700 drm_panel_unprepare(&panel->base);
703 static const struct drm_display_mode ampire_am_1280800n3tzqw_t00h_mode = {
706 .hsync_start = 1280 + 40,
707 .hsync_end = 1280 + 40 + 80,
708 .htotal = 1280 + 40 + 80 + 40,
710 .vsync_start = 800 + 3,
711 .vsync_end = 800 + 3 + 10,
712 .vtotal = 800 + 3 + 10 + 10,
713 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
716 static const struct panel_desc ampire_am_1280800n3tzqw_t00h = {
717 .modes = &ire_am_1280800n3tzqw_t00h_mode,
724 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
725 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
726 .connector_type = DRM_MODE_CONNECTOR_LVDS,
729 static const struct drm_display_mode ampire_am_480272h3tmqw_t01h_mode = {
732 .hsync_start = 480 + 2,
733 .hsync_end = 480 + 2 + 41,
734 .htotal = 480 + 2 + 41 + 2,
736 .vsync_start = 272 + 2,
737 .vsync_end = 272 + 2 + 10,
738 .vtotal = 272 + 2 + 10 + 2,
739 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
742 static const struct panel_desc ampire_am_480272h3tmqw_t01h = {
743 .modes = &ire_am_480272h3tmqw_t01h_mode,
750 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
753 static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = {
756 .hsync_start = 800 + 0,
757 .hsync_end = 800 + 0 + 255,
758 .htotal = 800 + 0 + 255 + 0,
760 .vsync_start = 480 + 2,
761 .vsync_end = 480 + 2 + 45,
762 .vtotal = 480 + 2 + 45 + 0,
763 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
766 static const struct display_timing ampire_am_800480l1tmqw_t00h_timing = {
767 .pixelclock = { 29930000, 33260000, 36590000 },
768 .hactive = { 800, 800, 800 },
769 .hfront_porch = { 1, 40, 168 },
770 .hback_porch = { 88, 88, 88 },
771 .hsync_len = { 1, 128, 128 },
772 .vactive = { 480, 480, 480 },
773 .vfront_porch = { 1, 35, 37 },
774 .vback_porch = { 8, 8, 8 },
775 .vsync_len = { 1, 2, 2 },
776 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
777 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
778 DISPLAY_FLAGS_SYNC_POSEDGE,
781 static const struct panel_desc ampire_am_800480l1tmqw_t00h = {
782 .timings = &ire_am_800480l1tmqw_t00h_timing,
789 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
790 .bus_flags = DRM_BUS_FLAG_DE_HIGH |
791 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
792 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
793 .connector_type = DRM_MODE_CONNECTOR_DPI,
796 static const struct panel_desc ampire_am800480r3tmqwa1h = {
797 .modes = &ire_am800480r3tmqwa1h_mode,
804 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
807 static const struct display_timing ampire_am800600p5tmqw_tb8h_timing = {
808 .pixelclock = { 34500000, 39600000, 50400000 },
809 .hactive = { 800, 800, 800 },
810 .hfront_porch = { 12, 112, 312 },
811 .hback_porch = { 87, 87, 48 },
812 .hsync_len = { 1, 1, 40 },
813 .vactive = { 600, 600, 600 },
814 .vfront_porch = { 1, 21, 61 },
815 .vback_porch = { 38, 38, 19 },
816 .vsync_len = { 1, 1, 20 },
817 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
818 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
819 DISPLAY_FLAGS_SYNC_POSEDGE,
822 static const struct panel_desc ampire_am800600p5tmqwtb8h = {
823 .timings = &ire_am800600p5tmqw_tb8h_timing,
830 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
831 .bus_flags = DRM_BUS_FLAG_DE_HIGH |
832 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
833 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
834 .connector_type = DRM_MODE_CONNECTOR_DPI,
837 static const struct display_timing santek_st0700i5y_rbslw_f_timing = {
838 .pixelclock = { 26400000, 33300000, 46800000 },
839 .hactive = { 800, 800, 800 },
840 .hfront_porch = { 16, 210, 354 },
841 .hback_porch = { 45, 36, 6 },
842 .hsync_len = { 1, 10, 40 },
843 .vactive = { 480, 480, 480 },
844 .vfront_porch = { 7, 22, 147 },
845 .vback_porch = { 22, 13, 3 },
846 .vsync_len = { 1, 10, 20 },
847 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
848 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE
851 static const struct panel_desc armadeus_st0700_adapt = {
852 .timings = &santek_st0700i5y_rbslw_f_timing,
859 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
860 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
863 static const struct drm_display_mode auo_b101aw03_mode = {
866 .hsync_start = 1024 + 156,
867 .hsync_end = 1024 + 156 + 8,
868 .htotal = 1024 + 156 + 8 + 156,
870 .vsync_start = 600 + 16,
871 .vsync_end = 600 + 16 + 6,
872 .vtotal = 600 + 16 + 6 + 16,
875 static const struct panel_desc auo_b101aw03 = {
876 .modes = &auo_b101aw03_mode,
883 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
884 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
885 .connector_type = DRM_MODE_CONNECTOR_LVDS,
888 static const struct drm_display_mode auo_b101xtn01_mode = {
891 .hsync_start = 1366 + 20,
892 .hsync_end = 1366 + 20 + 70,
893 .htotal = 1366 + 20 + 70,
895 .vsync_start = 768 + 14,
896 .vsync_end = 768 + 14 + 42,
897 .vtotal = 768 + 14 + 42,
898 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
901 static const struct panel_desc auo_b101xtn01 = {
902 .modes = &auo_b101xtn01_mode,
911 static const struct drm_display_mode auo_b116xw03_mode = {
914 .hsync_start = 1366 + 40,
915 .hsync_end = 1366 + 40 + 40,
916 .htotal = 1366 + 40 + 40 + 32,
918 .vsync_start = 768 + 10,
919 .vsync_end = 768 + 10 + 12,
920 .vtotal = 768 + 10 + 12 + 6,
921 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
924 static const struct panel_desc auo_b116xw03 = {
925 .modes = &auo_b116xw03_mode,
938 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
939 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
940 .connector_type = DRM_MODE_CONNECTOR_LVDS,
943 static const struct display_timing auo_g070vvn01_timings = {
944 .pixelclock = { 33300000, 34209000, 45000000 },
945 .hactive = { 800, 800, 800 },
946 .hfront_porch = { 20, 40, 200 },
947 .hback_porch = { 87, 40, 1 },
948 .hsync_len = { 1, 48, 87 },
949 .vactive = { 480, 480, 480 },
950 .vfront_porch = { 5, 13, 200 },
951 .vback_porch = { 31, 31, 29 },
952 .vsync_len = { 1, 1, 3 },
955 static const struct panel_desc auo_g070vvn01 = {
956 .timings = &auo_g070vvn01_timings,
971 static const struct drm_display_mode auo_g101evn010_mode = {
974 .hsync_start = 1280 + 82,
975 .hsync_end = 1280 + 82 + 2,
976 .htotal = 1280 + 82 + 2 + 84,
978 .vsync_start = 800 + 8,
979 .vsync_end = 800 + 8 + 2,
980 .vtotal = 800 + 8 + 2 + 6,
983 static const struct panel_desc auo_g101evn010 = {
984 .modes = &auo_g101evn010_mode,
991 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
992 .connector_type = DRM_MODE_CONNECTOR_LVDS,
995 static const struct drm_display_mode auo_g104sn02_mode = {
998 .hsync_start = 800 + 40,
999 .hsync_end = 800 + 40 + 216,
1000 .htotal = 800 + 40 + 216 + 128,
1002 .vsync_start = 600 + 10,
1003 .vsync_end = 600 + 10 + 35,
1004 .vtotal = 600 + 10 + 35 + 2,
1007 static const struct panel_desc auo_g104sn02 = {
1008 .modes = &auo_g104sn02_mode,
1015 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1016 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1019 static const struct display_timing auo_g121ean01_timing = {
1020 .pixelclock = { 60000000, 74400000, 90000000 },
1021 .hactive = { 1280, 1280, 1280 },
1022 .hfront_porch = { 20, 50, 100 },
1023 .hback_porch = { 20, 50, 100 },
1024 .hsync_len = { 30, 100, 200 },
1025 .vactive = { 800, 800, 800 },
1026 .vfront_porch = { 2, 10, 25 },
1027 .vback_porch = { 2, 10, 25 },
1028 .vsync_len = { 4, 18, 50 },
1031 static const struct panel_desc auo_g121ean01 = {
1032 .timings = &auo_g121ean01_timing,
1039 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1040 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1043 static const struct display_timing auo_g133han01_timings = {
1044 .pixelclock = { 134000000, 141200000, 149000000 },
1045 .hactive = { 1920, 1920, 1920 },
1046 .hfront_porch = { 39, 58, 77 },
1047 .hback_porch = { 59, 88, 117 },
1048 .hsync_len = { 28, 42, 56 },
1049 .vactive = { 1080, 1080, 1080 },
1050 .vfront_porch = { 3, 8, 11 },
1051 .vback_porch = { 5, 14, 19 },
1052 .vsync_len = { 4, 14, 19 },
1055 static const struct panel_desc auo_g133han01 = {
1056 .timings = &auo_g133han01_timings,
1069 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
1070 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1073 static const struct drm_display_mode auo_g156xtn01_mode = {
1076 .hsync_start = 1366 + 33,
1077 .hsync_end = 1366 + 33 + 67,
1080 .vsync_start = 768 + 4,
1081 .vsync_end = 768 + 4 + 4,
1085 static const struct panel_desc auo_g156xtn01 = {
1086 .modes = &auo_g156xtn01_mode,
1093 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1094 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1097 static const struct display_timing auo_g185han01_timings = {
1098 .pixelclock = { 120000000, 144000000, 175000000 },
1099 .hactive = { 1920, 1920, 1920 },
1100 .hfront_porch = { 36, 120, 148 },
1101 .hback_porch = { 24, 88, 108 },
1102 .hsync_len = { 20, 48, 64 },
1103 .vactive = { 1080, 1080, 1080 },
1104 .vfront_porch = { 6, 10, 40 },
1105 .vback_porch = { 2, 5, 20 },
1106 .vsync_len = { 2, 5, 20 },
1109 static const struct panel_desc auo_g185han01 = {
1110 .timings = &auo_g185han01_timings,
1123 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1124 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1127 static const struct display_timing auo_g190ean01_timings = {
1128 .pixelclock = { 90000000, 108000000, 135000000 },
1129 .hactive = { 1280, 1280, 1280 },
1130 .hfront_porch = { 126, 184, 1266 },
1131 .hback_porch = { 84, 122, 844 },
1132 .hsync_len = { 70, 102, 704 },
1133 .vactive = { 1024, 1024, 1024 },
1134 .vfront_porch = { 4, 26, 76 },
1135 .vback_porch = { 2, 8, 25 },
1136 .vsync_len = { 2, 8, 25 },
1139 static const struct panel_desc auo_g190ean01 = {
1140 .timings = &auo_g190ean01_timings,
1153 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1154 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1157 static const struct display_timing auo_p320hvn03_timings = {
1158 .pixelclock = { 106000000, 148500000, 164000000 },
1159 .hactive = { 1920, 1920, 1920 },
1160 .hfront_porch = { 25, 50, 130 },
1161 .hback_porch = { 25, 50, 130 },
1162 .hsync_len = { 20, 40, 105 },
1163 .vactive = { 1080, 1080, 1080 },
1164 .vfront_porch = { 8, 17, 150 },
1165 .vback_porch = { 8, 17, 150 },
1166 .vsync_len = { 4, 11, 100 },
1169 static const struct panel_desc auo_p320hvn03 = {
1170 .timings = &auo_p320hvn03_timings,
1182 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1183 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1186 static const struct drm_display_mode auo_t215hvn01_mode = {
1189 .hsync_start = 1920 + 88,
1190 .hsync_end = 1920 + 88 + 44,
1191 .htotal = 1920 + 88 + 44 + 148,
1193 .vsync_start = 1080 + 4,
1194 .vsync_end = 1080 + 4 + 5,
1195 .vtotal = 1080 + 4 + 5 + 36,
1198 static const struct panel_desc auo_t215hvn01 = {
1199 .modes = &auo_t215hvn01_mode,
1210 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1211 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1214 static const struct drm_display_mode avic_tm070ddh03_mode = {
1217 .hsync_start = 1024 + 160,
1218 .hsync_end = 1024 + 160 + 4,
1219 .htotal = 1024 + 160 + 4 + 156,
1221 .vsync_start = 600 + 17,
1222 .vsync_end = 600 + 17 + 1,
1223 .vtotal = 600 + 17 + 1 + 17,
1226 static const struct panel_desc avic_tm070ddh03 = {
1227 .modes = &avic_tm070ddh03_mode,
1241 static const struct drm_display_mode bananapi_s070wv20_ct16_mode = {
1244 .hsync_start = 800 + 40,
1245 .hsync_end = 800 + 40 + 48,
1246 .htotal = 800 + 40 + 48 + 40,
1248 .vsync_start = 480 + 13,
1249 .vsync_end = 480 + 13 + 3,
1250 .vtotal = 480 + 13 + 3 + 29,
1253 static const struct panel_desc bananapi_s070wv20_ct16 = {
1254 .modes = &bananapi_s070wv20_ct16_mode,
1263 static const struct display_timing boe_ev121wxm_n10_1850_timing = {
1264 .pixelclock = { 69922000, 71000000, 72293000 },
1265 .hactive = { 1280, 1280, 1280 },
1266 .hfront_porch = { 48, 48, 48 },
1267 .hback_porch = { 80, 80, 80 },
1268 .hsync_len = { 32, 32, 32 },
1269 .vactive = { 800, 800, 800 },
1270 .vfront_porch = { 3, 3, 3 },
1271 .vback_porch = { 14, 14, 14 },
1272 .vsync_len = { 6, 6, 6 },
1275 static const struct panel_desc boe_ev121wxm_n10_1850 = {
1276 .timings = &boe_ev121wxm_n10_1850_timing,
1289 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1290 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1291 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1294 static const struct drm_display_mode boe_hv070wsa_mode = {
1297 .hsync_start = 1024 + 30,
1298 .hsync_end = 1024 + 30 + 30,
1299 .htotal = 1024 + 30 + 30 + 30,
1301 .vsync_start = 600 + 10,
1302 .vsync_end = 600 + 10 + 10,
1303 .vtotal = 600 + 10 + 10 + 10,
1306 static const struct panel_desc boe_hv070wsa = {
1307 .modes = &boe_hv070wsa_mode,
1314 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1315 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1316 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1319 static const struct drm_display_mode cdtech_s043wq26h_ct7_mode = {
1322 .hsync_start = 480 + 5,
1323 .hsync_end = 480 + 5 + 5,
1324 .htotal = 480 + 5 + 5 + 40,
1326 .vsync_start = 272 + 8,
1327 .vsync_end = 272 + 8 + 8,
1328 .vtotal = 272 + 8 + 8 + 8,
1329 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1332 static const struct panel_desc cdtech_s043wq26h_ct7 = {
1333 .modes = &cdtech_s043wq26h_ct7_mode,
1340 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1343 /* S070PWS19HP-FC21 2017/04/22 */
1344 static const struct drm_display_mode cdtech_s070pws19hp_fc21_mode = {
1347 .hsync_start = 1024 + 160,
1348 .hsync_end = 1024 + 160 + 20,
1349 .htotal = 1024 + 160 + 20 + 140,
1351 .vsync_start = 600 + 12,
1352 .vsync_end = 600 + 12 + 3,
1353 .vtotal = 600 + 12 + 3 + 20,
1354 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1357 static const struct panel_desc cdtech_s070pws19hp_fc21 = {
1358 .modes = &cdtech_s070pws19hp_fc21_mode,
1365 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1366 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
1367 .connector_type = DRM_MODE_CONNECTOR_DPI,
1370 /* S070SWV29HG-DC44 2017/09/21 */
1371 static const struct drm_display_mode cdtech_s070swv29hg_dc44_mode = {
1374 .hsync_start = 800 + 210,
1375 .hsync_end = 800 + 210 + 2,
1376 .htotal = 800 + 210 + 2 + 44,
1378 .vsync_start = 480 + 22,
1379 .vsync_end = 480 + 22 + 2,
1380 .vtotal = 480 + 22 + 2 + 21,
1381 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1384 static const struct panel_desc cdtech_s070swv29hg_dc44 = {
1385 .modes = &cdtech_s070swv29hg_dc44_mode,
1392 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1393 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
1394 .connector_type = DRM_MODE_CONNECTOR_DPI,
1397 static const struct drm_display_mode cdtech_s070wv95_ct16_mode = {
1400 .hsync_start = 800 + 40,
1401 .hsync_end = 800 + 40 + 40,
1402 .htotal = 800 + 40 + 40 + 48,
1404 .vsync_start = 480 + 29,
1405 .vsync_end = 480 + 29 + 13,
1406 .vtotal = 480 + 29 + 13 + 3,
1407 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1410 static const struct panel_desc cdtech_s070wv95_ct16 = {
1411 .modes = &cdtech_s070wv95_ct16_mode,
1420 static const struct display_timing chefree_ch101olhlwh_002_timing = {
1421 .pixelclock = { 68900000, 71100000, 73400000 },
1422 .hactive = { 1280, 1280, 1280 },
1423 .hfront_porch = { 65, 80, 95 },
1424 .hback_porch = { 64, 79, 94 },
1425 .hsync_len = { 1, 1, 1 },
1426 .vactive = { 800, 800, 800 },
1427 .vfront_porch = { 7, 11, 14 },
1428 .vback_porch = { 7, 11, 14 },
1429 .vsync_len = { 1, 1, 1 },
1430 .flags = DISPLAY_FLAGS_DE_HIGH,
1433 static const struct panel_desc chefree_ch101olhlwh_002 = {
1434 .timings = &chefree_ch101olhlwh_002_timing,
1445 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1446 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1447 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1450 static const struct drm_display_mode chunghwa_claa070wp03xg_mode = {
1453 .hsync_start = 800 + 49,
1454 .hsync_end = 800 + 49 + 33,
1455 .htotal = 800 + 49 + 33 + 17,
1457 .vsync_start = 1280 + 1,
1458 .vsync_end = 1280 + 1 + 7,
1459 .vtotal = 1280 + 1 + 7 + 15,
1460 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1463 static const struct panel_desc chunghwa_claa070wp03xg = {
1464 .modes = &chunghwa_claa070wp03xg_mode,
1471 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1472 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1473 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1476 static const struct drm_display_mode chunghwa_claa101wa01a_mode = {
1479 .hsync_start = 1366 + 58,
1480 .hsync_end = 1366 + 58 + 58,
1481 .htotal = 1366 + 58 + 58 + 58,
1483 .vsync_start = 768 + 4,
1484 .vsync_end = 768 + 4 + 4,
1485 .vtotal = 768 + 4 + 4 + 4,
1488 static const struct panel_desc chunghwa_claa101wa01a = {
1489 .modes = &chunghwa_claa101wa01a_mode,
1496 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1497 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1498 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1501 static const struct drm_display_mode chunghwa_claa101wb01_mode = {
1504 .hsync_start = 1366 + 48,
1505 .hsync_end = 1366 + 48 + 32,
1506 .htotal = 1366 + 48 + 32 + 20,
1508 .vsync_start = 768 + 16,
1509 .vsync_end = 768 + 16 + 8,
1510 .vtotal = 768 + 16 + 8 + 16,
1513 static const struct panel_desc chunghwa_claa101wb01 = {
1514 .modes = &chunghwa_claa101wb01_mode,
1521 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1522 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1523 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1526 static const struct display_timing dataimage_fg040346dsswbg04_timing = {
1527 .pixelclock = { 5000000, 9000000, 12000000 },
1528 .hactive = { 480, 480, 480 },
1529 .hfront_porch = { 12, 12, 12 },
1530 .hback_porch = { 12, 12, 12 },
1531 .hsync_len = { 21, 21, 21 },
1532 .vactive = { 272, 272, 272 },
1533 .vfront_porch = { 4, 4, 4 },
1534 .vback_porch = { 4, 4, 4 },
1535 .vsync_len = { 8, 8, 8 },
1538 static const struct panel_desc dataimage_fg040346dsswbg04 = {
1539 .timings = &dataimage_fg040346dsswbg04_timing,
1546 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1547 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1548 .connector_type = DRM_MODE_CONNECTOR_DPI,
1551 static const struct display_timing dataimage_fg1001l0dsswmg01_timing = {
1552 .pixelclock = { 68900000, 71110000, 73400000 },
1553 .hactive = { 1280, 1280, 1280 },
1554 .vactive = { 800, 800, 800 },
1555 .hback_porch = { 100, 100, 100 },
1556 .hfront_porch = { 100, 100, 100 },
1557 .vback_porch = { 5, 5, 5 },
1558 .vfront_porch = { 5, 5, 5 },
1559 .hsync_len = { 24, 24, 24 },
1560 .vsync_len = { 3, 3, 3 },
1561 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
1562 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
1565 static const struct panel_desc dataimage_fg1001l0dsswmg01 = {
1566 .timings = &dataimage_fg1001l0dsswmg01_timing,
1575 static const struct drm_display_mode dataimage_scf0700c48ggu18_mode = {
1578 .hsync_start = 800 + 40,
1579 .hsync_end = 800 + 40 + 128,
1580 .htotal = 800 + 40 + 128 + 88,
1582 .vsync_start = 480 + 10,
1583 .vsync_end = 480 + 10 + 2,
1584 .vtotal = 480 + 10 + 2 + 33,
1585 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1588 static const struct panel_desc dataimage_scf0700c48ggu18 = {
1589 .modes = &dataimage_scf0700c48ggu18_mode,
1596 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1597 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1600 static const struct display_timing dlc_dlc0700yzg_1_timing = {
1601 .pixelclock = { 45000000, 51200000, 57000000 },
1602 .hactive = { 1024, 1024, 1024 },
1603 .hfront_porch = { 100, 106, 113 },
1604 .hback_porch = { 100, 106, 113 },
1605 .hsync_len = { 100, 108, 114 },
1606 .vactive = { 600, 600, 600 },
1607 .vfront_porch = { 8, 11, 15 },
1608 .vback_porch = { 8, 11, 15 },
1609 .vsync_len = { 9, 13, 15 },
1610 .flags = DISPLAY_FLAGS_DE_HIGH,
1613 static const struct panel_desc dlc_dlc0700yzg_1 = {
1614 .timings = &dlc_dlc0700yzg_1_timing,
1626 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1627 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1630 static const struct display_timing dlc_dlc1010gig_timing = {
1631 .pixelclock = { 68900000, 71100000, 73400000 },
1632 .hactive = { 1280, 1280, 1280 },
1633 .hfront_porch = { 43, 53, 63 },
1634 .hback_porch = { 43, 53, 63 },
1635 .hsync_len = { 44, 54, 64 },
1636 .vactive = { 800, 800, 800 },
1637 .vfront_porch = { 5, 8, 11 },
1638 .vback_porch = { 5, 8, 11 },
1639 .vsync_len = { 5, 7, 11 },
1640 .flags = DISPLAY_FLAGS_DE_HIGH,
1643 static const struct panel_desc dlc_dlc1010gig = {
1644 .timings = &dlc_dlc1010gig_timing,
1657 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1658 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1661 static const struct drm_display_mode edt_et035012dm6_mode = {
1664 .hsync_start = 320 + 20,
1665 .hsync_end = 320 + 20 + 30,
1666 .htotal = 320 + 20 + 68,
1668 .vsync_start = 240 + 4,
1669 .vsync_end = 240 + 4 + 4,
1670 .vtotal = 240 + 4 + 4 + 14,
1671 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1674 static const struct panel_desc edt_et035012dm6 = {
1675 .modes = &edt_et035012dm6_mode,
1682 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1683 .bus_flags = DRM_BUS_FLAG_DE_LOW | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
1686 static const struct drm_display_mode edt_etm0350g0dh6_mode = {
1689 .hsync_start = 320 + 20,
1690 .hsync_end = 320 + 20 + 68,
1691 .htotal = 320 + 20 + 68,
1693 .vsync_start = 240 + 4,
1694 .vsync_end = 240 + 4 + 18,
1695 .vtotal = 240 + 4 + 18,
1696 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1699 static const struct panel_desc edt_etm0350g0dh6 = {
1700 .modes = &edt_etm0350g0dh6_mode,
1707 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1708 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
1709 .connector_type = DRM_MODE_CONNECTOR_DPI,
1712 static const struct drm_display_mode edt_etm043080dh6gp_mode = {
1715 .hsync_start = 480 + 8,
1716 .hsync_end = 480 + 8 + 4,
1717 .htotal = 480 + 8 + 4 + 41,
1720 * IWG22M: Y resolution changed for "dc_linuxfb" module crashing while
1725 .vsync_start = 288 + 2,
1726 .vsync_end = 288 + 2 + 4,
1727 .vtotal = 288 + 2 + 4 + 10,
1730 static const struct panel_desc edt_etm043080dh6gp = {
1731 .modes = &edt_etm043080dh6gp_mode,
1738 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1739 .connector_type = DRM_MODE_CONNECTOR_DPI,
1742 static const struct drm_display_mode edt_etm0430g0dh6_mode = {
1745 .hsync_start = 480 + 2,
1746 .hsync_end = 480 + 2 + 41,
1747 .htotal = 480 + 2 + 41 + 2,
1749 .vsync_start = 272 + 2,
1750 .vsync_end = 272 + 2 + 10,
1751 .vtotal = 272 + 2 + 10 + 2,
1752 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1755 static const struct panel_desc edt_etm0430g0dh6 = {
1756 .modes = &edt_etm0430g0dh6_mode,
1763 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1764 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
1765 .connector_type = DRM_MODE_CONNECTOR_DPI,
1768 static const struct drm_display_mode edt_et057090dhu_mode = {
1771 .hsync_start = 640 + 16,
1772 .hsync_end = 640 + 16 + 30,
1773 .htotal = 640 + 16 + 30 + 114,
1775 .vsync_start = 480 + 10,
1776 .vsync_end = 480 + 10 + 3,
1777 .vtotal = 480 + 10 + 3 + 32,
1778 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1781 static const struct panel_desc edt_et057090dhu = {
1782 .modes = &edt_et057090dhu_mode,
1789 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1790 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
1791 .connector_type = DRM_MODE_CONNECTOR_DPI,
1794 static const struct drm_display_mode edt_etm0700g0dh6_mode = {
1797 .hsync_start = 800 + 40,
1798 .hsync_end = 800 + 40 + 128,
1799 .htotal = 800 + 40 + 128 + 88,
1801 .vsync_start = 480 + 10,
1802 .vsync_end = 480 + 10 + 2,
1803 .vtotal = 480 + 10 + 2 + 33,
1804 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1807 static const struct panel_desc edt_etm0700g0dh6 = {
1808 .modes = &edt_etm0700g0dh6_mode,
1815 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1816 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
1817 .connector_type = DRM_MODE_CONNECTOR_DPI,
1820 static const struct panel_desc edt_etm0700g0bdh6 = {
1821 .modes = &edt_etm0700g0dh6_mode,
1828 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1829 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1830 .connector_type = DRM_MODE_CONNECTOR_DPI,
1833 static const struct display_timing edt_etml0700y5dha_timing = {
1834 .pixelclock = { 40800000, 51200000, 67200000 },
1835 .hactive = { 1024, 1024, 1024 },
1836 .hfront_porch = { 30, 106, 125 },
1837 .hback_porch = { 30, 106, 125 },
1838 .hsync_len = { 30, 108, 126 },
1839 .vactive = { 600, 600, 600 },
1840 .vfront_porch = { 3, 12, 67},
1841 .vback_porch = { 3, 12, 67 },
1842 .vsync_len = { 4, 11, 66 },
1843 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
1844 DISPLAY_FLAGS_DE_HIGH,
1847 static const struct panel_desc edt_etml0700y5dha = {
1848 .timings = &edt_etml0700y5dha_timing,
1855 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1856 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1859 static const struct drm_display_mode edt_etmv570g2dhu_mode = {
1863 .hsync_end = 640 + 16,
1864 .htotal = 640 + 16 + 30 + 114,
1866 .vsync_start = 480 + 10,
1867 .vsync_end = 480 + 10 + 3,
1868 .vtotal = 480 + 10 + 3 + 35,
1869 .flags = DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_PHSYNC,
1872 static const struct panel_desc edt_etmv570g2dhu = {
1873 .modes = &edt_etmv570g2dhu_mode,
1880 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1881 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
1882 .connector_type = DRM_MODE_CONNECTOR_DPI,
1885 static const struct display_timing eink_vb3300_kca_timing = {
1886 .pixelclock = { 40000000, 40000000, 40000000 },
1887 .hactive = { 334, 334, 334 },
1888 .hfront_porch = { 1, 1, 1 },
1889 .hback_porch = { 1, 1, 1 },
1890 .hsync_len = { 1, 1, 1 },
1891 .vactive = { 1405, 1405, 1405 },
1892 .vfront_porch = { 1, 1, 1 },
1893 .vback_porch = { 1, 1, 1 },
1894 .vsync_len = { 1, 1, 1 },
1895 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
1896 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE,
1899 static const struct panel_desc eink_vb3300_kca = {
1900 .timings = &eink_vb3300_kca_timing,
1907 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1908 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1909 .connector_type = DRM_MODE_CONNECTOR_DPI,
1912 static const struct display_timing evervision_vgg804821_timing = {
1913 .pixelclock = { 27600000, 33300000, 50000000 },
1914 .hactive = { 800, 800, 800 },
1915 .hfront_porch = { 40, 66, 70 },
1916 .hback_porch = { 40, 67, 70 },
1917 .hsync_len = { 40, 67, 70 },
1918 .vactive = { 480, 480, 480 },
1919 .vfront_porch = { 6, 10, 10 },
1920 .vback_porch = { 7, 11, 11 },
1921 .vsync_len = { 7, 11, 11 },
1922 .flags = DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH |
1923 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE |
1924 DISPLAY_FLAGS_SYNC_NEGEDGE,
1927 static const struct panel_desc evervision_vgg804821 = {
1928 .timings = &evervision_vgg804821_timing,
1935 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1936 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
1939 static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = {
1942 .hsync_start = 800 + 168,
1943 .hsync_end = 800 + 168 + 64,
1944 .htotal = 800 + 168 + 64 + 88,
1946 .vsync_start = 480 + 37,
1947 .vsync_end = 480 + 37 + 2,
1948 .vtotal = 480 + 37 + 2 + 8,
1951 static const struct panel_desc foxlink_fl500wvr00_a0t = {
1952 .modes = &foxlink_fl500wvr00_a0t_mode,
1959 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1962 static const struct drm_display_mode frida_frd350h54004_modes[] = {
1966 .hsync_start = 320 + 44,
1967 .hsync_end = 320 + 44 + 16,
1968 .htotal = 320 + 44 + 16 + 20,
1970 .vsync_start = 240 + 2,
1971 .vsync_end = 240 + 2 + 6,
1972 .vtotal = 240 + 2 + 6 + 2,
1973 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1978 .hsync_start = 320 + 56,
1979 .hsync_end = 320 + 56 + 16,
1980 .htotal = 320 + 56 + 16 + 40,
1982 .vsync_start = 240 + 2,
1983 .vsync_end = 240 + 2 + 6,
1984 .vtotal = 240 + 2 + 6 + 2,
1985 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1989 static const struct panel_desc frida_frd350h54004 = {
1990 .modes = frida_frd350h54004_modes,
1991 .num_modes = ARRAY_SIZE(frida_frd350h54004_modes),
1997 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1998 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
1999 .connector_type = DRM_MODE_CONNECTOR_DPI,
2002 static const struct drm_display_mode friendlyarm_hd702e_mode = {
2005 .hsync_start = 800 + 20,
2006 .hsync_end = 800 + 20 + 24,
2007 .htotal = 800 + 20 + 24 + 20,
2009 .vsync_start = 1280 + 4,
2010 .vsync_end = 1280 + 4 + 8,
2011 .vtotal = 1280 + 4 + 8 + 4,
2012 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2015 static const struct panel_desc friendlyarm_hd702e = {
2016 .modes = &friendlyarm_hd702e_mode,
2024 static const struct drm_display_mode geekworm_mzp280_mode = {
2027 .hsync_start = 480 + 41,
2028 .hsync_end = 480 + 41 + 20,
2029 .htotal = 480 + 41 + 20 + 60,
2031 .vsync_start = 640 + 5,
2032 .vsync_end = 640 + 5 + 10,
2033 .vtotal = 640 + 5 + 10 + 10,
2034 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2037 static const struct panel_desc geekworm_mzp280 = {
2038 .modes = &geekworm_mzp280_mode,
2045 .bus_format = MEDIA_BUS_FMT_RGB565_1X24_CPADHI,
2046 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
2047 .connector_type = DRM_MODE_CONNECTOR_DPI,
2050 static const struct drm_display_mode giantplus_gpg482739qs5_mode = {
2053 .hsync_start = 480 + 5,
2054 .hsync_end = 480 + 5 + 1,
2055 .htotal = 480 + 5 + 1 + 40,
2057 .vsync_start = 272 + 8,
2058 .vsync_end = 272 + 8 + 1,
2059 .vtotal = 272 + 8 + 1 + 8,
2062 static const struct panel_desc giantplus_gpg482739qs5 = {
2063 .modes = &giantplus_gpg482739qs5_mode,
2070 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2073 static const struct display_timing giantplus_gpm940b0_timing = {
2074 .pixelclock = { 13500000, 27000000, 27500000 },
2075 .hactive = { 320, 320, 320 },
2076 .hfront_porch = { 14, 686, 718 },
2077 .hback_porch = { 50, 70, 255 },
2078 .hsync_len = { 1, 1, 1 },
2079 .vactive = { 240, 240, 240 },
2080 .vfront_porch = { 1, 1, 179 },
2081 .vback_porch = { 1, 21, 31 },
2082 .vsync_len = { 1, 1, 6 },
2083 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
2086 static const struct panel_desc giantplus_gpm940b0 = {
2087 .timings = &giantplus_gpm940b0_timing,
2094 .bus_format = MEDIA_BUS_FMT_RGB888_3X8,
2095 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
2098 static const struct display_timing hannstar_hsd070pww1_timing = {
2099 .pixelclock = { 64300000, 71100000, 82000000 },
2100 .hactive = { 1280, 1280, 1280 },
2101 .hfront_porch = { 1, 1, 10 },
2102 .hback_porch = { 1, 1, 10 },
2104 * According to the data sheet, the minimum horizontal blanking interval
2105 * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the
2106 * minimum working horizontal blanking interval to be 60 clocks.
2108 .hsync_len = { 58, 158, 661 },
2109 .vactive = { 800, 800, 800 },
2110 .vfront_porch = { 1, 1, 10 },
2111 .vback_porch = { 1, 1, 10 },
2112 .vsync_len = { 1, 21, 203 },
2113 .flags = DISPLAY_FLAGS_DE_HIGH,
2116 static const struct panel_desc hannstar_hsd070pww1 = {
2117 .timings = &hannstar_hsd070pww1_timing,
2124 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2125 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2128 static const struct display_timing hannstar_hsd100pxn1_timing = {
2129 .pixelclock = { 55000000, 65000000, 75000000 },
2130 .hactive = { 1024, 1024, 1024 },
2131 .hfront_porch = { 40, 40, 40 },
2132 .hback_porch = { 220, 220, 220 },
2133 .hsync_len = { 20, 60, 100 },
2134 .vactive = { 768, 768, 768 },
2135 .vfront_porch = { 7, 7, 7 },
2136 .vback_porch = { 21, 21, 21 },
2137 .vsync_len = { 10, 10, 10 },
2138 .flags = DISPLAY_FLAGS_DE_HIGH,
2141 static const struct panel_desc hannstar_hsd100pxn1 = {
2142 .timings = &hannstar_hsd100pxn1_timing,
2149 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2150 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2153 static const struct display_timing hannstar_hsd101pww2_timing = {
2154 .pixelclock = { 64300000, 71100000, 82000000 },
2155 .hactive = { 1280, 1280, 1280 },
2156 .hfront_porch = { 1, 1, 10 },
2157 .hback_porch = { 1, 1, 10 },
2158 .hsync_len = { 58, 158, 661 },
2159 .vactive = { 800, 800, 800 },
2160 .vfront_porch = { 1, 1, 10 },
2161 .vback_porch = { 1, 1, 10 },
2162 .vsync_len = { 1, 21, 203 },
2163 .flags = DISPLAY_FLAGS_DE_HIGH,
2166 static const struct panel_desc hannstar_hsd101pww2 = {
2167 .timings = &hannstar_hsd101pww2_timing,
2174 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2175 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2178 static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = {
2181 .hsync_start = 800 + 85,
2182 .hsync_end = 800 + 85 + 86,
2183 .htotal = 800 + 85 + 86 + 85,
2185 .vsync_start = 480 + 16,
2186 .vsync_end = 480 + 16 + 13,
2187 .vtotal = 480 + 16 + 13 + 16,
2190 static const struct panel_desc hitachi_tx23d38vm0caa = {
2191 .modes = &hitachi_tx23d38vm0caa_mode,
2204 static const struct drm_display_mode innolux_at043tn24_mode = {
2207 .hsync_start = 480 + 2,
2208 .hsync_end = 480 + 2 + 41,
2209 .htotal = 480 + 2 + 41 + 2,
2211 .vsync_start = 272 + 2,
2212 .vsync_end = 272 + 2 + 10,
2213 .vtotal = 272 + 2 + 10 + 2,
2214 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
2217 static const struct panel_desc innolux_at043tn24 = {
2218 .modes = &innolux_at043tn24_mode,
2225 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2226 .connector_type = DRM_MODE_CONNECTOR_DPI,
2227 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
2230 static const struct display_timing innolux_at056tn53v1_timing = {
2231 .pixelclock = { 39700000, 39700000, 39700000},
2232 .hactive = { 640, 640, 640 },
2233 .hfront_porch = { 16, 16, 16 },
2234 .hback_porch = { 134, 134, 134 },
2235 .hsync_len = { 10, 10, 10},
2236 .vactive = { 480, 480, 480 },
2237 .vfront_porch = { 32, 32, 32},
2238 .vback_porch = { 11, 11, 11 },
2239 .vsync_len = { 2, 2, 2 },
2240 .flags = DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_PHSYNC,
2243 static const struct panel_desc innolux_at056tn53v1 = {
2244 .timings = &innolux_at056tn53v1_timing,
2257 .bus_format = MEDIA_BUS_FMT_BGR666_1X24_CPADHI,
2258 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
2259 .connector_type = DRM_MODE_CONNECTOR_DPI,
2262 static const struct drm_display_mode innolux_at070tn92_mode = {
2265 .hsync_start = 800 + 210,
2266 .hsync_end = 800 + 210 + 20,
2267 .htotal = 800 + 210 + 20 + 46,
2269 .vsync_start = 480 + 22,
2270 .vsync_end = 480 + 22 + 10,
2271 .vtotal = 480 + 22 + 23 + 10,
2274 static const struct panel_desc innolux_at070tn92 = {
2275 .modes = &innolux_at070tn92_mode,
2281 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2284 static const struct display_timing innolux_g070ace_l01_timing = {
2285 .pixelclock = { 25200000, 35000000, 35700000 },
2286 .hactive = { 800, 800, 800 },
2287 .hfront_porch = { 30, 32, 87 },
2288 .hback_porch = { 30, 32, 87 },
2289 .hsync_len = { 1, 1, 1 },
2290 .vactive = { 480, 480, 480 },
2291 .vfront_porch = { 3, 3, 3 },
2292 .vback_porch = { 13, 13, 13 },
2293 .vsync_len = { 1, 1, 4 },
2294 .flags = DISPLAY_FLAGS_DE_HIGH,
2297 static const struct panel_desc innolux_g070ace_l01 = {
2298 .timings = &innolux_g070ace_l01_timing,
2311 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2312 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2313 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2316 static const struct display_timing innolux_g070y2_l01_timing = {
2317 .pixelclock = { 28000000, 29500000, 32000000 },
2318 .hactive = { 800, 800, 800 },
2319 .hfront_porch = { 61, 91, 141 },
2320 .hback_porch = { 60, 90, 140 },
2321 .hsync_len = { 12, 12, 12 },
2322 .vactive = { 480, 480, 480 },
2323 .vfront_porch = { 4, 9, 30 },
2324 .vback_porch = { 4, 8, 28 },
2325 .vsync_len = { 2, 2, 2 },
2326 .flags = DISPLAY_FLAGS_DE_HIGH,
2329 static const struct panel_desc innolux_g070y2_l01 = {
2330 .timings = &innolux_g070y2_l01_timing,
2343 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2344 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2345 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2348 static const struct drm_display_mode innolux_g070y2_t02_mode = {
2351 .hsync_start = 800 + 210,
2352 .hsync_end = 800 + 210 + 20,
2353 .htotal = 800 + 210 + 20 + 46,
2355 .vsync_start = 480 + 22,
2356 .vsync_end = 480 + 22 + 10,
2357 .vtotal = 480 + 22 + 23 + 10,
2360 static const struct panel_desc innolux_g070y2_t02 = {
2361 .modes = &innolux_g070y2_t02_mode,
2368 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2369 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
2370 .connector_type = DRM_MODE_CONNECTOR_DPI,
2373 static const struct display_timing innolux_g101ice_l01_timing = {
2374 .pixelclock = { 60400000, 71100000, 74700000 },
2375 .hactive = { 1280, 1280, 1280 },
2376 .hfront_porch = { 30, 60, 70 },
2377 .hback_porch = { 30, 60, 70 },
2378 .hsync_len = { 22, 40, 60 },
2379 .vactive = { 800, 800, 800 },
2380 .vfront_porch = { 3, 8, 14 },
2381 .vback_porch = { 3, 8, 14 },
2382 .vsync_len = { 4, 7, 12 },
2383 .flags = DISPLAY_FLAGS_DE_HIGH,
2386 static const struct panel_desc innolux_g101ice_l01 = {
2387 .timings = &innolux_g101ice_l01_timing,
2398 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2399 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2400 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2403 static const struct display_timing innolux_g121i1_l01_timing = {
2404 .pixelclock = { 67450000, 71000000, 74550000 },
2405 .hactive = { 1280, 1280, 1280 },
2406 .hfront_porch = { 40, 80, 160 },
2407 .hback_porch = { 39, 79, 159 },
2408 .hsync_len = { 1, 1, 1 },
2409 .vactive = { 800, 800, 800 },
2410 .vfront_porch = { 5, 11, 100 },
2411 .vback_porch = { 4, 11, 99 },
2412 .vsync_len = { 1, 1, 1 },
2415 static const struct panel_desc innolux_g121i1_l01 = {
2416 .timings = &innolux_g121i1_l01_timing,
2427 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2428 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2431 static const struct drm_display_mode innolux_g121x1_l03_mode = {
2434 .hsync_start = 1024 + 0,
2435 .hsync_end = 1024 + 1,
2436 .htotal = 1024 + 0 + 1 + 320,
2438 .vsync_start = 768 + 38,
2439 .vsync_end = 768 + 38 + 1,
2440 .vtotal = 768 + 38 + 1 + 0,
2441 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
2444 static const struct panel_desc innolux_g121x1_l03 = {
2445 .modes = &innolux_g121x1_l03_mode,
2459 static const struct display_timing innolux_g156hce_l01_timings = {
2460 .pixelclock = { 120000000, 141860000, 150000000 },
2461 .hactive = { 1920, 1920, 1920 },
2462 .hfront_porch = { 80, 90, 100 },
2463 .hback_porch = { 80, 90, 100 },
2464 .hsync_len = { 20, 30, 30 },
2465 .vactive = { 1080, 1080, 1080 },
2466 .vfront_porch = { 3, 10, 20 },
2467 .vback_porch = { 3, 10, 20 },
2468 .vsync_len = { 4, 10, 10 },
2471 static const struct panel_desc innolux_g156hce_l01 = {
2472 .timings = &innolux_g156hce_l01_timings,
2480 .prepare = 1, /* T1+T2 */
2481 .enable = 450, /* T5 */
2482 .disable = 200, /* T6 */
2483 .unprepare = 10, /* T3+T7 */
2485 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2486 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2487 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2490 static const struct drm_display_mode innolux_n156bge_l21_mode = {
2493 .hsync_start = 1366 + 16,
2494 .hsync_end = 1366 + 16 + 34,
2495 .htotal = 1366 + 16 + 34 + 50,
2497 .vsync_start = 768 + 2,
2498 .vsync_end = 768 + 2 + 6,
2499 .vtotal = 768 + 2 + 6 + 12,
2502 static const struct panel_desc innolux_n156bge_l21 = {
2503 .modes = &innolux_n156bge_l21_mode,
2510 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2511 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2512 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2515 static const struct drm_display_mode innolux_zj070na_01p_mode = {
2518 .hsync_start = 1024 + 128,
2519 .hsync_end = 1024 + 128 + 64,
2520 .htotal = 1024 + 128 + 64 + 128,
2522 .vsync_start = 600 + 16,
2523 .vsync_end = 600 + 16 + 4,
2524 .vtotal = 600 + 16 + 4 + 16,
2527 static const struct panel_desc innolux_zj070na_01p = {
2528 .modes = &innolux_zj070na_01p_mode,
2537 static const struct display_timing koe_tx14d24vm1bpa_timing = {
2538 .pixelclock = { 5580000, 5850000, 6200000 },
2539 .hactive = { 320, 320, 320 },
2540 .hfront_porch = { 30, 30, 30 },
2541 .hback_porch = { 30, 30, 30 },
2542 .hsync_len = { 1, 5, 17 },
2543 .vactive = { 240, 240, 240 },
2544 .vfront_porch = { 6, 6, 6 },
2545 .vback_porch = { 5, 5, 5 },
2546 .vsync_len = { 1, 2, 11 },
2547 .flags = DISPLAY_FLAGS_DE_HIGH,
2550 static const struct panel_desc koe_tx14d24vm1bpa = {
2551 .timings = &koe_tx14d24vm1bpa_timing,
2560 static const struct display_timing koe_tx26d202vm0bwa_timing = {
2561 .pixelclock = { 151820000, 156720000, 159780000 },
2562 .hactive = { 1920, 1920, 1920 },
2563 .hfront_porch = { 105, 130, 142 },
2564 .hback_porch = { 45, 70, 82 },
2565 .hsync_len = { 30, 30, 30 },
2566 .vactive = { 1200, 1200, 1200},
2567 .vfront_porch = { 3, 5, 10 },
2568 .vback_porch = { 2, 5, 10 },
2569 .vsync_len = { 5, 5, 5 },
2572 static const struct panel_desc koe_tx26d202vm0bwa = {
2573 .timings = &koe_tx26d202vm0bwa_timing,
2586 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2587 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2588 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2591 static const struct display_timing koe_tx31d200vm0baa_timing = {
2592 .pixelclock = { 39600000, 43200000, 48000000 },
2593 .hactive = { 1280, 1280, 1280 },
2594 .hfront_porch = { 16, 36, 56 },
2595 .hback_porch = { 16, 36, 56 },
2596 .hsync_len = { 8, 8, 8 },
2597 .vactive = { 480, 480, 480 },
2598 .vfront_porch = { 6, 21, 33 },
2599 .vback_porch = { 6, 21, 33 },
2600 .vsync_len = { 8, 8, 8 },
2601 .flags = DISPLAY_FLAGS_DE_HIGH,
2604 static const struct panel_desc koe_tx31d200vm0baa = {
2605 .timings = &koe_tx31d200vm0baa_timing,
2612 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2613 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2616 static const struct display_timing kyo_tcg121xglp_timing = {
2617 .pixelclock = { 52000000, 65000000, 71000000 },
2618 .hactive = { 1024, 1024, 1024 },
2619 .hfront_porch = { 2, 2, 2 },
2620 .hback_porch = { 2, 2, 2 },
2621 .hsync_len = { 86, 124, 244 },
2622 .vactive = { 768, 768, 768 },
2623 .vfront_porch = { 2, 2, 2 },
2624 .vback_porch = { 2, 2, 2 },
2625 .vsync_len = { 6, 34, 73 },
2626 .flags = DISPLAY_FLAGS_DE_HIGH,
2629 static const struct panel_desc kyo_tcg121xglp = {
2630 .timings = &kyo_tcg121xglp_timing,
2637 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2638 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2641 static const struct drm_display_mode lemaker_bl035_rgb_002_mode = {
2644 .hsync_start = 320 + 20,
2645 .hsync_end = 320 + 20 + 30,
2646 .htotal = 320 + 20 + 30 + 38,
2648 .vsync_start = 240 + 4,
2649 .vsync_end = 240 + 4 + 3,
2650 .vtotal = 240 + 4 + 3 + 15,
2653 static const struct panel_desc lemaker_bl035_rgb_002 = {
2654 .modes = &lemaker_bl035_rgb_002_mode,
2660 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2661 .bus_flags = DRM_BUS_FLAG_DE_LOW,
2664 static const struct drm_display_mode lg_lb070wv8_mode = {
2667 .hsync_start = 800 + 88,
2668 .hsync_end = 800 + 88 + 80,
2669 .htotal = 800 + 88 + 80 + 88,
2671 .vsync_start = 480 + 10,
2672 .vsync_end = 480 + 10 + 25,
2673 .vtotal = 480 + 10 + 25 + 10,
2676 static const struct panel_desc lg_lb070wv8 = {
2677 .modes = &lg_lb070wv8_mode,
2684 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2685 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2688 static const struct display_timing logictechno_lt161010_2nh_timing = {
2689 .pixelclock = { 26400000, 33300000, 46800000 },
2690 .hactive = { 800, 800, 800 },
2691 .hfront_porch = { 16, 210, 354 },
2692 .hback_porch = { 46, 46, 46 },
2693 .hsync_len = { 1, 20, 40 },
2694 .vactive = { 480, 480, 480 },
2695 .vfront_porch = { 7, 22, 147 },
2696 .vback_porch = { 23, 23, 23 },
2697 .vsync_len = { 1, 10, 20 },
2698 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
2699 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
2700 DISPLAY_FLAGS_SYNC_POSEDGE,
2703 static const struct panel_desc logictechno_lt161010_2nh = {
2704 .timings = &logictechno_lt161010_2nh_timing,
2711 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2712 .bus_flags = DRM_BUS_FLAG_DE_HIGH |
2713 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
2714 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
2715 .connector_type = DRM_MODE_CONNECTOR_DPI,
2718 static const struct display_timing logictechno_lt170410_2whc_timing = {
2719 .pixelclock = { 68900000, 71100000, 73400000 },
2720 .hactive = { 1280, 1280, 1280 },
2721 .hfront_porch = { 23, 60, 71 },
2722 .hback_porch = { 23, 60, 71 },
2723 .hsync_len = { 15, 40, 47 },
2724 .vactive = { 800, 800, 800 },
2725 .vfront_porch = { 5, 7, 10 },
2726 .vback_porch = { 5, 7, 10 },
2727 .vsync_len = { 6, 9, 12 },
2728 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
2729 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
2730 DISPLAY_FLAGS_SYNC_POSEDGE,
2733 static const struct panel_desc logictechno_lt170410_2whc = {
2734 .timings = &logictechno_lt170410_2whc_timing,
2741 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2742 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2743 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2746 static const struct drm_display_mode logictechno_lttd800480070_l2rt_mode = {
2749 .hsync_start = 800 + 112,
2750 .hsync_end = 800 + 112 + 3,
2751 .htotal = 800 + 112 + 3 + 85,
2753 .vsync_start = 480 + 38,
2754 .vsync_end = 480 + 38 + 3,
2755 .vtotal = 480 + 38 + 3 + 29,
2756 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2759 static const struct panel_desc logictechno_lttd800480070_l2rt = {
2760 .modes = &logictechno_lttd800480070_l2rt_mode,
2773 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2774 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
2775 .connector_type = DRM_MODE_CONNECTOR_DPI,
2778 static const struct drm_display_mode logictechno_lttd800480070_l6wh_rt_mode = {
2781 .hsync_start = 800 + 154,
2782 .hsync_end = 800 + 154 + 3,
2783 .htotal = 800 + 154 + 3 + 43,
2785 .vsync_start = 480 + 47,
2786 .vsync_end = 480 + 47 + 3,
2787 .vtotal = 480 + 47 + 3 + 20,
2788 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2791 static const struct panel_desc logictechno_lttd800480070_l6wh_rt = {
2792 .modes = &logictechno_lttd800480070_l6wh_rt_mode,
2805 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2806 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
2807 .connector_type = DRM_MODE_CONNECTOR_DPI,
2810 static const struct drm_display_mode logicpd_type_28_mode = {
2813 .hsync_start = 480 + 3,
2814 .hsync_end = 480 + 3 + 42,
2815 .htotal = 480 + 3 + 42 + 2,
2818 .vsync_start = 272 + 2,
2819 .vsync_end = 272 + 2 + 11,
2820 .vtotal = 272 + 2 + 11 + 3,
2821 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
2824 static const struct panel_desc logicpd_type_28 = {
2825 .modes = &logicpd_type_28_mode,
2838 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2839 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE |
2840 DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE,
2841 .connector_type = DRM_MODE_CONNECTOR_DPI,
2844 static const struct drm_display_mode mitsubishi_aa070mc01_mode = {
2847 .hsync_start = 800 + 0,
2848 .hsync_end = 800 + 1,
2849 .htotal = 800 + 0 + 1 + 160,
2851 .vsync_start = 480 + 0,
2852 .vsync_end = 480 + 48 + 1,
2853 .vtotal = 480 + 48 + 1 + 0,
2854 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
2857 static const struct panel_desc mitsubishi_aa070mc01 = {
2858 .modes = &mitsubishi_aa070mc01_mode,
2871 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2872 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2873 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2876 static const struct display_timing multi_inno_mi0700s4t_6_timing = {
2877 .pixelclock = { 29000000, 33000000, 38000000 },
2878 .hactive = { 800, 800, 800 },
2879 .hfront_porch = { 180, 210, 240 },
2880 .hback_porch = { 16, 16, 16 },
2881 .hsync_len = { 30, 30, 30 },
2882 .vactive = { 480, 480, 480 },
2883 .vfront_porch = { 12, 22, 32 },
2884 .vback_porch = { 10, 10, 10 },
2885 .vsync_len = { 13, 13, 13 },
2886 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
2887 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
2888 DISPLAY_FLAGS_SYNC_POSEDGE,
2891 static const struct panel_desc multi_inno_mi0700s4t_6 = {
2892 .timings = &multi_inno_mi0700s4t_6_timing,
2899 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2900 .bus_flags = DRM_BUS_FLAG_DE_HIGH |
2901 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
2902 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
2903 .connector_type = DRM_MODE_CONNECTOR_DPI,
2906 static const struct display_timing multi_inno_mi0800ft_9_timing = {
2907 .pixelclock = { 32000000, 40000000, 50000000 },
2908 .hactive = { 800, 800, 800 },
2909 .hfront_porch = { 16, 210, 354 },
2910 .hback_porch = { 6, 26, 45 },
2911 .hsync_len = { 1, 20, 40 },
2912 .vactive = { 600, 600, 600 },
2913 .vfront_porch = { 1, 12, 77 },
2914 .vback_porch = { 3, 13, 22 },
2915 .vsync_len = { 1, 10, 20 },
2916 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
2917 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
2918 DISPLAY_FLAGS_SYNC_POSEDGE,
2921 static const struct panel_desc multi_inno_mi0800ft_9 = {
2922 .timings = &multi_inno_mi0800ft_9_timing,
2929 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2930 .bus_flags = DRM_BUS_FLAG_DE_HIGH |
2931 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
2932 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
2933 .connector_type = DRM_MODE_CONNECTOR_DPI,
2936 static const struct display_timing multi_inno_mi1010ait_1cp_timing = {
2937 .pixelclock = { 68900000, 70000000, 73400000 },
2938 .hactive = { 1280, 1280, 1280 },
2939 .hfront_porch = { 30, 60, 71 },
2940 .hback_porch = { 30, 60, 71 },
2941 .hsync_len = { 10, 10, 48 },
2942 .vactive = { 800, 800, 800 },
2943 .vfront_porch = { 5, 10, 10 },
2944 .vback_porch = { 5, 10, 10 },
2945 .vsync_len = { 5, 6, 13 },
2946 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
2947 DISPLAY_FLAGS_DE_HIGH,
2950 static const struct panel_desc multi_inno_mi1010ait_1cp = {
2951 .timings = &multi_inno_mi1010ait_1cp_timing,
2962 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2963 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2964 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2967 static const struct display_timing nec_nl12880bc20_05_timing = {
2968 .pixelclock = { 67000000, 71000000, 75000000 },
2969 .hactive = { 1280, 1280, 1280 },
2970 .hfront_porch = { 2, 30, 30 },
2971 .hback_porch = { 6, 100, 100 },
2972 .hsync_len = { 2, 30, 30 },
2973 .vactive = { 800, 800, 800 },
2974 .vfront_porch = { 5, 5, 5 },
2975 .vback_porch = { 11, 11, 11 },
2976 .vsync_len = { 7, 7, 7 },
2979 static const struct panel_desc nec_nl12880bc20_05 = {
2980 .timings = &nec_nl12880bc20_05_timing,
2991 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2992 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2995 static const struct drm_display_mode nec_nl4827hc19_05b_mode = {
2998 .hsync_start = 480 + 2,
2999 .hsync_end = 480 + 2 + 41,
3000 .htotal = 480 + 2 + 41 + 2,
3002 .vsync_start = 272 + 2,
3003 .vsync_end = 272 + 2 + 4,
3004 .vtotal = 272 + 2 + 4 + 2,
3005 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3008 static const struct panel_desc nec_nl4827hc19_05b = {
3009 .modes = &nec_nl4827hc19_05b_mode,
3016 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3017 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
3020 static const struct drm_display_mode netron_dy_e231732_mode = {
3023 .hsync_start = 1024 + 160,
3024 .hsync_end = 1024 + 160 + 70,
3025 .htotal = 1024 + 160 + 70 + 90,
3027 .vsync_start = 600 + 127,
3028 .vsync_end = 600 + 127 + 20,
3029 .vtotal = 600 + 127 + 20 + 3,
3032 static const struct panel_desc netron_dy_e231732 = {
3033 .modes = &netron_dy_e231732_mode,
3039 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3042 static const struct drm_display_mode newhaven_nhd_43_480272ef_atxl_mode = {
3045 .hsync_start = 480 + 2,
3046 .hsync_end = 480 + 2 + 41,
3047 .htotal = 480 + 2 + 41 + 2,
3049 .vsync_start = 272 + 2,
3050 .vsync_end = 272 + 2 + 10,
3051 .vtotal = 272 + 2 + 10 + 2,
3052 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3055 static const struct panel_desc newhaven_nhd_43_480272ef_atxl = {
3056 .modes = &newhaven_nhd_43_480272ef_atxl_mode,
3063 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3064 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE |
3065 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
3066 .connector_type = DRM_MODE_CONNECTOR_DPI,
3069 static const struct display_timing nlt_nl192108ac18_02d_timing = {
3070 .pixelclock = { 130000000, 148350000, 163000000 },
3071 .hactive = { 1920, 1920, 1920 },
3072 .hfront_porch = { 80, 100, 100 },
3073 .hback_porch = { 100, 120, 120 },
3074 .hsync_len = { 50, 60, 60 },
3075 .vactive = { 1080, 1080, 1080 },
3076 .vfront_porch = { 12, 30, 30 },
3077 .vback_porch = { 4, 10, 10 },
3078 .vsync_len = { 4, 5, 5 },
3081 static const struct panel_desc nlt_nl192108ac18_02d = {
3082 .timings = &nlt_nl192108ac18_02d_timing,
3092 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3093 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3096 static const struct drm_display_mode nvd_9128_mode = {
3099 .hsync_start = 800 + 130,
3100 .hsync_end = 800 + 130 + 98,
3101 .htotal = 800 + 0 + 130 + 98,
3103 .vsync_start = 480 + 10,
3104 .vsync_end = 480 + 10 + 50,
3105 .vtotal = 480 + 0 + 10 + 50,
3108 static const struct panel_desc nvd_9128 = {
3109 .modes = &nvd_9128_mode,
3116 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3117 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3120 static const struct display_timing okaya_rs800480t_7x0gp_timing = {
3121 .pixelclock = { 30000000, 30000000, 40000000 },
3122 .hactive = { 800, 800, 800 },
3123 .hfront_porch = { 40, 40, 40 },
3124 .hback_porch = { 40, 40, 40 },
3125 .hsync_len = { 1, 48, 48 },
3126 .vactive = { 480, 480, 480 },
3127 .vfront_porch = { 13, 13, 13 },
3128 .vback_porch = { 29, 29, 29 },
3129 .vsync_len = { 3, 3, 3 },
3130 .flags = DISPLAY_FLAGS_DE_HIGH,
3133 static const struct panel_desc okaya_rs800480t_7x0gp = {
3134 .timings = &okaya_rs800480t_7x0gp_timing,
3147 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3150 static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode = {
3153 .hsync_start = 480 + 5,
3154 .hsync_end = 480 + 5 + 30,
3155 .htotal = 480 + 5 + 30 + 10,
3157 .vsync_start = 272 + 8,
3158 .vsync_end = 272 + 8 + 5,
3159 .vtotal = 272 + 8 + 5 + 3,
3162 static const struct panel_desc olimex_lcd_olinuxino_43ts = {
3163 .modes = &olimex_lcd_olinuxino_43ts_mode,
3169 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3173 * 800x480 CVT. The panel appears to be quite accepting, at least as far as
3174 * pixel clocks, but this is the timing that was being used in the Adafruit
3175 * installation instructions.
3177 static const struct drm_display_mode ontat_yx700wv03_mode = {
3187 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3192 * https://www.adafruit.com/images/product-files/2406/c3163.pdf
3194 static const struct panel_desc ontat_yx700wv03 = {
3195 .modes = &ontat_yx700wv03_mode,
3202 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3205 static const struct drm_display_mode ortustech_com37h3m_mode = {
3208 .hsync_start = 480 + 40,
3209 .hsync_end = 480 + 40 + 10,
3210 .htotal = 480 + 40 + 10 + 40,
3212 .vsync_start = 640 + 4,
3213 .vsync_end = 640 + 4 + 2,
3214 .vtotal = 640 + 4 + 2 + 4,
3215 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3218 static const struct panel_desc ortustech_com37h3m = {
3219 .modes = &ortustech_com37h3m_mode,
3223 .width = 56, /* 56.16mm */
3224 .height = 75, /* 74.88mm */
3226 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3227 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
3228 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
3231 static const struct drm_display_mode ortustech_com43h4m85ulc_mode = {
3234 .hsync_start = 480 + 10,
3235 .hsync_end = 480 + 10 + 10,
3236 .htotal = 480 + 10 + 10 + 15,
3238 .vsync_start = 800 + 3,
3239 .vsync_end = 800 + 3 + 3,
3240 .vtotal = 800 + 3 + 3 + 3,
3243 static const struct panel_desc ortustech_com43h4m85ulc = {
3244 .modes = &ortustech_com43h4m85ulc_mode,
3251 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3252 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
3253 .connector_type = DRM_MODE_CONNECTOR_DPI,
3256 static const struct drm_display_mode osddisplays_osd070t1718_19ts_mode = {
3259 .hsync_start = 800 + 210,
3260 .hsync_end = 800 + 210 + 30,
3261 .htotal = 800 + 210 + 30 + 16,
3263 .vsync_start = 480 + 22,
3264 .vsync_end = 480 + 22 + 13,
3265 .vtotal = 480 + 22 + 13 + 10,
3266 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3269 static const struct panel_desc osddisplays_osd070t1718_19ts = {
3270 .modes = &osddisplays_osd070t1718_19ts_mode,
3277 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3278 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE |
3279 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
3280 .connector_type = DRM_MODE_CONNECTOR_DPI,
3283 static const struct drm_display_mode pda_91_00156_a0_mode = {
3286 .hsync_start = 800 + 1,
3287 .hsync_end = 800 + 1 + 64,
3288 .htotal = 800 + 1 + 64 + 64,
3290 .vsync_start = 480 + 1,
3291 .vsync_end = 480 + 1 + 23,
3292 .vtotal = 480 + 1 + 23 + 22,
3295 static const struct panel_desc pda_91_00156_a0 = {
3296 .modes = &pda_91_00156_a0_mode,
3302 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3305 static const struct drm_display_mode powertip_ph800480t013_idf02_mode = {
3308 .hsync_start = 800 + 54,
3309 .hsync_end = 800 + 54 + 2,
3310 .htotal = 800 + 54 + 2 + 44,
3312 .vsync_start = 480 + 49,
3313 .vsync_end = 480 + 49 + 2,
3314 .vtotal = 480 + 49 + 2 + 22,
3315 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3318 static const struct panel_desc powertip_ph800480t013_idf02 = {
3319 .modes = &powertip_ph800480t013_idf02_mode,
3326 .bus_flags = DRM_BUS_FLAG_DE_HIGH |
3327 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
3328 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
3329 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3330 .connector_type = DRM_MODE_CONNECTOR_DPI,
3333 static const struct drm_display_mode qd43003c0_40_mode = {
3336 .hsync_start = 480 + 8,
3337 .hsync_end = 480 + 8 + 4,
3338 .htotal = 480 + 8 + 4 + 39,
3340 .vsync_start = 272 + 4,
3341 .vsync_end = 272 + 4 + 10,
3342 .vtotal = 272 + 4 + 10 + 2,
3345 static const struct panel_desc qd43003c0_40 = {
3346 .modes = &qd43003c0_40_mode,
3353 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3356 static const struct drm_display_mode qishenglong_gopher2b_lcd_modes[] = {
3360 .hsync_start = 480 + 77,
3361 .hsync_end = 480 + 77 + 41,
3362 .htotal = 480 + 77 + 41 + 2,
3364 .vsync_start = 272 + 16,
3365 .vsync_end = 272 + 16 + 10,
3366 .vtotal = 272 + 16 + 10 + 2,
3367 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3372 .hsync_start = 480 + 17,
3373 .hsync_end = 480 + 17 + 41,
3374 .htotal = 480 + 17 + 41 + 2,
3376 .vsync_start = 272 + 116,
3377 .vsync_end = 272 + 116 + 10,
3378 .vtotal = 272 + 116 + 10 + 2,
3379 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3383 static const struct panel_desc qishenglong_gopher2b_lcd = {
3384 .modes = qishenglong_gopher2b_lcd_modes,
3385 .num_modes = ARRAY_SIZE(qishenglong_gopher2b_lcd_modes),
3391 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3392 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
3393 .connector_type = DRM_MODE_CONNECTOR_DPI,
3396 static const struct display_timing rocktech_rk043fn48h_timing = {
3397 .pixelclock = { 6000000, 9000000, 12000000 },
3398 .hactive = { 480, 480, 480 },
3399 .hback_porch = { 8, 43, 43 },
3400 .hfront_porch = { 2, 8, 8 },
3401 .hsync_len = { 1, 1, 1 },
3402 .vactive = { 272, 272, 272 },
3403 .vback_porch = { 2, 12, 12 },
3404 .vfront_porch = { 1, 4, 4 },
3405 .vsync_len = { 1, 10, 10 },
3406 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW |
3407 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE,
3410 static const struct panel_desc rocktech_rk043fn48h = {
3411 .timings = &rocktech_rk043fn48h_timing,
3418 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3419 .connector_type = DRM_MODE_CONNECTOR_DPI,
3422 static const struct drm_display_mode raspberrypi_7inch_mode = {
3425 .hsync_start = 800 + 59,
3426 .hsync_end = 800 + 59 + 2,
3427 .htotal = 800 + 59 + 2 + 46,
3429 .vsync_start = 480 + 7,
3430 .vsync_end = 480 + 7 + 2,
3431 .vtotal = 480 + 7 + 2 + 21,
3432 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3435 static const struct panel_desc raspberrypi_7inch = {
3436 .modes = &raspberrypi_7inch_mode,
3443 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3444 .connector_type = DRM_MODE_CONNECTOR_DSI,
3447 static const struct display_timing rocktech_rk070er9427_timing = {
3448 .pixelclock = { 26400000, 33300000, 46800000 },
3449 .hactive = { 800, 800, 800 },
3450 .hfront_porch = { 16, 210, 354 },
3451 .hback_porch = { 46, 46, 46 },
3452 .hsync_len = { 1, 1, 1 },
3453 .vactive = { 480, 480, 480 },
3454 .vfront_porch = { 7, 22, 147 },
3455 .vback_porch = { 23, 23, 23 },
3456 .vsync_len = { 1, 1, 1 },
3457 .flags = DISPLAY_FLAGS_DE_HIGH,
3460 static const struct panel_desc rocktech_rk070er9427 = {
3461 .timings = &rocktech_rk070er9427_timing,
3474 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3477 static const struct drm_display_mode rocktech_rk101ii01d_ct_mode = {
3480 .hsync_start = 1280 + 48,
3481 .hsync_end = 1280 + 48 + 32,
3482 .htotal = 1280 + 48 + 32 + 80,
3484 .vsync_start = 800 + 2,
3485 .vsync_end = 800 + 2 + 5,
3486 .vtotal = 800 + 2 + 5 + 16,
3489 static const struct panel_desc rocktech_rk101ii01d_ct = {
3490 .modes = &rocktech_rk101ii01d_ct_mode,
3501 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
3502 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3503 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3506 static const struct display_timing samsung_ltl101al01_timing = {
3507 .pixelclock = { 66663000, 66663000, 66663000 },
3508 .hactive = { 1280, 1280, 1280 },
3509 .hfront_porch = { 18, 18, 18 },
3510 .hback_porch = { 36, 36, 36 },
3511 .hsync_len = { 16, 16, 16 },
3512 .vactive = { 800, 800, 800 },
3513 .vfront_porch = { 4, 4, 4 },
3514 .vback_porch = { 16, 16, 16 },
3515 .vsync_len = { 3, 3, 3 },
3516 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
3519 static const struct panel_desc samsung_ltl101al01 = {
3520 .timings = &samsung_ltl101al01_timing,
3533 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3534 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3537 static const struct drm_display_mode samsung_ltn101nt05_mode = {
3540 .hsync_start = 1024 + 24,
3541 .hsync_end = 1024 + 24 + 136,
3542 .htotal = 1024 + 24 + 136 + 160,
3544 .vsync_start = 600 + 3,
3545 .vsync_end = 600 + 3 + 6,
3546 .vtotal = 600 + 3 + 6 + 61,
3549 static const struct panel_desc samsung_ltn101nt05 = {
3550 .modes = &samsung_ltn101nt05_mode,
3557 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
3558 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
3559 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3562 static const struct display_timing satoz_sat050at40h12r2_timing = {
3563 .pixelclock = {33300000, 33300000, 50000000},
3564 .hactive = {800, 800, 800},
3565 .hfront_porch = {16, 210, 354},
3566 .hback_porch = {46, 46, 46},
3567 .hsync_len = {1, 1, 40},
3568 .vactive = {480, 480, 480},
3569 .vfront_porch = {7, 22, 147},
3570 .vback_porch = {23, 23, 23},
3571 .vsync_len = {1, 1, 20},
3574 static const struct panel_desc satoz_sat050at40h12r2 = {
3575 .timings = &satoz_sat050at40h12r2_timing,
3582 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3583 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3586 static const struct drm_display_mode sharp_lq070y3dg3b_mode = {
3589 .hsync_start = 800 + 64,
3590 .hsync_end = 800 + 64 + 128,
3591 .htotal = 800 + 64 + 128 + 64,
3593 .vsync_start = 480 + 8,
3594 .vsync_end = 480 + 8 + 2,
3595 .vtotal = 480 + 8 + 2 + 35,
3596 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE,
3599 static const struct panel_desc sharp_lq070y3dg3b = {
3600 .modes = &sharp_lq070y3dg3b_mode,
3604 .width = 152, /* 152.4mm */
3605 .height = 91, /* 91.4mm */
3607 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3608 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
3609 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
3612 static const struct drm_display_mode sharp_lq035q7db03_mode = {
3615 .hsync_start = 240 + 16,
3616 .hsync_end = 240 + 16 + 7,
3617 .htotal = 240 + 16 + 7 + 5,
3619 .vsync_start = 320 + 9,
3620 .vsync_end = 320 + 9 + 1,
3621 .vtotal = 320 + 9 + 1 + 7,
3624 static const struct panel_desc sharp_lq035q7db03 = {
3625 .modes = &sharp_lq035q7db03_mode,
3632 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3635 static const struct display_timing sharp_lq101k1ly04_timing = {
3636 .pixelclock = { 60000000, 65000000, 80000000 },
3637 .hactive = { 1280, 1280, 1280 },
3638 .hfront_porch = { 20, 20, 20 },
3639 .hback_porch = { 20, 20, 20 },
3640 .hsync_len = { 10, 10, 10 },
3641 .vactive = { 800, 800, 800 },
3642 .vfront_porch = { 4, 4, 4 },
3643 .vback_porch = { 4, 4, 4 },
3644 .vsync_len = { 4, 4, 4 },
3645 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE,
3648 static const struct panel_desc sharp_lq101k1ly04 = {
3649 .timings = &sharp_lq101k1ly04_timing,
3656 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
3657 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3660 static const struct drm_display_mode sharp_ls020b1dd01d_modes[] = {
3664 .hsync_start = 240 + 58,
3665 .hsync_end = 240 + 58 + 1,
3666 .htotal = 240 + 58 + 1 + 1,
3668 .vsync_start = 160 + 24,
3669 .vsync_end = 160 + 24 + 10,
3670 .vtotal = 160 + 24 + 10 + 6,
3671 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC,
3676 .hsync_start = 240 + 8,
3677 .hsync_end = 240 + 8 + 1,
3678 .htotal = 240 + 8 + 1 + 1,
3680 .vsync_start = 160 + 24,
3681 .vsync_end = 160 + 24 + 10,
3682 .vtotal = 160 + 24 + 10 + 6,
3683 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC,
3687 static const struct panel_desc sharp_ls020b1dd01d = {
3688 .modes = sharp_ls020b1dd01d_modes,
3689 .num_modes = ARRAY_SIZE(sharp_ls020b1dd01d_modes),
3695 .bus_format = MEDIA_BUS_FMT_RGB565_1X16,
3696 .bus_flags = DRM_BUS_FLAG_DE_HIGH
3697 | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE
3698 | DRM_BUS_FLAG_SHARP_SIGNALS,
3701 static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = {
3704 .hsync_start = 800 + 1,
3705 .hsync_end = 800 + 1 + 64,
3706 .htotal = 800 + 1 + 64 + 64,
3708 .vsync_start = 480 + 1,
3709 .vsync_end = 480 + 1 + 23,
3710 .vtotal = 480 + 1 + 23 + 22,
3713 static const struct panel_desc shelly_sca07010_bfn_lnn = {
3714 .modes = &shelly_sca07010_bfn_lnn_mode,
3720 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3723 static const struct drm_display_mode starry_kr070pe2t_mode = {
3726 .hsync_start = 800 + 209,
3727 .hsync_end = 800 + 209 + 1,
3728 .htotal = 800 + 209 + 1 + 45,
3730 .vsync_start = 480 + 22,
3731 .vsync_end = 480 + 22 + 1,
3732 .vtotal = 480 + 22 + 1 + 22,
3735 static const struct panel_desc starry_kr070pe2t = {
3736 .modes = &starry_kr070pe2t_mode,
3743 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3744 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
3745 .connector_type = DRM_MODE_CONNECTOR_DPI,
3748 static const struct display_timing startek_kd070wvfpa_mode = {
3749 .pixelclock = { 25200000, 27200000, 30500000 },
3750 .hactive = { 800, 800, 800 },
3751 .hfront_porch = { 19, 44, 115 },
3752 .hback_porch = { 5, 16, 101 },
3753 .hsync_len = { 1, 2, 100 },
3754 .vactive = { 480, 480, 480 },
3755 .vfront_porch = { 5, 43, 67 },
3756 .vback_porch = { 5, 5, 67 },
3757 .vsync_len = { 1, 2, 66 },
3758 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
3759 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
3760 DISPLAY_FLAGS_SYNC_POSEDGE,
3763 static const struct panel_desc startek_kd070wvfpa = {
3764 .timings = &startek_kd070wvfpa_mode,
3776 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3777 .connector_type = DRM_MODE_CONNECTOR_DPI,
3778 .bus_flags = DRM_BUS_FLAG_DE_HIGH |
3779 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
3780 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
3783 static const struct display_timing tsd_tst043015cmhx_timing = {
3784 .pixelclock = { 5000000, 9000000, 12000000 },
3785 .hactive = { 480, 480, 480 },
3786 .hfront_porch = { 4, 5, 65 },
3787 .hback_porch = { 36, 40, 255 },
3788 .hsync_len = { 1, 1, 1 },
3789 .vactive = { 272, 272, 272 },
3790 .vfront_porch = { 2, 8, 97 },
3791 .vback_porch = { 3, 8, 31 },
3792 .vsync_len = { 1, 1, 1 },
3794 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
3795 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE,
3798 static const struct panel_desc tsd_tst043015cmhx = {
3799 .timings = &tsd_tst043015cmhx_timing,
3806 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3807 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
3810 static const struct drm_display_mode tfc_s9700rtwv43tr_01b_mode = {
3813 .hsync_start = 800 + 39,
3814 .hsync_end = 800 + 39 + 47,
3815 .htotal = 800 + 39 + 47 + 39,
3817 .vsync_start = 480 + 13,
3818 .vsync_end = 480 + 13 + 2,
3819 .vtotal = 480 + 13 + 2 + 29,
3822 static const struct panel_desc tfc_s9700rtwv43tr_01b = {
3823 .modes = &tfc_s9700rtwv43tr_01b_mode,
3830 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3831 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
3834 static const struct display_timing tianma_tm070jdhg30_timing = {
3835 .pixelclock = { 62600000, 68200000, 78100000 },
3836 .hactive = { 1280, 1280, 1280 },
3837 .hfront_porch = { 15, 64, 159 },
3838 .hback_porch = { 5, 5, 5 },
3839 .hsync_len = { 1, 1, 256 },
3840 .vactive = { 800, 800, 800 },
3841 .vfront_porch = { 3, 40, 99 },
3842 .vback_porch = { 2, 2, 2 },
3843 .vsync_len = { 1, 1, 128 },
3844 .flags = DISPLAY_FLAGS_DE_HIGH,
3847 static const struct panel_desc tianma_tm070jdhg30 = {
3848 .timings = &tianma_tm070jdhg30_timing,
3855 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3856 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3857 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
3860 static const struct panel_desc tianma_tm070jvhg33 = {
3861 .timings = &tianma_tm070jdhg30_timing,
3868 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3869 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3870 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
3873 static const struct display_timing tianma_tm070rvhg71_timing = {
3874 .pixelclock = { 27700000, 29200000, 39600000 },
3875 .hactive = { 800, 800, 800 },
3876 .hfront_porch = { 12, 40, 212 },
3877 .hback_porch = { 88, 88, 88 },
3878 .hsync_len = { 1, 1, 40 },
3879 .vactive = { 480, 480, 480 },
3880 .vfront_porch = { 1, 13, 88 },
3881 .vback_porch = { 32, 32, 32 },
3882 .vsync_len = { 1, 1, 3 },
3883 .flags = DISPLAY_FLAGS_DE_HIGH,
3886 static const struct panel_desc tianma_tm070rvhg71 = {
3887 .timings = &tianma_tm070rvhg71_timing,
3894 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3895 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3898 static const struct drm_display_mode ti_nspire_cx_lcd_mode[] = {
3902 .hsync_start = 320 + 50,
3903 .hsync_end = 320 + 50 + 6,
3904 .htotal = 320 + 50 + 6 + 38,
3906 .vsync_start = 240 + 3,
3907 .vsync_end = 240 + 3 + 1,
3908 .vtotal = 240 + 3 + 1 + 17,
3909 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3913 static const struct panel_desc ti_nspire_cx_lcd_panel = {
3914 .modes = ti_nspire_cx_lcd_mode,
3921 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3922 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
3925 static const struct drm_display_mode ti_nspire_classic_lcd_mode[] = {
3929 .hsync_start = 320 + 6,
3930 .hsync_end = 320 + 6 + 6,
3931 .htotal = 320 + 6 + 6 + 6,
3933 .vsync_start = 240 + 0,
3934 .vsync_end = 240 + 0 + 1,
3935 .vtotal = 240 + 0 + 1 + 0,
3936 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
3940 static const struct panel_desc ti_nspire_classic_lcd_panel = {
3941 .modes = ti_nspire_classic_lcd_mode,
3943 /* The grayscale panel has 8 bit for the color .. Y (black) */
3949 /* This is the grayscale bus format */
3950 .bus_format = MEDIA_BUS_FMT_Y8_1X8,
3951 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
3954 static const struct drm_display_mode toshiba_lt089ac29000_mode = {
3957 .hsync_start = 1280 + 192,
3958 .hsync_end = 1280 + 192 + 128,
3959 .htotal = 1280 + 192 + 128 + 64,
3961 .vsync_start = 768 + 20,
3962 .vsync_end = 768 + 20 + 7,
3963 .vtotal = 768 + 20 + 7 + 3,
3966 static const struct panel_desc toshiba_lt089ac29000 = {
3967 .modes = &toshiba_lt089ac29000_mode,
3973 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
3974 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
3975 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3978 static const struct drm_display_mode tpk_f07a_0102_mode = {
3981 .hsync_start = 800 + 40,
3982 .hsync_end = 800 + 40 + 128,
3983 .htotal = 800 + 40 + 128 + 88,
3985 .vsync_start = 480 + 10,
3986 .vsync_end = 480 + 10 + 2,
3987 .vtotal = 480 + 10 + 2 + 33,
3990 static const struct panel_desc tpk_f07a_0102 = {
3991 .modes = &tpk_f07a_0102_mode,
3997 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
4000 static const struct drm_display_mode tpk_f10a_0102_mode = {
4003 .hsync_start = 1024 + 176,
4004 .hsync_end = 1024 + 176 + 5,
4005 .htotal = 1024 + 176 + 5 + 88,
4007 .vsync_start = 600 + 20,
4008 .vsync_end = 600 + 20 + 5,
4009 .vtotal = 600 + 20 + 5 + 25,
4012 static const struct panel_desc tpk_f10a_0102 = {
4013 .modes = &tpk_f10a_0102_mode,
4021 static const struct display_timing urt_umsh_8596md_timing = {
4022 .pixelclock = { 33260000, 33260000, 33260000 },
4023 .hactive = { 800, 800, 800 },
4024 .hfront_porch = { 41, 41, 41 },
4025 .hback_porch = { 216 - 128, 216 - 128, 216 - 128 },
4026 .hsync_len = { 71, 128, 128 },
4027 .vactive = { 480, 480, 480 },
4028 .vfront_porch = { 10, 10, 10 },
4029 .vback_porch = { 35 - 2, 35 - 2, 35 - 2 },
4030 .vsync_len = { 2, 2, 2 },
4031 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE |
4032 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
4035 static const struct panel_desc urt_umsh_8596md_lvds = {
4036 .timings = &urt_umsh_8596md_timing,
4043 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
4044 .connector_type = DRM_MODE_CONNECTOR_LVDS,
4047 static const struct panel_desc urt_umsh_8596md_parallel = {
4048 .timings = &urt_umsh_8596md_timing,
4055 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
4058 static const struct drm_display_mode vivax_tpc9150_panel_mode = {
4061 .hsync_start = 1024 + 160,
4062 .hsync_end = 1024 + 160 + 100,
4063 .htotal = 1024 + 160 + 100 + 60,
4065 .vsync_start = 600 + 12,
4066 .vsync_end = 600 + 12 + 10,
4067 .vtotal = 600 + 12 + 10 + 13,
4070 static const struct panel_desc vivax_tpc9150_panel = {
4071 .modes = &vivax_tpc9150_panel_mode,
4078 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
4079 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
4080 .connector_type = DRM_MODE_CONNECTOR_LVDS,
4083 static const struct drm_display_mode vl050_8048nt_c01_mode = {
4086 .hsync_start = 800 + 210,
4087 .hsync_end = 800 + 210 + 20,
4088 .htotal = 800 + 210 + 20 + 46,
4090 .vsync_start = 480 + 22,
4091 .vsync_end = 480 + 22 + 10,
4092 .vtotal = 480 + 22 + 10 + 23,
4093 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
4096 static const struct panel_desc vl050_8048nt_c01 = {
4097 .modes = &vl050_8048nt_c01_mode,
4104 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
4105 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
4108 static const struct drm_display_mode winstar_wf35ltiacd_mode = {
4111 .hsync_start = 320 + 20,
4112 .hsync_end = 320 + 20 + 30,
4113 .htotal = 320 + 20 + 30 + 38,
4115 .vsync_start = 240 + 4,
4116 .vsync_end = 240 + 4 + 3,
4117 .vtotal = 240 + 4 + 3 + 15,
4118 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
4121 static const struct panel_desc winstar_wf35ltiacd = {
4122 .modes = &winstar_wf35ltiacd_mode,
4129 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
4132 static const struct drm_display_mode yes_optoelectronics_ytc700tlag_05_201c_mode = {
4135 .hsync_start = 1024 + 100,
4136 .hsync_end = 1024 + 100 + 100,
4137 .htotal = 1024 + 100 + 100 + 120,
4139 .vsync_start = 600 + 10,
4140 .vsync_end = 600 + 10 + 10,
4141 .vtotal = 600 + 10 + 10 + 15,
4142 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
4145 static const struct panel_desc yes_optoelectronics_ytc700tlag_05_201c = {
4146 .modes = &yes_optoelectronics_ytc700tlag_05_201c_mode,
4153 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
4154 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
4155 .connector_type = DRM_MODE_CONNECTOR_LVDS,
4158 static const struct drm_display_mode arm_rtsm_mode[] = {
4162 .hsync_start = 1024 + 24,
4163 .hsync_end = 1024 + 24 + 136,
4164 .htotal = 1024 + 24 + 136 + 160,
4166 .vsync_start = 768 + 3,
4167 .vsync_end = 768 + 3 + 6,
4168 .vtotal = 768 + 3 + 6 + 29,
4169 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
4173 static const struct panel_desc arm_rtsm = {
4174 .modes = arm_rtsm_mode,
4181 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
4184 static const struct of_device_id platform_of_match[] = {
4186 .compatible = "ampire,am-1280800n3tzqw-t00h",
4187 .data = &ire_am_1280800n3tzqw_t00h,
4189 .compatible = "ampire,am-480272h3tmqw-t01h",
4190 .data = &ire_am_480272h3tmqw_t01h,
4192 .compatible = "ampire,am-800480l1tmqw-t00h",
4193 .data = &ire_am_800480l1tmqw_t00h,
4195 .compatible = "ampire,am800480r3tmqwa1h",
4196 .data = &ire_am800480r3tmqwa1h,
4198 .compatible = "ampire,am800600p5tmqw-tb8h",
4199 .data = &ire_am800600p5tmqwtb8h,
4201 .compatible = "arm,rtsm-display",
4204 .compatible = "armadeus,st0700-adapt",
4205 .data = &armadeus_st0700_adapt,
4207 .compatible = "auo,b101aw03",
4208 .data = &auo_b101aw03,
4210 .compatible = "auo,b101xtn01",
4211 .data = &auo_b101xtn01,
4213 .compatible = "auo,b116xw03",
4214 .data = &auo_b116xw03,
4216 .compatible = "auo,g070vvn01",
4217 .data = &auo_g070vvn01,
4219 .compatible = "auo,g101evn010",
4220 .data = &auo_g101evn010,
4222 .compatible = "auo,g104sn02",
4223 .data = &auo_g104sn02,
4225 .compatible = "auo,g121ean01",
4226 .data = &auo_g121ean01,
4228 .compatible = "auo,g133han01",
4229 .data = &auo_g133han01,
4231 .compatible = "auo,g156xtn01",
4232 .data = &auo_g156xtn01,
4234 .compatible = "auo,g185han01",
4235 .data = &auo_g185han01,
4237 .compatible = "auo,g190ean01",
4238 .data = &auo_g190ean01,
4240 .compatible = "auo,p320hvn03",
4241 .data = &auo_p320hvn03,
4243 .compatible = "auo,t215hvn01",
4244 .data = &auo_t215hvn01,
4246 .compatible = "avic,tm070ddh03",
4247 .data = &avic_tm070ddh03,
4249 .compatible = "bananapi,s070wv20-ct16",
4250 .data = &bananapi_s070wv20_ct16,
4252 .compatible = "boe,ev121wxm-n10-1850",
4253 .data = &boe_ev121wxm_n10_1850,
4255 .compatible = "boe,hv070wsa-100",
4256 .data = &boe_hv070wsa
4258 .compatible = "cdtech,s043wq26h-ct7",
4259 .data = &cdtech_s043wq26h_ct7,
4261 .compatible = "cdtech,s070pws19hp-fc21",
4262 .data = &cdtech_s070pws19hp_fc21,
4264 .compatible = "cdtech,s070swv29hg-dc44",
4265 .data = &cdtech_s070swv29hg_dc44,
4267 .compatible = "cdtech,s070wv95-ct16",
4268 .data = &cdtech_s070wv95_ct16,
4270 .compatible = "chefree,ch101olhlwh-002",
4271 .data = &chefree_ch101olhlwh_002,
4273 .compatible = "chunghwa,claa070wp03xg",
4274 .data = &chunghwa_claa070wp03xg,
4276 .compatible = "chunghwa,claa101wa01a",
4277 .data = &chunghwa_claa101wa01a
4279 .compatible = "chunghwa,claa101wb01",
4280 .data = &chunghwa_claa101wb01
4282 .compatible = "dataimage,fg040346dsswbg04",
4283 .data = &dataimage_fg040346dsswbg04,
4285 .compatible = "dataimage,fg1001l0dsswmg01",
4286 .data = &dataimage_fg1001l0dsswmg01,
4288 .compatible = "dataimage,scf0700c48ggu18",
4289 .data = &dataimage_scf0700c48ggu18,
4291 .compatible = "dlc,dlc0700yzg-1",
4292 .data = &dlc_dlc0700yzg_1,
4294 .compatible = "dlc,dlc1010gig",
4295 .data = &dlc_dlc1010gig,
4297 .compatible = "edt,et035012dm6",
4298 .data = &edt_et035012dm6,
4300 .compatible = "edt,etm0350g0dh6",
4301 .data = &edt_etm0350g0dh6,
4303 .compatible = "edt,etm043080dh6gp",
4304 .data = &edt_etm043080dh6gp,
4306 .compatible = "edt,etm0430g0dh6",
4307 .data = &edt_etm0430g0dh6,
4309 .compatible = "edt,et057090dhu",
4310 .data = &edt_et057090dhu,
4312 .compatible = "edt,et070080dh6",
4313 .data = &edt_etm0700g0dh6,
4315 .compatible = "edt,etm0700g0dh6",
4316 .data = &edt_etm0700g0dh6,
4318 .compatible = "edt,etm0700g0bdh6",
4319 .data = &edt_etm0700g0bdh6,
4321 .compatible = "edt,etm0700g0edh6",
4322 .data = &edt_etm0700g0bdh6,
4324 .compatible = "edt,etml0700y5dha",
4325 .data = &edt_etml0700y5dha,
4327 .compatible = "edt,etmv570g2dhu",
4328 .data = &edt_etmv570g2dhu,
4330 .compatible = "eink,vb3300-kca",
4331 .data = &eink_vb3300_kca,
4333 .compatible = "evervision,vgg804821",
4334 .data = &evervision_vgg804821,
4336 .compatible = "foxlink,fl500wvr00-a0t",
4337 .data = &foxlink_fl500wvr00_a0t,
4339 .compatible = "frida,frd350h54004",
4340 .data = &frida_frd350h54004,
4342 .compatible = "friendlyarm,hd702e",
4343 .data = &friendlyarm_hd702e,
4345 .compatible = "geekworm,mzp280",
4346 .data = &geekworm_mzp280,
4348 .compatible = "giantplus,gpg482739qs5",
4349 .data = &giantplus_gpg482739qs5
4351 .compatible = "giantplus,gpm940b0",
4352 .data = &giantplus_gpm940b0,
4354 .compatible = "hannstar,hsd070pww1",
4355 .data = &hannstar_hsd070pww1,
4357 .compatible = "hannstar,hsd100pxn1",
4358 .data = &hannstar_hsd100pxn1,
4360 .compatible = "hannstar,hsd101pww2",
4361 .data = &hannstar_hsd101pww2,
4363 .compatible = "hit,tx23d38vm0caa",
4364 .data = &hitachi_tx23d38vm0caa
4366 .compatible = "innolux,at043tn24",
4367 .data = &innolux_at043tn24,
4369 .compatible = "innolux,at056tn53v1",
4370 .data = &innolux_at056tn53v1,
4372 .compatible = "innolux,at070tn92",
4373 .data = &innolux_at070tn92,
4375 .compatible = "innolux,g070ace-l01",
4376 .data = &innolux_g070ace_l01,
4378 .compatible = "innolux,g070y2-l01",
4379 .data = &innolux_g070y2_l01,
4381 .compatible = "innolux,g070y2-t02",
4382 .data = &innolux_g070y2_t02,
4384 .compatible = "innolux,g101ice-l01",
4385 .data = &innolux_g101ice_l01
4387 .compatible = "innolux,g121i1-l01",
4388 .data = &innolux_g121i1_l01
4390 .compatible = "innolux,g121x1-l03",
4391 .data = &innolux_g121x1_l03,
4393 .compatible = "innolux,g156hce-l01",
4394 .data = &innolux_g156hce_l01,
4396 .compatible = "innolux,n156bge-l21",
4397 .data = &innolux_n156bge_l21,
4399 .compatible = "innolux,zj070na-01p",
4400 .data = &innolux_zj070na_01p,
4402 .compatible = "koe,tx14d24vm1bpa",
4403 .data = &koe_tx14d24vm1bpa,
4405 .compatible = "koe,tx26d202vm0bwa",
4406 .data = &koe_tx26d202vm0bwa,
4408 .compatible = "koe,tx31d200vm0baa",
4409 .data = &koe_tx31d200vm0baa,
4411 .compatible = "kyo,tcg121xglp",
4412 .data = &kyo_tcg121xglp,
4414 .compatible = "lemaker,bl035-rgb-002",
4415 .data = &lemaker_bl035_rgb_002,
4417 .compatible = "lg,lb070wv8",
4418 .data = &lg_lb070wv8,
4420 .compatible = "logicpd,type28",
4421 .data = &logicpd_type_28,
4423 .compatible = "logictechno,lt161010-2nhc",
4424 .data = &logictechno_lt161010_2nh,
4426 .compatible = "logictechno,lt161010-2nhr",
4427 .data = &logictechno_lt161010_2nh,
4429 .compatible = "logictechno,lt170410-2whc",
4430 .data = &logictechno_lt170410_2whc,
4432 .compatible = "logictechno,lttd800480070-l2rt",
4433 .data = &logictechno_lttd800480070_l2rt,
4435 .compatible = "logictechno,lttd800480070-l6wh-rt",
4436 .data = &logictechno_lttd800480070_l6wh_rt,
4438 .compatible = "mitsubishi,aa070mc01-ca1",
4439 .data = &mitsubishi_aa070mc01,
4441 .compatible = "multi-inno,mi0700s4t-6",
4442 .data = &multi_inno_mi0700s4t_6,
4444 .compatible = "multi-inno,mi0800ft-9",
4445 .data = &multi_inno_mi0800ft_9,
4447 .compatible = "multi-inno,mi1010ait-1cp",
4448 .data = &multi_inno_mi1010ait_1cp,
4450 .compatible = "nec,nl12880bc20-05",
4451 .data = &nec_nl12880bc20_05,
4453 .compatible = "nec,nl4827hc19-05b",
4454 .data = &nec_nl4827hc19_05b,
4456 .compatible = "netron-dy,e231732",
4457 .data = &netron_dy_e231732,
4459 .compatible = "newhaven,nhd-4.3-480272ef-atxl",
4460 .data = &newhaven_nhd_43_480272ef_atxl,
4462 .compatible = "nlt,nl192108ac18-02d",
4463 .data = &nlt_nl192108ac18_02d,
4465 .compatible = "nvd,9128",
4468 .compatible = "okaya,rs800480t-7x0gp",
4469 .data = &okaya_rs800480t_7x0gp,
4471 .compatible = "olimex,lcd-olinuxino-43-ts",
4472 .data = &olimex_lcd_olinuxino_43ts,
4474 .compatible = "ontat,yx700wv03",
4475 .data = &ontat_yx700wv03,
4477 .compatible = "ortustech,com37h3m05dtc",
4478 .data = &ortustech_com37h3m,
4480 .compatible = "ortustech,com37h3m99dtc",
4481 .data = &ortustech_com37h3m,
4483 .compatible = "ortustech,com43h4m85ulc",
4484 .data = &ortustech_com43h4m85ulc,
4486 .compatible = "osddisplays,osd070t1718-19ts",
4487 .data = &osddisplays_osd070t1718_19ts,
4489 .compatible = "pda,91-00156-a0",
4490 .data = &pda_91_00156_a0,
4492 .compatible = "powertip,ph800480t013-idf02",
4493 .data = &powertip_ph800480t013_idf02,
4495 .compatible = "qiaodian,qd43003c0-40",
4496 .data = &qd43003c0_40,
4498 .compatible = "qishenglong,gopher2b-lcd",
4499 .data = &qishenglong_gopher2b_lcd,
4501 .compatible = "rocktech,rk043fn48h",
4502 .data = &rocktech_rk043fn48h,
4504 .compatible = "raspberrypi,7inch-dsi",
4505 .data = &raspberrypi_7inch,
4507 .compatible = "rocktech,rk070er9427",
4508 .data = &rocktech_rk070er9427,
4510 .compatible = "rocktech,rk101ii01d-ct",
4511 .data = &rocktech_rk101ii01d_ct,
4513 .compatible = "samsung,ltl101al01",
4514 .data = &samsung_ltl101al01,
4516 .compatible = "samsung,ltn101nt05",
4517 .data = &samsung_ltn101nt05,
4519 .compatible = "satoz,sat050at40h12r2",
4520 .data = &satoz_sat050at40h12r2,
4522 .compatible = "sharp,lq035q7db03",
4523 .data = &sharp_lq035q7db03,
4525 .compatible = "sharp,lq070y3dg3b",
4526 .data = &sharp_lq070y3dg3b,
4528 .compatible = "sharp,lq101k1ly04",
4529 .data = &sharp_lq101k1ly04,
4531 .compatible = "sharp,ls020b1dd01d",
4532 .data = &sharp_ls020b1dd01d,
4534 .compatible = "shelly,sca07010-bfn-lnn",
4535 .data = &shelly_sca07010_bfn_lnn,
4537 .compatible = "starry,kr070pe2t",
4538 .data = &starry_kr070pe2t,
4540 .compatible = "startek,kd070wvfpa",
4541 .data = &startek_kd070wvfpa,
4543 .compatible = "team-source-display,tst043015cmhx",
4544 .data = &tsd_tst043015cmhx,
4546 .compatible = "tfc,s9700rtwv43tr-01b",
4547 .data = &tfc_s9700rtwv43tr_01b,
4549 .compatible = "tianma,tm070jdhg30",
4550 .data = &tianma_tm070jdhg30,
4552 .compatible = "tianma,tm070jvhg33",
4553 .data = &tianma_tm070jvhg33,
4555 .compatible = "tianma,tm070rvhg71",
4556 .data = &tianma_tm070rvhg71,
4558 .compatible = "ti,nspire-cx-lcd-panel",
4559 .data = &ti_nspire_cx_lcd_panel,
4561 .compatible = "ti,nspire-classic-lcd-panel",
4562 .data = &ti_nspire_classic_lcd_panel,
4564 .compatible = "toshiba,lt089ac29000",
4565 .data = &toshiba_lt089ac29000,
4567 .compatible = "tpk,f07a-0102",
4568 .data = &tpk_f07a_0102,
4570 .compatible = "tpk,f10a-0102",
4571 .data = &tpk_f10a_0102,
4573 .compatible = "urt,umsh-8596md-t",
4574 .data = &urt_umsh_8596md_parallel,
4576 .compatible = "urt,umsh-8596md-1t",
4577 .data = &urt_umsh_8596md_parallel,
4579 .compatible = "urt,umsh-8596md-7t",
4580 .data = &urt_umsh_8596md_parallel,
4582 .compatible = "urt,umsh-8596md-11t",
4583 .data = &urt_umsh_8596md_lvds,
4585 .compatible = "urt,umsh-8596md-19t",
4586 .data = &urt_umsh_8596md_lvds,
4588 .compatible = "urt,umsh-8596md-20t",
4589 .data = &urt_umsh_8596md_parallel,
4591 .compatible = "vivax,tpc9150-panel",
4592 .data = &vivax_tpc9150_panel,
4594 .compatible = "vxt,vl050-8048nt-c01",
4595 .data = &vl050_8048nt_c01,
4597 .compatible = "winstar,wf35ltiacd",
4598 .data = &winstar_wf35ltiacd,
4600 .compatible = "yes-optoelectronics,ytc700tlag-05-201c",
4601 .data = &yes_optoelectronics_ytc700tlag_05_201c,
4603 /* Must be the last entry */
4604 .compatible = "panel-dpi",
4610 MODULE_DEVICE_TABLE(of, platform_of_match);
4612 static int panel_simple_platform_probe(struct platform_device *pdev)
4614 const struct panel_desc *desc;
4616 desc = of_device_get_match_data(&pdev->dev);
4620 return panel_simple_probe(&pdev->dev, desc);
4623 static void panel_simple_platform_remove(struct platform_device *pdev)
4625 panel_simple_remove(&pdev->dev);
4628 static void panel_simple_platform_shutdown(struct platform_device *pdev)
4630 panel_simple_shutdown(&pdev->dev);
4633 static const struct dev_pm_ops panel_simple_pm_ops = {
4634 SET_RUNTIME_PM_OPS(panel_simple_suspend, panel_simple_resume, NULL)
4635 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
4636 pm_runtime_force_resume)
4639 static struct platform_driver panel_simple_platform_driver = {
4641 .name = "panel-simple",
4642 .of_match_table = platform_of_match,
4643 .pm = &panel_simple_pm_ops,
4645 .probe = panel_simple_platform_probe,
4646 .remove_new = panel_simple_platform_remove,
4647 .shutdown = panel_simple_platform_shutdown,
4650 struct panel_desc_dsi {
4651 struct panel_desc desc;
4653 unsigned long flags;
4654 enum mipi_dsi_pixel_format format;
4658 static const struct drm_display_mode auo_b080uan01_mode = {
4661 .hsync_start = 1200 + 62,
4662 .hsync_end = 1200 + 62 + 4,
4663 .htotal = 1200 + 62 + 4 + 62,
4665 .vsync_start = 1920 + 9,
4666 .vsync_end = 1920 + 9 + 2,
4667 .vtotal = 1920 + 9 + 2 + 8,
4670 static const struct panel_desc_dsi auo_b080uan01 = {
4672 .modes = &auo_b080uan01_mode,
4679 .connector_type = DRM_MODE_CONNECTOR_DSI,
4681 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
4682 .format = MIPI_DSI_FMT_RGB888,
4686 static const struct drm_display_mode boe_tv080wum_nl0_mode = {
4689 .hsync_start = 1200 + 120,
4690 .hsync_end = 1200 + 120 + 20,
4691 .htotal = 1200 + 120 + 20 + 21,
4693 .vsync_start = 1920 + 21,
4694 .vsync_end = 1920 + 21 + 3,
4695 .vtotal = 1920 + 21 + 3 + 18,
4696 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
4699 static const struct panel_desc_dsi boe_tv080wum_nl0 = {
4701 .modes = &boe_tv080wum_nl0_mode,
4707 .connector_type = DRM_MODE_CONNECTOR_DSI,
4709 .flags = MIPI_DSI_MODE_VIDEO |
4710 MIPI_DSI_MODE_VIDEO_BURST |
4711 MIPI_DSI_MODE_VIDEO_SYNC_PULSE,
4712 .format = MIPI_DSI_FMT_RGB888,
4716 static const struct drm_display_mode lg_ld070wx3_sl01_mode = {
4719 .hsync_start = 800 + 32,
4720 .hsync_end = 800 + 32 + 1,
4721 .htotal = 800 + 32 + 1 + 57,
4723 .vsync_start = 1280 + 28,
4724 .vsync_end = 1280 + 28 + 1,
4725 .vtotal = 1280 + 28 + 1 + 14,
4728 static const struct panel_desc_dsi lg_ld070wx3_sl01 = {
4730 .modes = &lg_ld070wx3_sl01_mode,
4737 .connector_type = DRM_MODE_CONNECTOR_DSI,
4739 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
4740 .format = MIPI_DSI_FMT_RGB888,
4744 static const struct drm_display_mode lg_lh500wx1_sd03_mode = {
4747 .hsync_start = 720 + 12,
4748 .hsync_end = 720 + 12 + 4,
4749 .htotal = 720 + 12 + 4 + 112,
4751 .vsync_start = 1280 + 8,
4752 .vsync_end = 1280 + 8 + 4,
4753 .vtotal = 1280 + 8 + 4 + 12,
4756 static const struct panel_desc_dsi lg_lh500wx1_sd03 = {
4758 .modes = &lg_lh500wx1_sd03_mode,
4765 .connector_type = DRM_MODE_CONNECTOR_DSI,
4767 .flags = MIPI_DSI_MODE_VIDEO,
4768 .format = MIPI_DSI_FMT_RGB888,
4772 static const struct drm_display_mode panasonic_vvx10f004b00_mode = {
4775 .hsync_start = 1920 + 154,
4776 .hsync_end = 1920 + 154 + 16,
4777 .htotal = 1920 + 154 + 16 + 32,
4779 .vsync_start = 1200 + 17,
4780 .vsync_end = 1200 + 17 + 2,
4781 .vtotal = 1200 + 17 + 2 + 16,
4784 static const struct panel_desc_dsi panasonic_vvx10f004b00 = {
4786 .modes = &panasonic_vvx10f004b00_mode,
4793 .connector_type = DRM_MODE_CONNECTOR_DSI,
4795 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
4796 MIPI_DSI_CLOCK_NON_CONTINUOUS,
4797 .format = MIPI_DSI_FMT_RGB888,
4801 static const struct drm_display_mode lg_acx467akm_7_mode = {
4804 .hsync_start = 1080 + 2,
4805 .hsync_end = 1080 + 2 + 2,
4806 .htotal = 1080 + 2 + 2 + 2,
4808 .vsync_start = 1920 + 2,
4809 .vsync_end = 1920 + 2 + 2,
4810 .vtotal = 1920 + 2 + 2 + 2,
4813 static const struct panel_desc_dsi lg_acx467akm_7 = {
4815 .modes = &lg_acx467akm_7_mode,
4822 .connector_type = DRM_MODE_CONNECTOR_DSI,
4825 .format = MIPI_DSI_FMT_RGB888,
4829 static const struct drm_display_mode osd101t2045_53ts_mode = {
4832 .hsync_start = 1920 + 112,
4833 .hsync_end = 1920 + 112 + 16,
4834 .htotal = 1920 + 112 + 16 + 32,
4836 .vsync_start = 1200 + 16,
4837 .vsync_end = 1200 + 16 + 2,
4838 .vtotal = 1200 + 16 + 2 + 16,
4839 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
4842 static const struct panel_desc_dsi osd101t2045_53ts = {
4844 .modes = &osd101t2045_53ts_mode,
4851 .connector_type = DRM_MODE_CONNECTOR_DSI,
4853 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
4854 MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
4855 MIPI_DSI_MODE_NO_EOT_PACKET,
4856 .format = MIPI_DSI_FMT_RGB888,
4860 static const struct of_device_id dsi_of_match[] = {
4862 .compatible = "auo,b080uan01",
4863 .data = &auo_b080uan01
4865 .compatible = "boe,tv080wum-nl0",
4866 .data = &boe_tv080wum_nl0
4868 .compatible = "lg,ld070wx3-sl01",
4869 .data = &lg_ld070wx3_sl01
4871 .compatible = "lg,lh500wx1-sd03",
4872 .data = &lg_lh500wx1_sd03
4874 .compatible = "panasonic,vvx10f004b00",
4875 .data = &panasonic_vvx10f004b00
4877 .compatible = "lg,acx467akm-7",
4878 .data = &lg_acx467akm_7
4880 .compatible = "osddisplays,osd101t2045-53ts",
4881 .data = &osd101t2045_53ts
4886 MODULE_DEVICE_TABLE(of, dsi_of_match);
4888 static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi)
4890 const struct panel_desc_dsi *desc;
4893 desc = of_device_get_match_data(&dsi->dev);
4897 err = panel_simple_probe(&dsi->dev, &desc->desc);
4901 dsi->mode_flags = desc->flags;
4902 dsi->format = desc->format;
4903 dsi->lanes = desc->lanes;
4905 err = mipi_dsi_attach(dsi);
4907 struct panel_simple *panel = mipi_dsi_get_drvdata(dsi);
4909 drm_panel_remove(&panel->base);
4915 static void panel_simple_dsi_remove(struct mipi_dsi_device *dsi)
4919 err = mipi_dsi_detach(dsi);
4921 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err);
4923 panel_simple_remove(&dsi->dev);
4926 static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi)
4928 panel_simple_shutdown(&dsi->dev);
4931 static struct mipi_dsi_driver panel_simple_dsi_driver = {
4933 .name = "panel-simple-dsi",
4934 .of_match_table = dsi_of_match,
4935 .pm = &panel_simple_pm_ops,
4937 .probe = panel_simple_dsi_probe,
4938 .remove = panel_simple_dsi_remove,
4939 .shutdown = panel_simple_dsi_shutdown,
4942 static int __init panel_simple_init(void)
4946 err = platform_driver_register(&panel_simple_platform_driver);
4950 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) {
4951 err = mipi_dsi_driver_register(&panel_simple_dsi_driver);
4953 goto err_did_platform_register;
4958 err_did_platform_register:
4959 platform_driver_unregister(&panel_simple_platform_driver);
4963 module_init(panel_simple_init);
4965 static void __exit panel_simple_exit(void)
4967 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI))
4968 mipi_dsi_driver_unregister(&panel_simple_dsi_driver);
4970 platform_driver_unregister(&panel_simple_platform_driver);
4972 module_exit(panel_simple_exit);
4974 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
4975 MODULE_DESCRIPTION("DRM Driver for Simple Panels");
4976 MODULE_LICENSE("GPL and additional rights");