2 * Copyright (C) 2013, NVIDIA Corporation. All rights reserved.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sub license,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the
12 * next paragraph) shall be included in all copies or substantial portions
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 #include <linux/delay.h>
25 #include <linux/gpio/consumer.h>
26 #include <linux/iopoll.h>
27 #include <linux/module.h>
28 #include <linux/of_platform.h>
29 #include <linux/platform_device.h>
30 #include <linux/pm_runtime.h>
31 #include <linux/regulator/consumer.h>
33 #include <video/display_timing.h>
34 #include <video/of_display_timing.h>
35 #include <video/videomode.h>
37 #include <drm/drm_crtc.h>
38 #include <drm/drm_device.h>
39 #include <drm/drm_dp_aux_bus.h>
40 #include <drm/drm_dp_helper.h>
41 #include <drm/drm_mipi_dsi.h>
42 #include <drm/drm_panel.h>
45 * struct panel_desc - Describes a simple panel.
49 * @modes: Pointer to array of fixed modes appropriate for this panel.
51 * If only one mode then this can just be the address of the mode.
52 * NOTE: cannot be used with "timings" and also if this is specified
53 * then you cannot override the mode in the device tree.
55 const struct drm_display_mode *modes;
57 /** @num_modes: Number of elements in modes array. */
58 unsigned int num_modes;
61 * @timings: Pointer to array of display timings
63 * NOTE: cannot be used with "modes" and also these will be used to
64 * validate a device tree override if one is present.
66 const struct display_timing *timings;
68 /** @num_timings: Number of elements in timings array. */
69 unsigned int num_timings;
71 /** @bpc: Bits per color. */
74 /** @size: Structure containing the physical size of this panel. */
77 * @size.width: Width (in mm) of the active display area.
82 * @size.height: Height (in mm) of the active display area.
87 /** @delay: Structure containing various delay values for this panel. */
90 * @delay.prepare: Time for the panel to become ready.
92 * The time (in milliseconds) that it takes for the panel to
93 * become ready and start receiving video data
98 * @delay.hpd_absent_delay: Time to wait if HPD isn't hooked up.
100 * Add this to the prepare delay if we know Hot Plug Detect
103 unsigned int hpd_absent_delay;
106 * @delay.prepare_to_enable: Time between prepare and enable.
108 * The minimum time, in milliseconds, that needs to have passed
109 * between when prepare finished and enable may begin. If at
110 * enable time less time has passed since prepare finished,
111 * the driver waits for the remaining time.
113 * If a fixed enable delay is also specified, we'll start
114 * counting before delaying for the fixed delay.
116 * If a fixed prepare delay is also specified, we won't start
117 * counting until after the fixed delay. We can't overlap this
118 * fixed delay with the min time because the fixed delay
119 * doesn't happen at the end of the function if a HPD GPIO was
125 * // do fixed prepare delay
126 * // wait for HPD GPIO if applicable
127 * // start counting for prepare_to_enable
130 * // do fixed enable delay
131 * // enforce prepare_to_enable min time
133 unsigned int prepare_to_enable;
136 * @delay.enable: Time for the panel to display a valid frame.
138 * The time (in milliseconds) that it takes for the panel to
139 * display the first valid frame after starting to receive
145 * @delay.disable: Time for the panel to turn the display off.
147 * The time (in milliseconds) that it takes for the panel to
148 * turn the display off (no content is visible).
150 unsigned int disable;
153 * @delay.unprepare: Time to power down completely.
155 * The time (in milliseconds) that it takes for the panel
156 * to power itself down completely.
158 * This time is used to prevent a future "prepare" from
159 * starting until at least this many milliseconds has passed.
160 * If at prepare time less time has passed since unprepare
161 * finished, the driver waits for the remaining time.
163 unsigned int unprepare;
166 /** @bus_format: See MEDIA_BUS_FMT_... defines. */
169 /** @bus_flags: See DRM_BUS_FLAG_... defines. */
172 /** @connector_type: LVDS, eDP, DSI, DPI, etc. */
176 struct panel_simple {
177 struct drm_panel base;
183 ktime_t prepared_time;
184 ktime_t unprepared_time;
186 const struct panel_desc *desc;
188 struct regulator *supply;
189 struct i2c_adapter *ddc;
190 struct drm_dp_aux *aux;
192 struct gpio_desc *enable_gpio;
193 struct gpio_desc *hpd_gpio;
197 struct drm_display_mode override_mode;
200 static inline struct panel_simple *to_panel_simple(struct drm_panel *panel)
202 return container_of(panel, struct panel_simple, base);
205 static unsigned int panel_simple_get_timings_modes(struct panel_simple *panel,
206 struct drm_connector *connector)
208 struct drm_display_mode *mode;
209 unsigned int i, num = 0;
211 for (i = 0; i < panel->desc->num_timings; i++) {
212 const struct display_timing *dt = &panel->desc->timings[i];
215 videomode_from_timing(dt, &vm);
216 mode = drm_mode_create(connector->dev);
218 dev_err(panel->base.dev, "failed to add mode %ux%u\n",
219 dt->hactive.typ, dt->vactive.typ);
223 drm_display_mode_from_videomode(&vm, mode);
225 mode->type |= DRM_MODE_TYPE_DRIVER;
227 if (panel->desc->num_timings == 1)
228 mode->type |= DRM_MODE_TYPE_PREFERRED;
230 drm_mode_probed_add(connector, mode);
237 static unsigned int panel_simple_get_display_modes(struct panel_simple *panel,
238 struct drm_connector *connector)
240 struct drm_display_mode *mode;
241 unsigned int i, num = 0;
243 for (i = 0; i < panel->desc->num_modes; i++) {
244 const struct drm_display_mode *m = &panel->desc->modes[i];
246 mode = drm_mode_duplicate(connector->dev, m);
248 dev_err(panel->base.dev, "failed to add mode %ux%u@%u\n",
249 m->hdisplay, m->vdisplay,
250 drm_mode_vrefresh(m));
254 mode->type |= DRM_MODE_TYPE_DRIVER;
256 if (panel->desc->num_modes == 1)
257 mode->type |= DRM_MODE_TYPE_PREFERRED;
259 drm_mode_set_name(mode);
261 drm_mode_probed_add(connector, mode);
268 static int panel_simple_get_non_edid_modes(struct panel_simple *panel,
269 struct drm_connector *connector)
271 struct drm_display_mode *mode;
272 bool has_override = panel->override_mode.type;
273 unsigned int num = 0;
279 mode = drm_mode_duplicate(connector->dev,
280 &panel->override_mode);
282 drm_mode_probed_add(connector, mode);
285 dev_err(panel->base.dev, "failed to add override mode\n");
289 /* Only add timings if override was not there or failed to validate */
290 if (num == 0 && panel->desc->num_timings)
291 num = panel_simple_get_timings_modes(panel, connector);
294 * Only add fixed modes if timings/override added no mode.
296 * We should only ever have either the display timings specified
297 * or a fixed mode. Anything else is rather bogus.
299 WARN_ON(panel->desc->num_timings && panel->desc->num_modes);
301 num = panel_simple_get_display_modes(panel, connector);
303 connector->display_info.bpc = panel->desc->bpc;
304 connector->display_info.width_mm = panel->desc->size.width;
305 connector->display_info.height_mm = panel->desc->size.height;
306 if (panel->desc->bus_format)
307 drm_display_info_set_bus_formats(&connector->display_info,
308 &panel->desc->bus_format, 1);
309 connector->display_info.bus_flags = panel->desc->bus_flags;
314 static void panel_simple_wait(ktime_t start_ktime, unsigned int min_ms)
316 ktime_t now_ktime, min_ktime;
321 min_ktime = ktime_add(start_ktime, ms_to_ktime(min_ms));
322 now_ktime = ktime_get();
324 if (ktime_before(now_ktime, min_ktime))
325 msleep(ktime_to_ms(ktime_sub(min_ktime, now_ktime)) + 1);
328 static int panel_simple_disable(struct drm_panel *panel)
330 struct panel_simple *p = to_panel_simple(panel);
335 if (p->desc->delay.disable)
336 msleep(p->desc->delay.disable);
343 static int panel_simple_suspend(struct device *dev)
345 struct panel_simple *p = dev_get_drvdata(dev);
347 gpiod_set_value_cansleep(p->enable_gpio, 0);
348 regulator_disable(p->supply);
349 p->unprepared_time = ktime_get();
357 static int panel_simple_unprepare(struct drm_panel *panel)
359 struct panel_simple *p = to_panel_simple(panel);
362 /* Unpreparing when already unprepared is a no-op */
366 pm_runtime_mark_last_busy(panel->dev);
367 ret = pm_runtime_put_autosuspend(panel->dev);
375 static int panel_simple_get_hpd_gpio(struct device *dev, struct panel_simple *p)
379 p->hpd_gpio = devm_gpiod_get_optional(dev, "hpd", GPIOD_IN);
380 if (IS_ERR(p->hpd_gpio)) {
381 err = PTR_ERR(p->hpd_gpio);
383 if (err != -EPROBE_DEFER)
384 dev_err(dev, "failed to get 'hpd' GPIO: %d\n", err);
392 static int panel_simple_prepare_once(struct panel_simple *p)
394 struct device *dev = p->base.dev;
398 unsigned long hpd_wait_us;
400 panel_simple_wait(p->unprepared_time, p->desc->delay.unprepare);
402 err = regulator_enable(p->supply);
404 dev_err(dev, "failed to enable supply: %d\n", err);
408 gpiod_set_value_cansleep(p->enable_gpio, 1);
410 delay = p->desc->delay.prepare;
412 delay += p->desc->delay.hpd_absent_delay;
417 if (p->desc->delay.hpd_absent_delay)
418 hpd_wait_us = p->desc->delay.hpd_absent_delay * 1000UL;
420 hpd_wait_us = 2000000;
422 err = readx_poll_timeout(gpiod_get_value_cansleep, p->hpd_gpio,
423 hpd_asserted, hpd_asserted,
425 if (hpd_asserted < 0)
429 if (err != -ETIMEDOUT)
431 "error waiting for hpd GPIO: %d\n", err);
436 p->prepared_time = ktime_get();
441 gpiod_set_value_cansleep(p->enable_gpio, 0);
442 regulator_disable(p->supply);
443 p->unprepared_time = ktime_get();
449 * Some panels simply don't always come up and need to be power cycled to
450 * work properly. We'll allow for a handful of retries.
452 #define MAX_PANEL_PREPARE_TRIES 5
454 static int panel_simple_resume(struct device *dev)
456 struct panel_simple *p = dev_get_drvdata(dev);
460 for (try = 0; try < MAX_PANEL_PREPARE_TRIES; try++) {
461 ret = panel_simple_prepare_once(p);
462 if (ret != -ETIMEDOUT)
466 if (ret == -ETIMEDOUT)
467 dev_err(dev, "Prepare timeout after %d tries\n", try);
469 dev_warn(dev, "Prepare needed %d retries\n", try);
474 static int panel_simple_prepare(struct drm_panel *panel)
476 struct panel_simple *p = to_panel_simple(panel);
479 /* Preparing when already prepared is a no-op */
483 ret = pm_runtime_get_sync(panel->dev);
485 pm_runtime_put_autosuspend(panel->dev);
494 static int panel_simple_enable(struct drm_panel *panel)
496 struct panel_simple *p = to_panel_simple(panel);
501 if (p->desc->delay.enable)
502 msleep(p->desc->delay.enable);
504 panel_simple_wait(p->prepared_time, p->desc->delay.prepare_to_enable);
511 static int panel_simple_get_modes(struct drm_panel *panel,
512 struct drm_connector *connector)
514 struct panel_simple *p = to_panel_simple(panel);
517 /* probe EDID if a DDC bus is available */
519 pm_runtime_get_sync(panel->dev);
522 p->edid = drm_get_edid(connector, p->ddc);
525 num += drm_add_edid_modes(connector, p->edid);
527 pm_runtime_mark_last_busy(panel->dev);
528 pm_runtime_put_autosuspend(panel->dev);
531 /* add hard-coded panel modes */
532 num += panel_simple_get_non_edid_modes(p, connector);
537 static int panel_simple_get_timings(struct drm_panel *panel,
538 unsigned int num_timings,
539 struct display_timing *timings)
541 struct panel_simple *p = to_panel_simple(panel);
544 if (p->desc->num_timings < num_timings)
545 num_timings = p->desc->num_timings;
548 for (i = 0; i < num_timings; i++)
549 timings[i] = p->desc->timings[i];
551 return p->desc->num_timings;
554 static const struct drm_panel_funcs panel_simple_funcs = {
555 .disable = panel_simple_disable,
556 .unprepare = panel_simple_unprepare,
557 .prepare = panel_simple_prepare,
558 .enable = panel_simple_enable,
559 .get_modes = panel_simple_get_modes,
560 .get_timings = panel_simple_get_timings,
563 static struct panel_desc panel_dpi;
565 static int panel_dpi_probe(struct device *dev,
566 struct panel_simple *panel)
568 struct display_timing *timing;
569 const struct device_node *np;
570 struct panel_desc *desc;
571 unsigned int bus_flags;
576 desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL);
580 timing = devm_kzalloc(dev, sizeof(*timing), GFP_KERNEL);
584 ret = of_get_display_timing(np, "panel-timing", timing);
586 dev_err(dev, "%pOF: no panel-timing node found for \"panel-dpi\" binding\n",
591 desc->timings = timing;
592 desc->num_timings = 1;
594 of_property_read_u32(np, "width-mm", &desc->size.width);
595 of_property_read_u32(np, "height-mm", &desc->size.height);
596 of_property_read_u32(np, "bus-format", &desc->bus_format);
598 /* Extract bus_flags from display_timing */
600 vm.flags = timing->flags;
601 drm_bus_flags_from_videomode(&vm, &bus_flags);
602 desc->bus_flags = bus_flags;
604 /* We do not know the connector for the DT node, so guess it */
605 desc->connector_type = DRM_MODE_CONNECTOR_DPI;
606 /* Likewise for the bit depth. */
614 #define PANEL_SIMPLE_BOUNDS_CHECK(to_check, bounds, field) \
615 (to_check->field.typ >= bounds->field.min && \
616 to_check->field.typ <= bounds->field.max)
617 static void panel_simple_parse_panel_timing_node(struct device *dev,
618 struct panel_simple *panel,
619 const struct display_timing *ot)
621 const struct panel_desc *desc = panel->desc;
625 if (WARN_ON(desc->num_modes)) {
626 dev_err(dev, "Reject override mode: panel has a fixed mode\n");
629 if (WARN_ON(!desc->num_timings)) {
630 dev_err(dev, "Reject override mode: no timings specified\n");
634 for (i = 0; i < panel->desc->num_timings; i++) {
635 const struct display_timing *dt = &panel->desc->timings[i];
637 if (!PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hactive) ||
638 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hfront_porch) ||
639 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hback_porch) ||
640 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hsync_len) ||
641 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vactive) ||
642 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vfront_porch) ||
643 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vback_porch) ||
644 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vsync_len))
647 if (ot->flags != dt->flags)
650 videomode_from_timing(ot, &vm);
651 drm_display_mode_from_videomode(&vm, &panel->override_mode);
652 panel->override_mode.type |= DRM_MODE_TYPE_DRIVER |
653 DRM_MODE_TYPE_PREFERRED;
657 if (WARN_ON(!panel->override_mode.type))
658 dev_err(dev, "Reject override mode: No display_timing found\n");
661 static int panel_simple_probe(struct device *dev, const struct panel_desc *desc,
662 struct drm_dp_aux *aux)
664 struct panel_simple *panel;
665 struct display_timing dt;
666 struct device_node *ddc;
671 panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL);
675 panel->enabled = false;
676 panel->prepared_time = 0;
680 panel->no_hpd = of_property_read_bool(dev->of_node, "no-hpd");
681 if (!panel->no_hpd) {
682 err = panel_simple_get_hpd_gpio(dev, panel);
687 panel->supply = devm_regulator_get(dev, "power");
688 if (IS_ERR(panel->supply))
689 return PTR_ERR(panel->supply);
691 panel->enable_gpio = devm_gpiod_get_optional(dev, "enable",
693 if (IS_ERR(panel->enable_gpio)) {
694 err = PTR_ERR(panel->enable_gpio);
695 if (err != -EPROBE_DEFER)
696 dev_err(dev, "failed to request GPIO: %d\n", err);
700 ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0);
702 panel->ddc = of_find_i2c_adapter_by_node(ddc);
706 return -EPROBE_DEFER;
708 panel->ddc = &aux->ddc;
711 if (desc == &panel_dpi) {
712 /* Handle the generic panel-dpi binding */
713 err = panel_dpi_probe(dev, panel);
718 if (!of_get_display_timing(dev->of_node, "panel-timing", &dt))
719 panel_simple_parse_panel_timing_node(dev, panel, &dt);
722 connector_type = desc->connector_type;
723 /* Catch common mistakes for panels. */
724 switch (connector_type) {
726 dev_warn(dev, "Specify missing connector_type\n");
727 connector_type = DRM_MODE_CONNECTOR_DPI;
729 case DRM_MODE_CONNECTOR_LVDS:
730 WARN_ON(desc->bus_flags &
731 ~(DRM_BUS_FLAG_DE_LOW |
732 DRM_BUS_FLAG_DE_HIGH |
733 DRM_BUS_FLAG_DATA_MSB_TO_LSB |
734 DRM_BUS_FLAG_DATA_LSB_TO_MSB));
735 WARN_ON(desc->bus_format != MEDIA_BUS_FMT_RGB666_1X7X3_SPWG &&
736 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_SPWG &&
737 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA);
738 WARN_ON(desc->bus_format == MEDIA_BUS_FMT_RGB666_1X7X3_SPWG &&
740 WARN_ON((desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_SPWG ||
741 desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA) &&
744 case DRM_MODE_CONNECTOR_eDP:
745 if (desc->bpc != 6 && desc->bpc != 8 && desc->bpc != 10)
746 dev_warn(dev, "Expected bpc in {6,8,10} but got: %u\n", desc->bpc);
748 case DRM_MODE_CONNECTOR_DSI:
749 if (desc->bpc != 6 && desc->bpc != 8)
750 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc);
752 case DRM_MODE_CONNECTOR_DPI:
753 bus_flags = DRM_BUS_FLAG_DE_LOW |
754 DRM_BUS_FLAG_DE_HIGH |
755 DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE |
756 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
757 DRM_BUS_FLAG_DATA_MSB_TO_LSB |
758 DRM_BUS_FLAG_DATA_LSB_TO_MSB |
759 DRM_BUS_FLAG_SYNC_SAMPLE_POSEDGE |
760 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE;
761 if (desc->bus_flags & ~bus_flags)
762 dev_warn(dev, "Unexpected bus_flags(%d)\n", desc->bus_flags & ~bus_flags);
763 if (!(desc->bus_flags & bus_flags))
764 dev_warn(dev, "Specify missing bus_flags\n");
765 if (desc->bus_format == 0)
766 dev_warn(dev, "Specify missing bus_format\n");
767 if (desc->bpc != 6 && desc->bpc != 8)
768 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc);
771 dev_warn(dev, "Specify a valid connector_type: %d\n", desc->connector_type);
772 connector_type = DRM_MODE_CONNECTOR_DPI;
776 dev_set_drvdata(dev, panel);
779 * We use runtime PM for prepare / unprepare since those power the panel
780 * on and off and those can be very slow operations. This is important
781 * to optimize powering the panel on briefly to read the EDID before
782 * fully enabling the panel.
784 pm_runtime_enable(dev);
785 pm_runtime_set_autosuspend_delay(dev, 1000);
786 pm_runtime_use_autosuspend(dev);
788 drm_panel_init(&panel->base, dev, &panel_simple_funcs, connector_type);
790 err = drm_panel_of_backlight(&panel->base);
792 goto disable_pm_runtime;
794 if (!panel->base.backlight && panel->aux) {
795 pm_runtime_get_sync(dev);
796 err = drm_panel_dp_aux_backlight(&panel->base, panel->aux);
797 pm_runtime_mark_last_busy(dev);
798 pm_runtime_put_autosuspend(dev);
800 goto disable_pm_runtime;
803 drm_panel_add(&panel->base);
808 pm_runtime_dont_use_autosuspend(dev);
809 pm_runtime_disable(dev);
811 if (panel->ddc && (!panel->aux || panel->ddc != &panel->aux->ddc))
812 put_device(&panel->ddc->dev);
817 static int panel_simple_remove(struct device *dev)
819 struct panel_simple *panel = dev_get_drvdata(dev);
821 drm_panel_remove(&panel->base);
822 drm_panel_disable(&panel->base);
823 drm_panel_unprepare(&panel->base);
825 pm_runtime_dont_use_autosuspend(dev);
826 pm_runtime_disable(dev);
827 if (panel->ddc && (!panel->aux || panel->ddc != &panel->aux->ddc))
828 put_device(&panel->ddc->dev);
833 static void panel_simple_shutdown(struct device *dev)
835 struct panel_simple *panel = dev_get_drvdata(dev);
837 drm_panel_disable(&panel->base);
838 drm_panel_unprepare(&panel->base);
841 static const struct drm_display_mode ampire_am_1280800n3tzqw_t00h_mode = {
844 .hsync_start = 1280 + 40,
845 .hsync_end = 1280 + 40 + 80,
846 .htotal = 1280 + 40 + 80 + 40,
848 .vsync_start = 800 + 3,
849 .vsync_end = 800 + 3 + 10,
850 .vtotal = 800 + 3 + 10 + 10,
851 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
854 static const struct panel_desc ampire_am_1280800n3tzqw_t00h = {
855 .modes = &ire_am_1280800n3tzqw_t00h_mode,
862 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
863 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
864 .connector_type = DRM_MODE_CONNECTOR_LVDS,
867 static const struct drm_display_mode ampire_am_480272h3tmqw_t01h_mode = {
870 .hsync_start = 480 + 2,
871 .hsync_end = 480 + 2 + 41,
872 .htotal = 480 + 2 + 41 + 2,
874 .vsync_start = 272 + 2,
875 .vsync_end = 272 + 2 + 10,
876 .vtotal = 272 + 2 + 10 + 2,
877 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
880 static const struct panel_desc ampire_am_480272h3tmqw_t01h = {
881 .modes = &ire_am_480272h3tmqw_t01h_mode,
888 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
891 static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = {
894 .hsync_start = 800 + 0,
895 .hsync_end = 800 + 0 + 255,
896 .htotal = 800 + 0 + 255 + 0,
898 .vsync_start = 480 + 2,
899 .vsync_end = 480 + 2 + 45,
900 .vtotal = 480 + 2 + 45 + 0,
901 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
904 static const struct panel_desc ampire_am800480r3tmqwa1h = {
905 .modes = &ire_am800480r3tmqwa1h_mode,
912 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
915 static const struct display_timing santek_st0700i5y_rbslw_f_timing = {
916 .pixelclock = { 26400000, 33300000, 46800000 },
917 .hactive = { 800, 800, 800 },
918 .hfront_porch = { 16, 210, 354 },
919 .hback_porch = { 45, 36, 6 },
920 .hsync_len = { 1, 10, 40 },
921 .vactive = { 480, 480, 480 },
922 .vfront_porch = { 7, 22, 147 },
923 .vback_porch = { 22, 13, 3 },
924 .vsync_len = { 1, 10, 20 },
925 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
926 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE
929 static const struct panel_desc armadeus_st0700_adapt = {
930 .timings = &santek_st0700i5y_rbslw_f_timing,
937 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
938 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
941 static const struct drm_display_mode auo_b101aw03_mode = {
944 .hsync_start = 1024 + 156,
945 .hsync_end = 1024 + 156 + 8,
946 .htotal = 1024 + 156 + 8 + 156,
948 .vsync_start = 600 + 16,
949 .vsync_end = 600 + 16 + 6,
950 .vtotal = 600 + 16 + 6 + 16,
953 static const struct panel_desc auo_b101aw03 = {
954 .modes = &auo_b101aw03_mode,
961 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
962 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
963 .connector_type = DRM_MODE_CONNECTOR_LVDS,
966 static const struct display_timing auo_b101ean01_timing = {
967 .pixelclock = { 65300000, 72500000, 75000000 },
968 .hactive = { 1280, 1280, 1280 },
969 .hfront_porch = { 18, 119, 119 },
970 .hback_porch = { 21, 21, 21 },
971 .hsync_len = { 32, 32, 32 },
972 .vactive = { 800, 800, 800 },
973 .vfront_porch = { 4, 4, 4 },
974 .vback_porch = { 8, 8, 8 },
975 .vsync_len = { 18, 20, 20 },
978 static const struct panel_desc auo_b101ean01 = {
979 .timings = &auo_b101ean01_timing,
988 static const struct drm_display_mode auo_b101xtn01_mode = {
991 .hsync_start = 1366 + 20,
992 .hsync_end = 1366 + 20 + 70,
993 .htotal = 1366 + 20 + 70,
995 .vsync_start = 768 + 14,
996 .vsync_end = 768 + 14 + 42,
997 .vtotal = 768 + 14 + 42,
998 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1001 static const struct panel_desc auo_b101xtn01 = {
1002 .modes = &auo_b101xtn01_mode,
1011 static const struct drm_display_mode auo_b116xak01_mode = {
1014 .hsync_start = 1366 + 48,
1015 .hsync_end = 1366 + 48 + 32,
1016 .htotal = 1366 + 48 + 32 + 10,
1018 .vsync_start = 768 + 4,
1019 .vsync_end = 768 + 4 + 6,
1020 .vtotal = 768 + 4 + 6 + 15,
1021 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1024 static const struct panel_desc auo_b116xak01 = {
1025 .modes = &auo_b116xak01_mode,
1033 .hpd_absent_delay = 200,
1035 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1036 .connector_type = DRM_MODE_CONNECTOR_eDP,
1039 static const struct drm_display_mode auo_b116xw03_mode = {
1042 .hsync_start = 1366 + 40,
1043 .hsync_end = 1366 + 40 + 40,
1044 .htotal = 1366 + 40 + 40 + 32,
1046 .vsync_start = 768 + 10,
1047 .vsync_end = 768 + 10 + 12,
1048 .vtotal = 768 + 10 + 12 + 6,
1049 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1052 static const struct panel_desc auo_b116xw03 = {
1053 .modes = &auo_b116xw03_mode,
1063 .bus_flags = DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE,
1064 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1065 .connector_type = DRM_MODE_CONNECTOR_eDP,
1068 static const struct drm_display_mode auo_b133xtn01_mode = {
1071 .hsync_start = 1366 + 48,
1072 .hsync_end = 1366 + 48 + 32,
1073 .htotal = 1366 + 48 + 32 + 20,
1075 .vsync_start = 768 + 3,
1076 .vsync_end = 768 + 3 + 6,
1077 .vtotal = 768 + 3 + 6 + 13,
1080 static const struct panel_desc auo_b133xtn01 = {
1081 .modes = &auo_b133xtn01_mode,
1090 static const struct drm_display_mode auo_b133han05_mode = {
1093 .hsync_start = 1920 + 58,
1094 .hsync_end = 1920 + 58 + 42,
1095 .htotal = 1920 + 58 + 42 + 60,
1097 .vsync_start = 1080 + 3,
1098 .vsync_end = 1080 + 3 + 5,
1099 .vtotal = 1080 + 3 + 5 + 54,
1102 static const struct panel_desc auo_b133han05 = {
1103 .modes = &auo_b133han05_mode,
1115 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1116 .bus_flags = DRM_BUS_FLAG_DATA_MSB_TO_LSB,
1117 .connector_type = DRM_MODE_CONNECTOR_eDP,
1120 static const struct drm_display_mode auo_b133htn01_mode = {
1123 .hsync_start = 1920 + 172,
1124 .hsync_end = 1920 + 172 + 80,
1125 .htotal = 1920 + 172 + 80 + 60,
1127 .vsync_start = 1080 + 25,
1128 .vsync_end = 1080 + 25 + 10,
1129 .vtotal = 1080 + 25 + 10 + 10,
1132 static const struct panel_desc auo_b133htn01 = {
1133 .modes = &auo_b133htn01_mode,
1147 static const struct drm_display_mode auo_b140han06_mode = {
1150 .hsync_start = 1920 + 16,
1151 .hsync_end = 1920 + 16 + 16,
1152 .htotal = 1920 + 16 + 16 + 152,
1154 .vsync_start = 1080 + 3,
1155 .vsync_end = 1080 + 3 + 14,
1156 .vtotal = 1080 + 3 + 14 + 19,
1159 static const struct panel_desc auo_b140han06 = {
1160 .modes = &auo_b140han06_mode,
1172 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1173 .bus_flags = DRM_BUS_FLAG_DATA_MSB_TO_LSB,
1174 .connector_type = DRM_MODE_CONNECTOR_eDP,
1177 static const struct display_timing auo_g070vvn01_timings = {
1178 .pixelclock = { 33300000, 34209000, 45000000 },
1179 .hactive = { 800, 800, 800 },
1180 .hfront_porch = { 20, 40, 200 },
1181 .hback_porch = { 87, 40, 1 },
1182 .hsync_len = { 1, 48, 87 },
1183 .vactive = { 480, 480, 480 },
1184 .vfront_porch = { 5, 13, 200 },
1185 .vback_porch = { 31, 31, 29 },
1186 .vsync_len = { 1, 1, 3 },
1189 static const struct panel_desc auo_g070vvn01 = {
1190 .timings = &auo_g070vvn01_timings,
1205 static const struct drm_display_mode auo_g101evn010_mode = {
1208 .hsync_start = 1280 + 82,
1209 .hsync_end = 1280 + 82 + 2,
1210 .htotal = 1280 + 82 + 2 + 84,
1212 .vsync_start = 800 + 8,
1213 .vsync_end = 800 + 8 + 2,
1214 .vtotal = 800 + 8 + 2 + 6,
1217 static const struct panel_desc auo_g101evn010 = {
1218 .modes = &auo_g101evn010_mode,
1225 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1226 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1229 static const struct drm_display_mode auo_g104sn02_mode = {
1232 .hsync_start = 800 + 40,
1233 .hsync_end = 800 + 40 + 216,
1234 .htotal = 800 + 40 + 216 + 128,
1236 .vsync_start = 600 + 10,
1237 .vsync_end = 600 + 10 + 35,
1238 .vtotal = 600 + 10 + 35 + 2,
1241 static const struct panel_desc auo_g104sn02 = {
1242 .modes = &auo_g104sn02_mode,
1249 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1250 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1253 static const struct drm_display_mode auo_g121ean01_mode = {
1256 .hsync_start = 1280 + 58,
1257 .hsync_end = 1280 + 58 + 8,
1258 .htotal = 1280 + 58 + 8 + 70,
1260 .vsync_start = 800 + 6,
1261 .vsync_end = 800 + 6 + 4,
1262 .vtotal = 800 + 6 + 4 + 10,
1265 static const struct panel_desc auo_g121ean01 = {
1266 .modes = &auo_g121ean01_mode,
1273 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1274 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1277 static const struct display_timing auo_g133han01_timings = {
1278 .pixelclock = { 134000000, 141200000, 149000000 },
1279 .hactive = { 1920, 1920, 1920 },
1280 .hfront_porch = { 39, 58, 77 },
1281 .hback_porch = { 59, 88, 117 },
1282 .hsync_len = { 28, 42, 56 },
1283 .vactive = { 1080, 1080, 1080 },
1284 .vfront_porch = { 3, 8, 11 },
1285 .vback_porch = { 5, 14, 19 },
1286 .vsync_len = { 4, 14, 19 },
1289 static const struct panel_desc auo_g133han01 = {
1290 .timings = &auo_g133han01_timings,
1303 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
1304 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1307 static const struct drm_display_mode auo_g156xtn01_mode = {
1310 .hsync_start = 1366 + 33,
1311 .hsync_end = 1366 + 33 + 67,
1314 .vsync_start = 768 + 4,
1315 .vsync_end = 768 + 4 + 4,
1319 static const struct panel_desc auo_g156xtn01 = {
1320 .modes = &auo_g156xtn01_mode,
1327 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1328 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1331 static const struct display_timing auo_g185han01_timings = {
1332 .pixelclock = { 120000000, 144000000, 175000000 },
1333 .hactive = { 1920, 1920, 1920 },
1334 .hfront_porch = { 36, 120, 148 },
1335 .hback_porch = { 24, 88, 108 },
1336 .hsync_len = { 20, 48, 64 },
1337 .vactive = { 1080, 1080, 1080 },
1338 .vfront_porch = { 6, 10, 40 },
1339 .vback_porch = { 2, 5, 20 },
1340 .vsync_len = { 2, 5, 20 },
1343 static const struct panel_desc auo_g185han01 = {
1344 .timings = &auo_g185han01_timings,
1357 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1358 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1361 static const struct display_timing auo_g190ean01_timings = {
1362 .pixelclock = { 90000000, 108000000, 135000000 },
1363 .hactive = { 1280, 1280, 1280 },
1364 .hfront_porch = { 126, 184, 1266 },
1365 .hback_porch = { 84, 122, 844 },
1366 .hsync_len = { 70, 102, 704 },
1367 .vactive = { 1024, 1024, 1024 },
1368 .vfront_porch = { 4, 26, 76 },
1369 .vback_porch = { 2, 8, 25 },
1370 .vsync_len = { 2, 8, 25 },
1373 static const struct panel_desc auo_g190ean01 = {
1374 .timings = &auo_g190ean01_timings,
1387 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1388 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1391 static const struct display_timing auo_p320hvn03_timings = {
1392 .pixelclock = { 106000000, 148500000, 164000000 },
1393 .hactive = { 1920, 1920, 1920 },
1394 .hfront_porch = { 25, 50, 130 },
1395 .hback_porch = { 25, 50, 130 },
1396 .hsync_len = { 20, 40, 105 },
1397 .vactive = { 1080, 1080, 1080 },
1398 .vfront_porch = { 8, 17, 150 },
1399 .vback_porch = { 8, 17, 150 },
1400 .vsync_len = { 4, 11, 100 },
1403 static const struct panel_desc auo_p320hvn03 = {
1404 .timings = &auo_p320hvn03_timings,
1416 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1417 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1420 static const struct drm_display_mode auo_t215hvn01_mode = {
1423 .hsync_start = 1920 + 88,
1424 .hsync_end = 1920 + 88 + 44,
1425 .htotal = 1920 + 88 + 44 + 148,
1427 .vsync_start = 1080 + 4,
1428 .vsync_end = 1080 + 4 + 5,
1429 .vtotal = 1080 + 4 + 5 + 36,
1432 static const struct panel_desc auo_t215hvn01 = {
1433 .modes = &auo_t215hvn01_mode,
1446 static const struct drm_display_mode avic_tm070ddh03_mode = {
1449 .hsync_start = 1024 + 160,
1450 .hsync_end = 1024 + 160 + 4,
1451 .htotal = 1024 + 160 + 4 + 156,
1453 .vsync_start = 600 + 17,
1454 .vsync_end = 600 + 17 + 1,
1455 .vtotal = 600 + 17 + 1 + 17,
1458 static const struct panel_desc avic_tm070ddh03 = {
1459 .modes = &avic_tm070ddh03_mode,
1473 static const struct drm_display_mode bananapi_s070wv20_ct16_mode = {
1476 .hsync_start = 800 + 40,
1477 .hsync_end = 800 + 40 + 48,
1478 .htotal = 800 + 40 + 48 + 40,
1480 .vsync_start = 480 + 13,
1481 .vsync_end = 480 + 13 + 3,
1482 .vtotal = 480 + 13 + 3 + 29,
1485 static const struct panel_desc bananapi_s070wv20_ct16 = {
1486 .modes = &bananapi_s070wv20_ct16_mode,
1495 static const struct drm_display_mode boe_hv070wsa_mode = {
1498 .hsync_start = 1024 + 30,
1499 .hsync_end = 1024 + 30 + 30,
1500 .htotal = 1024 + 30 + 30 + 30,
1502 .vsync_start = 600 + 10,
1503 .vsync_end = 600 + 10 + 10,
1504 .vtotal = 600 + 10 + 10 + 10,
1507 static const struct panel_desc boe_hv070wsa = {
1508 .modes = &boe_hv070wsa_mode,
1515 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1516 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1517 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1520 static const struct drm_display_mode boe_nv101wxmn51_modes[] = {
1524 .hsync_start = 1280 + 48,
1525 .hsync_end = 1280 + 48 + 32,
1526 .htotal = 1280 + 48 + 32 + 80,
1528 .vsync_start = 800 + 3,
1529 .vsync_end = 800 + 3 + 5,
1530 .vtotal = 800 + 3 + 5 + 24,
1535 .hsync_start = 1280 + 48,
1536 .hsync_end = 1280 + 48 + 32,
1537 .htotal = 1280 + 48 + 32 + 80,
1539 .vsync_start = 800 + 3,
1540 .vsync_end = 800 + 3 + 5,
1541 .vtotal = 800 + 3 + 5 + 24,
1545 static const struct panel_desc boe_nv101wxmn51 = {
1546 .modes = boe_nv101wxmn51_modes,
1547 .num_modes = ARRAY_SIZE(boe_nv101wxmn51_modes),
1560 static const struct drm_display_mode boe_nv110wtm_n61_modes[] = {
1564 .hsync_start = 2160 + 48,
1565 .hsync_end = 2160 + 48 + 32,
1566 .htotal = 2160 + 48 + 32 + 100,
1568 .vsync_start = 1440 + 3,
1569 .vsync_end = 1440 + 3 + 6,
1570 .vtotal = 1440 + 3 + 6 + 31,
1571 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC,
1576 .hsync_start = 2160 + 48,
1577 .hsync_end = 2160 + 48 + 32,
1578 .htotal = 2160 + 48 + 32 + 100,
1580 .vsync_start = 1440 + 3,
1581 .vsync_end = 1440 + 3 + 6,
1582 .vtotal = 1440 + 3 + 6 + 31,
1583 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC,
1587 static const struct panel_desc boe_nv110wtm_n61 = {
1588 .modes = boe_nv110wtm_n61_modes,
1589 .num_modes = ARRAY_SIZE(boe_nv110wtm_n61_modes),
1596 .hpd_absent_delay = 200,
1597 .prepare_to_enable = 80,
1601 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1602 .bus_flags = DRM_BUS_FLAG_DATA_MSB_TO_LSB,
1603 .connector_type = DRM_MODE_CONNECTOR_eDP,
1606 /* Also used for boe_nv133fhm_n62 */
1607 static const struct drm_display_mode boe_nv133fhm_n61_modes = {
1610 .hsync_start = 1920 + 48,
1611 .hsync_end = 1920 + 48 + 32,
1612 .htotal = 1920 + 48 + 32 + 200,
1614 .vsync_start = 1080 + 3,
1615 .vsync_end = 1080 + 3 + 6,
1616 .vtotal = 1080 + 3 + 6 + 31,
1617 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC,
1620 /* Also used for boe_nv133fhm_n62 */
1621 static const struct panel_desc boe_nv133fhm_n61 = {
1622 .modes = &boe_nv133fhm_n61_modes,
1631 * When power is first given to the panel there's a short
1632 * spike on the HPD line. It was explained that this spike
1633 * was until the TCON data download was complete. On
1634 * one system this was measured at 8 ms. We'll put 15 ms
1635 * in the prepare delay just to be safe and take it away
1636 * from the hpd_absent_delay (which would otherwise be 200 ms)
1637 * to handle this. That means:
1638 * - If HPD isn't hooked up you still have 200 ms delay.
1639 * - If HPD is hooked up we won't try to look at it for the
1643 .hpd_absent_delay = 185,
1647 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1648 .bus_flags = DRM_BUS_FLAG_DATA_MSB_TO_LSB,
1649 .connector_type = DRM_MODE_CONNECTOR_eDP,
1652 static const struct drm_display_mode boe_nv140fhmn49_modes[] = {
1656 .hsync_start = 1920 + 48,
1657 .hsync_end = 1920 + 48 + 32,
1660 .vsync_start = 1080 + 3,
1661 .vsync_end = 1080 + 3 + 5,
1666 static const struct panel_desc boe_nv140fhmn49 = {
1667 .modes = boe_nv140fhmn49_modes,
1668 .num_modes = ARRAY_SIZE(boe_nv140fhmn49_modes),
1679 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1680 .connector_type = DRM_MODE_CONNECTOR_eDP,
1683 static const struct drm_display_mode cdtech_s043wq26h_ct7_mode = {
1686 .hsync_start = 480 + 5,
1687 .hsync_end = 480 + 5 + 5,
1688 .htotal = 480 + 5 + 5 + 40,
1690 .vsync_start = 272 + 8,
1691 .vsync_end = 272 + 8 + 8,
1692 .vtotal = 272 + 8 + 8 + 8,
1693 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1696 static const struct panel_desc cdtech_s043wq26h_ct7 = {
1697 .modes = &cdtech_s043wq26h_ct7_mode,
1704 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1707 /* S070PWS19HP-FC21 2017/04/22 */
1708 static const struct drm_display_mode cdtech_s070pws19hp_fc21_mode = {
1711 .hsync_start = 1024 + 160,
1712 .hsync_end = 1024 + 160 + 20,
1713 .htotal = 1024 + 160 + 20 + 140,
1715 .vsync_start = 600 + 12,
1716 .vsync_end = 600 + 12 + 3,
1717 .vtotal = 600 + 12 + 3 + 20,
1718 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1721 static const struct panel_desc cdtech_s070pws19hp_fc21 = {
1722 .modes = &cdtech_s070pws19hp_fc21_mode,
1729 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1730 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
1731 .connector_type = DRM_MODE_CONNECTOR_DPI,
1734 /* S070SWV29HG-DC44 2017/09/21 */
1735 static const struct drm_display_mode cdtech_s070swv29hg_dc44_mode = {
1738 .hsync_start = 800 + 210,
1739 .hsync_end = 800 + 210 + 2,
1740 .htotal = 800 + 210 + 2 + 44,
1742 .vsync_start = 480 + 22,
1743 .vsync_end = 480 + 22 + 2,
1744 .vtotal = 480 + 22 + 2 + 21,
1745 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1748 static const struct panel_desc cdtech_s070swv29hg_dc44 = {
1749 .modes = &cdtech_s070swv29hg_dc44_mode,
1756 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1757 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
1758 .connector_type = DRM_MODE_CONNECTOR_DPI,
1761 static const struct drm_display_mode cdtech_s070wv95_ct16_mode = {
1764 .hsync_start = 800 + 40,
1765 .hsync_end = 800 + 40 + 40,
1766 .htotal = 800 + 40 + 40 + 48,
1768 .vsync_start = 480 + 29,
1769 .vsync_end = 480 + 29 + 13,
1770 .vtotal = 480 + 29 + 13 + 3,
1771 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1774 static const struct panel_desc cdtech_s070wv95_ct16 = {
1775 .modes = &cdtech_s070wv95_ct16_mode,
1784 static const struct display_timing chefree_ch101olhlwh_002_timing = {
1785 .pixelclock = { 68900000, 71100000, 73400000 },
1786 .hactive = { 1280, 1280, 1280 },
1787 .hfront_porch = { 65, 80, 95 },
1788 .hback_porch = { 64, 79, 94 },
1789 .hsync_len = { 1, 1, 1 },
1790 .vactive = { 800, 800, 800 },
1791 .vfront_porch = { 7, 11, 14 },
1792 .vback_porch = { 7, 11, 14 },
1793 .vsync_len = { 1, 1, 1 },
1794 .flags = DISPLAY_FLAGS_DE_HIGH,
1797 static const struct panel_desc chefree_ch101olhlwh_002 = {
1798 .timings = &chefree_ch101olhlwh_002_timing,
1809 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1810 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1811 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1814 static const struct drm_display_mode chunghwa_claa070wp03xg_mode = {
1817 .hsync_start = 800 + 49,
1818 .hsync_end = 800 + 49 + 33,
1819 .htotal = 800 + 49 + 33 + 17,
1821 .vsync_start = 1280 + 1,
1822 .vsync_end = 1280 + 1 + 7,
1823 .vtotal = 1280 + 1 + 7 + 15,
1824 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1827 static const struct panel_desc chunghwa_claa070wp03xg = {
1828 .modes = &chunghwa_claa070wp03xg_mode,
1835 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1836 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1837 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1840 static const struct drm_display_mode chunghwa_claa101wa01a_mode = {
1843 .hsync_start = 1366 + 58,
1844 .hsync_end = 1366 + 58 + 58,
1845 .htotal = 1366 + 58 + 58 + 58,
1847 .vsync_start = 768 + 4,
1848 .vsync_end = 768 + 4 + 4,
1849 .vtotal = 768 + 4 + 4 + 4,
1852 static const struct panel_desc chunghwa_claa101wa01a = {
1853 .modes = &chunghwa_claa101wa01a_mode,
1860 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1861 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1862 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1865 static const struct drm_display_mode chunghwa_claa101wb01_mode = {
1868 .hsync_start = 1366 + 48,
1869 .hsync_end = 1366 + 48 + 32,
1870 .htotal = 1366 + 48 + 32 + 20,
1872 .vsync_start = 768 + 16,
1873 .vsync_end = 768 + 16 + 8,
1874 .vtotal = 768 + 16 + 8 + 16,
1877 static const struct panel_desc chunghwa_claa101wb01 = {
1878 .modes = &chunghwa_claa101wb01_mode,
1885 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1886 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1887 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1890 static const struct drm_display_mode dataimage_scf0700c48ggu18_mode = {
1893 .hsync_start = 800 + 40,
1894 .hsync_end = 800 + 40 + 128,
1895 .htotal = 800 + 40 + 128 + 88,
1897 .vsync_start = 480 + 10,
1898 .vsync_end = 480 + 10 + 2,
1899 .vtotal = 480 + 10 + 2 + 33,
1900 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1903 static const struct panel_desc dataimage_scf0700c48ggu18 = {
1904 .modes = &dataimage_scf0700c48ggu18_mode,
1911 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1912 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1915 static const struct display_timing dlc_dlc0700yzg_1_timing = {
1916 .pixelclock = { 45000000, 51200000, 57000000 },
1917 .hactive = { 1024, 1024, 1024 },
1918 .hfront_porch = { 100, 106, 113 },
1919 .hback_porch = { 100, 106, 113 },
1920 .hsync_len = { 100, 108, 114 },
1921 .vactive = { 600, 600, 600 },
1922 .vfront_porch = { 8, 11, 15 },
1923 .vback_porch = { 8, 11, 15 },
1924 .vsync_len = { 9, 13, 15 },
1925 .flags = DISPLAY_FLAGS_DE_HIGH,
1928 static const struct panel_desc dlc_dlc0700yzg_1 = {
1929 .timings = &dlc_dlc0700yzg_1_timing,
1941 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1942 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1945 static const struct display_timing dlc_dlc1010gig_timing = {
1946 .pixelclock = { 68900000, 71100000, 73400000 },
1947 .hactive = { 1280, 1280, 1280 },
1948 .hfront_porch = { 43, 53, 63 },
1949 .hback_porch = { 43, 53, 63 },
1950 .hsync_len = { 44, 54, 64 },
1951 .vactive = { 800, 800, 800 },
1952 .vfront_porch = { 5, 8, 11 },
1953 .vback_porch = { 5, 8, 11 },
1954 .vsync_len = { 5, 7, 11 },
1955 .flags = DISPLAY_FLAGS_DE_HIGH,
1958 static const struct panel_desc dlc_dlc1010gig = {
1959 .timings = &dlc_dlc1010gig_timing,
1972 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1973 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1976 static const struct drm_display_mode edt_et035012dm6_mode = {
1979 .hsync_start = 320 + 20,
1980 .hsync_end = 320 + 20 + 30,
1981 .htotal = 320 + 20 + 68,
1983 .vsync_start = 240 + 4,
1984 .vsync_end = 240 + 4 + 4,
1985 .vtotal = 240 + 4 + 4 + 14,
1986 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1989 static const struct panel_desc edt_et035012dm6 = {
1990 .modes = &edt_et035012dm6_mode,
1997 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1998 .bus_flags = DRM_BUS_FLAG_DE_LOW | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
2001 static const struct drm_display_mode edt_etm0350g0dh6_mode = {
2004 .hsync_start = 320 + 20,
2005 .hsync_end = 320 + 20 + 68,
2006 .htotal = 320 + 20 + 68,
2008 .vsync_start = 240 + 4,
2009 .vsync_end = 240 + 4 + 18,
2010 .vtotal = 240 + 4 + 18,
2011 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2014 static const struct panel_desc edt_etm0350g0dh6 = {
2015 .modes = &edt_etm0350g0dh6_mode,
2022 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2023 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
2024 .connector_type = DRM_MODE_CONNECTOR_DPI,
2027 static const struct drm_display_mode edt_etm043080dh6gp_mode = {
2030 .hsync_start = 480 + 8,
2031 .hsync_end = 480 + 8 + 4,
2032 .htotal = 480 + 8 + 4 + 41,
2035 * IWG22M: Y resolution changed for "dc_linuxfb" module crashing while
2040 .vsync_start = 288 + 2,
2041 .vsync_end = 288 + 2 + 4,
2042 .vtotal = 288 + 2 + 4 + 10,
2045 static const struct panel_desc edt_etm043080dh6gp = {
2046 .modes = &edt_etm043080dh6gp_mode,
2053 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2054 .connector_type = DRM_MODE_CONNECTOR_DPI,
2057 static const struct drm_display_mode edt_etm0430g0dh6_mode = {
2060 .hsync_start = 480 + 2,
2061 .hsync_end = 480 + 2 + 41,
2062 .htotal = 480 + 2 + 41 + 2,
2064 .vsync_start = 272 + 2,
2065 .vsync_end = 272 + 2 + 10,
2066 .vtotal = 272 + 2 + 10 + 2,
2067 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
2070 static const struct panel_desc edt_etm0430g0dh6 = {
2071 .modes = &edt_etm0430g0dh6_mode,
2078 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2079 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
2080 .connector_type = DRM_MODE_CONNECTOR_DPI,
2083 static const struct drm_display_mode edt_et057090dhu_mode = {
2086 .hsync_start = 640 + 16,
2087 .hsync_end = 640 + 16 + 30,
2088 .htotal = 640 + 16 + 30 + 114,
2090 .vsync_start = 480 + 10,
2091 .vsync_end = 480 + 10 + 3,
2092 .vtotal = 480 + 10 + 3 + 32,
2093 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2096 static const struct panel_desc edt_et057090dhu = {
2097 .modes = &edt_et057090dhu_mode,
2104 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2105 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
2106 .connector_type = DRM_MODE_CONNECTOR_DPI,
2109 static const struct drm_display_mode edt_etm0700g0dh6_mode = {
2112 .hsync_start = 800 + 40,
2113 .hsync_end = 800 + 40 + 128,
2114 .htotal = 800 + 40 + 128 + 88,
2116 .vsync_start = 480 + 10,
2117 .vsync_end = 480 + 10 + 2,
2118 .vtotal = 480 + 10 + 2 + 33,
2119 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
2122 static const struct panel_desc edt_etm0700g0dh6 = {
2123 .modes = &edt_etm0700g0dh6_mode,
2130 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2131 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
2132 .connector_type = DRM_MODE_CONNECTOR_DPI,
2135 static const struct panel_desc edt_etm0700g0bdh6 = {
2136 .modes = &edt_etm0700g0dh6_mode,
2143 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2144 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
2145 .connector_type = DRM_MODE_CONNECTOR_DPI,
2148 static const struct drm_display_mode edt_etmv570g2dhu_mode = {
2152 .hsync_end = 640 + 16,
2153 .htotal = 640 + 16 + 30 + 114,
2155 .vsync_start = 480 + 10,
2156 .vsync_end = 480 + 10 + 3,
2157 .vtotal = 480 + 10 + 3 + 35,
2158 .flags = DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_PHSYNC,
2161 static const struct panel_desc edt_etmv570g2dhu = {
2162 .modes = &edt_etmv570g2dhu_mode,
2169 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2170 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
2171 .connector_type = DRM_MODE_CONNECTOR_DPI,
2174 static const struct display_timing eink_vb3300_kca_timing = {
2175 .pixelclock = { 40000000, 40000000, 40000000 },
2176 .hactive = { 334, 334, 334 },
2177 .hfront_porch = { 1, 1, 1 },
2178 .hback_porch = { 1, 1, 1 },
2179 .hsync_len = { 1, 1, 1 },
2180 .vactive = { 1405, 1405, 1405 },
2181 .vfront_porch = { 1, 1, 1 },
2182 .vback_porch = { 1, 1, 1 },
2183 .vsync_len = { 1, 1, 1 },
2184 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
2185 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE,
2188 static const struct panel_desc eink_vb3300_kca = {
2189 .timings = &eink_vb3300_kca_timing,
2196 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2197 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
2198 .connector_type = DRM_MODE_CONNECTOR_DPI,
2201 static const struct display_timing evervision_vgg804821_timing = {
2202 .pixelclock = { 27600000, 33300000, 50000000 },
2203 .hactive = { 800, 800, 800 },
2204 .hfront_porch = { 40, 66, 70 },
2205 .hback_porch = { 40, 67, 70 },
2206 .hsync_len = { 40, 67, 70 },
2207 .vactive = { 480, 480, 480 },
2208 .vfront_porch = { 6, 10, 10 },
2209 .vback_porch = { 7, 11, 11 },
2210 .vsync_len = { 7, 11, 11 },
2211 .flags = DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH |
2212 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE |
2213 DISPLAY_FLAGS_SYNC_NEGEDGE,
2216 static const struct panel_desc evervision_vgg804821 = {
2217 .timings = &evervision_vgg804821_timing,
2224 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2225 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
2228 static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = {
2231 .hsync_start = 800 + 168,
2232 .hsync_end = 800 + 168 + 64,
2233 .htotal = 800 + 168 + 64 + 88,
2235 .vsync_start = 480 + 37,
2236 .vsync_end = 480 + 37 + 2,
2237 .vtotal = 480 + 37 + 2 + 8,
2240 static const struct panel_desc foxlink_fl500wvr00_a0t = {
2241 .modes = &foxlink_fl500wvr00_a0t_mode,
2248 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2251 static const struct drm_display_mode frida_frd350h54004_modes[] = {
2255 .hsync_start = 320 + 44,
2256 .hsync_end = 320 + 44 + 16,
2257 .htotal = 320 + 44 + 16 + 20,
2259 .vsync_start = 240 + 2,
2260 .vsync_end = 240 + 2 + 6,
2261 .vtotal = 240 + 2 + 6 + 2,
2262 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
2267 .hsync_start = 320 + 56,
2268 .hsync_end = 320 + 56 + 16,
2269 .htotal = 320 + 56 + 16 + 40,
2271 .vsync_start = 240 + 2,
2272 .vsync_end = 240 + 2 + 6,
2273 .vtotal = 240 + 2 + 6 + 2,
2274 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
2278 static const struct panel_desc frida_frd350h54004 = {
2279 .modes = frida_frd350h54004_modes,
2280 .num_modes = ARRAY_SIZE(frida_frd350h54004_modes),
2286 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2287 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
2288 .connector_type = DRM_MODE_CONNECTOR_DPI,
2291 static const struct drm_display_mode friendlyarm_hd702e_mode = {
2294 .hsync_start = 800 + 20,
2295 .hsync_end = 800 + 20 + 24,
2296 .htotal = 800 + 20 + 24 + 20,
2298 .vsync_start = 1280 + 4,
2299 .vsync_end = 1280 + 4 + 8,
2300 .vtotal = 1280 + 4 + 8 + 4,
2301 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2304 static const struct panel_desc friendlyarm_hd702e = {
2305 .modes = &friendlyarm_hd702e_mode,
2313 static const struct drm_display_mode geekworm_mzp280_mode = {
2316 .hsync_start = 480 + 41,
2317 .hsync_end = 480 + 41 + 20,
2318 .htotal = 480 + 41 + 20 + 60,
2320 .vsync_start = 640 + 5,
2321 .vsync_end = 640 + 5 + 10,
2322 .vtotal = 640 + 5 + 10 + 10,
2323 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2326 static const struct panel_desc geekworm_mzp280 = {
2327 .modes = &geekworm_mzp280_mode,
2334 .bus_format = MEDIA_BUS_FMT_RGB565_1X24_CPADHI,
2335 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
2336 .connector_type = DRM_MODE_CONNECTOR_DPI,
2339 static const struct drm_display_mode giantplus_gpg482739qs5_mode = {
2342 .hsync_start = 480 + 5,
2343 .hsync_end = 480 + 5 + 1,
2344 .htotal = 480 + 5 + 1 + 40,
2346 .vsync_start = 272 + 8,
2347 .vsync_end = 272 + 8 + 1,
2348 .vtotal = 272 + 8 + 1 + 8,
2351 static const struct panel_desc giantplus_gpg482739qs5 = {
2352 .modes = &giantplus_gpg482739qs5_mode,
2359 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2362 static const struct display_timing giantplus_gpm940b0_timing = {
2363 .pixelclock = { 13500000, 27000000, 27500000 },
2364 .hactive = { 320, 320, 320 },
2365 .hfront_porch = { 14, 686, 718 },
2366 .hback_porch = { 50, 70, 255 },
2367 .hsync_len = { 1, 1, 1 },
2368 .vactive = { 240, 240, 240 },
2369 .vfront_porch = { 1, 1, 179 },
2370 .vback_porch = { 1, 21, 31 },
2371 .vsync_len = { 1, 1, 6 },
2372 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
2375 static const struct panel_desc giantplus_gpm940b0 = {
2376 .timings = &giantplus_gpm940b0_timing,
2383 .bus_format = MEDIA_BUS_FMT_RGB888_3X8,
2384 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
2387 static const struct display_timing hannstar_hsd070pww1_timing = {
2388 .pixelclock = { 64300000, 71100000, 82000000 },
2389 .hactive = { 1280, 1280, 1280 },
2390 .hfront_porch = { 1, 1, 10 },
2391 .hback_porch = { 1, 1, 10 },
2393 * According to the data sheet, the minimum horizontal blanking interval
2394 * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the
2395 * minimum working horizontal blanking interval to be 60 clocks.
2397 .hsync_len = { 58, 158, 661 },
2398 .vactive = { 800, 800, 800 },
2399 .vfront_porch = { 1, 1, 10 },
2400 .vback_porch = { 1, 1, 10 },
2401 .vsync_len = { 1, 21, 203 },
2402 .flags = DISPLAY_FLAGS_DE_HIGH,
2405 static const struct panel_desc hannstar_hsd070pww1 = {
2406 .timings = &hannstar_hsd070pww1_timing,
2413 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2414 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2417 static const struct display_timing hannstar_hsd100pxn1_timing = {
2418 .pixelclock = { 55000000, 65000000, 75000000 },
2419 .hactive = { 1024, 1024, 1024 },
2420 .hfront_porch = { 40, 40, 40 },
2421 .hback_porch = { 220, 220, 220 },
2422 .hsync_len = { 20, 60, 100 },
2423 .vactive = { 768, 768, 768 },
2424 .vfront_porch = { 7, 7, 7 },
2425 .vback_porch = { 21, 21, 21 },
2426 .vsync_len = { 10, 10, 10 },
2427 .flags = DISPLAY_FLAGS_DE_HIGH,
2430 static const struct panel_desc hannstar_hsd100pxn1 = {
2431 .timings = &hannstar_hsd100pxn1_timing,
2438 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2439 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2442 static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = {
2445 .hsync_start = 800 + 85,
2446 .hsync_end = 800 + 85 + 86,
2447 .htotal = 800 + 85 + 86 + 85,
2449 .vsync_start = 480 + 16,
2450 .vsync_end = 480 + 16 + 13,
2451 .vtotal = 480 + 16 + 13 + 16,
2454 static const struct panel_desc hitachi_tx23d38vm0caa = {
2455 .modes = &hitachi_tx23d38vm0caa_mode,
2468 static const struct drm_display_mode innolux_at043tn24_mode = {
2471 .hsync_start = 480 + 2,
2472 .hsync_end = 480 + 2 + 41,
2473 .htotal = 480 + 2 + 41 + 2,
2475 .vsync_start = 272 + 2,
2476 .vsync_end = 272 + 2 + 10,
2477 .vtotal = 272 + 2 + 10 + 2,
2478 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
2481 static const struct panel_desc innolux_at043tn24 = {
2482 .modes = &innolux_at043tn24_mode,
2489 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2490 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
2493 static const struct display_timing innolux_at056tn53v1_timing = {
2494 .pixelclock = { 39700000, 39700000, 39700000},
2495 .hactive = { 640, 640, 640 },
2496 .hfront_porch = { 16, 16, 16 },
2497 .hback_porch = { 134, 134, 134 },
2498 .hsync_len = { 10, 10, 10},
2499 .vactive = { 480, 480, 480 },
2500 .vfront_porch = { 32, 32, 32},
2501 .vback_porch = { 11, 11, 11 },
2502 .vsync_len = { 2, 2, 2 },
2503 .flags = DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_PHSYNC,
2506 static const struct panel_desc innolux_at056tn53v1 = {
2507 .timings = &innolux_at056tn53v1_timing,
2520 .bus_format = MEDIA_BUS_FMT_BGR666_1X24_CPADHI,
2521 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
2522 .connector_type = DRM_MODE_CONNECTOR_DPI,
2525 static const struct drm_display_mode innolux_at070tn92_mode = {
2528 .hsync_start = 800 + 210,
2529 .hsync_end = 800 + 210 + 20,
2530 .htotal = 800 + 210 + 20 + 46,
2532 .vsync_start = 480 + 22,
2533 .vsync_end = 480 + 22 + 10,
2534 .vtotal = 480 + 22 + 23 + 10,
2537 static const struct panel_desc innolux_at070tn92 = {
2538 .modes = &innolux_at070tn92_mode,
2544 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2547 static const struct display_timing innolux_g070y2_l01_timing = {
2548 .pixelclock = { 28000000, 29500000, 32000000 },
2549 .hactive = { 800, 800, 800 },
2550 .hfront_porch = { 61, 91, 141 },
2551 .hback_porch = { 60, 90, 140 },
2552 .hsync_len = { 12, 12, 12 },
2553 .vactive = { 480, 480, 480 },
2554 .vfront_porch = { 4, 9, 30 },
2555 .vback_porch = { 4, 8, 28 },
2556 .vsync_len = { 2, 2, 2 },
2557 .flags = DISPLAY_FLAGS_DE_HIGH,
2560 static const struct panel_desc innolux_g070y2_l01 = {
2561 .timings = &innolux_g070y2_l01_timing,
2574 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2575 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2576 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2579 static const struct display_timing innolux_g101ice_l01_timing = {
2580 .pixelclock = { 60400000, 71100000, 74700000 },
2581 .hactive = { 1280, 1280, 1280 },
2582 .hfront_porch = { 41, 80, 100 },
2583 .hback_porch = { 40, 79, 99 },
2584 .hsync_len = { 1, 1, 1 },
2585 .vactive = { 800, 800, 800 },
2586 .vfront_porch = { 5, 11, 14 },
2587 .vback_porch = { 4, 11, 14 },
2588 .vsync_len = { 1, 1, 1 },
2589 .flags = DISPLAY_FLAGS_DE_HIGH,
2592 static const struct panel_desc innolux_g101ice_l01 = {
2593 .timings = &innolux_g101ice_l01_timing,
2604 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2605 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2608 static const struct display_timing innolux_g121i1_l01_timing = {
2609 .pixelclock = { 67450000, 71000000, 74550000 },
2610 .hactive = { 1280, 1280, 1280 },
2611 .hfront_porch = { 40, 80, 160 },
2612 .hback_porch = { 39, 79, 159 },
2613 .hsync_len = { 1, 1, 1 },
2614 .vactive = { 800, 800, 800 },
2615 .vfront_porch = { 5, 11, 100 },
2616 .vback_porch = { 4, 11, 99 },
2617 .vsync_len = { 1, 1, 1 },
2620 static const struct panel_desc innolux_g121i1_l01 = {
2621 .timings = &innolux_g121i1_l01_timing,
2632 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2633 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2636 static const struct drm_display_mode innolux_g121x1_l03_mode = {
2639 .hsync_start = 1024 + 0,
2640 .hsync_end = 1024 + 1,
2641 .htotal = 1024 + 0 + 1 + 320,
2643 .vsync_start = 768 + 38,
2644 .vsync_end = 768 + 38 + 1,
2645 .vtotal = 768 + 38 + 1 + 0,
2646 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
2649 static const struct panel_desc innolux_g121x1_l03 = {
2650 .modes = &innolux_g121x1_l03_mode,
2664 static const struct drm_display_mode innolux_n116bca_ea1_mode = {
2667 .hsync_start = 1366 + 136,
2668 .hsync_end = 1366 + 136 + 30,
2669 .htotal = 1366 + 136 + 30 + 60,
2671 .vsync_start = 768 + 8,
2672 .vsync_end = 768 + 8 + 12,
2673 .vtotal = 768 + 8 + 12 + 12,
2674 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
2677 static const struct panel_desc innolux_n116bca_ea1 = {
2678 .modes = &innolux_n116bca_ea1_mode,
2686 .hpd_absent_delay = 200,
2687 .prepare_to_enable = 80,
2690 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2691 .connector_type = DRM_MODE_CONNECTOR_eDP,
2695 * Datasheet specifies that at 60 Hz refresh rate:
2696 * - total horizontal time: { 1506, 1592, 1716 }
2697 * - total vertical time: { 788, 800, 868 }
2699 * ...but doesn't go into exactly how that should be split into a front
2700 * porch, back porch, or sync length. For now we'll leave a single setting
2701 * here which allows a bit of tweaking of the pixel clock at the expense of
2704 static const struct display_timing innolux_n116bge_timing = {
2705 .pixelclock = { 72600000, 76420000, 80240000 },
2706 .hactive = { 1366, 1366, 1366 },
2707 .hfront_porch = { 136, 136, 136 },
2708 .hback_porch = { 60, 60, 60 },
2709 .hsync_len = { 30, 30, 30 },
2710 .vactive = { 768, 768, 768 },
2711 .vfront_porch = { 8, 8, 8 },
2712 .vback_porch = { 12, 12, 12 },
2713 .vsync_len = { 12, 12, 12 },
2714 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW,
2717 static const struct panel_desc innolux_n116bge = {
2718 .timings = &innolux_n116bge_timing,
2725 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2726 .connector_type = DRM_MODE_CONNECTOR_eDP,
2729 static const struct drm_display_mode innolux_n125hce_gn1_mode = {
2732 .hsync_start = 1920 + 40,
2733 .hsync_end = 1920 + 40 + 40,
2734 .htotal = 1920 + 40 + 40 + 80,
2736 .vsync_start = 1080 + 4,
2737 .vsync_end = 1080 + 4 + 4,
2738 .vtotal = 1080 + 4 + 4 + 24,
2741 static const struct panel_desc innolux_n125hce_gn1 = {
2742 .modes = &innolux_n125hce_gn1_mode,
2749 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2750 .bus_flags = DRM_BUS_FLAG_DATA_MSB_TO_LSB,
2751 .connector_type = DRM_MODE_CONNECTOR_eDP,
2754 static const struct drm_display_mode innolux_n156bge_l21_mode = {
2757 .hsync_start = 1366 + 16,
2758 .hsync_end = 1366 + 16 + 34,
2759 .htotal = 1366 + 16 + 34 + 50,
2761 .vsync_start = 768 + 2,
2762 .vsync_end = 768 + 2 + 6,
2763 .vtotal = 768 + 2 + 6 + 12,
2766 static const struct panel_desc innolux_n156bge_l21 = {
2767 .modes = &innolux_n156bge_l21_mode,
2774 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2775 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2776 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2779 static const struct drm_display_mode innolux_p120zdg_bf1_mode = {
2782 .hsync_start = 2160 + 48,
2783 .hsync_end = 2160 + 48 + 32,
2784 .htotal = 2160 + 48 + 32 + 80,
2786 .vsync_start = 1440 + 3,
2787 .vsync_end = 1440 + 3 + 10,
2788 .vtotal = 1440 + 3 + 10 + 27,
2789 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
2792 static const struct panel_desc innolux_p120zdg_bf1 = {
2793 .modes = &innolux_p120zdg_bf1_mode,
2801 .hpd_absent_delay = 200,
2806 static const struct drm_display_mode innolux_zj070na_01p_mode = {
2809 .hsync_start = 1024 + 128,
2810 .hsync_end = 1024 + 128 + 64,
2811 .htotal = 1024 + 128 + 64 + 128,
2813 .vsync_start = 600 + 16,
2814 .vsync_end = 600 + 16 + 4,
2815 .vtotal = 600 + 16 + 4 + 16,
2818 static const struct panel_desc innolux_zj070na_01p = {
2819 .modes = &innolux_zj070na_01p_mode,
2828 static const struct drm_display_mode ivo_m133nwf4_r0_mode = {
2831 .hsync_start = 1920 + 24,
2832 .hsync_end = 1920 + 24 + 48,
2833 .htotal = 1920 + 24 + 48 + 88,
2835 .vsync_start = 1080 + 3,
2836 .vsync_end = 1080 + 3 + 12,
2837 .vtotal = 1080 + 3 + 12 + 17,
2838 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
2841 static const struct panel_desc ivo_m133nwf4_r0 = {
2842 .modes = &ivo_m133nwf4_r0_mode,
2850 .hpd_absent_delay = 200,
2853 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2854 .bus_flags = DRM_BUS_FLAG_DATA_MSB_TO_LSB,
2855 .connector_type = DRM_MODE_CONNECTOR_eDP,
2858 static const struct drm_display_mode kingdisplay_kd116n21_30nv_a010_mode = {
2861 .hsync_start = 1366 + 40,
2862 .hsync_end = 1366 + 40 + 32,
2863 .htotal = 1366 + 40 + 32 + 62,
2865 .vsync_start = 768 + 5,
2866 .vsync_end = 768 + 5 + 5,
2867 .vtotal = 768 + 5 + 5 + 122,
2868 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2871 static const struct panel_desc kingdisplay_kd116n21_30nv_a010 = {
2872 .modes = &kingdisplay_kd116n21_30nv_a010_mode,
2880 .hpd_absent_delay = 200,
2882 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2883 .connector_type = DRM_MODE_CONNECTOR_eDP,
2886 static const struct display_timing koe_tx14d24vm1bpa_timing = {
2887 .pixelclock = { 5580000, 5850000, 6200000 },
2888 .hactive = { 320, 320, 320 },
2889 .hfront_porch = { 30, 30, 30 },
2890 .hback_porch = { 30, 30, 30 },
2891 .hsync_len = { 1, 5, 17 },
2892 .vactive = { 240, 240, 240 },
2893 .vfront_porch = { 6, 6, 6 },
2894 .vback_porch = { 5, 5, 5 },
2895 .vsync_len = { 1, 2, 11 },
2896 .flags = DISPLAY_FLAGS_DE_HIGH,
2899 static const struct panel_desc koe_tx14d24vm1bpa = {
2900 .timings = &koe_tx14d24vm1bpa_timing,
2909 static const struct display_timing koe_tx26d202vm0bwa_timing = {
2910 .pixelclock = { 151820000, 156720000, 159780000 },
2911 .hactive = { 1920, 1920, 1920 },
2912 .hfront_porch = { 105, 130, 142 },
2913 .hback_porch = { 45, 70, 82 },
2914 .hsync_len = { 30, 30, 30 },
2915 .vactive = { 1200, 1200, 1200},
2916 .vfront_porch = { 3, 5, 10 },
2917 .vback_porch = { 2, 5, 10 },
2918 .vsync_len = { 5, 5, 5 },
2921 static const struct panel_desc koe_tx26d202vm0bwa = {
2922 .timings = &koe_tx26d202vm0bwa_timing,
2935 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2936 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2937 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2940 static const struct display_timing koe_tx31d200vm0baa_timing = {
2941 .pixelclock = { 39600000, 43200000, 48000000 },
2942 .hactive = { 1280, 1280, 1280 },
2943 .hfront_porch = { 16, 36, 56 },
2944 .hback_porch = { 16, 36, 56 },
2945 .hsync_len = { 8, 8, 8 },
2946 .vactive = { 480, 480, 480 },
2947 .vfront_porch = { 6, 21, 33 },
2948 .vback_porch = { 6, 21, 33 },
2949 .vsync_len = { 8, 8, 8 },
2950 .flags = DISPLAY_FLAGS_DE_HIGH,
2953 static const struct panel_desc koe_tx31d200vm0baa = {
2954 .timings = &koe_tx31d200vm0baa_timing,
2961 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2962 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2965 static const struct display_timing kyo_tcg121xglp_timing = {
2966 .pixelclock = { 52000000, 65000000, 71000000 },
2967 .hactive = { 1024, 1024, 1024 },
2968 .hfront_porch = { 2, 2, 2 },
2969 .hback_porch = { 2, 2, 2 },
2970 .hsync_len = { 86, 124, 244 },
2971 .vactive = { 768, 768, 768 },
2972 .vfront_porch = { 2, 2, 2 },
2973 .vback_porch = { 2, 2, 2 },
2974 .vsync_len = { 6, 34, 73 },
2975 .flags = DISPLAY_FLAGS_DE_HIGH,
2978 static const struct panel_desc kyo_tcg121xglp = {
2979 .timings = &kyo_tcg121xglp_timing,
2986 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2987 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2990 static const struct drm_display_mode lemaker_bl035_rgb_002_mode = {
2993 .hsync_start = 320 + 20,
2994 .hsync_end = 320 + 20 + 30,
2995 .htotal = 320 + 20 + 30 + 38,
2997 .vsync_start = 240 + 4,
2998 .vsync_end = 240 + 4 + 3,
2999 .vtotal = 240 + 4 + 3 + 15,
3002 static const struct panel_desc lemaker_bl035_rgb_002 = {
3003 .modes = &lemaker_bl035_rgb_002_mode,
3009 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3010 .bus_flags = DRM_BUS_FLAG_DE_LOW,
3013 static const struct drm_display_mode lg_lb070wv8_mode = {
3016 .hsync_start = 800 + 88,
3017 .hsync_end = 800 + 88 + 80,
3018 .htotal = 800 + 88 + 80 + 88,
3020 .vsync_start = 480 + 10,
3021 .vsync_end = 480 + 10 + 25,
3022 .vtotal = 480 + 10 + 25 + 10,
3025 static const struct panel_desc lg_lb070wv8 = {
3026 .modes = &lg_lb070wv8_mode,
3033 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3034 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3037 static const struct drm_display_mode lg_lp079qx1_sp0v_mode = {
3040 .hsync_start = 1536 + 12,
3041 .hsync_end = 1536 + 12 + 16,
3042 .htotal = 1536 + 12 + 16 + 48,
3044 .vsync_start = 2048 + 8,
3045 .vsync_end = 2048 + 8 + 4,
3046 .vtotal = 2048 + 8 + 4 + 8,
3047 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3050 static const struct panel_desc lg_lp079qx1_sp0v = {
3051 .modes = &lg_lp079qx1_sp0v_mode,
3059 static const struct drm_display_mode lg_lp097qx1_spa1_mode = {
3062 .hsync_start = 2048 + 150,
3063 .hsync_end = 2048 + 150 + 5,
3064 .htotal = 2048 + 150 + 5 + 5,
3066 .vsync_start = 1536 + 3,
3067 .vsync_end = 1536 + 3 + 1,
3068 .vtotal = 1536 + 3 + 1 + 9,
3071 static const struct panel_desc lg_lp097qx1_spa1 = {
3072 .modes = &lg_lp097qx1_spa1_mode,
3080 static const struct drm_display_mode lg_lp120up1_mode = {
3083 .hsync_start = 1920 + 40,
3084 .hsync_end = 1920 + 40 + 40,
3085 .htotal = 1920 + 40 + 40+ 80,
3087 .vsync_start = 1280 + 4,
3088 .vsync_end = 1280 + 4 + 4,
3089 .vtotal = 1280 + 4 + 4 + 12,
3092 static const struct panel_desc lg_lp120up1 = {
3093 .modes = &lg_lp120up1_mode,
3100 .connector_type = DRM_MODE_CONNECTOR_eDP,
3103 static const struct drm_display_mode lg_lp129qe_mode = {
3106 .hsync_start = 2560 + 48,
3107 .hsync_end = 2560 + 48 + 32,
3108 .htotal = 2560 + 48 + 32 + 80,
3110 .vsync_start = 1700 + 3,
3111 .vsync_end = 1700 + 3 + 10,
3112 .vtotal = 1700 + 3 + 10 + 36,
3115 static const struct panel_desc lg_lp129qe = {
3116 .modes = &lg_lp129qe_mode,
3125 static const struct display_timing logictechno_lt161010_2nh_timing = {
3126 .pixelclock = { 26400000, 33300000, 46800000 },
3127 .hactive = { 800, 800, 800 },
3128 .hfront_porch = { 16, 210, 354 },
3129 .hback_porch = { 46, 46, 46 },
3130 .hsync_len = { 1, 20, 40 },
3131 .vactive = { 480, 480, 480 },
3132 .vfront_porch = { 7, 22, 147 },
3133 .vback_porch = { 23, 23, 23 },
3134 .vsync_len = { 1, 10, 20 },
3135 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
3136 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
3137 DISPLAY_FLAGS_SYNC_POSEDGE,
3140 static const struct panel_desc logictechno_lt161010_2nh = {
3141 .timings = &logictechno_lt161010_2nh_timing,
3147 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3148 .bus_flags = DRM_BUS_FLAG_DE_HIGH |
3149 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
3150 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
3151 .connector_type = DRM_MODE_CONNECTOR_DPI,
3154 static const struct display_timing logictechno_lt170410_2whc_timing = {
3155 .pixelclock = { 68900000, 71100000, 73400000 },
3156 .hactive = { 1280, 1280, 1280 },
3157 .hfront_porch = { 23, 60, 71 },
3158 .hback_porch = { 23, 60, 71 },
3159 .hsync_len = { 15, 40, 47 },
3160 .vactive = { 800, 800, 800 },
3161 .vfront_porch = { 5, 7, 10 },
3162 .vback_porch = { 5, 7, 10 },
3163 .vsync_len = { 6, 9, 12 },
3164 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
3165 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
3166 DISPLAY_FLAGS_SYNC_POSEDGE,
3169 static const struct panel_desc logictechno_lt170410_2whc = {
3170 .timings = &logictechno_lt170410_2whc_timing,
3176 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3177 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
3178 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3181 static const struct drm_display_mode logictechno_lttd800480070_l6wh_rt_mode = {
3184 .hsync_start = 800 + 154,
3185 .hsync_end = 800 + 154 + 3,
3186 .htotal = 800 + 154 + 3 + 43,
3188 .vsync_start = 480 + 47,
3189 .vsync_end = 480 + 47 + 3,
3190 .vtotal = 480 + 47 + 3 + 20,
3191 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3194 static const struct panel_desc logictechno_lttd800480070_l6wh_rt = {
3195 .modes = &logictechno_lttd800480070_l6wh_rt_mode,
3208 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3209 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
3210 .connector_type = DRM_MODE_CONNECTOR_DPI,
3213 static const struct drm_display_mode mitsubishi_aa070mc01_mode = {
3216 .hsync_start = 800 + 0,
3217 .hsync_end = 800 + 1,
3218 .htotal = 800 + 0 + 1 + 160,
3220 .vsync_start = 480 + 0,
3221 .vsync_end = 480 + 48 + 1,
3222 .vtotal = 480 + 48 + 1 + 0,
3223 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
3226 static const struct drm_display_mode logicpd_type_28_mode = {
3229 .hsync_start = 480 + 3,
3230 .hsync_end = 480 + 3 + 42,
3231 .htotal = 480 + 3 + 42 + 2,
3234 .vsync_start = 272 + 2,
3235 .vsync_end = 272 + 2 + 11,
3236 .vtotal = 272 + 2 + 11 + 3,
3237 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
3240 static const struct panel_desc logicpd_type_28 = {
3241 .modes = &logicpd_type_28_mode,
3254 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3255 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE |
3256 DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE,
3257 .connector_type = DRM_MODE_CONNECTOR_DPI,
3260 static const struct panel_desc mitsubishi_aa070mc01 = {
3261 .modes = &mitsubishi_aa070mc01_mode,
3274 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3275 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3276 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
3279 static const struct display_timing multi_inno_mi1010ait_1cp_timing = {
3280 .pixelclock = { 68900000, 70000000, 73400000 },
3281 .hactive = { 1280, 1280, 1280 },
3282 .hfront_porch = { 30, 60, 71 },
3283 .hback_porch = { 30, 60, 71 },
3284 .hsync_len = { 10, 10, 48 },
3285 .vactive = { 800, 800, 800 },
3286 .vfront_porch = { 5, 10, 10 },
3287 .vback_porch = { 5, 10, 10 },
3288 .vsync_len = { 5, 6, 13 },
3289 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
3290 DISPLAY_FLAGS_DE_HIGH,
3293 static const struct panel_desc multi_inno_mi1010ait_1cp = {
3294 .timings = &multi_inno_mi1010ait_1cp_timing,
3305 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3306 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
3307 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3310 static const struct display_timing nec_nl12880bc20_05_timing = {
3311 .pixelclock = { 67000000, 71000000, 75000000 },
3312 .hactive = { 1280, 1280, 1280 },
3313 .hfront_porch = { 2, 30, 30 },
3314 .hback_porch = { 6, 100, 100 },
3315 .hsync_len = { 2, 30, 30 },
3316 .vactive = { 800, 800, 800 },
3317 .vfront_porch = { 5, 5, 5 },
3318 .vback_porch = { 11, 11, 11 },
3319 .vsync_len = { 7, 7, 7 },
3322 static const struct panel_desc nec_nl12880bc20_05 = {
3323 .timings = &nec_nl12880bc20_05_timing,
3334 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3335 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3338 static const struct drm_display_mode nec_nl4827hc19_05b_mode = {
3341 .hsync_start = 480 + 2,
3342 .hsync_end = 480 + 2 + 41,
3343 .htotal = 480 + 2 + 41 + 2,
3345 .vsync_start = 272 + 2,
3346 .vsync_end = 272 + 2 + 4,
3347 .vtotal = 272 + 2 + 4 + 2,
3348 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3351 static const struct panel_desc nec_nl4827hc19_05b = {
3352 .modes = &nec_nl4827hc19_05b_mode,
3359 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3360 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
3363 static const struct drm_display_mode netron_dy_e231732_mode = {
3366 .hsync_start = 1024 + 160,
3367 .hsync_end = 1024 + 160 + 70,
3368 .htotal = 1024 + 160 + 70 + 90,
3370 .vsync_start = 600 + 127,
3371 .vsync_end = 600 + 127 + 20,
3372 .vtotal = 600 + 127 + 20 + 3,
3375 static const struct panel_desc netron_dy_e231732 = {
3376 .modes = &netron_dy_e231732_mode,
3382 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3385 static const struct drm_display_mode neweast_wjfh116008a_modes[] = {
3389 .hsync_start = 1920 + 48,
3390 .hsync_end = 1920 + 48 + 32,
3391 .htotal = 1920 + 48 + 32 + 80,
3393 .vsync_start = 1080 + 3,
3394 .vsync_end = 1080 + 3 + 5,
3395 .vtotal = 1080 + 3 + 5 + 23,
3396 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3400 .hsync_start = 1920 + 48,
3401 .hsync_end = 1920 + 48 + 32,
3402 .htotal = 1920 + 48 + 32 + 80,
3404 .vsync_start = 1080 + 3,
3405 .vsync_end = 1080 + 3 + 5,
3406 .vtotal = 1080 + 3 + 5 + 23,
3407 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3411 static const struct panel_desc neweast_wjfh116008a = {
3412 .modes = neweast_wjfh116008a_modes,
3424 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3425 .connector_type = DRM_MODE_CONNECTOR_eDP,
3428 static const struct drm_display_mode newhaven_nhd_43_480272ef_atxl_mode = {
3431 .hsync_start = 480 + 2,
3432 .hsync_end = 480 + 2 + 41,
3433 .htotal = 480 + 2 + 41 + 2,
3435 .vsync_start = 272 + 2,
3436 .vsync_end = 272 + 2 + 10,
3437 .vtotal = 272 + 2 + 10 + 2,
3438 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3441 static const struct panel_desc newhaven_nhd_43_480272ef_atxl = {
3442 .modes = &newhaven_nhd_43_480272ef_atxl_mode,
3449 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3450 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE |
3451 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
3452 .connector_type = DRM_MODE_CONNECTOR_DPI,
3455 static const struct display_timing nlt_nl192108ac18_02d_timing = {
3456 .pixelclock = { 130000000, 148350000, 163000000 },
3457 .hactive = { 1920, 1920, 1920 },
3458 .hfront_porch = { 80, 100, 100 },
3459 .hback_porch = { 100, 120, 120 },
3460 .hsync_len = { 50, 60, 60 },
3461 .vactive = { 1080, 1080, 1080 },
3462 .vfront_porch = { 12, 30, 30 },
3463 .vback_porch = { 4, 10, 10 },
3464 .vsync_len = { 4, 5, 5 },
3467 static const struct panel_desc nlt_nl192108ac18_02d = {
3468 .timings = &nlt_nl192108ac18_02d_timing,
3478 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3479 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3482 static const struct drm_display_mode nvd_9128_mode = {
3485 .hsync_start = 800 + 130,
3486 .hsync_end = 800 + 130 + 98,
3487 .htotal = 800 + 0 + 130 + 98,
3489 .vsync_start = 480 + 10,
3490 .vsync_end = 480 + 10 + 50,
3491 .vtotal = 480 + 0 + 10 + 50,
3494 static const struct panel_desc nvd_9128 = {
3495 .modes = &nvd_9128_mode,
3502 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3503 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3506 static const struct display_timing okaya_rs800480t_7x0gp_timing = {
3507 .pixelclock = { 30000000, 30000000, 40000000 },
3508 .hactive = { 800, 800, 800 },
3509 .hfront_porch = { 40, 40, 40 },
3510 .hback_porch = { 40, 40, 40 },
3511 .hsync_len = { 1, 48, 48 },
3512 .vactive = { 480, 480, 480 },
3513 .vfront_porch = { 13, 13, 13 },
3514 .vback_porch = { 29, 29, 29 },
3515 .vsync_len = { 3, 3, 3 },
3516 .flags = DISPLAY_FLAGS_DE_HIGH,
3519 static const struct panel_desc okaya_rs800480t_7x0gp = {
3520 .timings = &okaya_rs800480t_7x0gp_timing,
3533 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3536 static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode = {
3539 .hsync_start = 480 + 5,
3540 .hsync_end = 480 + 5 + 30,
3541 .htotal = 480 + 5 + 30 + 10,
3543 .vsync_start = 272 + 8,
3544 .vsync_end = 272 + 8 + 5,
3545 .vtotal = 272 + 8 + 5 + 3,
3548 static const struct panel_desc olimex_lcd_olinuxino_43ts = {
3549 .modes = &olimex_lcd_olinuxino_43ts_mode,
3555 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3559 * 800x480 CVT. The panel appears to be quite accepting, at least as far as
3560 * pixel clocks, but this is the timing that was being used in the Adafruit
3561 * installation instructions.
3563 static const struct drm_display_mode ontat_yx700wv03_mode = {
3573 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3578 * https://www.adafruit.com/images/product-files/2406/c3163.pdf
3580 static const struct panel_desc ontat_yx700wv03 = {
3581 .modes = &ontat_yx700wv03_mode,
3588 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3591 static const struct drm_display_mode ortustech_com37h3m_mode = {
3594 .hsync_start = 480 + 40,
3595 .hsync_end = 480 + 40 + 10,
3596 .htotal = 480 + 40 + 10 + 40,
3598 .vsync_start = 640 + 4,
3599 .vsync_end = 640 + 4 + 2,
3600 .vtotal = 640 + 4 + 2 + 4,
3601 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3604 static const struct panel_desc ortustech_com37h3m = {
3605 .modes = &ortustech_com37h3m_mode,
3609 .width = 56, /* 56.16mm */
3610 .height = 75, /* 74.88mm */
3612 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3613 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
3614 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
3617 static const struct drm_display_mode ortustech_com43h4m85ulc_mode = {
3620 .hsync_start = 480 + 10,
3621 .hsync_end = 480 + 10 + 10,
3622 .htotal = 480 + 10 + 10 + 15,
3624 .vsync_start = 800 + 3,
3625 .vsync_end = 800 + 3 + 3,
3626 .vtotal = 800 + 3 + 3 + 3,
3629 static const struct panel_desc ortustech_com43h4m85ulc = {
3630 .modes = &ortustech_com43h4m85ulc_mode,
3637 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3638 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
3639 .connector_type = DRM_MODE_CONNECTOR_DPI,
3642 static const struct drm_display_mode osddisplays_osd070t1718_19ts_mode = {
3645 .hsync_start = 800 + 210,
3646 .hsync_end = 800 + 210 + 30,
3647 .htotal = 800 + 210 + 30 + 16,
3649 .vsync_start = 480 + 22,
3650 .vsync_end = 480 + 22 + 13,
3651 .vtotal = 480 + 22 + 13 + 10,
3652 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3655 static const struct panel_desc osddisplays_osd070t1718_19ts = {
3656 .modes = &osddisplays_osd070t1718_19ts_mode,
3663 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3664 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE |
3665 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
3666 .connector_type = DRM_MODE_CONNECTOR_DPI,
3669 static const struct drm_display_mode pda_91_00156_a0_mode = {
3672 .hsync_start = 800 + 1,
3673 .hsync_end = 800 + 1 + 64,
3674 .htotal = 800 + 1 + 64 + 64,
3676 .vsync_start = 480 + 1,
3677 .vsync_end = 480 + 1 + 23,
3678 .vtotal = 480 + 1 + 23 + 22,
3681 static const struct panel_desc pda_91_00156_a0 = {
3682 .modes = &pda_91_00156_a0_mode,
3688 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3691 static const struct drm_display_mode powertip_ph800480t013_idf02_mode = {
3694 .hsync_start = 800 + 54,
3695 .hsync_end = 800 + 54 + 2,
3696 .htotal = 800 + 54 + 2 + 44,
3698 .vsync_start = 480 + 49,
3699 .vsync_end = 480 + 49 + 2,
3700 .vtotal = 480 + 49 + 2 + 22,
3703 static const struct panel_desc powertip_ph800480t013_idf02 = {
3704 .modes = &powertip_ph800480t013_idf02_mode,
3710 .bus_flags = DRM_BUS_FLAG_DE_HIGH |
3711 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
3712 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
3713 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3714 .connector_type = DRM_MODE_CONNECTOR_DPI,
3717 static const struct drm_display_mode qd43003c0_40_mode = {
3720 .hsync_start = 480 + 8,
3721 .hsync_end = 480 + 8 + 4,
3722 .htotal = 480 + 8 + 4 + 39,
3724 .vsync_start = 272 + 4,
3725 .vsync_end = 272 + 4 + 10,
3726 .vtotal = 272 + 4 + 10 + 2,
3729 static const struct panel_desc qd43003c0_40 = {
3730 .modes = &qd43003c0_40_mode,
3737 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3740 static const struct drm_display_mode qishenglong_gopher2b_lcd_modes[] = {
3744 .hsync_start = 480 + 77,
3745 .hsync_end = 480 + 77 + 41,
3746 .htotal = 480 + 77 + 41 + 2,
3748 .vsync_start = 272 + 16,
3749 .vsync_end = 272 + 16 + 10,
3750 .vtotal = 272 + 16 + 10 + 2,
3751 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3756 .hsync_start = 480 + 17,
3757 .hsync_end = 480 + 17 + 41,
3758 .htotal = 480 + 17 + 41 + 2,
3760 .vsync_start = 272 + 116,
3761 .vsync_end = 272 + 116 + 10,
3762 .vtotal = 272 + 116 + 10 + 2,
3763 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3767 static const struct panel_desc qishenglong_gopher2b_lcd = {
3768 .modes = qishenglong_gopher2b_lcd_modes,
3769 .num_modes = ARRAY_SIZE(qishenglong_gopher2b_lcd_modes),
3775 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3776 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
3777 .connector_type = DRM_MODE_CONNECTOR_DPI,
3780 static const struct drm_display_mode raspberrypi_7inch_mode = {
3781 .clock = 25979400 / 1000,
3783 .hsync_start = 800 + 2,
3784 .hsync_end = 800 + 2 + 2,
3785 .htotal = 800 + 2 + 2 + 46,
3787 .vsync_start = 480 + 7,
3788 .vsync_end = 480 + 7 + 2,
3789 .vtotal = 480 + 7 + 2 + 21,
3790 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3793 static const struct panel_desc raspberrypi_7inch = {
3794 .modes = &raspberrypi_7inch_mode,
3801 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3802 .connector_type = DRM_MODE_CONNECTOR_DSI,
3805 static const struct display_timing rocktech_rk070er9427_timing = {
3806 .pixelclock = { 26400000, 33300000, 46800000 },
3807 .hactive = { 800, 800, 800 },
3808 .hfront_porch = { 16, 210, 354 },
3809 .hback_porch = { 46, 46, 46 },
3810 .hsync_len = { 1, 1, 1 },
3811 .vactive = { 480, 480, 480 },
3812 .vfront_porch = { 7, 22, 147 },
3813 .vback_porch = { 23, 23, 23 },
3814 .vsync_len = { 1, 1, 1 },
3815 .flags = DISPLAY_FLAGS_DE_HIGH,
3818 static const struct panel_desc rocktech_rk070er9427 = {
3819 .timings = &rocktech_rk070er9427_timing,
3832 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3835 static const struct drm_display_mode rocktech_rk101ii01d_ct_mode = {
3838 .hsync_start = 1280 + 48,
3839 .hsync_end = 1280 + 48 + 32,
3840 .htotal = 1280 + 48 + 32 + 80,
3842 .vsync_start = 800 + 2,
3843 .vsync_end = 800 + 2 + 5,
3844 .vtotal = 800 + 2 + 5 + 16,
3847 static const struct panel_desc rocktech_rk101ii01d_ct = {
3848 .modes = &rocktech_rk101ii01d_ct_mode,
3858 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
3859 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3860 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3863 static const struct drm_display_mode samsung_lsn122dl01_c01_mode = {
3866 .hsync_start = 2560 + 48,
3867 .hsync_end = 2560 + 48 + 32,
3868 .htotal = 2560 + 48 + 32 + 80,
3870 .vsync_start = 1600 + 2,
3871 .vsync_end = 1600 + 2 + 5,
3872 .vtotal = 1600 + 2 + 5 + 57,
3875 static const struct panel_desc samsung_lsn122dl01_c01 = {
3876 .modes = &samsung_lsn122dl01_c01_mode,
3884 static const struct drm_display_mode samsung_ltn101nt05_mode = {
3887 .hsync_start = 1024 + 24,
3888 .hsync_end = 1024 + 24 + 136,
3889 .htotal = 1024 + 24 + 136 + 160,
3891 .vsync_start = 600 + 3,
3892 .vsync_end = 600 + 3 + 6,
3893 .vtotal = 600 + 3 + 6 + 61,
3896 static const struct panel_desc samsung_ltn101nt05 = {
3897 .modes = &samsung_ltn101nt05_mode,
3904 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
3905 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
3906 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3909 static const struct drm_display_mode samsung_ltn140at29_301_mode = {
3912 .hsync_start = 1366 + 64,
3913 .hsync_end = 1366 + 64 + 48,
3914 .htotal = 1366 + 64 + 48 + 128,
3916 .vsync_start = 768 + 2,
3917 .vsync_end = 768 + 2 + 5,
3918 .vtotal = 768 + 2 + 5 + 17,
3921 static const struct panel_desc samsung_ltn140at29_301 = {
3922 .modes = &samsung_ltn140at29_301_mode,
3931 static const struct display_timing satoz_sat050at40h12r2_timing = {
3932 .pixelclock = {33300000, 33300000, 50000000},
3933 .hactive = {800, 800, 800},
3934 .hfront_porch = {16, 210, 354},
3935 .hback_porch = {46, 46, 46},
3936 .hsync_len = {1, 1, 40},
3937 .vactive = {480, 480, 480},
3938 .vfront_porch = {7, 22, 147},
3939 .vback_porch = {23, 23, 23},
3940 .vsync_len = {1, 1, 20},
3943 static const struct panel_desc satoz_sat050at40h12r2 = {
3944 .timings = &satoz_sat050at40h12r2_timing,
3951 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3952 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3955 static const struct drm_display_mode sharp_ld_d5116z01b_mode = {
3958 .hsync_start = 1920 + 48,
3959 .hsync_end = 1920 + 48 + 32,
3960 .htotal = 1920 + 48 + 32 + 80,
3962 .vsync_start = 1280 + 3,
3963 .vsync_end = 1280 + 3 + 10,
3964 .vtotal = 1280 + 3 + 10 + 57,
3965 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
3968 static const struct panel_desc sharp_ld_d5116z01b = {
3969 .modes = &sharp_ld_d5116z01b_mode,
3976 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3977 .bus_flags = DRM_BUS_FLAG_DATA_MSB_TO_LSB,
3980 static const struct drm_display_mode sharp_lq070y3dg3b_mode = {
3983 .hsync_start = 800 + 64,
3984 .hsync_end = 800 + 64 + 128,
3985 .htotal = 800 + 64 + 128 + 64,
3987 .vsync_start = 480 + 8,
3988 .vsync_end = 480 + 8 + 2,
3989 .vtotal = 480 + 8 + 2 + 35,
3990 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE,
3993 static const struct panel_desc sharp_lq070y3dg3b = {
3994 .modes = &sharp_lq070y3dg3b_mode,
3998 .width = 152, /* 152.4mm */
3999 .height = 91, /* 91.4mm */
4001 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
4002 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
4003 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
4006 static const struct drm_display_mode sharp_lq035q7db03_mode = {
4009 .hsync_start = 240 + 16,
4010 .hsync_end = 240 + 16 + 7,
4011 .htotal = 240 + 16 + 7 + 5,
4013 .vsync_start = 320 + 9,
4014 .vsync_end = 320 + 9 + 1,
4015 .vtotal = 320 + 9 + 1 + 7,
4018 static const struct panel_desc sharp_lq035q7db03 = {
4019 .modes = &sharp_lq035q7db03_mode,
4026 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
4029 static const struct display_timing sharp_lq101k1ly04_timing = {
4030 .pixelclock = { 60000000, 65000000, 80000000 },
4031 .hactive = { 1280, 1280, 1280 },
4032 .hfront_porch = { 20, 20, 20 },
4033 .hback_porch = { 20, 20, 20 },
4034 .hsync_len = { 10, 10, 10 },
4035 .vactive = { 800, 800, 800 },
4036 .vfront_porch = { 4, 4, 4 },
4037 .vback_porch = { 4, 4, 4 },
4038 .vsync_len = { 4, 4, 4 },
4039 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE,
4042 static const struct panel_desc sharp_lq101k1ly04 = {
4043 .timings = &sharp_lq101k1ly04_timing,
4050 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
4051 .connector_type = DRM_MODE_CONNECTOR_LVDS,
4054 static const struct display_timing sharp_lq123p1jx31_timing = {
4055 .pixelclock = { 252750000, 252750000, 266604720 },
4056 .hactive = { 2400, 2400, 2400 },
4057 .hfront_porch = { 48, 48, 48 },
4058 .hback_porch = { 80, 80, 84 },
4059 .hsync_len = { 32, 32, 32 },
4060 .vactive = { 1600, 1600, 1600 },
4061 .vfront_porch = { 3, 3, 3 },
4062 .vback_porch = { 33, 33, 120 },
4063 .vsync_len = { 10, 10, 10 },
4064 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW,
4067 static const struct panel_desc sharp_lq123p1jx31 = {
4068 .timings = &sharp_lq123p1jx31_timing,
4082 static const struct drm_display_mode sharp_ls020b1dd01d_modes[] = {
4086 .hsync_start = 240 + 58,
4087 .hsync_end = 240 + 58 + 1,
4088 .htotal = 240 + 58 + 1 + 1,
4090 .vsync_start = 160 + 24,
4091 .vsync_end = 160 + 24 + 10,
4092 .vtotal = 160 + 24 + 10 + 6,
4093 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC,
4098 .hsync_start = 240 + 8,
4099 .hsync_end = 240 + 8 + 1,
4100 .htotal = 240 + 8 + 1 + 1,
4102 .vsync_start = 160 + 24,
4103 .vsync_end = 160 + 24 + 10,
4104 .vtotal = 160 + 24 + 10 + 6,
4105 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC,
4109 static const struct panel_desc sharp_ls020b1dd01d = {
4110 .modes = sharp_ls020b1dd01d_modes,
4111 .num_modes = ARRAY_SIZE(sharp_ls020b1dd01d_modes),
4117 .bus_format = MEDIA_BUS_FMT_RGB565_1X16,
4118 .bus_flags = DRM_BUS_FLAG_DE_HIGH
4119 | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE
4120 | DRM_BUS_FLAG_SHARP_SIGNALS,
4123 static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = {
4126 .hsync_start = 800 + 1,
4127 .hsync_end = 800 + 1 + 64,
4128 .htotal = 800 + 1 + 64 + 64,
4130 .vsync_start = 480 + 1,
4131 .vsync_end = 480 + 1 + 23,
4132 .vtotal = 480 + 1 + 23 + 22,
4135 static const struct panel_desc shelly_sca07010_bfn_lnn = {
4136 .modes = &shelly_sca07010_bfn_lnn_mode,
4142 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
4145 static const struct drm_display_mode starry_kr070pe2t_mode = {
4148 .hsync_start = 800 + 209,
4149 .hsync_end = 800 + 209 + 1,
4150 .htotal = 800 + 209 + 1 + 45,
4152 .vsync_start = 480 + 22,
4153 .vsync_end = 480 + 22 + 1,
4154 .vtotal = 480 + 22 + 1 + 22,
4157 static const struct panel_desc starry_kr070pe2t = {
4158 .modes = &starry_kr070pe2t_mode,
4165 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
4166 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
4167 .connector_type = DRM_MODE_CONNECTOR_DPI,
4170 static const struct drm_display_mode starry_kr122ea0sra_mode = {
4173 .hsync_start = 1920 + 16,
4174 .hsync_end = 1920 + 16 + 16,
4175 .htotal = 1920 + 16 + 16 + 32,
4177 .vsync_start = 1200 + 15,
4178 .vsync_end = 1200 + 15 + 2,
4179 .vtotal = 1200 + 15 + 2 + 18,
4180 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
4183 static const struct panel_desc starry_kr122ea0sra = {
4184 .modes = &starry_kr122ea0sra_mode,
4191 .prepare = 10 + 200,
4193 .unprepare = 10 + 500,
4197 static const struct drm_display_mode tfc_s9700rtwv43tr_01b_mode = {
4200 .hsync_start = 800 + 39,
4201 .hsync_end = 800 + 39 + 47,
4202 .htotal = 800 + 39 + 47 + 39,
4204 .vsync_start = 480 + 13,
4205 .vsync_end = 480 + 13 + 2,
4206 .vtotal = 480 + 13 + 2 + 29,
4209 static const struct panel_desc tfc_s9700rtwv43tr_01b = {
4210 .modes = &tfc_s9700rtwv43tr_01b_mode,
4217 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
4218 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
4221 static const struct display_timing tianma_tm070jdhg30_timing = {
4222 .pixelclock = { 62600000, 68200000, 78100000 },
4223 .hactive = { 1280, 1280, 1280 },
4224 .hfront_porch = { 15, 64, 159 },
4225 .hback_porch = { 5, 5, 5 },
4226 .hsync_len = { 1, 1, 256 },
4227 .vactive = { 800, 800, 800 },
4228 .vfront_porch = { 3, 40, 99 },
4229 .vback_porch = { 2, 2, 2 },
4230 .vsync_len = { 1, 1, 128 },
4231 .flags = DISPLAY_FLAGS_DE_HIGH,
4234 static const struct panel_desc tianma_tm070jdhg30 = {
4235 .timings = &tianma_tm070jdhg30_timing,
4242 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
4243 .connector_type = DRM_MODE_CONNECTOR_LVDS,
4246 static const struct panel_desc tianma_tm070jvhg33 = {
4247 .timings = &tianma_tm070jdhg30_timing,
4254 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
4255 .connector_type = DRM_MODE_CONNECTOR_LVDS,
4258 static const struct display_timing tianma_tm070rvhg71_timing = {
4259 .pixelclock = { 27700000, 29200000, 39600000 },
4260 .hactive = { 800, 800, 800 },
4261 .hfront_porch = { 12, 40, 212 },
4262 .hback_porch = { 88, 88, 88 },
4263 .hsync_len = { 1, 1, 40 },
4264 .vactive = { 480, 480, 480 },
4265 .vfront_porch = { 1, 13, 88 },
4266 .vback_porch = { 32, 32, 32 },
4267 .vsync_len = { 1, 1, 3 },
4268 .flags = DISPLAY_FLAGS_DE_HIGH,
4271 static const struct panel_desc tianma_tm070rvhg71 = {
4272 .timings = &tianma_tm070rvhg71_timing,
4279 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
4280 .connector_type = DRM_MODE_CONNECTOR_LVDS,
4283 static const struct drm_display_mode ti_nspire_cx_lcd_mode[] = {
4287 .hsync_start = 320 + 50,
4288 .hsync_end = 320 + 50 + 6,
4289 .htotal = 320 + 50 + 6 + 38,
4291 .vsync_start = 240 + 3,
4292 .vsync_end = 240 + 3 + 1,
4293 .vtotal = 240 + 3 + 1 + 17,
4294 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
4298 static const struct panel_desc ti_nspire_cx_lcd_panel = {
4299 .modes = ti_nspire_cx_lcd_mode,
4306 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
4307 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
4310 static const struct drm_display_mode ti_nspire_classic_lcd_mode[] = {
4314 .hsync_start = 320 + 6,
4315 .hsync_end = 320 + 6 + 6,
4316 .htotal = 320 + 6 + 6 + 6,
4318 .vsync_start = 240 + 0,
4319 .vsync_end = 240 + 0 + 1,
4320 .vtotal = 240 + 0 + 1 + 0,
4321 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
4325 static const struct panel_desc ti_nspire_classic_lcd_panel = {
4326 .modes = ti_nspire_classic_lcd_mode,
4328 /* The grayscale panel has 8 bit for the color .. Y (black) */
4334 /* This is the grayscale bus format */
4335 .bus_format = MEDIA_BUS_FMT_Y8_1X8,
4336 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
4339 static const struct drm_display_mode toshiba_lt089ac29000_mode = {
4342 .hsync_start = 1280 + 192,
4343 .hsync_end = 1280 + 192 + 128,
4344 .htotal = 1280 + 192 + 128 + 64,
4346 .vsync_start = 768 + 20,
4347 .vsync_end = 768 + 20 + 7,
4348 .vtotal = 768 + 20 + 7 + 3,
4351 static const struct panel_desc toshiba_lt089ac29000 = {
4352 .modes = &toshiba_lt089ac29000_mode,
4358 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
4359 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
4360 .connector_type = DRM_MODE_CONNECTOR_LVDS,
4363 static const struct drm_display_mode tpk_f07a_0102_mode = {
4366 .hsync_start = 800 + 40,
4367 .hsync_end = 800 + 40 + 128,
4368 .htotal = 800 + 40 + 128 + 88,
4370 .vsync_start = 480 + 10,
4371 .vsync_end = 480 + 10 + 2,
4372 .vtotal = 480 + 10 + 2 + 33,
4375 static const struct panel_desc tpk_f07a_0102 = {
4376 .modes = &tpk_f07a_0102_mode,
4382 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
4385 static const struct drm_display_mode tpk_f10a_0102_mode = {
4388 .hsync_start = 1024 + 176,
4389 .hsync_end = 1024 + 176 + 5,
4390 .htotal = 1024 + 176 + 5 + 88,
4392 .vsync_start = 600 + 20,
4393 .vsync_end = 600 + 20 + 5,
4394 .vtotal = 600 + 20 + 5 + 25,
4397 static const struct panel_desc tpk_f10a_0102 = {
4398 .modes = &tpk_f10a_0102_mode,
4406 static const struct display_timing urt_umsh_8596md_timing = {
4407 .pixelclock = { 33260000, 33260000, 33260000 },
4408 .hactive = { 800, 800, 800 },
4409 .hfront_porch = { 41, 41, 41 },
4410 .hback_porch = { 216 - 128, 216 - 128, 216 - 128 },
4411 .hsync_len = { 71, 128, 128 },
4412 .vactive = { 480, 480, 480 },
4413 .vfront_porch = { 10, 10, 10 },
4414 .vback_porch = { 35 - 2, 35 - 2, 35 - 2 },
4415 .vsync_len = { 2, 2, 2 },
4416 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE |
4417 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
4420 static const struct panel_desc urt_umsh_8596md_lvds = {
4421 .timings = &urt_umsh_8596md_timing,
4428 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
4429 .connector_type = DRM_MODE_CONNECTOR_LVDS,
4432 static const struct panel_desc urt_umsh_8596md_parallel = {
4433 .timings = &urt_umsh_8596md_timing,
4440 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
4443 static const struct drm_display_mode vl050_8048nt_c01_mode = {
4446 .hsync_start = 800 + 210,
4447 .hsync_end = 800 + 210 + 20,
4448 .htotal = 800 + 210 + 20 + 46,
4450 .vsync_start = 480 + 22,
4451 .vsync_end = 480 + 22 + 10,
4452 .vtotal = 480 + 22 + 10 + 23,
4453 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
4456 static const struct panel_desc vl050_8048nt_c01 = {
4457 .modes = &vl050_8048nt_c01_mode,
4464 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
4465 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
4468 static const struct drm_display_mode winstar_wf35ltiacd_mode = {
4471 .hsync_start = 320 + 20,
4472 .hsync_end = 320 + 20 + 30,
4473 .htotal = 320 + 20 + 30 + 38,
4475 .vsync_start = 240 + 4,
4476 .vsync_end = 240 + 4 + 3,
4477 .vtotal = 240 + 4 + 3 + 15,
4478 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
4481 static const struct panel_desc winstar_wf35ltiacd = {
4482 .modes = &winstar_wf35ltiacd_mode,
4489 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
4492 static const struct drm_display_mode yes_optoelectronics_ytc700tlag_05_201c_mode = {
4495 .hsync_start = 1024 + 100,
4496 .hsync_end = 1024 + 100 + 100,
4497 .htotal = 1024 + 100 + 100 + 120,
4499 .vsync_start = 600 + 10,
4500 .vsync_end = 600 + 10 + 10,
4501 .vtotal = 600 + 10 + 10 + 15,
4502 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
4505 static const struct panel_desc yes_optoelectronics_ytc700tlag_05_201c = {
4506 .modes = &yes_optoelectronics_ytc700tlag_05_201c_mode,
4513 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
4514 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
4515 .connector_type = DRM_MODE_CONNECTOR_LVDS,
4518 static const struct drm_display_mode arm_rtsm_mode[] = {
4522 .hsync_start = 1024 + 24,
4523 .hsync_end = 1024 + 24 + 136,
4524 .htotal = 1024 + 24 + 136 + 160,
4526 .vsync_start = 768 + 3,
4527 .vsync_end = 768 + 3 + 6,
4528 .vtotal = 768 + 3 + 6 + 29,
4529 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
4533 static const struct panel_desc arm_rtsm = {
4534 .modes = arm_rtsm_mode,
4541 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
4544 static const struct of_device_id platform_of_match[] = {
4546 .compatible = "ampire,am-1280800n3tzqw-t00h",
4547 .data = &ire_am_1280800n3tzqw_t00h,
4549 .compatible = "ampire,am-480272h3tmqw-t01h",
4550 .data = &ire_am_480272h3tmqw_t01h,
4552 .compatible = "ampire,am800480r3tmqwa1h",
4553 .data = &ire_am800480r3tmqwa1h,
4555 .compatible = "arm,rtsm-display",
4558 .compatible = "armadeus,st0700-adapt",
4559 .data = &armadeus_st0700_adapt,
4561 .compatible = "auo,b101aw03",
4562 .data = &auo_b101aw03,
4564 .compatible = "auo,b101ean01",
4565 .data = &auo_b101ean01,
4567 .compatible = "auo,b101xtn01",
4568 .data = &auo_b101xtn01,
4570 .compatible = "auo,b116xa01",
4571 .data = &auo_b116xak01,
4573 .compatible = "auo,b116xw03",
4574 .data = &auo_b116xw03,
4576 .compatible = "auo,b133han05",
4577 .data = &auo_b133han05,
4579 .compatible = "auo,b133htn01",
4580 .data = &auo_b133htn01,
4582 .compatible = "auo,b140han06",
4583 .data = &auo_b140han06,
4585 .compatible = "auo,b133xtn01",
4586 .data = &auo_b133xtn01,
4588 .compatible = "auo,g070vvn01",
4589 .data = &auo_g070vvn01,
4591 .compatible = "auo,g101evn010",
4592 .data = &auo_g101evn010,
4594 .compatible = "auo,g104sn02",
4595 .data = &auo_g104sn02,
4597 .compatible = "auo,g121ean01",
4598 .data = &auo_g121ean01,
4600 .compatible = "auo,g133han01",
4601 .data = &auo_g133han01,
4603 .compatible = "auo,g156xtn01",
4604 .data = &auo_g156xtn01,
4606 .compatible = "auo,g185han01",
4607 .data = &auo_g185han01,
4609 .compatible = "auo,g190ean01",
4610 .data = &auo_g190ean01,
4612 .compatible = "auo,p320hvn03",
4613 .data = &auo_p320hvn03,
4615 .compatible = "auo,t215hvn01",
4616 .data = &auo_t215hvn01,
4618 .compatible = "avic,tm070ddh03",
4619 .data = &avic_tm070ddh03,
4621 .compatible = "bananapi,s070wv20-ct16",
4622 .data = &bananapi_s070wv20_ct16,
4624 .compatible = "boe,hv070wsa-100",
4625 .data = &boe_hv070wsa
4627 .compatible = "boe,nv101wxmn51",
4628 .data = &boe_nv101wxmn51,
4630 .compatible = "boe,nv110wtm-n61",
4631 .data = &boe_nv110wtm_n61,
4633 .compatible = "boe,nv133fhm-n61",
4634 .data = &boe_nv133fhm_n61,
4636 .compatible = "boe,nv133fhm-n62",
4637 .data = &boe_nv133fhm_n61,
4639 .compatible = "boe,nv140fhmn49",
4640 .data = &boe_nv140fhmn49,
4642 .compatible = "cdtech,s043wq26h-ct7",
4643 .data = &cdtech_s043wq26h_ct7,
4645 .compatible = "cdtech,s070pws19hp-fc21",
4646 .data = &cdtech_s070pws19hp_fc21,
4648 .compatible = "cdtech,s070swv29hg-dc44",
4649 .data = &cdtech_s070swv29hg_dc44,
4651 .compatible = "cdtech,s070wv95-ct16",
4652 .data = &cdtech_s070wv95_ct16,
4654 .compatible = "chefree,ch101olhlwh-002",
4655 .data = &chefree_ch101olhlwh_002,
4657 .compatible = "chunghwa,claa070wp03xg",
4658 .data = &chunghwa_claa070wp03xg,
4660 .compatible = "chunghwa,claa101wa01a",
4661 .data = &chunghwa_claa101wa01a
4663 .compatible = "chunghwa,claa101wb01",
4664 .data = &chunghwa_claa101wb01
4666 .compatible = "dataimage,scf0700c48ggu18",
4667 .data = &dataimage_scf0700c48ggu18,
4669 .compatible = "dlc,dlc0700yzg-1",
4670 .data = &dlc_dlc0700yzg_1,
4672 .compatible = "dlc,dlc1010gig",
4673 .data = &dlc_dlc1010gig,
4675 .compatible = "edt,et035012dm6",
4676 .data = &edt_et035012dm6,
4678 .compatible = "edt,etm0350g0dh6",
4679 .data = &edt_etm0350g0dh6,
4681 .compatible = "edt,etm043080dh6gp",
4682 .data = &edt_etm043080dh6gp,
4684 .compatible = "edt,etm0430g0dh6",
4685 .data = &edt_etm0430g0dh6,
4687 .compatible = "edt,et057090dhu",
4688 .data = &edt_et057090dhu,
4690 .compatible = "edt,et070080dh6",
4691 .data = &edt_etm0700g0dh6,
4693 .compatible = "edt,etm0700g0dh6",
4694 .data = &edt_etm0700g0dh6,
4696 .compatible = "edt,etm0700g0bdh6",
4697 .data = &edt_etm0700g0bdh6,
4699 .compatible = "edt,etm0700g0edh6",
4700 .data = &edt_etm0700g0bdh6,
4702 .compatible = "edt,etmv570g2dhu",
4703 .data = &edt_etmv570g2dhu,
4705 .compatible = "eink,vb3300-kca",
4706 .data = &eink_vb3300_kca,
4708 .compatible = "evervision,vgg804821",
4709 .data = &evervision_vgg804821,
4711 .compatible = "foxlink,fl500wvr00-a0t",
4712 .data = &foxlink_fl500wvr00_a0t,
4714 .compatible = "frida,frd350h54004",
4715 .data = &frida_frd350h54004,
4717 .compatible = "friendlyarm,hd702e",
4718 .data = &friendlyarm_hd702e,
4720 .compatible = "geekworm,mzp280",
4721 .data = &geekworm_mzp280,
4723 .compatible = "giantplus,gpg482739qs5",
4724 .data = &giantplus_gpg482739qs5
4726 .compatible = "giantplus,gpm940b0",
4727 .data = &giantplus_gpm940b0,
4729 .compatible = "hannstar,hsd070pww1",
4730 .data = &hannstar_hsd070pww1,
4732 .compatible = "hannstar,hsd100pxn1",
4733 .data = &hannstar_hsd100pxn1,
4735 .compatible = "hit,tx23d38vm0caa",
4736 .data = &hitachi_tx23d38vm0caa
4738 .compatible = "innolux,at043tn24",
4739 .data = &innolux_at043tn24,
4741 .compatible = "innolux,at056tn53v1",
4742 .data = &innolux_at056tn53v1,
4744 .compatible = "innolux,at070tn92",
4745 .data = &innolux_at070tn92,
4747 .compatible = "innolux,g070y2-l01",
4748 .data = &innolux_g070y2_l01,
4750 .compatible = "innolux,g101ice-l01",
4751 .data = &innolux_g101ice_l01
4753 .compatible = "innolux,g121i1-l01",
4754 .data = &innolux_g121i1_l01
4756 .compatible = "innolux,g121x1-l03",
4757 .data = &innolux_g121x1_l03,
4759 .compatible = "innolux,n116bca-ea1",
4760 .data = &innolux_n116bca_ea1,
4762 .compatible = "innolux,n116bge",
4763 .data = &innolux_n116bge,
4765 .compatible = "innolux,n125hce-gn1",
4766 .data = &innolux_n125hce_gn1,
4768 .compatible = "innolux,n156bge-l21",
4769 .data = &innolux_n156bge_l21,
4771 .compatible = "innolux,p120zdg-bf1",
4772 .data = &innolux_p120zdg_bf1,
4774 .compatible = "innolux,zj070na-01p",
4775 .data = &innolux_zj070na_01p,
4777 .compatible = "ivo,m133nwf4-r0",
4778 .data = &ivo_m133nwf4_r0,
4780 .compatible = "kingdisplay,kd116n21-30nv-a010",
4781 .data = &kingdisplay_kd116n21_30nv_a010,
4783 .compatible = "koe,tx14d24vm1bpa",
4784 .data = &koe_tx14d24vm1bpa,
4786 .compatible = "koe,tx26d202vm0bwa",
4787 .data = &koe_tx26d202vm0bwa,
4789 .compatible = "koe,tx31d200vm0baa",
4790 .data = &koe_tx31d200vm0baa,
4792 .compatible = "kyo,tcg121xglp",
4793 .data = &kyo_tcg121xglp,
4795 .compatible = "lemaker,bl035-rgb-002",
4796 .data = &lemaker_bl035_rgb_002,
4798 .compatible = "lg,lb070wv8",
4799 .data = &lg_lb070wv8,
4801 .compatible = "lg,lp079qx1-sp0v",
4802 .data = &lg_lp079qx1_sp0v,
4804 .compatible = "lg,lp097qx1-spa1",
4805 .data = &lg_lp097qx1_spa1,
4807 .compatible = "lg,lp120up1",
4808 .data = &lg_lp120up1,
4810 .compatible = "lg,lp129qe",
4811 .data = &lg_lp129qe,
4813 .compatible = "logicpd,type28",
4814 .data = &logicpd_type_28,
4816 .compatible = "logictechno,lt161010-2nhc",
4817 .data = &logictechno_lt161010_2nh,
4819 .compatible = "logictechno,lt161010-2nhr",
4820 .data = &logictechno_lt161010_2nh,
4822 .compatible = "logictechno,lt170410-2whc",
4823 .data = &logictechno_lt170410_2whc,
4825 .compatible = "logictechno,lttd800480070-l6wh-rt",
4826 .data = &logictechno_lttd800480070_l6wh_rt,
4828 .compatible = "mitsubishi,aa070mc01-ca1",
4829 .data = &mitsubishi_aa070mc01,
4831 .compatible = "multi-inno,mi1010ait-1cp",
4832 .data = &multi_inno_mi1010ait_1cp,
4834 .compatible = "nec,nl12880bc20-05",
4835 .data = &nec_nl12880bc20_05,
4837 .compatible = "nec,nl4827hc19-05b",
4838 .data = &nec_nl4827hc19_05b,
4840 .compatible = "netron-dy,e231732",
4841 .data = &netron_dy_e231732,
4843 .compatible = "neweast,wjfh116008a",
4844 .data = &neweast_wjfh116008a,
4846 .compatible = "newhaven,nhd-4.3-480272ef-atxl",
4847 .data = &newhaven_nhd_43_480272ef_atxl,
4849 .compatible = "nlt,nl192108ac18-02d",
4850 .data = &nlt_nl192108ac18_02d,
4852 .compatible = "nvd,9128",
4855 .compatible = "okaya,rs800480t-7x0gp",
4856 .data = &okaya_rs800480t_7x0gp,
4858 .compatible = "olimex,lcd-olinuxino-43-ts",
4859 .data = &olimex_lcd_olinuxino_43ts,
4861 .compatible = "ontat,yx700wv03",
4862 .data = &ontat_yx700wv03,
4864 .compatible = "ortustech,com37h3m05dtc",
4865 .data = &ortustech_com37h3m,
4867 .compatible = "ortustech,com37h3m99dtc",
4868 .data = &ortustech_com37h3m,
4870 .compatible = "ortustech,com43h4m85ulc",
4871 .data = &ortustech_com43h4m85ulc,
4873 .compatible = "osddisplays,osd070t1718-19ts",
4874 .data = &osddisplays_osd070t1718_19ts,
4876 .compatible = "pda,91-00156-a0",
4877 .data = &pda_91_00156_a0,
4879 .compatible = "powertip,ph800480t013-idf02",
4880 .data = &powertip_ph800480t013_idf02,
4882 .compatible = "qiaodian,qd43003c0-40",
4883 .data = &qd43003c0_40,
4885 .compatible = "qishenglong,gopher2b-lcd",
4886 .data = &qishenglong_gopher2b_lcd,
4888 .compatible = "raspberrypi,7inch-dsi",
4889 .data = &raspberrypi_7inch,
4891 .compatible = "rocktech,rk070er9427",
4892 .data = &rocktech_rk070er9427,
4894 .compatible = "rocktech,rk101ii01d-ct",
4895 .data = &rocktech_rk101ii01d_ct,
4897 .compatible = "samsung,lsn122dl01-c01",
4898 .data = &samsung_lsn122dl01_c01,
4900 .compatible = "samsung,ltn101nt05",
4901 .data = &samsung_ltn101nt05,
4903 .compatible = "samsung,ltn140at29-301",
4904 .data = &samsung_ltn140at29_301,
4906 .compatible = "satoz,sat050at40h12r2",
4907 .data = &satoz_sat050at40h12r2,
4909 .compatible = "sharp,ld-d5116z01b",
4910 .data = &sharp_ld_d5116z01b,
4912 .compatible = "sharp,lq035q7db03",
4913 .data = &sharp_lq035q7db03,
4915 .compatible = "sharp,lq070y3dg3b",
4916 .data = &sharp_lq070y3dg3b,
4918 .compatible = "sharp,lq101k1ly04",
4919 .data = &sharp_lq101k1ly04,
4921 .compatible = "sharp,lq123p1jx31",
4922 .data = &sharp_lq123p1jx31,
4924 .compatible = "sharp,ls020b1dd01d",
4925 .data = &sharp_ls020b1dd01d,
4927 .compatible = "shelly,sca07010-bfn-lnn",
4928 .data = &shelly_sca07010_bfn_lnn,
4930 .compatible = "starry,kr070pe2t",
4931 .data = &starry_kr070pe2t,
4933 .compatible = "starry,kr122ea0sra",
4934 .data = &starry_kr122ea0sra,
4936 .compatible = "tfc,s9700rtwv43tr-01b",
4937 .data = &tfc_s9700rtwv43tr_01b,
4939 .compatible = "tianma,tm070jdhg30",
4940 .data = &tianma_tm070jdhg30,
4942 .compatible = "tianma,tm070jvhg33",
4943 .data = &tianma_tm070jvhg33,
4945 .compatible = "tianma,tm070rvhg71",
4946 .data = &tianma_tm070rvhg71,
4948 .compatible = "ti,nspire-cx-lcd-panel",
4949 .data = &ti_nspire_cx_lcd_panel,
4951 .compatible = "ti,nspire-classic-lcd-panel",
4952 .data = &ti_nspire_classic_lcd_panel,
4954 .compatible = "toshiba,lt089ac29000",
4955 .data = &toshiba_lt089ac29000,
4957 .compatible = "tpk,f07a-0102",
4958 .data = &tpk_f07a_0102,
4960 .compatible = "tpk,f10a-0102",
4961 .data = &tpk_f10a_0102,
4963 .compatible = "urt,umsh-8596md-t",
4964 .data = &urt_umsh_8596md_parallel,
4966 .compatible = "urt,umsh-8596md-1t",
4967 .data = &urt_umsh_8596md_parallel,
4969 .compatible = "urt,umsh-8596md-7t",
4970 .data = &urt_umsh_8596md_parallel,
4972 .compatible = "urt,umsh-8596md-11t",
4973 .data = &urt_umsh_8596md_lvds,
4975 .compatible = "urt,umsh-8596md-19t",
4976 .data = &urt_umsh_8596md_lvds,
4978 .compatible = "urt,umsh-8596md-20t",
4979 .data = &urt_umsh_8596md_parallel,
4981 .compatible = "vxt,vl050-8048nt-c01",
4982 .data = &vl050_8048nt_c01,
4984 .compatible = "winstar,wf35ltiacd",
4985 .data = &winstar_wf35ltiacd,
4987 .compatible = "yes-optoelectronics,ytc700tlag-05-201c",
4988 .data = &yes_optoelectronics_ytc700tlag_05_201c,
4990 /* Must be the last entry */
4991 .compatible = "panel-dpi",
4997 MODULE_DEVICE_TABLE(of, platform_of_match);
4999 static int panel_simple_platform_probe(struct platform_device *pdev)
5001 const struct of_device_id *id;
5003 id = of_match_node(platform_of_match, pdev->dev.of_node);
5007 return panel_simple_probe(&pdev->dev, id->data, NULL);
5010 static int panel_simple_platform_remove(struct platform_device *pdev)
5012 return panel_simple_remove(&pdev->dev);
5015 static void panel_simple_platform_shutdown(struct platform_device *pdev)
5017 panel_simple_shutdown(&pdev->dev);
5020 static const struct dev_pm_ops panel_simple_pm_ops = {
5021 SET_RUNTIME_PM_OPS(panel_simple_suspend, panel_simple_resume, NULL)
5022 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
5023 pm_runtime_force_resume)
5026 static struct platform_driver panel_simple_platform_driver = {
5028 .name = "panel-simple",
5029 .of_match_table = platform_of_match,
5030 .pm = &panel_simple_pm_ops,
5032 .probe = panel_simple_platform_probe,
5033 .remove = panel_simple_platform_remove,
5034 .shutdown = panel_simple_platform_shutdown,
5037 struct panel_desc_dsi {
5038 struct panel_desc desc;
5040 unsigned long flags;
5041 enum mipi_dsi_pixel_format format;
5045 static const struct drm_display_mode auo_b080uan01_mode = {
5048 .hsync_start = 1200 + 62,
5049 .hsync_end = 1200 + 62 + 4,
5050 .htotal = 1200 + 62 + 4 + 62,
5052 .vsync_start = 1920 + 9,
5053 .vsync_end = 1920 + 9 + 2,
5054 .vtotal = 1920 + 9 + 2 + 8,
5057 static const struct panel_desc_dsi auo_b080uan01 = {
5059 .modes = &auo_b080uan01_mode,
5066 .connector_type = DRM_MODE_CONNECTOR_DSI,
5068 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
5069 .format = MIPI_DSI_FMT_RGB888,
5073 static const struct drm_display_mode boe_tv080wum_nl0_mode = {
5076 .hsync_start = 1200 + 120,
5077 .hsync_end = 1200 + 120 + 20,
5078 .htotal = 1200 + 120 + 20 + 21,
5080 .vsync_start = 1920 + 21,
5081 .vsync_end = 1920 + 21 + 3,
5082 .vtotal = 1920 + 21 + 3 + 18,
5083 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
5086 static const struct panel_desc_dsi boe_tv080wum_nl0 = {
5088 .modes = &boe_tv080wum_nl0_mode,
5094 .connector_type = DRM_MODE_CONNECTOR_DSI,
5096 .flags = MIPI_DSI_MODE_VIDEO |
5097 MIPI_DSI_MODE_VIDEO_BURST |
5098 MIPI_DSI_MODE_VIDEO_SYNC_PULSE,
5099 .format = MIPI_DSI_FMT_RGB888,
5103 static const struct drm_display_mode lg_ld070wx3_sl01_mode = {
5106 .hsync_start = 800 + 32,
5107 .hsync_end = 800 + 32 + 1,
5108 .htotal = 800 + 32 + 1 + 57,
5110 .vsync_start = 1280 + 28,
5111 .vsync_end = 1280 + 28 + 1,
5112 .vtotal = 1280 + 28 + 1 + 14,
5115 static const struct panel_desc_dsi lg_ld070wx3_sl01 = {
5117 .modes = &lg_ld070wx3_sl01_mode,
5124 .connector_type = DRM_MODE_CONNECTOR_DSI,
5126 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
5127 .format = MIPI_DSI_FMT_RGB888,
5131 static const struct drm_display_mode lg_lh500wx1_sd03_mode = {
5134 .hsync_start = 720 + 12,
5135 .hsync_end = 720 + 12 + 4,
5136 .htotal = 720 + 12 + 4 + 112,
5138 .vsync_start = 1280 + 8,
5139 .vsync_end = 1280 + 8 + 4,
5140 .vtotal = 1280 + 8 + 4 + 12,
5143 static const struct panel_desc_dsi lg_lh500wx1_sd03 = {
5145 .modes = &lg_lh500wx1_sd03_mode,
5152 .connector_type = DRM_MODE_CONNECTOR_DSI,
5154 .flags = MIPI_DSI_MODE_VIDEO,
5155 .format = MIPI_DSI_FMT_RGB888,
5159 static const struct drm_display_mode panasonic_vvx10f004b00_mode = {
5162 .hsync_start = 1920 + 154,
5163 .hsync_end = 1920 + 154 + 16,
5164 .htotal = 1920 + 154 + 16 + 32,
5166 .vsync_start = 1200 + 17,
5167 .vsync_end = 1200 + 17 + 2,
5168 .vtotal = 1200 + 17 + 2 + 16,
5171 static const struct panel_desc_dsi panasonic_vvx10f004b00 = {
5173 .modes = &panasonic_vvx10f004b00_mode,
5180 .connector_type = DRM_MODE_CONNECTOR_DSI,
5182 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
5183 MIPI_DSI_CLOCK_NON_CONTINUOUS,
5184 .format = MIPI_DSI_FMT_RGB888,
5188 static const struct drm_display_mode lg_acx467akm_7_mode = {
5191 .hsync_start = 1080 + 2,
5192 .hsync_end = 1080 + 2 + 2,
5193 .htotal = 1080 + 2 + 2 + 2,
5195 .vsync_start = 1920 + 2,
5196 .vsync_end = 1920 + 2 + 2,
5197 .vtotal = 1920 + 2 + 2 + 2,
5200 static const struct panel_desc_dsi lg_acx467akm_7 = {
5202 .modes = &lg_acx467akm_7_mode,
5209 .connector_type = DRM_MODE_CONNECTOR_DSI,
5212 .format = MIPI_DSI_FMT_RGB888,
5216 static const struct drm_display_mode osd101t2045_53ts_mode = {
5219 .hsync_start = 1920 + 112,
5220 .hsync_end = 1920 + 112 + 16,
5221 .htotal = 1920 + 112 + 16 + 32,
5223 .vsync_start = 1200 + 16,
5224 .vsync_end = 1200 + 16 + 2,
5225 .vtotal = 1200 + 16 + 2 + 16,
5226 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
5229 static const struct panel_desc_dsi osd101t2045_53ts = {
5231 .modes = &osd101t2045_53ts_mode,
5238 .connector_type = DRM_MODE_CONNECTOR_DSI,
5240 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
5241 MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
5242 MIPI_DSI_MODE_NO_EOT_PACKET,
5243 .format = MIPI_DSI_FMT_RGB888,
5247 static const struct of_device_id dsi_of_match[] = {
5249 .compatible = "auo,b080uan01",
5250 .data = &auo_b080uan01
5252 .compatible = "boe,tv080wum-nl0",
5253 .data = &boe_tv080wum_nl0
5255 .compatible = "lg,ld070wx3-sl01",
5256 .data = &lg_ld070wx3_sl01
5258 .compatible = "lg,lh500wx1-sd03",
5259 .data = &lg_lh500wx1_sd03
5261 .compatible = "panasonic,vvx10f004b00",
5262 .data = &panasonic_vvx10f004b00
5264 .compatible = "lg,acx467akm-7",
5265 .data = &lg_acx467akm_7
5267 .compatible = "osddisplays,osd101t2045-53ts",
5268 .data = &osd101t2045_53ts
5273 MODULE_DEVICE_TABLE(of, dsi_of_match);
5275 static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi)
5277 const struct panel_desc_dsi *desc;
5278 const struct of_device_id *id;
5281 id = of_match_node(dsi_of_match, dsi->dev.of_node);
5287 err = panel_simple_probe(&dsi->dev, &desc->desc, NULL);
5291 dsi->mode_flags = desc->flags;
5292 dsi->format = desc->format;
5293 dsi->lanes = desc->lanes;
5295 err = mipi_dsi_attach(dsi);
5297 struct panel_simple *panel = mipi_dsi_get_drvdata(dsi);
5299 drm_panel_remove(&panel->base);
5305 static int panel_simple_dsi_remove(struct mipi_dsi_device *dsi)
5309 err = mipi_dsi_detach(dsi);
5311 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err);
5313 return panel_simple_remove(&dsi->dev);
5316 static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi)
5318 panel_simple_shutdown(&dsi->dev);
5321 static struct mipi_dsi_driver panel_simple_dsi_driver = {
5323 .name = "panel-simple-dsi",
5324 .of_match_table = dsi_of_match,
5325 .pm = &panel_simple_pm_ops,
5327 .probe = panel_simple_dsi_probe,
5328 .remove = panel_simple_dsi_remove,
5329 .shutdown = panel_simple_dsi_shutdown,
5332 static int panel_simple_dp_aux_ep_probe(struct dp_aux_ep_device *aux_ep)
5334 const struct of_device_id *id;
5336 id = of_match_node(platform_of_match, aux_ep->dev.of_node);
5340 return panel_simple_probe(&aux_ep->dev, id->data, aux_ep->aux);
5343 static void panel_simple_dp_aux_ep_remove(struct dp_aux_ep_device *aux_ep)
5345 panel_simple_remove(&aux_ep->dev);
5348 static void panel_simple_dp_aux_ep_shutdown(struct dp_aux_ep_device *aux_ep)
5350 panel_simple_shutdown(&aux_ep->dev);
5353 static struct dp_aux_ep_driver panel_simple_dp_aux_ep_driver = {
5355 .name = "panel-simple-dp-aux",
5356 .of_match_table = platform_of_match, /* Same as platform one! */
5357 .pm = &panel_simple_pm_ops,
5359 .probe = panel_simple_dp_aux_ep_probe,
5360 .remove = panel_simple_dp_aux_ep_remove,
5361 .shutdown = panel_simple_dp_aux_ep_shutdown,
5364 static int __init panel_simple_init(void)
5368 err = platform_driver_register(&panel_simple_platform_driver);
5372 err = dp_aux_dp_driver_register(&panel_simple_dp_aux_ep_driver);
5374 goto err_did_platform_register;
5376 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) {
5377 err = mipi_dsi_driver_register(&panel_simple_dsi_driver);
5379 goto err_did_aux_ep_register;
5384 err_did_aux_ep_register:
5385 dp_aux_dp_driver_unregister(&panel_simple_dp_aux_ep_driver);
5387 err_did_platform_register:
5388 platform_driver_unregister(&panel_simple_platform_driver);
5392 module_init(panel_simple_init);
5394 static void __exit panel_simple_exit(void)
5396 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI))
5397 mipi_dsi_driver_unregister(&panel_simple_dsi_driver);
5399 dp_aux_dp_driver_unregister(&panel_simple_dp_aux_ep_driver);
5400 platform_driver_unregister(&panel_simple_platform_driver);
5402 module_exit(panel_simple_exit);
5404 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
5405 MODULE_DESCRIPTION("DRM Driver for Simple Panels");
5406 MODULE_LICENSE("GPL and additional rights");