2 * Copyright (C) 2013, NVIDIA Corporation. All rights reserved.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sub license,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the
12 * next paragraph) shall be included in all copies or substantial portions
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 #include <linux/delay.h>
25 #include <linux/gpio/consumer.h>
26 #include <linux/iopoll.h>
27 #include <linux/module.h>
28 #include <linux/of_platform.h>
29 #include <linux/platform_device.h>
30 #include <linux/pm_runtime.h>
31 #include <linux/regulator/consumer.h>
33 #include <video/display_timing.h>
34 #include <video/of_display_timing.h>
35 #include <video/videomode.h>
37 #include <drm/drm_crtc.h>
38 #include <drm/drm_device.h>
39 #include <drm/drm_dp_aux_bus.h>
40 #include <drm/drm_dp_helper.h>
41 #include <drm/drm_mipi_dsi.h>
42 #include <drm/drm_panel.h>
45 * struct panel_desc - Describes a simple panel.
49 * @modes: Pointer to array of fixed modes appropriate for this panel.
51 * If only one mode then this can just be the address of the mode.
52 * NOTE: cannot be used with "timings" and also if this is specified
53 * then you cannot override the mode in the device tree.
55 const struct drm_display_mode *modes;
57 /** @num_modes: Number of elements in modes array. */
58 unsigned int num_modes;
61 * @timings: Pointer to array of display timings
63 * NOTE: cannot be used with "modes" and also these will be used to
64 * validate a device tree override if one is present.
66 const struct display_timing *timings;
68 /** @num_timings: Number of elements in timings array. */
69 unsigned int num_timings;
71 /** @bpc: Bits per color. */
74 /** @size: Structure containing the physical size of this panel. */
77 * @size.width: Width (in mm) of the active display area.
82 * @size.height: Height (in mm) of the active display area.
87 /** @delay: Structure containing various delay values for this panel. */
90 * @delay.prepare: Time for the panel to become ready.
92 * The time (in milliseconds) that it takes for the panel to
93 * become ready and start receiving video data
98 * @delay.hpd_absent_delay: Time to wait if HPD isn't hooked up.
100 * Add this to the prepare delay if we know Hot Plug Detect
103 unsigned int hpd_absent_delay;
106 * @delay.prepare_to_enable: Time between prepare and enable.
108 * The minimum time, in milliseconds, that needs to have passed
109 * between when prepare finished and enable may begin. If at
110 * enable time less time has passed since prepare finished,
111 * the driver waits for the remaining time.
113 * If a fixed enable delay is also specified, we'll start
114 * counting before delaying for the fixed delay.
116 * If a fixed prepare delay is also specified, we won't start
117 * counting until after the fixed delay. We can't overlap this
118 * fixed delay with the min time because the fixed delay
119 * doesn't happen at the end of the function if a HPD GPIO was
125 * // do fixed prepare delay
126 * // wait for HPD GPIO if applicable
127 * // start counting for prepare_to_enable
130 * // do fixed enable delay
131 * // enforce prepare_to_enable min time
133 unsigned int prepare_to_enable;
136 * @delay.enable: Time for the panel to display a valid frame.
138 * The time (in milliseconds) that it takes for the panel to
139 * display the first valid frame after starting to receive
145 * @delay.disable: Time for the panel to turn the display off.
147 * The time (in milliseconds) that it takes for the panel to
148 * turn the display off (no content is visible).
150 unsigned int disable;
153 * @delay.unprepare: Time to power down completely.
155 * The time (in milliseconds) that it takes for the panel
156 * to power itself down completely.
158 * This time is used to prevent a future "prepare" from
159 * starting until at least this many milliseconds has passed.
160 * If at prepare time less time has passed since unprepare
161 * finished, the driver waits for the remaining time.
163 unsigned int unprepare;
166 /** @bus_format: See MEDIA_BUS_FMT_... defines. */
169 /** @bus_flags: See DRM_BUS_FLAG_... defines. */
172 /** @connector_type: LVDS, eDP, DSI, DPI, etc. */
176 struct panel_simple {
177 struct drm_panel base;
183 ktime_t prepared_time;
184 ktime_t unprepared_time;
186 const struct panel_desc *desc;
188 struct regulator *supply;
189 struct i2c_adapter *ddc;
190 struct drm_dp_aux *aux;
192 struct gpio_desc *enable_gpio;
193 struct gpio_desc *hpd_gpio;
197 struct drm_display_mode override_mode;
199 enum drm_panel_orientation orientation;
202 static inline struct panel_simple *to_panel_simple(struct drm_panel *panel)
204 return container_of(panel, struct panel_simple, base);
207 static unsigned int panel_simple_get_timings_modes(struct panel_simple *panel,
208 struct drm_connector *connector)
210 struct drm_display_mode *mode;
211 unsigned int i, num = 0;
213 for (i = 0; i < panel->desc->num_timings; i++) {
214 const struct display_timing *dt = &panel->desc->timings[i];
217 videomode_from_timing(dt, &vm);
218 mode = drm_mode_create(connector->dev);
220 dev_err(panel->base.dev, "failed to add mode %ux%u\n",
221 dt->hactive.typ, dt->vactive.typ);
225 drm_display_mode_from_videomode(&vm, mode);
227 mode->type |= DRM_MODE_TYPE_DRIVER;
229 if (panel->desc->num_timings == 1)
230 mode->type |= DRM_MODE_TYPE_PREFERRED;
232 drm_mode_probed_add(connector, mode);
239 static unsigned int panel_simple_get_display_modes(struct panel_simple *panel,
240 struct drm_connector *connector)
242 struct drm_display_mode *mode;
243 unsigned int i, num = 0;
245 for (i = 0; i < panel->desc->num_modes; i++) {
246 const struct drm_display_mode *m = &panel->desc->modes[i];
248 mode = drm_mode_duplicate(connector->dev, m);
250 dev_err(panel->base.dev, "failed to add mode %ux%u@%u\n",
251 m->hdisplay, m->vdisplay,
252 drm_mode_vrefresh(m));
256 mode->type |= DRM_MODE_TYPE_DRIVER;
258 if (panel->desc->num_modes == 1)
259 mode->type |= DRM_MODE_TYPE_PREFERRED;
261 drm_mode_set_name(mode);
263 drm_mode_probed_add(connector, mode);
270 static int panel_simple_get_non_edid_modes(struct panel_simple *panel,
271 struct drm_connector *connector)
273 struct drm_display_mode *mode;
274 bool has_override = panel->override_mode.type;
275 unsigned int num = 0;
281 mode = drm_mode_duplicate(connector->dev,
282 &panel->override_mode);
284 drm_mode_probed_add(connector, mode);
287 dev_err(panel->base.dev, "failed to add override mode\n");
291 /* Only add timings if override was not there or failed to validate */
292 if (num == 0 && panel->desc->num_timings)
293 num = panel_simple_get_timings_modes(panel, connector);
296 * Only add fixed modes if timings/override added no mode.
298 * We should only ever have either the display timings specified
299 * or a fixed mode. Anything else is rather bogus.
301 WARN_ON(panel->desc->num_timings && panel->desc->num_modes);
303 num = panel_simple_get_display_modes(panel, connector);
305 connector->display_info.bpc = panel->desc->bpc;
306 connector->display_info.width_mm = panel->desc->size.width;
307 connector->display_info.height_mm = panel->desc->size.height;
308 if (panel->desc->bus_format)
309 drm_display_info_set_bus_formats(&connector->display_info,
310 &panel->desc->bus_format, 1);
311 connector->display_info.bus_flags = panel->desc->bus_flags;
316 static void panel_simple_wait(ktime_t start_ktime, unsigned int min_ms)
318 ktime_t now_ktime, min_ktime;
323 min_ktime = ktime_add(start_ktime, ms_to_ktime(min_ms));
324 now_ktime = ktime_get();
326 if (ktime_before(now_ktime, min_ktime))
327 msleep(ktime_to_ms(ktime_sub(min_ktime, now_ktime)) + 1);
330 static int panel_simple_disable(struct drm_panel *panel)
332 struct panel_simple *p = to_panel_simple(panel);
337 if (p->desc->delay.disable)
338 msleep(p->desc->delay.disable);
345 static int panel_simple_suspend(struct device *dev)
347 struct panel_simple *p = dev_get_drvdata(dev);
349 gpiod_set_value_cansleep(p->enable_gpio, 0);
350 regulator_disable(p->supply);
351 p->unprepared_time = ktime_get();
359 static int panel_simple_unprepare(struct drm_panel *panel)
361 struct panel_simple *p = to_panel_simple(panel);
364 /* Unpreparing when already unprepared is a no-op */
368 pm_runtime_mark_last_busy(panel->dev);
369 ret = pm_runtime_put_autosuspend(panel->dev);
377 static int panel_simple_get_hpd_gpio(struct device *dev, struct panel_simple *p)
381 p->hpd_gpio = devm_gpiod_get_optional(dev, "hpd", GPIOD_IN);
382 if (IS_ERR(p->hpd_gpio)) {
383 err = PTR_ERR(p->hpd_gpio);
385 if (err != -EPROBE_DEFER)
386 dev_err(dev, "failed to get 'hpd' GPIO: %d\n", err);
394 static int panel_simple_prepare_once(struct panel_simple *p)
396 struct device *dev = p->base.dev;
400 unsigned long hpd_wait_us;
402 panel_simple_wait(p->unprepared_time, p->desc->delay.unprepare);
404 err = regulator_enable(p->supply);
406 dev_err(dev, "failed to enable supply: %d\n", err);
410 gpiod_set_value_cansleep(p->enable_gpio, 1);
412 delay = p->desc->delay.prepare;
414 delay += p->desc->delay.hpd_absent_delay;
419 if (p->desc->delay.hpd_absent_delay)
420 hpd_wait_us = p->desc->delay.hpd_absent_delay * 1000UL;
422 hpd_wait_us = 2000000;
424 err = readx_poll_timeout(gpiod_get_value_cansleep, p->hpd_gpio,
425 hpd_asserted, hpd_asserted,
427 if (hpd_asserted < 0)
431 if (err != -ETIMEDOUT)
433 "error waiting for hpd GPIO: %d\n", err);
438 p->prepared_time = ktime_get();
443 gpiod_set_value_cansleep(p->enable_gpio, 0);
444 regulator_disable(p->supply);
445 p->unprepared_time = ktime_get();
451 * Some panels simply don't always come up and need to be power cycled to
452 * work properly. We'll allow for a handful of retries.
454 #define MAX_PANEL_PREPARE_TRIES 5
456 static int panel_simple_resume(struct device *dev)
458 struct panel_simple *p = dev_get_drvdata(dev);
462 for (try = 0; try < MAX_PANEL_PREPARE_TRIES; try++) {
463 ret = panel_simple_prepare_once(p);
464 if (ret != -ETIMEDOUT)
468 if (ret == -ETIMEDOUT)
469 dev_err(dev, "Prepare timeout after %d tries\n", try);
471 dev_warn(dev, "Prepare needed %d retries\n", try);
476 static int panel_simple_prepare(struct drm_panel *panel)
478 struct panel_simple *p = to_panel_simple(panel);
481 /* Preparing when already prepared is a no-op */
485 ret = pm_runtime_get_sync(panel->dev);
487 pm_runtime_put_autosuspend(panel->dev);
496 static int panel_simple_enable(struct drm_panel *panel)
498 struct panel_simple *p = to_panel_simple(panel);
503 if (p->desc->delay.enable)
504 msleep(p->desc->delay.enable);
506 panel_simple_wait(p->prepared_time, p->desc->delay.prepare_to_enable);
513 static int panel_simple_get_modes(struct drm_panel *panel,
514 struct drm_connector *connector)
516 struct panel_simple *p = to_panel_simple(panel);
519 /* probe EDID if a DDC bus is available */
521 pm_runtime_get_sync(panel->dev);
524 p->edid = drm_get_edid(connector, p->ddc);
527 num += drm_add_edid_modes(connector, p->edid);
529 pm_runtime_mark_last_busy(panel->dev);
530 pm_runtime_put_autosuspend(panel->dev);
533 /* add hard-coded panel modes */
534 num += panel_simple_get_non_edid_modes(p, connector);
536 /* set up connector's "panel orientation" property */
537 drm_connector_set_panel_orientation(connector, p->orientation);
542 static int panel_simple_get_timings(struct drm_panel *panel,
543 unsigned int num_timings,
544 struct display_timing *timings)
546 struct panel_simple *p = to_panel_simple(panel);
549 if (p->desc->num_timings < num_timings)
550 num_timings = p->desc->num_timings;
553 for (i = 0; i < num_timings; i++)
554 timings[i] = p->desc->timings[i];
556 return p->desc->num_timings;
559 static const struct drm_panel_funcs panel_simple_funcs = {
560 .disable = panel_simple_disable,
561 .unprepare = panel_simple_unprepare,
562 .prepare = panel_simple_prepare,
563 .enable = panel_simple_enable,
564 .get_modes = panel_simple_get_modes,
565 .get_timings = panel_simple_get_timings,
568 static struct panel_desc panel_dpi;
570 static int panel_dpi_probe(struct device *dev,
571 struct panel_simple *panel)
573 struct display_timing *timing;
574 const struct device_node *np;
575 struct panel_desc *desc;
576 unsigned int bus_flags;
581 desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL);
585 timing = devm_kzalloc(dev, sizeof(*timing), GFP_KERNEL);
589 ret = of_get_display_timing(np, "panel-timing", timing);
591 dev_err(dev, "%pOF: no panel-timing node found for \"panel-dpi\" binding\n",
596 desc->timings = timing;
597 desc->num_timings = 1;
599 of_property_read_u32(np, "width-mm", &desc->size.width);
600 of_property_read_u32(np, "height-mm", &desc->size.height);
602 /* Extract bus_flags from display_timing */
604 vm.flags = timing->flags;
605 drm_bus_flags_from_videomode(&vm, &bus_flags);
606 desc->bus_flags = bus_flags;
608 /* We do not know the connector for the DT node, so guess it */
609 desc->connector_type = DRM_MODE_CONNECTOR_DPI;
616 #define PANEL_SIMPLE_BOUNDS_CHECK(to_check, bounds, field) \
617 (to_check->field.typ >= bounds->field.min && \
618 to_check->field.typ <= bounds->field.max)
619 static void panel_simple_parse_panel_timing_node(struct device *dev,
620 struct panel_simple *panel,
621 const struct display_timing *ot)
623 const struct panel_desc *desc = panel->desc;
627 if (WARN_ON(desc->num_modes)) {
628 dev_err(dev, "Reject override mode: panel has a fixed mode\n");
631 if (WARN_ON(!desc->num_timings)) {
632 dev_err(dev, "Reject override mode: no timings specified\n");
636 for (i = 0; i < panel->desc->num_timings; i++) {
637 const struct display_timing *dt = &panel->desc->timings[i];
639 if (!PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hactive) ||
640 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hfront_porch) ||
641 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hback_porch) ||
642 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hsync_len) ||
643 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vactive) ||
644 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vfront_porch) ||
645 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vback_porch) ||
646 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vsync_len))
649 if (ot->flags != dt->flags)
652 videomode_from_timing(ot, &vm);
653 drm_display_mode_from_videomode(&vm, &panel->override_mode);
654 panel->override_mode.type |= DRM_MODE_TYPE_DRIVER |
655 DRM_MODE_TYPE_PREFERRED;
659 if (WARN_ON(!panel->override_mode.type))
660 dev_err(dev, "Reject override mode: No display_timing found\n");
663 static int panel_simple_probe(struct device *dev, const struct panel_desc *desc,
664 struct drm_dp_aux *aux)
666 struct panel_simple *panel;
667 struct display_timing dt;
668 struct device_node *ddc;
673 panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL);
677 panel->enabled = false;
678 panel->prepared_time = 0;
682 panel->no_hpd = of_property_read_bool(dev->of_node, "no-hpd");
683 if (!panel->no_hpd) {
684 err = panel_simple_get_hpd_gpio(dev, panel);
689 panel->supply = devm_regulator_get(dev, "power");
690 if (IS_ERR(panel->supply))
691 return PTR_ERR(panel->supply);
693 panel->enable_gpio = devm_gpiod_get_optional(dev, "enable",
695 if (IS_ERR(panel->enable_gpio)) {
696 err = PTR_ERR(panel->enable_gpio);
697 if (err != -EPROBE_DEFER)
698 dev_err(dev, "failed to request GPIO: %d\n", err);
702 err = of_drm_get_panel_orientation(dev->of_node, &panel->orientation);
704 dev_err(dev, "%pOF: failed to get orientation %d\n", dev->of_node, err);
708 ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0);
710 panel->ddc = of_find_i2c_adapter_by_node(ddc);
714 return -EPROBE_DEFER;
716 panel->ddc = &aux->ddc;
719 if (desc == &panel_dpi) {
720 /* Handle the generic panel-dpi binding */
721 err = panel_dpi_probe(dev, panel);
726 if (!of_get_display_timing(dev->of_node, "panel-timing", &dt))
727 panel_simple_parse_panel_timing_node(dev, panel, &dt);
730 connector_type = desc->connector_type;
731 /* Catch common mistakes for panels. */
732 switch (connector_type) {
734 dev_warn(dev, "Specify missing connector_type\n");
735 connector_type = DRM_MODE_CONNECTOR_DPI;
737 case DRM_MODE_CONNECTOR_LVDS:
738 WARN_ON(desc->bus_flags &
739 ~(DRM_BUS_FLAG_DE_LOW |
740 DRM_BUS_FLAG_DE_HIGH |
741 DRM_BUS_FLAG_DATA_MSB_TO_LSB |
742 DRM_BUS_FLAG_DATA_LSB_TO_MSB));
743 WARN_ON(desc->bus_format != MEDIA_BUS_FMT_RGB666_1X7X3_SPWG &&
744 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_SPWG &&
745 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA);
746 WARN_ON(desc->bus_format == MEDIA_BUS_FMT_RGB666_1X7X3_SPWG &&
748 WARN_ON((desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_SPWG ||
749 desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA) &&
752 case DRM_MODE_CONNECTOR_eDP:
753 if (desc->bpc != 6 && desc->bpc != 8 && desc->bpc != 10)
754 dev_warn(dev, "Expected bpc in {6,8,10} but got: %u\n", desc->bpc);
756 case DRM_MODE_CONNECTOR_DSI:
757 if (desc->bpc != 6 && desc->bpc != 8)
758 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc);
760 case DRM_MODE_CONNECTOR_DPI:
761 bus_flags = DRM_BUS_FLAG_DE_LOW |
762 DRM_BUS_FLAG_DE_HIGH |
763 DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE |
764 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
765 DRM_BUS_FLAG_DATA_MSB_TO_LSB |
766 DRM_BUS_FLAG_DATA_LSB_TO_MSB |
767 DRM_BUS_FLAG_SYNC_SAMPLE_POSEDGE |
768 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE;
769 if (desc->bus_flags & ~bus_flags)
770 dev_warn(dev, "Unexpected bus_flags(%d)\n", desc->bus_flags & ~bus_flags);
771 if (!(desc->bus_flags & bus_flags))
772 dev_warn(dev, "Specify missing bus_flags\n");
773 if (desc->bus_format == 0)
774 dev_warn(dev, "Specify missing bus_format\n");
775 if (desc->bpc != 6 && desc->bpc != 8)
776 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc);
779 dev_warn(dev, "Specify a valid connector_type: %d\n", desc->connector_type);
780 connector_type = DRM_MODE_CONNECTOR_DPI;
784 dev_set_drvdata(dev, panel);
787 * We use runtime PM for prepare / unprepare since those power the panel
788 * on and off and those can be very slow operations. This is important
789 * to optimize powering the panel on briefly to read the EDID before
790 * fully enabling the panel.
792 pm_runtime_enable(dev);
793 pm_runtime_set_autosuspend_delay(dev, 1000);
794 pm_runtime_use_autosuspend(dev);
796 drm_panel_init(&panel->base, dev, &panel_simple_funcs, connector_type);
798 err = drm_panel_of_backlight(&panel->base);
800 goto disable_pm_runtime;
802 if (!panel->base.backlight && panel->aux) {
803 pm_runtime_get_sync(dev);
804 err = drm_panel_dp_aux_backlight(&panel->base, panel->aux);
805 pm_runtime_mark_last_busy(dev);
806 pm_runtime_put_autosuspend(dev);
808 goto disable_pm_runtime;
811 drm_panel_add(&panel->base);
816 pm_runtime_dont_use_autosuspend(dev);
817 pm_runtime_disable(dev);
819 if (panel->ddc && (!panel->aux || panel->ddc != &panel->aux->ddc))
820 put_device(&panel->ddc->dev);
825 static int panel_simple_remove(struct device *dev)
827 struct panel_simple *panel = dev_get_drvdata(dev);
829 drm_panel_remove(&panel->base);
830 drm_panel_disable(&panel->base);
831 drm_panel_unprepare(&panel->base);
833 pm_runtime_dont_use_autosuspend(dev);
834 pm_runtime_disable(dev);
835 if (panel->ddc && (!panel->aux || panel->ddc != &panel->aux->ddc))
836 put_device(&panel->ddc->dev);
841 static void panel_simple_shutdown(struct device *dev)
843 struct panel_simple *panel = dev_get_drvdata(dev);
845 drm_panel_disable(&panel->base);
846 drm_panel_unprepare(&panel->base);
849 static const struct drm_display_mode ampire_am_1280800n3tzqw_t00h_mode = {
852 .hsync_start = 1280 + 40,
853 .hsync_end = 1280 + 40 + 80,
854 .htotal = 1280 + 40 + 80 + 40,
856 .vsync_start = 800 + 3,
857 .vsync_end = 800 + 3 + 10,
858 .vtotal = 800 + 3 + 10 + 10,
859 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
862 static const struct panel_desc ampire_am_1280800n3tzqw_t00h = {
863 .modes = &ire_am_1280800n3tzqw_t00h_mode,
870 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
871 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
872 .connector_type = DRM_MODE_CONNECTOR_LVDS,
875 static const struct drm_display_mode ampire_am_480272h3tmqw_t01h_mode = {
878 .hsync_start = 480 + 2,
879 .hsync_end = 480 + 2 + 41,
880 .htotal = 480 + 2 + 41 + 2,
882 .vsync_start = 272 + 2,
883 .vsync_end = 272 + 2 + 10,
884 .vtotal = 272 + 2 + 10 + 2,
885 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
888 static const struct panel_desc ampire_am_480272h3tmqw_t01h = {
889 .modes = &ire_am_480272h3tmqw_t01h_mode,
896 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
899 static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = {
902 .hsync_start = 800 + 0,
903 .hsync_end = 800 + 0 + 255,
904 .htotal = 800 + 0 + 255 + 0,
906 .vsync_start = 480 + 2,
907 .vsync_end = 480 + 2 + 45,
908 .vtotal = 480 + 2 + 45 + 0,
909 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
912 static const struct panel_desc ampire_am800480r3tmqwa1h = {
913 .modes = &ire_am800480r3tmqwa1h_mode,
920 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
923 static const struct display_timing santek_st0700i5y_rbslw_f_timing = {
924 .pixelclock = { 26400000, 33300000, 46800000 },
925 .hactive = { 800, 800, 800 },
926 .hfront_porch = { 16, 210, 354 },
927 .hback_porch = { 45, 36, 6 },
928 .hsync_len = { 1, 10, 40 },
929 .vactive = { 480, 480, 480 },
930 .vfront_porch = { 7, 22, 147 },
931 .vback_porch = { 22, 13, 3 },
932 .vsync_len = { 1, 10, 20 },
933 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
934 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE
937 static const struct panel_desc armadeus_st0700_adapt = {
938 .timings = &santek_st0700i5y_rbslw_f_timing,
945 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
946 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
949 static const struct drm_display_mode auo_b101aw03_mode = {
952 .hsync_start = 1024 + 156,
953 .hsync_end = 1024 + 156 + 8,
954 .htotal = 1024 + 156 + 8 + 156,
956 .vsync_start = 600 + 16,
957 .vsync_end = 600 + 16 + 6,
958 .vtotal = 600 + 16 + 6 + 16,
961 static const struct panel_desc auo_b101aw03 = {
962 .modes = &auo_b101aw03_mode,
969 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
970 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
971 .connector_type = DRM_MODE_CONNECTOR_LVDS,
974 static const struct display_timing auo_b101ean01_timing = {
975 .pixelclock = { 65300000, 72500000, 75000000 },
976 .hactive = { 1280, 1280, 1280 },
977 .hfront_porch = { 18, 119, 119 },
978 .hback_porch = { 21, 21, 21 },
979 .hsync_len = { 32, 32, 32 },
980 .vactive = { 800, 800, 800 },
981 .vfront_porch = { 4, 4, 4 },
982 .vback_porch = { 8, 8, 8 },
983 .vsync_len = { 18, 20, 20 },
986 static const struct panel_desc auo_b101ean01 = {
987 .timings = &auo_b101ean01_timing,
996 static const struct drm_display_mode auo_b101xtn01_mode = {
999 .hsync_start = 1366 + 20,
1000 .hsync_end = 1366 + 20 + 70,
1001 .htotal = 1366 + 20 + 70,
1003 .vsync_start = 768 + 14,
1004 .vsync_end = 768 + 14 + 42,
1005 .vtotal = 768 + 14 + 42,
1006 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1009 static const struct panel_desc auo_b101xtn01 = {
1010 .modes = &auo_b101xtn01_mode,
1019 static const struct drm_display_mode auo_b116xak01_mode = {
1022 .hsync_start = 1366 + 48,
1023 .hsync_end = 1366 + 48 + 32,
1024 .htotal = 1366 + 48 + 32 + 10,
1026 .vsync_start = 768 + 4,
1027 .vsync_end = 768 + 4 + 6,
1028 .vtotal = 768 + 4 + 6 + 15,
1029 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1032 static const struct panel_desc auo_b116xak01 = {
1033 .modes = &auo_b116xak01_mode,
1041 .hpd_absent_delay = 200,
1043 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1044 .connector_type = DRM_MODE_CONNECTOR_eDP,
1047 static const struct drm_display_mode auo_b116xw03_mode = {
1050 .hsync_start = 1366 + 40,
1051 .hsync_end = 1366 + 40 + 40,
1052 .htotal = 1366 + 40 + 40 + 32,
1054 .vsync_start = 768 + 10,
1055 .vsync_end = 768 + 10 + 12,
1056 .vtotal = 768 + 10 + 12 + 6,
1057 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1060 static const struct panel_desc auo_b116xw03 = {
1061 .modes = &auo_b116xw03_mode,
1071 .bus_flags = DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE,
1072 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1073 .connector_type = DRM_MODE_CONNECTOR_eDP,
1076 static const struct drm_display_mode auo_b133xtn01_mode = {
1079 .hsync_start = 1366 + 48,
1080 .hsync_end = 1366 + 48 + 32,
1081 .htotal = 1366 + 48 + 32 + 20,
1083 .vsync_start = 768 + 3,
1084 .vsync_end = 768 + 3 + 6,
1085 .vtotal = 768 + 3 + 6 + 13,
1088 static const struct panel_desc auo_b133xtn01 = {
1089 .modes = &auo_b133xtn01_mode,
1098 static const struct drm_display_mode auo_b133han05_mode = {
1101 .hsync_start = 1920 + 58,
1102 .hsync_end = 1920 + 58 + 42,
1103 .htotal = 1920 + 58 + 42 + 60,
1105 .vsync_start = 1080 + 3,
1106 .vsync_end = 1080 + 3 + 5,
1107 .vtotal = 1080 + 3 + 5 + 54,
1110 static const struct panel_desc auo_b133han05 = {
1111 .modes = &auo_b133han05_mode,
1123 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1124 .bus_flags = DRM_BUS_FLAG_DATA_MSB_TO_LSB,
1125 .connector_type = DRM_MODE_CONNECTOR_eDP,
1128 static const struct drm_display_mode auo_b133htn01_mode = {
1131 .hsync_start = 1920 + 172,
1132 .hsync_end = 1920 + 172 + 80,
1133 .htotal = 1920 + 172 + 80 + 60,
1135 .vsync_start = 1080 + 25,
1136 .vsync_end = 1080 + 25 + 10,
1137 .vtotal = 1080 + 25 + 10 + 10,
1140 static const struct panel_desc auo_b133htn01 = {
1141 .modes = &auo_b133htn01_mode,
1155 static const struct drm_display_mode auo_b140han06_mode = {
1158 .hsync_start = 1920 + 16,
1159 .hsync_end = 1920 + 16 + 16,
1160 .htotal = 1920 + 16 + 16 + 152,
1162 .vsync_start = 1080 + 3,
1163 .vsync_end = 1080 + 3 + 14,
1164 .vtotal = 1080 + 3 + 14 + 19,
1167 static const struct panel_desc auo_b140han06 = {
1168 .modes = &auo_b140han06_mode,
1180 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1181 .bus_flags = DRM_BUS_FLAG_DATA_MSB_TO_LSB,
1182 .connector_type = DRM_MODE_CONNECTOR_eDP,
1185 static const struct display_timing auo_g070vvn01_timings = {
1186 .pixelclock = { 33300000, 34209000, 45000000 },
1187 .hactive = { 800, 800, 800 },
1188 .hfront_porch = { 20, 40, 200 },
1189 .hback_porch = { 87, 40, 1 },
1190 .hsync_len = { 1, 48, 87 },
1191 .vactive = { 480, 480, 480 },
1192 .vfront_porch = { 5, 13, 200 },
1193 .vback_porch = { 31, 31, 29 },
1194 .vsync_len = { 1, 1, 3 },
1197 static const struct panel_desc auo_g070vvn01 = {
1198 .timings = &auo_g070vvn01_timings,
1213 static const struct drm_display_mode auo_g101evn010_mode = {
1216 .hsync_start = 1280 + 82,
1217 .hsync_end = 1280 + 82 + 2,
1218 .htotal = 1280 + 82 + 2 + 84,
1220 .vsync_start = 800 + 8,
1221 .vsync_end = 800 + 8 + 2,
1222 .vtotal = 800 + 8 + 2 + 6,
1225 static const struct panel_desc auo_g101evn010 = {
1226 .modes = &auo_g101evn010_mode,
1233 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1234 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1237 static const struct drm_display_mode auo_g104sn02_mode = {
1240 .hsync_start = 800 + 40,
1241 .hsync_end = 800 + 40 + 216,
1242 .htotal = 800 + 40 + 216 + 128,
1244 .vsync_start = 600 + 10,
1245 .vsync_end = 600 + 10 + 35,
1246 .vtotal = 600 + 10 + 35 + 2,
1249 static const struct panel_desc auo_g104sn02 = {
1250 .modes = &auo_g104sn02_mode,
1257 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1258 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1261 static const struct drm_display_mode auo_g121ean01_mode = {
1264 .hsync_start = 1280 + 58,
1265 .hsync_end = 1280 + 58 + 8,
1266 .htotal = 1280 + 58 + 8 + 70,
1268 .vsync_start = 800 + 6,
1269 .vsync_end = 800 + 6 + 4,
1270 .vtotal = 800 + 6 + 4 + 10,
1273 static const struct panel_desc auo_g121ean01 = {
1274 .modes = &auo_g121ean01_mode,
1281 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1282 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1285 static const struct display_timing auo_g133han01_timings = {
1286 .pixelclock = { 134000000, 141200000, 149000000 },
1287 .hactive = { 1920, 1920, 1920 },
1288 .hfront_porch = { 39, 58, 77 },
1289 .hback_porch = { 59, 88, 117 },
1290 .hsync_len = { 28, 42, 56 },
1291 .vactive = { 1080, 1080, 1080 },
1292 .vfront_porch = { 3, 8, 11 },
1293 .vback_porch = { 5, 14, 19 },
1294 .vsync_len = { 4, 14, 19 },
1297 static const struct panel_desc auo_g133han01 = {
1298 .timings = &auo_g133han01_timings,
1311 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
1312 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1315 static const struct drm_display_mode auo_g156xtn01_mode = {
1318 .hsync_start = 1366 + 33,
1319 .hsync_end = 1366 + 33 + 67,
1322 .vsync_start = 768 + 4,
1323 .vsync_end = 768 + 4 + 4,
1327 static const struct panel_desc auo_g156xtn01 = {
1328 .modes = &auo_g156xtn01_mode,
1335 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1336 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1339 static const struct display_timing auo_g185han01_timings = {
1340 .pixelclock = { 120000000, 144000000, 175000000 },
1341 .hactive = { 1920, 1920, 1920 },
1342 .hfront_porch = { 36, 120, 148 },
1343 .hback_porch = { 24, 88, 108 },
1344 .hsync_len = { 20, 48, 64 },
1345 .vactive = { 1080, 1080, 1080 },
1346 .vfront_porch = { 6, 10, 40 },
1347 .vback_porch = { 2, 5, 20 },
1348 .vsync_len = { 2, 5, 20 },
1351 static const struct panel_desc auo_g185han01 = {
1352 .timings = &auo_g185han01_timings,
1365 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1366 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1369 static const struct display_timing auo_g190ean01_timings = {
1370 .pixelclock = { 90000000, 108000000, 135000000 },
1371 .hactive = { 1280, 1280, 1280 },
1372 .hfront_porch = { 126, 184, 1266 },
1373 .hback_porch = { 84, 122, 844 },
1374 .hsync_len = { 70, 102, 704 },
1375 .vactive = { 1024, 1024, 1024 },
1376 .vfront_porch = { 4, 26, 76 },
1377 .vback_porch = { 2, 8, 25 },
1378 .vsync_len = { 2, 8, 25 },
1381 static const struct panel_desc auo_g190ean01 = {
1382 .timings = &auo_g190ean01_timings,
1395 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1396 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1399 static const struct display_timing auo_p320hvn03_timings = {
1400 .pixelclock = { 106000000, 148500000, 164000000 },
1401 .hactive = { 1920, 1920, 1920 },
1402 .hfront_porch = { 25, 50, 130 },
1403 .hback_porch = { 25, 50, 130 },
1404 .hsync_len = { 20, 40, 105 },
1405 .vactive = { 1080, 1080, 1080 },
1406 .vfront_porch = { 8, 17, 150 },
1407 .vback_porch = { 8, 17, 150 },
1408 .vsync_len = { 4, 11, 100 },
1411 static const struct panel_desc auo_p320hvn03 = {
1412 .timings = &auo_p320hvn03_timings,
1424 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1425 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1428 static const struct drm_display_mode auo_t215hvn01_mode = {
1431 .hsync_start = 1920 + 88,
1432 .hsync_end = 1920 + 88 + 44,
1433 .htotal = 1920 + 88 + 44 + 148,
1435 .vsync_start = 1080 + 4,
1436 .vsync_end = 1080 + 4 + 5,
1437 .vtotal = 1080 + 4 + 5 + 36,
1440 static const struct panel_desc auo_t215hvn01 = {
1441 .modes = &auo_t215hvn01_mode,
1454 static const struct drm_display_mode avic_tm070ddh03_mode = {
1457 .hsync_start = 1024 + 160,
1458 .hsync_end = 1024 + 160 + 4,
1459 .htotal = 1024 + 160 + 4 + 156,
1461 .vsync_start = 600 + 17,
1462 .vsync_end = 600 + 17 + 1,
1463 .vtotal = 600 + 17 + 1 + 17,
1466 static const struct panel_desc avic_tm070ddh03 = {
1467 .modes = &avic_tm070ddh03_mode,
1481 static const struct drm_display_mode bananapi_s070wv20_ct16_mode = {
1484 .hsync_start = 800 + 40,
1485 .hsync_end = 800 + 40 + 48,
1486 .htotal = 800 + 40 + 48 + 40,
1488 .vsync_start = 480 + 13,
1489 .vsync_end = 480 + 13 + 3,
1490 .vtotal = 480 + 13 + 3 + 29,
1493 static const struct panel_desc bananapi_s070wv20_ct16 = {
1494 .modes = &bananapi_s070wv20_ct16_mode,
1503 static const struct drm_display_mode boe_hv070wsa_mode = {
1506 .hsync_start = 1024 + 30,
1507 .hsync_end = 1024 + 30 + 30,
1508 .htotal = 1024 + 30 + 30 + 30,
1510 .vsync_start = 600 + 10,
1511 .vsync_end = 600 + 10 + 10,
1512 .vtotal = 600 + 10 + 10 + 10,
1515 static const struct panel_desc boe_hv070wsa = {
1516 .modes = &boe_hv070wsa_mode,
1523 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1524 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1525 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1528 static const struct drm_display_mode boe_nv101wxmn51_modes[] = {
1532 .hsync_start = 1280 + 48,
1533 .hsync_end = 1280 + 48 + 32,
1534 .htotal = 1280 + 48 + 32 + 80,
1536 .vsync_start = 800 + 3,
1537 .vsync_end = 800 + 3 + 5,
1538 .vtotal = 800 + 3 + 5 + 24,
1543 .hsync_start = 1280 + 48,
1544 .hsync_end = 1280 + 48 + 32,
1545 .htotal = 1280 + 48 + 32 + 80,
1547 .vsync_start = 800 + 3,
1548 .vsync_end = 800 + 3 + 5,
1549 .vtotal = 800 + 3 + 5 + 24,
1553 static const struct panel_desc boe_nv101wxmn51 = {
1554 .modes = boe_nv101wxmn51_modes,
1555 .num_modes = ARRAY_SIZE(boe_nv101wxmn51_modes),
1568 static const struct drm_display_mode boe_nv110wtm_n61_modes[] = {
1572 .hsync_start = 2160 + 48,
1573 .hsync_end = 2160 + 48 + 32,
1574 .htotal = 2160 + 48 + 32 + 100,
1576 .vsync_start = 1440 + 3,
1577 .vsync_end = 1440 + 3 + 6,
1578 .vtotal = 1440 + 3 + 6 + 31,
1579 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC,
1584 .hsync_start = 2160 + 48,
1585 .hsync_end = 2160 + 48 + 32,
1586 .htotal = 2160 + 48 + 32 + 100,
1588 .vsync_start = 1440 + 3,
1589 .vsync_end = 1440 + 3 + 6,
1590 .vtotal = 1440 + 3 + 6 + 31,
1591 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC,
1595 static const struct panel_desc boe_nv110wtm_n61 = {
1596 .modes = boe_nv110wtm_n61_modes,
1597 .num_modes = ARRAY_SIZE(boe_nv110wtm_n61_modes),
1604 .hpd_absent_delay = 200,
1605 .prepare_to_enable = 80,
1609 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1610 .bus_flags = DRM_BUS_FLAG_DATA_MSB_TO_LSB,
1611 .connector_type = DRM_MODE_CONNECTOR_eDP,
1614 /* Also used for boe_nv133fhm_n62 */
1615 static const struct drm_display_mode boe_nv133fhm_n61_modes = {
1618 .hsync_start = 1920 + 48,
1619 .hsync_end = 1920 + 48 + 32,
1620 .htotal = 1920 + 48 + 32 + 200,
1622 .vsync_start = 1080 + 3,
1623 .vsync_end = 1080 + 3 + 6,
1624 .vtotal = 1080 + 3 + 6 + 31,
1625 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC,
1628 /* Also used for boe_nv133fhm_n62 */
1629 static const struct panel_desc boe_nv133fhm_n61 = {
1630 .modes = &boe_nv133fhm_n61_modes,
1639 * When power is first given to the panel there's a short
1640 * spike on the HPD line. It was explained that this spike
1641 * was until the TCON data download was complete. On
1642 * one system this was measured at 8 ms. We'll put 15 ms
1643 * in the prepare delay just to be safe and take it away
1644 * from the hpd_absent_delay (which would otherwise be 200 ms)
1645 * to handle this. That means:
1646 * - If HPD isn't hooked up you still have 200 ms delay.
1647 * - If HPD is hooked up we won't try to look at it for the
1651 .hpd_absent_delay = 185,
1655 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1656 .bus_flags = DRM_BUS_FLAG_DATA_MSB_TO_LSB,
1657 .connector_type = DRM_MODE_CONNECTOR_eDP,
1660 static const struct drm_display_mode boe_nv140fhmn49_modes[] = {
1664 .hsync_start = 1920 + 48,
1665 .hsync_end = 1920 + 48 + 32,
1668 .vsync_start = 1080 + 3,
1669 .vsync_end = 1080 + 3 + 5,
1674 static const struct panel_desc boe_nv140fhmn49 = {
1675 .modes = boe_nv140fhmn49_modes,
1676 .num_modes = ARRAY_SIZE(boe_nv140fhmn49_modes),
1687 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1688 .connector_type = DRM_MODE_CONNECTOR_eDP,
1691 static const struct drm_display_mode cdtech_s043wq26h_ct7_mode = {
1694 .hsync_start = 480 + 5,
1695 .hsync_end = 480 + 5 + 5,
1696 .htotal = 480 + 5 + 5 + 40,
1698 .vsync_start = 272 + 8,
1699 .vsync_end = 272 + 8 + 8,
1700 .vtotal = 272 + 8 + 8 + 8,
1701 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1704 static const struct panel_desc cdtech_s043wq26h_ct7 = {
1705 .modes = &cdtech_s043wq26h_ct7_mode,
1712 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1715 /* S070PWS19HP-FC21 2017/04/22 */
1716 static const struct drm_display_mode cdtech_s070pws19hp_fc21_mode = {
1719 .hsync_start = 1024 + 160,
1720 .hsync_end = 1024 + 160 + 20,
1721 .htotal = 1024 + 160 + 20 + 140,
1723 .vsync_start = 600 + 12,
1724 .vsync_end = 600 + 12 + 3,
1725 .vtotal = 600 + 12 + 3 + 20,
1726 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1729 static const struct panel_desc cdtech_s070pws19hp_fc21 = {
1730 .modes = &cdtech_s070pws19hp_fc21_mode,
1737 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1738 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
1739 .connector_type = DRM_MODE_CONNECTOR_DPI,
1742 /* S070SWV29HG-DC44 2017/09/21 */
1743 static const struct drm_display_mode cdtech_s070swv29hg_dc44_mode = {
1746 .hsync_start = 800 + 210,
1747 .hsync_end = 800 + 210 + 2,
1748 .htotal = 800 + 210 + 2 + 44,
1750 .vsync_start = 480 + 22,
1751 .vsync_end = 480 + 22 + 2,
1752 .vtotal = 480 + 22 + 2 + 21,
1753 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1756 static const struct panel_desc cdtech_s070swv29hg_dc44 = {
1757 .modes = &cdtech_s070swv29hg_dc44_mode,
1764 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1765 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
1766 .connector_type = DRM_MODE_CONNECTOR_DPI,
1769 static const struct drm_display_mode cdtech_s070wv95_ct16_mode = {
1772 .hsync_start = 800 + 40,
1773 .hsync_end = 800 + 40 + 40,
1774 .htotal = 800 + 40 + 40 + 48,
1776 .vsync_start = 480 + 29,
1777 .vsync_end = 480 + 29 + 13,
1778 .vtotal = 480 + 29 + 13 + 3,
1779 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1782 static const struct panel_desc cdtech_s070wv95_ct16 = {
1783 .modes = &cdtech_s070wv95_ct16_mode,
1792 static const struct display_timing chefree_ch101olhlwh_002_timing = {
1793 .pixelclock = { 68900000, 71100000, 73400000 },
1794 .hactive = { 1280, 1280, 1280 },
1795 .hfront_porch = { 65, 80, 95 },
1796 .hback_porch = { 64, 79, 94 },
1797 .hsync_len = { 1, 1, 1 },
1798 .vactive = { 800, 800, 800 },
1799 .vfront_porch = { 7, 11, 14 },
1800 .vback_porch = { 7, 11, 14 },
1801 .vsync_len = { 1, 1, 1 },
1802 .flags = DISPLAY_FLAGS_DE_HIGH,
1805 static const struct panel_desc chefree_ch101olhlwh_002 = {
1806 .timings = &chefree_ch101olhlwh_002_timing,
1817 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1818 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1819 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1822 static const struct drm_display_mode chunghwa_claa070wp03xg_mode = {
1825 .hsync_start = 800 + 49,
1826 .hsync_end = 800 + 49 + 33,
1827 .htotal = 800 + 49 + 33 + 17,
1829 .vsync_start = 1280 + 1,
1830 .vsync_end = 1280 + 1 + 7,
1831 .vtotal = 1280 + 1 + 7 + 15,
1832 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1835 static const struct panel_desc chunghwa_claa070wp03xg = {
1836 .modes = &chunghwa_claa070wp03xg_mode,
1843 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1844 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1845 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1848 static const struct drm_display_mode chunghwa_claa101wa01a_mode = {
1851 .hsync_start = 1366 + 58,
1852 .hsync_end = 1366 + 58 + 58,
1853 .htotal = 1366 + 58 + 58 + 58,
1855 .vsync_start = 768 + 4,
1856 .vsync_end = 768 + 4 + 4,
1857 .vtotal = 768 + 4 + 4 + 4,
1860 static const struct panel_desc chunghwa_claa101wa01a = {
1861 .modes = &chunghwa_claa101wa01a_mode,
1868 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1869 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1870 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1873 static const struct drm_display_mode chunghwa_claa101wb01_mode = {
1876 .hsync_start = 1366 + 48,
1877 .hsync_end = 1366 + 48 + 32,
1878 .htotal = 1366 + 48 + 32 + 20,
1880 .vsync_start = 768 + 16,
1881 .vsync_end = 768 + 16 + 8,
1882 .vtotal = 768 + 16 + 8 + 16,
1885 static const struct panel_desc chunghwa_claa101wb01 = {
1886 .modes = &chunghwa_claa101wb01_mode,
1893 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1894 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1895 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1898 static const struct drm_display_mode dataimage_scf0700c48ggu18_mode = {
1901 .hsync_start = 800 + 40,
1902 .hsync_end = 800 + 40 + 128,
1903 .htotal = 800 + 40 + 128 + 88,
1905 .vsync_start = 480 + 10,
1906 .vsync_end = 480 + 10 + 2,
1907 .vtotal = 480 + 10 + 2 + 33,
1908 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1911 static const struct panel_desc dataimage_scf0700c48ggu18 = {
1912 .modes = &dataimage_scf0700c48ggu18_mode,
1919 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1920 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1923 static const struct display_timing dlc_dlc0700yzg_1_timing = {
1924 .pixelclock = { 45000000, 51200000, 57000000 },
1925 .hactive = { 1024, 1024, 1024 },
1926 .hfront_porch = { 100, 106, 113 },
1927 .hback_porch = { 100, 106, 113 },
1928 .hsync_len = { 100, 108, 114 },
1929 .vactive = { 600, 600, 600 },
1930 .vfront_porch = { 8, 11, 15 },
1931 .vback_porch = { 8, 11, 15 },
1932 .vsync_len = { 9, 13, 15 },
1933 .flags = DISPLAY_FLAGS_DE_HIGH,
1936 static const struct panel_desc dlc_dlc0700yzg_1 = {
1937 .timings = &dlc_dlc0700yzg_1_timing,
1949 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1950 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1953 static const struct display_timing dlc_dlc1010gig_timing = {
1954 .pixelclock = { 68900000, 71100000, 73400000 },
1955 .hactive = { 1280, 1280, 1280 },
1956 .hfront_porch = { 43, 53, 63 },
1957 .hback_porch = { 43, 53, 63 },
1958 .hsync_len = { 44, 54, 64 },
1959 .vactive = { 800, 800, 800 },
1960 .vfront_porch = { 5, 8, 11 },
1961 .vback_porch = { 5, 8, 11 },
1962 .vsync_len = { 5, 7, 11 },
1963 .flags = DISPLAY_FLAGS_DE_HIGH,
1966 static const struct panel_desc dlc_dlc1010gig = {
1967 .timings = &dlc_dlc1010gig_timing,
1980 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1981 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1984 static const struct drm_display_mode edt_et035012dm6_mode = {
1987 .hsync_start = 320 + 20,
1988 .hsync_end = 320 + 20 + 30,
1989 .htotal = 320 + 20 + 68,
1991 .vsync_start = 240 + 4,
1992 .vsync_end = 240 + 4 + 4,
1993 .vtotal = 240 + 4 + 4 + 14,
1994 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1997 static const struct panel_desc edt_et035012dm6 = {
1998 .modes = &edt_et035012dm6_mode,
2005 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2006 .bus_flags = DRM_BUS_FLAG_DE_LOW | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
2009 static const struct drm_display_mode edt_etm0350g0dh6_mode = {
2012 .hsync_start = 320 + 20,
2013 .hsync_end = 320 + 20 + 68,
2014 .htotal = 320 + 20 + 68,
2016 .vsync_start = 240 + 4,
2017 .vsync_end = 240 + 4 + 18,
2018 .vtotal = 240 + 4 + 18,
2019 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2022 static const struct panel_desc edt_etm0350g0dh6 = {
2023 .modes = &edt_etm0350g0dh6_mode,
2030 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2031 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
2032 .connector_type = DRM_MODE_CONNECTOR_DPI,
2035 static const struct drm_display_mode edt_etm043080dh6gp_mode = {
2038 .hsync_start = 480 + 8,
2039 .hsync_end = 480 + 8 + 4,
2040 .htotal = 480 + 8 + 4 + 41,
2043 * IWG22M: Y resolution changed for "dc_linuxfb" module crashing while
2048 .vsync_start = 288 + 2,
2049 .vsync_end = 288 + 2 + 4,
2050 .vtotal = 288 + 2 + 4 + 10,
2053 static const struct panel_desc edt_etm043080dh6gp = {
2054 .modes = &edt_etm043080dh6gp_mode,
2061 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2062 .connector_type = DRM_MODE_CONNECTOR_DPI,
2065 static const struct drm_display_mode edt_etm0430g0dh6_mode = {
2068 .hsync_start = 480 + 2,
2069 .hsync_end = 480 + 2 + 41,
2070 .htotal = 480 + 2 + 41 + 2,
2072 .vsync_start = 272 + 2,
2073 .vsync_end = 272 + 2 + 10,
2074 .vtotal = 272 + 2 + 10 + 2,
2075 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
2078 static const struct panel_desc edt_etm0430g0dh6 = {
2079 .modes = &edt_etm0430g0dh6_mode,
2086 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2087 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
2088 .connector_type = DRM_MODE_CONNECTOR_DPI,
2091 static const struct drm_display_mode edt_et057090dhu_mode = {
2094 .hsync_start = 640 + 16,
2095 .hsync_end = 640 + 16 + 30,
2096 .htotal = 640 + 16 + 30 + 114,
2098 .vsync_start = 480 + 10,
2099 .vsync_end = 480 + 10 + 3,
2100 .vtotal = 480 + 10 + 3 + 32,
2101 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2104 static const struct panel_desc edt_et057090dhu = {
2105 .modes = &edt_et057090dhu_mode,
2112 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2113 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
2114 .connector_type = DRM_MODE_CONNECTOR_DPI,
2117 static const struct drm_display_mode edt_etm0700g0dh6_mode = {
2120 .hsync_start = 800 + 40,
2121 .hsync_end = 800 + 40 + 128,
2122 .htotal = 800 + 40 + 128 + 88,
2124 .vsync_start = 480 + 10,
2125 .vsync_end = 480 + 10 + 2,
2126 .vtotal = 480 + 10 + 2 + 33,
2127 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
2130 static const struct panel_desc edt_etm0700g0dh6 = {
2131 .modes = &edt_etm0700g0dh6_mode,
2138 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2139 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
2140 .connector_type = DRM_MODE_CONNECTOR_DPI,
2143 static const struct panel_desc edt_etm0700g0bdh6 = {
2144 .modes = &edt_etm0700g0dh6_mode,
2151 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2152 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
2153 .connector_type = DRM_MODE_CONNECTOR_DPI,
2156 static const struct drm_display_mode edt_etmv570g2dhu_mode = {
2160 .hsync_end = 640 + 16,
2161 .htotal = 640 + 16 + 30 + 114,
2163 .vsync_start = 480 + 10,
2164 .vsync_end = 480 + 10 + 3,
2165 .vtotal = 480 + 10 + 3 + 35,
2166 .flags = DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_PHSYNC,
2169 static const struct panel_desc edt_etmv570g2dhu = {
2170 .modes = &edt_etmv570g2dhu_mode,
2177 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2178 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
2179 .connector_type = DRM_MODE_CONNECTOR_DPI,
2182 static const struct display_timing eink_vb3300_kca_timing = {
2183 .pixelclock = { 40000000, 40000000, 40000000 },
2184 .hactive = { 334, 334, 334 },
2185 .hfront_porch = { 1, 1, 1 },
2186 .hback_porch = { 1, 1, 1 },
2187 .hsync_len = { 1, 1, 1 },
2188 .vactive = { 1405, 1405, 1405 },
2189 .vfront_porch = { 1, 1, 1 },
2190 .vback_porch = { 1, 1, 1 },
2191 .vsync_len = { 1, 1, 1 },
2192 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
2193 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE,
2196 static const struct panel_desc eink_vb3300_kca = {
2197 .timings = &eink_vb3300_kca_timing,
2204 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2205 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
2206 .connector_type = DRM_MODE_CONNECTOR_DPI,
2209 static const struct display_timing evervision_vgg804821_timing = {
2210 .pixelclock = { 27600000, 33300000, 50000000 },
2211 .hactive = { 800, 800, 800 },
2212 .hfront_porch = { 40, 66, 70 },
2213 .hback_porch = { 40, 67, 70 },
2214 .hsync_len = { 40, 67, 70 },
2215 .vactive = { 480, 480, 480 },
2216 .vfront_porch = { 6, 10, 10 },
2217 .vback_porch = { 7, 11, 11 },
2218 .vsync_len = { 7, 11, 11 },
2219 .flags = DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH |
2220 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE |
2221 DISPLAY_FLAGS_SYNC_NEGEDGE,
2224 static const struct panel_desc evervision_vgg804821 = {
2225 .timings = &evervision_vgg804821_timing,
2232 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2233 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
2236 static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = {
2239 .hsync_start = 800 + 168,
2240 .hsync_end = 800 + 168 + 64,
2241 .htotal = 800 + 168 + 64 + 88,
2243 .vsync_start = 480 + 37,
2244 .vsync_end = 480 + 37 + 2,
2245 .vtotal = 480 + 37 + 2 + 8,
2248 static const struct panel_desc foxlink_fl500wvr00_a0t = {
2249 .modes = &foxlink_fl500wvr00_a0t_mode,
2256 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2259 static const struct drm_display_mode frida_frd350h54004_modes[] = {
2263 .hsync_start = 320 + 44,
2264 .hsync_end = 320 + 44 + 16,
2265 .htotal = 320 + 44 + 16 + 20,
2267 .vsync_start = 240 + 2,
2268 .vsync_end = 240 + 2 + 6,
2269 .vtotal = 240 + 2 + 6 + 2,
2270 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
2275 .hsync_start = 320 + 56,
2276 .hsync_end = 320 + 56 + 16,
2277 .htotal = 320 + 56 + 16 + 40,
2279 .vsync_start = 240 + 2,
2280 .vsync_end = 240 + 2 + 6,
2281 .vtotal = 240 + 2 + 6 + 2,
2282 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
2286 static const struct panel_desc frida_frd350h54004 = {
2287 .modes = frida_frd350h54004_modes,
2288 .num_modes = ARRAY_SIZE(frida_frd350h54004_modes),
2294 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2295 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
2296 .connector_type = DRM_MODE_CONNECTOR_DPI,
2299 static const struct drm_display_mode friendlyarm_hd702e_mode = {
2302 .hsync_start = 800 + 20,
2303 .hsync_end = 800 + 20 + 24,
2304 .htotal = 800 + 20 + 24 + 20,
2306 .vsync_start = 1280 + 4,
2307 .vsync_end = 1280 + 4 + 8,
2308 .vtotal = 1280 + 4 + 8 + 4,
2309 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2312 static const struct panel_desc friendlyarm_hd702e = {
2313 .modes = &friendlyarm_hd702e_mode,
2321 static const struct drm_display_mode giantplus_gpg482739qs5_mode = {
2324 .hsync_start = 480 + 5,
2325 .hsync_end = 480 + 5 + 1,
2326 .htotal = 480 + 5 + 1 + 40,
2328 .vsync_start = 272 + 8,
2329 .vsync_end = 272 + 8 + 1,
2330 .vtotal = 272 + 8 + 1 + 8,
2333 static const struct panel_desc giantplus_gpg482739qs5 = {
2334 .modes = &giantplus_gpg482739qs5_mode,
2341 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2344 static const struct display_timing giantplus_gpm940b0_timing = {
2345 .pixelclock = { 13500000, 27000000, 27500000 },
2346 .hactive = { 320, 320, 320 },
2347 .hfront_porch = { 14, 686, 718 },
2348 .hback_porch = { 50, 70, 255 },
2349 .hsync_len = { 1, 1, 1 },
2350 .vactive = { 240, 240, 240 },
2351 .vfront_porch = { 1, 1, 179 },
2352 .vback_porch = { 1, 21, 31 },
2353 .vsync_len = { 1, 1, 6 },
2354 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
2357 static const struct panel_desc giantplus_gpm940b0 = {
2358 .timings = &giantplus_gpm940b0_timing,
2365 .bus_format = MEDIA_BUS_FMT_RGB888_3X8,
2366 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
2369 static const struct display_timing hannstar_hsd070pww1_timing = {
2370 .pixelclock = { 64300000, 71100000, 82000000 },
2371 .hactive = { 1280, 1280, 1280 },
2372 .hfront_porch = { 1, 1, 10 },
2373 .hback_porch = { 1, 1, 10 },
2375 * According to the data sheet, the minimum horizontal blanking interval
2376 * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the
2377 * minimum working horizontal blanking interval to be 60 clocks.
2379 .hsync_len = { 58, 158, 661 },
2380 .vactive = { 800, 800, 800 },
2381 .vfront_porch = { 1, 1, 10 },
2382 .vback_porch = { 1, 1, 10 },
2383 .vsync_len = { 1, 21, 203 },
2384 .flags = DISPLAY_FLAGS_DE_HIGH,
2387 static const struct panel_desc hannstar_hsd070pww1 = {
2388 .timings = &hannstar_hsd070pww1_timing,
2395 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2396 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2399 static const struct display_timing hannstar_hsd100pxn1_timing = {
2400 .pixelclock = { 55000000, 65000000, 75000000 },
2401 .hactive = { 1024, 1024, 1024 },
2402 .hfront_porch = { 40, 40, 40 },
2403 .hback_porch = { 220, 220, 220 },
2404 .hsync_len = { 20, 60, 100 },
2405 .vactive = { 768, 768, 768 },
2406 .vfront_porch = { 7, 7, 7 },
2407 .vback_porch = { 21, 21, 21 },
2408 .vsync_len = { 10, 10, 10 },
2409 .flags = DISPLAY_FLAGS_DE_HIGH,
2412 static const struct panel_desc hannstar_hsd100pxn1 = {
2413 .timings = &hannstar_hsd100pxn1_timing,
2420 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2421 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2424 static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = {
2427 .hsync_start = 800 + 85,
2428 .hsync_end = 800 + 85 + 86,
2429 .htotal = 800 + 85 + 86 + 85,
2431 .vsync_start = 480 + 16,
2432 .vsync_end = 480 + 16 + 13,
2433 .vtotal = 480 + 16 + 13 + 16,
2436 static const struct panel_desc hitachi_tx23d38vm0caa = {
2437 .modes = &hitachi_tx23d38vm0caa_mode,
2450 static const struct drm_display_mode innolux_at043tn24_mode = {
2453 .hsync_start = 480 + 2,
2454 .hsync_end = 480 + 2 + 41,
2455 .htotal = 480 + 2 + 41 + 2,
2457 .vsync_start = 272 + 2,
2458 .vsync_end = 272 + 2 + 10,
2459 .vtotal = 272 + 2 + 10 + 2,
2460 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
2463 static const struct panel_desc innolux_at043tn24 = {
2464 .modes = &innolux_at043tn24_mode,
2471 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2472 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
2475 static const struct drm_display_mode innolux_at070tn92_mode = {
2478 .hsync_start = 800 + 210,
2479 .hsync_end = 800 + 210 + 20,
2480 .htotal = 800 + 210 + 20 + 46,
2482 .vsync_start = 480 + 22,
2483 .vsync_end = 480 + 22 + 10,
2484 .vtotal = 480 + 22 + 23 + 10,
2487 static const struct panel_desc innolux_at070tn92 = {
2488 .modes = &innolux_at070tn92_mode,
2494 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2497 static const struct display_timing innolux_g070y2_l01_timing = {
2498 .pixelclock = { 28000000, 29500000, 32000000 },
2499 .hactive = { 800, 800, 800 },
2500 .hfront_porch = { 61, 91, 141 },
2501 .hback_porch = { 60, 90, 140 },
2502 .hsync_len = { 12, 12, 12 },
2503 .vactive = { 480, 480, 480 },
2504 .vfront_porch = { 4, 9, 30 },
2505 .vback_porch = { 4, 8, 28 },
2506 .vsync_len = { 2, 2, 2 },
2507 .flags = DISPLAY_FLAGS_DE_HIGH,
2510 static const struct panel_desc innolux_g070y2_l01 = {
2511 .timings = &innolux_g070y2_l01_timing,
2524 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2525 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2526 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2529 static const struct display_timing innolux_g101ice_l01_timing = {
2530 .pixelclock = { 60400000, 71100000, 74700000 },
2531 .hactive = { 1280, 1280, 1280 },
2532 .hfront_porch = { 41, 80, 100 },
2533 .hback_porch = { 40, 79, 99 },
2534 .hsync_len = { 1, 1, 1 },
2535 .vactive = { 800, 800, 800 },
2536 .vfront_porch = { 5, 11, 14 },
2537 .vback_porch = { 4, 11, 14 },
2538 .vsync_len = { 1, 1, 1 },
2539 .flags = DISPLAY_FLAGS_DE_HIGH,
2542 static const struct panel_desc innolux_g101ice_l01 = {
2543 .timings = &innolux_g101ice_l01_timing,
2554 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2555 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2558 static const struct display_timing innolux_g121i1_l01_timing = {
2559 .pixelclock = { 67450000, 71000000, 74550000 },
2560 .hactive = { 1280, 1280, 1280 },
2561 .hfront_porch = { 40, 80, 160 },
2562 .hback_porch = { 39, 79, 159 },
2563 .hsync_len = { 1, 1, 1 },
2564 .vactive = { 800, 800, 800 },
2565 .vfront_porch = { 5, 11, 100 },
2566 .vback_porch = { 4, 11, 99 },
2567 .vsync_len = { 1, 1, 1 },
2570 static const struct panel_desc innolux_g121i1_l01 = {
2571 .timings = &innolux_g121i1_l01_timing,
2582 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2583 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2586 static const struct drm_display_mode innolux_g121x1_l03_mode = {
2589 .hsync_start = 1024 + 0,
2590 .hsync_end = 1024 + 1,
2591 .htotal = 1024 + 0 + 1 + 320,
2593 .vsync_start = 768 + 38,
2594 .vsync_end = 768 + 38 + 1,
2595 .vtotal = 768 + 38 + 1 + 0,
2596 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
2599 static const struct panel_desc innolux_g121x1_l03 = {
2600 .modes = &innolux_g121x1_l03_mode,
2614 static const struct drm_display_mode innolux_n116bca_ea1_mode = {
2617 .hsync_start = 1366 + 136,
2618 .hsync_end = 1366 + 136 + 30,
2619 .htotal = 1366 + 136 + 30 + 60,
2621 .vsync_start = 768 + 8,
2622 .vsync_end = 768 + 8 + 12,
2623 .vtotal = 768 + 8 + 12 + 12,
2624 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
2627 static const struct panel_desc innolux_n116bca_ea1 = {
2628 .modes = &innolux_n116bca_ea1_mode,
2636 .hpd_absent_delay = 200,
2637 .prepare_to_enable = 80,
2640 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2641 .connector_type = DRM_MODE_CONNECTOR_eDP,
2645 * Datasheet specifies that at 60 Hz refresh rate:
2646 * - total horizontal time: { 1506, 1592, 1716 }
2647 * - total vertical time: { 788, 800, 868 }
2649 * ...but doesn't go into exactly how that should be split into a front
2650 * porch, back porch, or sync length. For now we'll leave a single setting
2651 * here which allows a bit of tweaking of the pixel clock at the expense of
2654 static const struct display_timing innolux_n116bge_timing = {
2655 .pixelclock = { 72600000, 76420000, 80240000 },
2656 .hactive = { 1366, 1366, 1366 },
2657 .hfront_porch = { 136, 136, 136 },
2658 .hback_porch = { 60, 60, 60 },
2659 .hsync_len = { 30, 30, 30 },
2660 .vactive = { 768, 768, 768 },
2661 .vfront_porch = { 8, 8, 8 },
2662 .vback_porch = { 12, 12, 12 },
2663 .vsync_len = { 12, 12, 12 },
2664 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW,
2667 static const struct panel_desc innolux_n116bge = {
2668 .timings = &innolux_n116bge_timing,
2675 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2676 .connector_type = DRM_MODE_CONNECTOR_eDP,
2679 static const struct drm_display_mode innolux_n125hce_gn1_mode = {
2682 .hsync_start = 1920 + 40,
2683 .hsync_end = 1920 + 40 + 40,
2684 .htotal = 1920 + 40 + 40 + 80,
2686 .vsync_start = 1080 + 4,
2687 .vsync_end = 1080 + 4 + 4,
2688 .vtotal = 1080 + 4 + 4 + 24,
2691 static const struct panel_desc innolux_n125hce_gn1 = {
2692 .modes = &innolux_n125hce_gn1_mode,
2699 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2700 .bus_flags = DRM_BUS_FLAG_DATA_MSB_TO_LSB,
2701 .connector_type = DRM_MODE_CONNECTOR_eDP,
2704 static const struct drm_display_mode innolux_n156bge_l21_mode = {
2707 .hsync_start = 1366 + 16,
2708 .hsync_end = 1366 + 16 + 34,
2709 .htotal = 1366 + 16 + 34 + 50,
2711 .vsync_start = 768 + 2,
2712 .vsync_end = 768 + 2 + 6,
2713 .vtotal = 768 + 2 + 6 + 12,
2716 static const struct panel_desc innolux_n156bge_l21 = {
2717 .modes = &innolux_n156bge_l21_mode,
2724 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2725 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2726 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2729 static const struct drm_display_mode innolux_p120zdg_bf1_mode = {
2732 .hsync_start = 2160 + 48,
2733 .hsync_end = 2160 + 48 + 32,
2734 .htotal = 2160 + 48 + 32 + 80,
2736 .vsync_start = 1440 + 3,
2737 .vsync_end = 1440 + 3 + 10,
2738 .vtotal = 1440 + 3 + 10 + 27,
2739 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
2742 static const struct panel_desc innolux_p120zdg_bf1 = {
2743 .modes = &innolux_p120zdg_bf1_mode,
2751 .hpd_absent_delay = 200,
2756 static const struct drm_display_mode innolux_zj070na_01p_mode = {
2759 .hsync_start = 1024 + 128,
2760 .hsync_end = 1024 + 128 + 64,
2761 .htotal = 1024 + 128 + 64 + 128,
2763 .vsync_start = 600 + 16,
2764 .vsync_end = 600 + 16 + 4,
2765 .vtotal = 600 + 16 + 4 + 16,
2768 static const struct panel_desc innolux_zj070na_01p = {
2769 .modes = &innolux_zj070na_01p_mode,
2778 static const struct drm_display_mode ivo_m133nwf4_r0_mode = {
2781 .hsync_start = 1920 + 24,
2782 .hsync_end = 1920 + 24 + 48,
2783 .htotal = 1920 + 24 + 48 + 88,
2785 .vsync_start = 1080 + 3,
2786 .vsync_end = 1080 + 3 + 12,
2787 .vtotal = 1080 + 3 + 12 + 17,
2788 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
2791 static const struct panel_desc ivo_m133nwf4_r0 = {
2792 .modes = &ivo_m133nwf4_r0_mode,
2800 .hpd_absent_delay = 200,
2803 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2804 .bus_flags = DRM_BUS_FLAG_DATA_MSB_TO_LSB,
2805 .connector_type = DRM_MODE_CONNECTOR_eDP,
2808 static const struct drm_display_mode kingdisplay_kd116n21_30nv_a010_mode = {
2811 .hsync_start = 1366 + 40,
2812 .hsync_end = 1366 + 40 + 32,
2813 .htotal = 1366 + 40 + 32 + 62,
2815 .vsync_start = 768 + 5,
2816 .vsync_end = 768 + 5 + 5,
2817 .vtotal = 768 + 5 + 5 + 122,
2818 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2821 static const struct panel_desc kingdisplay_kd116n21_30nv_a010 = {
2822 .modes = &kingdisplay_kd116n21_30nv_a010_mode,
2830 .hpd_absent_delay = 200,
2832 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2833 .connector_type = DRM_MODE_CONNECTOR_eDP,
2836 static const struct display_timing koe_tx14d24vm1bpa_timing = {
2837 .pixelclock = { 5580000, 5850000, 6200000 },
2838 .hactive = { 320, 320, 320 },
2839 .hfront_porch = { 30, 30, 30 },
2840 .hback_porch = { 30, 30, 30 },
2841 .hsync_len = { 1, 5, 17 },
2842 .vactive = { 240, 240, 240 },
2843 .vfront_porch = { 6, 6, 6 },
2844 .vback_porch = { 5, 5, 5 },
2845 .vsync_len = { 1, 2, 11 },
2846 .flags = DISPLAY_FLAGS_DE_HIGH,
2849 static const struct panel_desc koe_tx14d24vm1bpa = {
2850 .timings = &koe_tx14d24vm1bpa_timing,
2859 static const struct display_timing koe_tx26d202vm0bwa_timing = {
2860 .pixelclock = { 151820000, 156720000, 159780000 },
2861 .hactive = { 1920, 1920, 1920 },
2862 .hfront_porch = { 105, 130, 142 },
2863 .hback_porch = { 45, 70, 82 },
2864 .hsync_len = { 30, 30, 30 },
2865 .vactive = { 1200, 1200, 1200},
2866 .vfront_porch = { 3, 5, 10 },
2867 .vback_porch = { 2, 5, 10 },
2868 .vsync_len = { 5, 5, 5 },
2871 static const struct panel_desc koe_tx26d202vm0bwa = {
2872 .timings = &koe_tx26d202vm0bwa_timing,
2885 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2886 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2887 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2890 static const struct display_timing koe_tx31d200vm0baa_timing = {
2891 .pixelclock = { 39600000, 43200000, 48000000 },
2892 .hactive = { 1280, 1280, 1280 },
2893 .hfront_porch = { 16, 36, 56 },
2894 .hback_porch = { 16, 36, 56 },
2895 .hsync_len = { 8, 8, 8 },
2896 .vactive = { 480, 480, 480 },
2897 .vfront_porch = { 6, 21, 33 },
2898 .vback_porch = { 6, 21, 33 },
2899 .vsync_len = { 8, 8, 8 },
2900 .flags = DISPLAY_FLAGS_DE_HIGH,
2903 static const struct panel_desc koe_tx31d200vm0baa = {
2904 .timings = &koe_tx31d200vm0baa_timing,
2911 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2912 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2915 static const struct display_timing kyo_tcg121xglp_timing = {
2916 .pixelclock = { 52000000, 65000000, 71000000 },
2917 .hactive = { 1024, 1024, 1024 },
2918 .hfront_porch = { 2, 2, 2 },
2919 .hback_porch = { 2, 2, 2 },
2920 .hsync_len = { 86, 124, 244 },
2921 .vactive = { 768, 768, 768 },
2922 .vfront_porch = { 2, 2, 2 },
2923 .vback_porch = { 2, 2, 2 },
2924 .vsync_len = { 6, 34, 73 },
2925 .flags = DISPLAY_FLAGS_DE_HIGH,
2928 static const struct panel_desc kyo_tcg121xglp = {
2929 .timings = &kyo_tcg121xglp_timing,
2936 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2937 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2940 static const struct drm_display_mode lemaker_bl035_rgb_002_mode = {
2943 .hsync_start = 320 + 20,
2944 .hsync_end = 320 + 20 + 30,
2945 .htotal = 320 + 20 + 30 + 38,
2947 .vsync_start = 240 + 4,
2948 .vsync_end = 240 + 4 + 3,
2949 .vtotal = 240 + 4 + 3 + 15,
2952 static const struct panel_desc lemaker_bl035_rgb_002 = {
2953 .modes = &lemaker_bl035_rgb_002_mode,
2959 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2960 .bus_flags = DRM_BUS_FLAG_DE_LOW,
2963 static const struct drm_display_mode lg_lb070wv8_mode = {
2966 .hsync_start = 800 + 88,
2967 .hsync_end = 800 + 88 + 80,
2968 .htotal = 800 + 88 + 80 + 88,
2970 .vsync_start = 480 + 10,
2971 .vsync_end = 480 + 10 + 25,
2972 .vtotal = 480 + 10 + 25 + 10,
2975 static const struct panel_desc lg_lb070wv8 = {
2976 .modes = &lg_lb070wv8_mode,
2983 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2984 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2987 static const struct drm_display_mode lg_lp079qx1_sp0v_mode = {
2990 .hsync_start = 1536 + 12,
2991 .hsync_end = 1536 + 12 + 16,
2992 .htotal = 1536 + 12 + 16 + 48,
2994 .vsync_start = 2048 + 8,
2995 .vsync_end = 2048 + 8 + 4,
2996 .vtotal = 2048 + 8 + 4 + 8,
2997 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3000 static const struct panel_desc lg_lp079qx1_sp0v = {
3001 .modes = &lg_lp079qx1_sp0v_mode,
3009 static const struct drm_display_mode lg_lp097qx1_spa1_mode = {
3012 .hsync_start = 2048 + 150,
3013 .hsync_end = 2048 + 150 + 5,
3014 .htotal = 2048 + 150 + 5 + 5,
3016 .vsync_start = 1536 + 3,
3017 .vsync_end = 1536 + 3 + 1,
3018 .vtotal = 1536 + 3 + 1 + 9,
3021 static const struct panel_desc lg_lp097qx1_spa1 = {
3022 .modes = &lg_lp097qx1_spa1_mode,
3030 static const struct drm_display_mode lg_lp120up1_mode = {
3033 .hsync_start = 1920 + 40,
3034 .hsync_end = 1920 + 40 + 40,
3035 .htotal = 1920 + 40 + 40+ 80,
3037 .vsync_start = 1280 + 4,
3038 .vsync_end = 1280 + 4 + 4,
3039 .vtotal = 1280 + 4 + 4 + 12,
3042 static const struct panel_desc lg_lp120up1 = {
3043 .modes = &lg_lp120up1_mode,
3050 .connector_type = DRM_MODE_CONNECTOR_eDP,
3053 static const struct drm_display_mode lg_lp129qe_mode = {
3056 .hsync_start = 2560 + 48,
3057 .hsync_end = 2560 + 48 + 32,
3058 .htotal = 2560 + 48 + 32 + 80,
3060 .vsync_start = 1700 + 3,
3061 .vsync_end = 1700 + 3 + 10,
3062 .vtotal = 1700 + 3 + 10 + 36,
3065 static const struct panel_desc lg_lp129qe = {
3066 .modes = &lg_lp129qe_mode,
3075 static const struct display_timing logictechno_lt161010_2nh_timing = {
3076 .pixelclock = { 26400000, 33300000, 46800000 },
3077 .hactive = { 800, 800, 800 },
3078 .hfront_porch = { 16, 210, 354 },
3079 .hback_porch = { 46, 46, 46 },
3080 .hsync_len = { 1, 20, 40 },
3081 .vactive = { 480, 480, 480 },
3082 .vfront_porch = { 7, 22, 147 },
3083 .vback_porch = { 23, 23, 23 },
3084 .vsync_len = { 1, 10, 20 },
3085 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
3086 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
3087 DISPLAY_FLAGS_SYNC_POSEDGE,
3090 static const struct panel_desc logictechno_lt161010_2nh = {
3091 .timings = &logictechno_lt161010_2nh_timing,
3097 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3098 .bus_flags = DRM_BUS_FLAG_DE_HIGH |
3099 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
3100 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
3101 .connector_type = DRM_MODE_CONNECTOR_DPI,
3104 static const struct display_timing logictechno_lt170410_2whc_timing = {
3105 .pixelclock = { 68900000, 71100000, 73400000 },
3106 .hactive = { 1280, 1280, 1280 },
3107 .hfront_porch = { 23, 60, 71 },
3108 .hback_porch = { 23, 60, 71 },
3109 .hsync_len = { 15, 40, 47 },
3110 .vactive = { 800, 800, 800 },
3111 .vfront_porch = { 5, 7, 10 },
3112 .vback_porch = { 5, 7, 10 },
3113 .vsync_len = { 6, 9, 12 },
3114 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
3115 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
3116 DISPLAY_FLAGS_SYNC_POSEDGE,
3119 static const struct panel_desc logictechno_lt170410_2whc = {
3120 .timings = &logictechno_lt170410_2whc_timing,
3126 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3127 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
3128 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3131 static const struct drm_display_mode logictechno_lttd800480070_l6wh_rt_mode = {
3134 .hsync_start = 800 + 154,
3135 .hsync_end = 800 + 154 + 3,
3136 .htotal = 800 + 154 + 3 + 43,
3138 .vsync_start = 480 + 47,
3139 .vsync_end = 480 + 47 + 3,
3140 .vtotal = 480 + 47 + 3 + 20,
3141 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3144 static const struct panel_desc logictechno_lttd800480070_l6wh_rt = {
3145 .modes = &logictechno_lttd800480070_l6wh_rt_mode,
3158 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3159 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
3160 .connector_type = DRM_MODE_CONNECTOR_DPI,
3163 static const struct drm_display_mode mitsubishi_aa070mc01_mode = {
3166 .hsync_start = 800 + 0,
3167 .hsync_end = 800 + 1,
3168 .htotal = 800 + 0 + 1 + 160,
3170 .vsync_start = 480 + 0,
3171 .vsync_end = 480 + 48 + 1,
3172 .vtotal = 480 + 48 + 1 + 0,
3173 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
3176 static const struct drm_display_mode logicpd_type_28_mode = {
3179 .hsync_start = 480 + 3,
3180 .hsync_end = 480 + 3 + 42,
3181 .htotal = 480 + 3 + 42 + 2,
3184 .vsync_start = 272 + 2,
3185 .vsync_end = 272 + 2 + 11,
3186 .vtotal = 272 + 2 + 11 + 3,
3187 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
3190 static const struct panel_desc logicpd_type_28 = {
3191 .modes = &logicpd_type_28_mode,
3204 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3205 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE |
3206 DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE,
3207 .connector_type = DRM_MODE_CONNECTOR_DPI,
3210 static const struct panel_desc mitsubishi_aa070mc01 = {
3211 .modes = &mitsubishi_aa070mc01_mode,
3224 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3225 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3226 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
3229 static const struct display_timing multi_inno_mi1010ait_1cp_timing = {
3230 .pixelclock = { 68900000, 70000000, 73400000 },
3231 .hactive = { 1280, 1280, 1280 },
3232 .hfront_porch = { 30, 60, 71 },
3233 .hback_porch = { 30, 60, 71 },
3234 .hsync_len = { 10, 10, 48 },
3235 .vactive = { 800, 800, 800 },
3236 .vfront_porch = { 5, 10, 10 },
3237 .vback_porch = { 5, 10, 10 },
3238 .vsync_len = { 5, 6, 13 },
3239 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
3240 DISPLAY_FLAGS_DE_HIGH,
3243 static const struct panel_desc multi_inno_mi1010ait_1cp = {
3244 .timings = &multi_inno_mi1010ait_1cp_timing,
3255 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3256 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
3257 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3260 static const struct display_timing nec_nl12880bc20_05_timing = {
3261 .pixelclock = { 67000000, 71000000, 75000000 },
3262 .hactive = { 1280, 1280, 1280 },
3263 .hfront_porch = { 2, 30, 30 },
3264 .hback_porch = { 6, 100, 100 },
3265 .hsync_len = { 2, 30, 30 },
3266 .vactive = { 800, 800, 800 },
3267 .vfront_porch = { 5, 5, 5 },
3268 .vback_porch = { 11, 11, 11 },
3269 .vsync_len = { 7, 7, 7 },
3272 static const struct panel_desc nec_nl12880bc20_05 = {
3273 .timings = &nec_nl12880bc20_05_timing,
3284 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3285 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3288 static const struct drm_display_mode nec_nl4827hc19_05b_mode = {
3291 .hsync_start = 480 + 2,
3292 .hsync_end = 480 + 2 + 41,
3293 .htotal = 480 + 2 + 41 + 2,
3295 .vsync_start = 272 + 2,
3296 .vsync_end = 272 + 2 + 4,
3297 .vtotal = 272 + 2 + 4 + 2,
3298 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3301 static const struct panel_desc nec_nl4827hc19_05b = {
3302 .modes = &nec_nl4827hc19_05b_mode,
3309 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3310 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
3313 static const struct drm_display_mode netron_dy_e231732_mode = {
3316 .hsync_start = 1024 + 160,
3317 .hsync_end = 1024 + 160 + 70,
3318 .htotal = 1024 + 160 + 70 + 90,
3320 .vsync_start = 600 + 127,
3321 .vsync_end = 600 + 127 + 20,
3322 .vtotal = 600 + 127 + 20 + 3,
3325 static const struct panel_desc netron_dy_e231732 = {
3326 .modes = &netron_dy_e231732_mode,
3332 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3335 static const struct drm_display_mode neweast_wjfh116008a_modes[] = {
3339 .hsync_start = 1920 + 48,
3340 .hsync_end = 1920 + 48 + 32,
3341 .htotal = 1920 + 48 + 32 + 80,
3343 .vsync_start = 1080 + 3,
3344 .vsync_end = 1080 + 3 + 5,
3345 .vtotal = 1080 + 3 + 5 + 23,
3346 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3350 .hsync_start = 1920 + 48,
3351 .hsync_end = 1920 + 48 + 32,
3352 .htotal = 1920 + 48 + 32 + 80,
3354 .vsync_start = 1080 + 3,
3355 .vsync_end = 1080 + 3 + 5,
3356 .vtotal = 1080 + 3 + 5 + 23,
3357 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3361 static const struct panel_desc neweast_wjfh116008a = {
3362 .modes = neweast_wjfh116008a_modes,
3374 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3375 .connector_type = DRM_MODE_CONNECTOR_eDP,
3378 static const struct drm_display_mode newhaven_nhd_43_480272ef_atxl_mode = {
3381 .hsync_start = 480 + 2,
3382 .hsync_end = 480 + 2 + 41,
3383 .htotal = 480 + 2 + 41 + 2,
3385 .vsync_start = 272 + 2,
3386 .vsync_end = 272 + 2 + 10,
3387 .vtotal = 272 + 2 + 10 + 2,
3388 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3391 static const struct panel_desc newhaven_nhd_43_480272ef_atxl = {
3392 .modes = &newhaven_nhd_43_480272ef_atxl_mode,
3399 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3400 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE |
3401 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
3402 .connector_type = DRM_MODE_CONNECTOR_DPI,
3405 static const struct display_timing nlt_nl192108ac18_02d_timing = {
3406 .pixelclock = { 130000000, 148350000, 163000000 },
3407 .hactive = { 1920, 1920, 1920 },
3408 .hfront_porch = { 80, 100, 100 },
3409 .hback_porch = { 100, 120, 120 },
3410 .hsync_len = { 50, 60, 60 },
3411 .vactive = { 1080, 1080, 1080 },
3412 .vfront_porch = { 12, 30, 30 },
3413 .vback_porch = { 4, 10, 10 },
3414 .vsync_len = { 4, 5, 5 },
3417 static const struct panel_desc nlt_nl192108ac18_02d = {
3418 .timings = &nlt_nl192108ac18_02d_timing,
3428 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3429 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3432 static const struct drm_display_mode nvd_9128_mode = {
3435 .hsync_start = 800 + 130,
3436 .hsync_end = 800 + 130 + 98,
3437 .htotal = 800 + 0 + 130 + 98,
3439 .vsync_start = 480 + 10,
3440 .vsync_end = 480 + 10 + 50,
3441 .vtotal = 480 + 0 + 10 + 50,
3444 static const struct panel_desc nvd_9128 = {
3445 .modes = &nvd_9128_mode,
3452 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3453 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3456 static const struct display_timing okaya_rs800480t_7x0gp_timing = {
3457 .pixelclock = { 30000000, 30000000, 40000000 },
3458 .hactive = { 800, 800, 800 },
3459 .hfront_porch = { 40, 40, 40 },
3460 .hback_porch = { 40, 40, 40 },
3461 .hsync_len = { 1, 48, 48 },
3462 .vactive = { 480, 480, 480 },
3463 .vfront_porch = { 13, 13, 13 },
3464 .vback_porch = { 29, 29, 29 },
3465 .vsync_len = { 3, 3, 3 },
3466 .flags = DISPLAY_FLAGS_DE_HIGH,
3469 static const struct panel_desc okaya_rs800480t_7x0gp = {
3470 .timings = &okaya_rs800480t_7x0gp_timing,
3483 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3486 static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode = {
3489 .hsync_start = 480 + 5,
3490 .hsync_end = 480 + 5 + 30,
3491 .htotal = 480 + 5 + 30 + 10,
3493 .vsync_start = 272 + 8,
3494 .vsync_end = 272 + 8 + 5,
3495 .vtotal = 272 + 8 + 5 + 3,
3498 static const struct panel_desc olimex_lcd_olinuxino_43ts = {
3499 .modes = &olimex_lcd_olinuxino_43ts_mode,
3505 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3509 * 800x480 CVT. The panel appears to be quite accepting, at least as far as
3510 * pixel clocks, but this is the timing that was being used in the Adafruit
3511 * installation instructions.
3513 static const struct drm_display_mode ontat_yx700wv03_mode = {
3523 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3528 * https://www.adafruit.com/images/product-files/2406/c3163.pdf
3530 static const struct panel_desc ontat_yx700wv03 = {
3531 .modes = &ontat_yx700wv03_mode,
3538 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3541 static const struct drm_display_mode ortustech_com37h3m_mode = {
3544 .hsync_start = 480 + 40,
3545 .hsync_end = 480 + 40 + 10,
3546 .htotal = 480 + 40 + 10 + 40,
3548 .vsync_start = 640 + 4,
3549 .vsync_end = 640 + 4 + 2,
3550 .vtotal = 640 + 4 + 2 + 4,
3551 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3554 static const struct panel_desc ortustech_com37h3m = {
3555 .modes = &ortustech_com37h3m_mode,
3559 .width = 56, /* 56.16mm */
3560 .height = 75, /* 74.88mm */
3562 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3563 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
3564 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
3567 static const struct drm_display_mode ortustech_com43h4m85ulc_mode = {
3570 .hsync_start = 480 + 10,
3571 .hsync_end = 480 + 10 + 10,
3572 .htotal = 480 + 10 + 10 + 15,
3574 .vsync_start = 800 + 3,
3575 .vsync_end = 800 + 3 + 3,
3576 .vtotal = 800 + 3 + 3 + 3,
3579 static const struct panel_desc ortustech_com43h4m85ulc = {
3580 .modes = &ortustech_com43h4m85ulc_mode,
3587 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3588 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
3589 .connector_type = DRM_MODE_CONNECTOR_DPI,
3592 static const struct drm_display_mode osddisplays_osd070t1718_19ts_mode = {
3595 .hsync_start = 800 + 210,
3596 .hsync_end = 800 + 210 + 30,
3597 .htotal = 800 + 210 + 30 + 16,
3599 .vsync_start = 480 + 22,
3600 .vsync_end = 480 + 22 + 13,
3601 .vtotal = 480 + 22 + 13 + 10,
3602 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3605 static const struct panel_desc osddisplays_osd070t1718_19ts = {
3606 .modes = &osddisplays_osd070t1718_19ts_mode,
3613 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3614 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE |
3615 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
3616 .connector_type = DRM_MODE_CONNECTOR_DPI,
3619 static const struct drm_display_mode pda_91_00156_a0_mode = {
3622 .hsync_start = 800 + 1,
3623 .hsync_end = 800 + 1 + 64,
3624 .htotal = 800 + 1 + 64 + 64,
3626 .vsync_start = 480 + 1,
3627 .vsync_end = 480 + 1 + 23,
3628 .vtotal = 480 + 1 + 23 + 22,
3631 static const struct panel_desc pda_91_00156_a0 = {
3632 .modes = &pda_91_00156_a0_mode,
3638 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3641 static const struct drm_display_mode powertip_ph800480t013_idf02_mode = {
3644 .hsync_start = 800 + 54,
3645 .hsync_end = 800 + 54 + 2,
3646 .htotal = 800 + 54 + 2 + 44,
3648 .vsync_start = 480 + 49,
3649 .vsync_end = 480 + 49 + 2,
3650 .vtotal = 480 + 49 + 2 + 22,
3653 static const struct panel_desc powertip_ph800480t013_idf02 = {
3654 .modes = &powertip_ph800480t013_idf02_mode,
3660 .bus_flags = DRM_BUS_FLAG_DE_HIGH |
3661 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
3662 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
3663 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3664 .connector_type = DRM_MODE_CONNECTOR_DPI,
3667 static const struct drm_display_mode qd43003c0_40_mode = {
3670 .hsync_start = 480 + 8,
3671 .hsync_end = 480 + 8 + 4,
3672 .htotal = 480 + 8 + 4 + 39,
3674 .vsync_start = 272 + 4,
3675 .vsync_end = 272 + 4 + 10,
3676 .vtotal = 272 + 4 + 10 + 2,
3679 static const struct panel_desc qd43003c0_40 = {
3680 .modes = &qd43003c0_40_mode,
3687 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3690 static const struct drm_display_mode qishenglong_gopher2b_lcd_modes[] = {
3694 .hsync_start = 480 + 77,
3695 .hsync_end = 480 + 77 + 41,
3696 .htotal = 480 + 77 + 41 + 2,
3698 .vsync_start = 272 + 16,
3699 .vsync_end = 272 + 16 + 10,
3700 .vtotal = 272 + 16 + 10 + 2,
3701 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3706 .hsync_start = 480 + 17,
3707 .hsync_end = 480 + 17 + 41,
3708 .htotal = 480 + 17 + 41 + 2,
3710 .vsync_start = 272 + 116,
3711 .vsync_end = 272 + 116 + 10,
3712 .vtotal = 272 + 116 + 10 + 2,
3713 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3717 static const struct panel_desc qishenglong_gopher2b_lcd = {
3718 .modes = qishenglong_gopher2b_lcd_modes,
3719 .num_modes = ARRAY_SIZE(qishenglong_gopher2b_lcd_modes),
3725 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3726 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
3727 .connector_type = DRM_MODE_CONNECTOR_DPI,
3730 static const struct display_timing rocktech_rk070er9427_timing = {
3731 .pixelclock = { 26400000, 33300000, 46800000 },
3732 .hactive = { 800, 800, 800 },
3733 .hfront_porch = { 16, 210, 354 },
3734 .hback_porch = { 46, 46, 46 },
3735 .hsync_len = { 1, 1, 1 },
3736 .vactive = { 480, 480, 480 },
3737 .vfront_porch = { 7, 22, 147 },
3738 .vback_porch = { 23, 23, 23 },
3739 .vsync_len = { 1, 1, 1 },
3740 .flags = DISPLAY_FLAGS_DE_HIGH,
3743 static const struct panel_desc rocktech_rk070er9427 = {
3744 .timings = &rocktech_rk070er9427_timing,
3757 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3760 static const struct drm_display_mode rocktech_rk101ii01d_ct_mode = {
3763 .hsync_start = 1280 + 48,
3764 .hsync_end = 1280 + 48 + 32,
3765 .htotal = 1280 + 48 + 32 + 80,
3767 .vsync_start = 800 + 2,
3768 .vsync_end = 800 + 2 + 5,
3769 .vtotal = 800 + 2 + 5 + 16,
3772 static const struct panel_desc rocktech_rk101ii01d_ct = {
3773 .modes = &rocktech_rk101ii01d_ct_mode,
3783 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
3784 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3785 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3788 static const struct drm_display_mode samsung_lsn122dl01_c01_mode = {
3791 .hsync_start = 2560 + 48,
3792 .hsync_end = 2560 + 48 + 32,
3793 .htotal = 2560 + 48 + 32 + 80,
3795 .vsync_start = 1600 + 2,
3796 .vsync_end = 1600 + 2 + 5,
3797 .vtotal = 1600 + 2 + 5 + 57,
3800 static const struct panel_desc samsung_lsn122dl01_c01 = {
3801 .modes = &samsung_lsn122dl01_c01_mode,
3809 static const struct drm_display_mode samsung_ltn101nt05_mode = {
3812 .hsync_start = 1024 + 24,
3813 .hsync_end = 1024 + 24 + 136,
3814 .htotal = 1024 + 24 + 136 + 160,
3816 .vsync_start = 600 + 3,
3817 .vsync_end = 600 + 3 + 6,
3818 .vtotal = 600 + 3 + 6 + 61,
3821 static const struct panel_desc samsung_ltn101nt05 = {
3822 .modes = &samsung_ltn101nt05_mode,
3829 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
3830 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
3831 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3834 static const struct drm_display_mode samsung_ltn140at29_301_mode = {
3837 .hsync_start = 1366 + 64,
3838 .hsync_end = 1366 + 64 + 48,
3839 .htotal = 1366 + 64 + 48 + 128,
3841 .vsync_start = 768 + 2,
3842 .vsync_end = 768 + 2 + 5,
3843 .vtotal = 768 + 2 + 5 + 17,
3846 static const struct panel_desc samsung_ltn140at29_301 = {
3847 .modes = &samsung_ltn140at29_301_mode,
3856 static const struct display_timing satoz_sat050at40h12r2_timing = {
3857 .pixelclock = {33300000, 33300000, 50000000},
3858 .hactive = {800, 800, 800},
3859 .hfront_porch = {16, 210, 354},
3860 .hback_porch = {46, 46, 46},
3861 .hsync_len = {1, 1, 40},
3862 .vactive = {480, 480, 480},
3863 .vfront_porch = {7, 22, 147},
3864 .vback_porch = {23, 23, 23},
3865 .vsync_len = {1, 1, 20},
3868 static const struct panel_desc satoz_sat050at40h12r2 = {
3869 .timings = &satoz_sat050at40h12r2_timing,
3876 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3877 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3880 static const struct drm_display_mode sharp_ld_d5116z01b_mode = {
3883 .hsync_start = 1920 + 48,
3884 .hsync_end = 1920 + 48 + 32,
3885 .htotal = 1920 + 48 + 32 + 80,
3887 .vsync_start = 1280 + 3,
3888 .vsync_end = 1280 + 3 + 10,
3889 .vtotal = 1280 + 3 + 10 + 57,
3890 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
3893 static const struct panel_desc sharp_ld_d5116z01b = {
3894 .modes = &sharp_ld_d5116z01b_mode,
3901 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3902 .bus_flags = DRM_BUS_FLAG_DATA_MSB_TO_LSB,
3905 static const struct drm_display_mode sharp_lq070y3dg3b_mode = {
3908 .hsync_start = 800 + 64,
3909 .hsync_end = 800 + 64 + 128,
3910 .htotal = 800 + 64 + 128 + 64,
3912 .vsync_start = 480 + 8,
3913 .vsync_end = 480 + 8 + 2,
3914 .vtotal = 480 + 8 + 2 + 35,
3915 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE,
3918 static const struct panel_desc sharp_lq070y3dg3b = {
3919 .modes = &sharp_lq070y3dg3b_mode,
3923 .width = 152, /* 152.4mm */
3924 .height = 91, /* 91.4mm */
3926 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3927 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
3928 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
3931 static const struct drm_display_mode sharp_lq035q7db03_mode = {
3934 .hsync_start = 240 + 16,
3935 .hsync_end = 240 + 16 + 7,
3936 .htotal = 240 + 16 + 7 + 5,
3938 .vsync_start = 320 + 9,
3939 .vsync_end = 320 + 9 + 1,
3940 .vtotal = 320 + 9 + 1 + 7,
3943 static const struct panel_desc sharp_lq035q7db03 = {
3944 .modes = &sharp_lq035q7db03_mode,
3951 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3954 static const struct display_timing sharp_lq101k1ly04_timing = {
3955 .pixelclock = { 60000000, 65000000, 80000000 },
3956 .hactive = { 1280, 1280, 1280 },
3957 .hfront_porch = { 20, 20, 20 },
3958 .hback_porch = { 20, 20, 20 },
3959 .hsync_len = { 10, 10, 10 },
3960 .vactive = { 800, 800, 800 },
3961 .vfront_porch = { 4, 4, 4 },
3962 .vback_porch = { 4, 4, 4 },
3963 .vsync_len = { 4, 4, 4 },
3964 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE,
3967 static const struct panel_desc sharp_lq101k1ly04 = {
3968 .timings = &sharp_lq101k1ly04_timing,
3975 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
3976 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3979 static const struct display_timing sharp_lq123p1jx31_timing = {
3980 .pixelclock = { 252750000, 252750000, 266604720 },
3981 .hactive = { 2400, 2400, 2400 },
3982 .hfront_porch = { 48, 48, 48 },
3983 .hback_porch = { 80, 80, 84 },
3984 .hsync_len = { 32, 32, 32 },
3985 .vactive = { 1600, 1600, 1600 },
3986 .vfront_porch = { 3, 3, 3 },
3987 .vback_porch = { 33, 33, 120 },
3988 .vsync_len = { 10, 10, 10 },
3989 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW,
3992 static const struct panel_desc sharp_lq123p1jx31 = {
3993 .timings = &sharp_lq123p1jx31_timing,
4007 static const struct drm_display_mode sharp_ls020b1dd01d_modes[] = {
4011 .hsync_start = 240 + 58,
4012 .hsync_end = 240 + 58 + 1,
4013 .htotal = 240 + 58 + 1 + 1,
4015 .vsync_start = 160 + 24,
4016 .vsync_end = 160 + 24 + 10,
4017 .vtotal = 160 + 24 + 10 + 6,
4018 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC,
4023 .hsync_start = 240 + 8,
4024 .hsync_end = 240 + 8 + 1,
4025 .htotal = 240 + 8 + 1 + 1,
4027 .vsync_start = 160 + 24,
4028 .vsync_end = 160 + 24 + 10,
4029 .vtotal = 160 + 24 + 10 + 6,
4030 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC,
4034 static const struct panel_desc sharp_ls020b1dd01d = {
4035 .modes = sharp_ls020b1dd01d_modes,
4036 .num_modes = ARRAY_SIZE(sharp_ls020b1dd01d_modes),
4042 .bus_format = MEDIA_BUS_FMT_RGB565_1X16,
4043 .bus_flags = DRM_BUS_FLAG_DE_HIGH
4044 | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE
4045 | DRM_BUS_FLAG_SHARP_SIGNALS,
4048 static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = {
4051 .hsync_start = 800 + 1,
4052 .hsync_end = 800 + 1 + 64,
4053 .htotal = 800 + 1 + 64 + 64,
4055 .vsync_start = 480 + 1,
4056 .vsync_end = 480 + 1 + 23,
4057 .vtotal = 480 + 1 + 23 + 22,
4060 static const struct panel_desc shelly_sca07010_bfn_lnn = {
4061 .modes = &shelly_sca07010_bfn_lnn_mode,
4067 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
4070 static const struct drm_display_mode starry_kr070pe2t_mode = {
4073 .hsync_start = 800 + 209,
4074 .hsync_end = 800 + 209 + 1,
4075 .htotal = 800 + 209 + 1 + 45,
4077 .vsync_start = 480 + 22,
4078 .vsync_end = 480 + 22 + 1,
4079 .vtotal = 480 + 22 + 1 + 22,
4082 static const struct panel_desc starry_kr070pe2t = {
4083 .modes = &starry_kr070pe2t_mode,
4090 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
4091 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
4092 .connector_type = DRM_MODE_CONNECTOR_DPI,
4095 static const struct drm_display_mode starry_kr122ea0sra_mode = {
4098 .hsync_start = 1920 + 16,
4099 .hsync_end = 1920 + 16 + 16,
4100 .htotal = 1920 + 16 + 16 + 32,
4102 .vsync_start = 1200 + 15,
4103 .vsync_end = 1200 + 15 + 2,
4104 .vtotal = 1200 + 15 + 2 + 18,
4105 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
4108 static const struct panel_desc starry_kr122ea0sra = {
4109 .modes = &starry_kr122ea0sra_mode,
4116 .prepare = 10 + 200,
4118 .unprepare = 10 + 500,
4122 static const struct drm_display_mode tfc_s9700rtwv43tr_01b_mode = {
4125 .hsync_start = 800 + 39,
4126 .hsync_end = 800 + 39 + 47,
4127 .htotal = 800 + 39 + 47 + 39,
4129 .vsync_start = 480 + 13,
4130 .vsync_end = 480 + 13 + 2,
4131 .vtotal = 480 + 13 + 2 + 29,
4134 static const struct panel_desc tfc_s9700rtwv43tr_01b = {
4135 .modes = &tfc_s9700rtwv43tr_01b_mode,
4142 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
4143 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
4146 static const struct display_timing tianma_tm070jdhg30_timing = {
4147 .pixelclock = { 62600000, 68200000, 78100000 },
4148 .hactive = { 1280, 1280, 1280 },
4149 .hfront_porch = { 15, 64, 159 },
4150 .hback_porch = { 5, 5, 5 },
4151 .hsync_len = { 1, 1, 256 },
4152 .vactive = { 800, 800, 800 },
4153 .vfront_porch = { 3, 40, 99 },
4154 .vback_porch = { 2, 2, 2 },
4155 .vsync_len = { 1, 1, 128 },
4156 .flags = DISPLAY_FLAGS_DE_HIGH,
4159 static const struct panel_desc tianma_tm070jdhg30 = {
4160 .timings = &tianma_tm070jdhg30_timing,
4167 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
4168 .connector_type = DRM_MODE_CONNECTOR_LVDS,
4171 static const struct panel_desc tianma_tm070jvhg33 = {
4172 .timings = &tianma_tm070jdhg30_timing,
4179 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
4180 .connector_type = DRM_MODE_CONNECTOR_LVDS,
4183 static const struct display_timing tianma_tm070rvhg71_timing = {
4184 .pixelclock = { 27700000, 29200000, 39600000 },
4185 .hactive = { 800, 800, 800 },
4186 .hfront_porch = { 12, 40, 212 },
4187 .hback_porch = { 88, 88, 88 },
4188 .hsync_len = { 1, 1, 40 },
4189 .vactive = { 480, 480, 480 },
4190 .vfront_porch = { 1, 13, 88 },
4191 .vback_porch = { 32, 32, 32 },
4192 .vsync_len = { 1, 1, 3 },
4193 .flags = DISPLAY_FLAGS_DE_HIGH,
4196 static const struct panel_desc tianma_tm070rvhg71 = {
4197 .timings = &tianma_tm070rvhg71_timing,
4204 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
4205 .connector_type = DRM_MODE_CONNECTOR_LVDS,
4208 static const struct drm_display_mode ti_nspire_cx_lcd_mode[] = {
4212 .hsync_start = 320 + 50,
4213 .hsync_end = 320 + 50 + 6,
4214 .htotal = 320 + 50 + 6 + 38,
4216 .vsync_start = 240 + 3,
4217 .vsync_end = 240 + 3 + 1,
4218 .vtotal = 240 + 3 + 1 + 17,
4219 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
4223 static const struct panel_desc ti_nspire_cx_lcd_panel = {
4224 .modes = ti_nspire_cx_lcd_mode,
4231 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
4232 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
4235 static const struct drm_display_mode ti_nspire_classic_lcd_mode[] = {
4239 .hsync_start = 320 + 6,
4240 .hsync_end = 320 + 6 + 6,
4241 .htotal = 320 + 6 + 6 + 6,
4243 .vsync_start = 240 + 0,
4244 .vsync_end = 240 + 0 + 1,
4245 .vtotal = 240 + 0 + 1 + 0,
4246 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
4250 static const struct panel_desc ti_nspire_classic_lcd_panel = {
4251 .modes = ti_nspire_classic_lcd_mode,
4253 /* The grayscale panel has 8 bit for the color .. Y (black) */
4259 /* This is the grayscale bus format */
4260 .bus_format = MEDIA_BUS_FMT_Y8_1X8,
4261 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
4264 static const struct drm_display_mode toshiba_lt089ac29000_mode = {
4267 .hsync_start = 1280 + 192,
4268 .hsync_end = 1280 + 192 + 128,
4269 .htotal = 1280 + 192 + 128 + 64,
4271 .vsync_start = 768 + 20,
4272 .vsync_end = 768 + 20 + 7,
4273 .vtotal = 768 + 20 + 7 + 3,
4276 static const struct panel_desc toshiba_lt089ac29000 = {
4277 .modes = &toshiba_lt089ac29000_mode,
4283 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
4284 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
4285 .connector_type = DRM_MODE_CONNECTOR_LVDS,
4288 static const struct drm_display_mode tpk_f07a_0102_mode = {
4291 .hsync_start = 800 + 40,
4292 .hsync_end = 800 + 40 + 128,
4293 .htotal = 800 + 40 + 128 + 88,
4295 .vsync_start = 480 + 10,
4296 .vsync_end = 480 + 10 + 2,
4297 .vtotal = 480 + 10 + 2 + 33,
4300 static const struct panel_desc tpk_f07a_0102 = {
4301 .modes = &tpk_f07a_0102_mode,
4307 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
4310 static const struct drm_display_mode tpk_f10a_0102_mode = {
4313 .hsync_start = 1024 + 176,
4314 .hsync_end = 1024 + 176 + 5,
4315 .htotal = 1024 + 176 + 5 + 88,
4317 .vsync_start = 600 + 20,
4318 .vsync_end = 600 + 20 + 5,
4319 .vtotal = 600 + 20 + 5 + 25,
4322 static const struct panel_desc tpk_f10a_0102 = {
4323 .modes = &tpk_f10a_0102_mode,
4331 static const struct display_timing urt_umsh_8596md_timing = {
4332 .pixelclock = { 33260000, 33260000, 33260000 },
4333 .hactive = { 800, 800, 800 },
4334 .hfront_porch = { 41, 41, 41 },
4335 .hback_porch = { 216 - 128, 216 - 128, 216 - 128 },
4336 .hsync_len = { 71, 128, 128 },
4337 .vactive = { 480, 480, 480 },
4338 .vfront_porch = { 10, 10, 10 },
4339 .vback_porch = { 35 - 2, 35 - 2, 35 - 2 },
4340 .vsync_len = { 2, 2, 2 },
4341 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE |
4342 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
4345 static const struct panel_desc urt_umsh_8596md_lvds = {
4346 .timings = &urt_umsh_8596md_timing,
4353 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
4354 .connector_type = DRM_MODE_CONNECTOR_LVDS,
4357 static const struct panel_desc urt_umsh_8596md_parallel = {
4358 .timings = &urt_umsh_8596md_timing,
4365 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
4368 static const struct drm_display_mode vl050_8048nt_c01_mode = {
4371 .hsync_start = 800 + 210,
4372 .hsync_end = 800 + 210 + 20,
4373 .htotal = 800 + 210 + 20 + 46,
4375 .vsync_start = 480 + 22,
4376 .vsync_end = 480 + 22 + 10,
4377 .vtotal = 480 + 22 + 10 + 23,
4378 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
4381 static const struct panel_desc vl050_8048nt_c01 = {
4382 .modes = &vl050_8048nt_c01_mode,
4389 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
4390 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
4393 static const struct drm_display_mode winstar_wf35ltiacd_mode = {
4396 .hsync_start = 320 + 20,
4397 .hsync_end = 320 + 20 + 30,
4398 .htotal = 320 + 20 + 30 + 38,
4400 .vsync_start = 240 + 4,
4401 .vsync_end = 240 + 4 + 3,
4402 .vtotal = 240 + 4 + 3 + 15,
4403 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
4406 static const struct panel_desc winstar_wf35ltiacd = {
4407 .modes = &winstar_wf35ltiacd_mode,
4414 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
4417 static const struct drm_display_mode yes_optoelectronics_ytc700tlag_05_201c_mode = {
4420 .hsync_start = 1024 + 100,
4421 .hsync_end = 1024 + 100 + 100,
4422 .htotal = 1024 + 100 + 100 + 120,
4424 .vsync_start = 600 + 10,
4425 .vsync_end = 600 + 10 + 10,
4426 .vtotal = 600 + 10 + 10 + 15,
4427 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
4430 static const struct panel_desc yes_optoelectronics_ytc700tlag_05_201c = {
4431 .modes = &yes_optoelectronics_ytc700tlag_05_201c_mode,
4438 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
4439 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
4440 .connector_type = DRM_MODE_CONNECTOR_LVDS,
4443 static const struct drm_display_mode arm_rtsm_mode[] = {
4447 .hsync_start = 1024 + 24,
4448 .hsync_end = 1024 + 24 + 136,
4449 .htotal = 1024 + 24 + 136 + 160,
4451 .vsync_start = 768 + 3,
4452 .vsync_end = 768 + 3 + 6,
4453 .vtotal = 768 + 3 + 6 + 29,
4454 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
4458 static const struct panel_desc arm_rtsm = {
4459 .modes = arm_rtsm_mode,
4466 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
4469 static const struct of_device_id platform_of_match[] = {
4471 .compatible = "ampire,am-1280800n3tzqw-t00h",
4472 .data = &ire_am_1280800n3tzqw_t00h,
4474 .compatible = "ampire,am-480272h3tmqw-t01h",
4475 .data = &ire_am_480272h3tmqw_t01h,
4477 .compatible = "ampire,am800480r3tmqwa1h",
4478 .data = &ire_am800480r3tmqwa1h,
4480 .compatible = "arm,rtsm-display",
4483 .compatible = "armadeus,st0700-adapt",
4484 .data = &armadeus_st0700_adapt,
4486 .compatible = "auo,b101aw03",
4487 .data = &auo_b101aw03,
4489 .compatible = "auo,b101ean01",
4490 .data = &auo_b101ean01,
4492 .compatible = "auo,b101xtn01",
4493 .data = &auo_b101xtn01,
4495 .compatible = "auo,b116xa01",
4496 .data = &auo_b116xak01,
4498 .compatible = "auo,b116xw03",
4499 .data = &auo_b116xw03,
4501 .compatible = "auo,b133han05",
4502 .data = &auo_b133han05,
4504 .compatible = "auo,b133htn01",
4505 .data = &auo_b133htn01,
4507 .compatible = "auo,b140han06",
4508 .data = &auo_b140han06,
4510 .compatible = "auo,b133xtn01",
4511 .data = &auo_b133xtn01,
4513 .compatible = "auo,g070vvn01",
4514 .data = &auo_g070vvn01,
4516 .compatible = "auo,g101evn010",
4517 .data = &auo_g101evn010,
4519 .compatible = "auo,g104sn02",
4520 .data = &auo_g104sn02,
4522 .compatible = "auo,g121ean01",
4523 .data = &auo_g121ean01,
4525 .compatible = "auo,g133han01",
4526 .data = &auo_g133han01,
4528 .compatible = "auo,g156xtn01",
4529 .data = &auo_g156xtn01,
4531 .compatible = "auo,g185han01",
4532 .data = &auo_g185han01,
4534 .compatible = "auo,g190ean01",
4535 .data = &auo_g190ean01,
4537 .compatible = "auo,p320hvn03",
4538 .data = &auo_p320hvn03,
4540 .compatible = "auo,t215hvn01",
4541 .data = &auo_t215hvn01,
4543 .compatible = "avic,tm070ddh03",
4544 .data = &avic_tm070ddh03,
4546 .compatible = "bananapi,s070wv20-ct16",
4547 .data = &bananapi_s070wv20_ct16,
4549 .compatible = "boe,hv070wsa-100",
4550 .data = &boe_hv070wsa
4552 .compatible = "boe,nv101wxmn51",
4553 .data = &boe_nv101wxmn51,
4555 .compatible = "boe,nv110wtm-n61",
4556 .data = &boe_nv110wtm_n61,
4558 .compatible = "boe,nv133fhm-n61",
4559 .data = &boe_nv133fhm_n61,
4561 .compatible = "boe,nv133fhm-n62",
4562 .data = &boe_nv133fhm_n61,
4564 .compatible = "boe,nv140fhmn49",
4565 .data = &boe_nv140fhmn49,
4567 .compatible = "cdtech,s043wq26h-ct7",
4568 .data = &cdtech_s043wq26h_ct7,
4570 .compatible = "cdtech,s070pws19hp-fc21",
4571 .data = &cdtech_s070pws19hp_fc21,
4573 .compatible = "cdtech,s070swv29hg-dc44",
4574 .data = &cdtech_s070swv29hg_dc44,
4576 .compatible = "cdtech,s070wv95-ct16",
4577 .data = &cdtech_s070wv95_ct16,
4579 .compatible = "chefree,ch101olhlwh-002",
4580 .data = &chefree_ch101olhlwh_002,
4582 .compatible = "chunghwa,claa070wp03xg",
4583 .data = &chunghwa_claa070wp03xg,
4585 .compatible = "chunghwa,claa101wa01a",
4586 .data = &chunghwa_claa101wa01a
4588 .compatible = "chunghwa,claa101wb01",
4589 .data = &chunghwa_claa101wb01
4591 .compatible = "dataimage,scf0700c48ggu18",
4592 .data = &dataimage_scf0700c48ggu18,
4594 .compatible = "dlc,dlc0700yzg-1",
4595 .data = &dlc_dlc0700yzg_1,
4597 .compatible = "dlc,dlc1010gig",
4598 .data = &dlc_dlc1010gig,
4600 .compatible = "edt,et035012dm6",
4601 .data = &edt_et035012dm6,
4603 .compatible = "edt,etm0350g0dh6",
4604 .data = &edt_etm0350g0dh6,
4606 .compatible = "edt,etm043080dh6gp",
4607 .data = &edt_etm043080dh6gp,
4609 .compatible = "edt,etm0430g0dh6",
4610 .data = &edt_etm0430g0dh6,
4612 .compatible = "edt,et057090dhu",
4613 .data = &edt_et057090dhu,
4615 .compatible = "edt,et070080dh6",
4616 .data = &edt_etm0700g0dh6,
4618 .compatible = "edt,etm0700g0dh6",
4619 .data = &edt_etm0700g0dh6,
4621 .compatible = "edt,etm0700g0bdh6",
4622 .data = &edt_etm0700g0bdh6,
4624 .compatible = "edt,etm0700g0edh6",
4625 .data = &edt_etm0700g0bdh6,
4627 .compatible = "edt,etmv570g2dhu",
4628 .data = &edt_etmv570g2dhu,
4630 .compatible = "eink,vb3300-kca",
4631 .data = &eink_vb3300_kca,
4633 .compatible = "evervision,vgg804821",
4634 .data = &evervision_vgg804821,
4636 .compatible = "foxlink,fl500wvr00-a0t",
4637 .data = &foxlink_fl500wvr00_a0t,
4639 .compatible = "frida,frd350h54004",
4640 .data = &frida_frd350h54004,
4642 .compatible = "friendlyarm,hd702e",
4643 .data = &friendlyarm_hd702e,
4645 .compatible = "giantplus,gpg482739qs5",
4646 .data = &giantplus_gpg482739qs5
4648 .compatible = "giantplus,gpm940b0",
4649 .data = &giantplus_gpm940b0,
4651 .compatible = "hannstar,hsd070pww1",
4652 .data = &hannstar_hsd070pww1,
4654 .compatible = "hannstar,hsd100pxn1",
4655 .data = &hannstar_hsd100pxn1,
4657 .compatible = "hit,tx23d38vm0caa",
4658 .data = &hitachi_tx23d38vm0caa
4660 .compatible = "innolux,at043tn24",
4661 .data = &innolux_at043tn24,
4663 .compatible = "innolux,at070tn92",
4664 .data = &innolux_at070tn92,
4666 .compatible = "innolux,g070y2-l01",
4667 .data = &innolux_g070y2_l01,
4669 .compatible = "innolux,g101ice-l01",
4670 .data = &innolux_g101ice_l01
4672 .compatible = "innolux,g121i1-l01",
4673 .data = &innolux_g121i1_l01
4675 .compatible = "innolux,g121x1-l03",
4676 .data = &innolux_g121x1_l03,
4678 .compatible = "innolux,n116bca-ea1",
4679 .data = &innolux_n116bca_ea1,
4681 .compatible = "innolux,n116bge",
4682 .data = &innolux_n116bge,
4684 .compatible = "innolux,n125hce-gn1",
4685 .data = &innolux_n125hce_gn1,
4687 .compatible = "innolux,n156bge-l21",
4688 .data = &innolux_n156bge_l21,
4690 .compatible = "innolux,p120zdg-bf1",
4691 .data = &innolux_p120zdg_bf1,
4693 .compatible = "innolux,zj070na-01p",
4694 .data = &innolux_zj070na_01p,
4696 .compatible = "ivo,m133nwf4-r0",
4697 .data = &ivo_m133nwf4_r0,
4699 .compatible = "kingdisplay,kd116n21-30nv-a010",
4700 .data = &kingdisplay_kd116n21_30nv_a010,
4702 .compatible = "koe,tx14d24vm1bpa",
4703 .data = &koe_tx14d24vm1bpa,
4705 .compatible = "koe,tx26d202vm0bwa",
4706 .data = &koe_tx26d202vm0bwa,
4708 .compatible = "koe,tx31d200vm0baa",
4709 .data = &koe_tx31d200vm0baa,
4711 .compatible = "kyo,tcg121xglp",
4712 .data = &kyo_tcg121xglp,
4714 .compatible = "lemaker,bl035-rgb-002",
4715 .data = &lemaker_bl035_rgb_002,
4717 .compatible = "lg,lb070wv8",
4718 .data = &lg_lb070wv8,
4720 .compatible = "lg,lp079qx1-sp0v",
4721 .data = &lg_lp079qx1_sp0v,
4723 .compatible = "lg,lp097qx1-spa1",
4724 .data = &lg_lp097qx1_spa1,
4726 .compatible = "lg,lp120up1",
4727 .data = &lg_lp120up1,
4729 .compatible = "lg,lp129qe",
4730 .data = &lg_lp129qe,
4732 .compatible = "logicpd,type28",
4733 .data = &logicpd_type_28,
4735 .compatible = "logictechno,lt161010-2nhc",
4736 .data = &logictechno_lt161010_2nh,
4738 .compatible = "logictechno,lt161010-2nhr",
4739 .data = &logictechno_lt161010_2nh,
4741 .compatible = "logictechno,lt170410-2whc",
4742 .data = &logictechno_lt170410_2whc,
4744 .compatible = "logictechno,lttd800480070-l6wh-rt",
4745 .data = &logictechno_lttd800480070_l6wh_rt,
4747 .compatible = "mitsubishi,aa070mc01-ca1",
4748 .data = &mitsubishi_aa070mc01,
4750 .compatible = "multi-inno,mi1010ait-1cp",
4751 .data = &multi_inno_mi1010ait_1cp,
4753 .compatible = "nec,nl12880bc20-05",
4754 .data = &nec_nl12880bc20_05,
4756 .compatible = "nec,nl4827hc19-05b",
4757 .data = &nec_nl4827hc19_05b,
4759 .compatible = "netron-dy,e231732",
4760 .data = &netron_dy_e231732,
4762 .compatible = "neweast,wjfh116008a",
4763 .data = &neweast_wjfh116008a,
4765 .compatible = "newhaven,nhd-4.3-480272ef-atxl",
4766 .data = &newhaven_nhd_43_480272ef_atxl,
4768 .compatible = "nlt,nl192108ac18-02d",
4769 .data = &nlt_nl192108ac18_02d,
4771 .compatible = "nvd,9128",
4774 .compatible = "okaya,rs800480t-7x0gp",
4775 .data = &okaya_rs800480t_7x0gp,
4777 .compatible = "olimex,lcd-olinuxino-43-ts",
4778 .data = &olimex_lcd_olinuxino_43ts,
4780 .compatible = "ontat,yx700wv03",
4781 .data = &ontat_yx700wv03,
4783 .compatible = "ortustech,com37h3m05dtc",
4784 .data = &ortustech_com37h3m,
4786 .compatible = "ortustech,com37h3m99dtc",
4787 .data = &ortustech_com37h3m,
4789 .compatible = "ortustech,com43h4m85ulc",
4790 .data = &ortustech_com43h4m85ulc,
4792 .compatible = "osddisplays,osd070t1718-19ts",
4793 .data = &osddisplays_osd070t1718_19ts,
4795 .compatible = "pda,91-00156-a0",
4796 .data = &pda_91_00156_a0,
4798 .compatible = "powertip,ph800480t013-idf02",
4799 .data = &powertip_ph800480t013_idf02,
4801 .compatible = "qiaodian,qd43003c0-40",
4802 .data = &qd43003c0_40,
4804 .compatible = "qishenglong,gopher2b-lcd",
4805 .data = &qishenglong_gopher2b_lcd,
4807 .compatible = "rocktech,rk070er9427",
4808 .data = &rocktech_rk070er9427,
4810 .compatible = "rocktech,rk101ii01d-ct",
4811 .data = &rocktech_rk101ii01d_ct,
4813 .compatible = "samsung,lsn122dl01-c01",
4814 .data = &samsung_lsn122dl01_c01,
4816 .compatible = "samsung,ltn101nt05",
4817 .data = &samsung_ltn101nt05,
4819 .compatible = "samsung,ltn140at29-301",
4820 .data = &samsung_ltn140at29_301,
4822 .compatible = "satoz,sat050at40h12r2",
4823 .data = &satoz_sat050at40h12r2,
4825 .compatible = "sharp,ld-d5116z01b",
4826 .data = &sharp_ld_d5116z01b,
4828 .compatible = "sharp,lq035q7db03",
4829 .data = &sharp_lq035q7db03,
4831 .compatible = "sharp,lq070y3dg3b",
4832 .data = &sharp_lq070y3dg3b,
4834 .compatible = "sharp,lq101k1ly04",
4835 .data = &sharp_lq101k1ly04,
4837 .compatible = "sharp,lq123p1jx31",
4838 .data = &sharp_lq123p1jx31,
4840 .compatible = "sharp,ls020b1dd01d",
4841 .data = &sharp_ls020b1dd01d,
4843 .compatible = "shelly,sca07010-bfn-lnn",
4844 .data = &shelly_sca07010_bfn_lnn,
4846 .compatible = "starry,kr070pe2t",
4847 .data = &starry_kr070pe2t,
4849 .compatible = "starry,kr122ea0sra",
4850 .data = &starry_kr122ea0sra,
4852 .compatible = "tfc,s9700rtwv43tr-01b",
4853 .data = &tfc_s9700rtwv43tr_01b,
4855 .compatible = "tianma,tm070jdhg30",
4856 .data = &tianma_tm070jdhg30,
4858 .compatible = "tianma,tm070jvhg33",
4859 .data = &tianma_tm070jvhg33,
4861 .compatible = "tianma,tm070rvhg71",
4862 .data = &tianma_tm070rvhg71,
4864 .compatible = "ti,nspire-cx-lcd-panel",
4865 .data = &ti_nspire_cx_lcd_panel,
4867 .compatible = "ti,nspire-classic-lcd-panel",
4868 .data = &ti_nspire_classic_lcd_panel,
4870 .compatible = "toshiba,lt089ac29000",
4871 .data = &toshiba_lt089ac29000,
4873 .compatible = "tpk,f07a-0102",
4874 .data = &tpk_f07a_0102,
4876 .compatible = "tpk,f10a-0102",
4877 .data = &tpk_f10a_0102,
4879 .compatible = "urt,umsh-8596md-t",
4880 .data = &urt_umsh_8596md_parallel,
4882 .compatible = "urt,umsh-8596md-1t",
4883 .data = &urt_umsh_8596md_parallel,
4885 .compatible = "urt,umsh-8596md-7t",
4886 .data = &urt_umsh_8596md_parallel,
4888 .compatible = "urt,umsh-8596md-11t",
4889 .data = &urt_umsh_8596md_lvds,
4891 .compatible = "urt,umsh-8596md-19t",
4892 .data = &urt_umsh_8596md_lvds,
4894 .compatible = "urt,umsh-8596md-20t",
4895 .data = &urt_umsh_8596md_parallel,
4897 .compatible = "vxt,vl050-8048nt-c01",
4898 .data = &vl050_8048nt_c01,
4900 .compatible = "winstar,wf35ltiacd",
4901 .data = &winstar_wf35ltiacd,
4903 .compatible = "yes-optoelectronics,ytc700tlag-05-201c",
4904 .data = &yes_optoelectronics_ytc700tlag_05_201c,
4906 /* Must be the last entry */
4907 .compatible = "panel-dpi",
4913 MODULE_DEVICE_TABLE(of, platform_of_match);
4915 static int panel_simple_platform_probe(struct platform_device *pdev)
4917 const struct of_device_id *id;
4919 id = of_match_node(platform_of_match, pdev->dev.of_node);
4923 return panel_simple_probe(&pdev->dev, id->data, NULL);
4926 static int panel_simple_platform_remove(struct platform_device *pdev)
4928 return panel_simple_remove(&pdev->dev);
4931 static void panel_simple_platform_shutdown(struct platform_device *pdev)
4933 panel_simple_shutdown(&pdev->dev);
4936 static const struct dev_pm_ops panel_simple_pm_ops = {
4937 SET_RUNTIME_PM_OPS(panel_simple_suspend, panel_simple_resume, NULL)
4938 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
4939 pm_runtime_force_resume)
4942 static struct platform_driver panel_simple_platform_driver = {
4944 .name = "panel-simple",
4945 .of_match_table = platform_of_match,
4946 .pm = &panel_simple_pm_ops,
4948 .probe = panel_simple_platform_probe,
4949 .remove = panel_simple_platform_remove,
4950 .shutdown = panel_simple_platform_shutdown,
4953 struct panel_desc_dsi {
4954 struct panel_desc desc;
4956 unsigned long flags;
4957 enum mipi_dsi_pixel_format format;
4961 static const struct drm_display_mode auo_b080uan01_mode = {
4964 .hsync_start = 1200 + 62,
4965 .hsync_end = 1200 + 62 + 4,
4966 .htotal = 1200 + 62 + 4 + 62,
4968 .vsync_start = 1920 + 9,
4969 .vsync_end = 1920 + 9 + 2,
4970 .vtotal = 1920 + 9 + 2 + 8,
4973 static const struct panel_desc_dsi auo_b080uan01 = {
4975 .modes = &auo_b080uan01_mode,
4982 .connector_type = DRM_MODE_CONNECTOR_DSI,
4984 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
4985 .format = MIPI_DSI_FMT_RGB888,
4989 static const struct drm_display_mode boe_tv080wum_nl0_mode = {
4992 .hsync_start = 1200 + 120,
4993 .hsync_end = 1200 + 120 + 20,
4994 .htotal = 1200 + 120 + 20 + 21,
4996 .vsync_start = 1920 + 21,
4997 .vsync_end = 1920 + 21 + 3,
4998 .vtotal = 1920 + 21 + 3 + 18,
4999 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
5002 static const struct panel_desc_dsi boe_tv080wum_nl0 = {
5004 .modes = &boe_tv080wum_nl0_mode,
5010 .connector_type = DRM_MODE_CONNECTOR_DSI,
5012 .flags = MIPI_DSI_MODE_VIDEO |
5013 MIPI_DSI_MODE_VIDEO_BURST |
5014 MIPI_DSI_MODE_VIDEO_SYNC_PULSE,
5015 .format = MIPI_DSI_FMT_RGB888,
5019 static const struct drm_display_mode lg_ld070wx3_sl01_mode = {
5022 .hsync_start = 800 + 32,
5023 .hsync_end = 800 + 32 + 1,
5024 .htotal = 800 + 32 + 1 + 57,
5026 .vsync_start = 1280 + 28,
5027 .vsync_end = 1280 + 28 + 1,
5028 .vtotal = 1280 + 28 + 1 + 14,
5031 static const struct panel_desc_dsi lg_ld070wx3_sl01 = {
5033 .modes = &lg_ld070wx3_sl01_mode,
5040 .connector_type = DRM_MODE_CONNECTOR_DSI,
5042 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
5043 .format = MIPI_DSI_FMT_RGB888,
5047 static const struct drm_display_mode lg_lh500wx1_sd03_mode = {
5050 .hsync_start = 720 + 12,
5051 .hsync_end = 720 + 12 + 4,
5052 .htotal = 720 + 12 + 4 + 112,
5054 .vsync_start = 1280 + 8,
5055 .vsync_end = 1280 + 8 + 4,
5056 .vtotal = 1280 + 8 + 4 + 12,
5059 static const struct panel_desc_dsi lg_lh500wx1_sd03 = {
5061 .modes = &lg_lh500wx1_sd03_mode,
5068 .connector_type = DRM_MODE_CONNECTOR_DSI,
5070 .flags = MIPI_DSI_MODE_VIDEO,
5071 .format = MIPI_DSI_FMT_RGB888,
5075 static const struct drm_display_mode panasonic_vvx10f004b00_mode = {
5078 .hsync_start = 1920 + 154,
5079 .hsync_end = 1920 + 154 + 16,
5080 .htotal = 1920 + 154 + 16 + 32,
5082 .vsync_start = 1200 + 17,
5083 .vsync_end = 1200 + 17 + 2,
5084 .vtotal = 1200 + 17 + 2 + 16,
5087 static const struct panel_desc_dsi panasonic_vvx10f004b00 = {
5089 .modes = &panasonic_vvx10f004b00_mode,
5096 .connector_type = DRM_MODE_CONNECTOR_DSI,
5098 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
5099 MIPI_DSI_CLOCK_NON_CONTINUOUS,
5100 .format = MIPI_DSI_FMT_RGB888,
5104 static const struct drm_display_mode lg_acx467akm_7_mode = {
5107 .hsync_start = 1080 + 2,
5108 .hsync_end = 1080 + 2 + 2,
5109 .htotal = 1080 + 2 + 2 + 2,
5111 .vsync_start = 1920 + 2,
5112 .vsync_end = 1920 + 2 + 2,
5113 .vtotal = 1920 + 2 + 2 + 2,
5116 static const struct panel_desc_dsi lg_acx467akm_7 = {
5118 .modes = &lg_acx467akm_7_mode,
5125 .connector_type = DRM_MODE_CONNECTOR_DSI,
5128 .format = MIPI_DSI_FMT_RGB888,
5132 static const struct drm_display_mode osd101t2045_53ts_mode = {
5135 .hsync_start = 1920 + 112,
5136 .hsync_end = 1920 + 112 + 16,
5137 .htotal = 1920 + 112 + 16 + 32,
5139 .vsync_start = 1200 + 16,
5140 .vsync_end = 1200 + 16 + 2,
5141 .vtotal = 1200 + 16 + 2 + 16,
5142 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
5145 static const struct panel_desc_dsi osd101t2045_53ts = {
5147 .modes = &osd101t2045_53ts_mode,
5154 .connector_type = DRM_MODE_CONNECTOR_DSI,
5156 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
5157 MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
5158 MIPI_DSI_MODE_NO_EOT_PACKET,
5159 .format = MIPI_DSI_FMT_RGB888,
5163 static const struct of_device_id dsi_of_match[] = {
5165 .compatible = "auo,b080uan01",
5166 .data = &auo_b080uan01
5168 .compatible = "boe,tv080wum-nl0",
5169 .data = &boe_tv080wum_nl0
5171 .compatible = "lg,ld070wx3-sl01",
5172 .data = &lg_ld070wx3_sl01
5174 .compatible = "lg,lh500wx1-sd03",
5175 .data = &lg_lh500wx1_sd03
5177 .compatible = "panasonic,vvx10f004b00",
5178 .data = &panasonic_vvx10f004b00
5180 .compatible = "lg,acx467akm-7",
5181 .data = &lg_acx467akm_7
5183 .compatible = "osddisplays,osd101t2045-53ts",
5184 .data = &osd101t2045_53ts
5189 MODULE_DEVICE_TABLE(of, dsi_of_match);
5191 static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi)
5193 const struct panel_desc_dsi *desc;
5194 const struct of_device_id *id;
5197 id = of_match_node(dsi_of_match, dsi->dev.of_node);
5203 err = panel_simple_probe(&dsi->dev, &desc->desc, NULL);
5207 dsi->mode_flags = desc->flags;
5208 dsi->format = desc->format;
5209 dsi->lanes = desc->lanes;
5211 err = mipi_dsi_attach(dsi);
5213 struct panel_simple *panel = mipi_dsi_get_drvdata(dsi);
5215 drm_panel_remove(&panel->base);
5221 static int panel_simple_dsi_remove(struct mipi_dsi_device *dsi)
5225 err = mipi_dsi_detach(dsi);
5227 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err);
5229 return panel_simple_remove(&dsi->dev);
5232 static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi)
5234 panel_simple_shutdown(&dsi->dev);
5237 static struct mipi_dsi_driver panel_simple_dsi_driver = {
5239 .name = "panel-simple-dsi",
5240 .of_match_table = dsi_of_match,
5241 .pm = &panel_simple_pm_ops,
5243 .probe = panel_simple_dsi_probe,
5244 .remove = panel_simple_dsi_remove,
5245 .shutdown = panel_simple_dsi_shutdown,
5248 static int panel_simple_dp_aux_ep_probe(struct dp_aux_ep_device *aux_ep)
5250 const struct of_device_id *id;
5252 id = of_match_node(platform_of_match, aux_ep->dev.of_node);
5256 return panel_simple_probe(&aux_ep->dev, id->data, aux_ep->aux);
5259 static void panel_simple_dp_aux_ep_remove(struct dp_aux_ep_device *aux_ep)
5261 panel_simple_remove(&aux_ep->dev);
5264 static void panel_simple_dp_aux_ep_shutdown(struct dp_aux_ep_device *aux_ep)
5266 panel_simple_shutdown(&aux_ep->dev);
5269 static struct dp_aux_ep_driver panel_simple_dp_aux_ep_driver = {
5271 .name = "panel-simple-dp-aux",
5272 .of_match_table = platform_of_match, /* Same as platform one! */
5273 .pm = &panel_simple_pm_ops,
5275 .probe = panel_simple_dp_aux_ep_probe,
5276 .remove = panel_simple_dp_aux_ep_remove,
5277 .shutdown = panel_simple_dp_aux_ep_shutdown,
5280 static int __init panel_simple_init(void)
5284 err = platform_driver_register(&panel_simple_platform_driver);
5288 err = dp_aux_dp_driver_register(&panel_simple_dp_aux_ep_driver);
5290 goto err_did_platform_register;
5292 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) {
5293 err = mipi_dsi_driver_register(&panel_simple_dsi_driver);
5295 goto err_did_aux_ep_register;
5300 err_did_aux_ep_register:
5301 dp_aux_dp_driver_unregister(&panel_simple_dp_aux_ep_driver);
5303 err_did_platform_register:
5304 platform_driver_unregister(&panel_simple_platform_driver);
5308 module_init(panel_simple_init);
5310 static void __exit panel_simple_exit(void)
5312 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI))
5313 mipi_dsi_driver_unregister(&panel_simple_dsi_driver);
5315 dp_aux_dp_driver_unregister(&panel_simple_dp_aux_ep_driver);
5316 platform_driver_unregister(&panel_simple_platform_driver);
5318 module_exit(panel_simple_exit);
5320 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
5321 MODULE_DESCRIPTION("DRM Driver for Simple Panels");
5322 MODULE_LICENSE("GPL and additional rights");