2 * Copyright (C) 2013, NVIDIA Corporation. All rights reserved.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sub license,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the
12 * next paragraph) shall be included in all copies or substantial portions
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 #include <linux/delay.h>
25 #include <linux/gpio/consumer.h>
26 #include <linux/i2c.h>
27 #include <linux/media-bus-format.h>
28 #include <linux/module.h>
29 #include <linux/of_platform.h>
30 #include <linux/platform_device.h>
31 #include <linux/pm_runtime.h>
32 #include <linux/regulator/consumer.h>
34 #include <video/display_timing.h>
35 #include <video/of_display_timing.h>
36 #include <video/videomode.h>
38 #include <drm/drm_crtc.h>
39 #include <drm/drm_device.h>
40 #include <drm/drm_edid.h>
41 #include <drm/drm_mipi_dsi.h>
42 #include <drm/drm_panel.h>
45 * struct panel_desc - Describes a simple panel.
49 * @modes: Pointer to array of fixed modes appropriate for this panel.
51 * If only one mode then this can just be the address of the mode.
52 * NOTE: cannot be used with "timings" and also if this is specified
53 * then you cannot override the mode in the device tree.
55 const struct drm_display_mode *modes;
57 /** @num_modes: Number of elements in modes array. */
58 unsigned int num_modes;
61 * @timings: Pointer to array of display timings
63 * NOTE: cannot be used with "modes" and also these will be used to
64 * validate a device tree override if one is present.
66 const struct display_timing *timings;
68 /** @num_timings: Number of elements in timings array. */
69 unsigned int num_timings;
71 /** @bpc: Bits per color. */
74 /** @size: Structure containing the physical size of this panel. */
77 * @size.width: Width (in mm) of the active display area.
82 * @size.height: Height (in mm) of the active display area.
87 /** @delay: Structure containing various delay values for this panel. */
90 * @delay.prepare: Time for the panel to become ready.
92 * The time (in milliseconds) that it takes for the panel to
93 * become ready and start receiving video data
98 * @delay.enable: Time for the panel to display a valid frame.
100 * The time (in milliseconds) that it takes for the panel to
101 * display the first valid frame after starting to receive
107 * @delay.disable: Time for the panel to turn the display off.
109 * The time (in milliseconds) that it takes for the panel to
110 * turn the display off (no content is visible).
112 unsigned int disable;
115 * @delay.unprepare: Time to power down completely.
117 * The time (in milliseconds) that it takes for the panel
118 * to power itself down completely.
120 * This time is used to prevent a future "prepare" from
121 * starting until at least this many milliseconds has passed.
122 * If at prepare time less time has passed since unprepare
123 * finished, the driver waits for the remaining time.
125 unsigned int unprepare;
128 /** @bus_format: See MEDIA_BUS_FMT_... defines. */
131 /** @bus_flags: See DRM_BUS_FLAG_... defines. */
134 /** @connector_type: LVDS, eDP, DSI, DPI, etc. */
138 struct panel_simple {
139 struct drm_panel base;
144 ktime_t unprepared_time;
146 const struct panel_desc *desc;
148 struct regulator *supply;
149 struct i2c_adapter *ddc;
151 struct gpio_desc *enable_gpio;
155 struct drm_display_mode override_mode;
157 enum drm_panel_orientation orientation;
160 static inline struct panel_simple *to_panel_simple(struct drm_panel *panel)
162 return container_of(panel, struct panel_simple, base);
165 static unsigned int panel_simple_get_timings_modes(struct panel_simple *panel,
166 struct drm_connector *connector)
168 struct drm_display_mode *mode;
169 unsigned int i, num = 0;
171 for (i = 0; i < panel->desc->num_timings; i++) {
172 const struct display_timing *dt = &panel->desc->timings[i];
175 videomode_from_timing(dt, &vm);
176 mode = drm_mode_create(connector->dev);
178 dev_err(panel->base.dev, "failed to add mode %ux%u\n",
179 dt->hactive.typ, dt->vactive.typ);
183 drm_display_mode_from_videomode(&vm, mode);
185 mode->type |= DRM_MODE_TYPE_DRIVER;
187 if (panel->desc->num_timings == 1)
188 mode->type |= DRM_MODE_TYPE_PREFERRED;
190 drm_mode_probed_add(connector, mode);
197 static unsigned int panel_simple_get_display_modes(struct panel_simple *panel,
198 struct drm_connector *connector)
200 struct drm_display_mode *mode;
201 unsigned int i, num = 0;
203 for (i = 0; i < panel->desc->num_modes; i++) {
204 const struct drm_display_mode *m = &panel->desc->modes[i];
206 mode = drm_mode_duplicate(connector->dev, m);
208 dev_err(panel->base.dev, "failed to add mode %ux%u@%u\n",
209 m->hdisplay, m->vdisplay,
210 drm_mode_vrefresh(m));
214 mode->type |= DRM_MODE_TYPE_DRIVER;
216 if (panel->desc->num_modes == 1)
217 mode->type |= DRM_MODE_TYPE_PREFERRED;
219 drm_mode_set_name(mode);
221 drm_mode_probed_add(connector, mode);
228 static int panel_simple_get_non_edid_modes(struct panel_simple *panel,
229 struct drm_connector *connector)
231 struct drm_display_mode *mode;
232 bool has_override = panel->override_mode.type;
233 unsigned int num = 0;
239 mode = drm_mode_duplicate(connector->dev,
240 &panel->override_mode);
242 drm_mode_probed_add(connector, mode);
245 dev_err(panel->base.dev, "failed to add override mode\n");
249 /* Only add timings if override was not there or failed to validate */
250 if (num == 0 && panel->desc->num_timings)
251 num = panel_simple_get_timings_modes(panel, connector);
254 * Only add fixed modes if timings/override added no mode.
256 * We should only ever have either the display timings specified
257 * or a fixed mode. Anything else is rather bogus.
259 WARN_ON(panel->desc->num_timings && panel->desc->num_modes);
261 num = panel_simple_get_display_modes(panel, connector);
263 connector->display_info.bpc = panel->desc->bpc;
264 connector->display_info.width_mm = panel->desc->size.width;
265 connector->display_info.height_mm = panel->desc->size.height;
266 if (panel->desc->bus_format)
267 drm_display_info_set_bus_formats(&connector->display_info,
268 &panel->desc->bus_format, 1);
269 connector->display_info.bus_flags = panel->desc->bus_flags;
274 static void panel_simple_wait(ktime_t start_ktime, unsigned int min_ms)
276 ktime_t now_ktime, min_ktime;
281 min_ktime = ktime_add(start_ktime, ms_to_ktime(min_ms));
282 now_ktime = ktime_get_boottime();
284 if (ktime_before(now_ktime, min_ktime))
285 msleep(ktime_to_ms(ktime_sub(min_ktime, now_ktime)) + 1);
288 static int panel_simple_disable(struct drm_panel *panel)
290 struct panel_simple *p = to_panel_simple(panel);
295 if (p->desc->delay.disable)
296 msleep(p->desc->delay.disable);
303 static int panel_simple_suspend(struct device *dev)
305 struct panel_simple *p = dev_get_drvdata(dev);
307 gpiod_set_value_cansleep(p->enable_gpio, 0);
308 regulator_disable(p->supply);
309 p->unprepared_time = ktime_get_boottime();
317 static int panel_simple_unprepare(struct drm_panel *panel)
319 struct panel_simple *p = to_panel_simple(panel);
322 /* Unpreparing when already unprepared is a no-op */
326 pm_runtime_mark_last_busy(panel->dev);
327 ret = pm_runtime_put_autosuspend(panel->dev);
335 static int panel_simple_resume(struct device *dev)
337 struct panel_simple *p = dev_get_drvdata(dev);
340 panel_simple_wait(p->unprepared_time, p->desc->delay.unprepare);
342 err = regulator_enable(p->supply);
344 dev_err(dev, "failed to enable supply: %d\n", err);
348 gpiod_set_value_cansleep(p->enable_gpio, 1);
350 if (p->desc->delay.prepare)
351 msleep(p->desc->delay.prepare);
356 static int panel_simple_prepare(struct drm_panel *panel)
358 struct panel_simple *p = to_panel_simple(panel);
361 /* Preparing when already prepared is a no-op */
365 ret = pm_runtime_get_sync(panel->dev);
367 pm_runtime_put_autosuspend(panel->dev);
376 static int panel_simple_enable(struct drm_panel *panel)
378 struct panel_simple *p = to_panel_simple(panel);
383 if (p->desc->delay.enable)
384 msleep(p->desc->delay.enable);
391 static int panel_simple_get_modes(struct drm_panel *panel,
392 struct drm_connector *connector)
394 struct panel_simple *p = to_panel_simple(panel);
397 /* probe EDID if a DDC bus is available */
399 pm_runtime_get_sync(panel->dev);
402 p->edid = drm_get_edid(connector, p->ddc);
405 num += drm_add_edid_modes(connector, p->edid);
407 pm_runtime_mark_last_busy(panel->dev);
408 pm_runtime_put_autosuspend(panel->dev);
411 /* add hard-coded panel modes */
412 num += panel_simple_get_non_edid_modes(p, connector);
415 * TODO: Remove once all drm drivers call
416 * drm_connector_set_orientation_from_panel()
418 drm_connector_set_panel_orientation(connector, p->orientation);
423 static int panel_simple_get_timings(struct drm_panel *panel,
424 unsigned int num_timings,
425 struct display_timing *timings)
427 struct panel_simple *p = to_panel_simple(panel);
430 if (p->desc->num_timings < num_timings)
431 num_timings = p->desc->num_timings;
434 for (i = 0; i < num_timings; i++)
435 timings[i] = p->desc->timings[i];
437 return p->desc->num_timings;
440 static enum drm_panel_orientation panel_simple_get_orientation(struct drm_panel *panel)
442 struct panel_simple *p = to_panel_simple(panel);
444 return p->orientation;
447 static const struct drm_panel_funcs panel_simple_funcs = {
448 .disable = panel_simple_disable,
449 .unprepare = panel_simple_unprepare,
450 .prepare = panel_simple_prepare,
451 .enable = panel_simple_enable,
452 .get_modes = panel_simple_get_modes,
453 .get_orientation = panel_simple_get_orientation,
454 .get_timings = panel_simple_get_timings,
457 static struct panel_desc panel_dpi;
459 static int panel_dpi_probe(struct device *dev,
460 struct panel_simple *panel)
462 struct display_timing *timing;
463 const struct device_node *np;
464 struct panel_desc *desc;
465 unsigned int bus_flags;
470 desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL);
474 timing = devm_kzalloc(dev, sizeof(*timing), GFP_KERNEL);
478 ret = of_get_display_timing(np, "panel-timing", timing);
480 dev_err(dev, "%pOF: no panel-timing node found for \"panel-dpi\" binding\n",
485 desc->timings = timing;
486 desc->num_timings = 1;
488 of_property_read_u32(np, "width-mm", &desc->size.width);
489 of_property_read_u32(np, "height-mm", &desc->size.height);
491 /* Extract bus_flags from display_timing */
493 vm.flags = timing->flags;
494 drm_bus_flags_from_videomode(&vm, &bus_flags);
495 desc->bus_flags = bus_flags;
497 /* We do not know the connector for the DT node, so guess it */
498 desc->connector_type = DRM_MODE_CONNECTOR_DPI;
505 #define PANEL_SIMPLE_BOUNDS_CHECK(to_check, bounds, field) \
506 (to_check->field.typ >= bounds->field.min && \
507 to_check->field.typ <= bounds->field.max)
508 static void panel_simple_parse_panel_timing_node(struct device *dev,
509 struct panel_simple *panel,
510 const struct display_timing *ot)
512 const struct panel_desc *desc = panel->desc;
516 if (WARN_ON(desc->num_modes)) {
517 dev_err(dev, "Reject override mode: panel has a fixed mode\n");
520 if (WARN_ON(!desc->num_timings)) {
521 dev_err(dev, "Reject override mode: no timings specified\n");
525 for (i = 0; i < panel->desc->num_timings; i++) {
526 const struct display_timing *dt = &panel->desc->timings[i];
528 if (!PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hactive) ||
529 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hfront_porch) ||
530 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hback_porch) ||
531 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hsync_len) ||
532 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vactive) ||
533 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vfront_porch) ||
534 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vback_porch) ||
535 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vsync_len))
538 if (ot->flags != dt->flags)
541 videomode_from_timing(ot, &vm);
542 drm_display_mode_from_videomode(&vm, &panel->override_mode);
543 panel->override_mode.type |= DRM_MODE_TYPE_DRIVER |
544 DRM_MODE_TYPE_PREFERRED;
548 if (WARN_ON(!panel->override_mode.type))
549 dev_err(dev, "Reject override mode: No display_timing found\n");
552 static int panel_simple_probe(struct device *dev, const struct panel_desc *desc)
554 struct panel_simple *panel;
555 struct display_timing dt;
556 struct device_node *ddc;
561 panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL);
565 panel->enabled = false;
568 panel->supply = devm_regulator_get(dev, "power");
569 if (IS_ERR(panel->supply))
570 return PTR_ERR(panel->supply);
572 panel->enable_gpio = devm_gpiod_get_optional(dev, "enable",
574 if (IS_ERR(panel->enable_gpio))
575 return dev_err_probe(dev, PTR_ERR(panel->enable_gpio),
576 "failed to request GPIO\n");
578 err = of_drm_get_panel_orientation(dev->of_node, &panel->orientation);
580 dev_err(dev, "%pOF: failed to get orientation %d\n", dev->of_node, err);
584 ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0);
586 panel->ddc = of_find_i2c_adapter_by_node(ddc);
590 return -EPROBE_DEFER;
593 if (desc == &panel_dpi) {
594 /* Handle the generic panel-dpi binding */
595 err = panel_dpi_probe(dev, panel);
600 if (!of_get_display_timing(dev->of_node, "panel-timing", &dt))
601 panel_simple_parse_panel_timing_node(dev, panel, &dt);
604 connector_type = desc->connector_type;
605 /* Catch common mistakes for panels. */
606 switch (connector_type) {
608 dev_warn(dev, "Specify missing connector_type\n");
609 connector_type = DRM_MODE_CONNECTOR_DPI;
611 case DRM_MODE_CONNECTOR_LVDS:
612 WARN_ON(desc->bus_flags &
613 ~(DRM_BUS_FLAG_DE_LOW |
614 DRM_BUS_FLAG_DE_HIGH |
615 DRM_BUS_FLAG_DATA_MSB_TO_LSB |
616 DRM_BUS_FLAG_DATA_LSB_TO_MSB));
617 WARN_ON(desc->bus_format != MEDIA_BUS_FMT_RGB666_1X7X3_SPWG &&
618 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_SPWG &&
619 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA);
620 WARN_ON(desc->bus_format == MEDIA_BUS_FMT_RGB666_1X7X3_SPWG &&
622 WARN_ON((desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_SPWG ||
623 desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA) &&
626 case DRM_MODE_CONNECTOR_eDP:
627 dev_warn(dev, "eDP panels moved to panel-edp\n");
630 case DRM_MODE_CONNECTOR_DSI:
631 if (desc->bpc != 6 && desc->bpc != 8)
632 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc);
634 case DRM_MODE_CONNECTOR_DPI:
635 bus_flags = DRM_BUS_FLAG_DE_LOW |
636 DRM_BUS_FLAG_DE_HIGH |
637 DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE |
638 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
639 DRM_BUS_FLAG_DATA_MSB_TO_LSB |
640 DRM_BUS_FLAG_DATA_LSB_TO_MSB |
641 DRM_BUS_FLAG_SYNC_SAMPLE_POSEDGE |
642 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE;
643 if (desc->bus_flags & ~bus_flags)
644 dev_warn(dev, "Unexpected bus_flags(%d)\n", desc->bus_flags & ~bus_flags);
645 if (!(desc->bus_flags & bus_flags))
646 dev_warn(dev, "Specify missing bus_flags\n");
647 if (desc->bus_format == 0)
648 dev_warn(dev, "Specify missing bus_format\n");
649 if (desc->bpc != 6 && desc->bpc != 8)
650 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc);
653 dev_warn(dev, "Specify a valid connector_type: %d\n", desc->connector_type);
654 connector_type = DRM_MODE_CONNECTOR_DPI;
658 dev_set_drvdata(dev, panel);
661 * We use runtime PM for prepare / unprepare since those power the panel
662 * on and off and those can be very slow operations. This is important
663 * to optimize powering the panel on briefly to read the EDID before
664 * fully enabling the panel.
666 pm_runtime_enable(dev);
667 pm_runtime_set_autosuspend_delay(dev, 1000);
668 pm_runtime_use_autosuspend(dev);
670 drm_panel_init(&panel->base, dev, &panel_simple_funcs, connector_type);
672 err = drm_panel_of_backlight(&panel->base);
674 dev_err_probe(dev, err, "Could not find backlight\n");
675 goto disable_pm_runtime;
678 drm_panel_add(&panel->base);
683 pm_runtime_dont_use_autosuspend(dev);
684 pm_runtime_disable(dev);
687 put_device(&panel->ddc->dev);
692 static void panel_simple_remove(struct device *dev)
694 struct panel_simple *panel = dev_get_drvdata(dev);
696 drm_panel_remove(&panel->base);
697 drm_panel_disable(&panel->base);
698 drm_panel_unprepare(&panel->base);
700 pm_runtime_dont_use_autosuspend(dev);
701 pm_runtime_disable(dev);
703 put_device(&panel->ddc->dev);
706 static void panel_simple_shutdown(struct device *dev)
708 struct panel_simple *panel = dev_get_drvdata(dev);
710 drm_panel_disable(&panel->base);
711 drm_panel_unprepare(&panel->base);
714 static const struct drm_display_mode ampire_am_1280800n3tzqw_t00h_mode = {
717 .hsync_start = 1280 + 40,
718 .hsync_end = 1280 + 40 + 80,
719 .htotal = 1280 + 40 + 80 + 40,
721 .vsync_start = 800 + 3,
722 .vsync_end = 800 + 3 + 10,
723 .vtotal = 800 + 3 + 10 + 10,
724 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
727 static const struct panel_desc ampire_am_1280800n3tzqw_t00h = {
728 .modes = &ire_am_1280800n3tzqw_t00h_mode,
735 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
736 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
737 .connector_type = DRM_MODE_CONNECTOR_LVDS,
740 static const struct drm_display_mode ampire_am_480272h3tmqw_t01h_mode = {
743 .hsync_start = 480 + 2,
744 .hsync_end = 480 + 2 + 41,
745 .htotal = 480 + 2 + 41 + 2,
747 .vsync_start = 272 + 2,
748 .vsync_end = 272 + 2 + 10,
749 .vtotal = 272 + 2 + 10 + 2,
750 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
753 static const struct panel_desc ampire_am_480272h3tmqw_t01h = {
754 .modes = &ire_am_480272h3tmqw_t01h_mode,
761 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
764 static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = {
767 .hsync_start = 800 + 0,
768 .hsync_end = 800 + 0 + 255,
769 .htotal = 800 + 0 + 255 + 0,
771 .vsync_start = 480 + 2,
772 .vsync_end = 480 + 2 + 45,
773 .vtotal = 480 + 2 + 45 + 0,
774 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
777 static const struct display_timing ampire_am_800480l1tmqw_t00h_timing = {
778 .pixelclock = { 29930000, 33260000, 36590000 },
779 .hactive = { 800, 800, 800 },
780 .hfront_porch = { 1, 40, 168 },
781 .hback_porch = { 88, 88, 88 },
782 .hsync_len = { 1, 128, 128 },
783 .vactive = { 480, 480, 480 },
784 .vfront_porch = { 1, 35, 37 },
785 .vback_porch = { 8, 8, 8 },
786 .vsync_len = { 1, 2, 2 },
787 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
788 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
789 DISPLAY_FLAGS_SYNC_POSEDGE,
792 static const struct panel_desc ampire_am_800480l1tmqw_t00h = {
793 .timings = &ire_am_800480l1tmqw_t00h_timing,
800 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
801 .bus_flags = DRM_BUS_FLAG_DE_HIGH |
802 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
803 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
804 .connector_type = DRM_MODE_CONNECTOR_DPI,
807 static const struct panel_desc ampire_am800480r3tmqwa1h = {
808 .modes = &ire_am800480r3tmqwa1h_mode,
815 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
818 static const struct display_timing ampire_am800600p5tmqw_tb8h_timing = {
819 .pixelclock = { 34500000, 39600000, 50400000 },
820 .hactive = { 800, 800, 800 },
821 .hfront_porch = { 12, 112, 312 },
822 .hback_porch = { 87, 87, 48 },
823 .hsync_len = { 1, 1, 40 },
824 .vactive = { 600, 600, 600 },
825 .vfront_porch = { 1, 21, 61 },
826 .vback_porch = { 38, 38, 19 },
827 .vsync_len = { 1, 1, 20 },
828 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
829 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
830 DISPLAY_FLAGS_SYNC_POSEDGE,
833 static const struct panel_desc ampire_am800600p5tmqwtb8h = {
834 .timings = &ire_am800600p5tmqw_tb8h_timing,
841 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
842 .bus_flags = DRM_BUS_FLAG_DE_HIGH |
843 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
844 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
845 .connector_type = DRM_MODE_CONNECTOR_DPI,
848 static const struct display_timing santek_st0700i5y_rbslw_f_timing = {
849 .pixelclock = { 26400000, 33300000, 46800000 },
850 .hactive = { 800, 800, 800 },
851 .hfront_porch = { 16, 210, 354 },
852 .hback_porch = { 45, 36, 6 },
853 .hsync_len = { 1, 10, 40 },
854 .vactive = { 480, 480, 480 },
855 .vfront_porch = { 7, 22, 147 },
856 .vback_porch = { 22, 13, 3 },
857 .vsync_len = { 1, 10, 20 },
858 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
859 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE
862 static const struct panel_desc armadeus_st0700_adapt = {
863 .timings = &santek_st0700i5y_rbslw_f_timing,
870 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
871 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
874 static const struct drm_display_mode auo_b101aw03_mode = {
877 .hsync_start = 1024 + 156,
878 .hsync_end = 1024 + 156 + 8,
879 .htotal = 1024 + 156 + 8 + 156,
881 .vsync_start = 600 + 16,
882 .vsync_end = 600 + 16 + 6,
883 .vtotal = 600 + 16 + 6 + 16,
886 static const struct panel_desc auo_b101aw03 = {
887 .modes = &auo_b101aw03_mode,
894 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
895 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
896 .connector_type = DRM_MODE_CONNECTOR_LVDS,
899 static const struct drm_display_mode auo_b101xtn01_mode = {
902 .hsync_start = 1366 + 20,
903 .hsync_end = 1366 + 20 + 70,
904 .htotal = 1366 + 20 + 70,
906 .vsync_start = 768 + 14,
907 .vsync_end = 768 + 14 + 42,
908 .vtotal = 768 + 14 + 42,
909 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
912 static const struct panel_desc auo_b101xtn01 = {
913 .modes = &auo_b101xtn01_mode,
922 static const struct display_timing auo_g070vvn01_timings = {
923 .pixelclock = { 33300000, 34209000, 45000000 },
924 .hactive = { 800, 800, 800 },
925 .hfront_porch = { 20, 40, 200 },
926 .hback_porch = { 87, 40, 1 },
927 .hsync_len = { 1, 48, 87 },
928 .vactive = { 480, 480, 480 },
929 .vfront_porch = { 5, 13, 200 },
930 .vback_porch = { 31, 31, 29 },
931 .vsync_len = { 1, 1, 3 },
934 static const struct panel_desc auo_g070vvn01 = {
935 .timings = &auo_g070vvn01_timings,
950 static const struct drm_display_mode auo_g101evn010_mode = {
953 .hsync_start = 1280 + 82,
954 .hsync_end = 1280 + 82 + 2,
955 .htotal = 1280 + 82 + 2 + 84,
957 .vsync_start = 800 + 8,
958 .vsync_end = 800 + 8 + 2,
959 .vtotal = 800 + 8 + 2 + 6,
962 static const struct panel_desc auo_g101evn010 = {
963 .modes = &auo_g101evn010_mode,
970 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
971 .connector_type = DRM_MODE_CONNECTOR_LVDS,
974 static const struct drm_display_mode auo_g104sn02_mode = {
977 .hsync_start = 800 + 40,
978 .hsync_end = 800 + 40 + 216,
979 .htotal = 800 + 40 + 216 + 128,
981 .vsync_start = 600 + 10,
982 .vsync_end = 600 + 10 + 35,
983 .vtotal = 600 + 10 + 35 + 2,
986 static const struct panel_desc auo_g104sn02 = {
987 .modes = &auo_g104sn02_mode,
994 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
995 .connector_type = DRM_MODE_CONNECTOR_LVDS,
998 static const struct drm_display_mode auo_g121ean01_mode = {
1001 .hsync_start = 1280 + 58,
1002 .hsync_end = 1280 + 58 + 8,
1003 .htotal = 1280 + 58 + 8 + 70,
1005 .vsync_start = 800 + 6,
1006 .vsync_end = 800 + 6 + 4,
1007 .vtotal = 800 + 6 + 4 + 10,
1010 static const struct panel_desc auo_g121ean01 = {
1011 .modes = &auo_g121ean01_mode,
1018 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1019 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1022 static const struct display_timing auo_g133han01_timings = {
1023 .pixelclock = { 134000000, 141200000, 149000000 },
1024 .hactive = { 1920, 1920, 1920 },
1025 .hfront_porch = { 39, 58, 77 },
1026 .hback_porch = { 59, 88, 117 },
1027 .hsync_len = { 28, 42, 56 },
1028 .vactive = { 1080, 1080, 1080 },
1029 .vfront_porch = { 3, 8, 11 },
1030 .vback_porch = { 5, 14, 19 },
1031 .vsync_len = { 4, 14, 19 },
1034 static const struct panel_desc auo_g133han01 = {
1035 .timings = &auo_g133han01_timings,
1048 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
1049 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1052 static const struct drm_display_mode auo_g156xtn01_mode = {
1055 .hsync_start = 1366 + 33,
1056 .hsync_end = 1366 + 33 + 67,
1059 .vsync_start = 768 + 4,
1060 .vsync_end = 768 + 4 + 4,
1064 static const struct panel_desc auo_g156xtn01 = {
1065 .modes = &auo_g156xtn01_mode,
1072 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1073 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1076 static const struct display_timing auo_g185han01_timings = {
1077 .pixelclock = { 120000000, 144000000, 175000000 },
1078 .hactive = { 1920, 1920, 1920 },
1079 .hfront_porch = { 36, 120, 148 },
1080 .hback_porch = { 24, 88, 108 },
1081 .hsync_len = { 20, 48, 64 },
1082 .vactive = { 1080, 1080, 1080 },
1083 .vfront_porch = { 6, 10, 40 },
1084 .vback_porch = { 2, 5, 20 },
1085 .vsync_len = { 2, 5, 20 },
1088 static const struct panel_desc auo_g185han01 = {
1089 .timings = &auo_g185han01_timings,
1102 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1103 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1106 static const struct display_timing auo_g190ean01_timings = {
1107 .pixelclock = { 90000000, 108000000, 135000000 },
1108 .hactive = { 1280, 1280, 1280 },
1109 .hfront_porch = { 126, 184, 1266 },
1110 .hback_porch = { 84, 122, 844 },
1111 .hsync_len = { 70, 102, 704 },
1112 .vactive = { 1024, 1024, 1024 },
1113 .vfront_porch = { 4, 26, 76 },
1114 .vback_porch = { 2, 8, 25 },
1115 .vsync_len = { 2, 8, 25 },
1118 static const struct panel_desc auo_g190ean01 = {
1119 .timings = &auo_g190ean01_timings,
1132 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1133 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1136 static const struct display_timing auo_p320hvn03_timings = {
1137 .pixelclock = { 106000000, 148500000, 164000000 },
1138 .hactive = { 1920, 1920, 1920 },
1139 .hfront_porch = { 25, 50, 130 },
1140 .hback_porch = { 25, 50, 130 },
1141 .hsync_len = { 20, 40, 105 },
1142 .vactive = { 1080, 1080, 1080 },
1143 .vfront_porch = { 8, 17, 150 },
1144 .vback_porch = { 8, 17, 150 },
1145 .vsync_len = { 4, 11, 100 },
1148 static const struct panel_desc auo_p320hvn03 = {
1149 .timings = &auo_p320hvn03_timings,
1161 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1162 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1165 static const struct drm_display_mode auo_t215hvn01_mode = {
1168 .hsync_start = 1920 + 88,
1169 .hsync_end = 1920 + 88 + 44,
1170 .htotal = 1920 + 88 + 44 + 148,
1172 .vsync_start = 1080 + 4,
1173 .vsync_end = 1080 + 4 + 5,
1174 .vtotal = 1080 + 4 + 5 + 36,
1177 static const struct panel_desc auo_t215hvn01 = {
1178 .modes = &auo_t215hvn01_mode,
1191 static const struct drm_display_mode avic_tm070ddh03_mode = {
1194 .hsync_start = 1024 + 160,
1195 .hsync_end = 1024 + 160 + 4,
1196 .htotal = 1024 + 160 + 4 + 156,
1198 .vsync_start = 600 + 17,
1199 .vsync_end = 600 + 17 + 1,
1200 .vtotal = 600 + 17 + 1 + 17,
1203 static const struct panel_desc avic_tm070ddh03 = {
1204 .modes = &avic_tm070ddh03_mode,
1218 static const struct drm_display_mode bananapi_s070wv20_ct16_mode = {
1221 .hsync_start = 800 + 40,
1222 .hsync_end = 800 + 40 + 48,
1223 .htotal = 800 + 40 + 48 + 40,
1225 .vsync_start = 480 + 13,
1226 .vsync_end = 480 + 13 + 3,
1227 .vtotal = 480 + 13 + 3 + 29,
1230 static const struct panel_desc bananapi_s070wv20_ct16 = {
1231 .modes = &bananapi_s070wv20_ct16_mode,
1240 static const struct display_timing boe_ev121wxm_n10_1850_timing = {
1241 .pixelclock = { 69922000, 71000000, 72293000 },
1242 .hactive = { 1280, 1280, 1280 },
1243 .hfront_porch = { 48, 48, 48 },
1244 .hback_porch = { 80, 80, 80 },
1245 .hsync_len = { 32, 32, 32 },
1246 .vactive = { 800, 800, 800 },
1247 .vfront_porch = { 3, 3, 3 },
1248 .vback_porch = { 14, 14, 14 },
1249 .vsync_len = { 6, 6, 6 },
1252 static const struct panel_desc boe_ev121wxm_n10_1850 = {
1253 .timings = &boe_ev121wxm_n10_1850_timing,
1266 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1267 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1268 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1271 static const struct drm_display_mode boe_hv070wsa_mode = {
1274 .hsync_start = 1024 + 30,
1275 .hsync_end = 1024 + 30 + 30,
1276 .htotal = 1024 + 30 + 30 + 30,
1278 .vsync_start = 600 + 10,
1279 .vsync_end = 600 + 10 + 10,
1280 .vtotal = 600 + 10 + 10 + 10,
1283 static const struct panel_desc boe_hv070wsa = {
1284 .modes = &boe_hv070wsa_mode,
1291 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1292 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1293 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1296 static const struct drm_display_mode cdtech_s043wq26h_ct7_mode = {
1299 .hsync_start = 480 + 5,
1300 .hsync_end = 480 + 5 + 5,
1301 .htotal = 480 + 5 + 5 + 40,
1303 .vsync_start = 272 + 8,
1304 .vsync_end = 272 + 8 + 8,
1305 .vtotal = 272 + 8 + 8 + 8,
1306 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1309 static const struct panel_desc cdtech_s043wq26h_ct7 = {
1310 .modes = &cdtech_s043wq26h_ct7_mode,
1317 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1320 /* S070PWS19HP-FC21 2017/04/22 */
1321 static const struct drm_display_mode cdtech_s070pws19hp_fc21_mode = {
1324 .hsync_start = 1024 + 160,
1325 .hsync_end = 1024 + 160 + 20,
1326 .htotal = 1024 + 160 + 20 + 140,
1328 .vsync_start = 600 + 12,
1329 .vsync_end = 600 + 12 + 3,
1330 .vtotal = 600 + 12 + 3 + 20,
1331 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1334 static const struct panel_desc cdtech_s070pws19hp_fc21 = {
1335 .modes = &cdtech_s070pws19hp_fc21_mode,
1342 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1343 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
1344 .connector_type = DRM_MODE_CONNECTOR_DPI,
1347 /* S070SWV29HG-DC44 2017/09/21 */
1348 static const struct drm_display_mode cdtech_s070swv29hg_dc44_mode = {
1351 .hsync_start = 800 + 210,
1352 .hsync_end = 800 + 210 + 2,
1353 .htotal = 800 + 210 + 2 + 44,
1355 .vsync_start = 480 + 22,
1356 .vsync_end = 480 + 22 + 2,
1357 .vtotal = 480 + 22 + 2 + 21,
1358 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1361 static const struct panel_desc cdtech_s070swv29hg_dc44 = {
1362 .modes = &cdtech_s070swv29hg_dc44_mode,
1369 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1370 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
1371 .connector_type = DRM_MODE_CONNECTOR_DPI,
1374 static const struct drm_display_mode cdtech_s070wv95_ct16_mode = {
1377 .hsync_start = 800 + 40,
1378 .hsync_end = 800 + 40 + 40,
1379 .htotal = 800 + 40 + 40 + 48,
1381 .vsync_start = 480 + 29,
1382 .vsync_end = 480 + 29 + 13,
1383 .vtotal = 480 + 29 + 13 + 3,
1384 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1387 static const struct panel_desc cdtech_s070wv95_ct16 = {
1388 .modes = &cdtech_s070wv95_ct16_mode,
1397 static const struct display_timing chefree_ch101olhlwh_002_timing = {
1398 .pixelclock = { 68900000, 71100000, 73400000 },
1399 .hactive = { 1280, 1280, 1280 },
1400 .hfront_porch = { 65, 80, 95 },
1401 .hback_porch = { 64, 79, 94 },
1402 .hsync_len = { 1, 1, 1 },
1403 .vactive = { 800, 800, 800 },
1404 .vfront_porch = { 7, 11, 14 },
1405 .vback_porch = { 7, 11, 14 },
1406 .vsync_len = { 1, 1, 1 },
1407 .flags = DISPLAY_FLAGS_DE_HIGH,
1410 static const struct panel_desc chefree_ch101olhlwh_002 = {
1411 .timings = &chefree_ch101olhlwh_002_timing,
1422 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1423 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1424 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1427 static const struct drm_display_mode chunghwa_claa070wp03xg_mode = {
1430 .hsync_start = 800 + 49,
1431 .hsync_end = 800 + 49 + 33,
1432 .htotal = 800 + 49 + 33 + 17,
1434 .vsync_start = 1280 + 1,
1435 .vsync_end = 1280 + 1 + 7,
1436 .vtotal = 1280 + 1 + 7 + 15,
1437 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1440 static const struct panel_desc chunghwa_claa070wp03xg = {
1441 .modes = &chunghwa_claa070wp03xg_mode,
1448 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1449 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1450 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1453 static const struct drm_display_mode chunghwa_claa101wa01a_mode = {
1456 .hsync_start = 1366 + 58,
1457 .hsync_end = 1366 + 58 + 58,
1458 .htotal = 1366 + 58 + 58 + 58,
1460 .vsync_start = 768 + 4,
1461 .vsync_end = 768 + 4 + 4,
1462 .vtotal = 768 + 4 + 4 + 4,
1465 static const struct panel_desc chunghwa_claa101wa01a = {
1466 .modes = &chunghwa_claa101wa01a_mode,
1473 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1474 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1475 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1478 static const struct drm_display_mode chunghwa_claa101wb01_mode = {
1481 .hsync_start = 1366 + 48,
1482 .hsync_end = 1366 + 48 + 32,
1483 .htotal = 1366 + 48 + 32 + 20,
1485 .vsync_start = 768 + 16,
1486 .vsync_end = 768 + 16 + 8,
1487 .vtotal = 768 + 16 + 8 + 16,
1490 static const struct panel_desc chunghwa_claa101wb01 = {
1491 .modes = &chunghwa_claa101wb01_mode,
1498 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1499 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1500 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1503 static const struct display_timing dataimage_fg040346dsswbg04_timing = {
1504 .pixelclock = { 5000000, 9000000, 12000000 },
1505 .hactive = { 480, 480, 480 },
1506 .hfront_porch = { 12, 12, 12 },
1507 .hback_porch = { 12, 12, 12 },
1508 .hsync_len = { 21, 21, 21 },
1509 .vactive = { 272, 272, 272 },
1510 .vfront_porch = { 4, 4, 4 },
1511 .vback_porch = { 4, 4, 4 },
1512 .vsync_len = { 8, 8, 8 },
1515 static const struct panel_desc dataimage_fg040346dsswbg04 = {
1516 .timings = &dataimage_fg040346dsswbg04_timing,
1523 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1524 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1525 .connector_type = DRM_MODE_CONNECTOR_DPI,
1528 static const struct display_timing dataimage_fg1001l0dsswmg01_timing = {
1529 .pixelclock = { 68900000, 71110000, 73400000 },
1530 .hactive = { 1280, 1280, 1280 },
1531 .vactive = { 800, 800, 800 },
1532 .hback_porch = { 100, 100, 100 },
1533 .hfront_porch = { 100, 100, 100 },
1534 .vback_porch = { 5, 5, 5 },
1535 .vfront_porch = { 5, 5, 5 },
1536 .hsync_len = { 24, 24, 24 },
1537 .vsync_len = { 3, 3, 3 },
1538 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
1539 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
1542 static const struct panel_desc dataimage_fg1001l0dsswmg01 = {
1543 .timings = &dataimage_fg1001l0dsswmg01_timing,
1552 static const struct drm_display_mode dataimage_scf0700c48ggu18_mode = {
1555 .hsync_start = 800 + 40,
1556 .hsync_end = 800 + 40 + 128,
1557 .htotal = 800 + 40 + 128 + 88,
1559 .vsync_start = 480 + 10,
1560 .vsync_end = 480 + 10 + 2,
1561 .vtotal = 480 + 10 + 2 + 33,
1562 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1565 static const struct panel_desc dataimage_scf0700c48ggu18 = {
1566 .modes = &dataimage_scf0700c48ggu18_mode,
1573 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1574 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1577 static const struct display_timing dlc_dlc0700yzg_1_timing = {
1578 .pixelclock = { 45000000, 51200000, 57000000 },
1579 .hactive = { 1024, 1024, 1024 },
1580 .hfront_porch = { 100, 106, 113 },
1581 .hback_porch = { 100, 106, 113 },
1582 .hsync_len = { 100, 108, 114 },
1583 .vactive = { 600, 600, 600 },
1584 .vfront_porch = { 8, 11, 15 },
1585 .vback_porch = { 8, 11, 15 },
1586 .vsync_len = { 9, 13, 15 },
1587 .flags = DISPLAY_FLAGS_DE_HIGH,
1590 static const struct panel_desc dlc_dlc0700yzg_1 = {
1591 .timings = &dlc_dlc0700yzg_1_timing,
1603 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1604 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1607 static const struct display_timing dlc_dlc1010gig_timing = {
1608 .pixelclock = { 68900000, 71100000, 73400000 },
1609 .hactive = { 1280, 1280, 1280 },
1610 .hfront_porch = { 43, 53, 63 },
1611 .hback_porch = { 43, 53, 63 },
1612 .hsync_len = { 44, 54, 64 },
1613 .vactive = { 800, 800, 800 },
1614 .vfront_porch = { 5, 8, 11 },
1615 .vback_porch = { 5, 8, 11 },
1616 .vsync_len = { 5, 7, 11 },
1617 .flags = DISPLAY_FLAGS_DE_HIGH,
1620 static const struct panel_desc dlc_dlc1010gig = {
1621 .timings = &dlc_dlc1010gig_timing,
1634 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1635 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1638 static const struct drm_display_mode edt_et035012dm6_mode = {
1641 .hsync_start = 320 + 20,
1642 .hsync_end = 320 + 20 + 30,
1643 .htotal = 320 + 20 + 68,
1645 .vsync_start = 240 + 4,
1646 .vsync_end = 240 + 4 + 4,
1647 .vtotal = 240 + 4 + 4 + 14,
1648 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1651 static const struct panel_desc edt_et035012dm6 = {
1652 .modes = &edt_et035012dm6_mode,
1659 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1660 .bus_flags = DRM_BUS_FLAG_DE_LOW | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
1663 static const struct drm_display_mode edt_etm0350g0dh6_mode = {
1666 .hsync_start = 320 + 20,
1667 .hsync_end = 320 + 20 + 68,
1668 .htotal = 320 + 20 + 68,
1670 .vsync_start = 240 + 4,
1671 .vsync_end = 240 + 4 + 18,
1672 .vtotal = 240 + 4 + 18,
1673 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1676 static const struct panel_desc edt_etm0350g0dh6 = {
1677 .modes = &edt_etm0350g0dh6_mode,
1684 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1685 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
1686 .connector_type = DRM_MODE_CONNECTOR_DPI,
1689 static const struct drm_display_mode edt_etm043080dh6gp_mode = {
1692 .hsync_start = 480 + 8,
1693 .hsync_end = 480 + 8 + 4,
1694 .htotal = 480 + 8 + 4 + 41,
1697 * IWG22M: Y resolution changed for "dc_linuxfb" module crashing while
1702 .vsync_start = 288 + 2,
1703 .vsync_end = 288 + 2 + 4,
1704 .vtotal = 288 + 2 + 4 + 10,
1707 static const struct panel_desc edt_etm043080dh6gp = {
1708 .modes = &edt_etm043080dh6gp_mode,
1715 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1716 .connector_type = DRM_MODE_CONNECTOR_DPI,
1719 static const struct drm_display_mode edt_etm0430g0dh6_mode = {
1722 .hsync_start = 480 + 2,
1723 .hsync_end = 480 + 2 + 41,
1724 .htotal = 480 + 2 + 41 + 2,
1726 .vsync_start = 272 + 2,
1727 .vsync_end = 272 + 2 + 10,
1728 .vtotal = 272 + 2 + 10 + 2,
1729 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1732 static const struct panel_desc edt_etm0430g0dh6 = {
1733 .modes = &edt_etm0430g0dh6_mode,
1740 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1741 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
1742 .connector_type = DRM_MODE_CONNECTOR_DPI,
1745 static const struct drm_display_mode edt_et057090dhu_mode = {
1748 .hsync_start = 640 + 16,
1749 .hsync_end = 640 + 16 + 30,
1750 .htotal = 640 + 16 + 30 + 114,
1752 .vsync_start = 480 + 10,
1753 .vsync_end = 480 + 10 + 3,
1754 .vtotal = 480 + 10 + 3 + 32,
1755 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1758 static const struct panel_desc edt_et057090dhu = {
1759 .modes = &edt_et057090dhu_mode,
1766 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1767 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
1768 .connector_type = DRM_MODE_CONNECTOR_DPI,
1771 static const struct drm_display_mode edt_etm0700g0dh6_mode = {
1774 .hsync_start = 800 + 40,
1775 .hsync_end = 800 + 40 + 128,
1776 .htotal = 800 + 40 + 128 + 88,
1778 .vsync_start = 480 + 10,
1779 .vsync_end = 480 + 10 + 2,
1780 .vtotal = 480 + 10 + 2 + 33,
1781 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1784 static const struct panel_desc edt_etm0700g0dh6 = {
1785 .modes = &edt_etm0700g0dh6_mode,
1792 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1793 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
1794 .connector_type = DRM_MODE_CONNECTOR_DPI,
1797 static const struct panel_desc edt_etm0700g0bdh6 = {
1798 .modes = &edt_etm0700g0dh6_mode,
1805 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1806 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1807 .connector_type = DRM_MODE_CONNECTOR_DPI,
1810 static const struct display_timing edt_etml0700y5dha_timing = {
1811 .pixelclock = { 40800000, 51200000, 67200000 },
1812 .hactive = { 1024, 1024, 1024 },
1813 .hfront_porch = { 30, 106, 125 },
1814 .hback_porch = { 30, 106, 125 },
1815 .hsync_len = { 30, 108, 126 },
1816 .vactive = { 600, 600, 600 },
1817 .vfront_porch = { 3, 12, 67},
1818 .vback_porch = { 3, 12, 67 },
1819 .vsync_len = { 4, 11, 66 },
1820 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
1821 DISPLAY_FLAGS_DE_HIGH,
1824 static const struct panel_desc edt_etml0700y5dha = {
1825 .timings = &edt_etml0700y5dha_timing,
1832 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1833 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1836 static const struct drm_display_mode edt_etmv570g2dhu_mode = {
1840 .hsync_end = 640 + 16,
1841 .htotal = 640 + 16 + 30 + 114,
1843 .vsync_start = 480 + 10,
1844 .vsync_end = 480 + 10 + 3,
1845 .vtotal = 480 + 10 + 3 + 35,
1846 .flags = DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_PHSYNC,
1849 static const struct panel_desc edt_etmv570g2dhu = {
1850 .modes = &edt_etmv570g2dhu_mode,
1857 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1858 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
1859 .connector_type = DRM_MODE_CONNECTOR_DPI,
1862 static const struct display_timing eink_vb3300_kca_timing = {
1863 .pixelclock = { 40000000, 40000000, 40000000 },
1864 .hactive = { 334, 334, 334 },
1865 .hfront_porch = { 1, 1, 1 },
1866 .hback_porch = { 1, 1, 1 },
1867 .hsync_len = { 1, 1, 1 },
1868 .vactive = { 1405, 1405, 1405 },
1869 .vfront_porch = { 1, 1, 1 },
1870 .vback_porch = { 1, 1, 1 },
1871 .vsync_len = { 1, 1, 1 },
1872 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
1873 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE,
1876 static const struct panel_desc eink_vb3300_kca = {
1877 .timings = &eink_vb3300_kca_timing,
1884 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1885 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1886 .connector_type = DRM_MODE_CONNECTOR_DPI,
1889 static const struct display_timing evervision_vgg804821_timing = {
1890 .pixelclock = { 27600000, 33300000, 50000000 },
1891 .hactive = { 800, 800, 800 },
1892 .hfront_porch = { 40, 66, 70 },
1893 .hback_porch = { 40, 67, 70 },
1894 .hsync_len = { 40, 67, 70 },
1895 .vactive = { 480, 480, 480 },
1896 .vfront_porch = { 6, 10, 10 },
1897 .vback_porch = { 7, 11, 11 },
1898 .vsync_len = { 7, 11, 11 },
1899 .flags = DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH |
1900 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE |
1901 DISPLAY_FLAGS_SYNC_NEGEDGE,
1904 static const struct panel_desc evervision_vgg804821 = {
1905 .timings = &evervision_vgg804821_timing,
1912 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1913 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
1916 static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = {
1919 .hsync_start = 800 + 168,
1920 .hsync_end = 800 + 168 + 64,
1921 .htotal = 800 + 168 + 64 + 88,
1923 .vsync_start = 480 + 37,
1924 .vsync_end = 480 + 37 + 2,
1925 .vtotal = 480 + 37 + 2 + 8,
1928 static const struct panel_desc foxlink_fl500wvr00_a0t = {
1929 .modes = &foxlink_fl500wvr00_a0t_mode,
1936 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1939 static const struct drm_display_mode frida_frd350h54004_modes[] = {
1943 .hsync_start = 320 + 44,
1944 .hsync_end = 320 + 44 + 16,
1945 .htotal = 320 + 44 + 16 + 20,
1947 .vsync_start = 240 + 2,
1948 .vsync_end = 240 + 2 + 6,
1949 .vtotal = 240 + 2 + 6 + 2,
1950 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1955 .hsync_start = 320 + 56,
1956 .hsync_end = 320 + 56 + 16,
1957 .htotal = 320 + 56 + 16 + 40,
1959 .vsync_start = 240 + 2,
1960 .vsync_end = 240 + 2 + 6,
1961 .vtotal = 240 + 2 + 6 + 2,
1962 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1966 static const struct panel_desc frida_frd350h54004 = {
1967 .modes = frida_frd350h54004_modes,
1968 .num_modes = ARRAY_SIZE(frida_frd350h54004_modes),
1974 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1975 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
1976 .connector_type = DRM_MODE_CONNECTOR_DPI,
1979 static const struct drm_display_mode friendlyarm_hd702e_mode = {
1982 .hsync_start = 800 + 20,
1983 .hsync_end = 800 + 20 + 24,
1984 .htotal = 800 + 20 + 24 + 20,
1986 .vsync_start = 1280 + 4,
1987 .vsync_end = 1280 + 4 + 8,
1988 .vtotal = 1280 + 4 + 8 + 4,
1989 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1992 static const struct panel_desc friendlyarm_hd702e = {
1993 .modes = &friendlyarm_hd702e_mode,
2001 static const struct drm_display_mode giantplus_gpg482739qs5_mode = {
2004 .hsync_start = 480 + 5,
2005 .hsync_end = 480 + 5 + 1,
2006 .htotal = 480 + 5 + 1 + 40,
2008 .vsync_start = 272 + 8,
2009 .vsync_end = 272 + 8 + 1,
2010 .vtotal = 272 + 8 + 1 + 8,
2013 static const struct panel_desc giantplus_gpg482739qs5 = {
2014 .modes = &giantplus_gpg482739qs5_mode,
2021 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2024 static const struct display_timing giantplus_gpm940b0_timing = {
2025 .pixelclock = { 13500000, 27000000, 27500000 },
2026 .hactive = { 320, 320, 320 },
2027 .hfront_porch = { 14, 686, 718 },
2028 .hback_porch = { 50, 70, 255 },
2029 .hsync_len = { 1, 1, 1 },
2030 .vactive = { 240, 240, 240 },
2031 .vfront_porch = { 1, 1, 179 },
2032 .vback_porch = { 1, 21, 31 },
2033 .vsync_len = { 1, 1, 6 },
2034 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
2037 static const struct panel_desc giantplus_gpm940b0 = {
2038 .timings = &giantplus_gpm940b0_timing,
2045 .bus_format = MEDIA_BUS_FMT_RGB888_3X8,
2046 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
2049 static const struct display_timing hannstar_hsd070pww1_timing = {
2050 .pixelclock = { 64300000, 71100000, 82000000 },
2051 .hactive = { 1280, 1280, 1280 },
2052 .hfront_porch = { 1, 1, 10 },
2053 .hback_porch = { 1, 1, 10 },
2055 * According to the data sheet, the minimum horizontal blanking interval
2056 * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the
2057 * minimum working horizontal blanking interval to be 60 clocks.
2059 .hsync_len = { 58, 158, 661 },
2060 .vactive = { 800, 800, 800 },
2061 .vfront_porch = { 1, 1, 10 },
2062 .vback_porch = { 1, 1, 10 },
2063 .vsync_len = { 1, 21, 203 },
2064 .flags = DISPLAY_FLAGS_DE_HIGH,
2067 static const struct panel_desc hannstar_hsd070pww1 = {
2068 .timings = &hannstar_hsd070pww1_timing,
2075 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2076 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2079 static const struct display_timing hannstar_hsd100pxn1_timing = {
2080 .pixelclock = { 55000000, 65000000, 75000000 },
2081 .hactive = { 1024, 1024, 1024 },
2082 .hfront_porch = { 40, 40, 40 },
2083 .hback_porch = { 220, 220, 220 },
2084 .hsync_len = { 20, 60, 100 },
2085 .vactive = { 768, 768, 768 },
2086 .vfront_porch = { 7, 7, 7 },
2087 .vback_porch = { 21, 21, 21 },
2088 .vsync_len = { 10, 10, 10 },
2089 .flags = DISPLAY_FLAGS_DE_HIGH,
2092 static const struct panel_desc hannstar_hsd100pxn1 = {
2093 .timings = &hannstar_hsd100pxn1_timing,
2100 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2101 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2104 static const struct display_timing hannstar_hsd101pww2_timing = {
2105 .pixelclock = { 64300000, 71100000, 82000000 },
2106 .hactive = { 1280, 1280, 1280 },
2107 .hfront_porch = { 1, 1, 10 },
2108 .hback_porch = { 1, 1, 10 },
2109 .hsync_len = { 58, 158, 661 },
2110 .vactive = { 800, 800, 800 },
2111 .vfront_porch = { 1, 1, 10 },
2112 .vback_porch = { 1, 1, 10 },
2113 .vsync_len = { 1, 21, 203 },
2114 .flags = DISPLAY_FLAGS_DE_HIGH,
2117 static const struct panel_desc hannstar_hsd101pww2 = {
2118 .timings = &hannstar_hsd101pww2_timing,
2125 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2126 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2129 static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = {
2132 .hsync_start = 800 + 85,
2133 .hsync_end = 800 + 85 + 86,
2134 .htotal = 800 + 85 + 86 + 85,
2136 .vsync_start = 480 + 16,
2137 .vsync_end = 480 + 16 + 13,
2138 .vtotal = 480 + 16 + 13 + 16,
2141 static const struct panel_desc hitachi_tx23d38vm0caa = {
2142 .modes = &hitachi_tx23d38vm0caa_mode,
2155 static const struct drm_display_mode innolux_at043tn24_mode = {
2158 .hsync_start = 480 + 2,
2159 .hsync_end = 480 + 2 + 41,
2160 .htotal = 480 + 2 + 41 + 2,
2162 .vsync_start = 272 + 2,
2163 .vsync_end = 272 + 2 + 10,
2164 .vtotal = 272 + 2 + 10 + 2,
2165 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
2168 static const struct panel_desc innolux_at043tn24 = {
2169 .modes = &innolux_at043tn24_mode,
2176 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2177 .connector_type = DRM_MODE_CONNECTOR_DPI,
2178 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
2181 static const struct drm_display_mode innolux_at070tn92_mode = {
2184 .hsync_start = 800 + 210,
2185 .hsync_end = 800 + 210 + 20,
2186 .htotal = 800 + 210 + 20 + 46,
2188 .vsync_start = 480 + 22,
2189 .vsync_end = 480 + 22 + 10,
2190 .vtotal = 480 + 22 + 23 + 10,
2193 static const struct panel_desc innolux_at070tn92 = {
2194 .modes = &innolux_at070tn92_mode,
2200 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2203 static const struct display_timing innolux_g070ace_l01_timing = {
2204 .pixelclock = { 25200000, 35000000, 35700000 },
2205 .hactive = { 800, 800, 800 },
2206 .hfront_porch = { 30, 32, 87 },
2207 .hback_porch = { 30, 32, 87 },
2208 .hsync_len = { 1, 1, 1 },
2209 .vactive = { 480, 480, 480 },
2210 .vfront_porch = { 3, 3, 3 },
2211 .vback_porch = { 13, 13, 13 },
2212 .vsync_len = { 1, 1, 4 },
2213 .flags = DISPLAY_FLAGS_DE_HIGH,
2216 static const struct panel_desc innolux_g070ace_l01 = {
2217 .timings = &innolux_g070ace_l01_timing,
2230 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2231 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2232 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2235 static const struct display_timing innolux_g070y2_l01_timing = {
2236 .pixelclock = { 28000000, 29500000, 32000000 },
2237 .hactive = { 800, 800, 800 },
2238 .hfront_porch = { 61, 91, 141 },
2239 .hback_porch = { 60, 90, 140 },
2240 .hsync_len = { 12, 12, 12 },
2241 .vactive = { 480, 480, 480 },
2242 .vfront_porch = { 4, 9, 30 },
2243 .vback_porch = { 4, 8, 28 },
2244 .vsync_len = { 2, 2, 2 },
2245 .flags = DISPLAY_FLAGS_DE_HIGH,
2248 static const struct panel_desc innolux_g070y2_l01 = {
2249 .timings = &innolux_g070y2_l01_timing,
2262 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2263 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2264 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2267 static const struct drm_display_mode innolux_g070y2_t02_mode = {
2270 .hsync_start = 800 + 210,
2271 .hsync_end = 800 + 210 + 20,
2272 .htotal = 800 + 210 + 20 + 46,
2274 .vsync_start = 480 + 22,
2275 .vsync_end = 480 + 22 + 10,
2276 .vtotal = 480 + 22 + 23 + 10,
2279 static const struct panel_desc innolux_g070y2_t02 = {
2280 .modes = &innolux_g070y2_t02_mode,
2287 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2288 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
2289 .connector_type = DRM_MODE_CONNECTOR_DPI,
2292 static const struct display_timing innolux_g101ice_l01_timing = {
2293 .pixelclock = { 60400000, 71100000, 74700000 },
2294 .hactive = { 1280, 1280, 1280 },
2295 .hfront_porch = { 41, 80, 100 },
2296 .hback_porch = { 40, 79, 99 },
2297 .hsync_len = { 1, 1, 1 },
2298 .vactive = { 800, 800, 800 },
2299 .vfront_porch = { 5, 11, 14 },
2300 .vback_porch = { 4, 11, 14 },
2301 .vsync_len = { 1, 1, 1 },
2302 .flags = DISPLAY_FLAGS_DE_HIGH,
2305 static const struct panel_desc innolux_g101ice_l01 = {
2306 .timings = &innolux_g101ice_l01_timing,
2317 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2318 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2321 static const struct display_timing innolux_g121i1_l01_timing = {
2322 .pixelclock = { 67450000, 71000000, 74550000 },
2323 .hactive = { 1280, 1280, 1280 },
2324 .hfront_porch = { 40, 80, 160 },
2325 .hback_porch = { 39, 79, 159 },
2326 .hsync_len = { 1, 1, 1 },
2327 .vactive = { 800, 800, 800 },
2328 .vfront_porch = { 5, 11, 100 },
2329 .vback_porch = { 4, 11, 99 },
2330 .vsync_len = { 1, 1, 1 },
2333 static const struct panel_desc innolux_g121i1_l01 = {
2334 .timings = &innolux_g121i1_l01_timing,
2345 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2346 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2349 static const struct drm_display_mode innolux_g121x1_l03_mode = {
2352 .hsync_start = 1024 + 0,
2353 .hsync_end = 1024 + 1,
2354 .htotal = 1024 + 0 + 1 + 320,
2356 .vsync_start = 768 + 38,
2357 .vsync_end = 768 + 38 + 1,
2358 .vtotal = 768 + 38 + 1 + 0,
2359 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
2362 static const struct panel_desc innolux_g121x1_l03 = {
2363 .modes = &innolux_g121x1_l03_mode,
2377 static const struct drm_display_mode innolux_n156bge_l21_mode = {
2380 .hsync_start = 1366 + 16,
2381 .hsync_end = 1366 + 16 + 34,
2382 .htotal = 1366 + 16 + 34 + 50,
2384 .vsync_start = 768 + 2,
2385 .vsync_end = 768 + 2 + 6,
2386 .vtotal = 768 + 2 + 6 + 12,
2389 static const struct panel_desc innolux_n156bge_l21 = {
2390 .modes = &innolux_n156bge_l21_mode,
2397 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2398 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2399 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2402 static const struct drm_display_mode innolux_zj070na_01p_mode = {
2405 .hsync_start = 1024 + 128,
2406 .hsync_end = 1024 + 128 + 64,
2407 .htotal = 1024 + 128 + 64 + 128,
2409 .vsync_start = 600 + 16,
2410 .vsync_end = 600 + 16 + 4,
2411 .vtotal = 600 + 16 + 4 + 16,
2414 static const struct panel_desc innolux_zj070na_01p = {
2415 .modes = &innolux_zj070na_01p_mode,
2424 static const struct display_timing koe_tx14d24vm1bpa_timing = {
2425 .pixelclock = { 5580000, 5850000, 6200000 },
2426 .hactive = { 320, 320, 320 },
2427 .hfront_porch = { 30, 30, 30 },
2428 .hback_porch = { 30, 30, 30 },
2429 .hsync_len = { 1, 5, 17 },
2430 .vactive = { 240, 240, 240 },
2431 .vfront_porch = { 6, 6, 6 },
2432 .vback_porch = { 5, 5, 5 },
2433 .vsync_len = { 1, 2, 11 },
2434 .flags = DISPLAY_FLAGS_DE_HIGH,
2437 static const struct panel_desc koe_tx14d24vm1bpa = {
2438 .timings = &koe_tx14d24vm1bpa_timing,
2447 static const struct display_timing koe_tx26d202vm0bwa_timing = {
2448 .pixelclock = { 151820000, 156720000, 159780000 },
2449 .hactive = { 1920, 1920, 1920 },
2450 .hfront_porch = { 105, 130, 142 },
2451 .hback_porch = { 45, 70, 82 },
2452 .hsync_len = { 30, 30, 30 },
2453 .vactive = { 1200, 1200, 1200},
2454 .vfront_porch = { 3, 5, 10 },
2455 .vback_porch = { 2, 5, 10 },
2456 .vsync_len = { 5, 5, 5 },
2459 static const struct panel_desc koe_tx26d202vm0bwa = {
2460 .timings = &koe_tx26d202vm0bwa_timing,
2473 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2474 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2475 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2478 static const struct display_timing koe_tx31d200vm0baa_timing = {
2479 .pixelclock = { 39600000, 43200000, 48000000 },
2480 .hactive = { 1280, 1280, 1280 },
2481 .hfront_porch = { 16, 36, 56 },
2482 .hback_porch = { 16, 36, 56 },
2483 .hsync_len = { 8, 8, 8 },
2484 .vactive = { 480, 480, 480 },
2485 .vfront_porch = { 6, 21, 33 },
2486 .vback_porch = { 6, 21, 33 },
2487 .vsync_len = { 8, 8, 8 },
2488 .flags = DISPLAY_FLAGS_DE_HIGH,
2491 static const struct panel_desc koe_tx31d200vm0baa = {
2492 .timings = &koe_tx31d200vm0baa_timing,
2499 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2500 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2503 static const struct display_timing kyo_tcg121xglp_timing = {
2504 .pixelclock = { 52000000, 65000000, 71000000 },
2505 .hactive = { 1024, 1024, 1024 },
2506 .hfront_porch = { 2, 2, 2 },
2507 .hback_porch = { 2, 2, 2 },
2508 .hsync_len = { 86, 124, 244 },
2509 .vactive = { 768, 768, 768 },
2510 .vfront_porch = { 2, 2, 2 },
2511 .vback_porch = { 2, 2, 2 },
2512 .vsync_len = { 6, 34, 73 },
2513 .flags = DISPLAY_FLAGS_DE_HIGH,
2516 static const struct panel_desc kyo_tcg121xglp = {
2517 .timings = &kyo_tcg121xglp_timing,
2524 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2525 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2528 static const struct drm_display_mode lemaker_bl035_rgb_002_mode = {
2531 .hsync_start = 320 + 20,
2532 .hsync_end = 320 + 20 + 30,
2533 .htotal = 320 + 20 + 30 + 38,
2535 .vsync_start = 240 + 4,
2536 .vsync_end = 240 + 4 + 3,
2537 .vtotal = 240 + 4 + 3 + 15,
2540 static const struct panel_desc lemaker_bl035_rgb_002 = {
2541 .modes = &lemaker_bl035_rgb_002_mode,
2547 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2548 .bus_flags = DRM_BUS_FLAG_DE_LOW,
2551 static const struct drm_display_mode lg_lb070wv8_mode = {
2554 .hsync_start = 800 + 88,
2555 .hsync_end = 800 + 88 + 80,
2556 .htotal = 800 + 88 + 80 + 88,
2558 .vsync_start = 480 + 10,
2559 .vsync_end = 480 + 10 + 25,
2560 .vtotal = 480 + 10 + 25 + 10,
2563 static const struct panel_desc lg_lb070wv8 = {
2564 .modes = &lg_lb070wv8_mode,
2571 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2572 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2575 static const struct display_timing logictechno_lt161010_2nh_timing = {
2576 .pixelclock = { 26400000, 33300000, 46800000 },
2577 .hactive = { 800, 800, 800 },
2578 .hfront_porch = { 16, 210, 354 },
2579 .hback_porch = { 46, 46, 46 },
2580 .hsync_len = { 1, 20, 40 },
2581 .vactive = { 480, 480, 480 },
2582 .vfront_porch = { 7, 22, 147 },
2583 .vback_porch = { 23, 23, 23 },
2584 .vsync_len = { 1, 10, 20 },
2585 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
2586 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
2587 DISPLAY_FLAGS_SYNC_POSEDGE,
2590 static const struct panel_desc logictechno_lt161010_2nh = {
2591 .timings = &logictechno_lt161010_2nh_timing,
2598 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2599 .bus_flags = DRM_BUS_FLAG_DE_HIGH |
2600 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
2601 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
2602 .connector_type = DRM_MODE_CONNECTOR_DPI,
2605 static const struct display_timing logictechno_lt170410_2whc_timing = {
2606 .pixelclock = { 68900000, 71100000, 73400000 },
2607 .hactive = { 1280, 1280, 1280 },
2608 .hfront_porch = { 23, 60, 71 },
2609 .hback_porch = { 23, 60, 71 },
2610 .hsync_len = { 15, 40, 47 },
2611 .vactive = { 800, 800, 800 },
2612 .vfront_porch = { 5, 7, 10 },
2613 .vback_porch = { 5, 7, 10 },
2614 .vsync_len = { 6, 9, 12 },
2615 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
2616 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
2617 DISPLAY_FLAGS_SYNC_POSEDGE,
2620 static const struct panel_desc logictechno_lt170410_2whc = {
2621 .timings = &logictechno_lt170410_2whc_timing,
2628 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2629 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2630 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2633 static const struct drm_display_mode logictechno_lttd800480070_l2rt_mode = {
2636 .hsync_start = 800 + 112,
2637 .hsync_end = 800 + 112 + 3,
2638 .htotal = 800 + 112 + 3 + 85,
2640 .vsync_start = 480 + 38,
2641 .vsync_end = 480 + 38 + 3,
2642 .vtotal = 480 + 38 + 3 + 29,
2643 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2646 static const struct panel_desc logictechno_lttd800480070_l2rt = {
2647 .modes = &logictechno_lttd800480070_l2rt_mode,
2660 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2661 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
2662 .connector_type = DRM_MODE_CONNECTOR_DPI,
2665 static const struct drm_display_mode logictechno_lttd800480070_l6wh_rt_mode = {
2668 .hsync_start = 800 + 154,
2669 .hsync_end = 800 + 154 + 3,
2670 .htotal = 800 + 154 + 3 + 43,
2672 .vsync_start = 480 + 47,
2673 .vsync_end = 480 + 47 + 3,
2674 .vtotal = 480 + 47 + 3 + 20,
2675 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2678 static const struct panel_desc logictechno_lttd800480070_l6wh_rt = {
2679 .modes = &logictechno_lttd800480070_l6wh_rt_mode,
2692 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2693 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
2694 .connector_type = DRM_MODE_CONNECTOR_DPI,
2697 static const struct drm_display_mode logicpd_type_28_mode = {
2700 .hsync_start = 480 + 3,
2701 .hsync_end = 480 + 3 + 42,
2702 .htotal = 480 + 3 + 42 + 2,
2705 .vsync_start = 272 + 2,
2706 .vsync_end = 272 + 2 + 11,
2707 .vtotal = 272 + 2 + 11 + 3,
2708 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
2711 static const struct panel_desc logicpd_type_28 = {
2712 .modes = &logicpd_type_28_mode,
2725 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2726 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE |
2727 DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE,
2728 .connector_type = DRM_MODE_CONNECTOR_DPI,
2731 static const struct drm_display_mode mitsubishi_aa070mc01_mode = {
2734 .hsync_start = 800 + 0,
2735 .hsync_end = 800 + 1,
2736 .htotal = 800 + 0 + 1 + 160,
2738 .vsync_start = 480 + 0,
2739 .vsync_end = 480 + 48 + 1,
2740 .vtotal = 480 + 48 + 1 + 0,
2741 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
2744 static const struct panel_desc mitsubishi_aa070mc01 = {
2745 .modes = &mitsubishi_aa070mc01_mode,
2758 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2759 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2760 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2763 static const struct display_timing multi_inno_mi0700s4t_6_timing = {
2764 .pixelclock = { 29000000, 33000000, 38000000 },
2765 .hactive = { 800, 800, 800 },
2766 .hfront_porch = { 180, 210, 240 },
2767 .hback_porch = { 16, 16, 16 },
2768 .hsync_len = { 30, 30, 30 },
2769 .vactive = { 480, 480, 480 },
2770 .vfront_porch = { 12, 22, 32 },
2771 .vback_porch = { 10, 10, 10 },
2772 .vsync_len = { 13, 13, 13 },
2773 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
2774 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
2775 DISPLAY_FLAGS_SYNC_POSEDGE,
2778 static const struct panel_desc multi_inno_mi0700s4t_6 = {
2779 .timings = &multi_inno_mi0700s4t_6_timing,
2786 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2787 .bus_flags = DRM_BUS_FLAG_DE_HIGH |
2788 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
2789 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
2790 .connector_type = DRM_MODE_CONNECTOR_DPI,
2793 static const struct display_timing multi_inno_mi0800ft_9_timing = {
2794 .pixelclock = { 32000000, 40000000, 50000000 },
2795 .hactive = { 800, 800, 800 },
2796 .hfront_porch = { 16, 210, 354 },
2797 .hback_porch = { 6, 26, 45 },
2798 .hsync_len = { 1, 20, 40 },
2799 .vactive = { 600, 600, 600 },
2800 .vfront_porch = { 1, 12, 77 },
2801 .vback_porch = { 3, 13, 22 },
2802 .vsync_len = { 1, 10, 20 },
2803 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
2804 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
2805 DISPLAY_FLAGS_SYNC_POSEDGE,
2808 static const struct panel_desc multi_inno_mi0800ft_9 = {
2809 .timings = &multi_inno_mi0800ft_9_timing,
2816 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2817 .bus_flags = DRM_BUS_FLAG_DE_HIGH |
2818 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
2819 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
2820 .connector_type = DRM_MODE_CONNECTOR_DPI,
2823 static const struct display_timing multi_inno_mi1010ait_1cp_timing = {
2824 .pixelclock = { 68900000, 70000000, 73400000 },
2825 .hactive = { 1280, 1280, 1280 },
2826 .hfront_porch = { 30, 60, 71 },
2827 .hback_porch = { 30, 60, 71 },
2828 .hsync_len = { 10, 10, 48 },
2829 .vactive = { 800, 800, 800 },
2830 .vfront_porch = { 5, 10, 10 },
2831 .vback_porch = { 5, 10, 10 },
2832 .vsync_len = { 5, 6, 13 },
2833 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
2834 DISPLAY_FLAGS_DE_HIGH,
2837 static const struct panel_desc multi_inno_mi1010ait_1cp = {
2838 .timings = &multi_inno_mi1010ait_1cp_timing,
2849 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2850 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2851 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2854 static const struct display_timing nec_nl12880bc20_05_timing = {
2855 .pixelclock = { 67000000, 71000000, 75000000 },
2856 .hactive = { 1280, 1280, 1280 },
2857 .hfront_porch = { 2, 30, 30 },
2858 .hback_porch = { 6, 100, 100 },
2859 .hsync_len = { 2, 30, 30 },
2860 .vactive = { 800, 800, 800 },
2861 .vfront_porch = { 5, 5, 5 },
2862 .vback_porch = { 11, 11, 11 },
2863 .vsync_len = { 7, 7, 7 },
2866 static const struct panel_desc nec_nl12880bc20_05 = {
2867 .timings = &nec_nl12880bc20_05_timing,
2878 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2879 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2882 static const struct drm_display_mode nec_nl4827hc19_05b_mode = {
2885 .hsync_start = 480 + 2,
2886 .hsync_end = 480 + 2 + 41,
2887 .htotal = 480 + 2 + 41 + 2,
2889 .vsync_start = 272 + 2,
2890 .vsync_end = 272 + 2 + 4,
2891 .vtotal = 272 + 2 + 4 + 2,
2892 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2895 static const struct panel_desc nec_nl4827hc19_05b = {
2896 .modes = &nec_nl4827hc19_05b_mode,
2903 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2904 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
2907 static const struct drm_display_mode netron_dy_e231732_mode = {
2910 .hsync_start = 1024 + 160,
2911 .hsync_end = 1024 + 160 + 70,
2912 .htotal = 1024 + 160 + 70 + 90,
2914 .vsync_start = 600 + 127,
2915 .vsync_end = 600 + 127 + 20,
2916 .vtotal = 600 + 127 + 20 + 3,
2919 static const struct panel_desc netron_dy_e231732 = {
2920 .modes = &netron_dy_e231732_mode,
2926 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2929 static const struct drm_display_mode newhaven_nhd_43_480272ef_atxl_mode = {
2932 .hsync_start = 480 + 2,
2933 .hsync_end = 480 + 2 + 41,
2934 .htotal = 480 + 2 + 41 + 2,
2936 .vsync_start = 272 + 2,
2937 .vsync_end = 272 + 2 + 10,
2938 .vtotal = 272 + 2 + 10 + 2,
2939 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2942 static const struct panel_desc newhaven_nhd_43_480272ef_atxl = {
2943 .modes = &newhaven_nhd_43_480272ef_atxl_mode,
2950 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2951 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE |
2952 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
2953 .connector_type = DRM_MODE_CONNECTOR_DPI,
2956 static const struct display_timing nlt_nl192108ac18_02d_timing = {
2957 .pixelclock = { 130000000, 148350000, 163000000 },
2958 .hactive = { 1920, 1920, 1920 },
2959 .hfront_porch = { 80, 100, 100 },
2960 .hback_porch = { 100, 120, 120 },
2961 .hsync_len = { 50, 60, 60 },
2962 .vactive = { 1080, 1080, 1080 },
2963 .vfront_porch = { 12, 30, 30 },
2964 .vback_porch = { 4, 10, 10 },
2965 .vsync_len = { 4, 5, 5 },
2968 static const struct panel_desc nlt_nl192108ac18_02d = {
2969 .timings = &nlt_nl192108ac18_02d_timing,
2979 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2980 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2983 static const struct drm_display_mode nvd_9128_mode = {
2986 .hsync_start = 800 + 130,
2987 .hsync_end = 800 + 130 + 98,
2988 .htotal = 800 + 0 + 130 + 98,
2990 .vsync_start = 480 + 10,
2991 .vsync_end = 480 + 10 + 50,
2992 .vtotal = 480 + 0 + 10 + 50,
2995 static const struct panel_desc nvd_9128 = {
2996 .modes = &nvd_9128_mode,
3003 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3004 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3007 static const struct display_timing okaya_rs800480t_7x0gp_timing = {
3008 .pixelclock = { 30000000, 30000000, 40000000 },
3009 .hactive = { 800, 800, 800 },
3010 .hfront_porch = { 40, 40, 40 },
3011 .hback_porch = { 40, 40, 40 },
3012 .hsync_len = { 1, 48, 48 },
3013 .vactive = { 480, 480, 480 },
3014 .vfront_porch = { 13, 13, 13 },
3015 .vback_porch = { 29, 29, 29 },
3016 .vsync_len = { 3, 3, 3 },
3017 .flags = DISPLAY_FLAGS_DE_HIGH,
3020 static const struct panel_desc okaya_rs800480t_7x0gp = {
3021 .timings = &okaya_rs800480t_7x0gp_timing,
3034 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3037 static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode = {
3040 .hsync_start = 480 + 5,
3041 .hsync_end = 480 + 5 + 30,
3042 .htotal = 480 + 5 + 30 + 10,
3044 .vsync_start = 272 + 8,
3045 .vsync_end = 272 + 8 + 5,
3046 .vtotal = 272 + 8 + 5 + 3,
3049 static const struct panel_desc olimex_lcd_olinuxino_43ts = {
3050 .modes = &olimex_lcd_olinuxino_43ts_mode,
3056 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3060 * 800x480 CVT. The panel appears to be quite accepting, at least as far as
3061 * pixel clocks, but this is the timing that was being used in the Adafruit
3062 * installation instructions.
3064 static const struct drm_display_mode ontat_yx700wv03_mode = {
3074 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3079 * https://www.adafruit.com/images/product-files/2406/c3163.pdf
3081 static const struct panel_desc ontat_yx700wv03 = {
3082 .modes = &ontat_yx700wv03_mode,
3089 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3092 static const struct drm_display_mode ortustech_com37h3m_mode = {
3095 .hsync_start = 480 + 40,
3096 .hsync_end = 480 + 40 + 10,
3097 .htotal = 480 + 40 + 10 + 40,
3099 .vsync_start = 640 + 4,
3100 .vsync_end = 640 + 4 + 2,
3101 .vtotal = 640 + 4 + 2 + 4,
3102 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3105 static const struct panel_desc ortustech_com37h3m = {
3106 .modes = &ortustech_com37h3m_mode,
3110 .width = 56, /* 56.16mm */
3111 .height = 75, /* 74.88mm */
3113 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3114 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
3115 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
3118 static const struct drm_display_mode ortustech_com43h4m85ulc_mode = {
3121 .hsync_start = 480 + 10,
3122 .hsync_end = 480 + 10 + 10,
3123 .htotal = 480 + 10 + 10 + 15,
3125 .vsync_start = 800 + 3,
3126 .vsync_end = 800 + 3 + 3,
3127 .vtotal = 800 + 3 + 3 + 3,
3130 static const struct panel_desc ortustech_com43h4m85ulc = {
3131 .modes = &ortustech_com43h4m85ulc_mode,
3138 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3139 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
3140 .connector_type = DRM_MODE_CONNECTOR_DPI,
3143 static const struct drm_display_mode osddisplays_osd070t1718_19ts_mode = {
3146 .hsync_start = 800 + 210,
3147 .hsync_end = 800 + 210 + 30,
3148 .htotal = 800 + 210 + 30 + 16,
3150 .vsync_start = 480 + 22,
3151 .vsync_end = 480 + 22 + 13,
3152 .vtotal = 480 + 22 + 13 + 10,
3153 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3156 static const struct panel_desc osddisplays_osd070t1718_19ts = {
3157 .modes = &osddisplays_osd070t1718_19ts_mode,
3164 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3165 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE |
3166 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
3167 .connector_type = DRM_MODE_CONNECTOR_DPI,
3170 static const struct drm_display_mode pda_91_00156_a0_mode = {
3173 .hsync_start = 800 + 1,
3174 .hsync_end = 800 + 1 + 64,
3175 .htotal = 800 + 1 + 64 + 64,
3177 .vsync_start = 480 + 1,
3178 .vsync_end = 480 + 1 + 23,
3179 .vtotal = 480 + 1 + 23 + 22,
3182 static const struct panel_desc pda_91_00156_a0 = {
3183 .modes = &pda_91_00156_a0_mode,
3189 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3192 static const struct drm_display_mode powertip_ph800480t013_idf02_mode = {
3195 .hsync_start = 800 + 54,
3196 .hsync_end = 800 + 54 + 2,
3197 .htotal = 800 + 54 + 2 + 44,
3199 .vsync_start = 480 + 49,
3200 .vsync_end = 480 + 49 + 2,
3201 .vtotal = 480 + 49 + 2 + 22,
3202 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3205 static const struct panel_desc powertip_ph800480t013_idf02 = {
3206 .modes = &powertip_ph800480t013_idf02_mode,
3212 .bus_flags = DRM_BUS_FLAG_DE_HIGH |
3213 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
3214 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
3215 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3216 .connector_type = DRM_MODE_CONNECTOR_DPI,
3219 static const struct drm_display_mode qd43003c0_40_mode = {
3222 .hsync_start = 480 + 8,
3223 .hsync_end = 480 + 8 + 4,
3224 .htotal = 480 + 8 + 4 + 39,
3226 .vsync_start = 272 + 4,
3227 .vsync_end = 272 + 4 + 10,
3228 .vtotal = 272 + 4 + 10 + 2,
3231 static const struct panel_desc qd43003c0_40 = {
3232 .modes = &qd43003c0_40_mode,
3239 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3242 static const struct drm_display_mode qishenglong_gopher2b_lcd_modes[] = {
3246 .hsync_start = 480 + 77,
3247 .hsync_end = 480 + 77 + 41,
3248 .htotal = 480 + 77 + 41 + 2,
3250 .vsync_start = 272 + 16,
3251 .vsync_end = 272 + 16 + 10,
3252 .vtotal = 272 + 16 + 10 + 2,
3253 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3258 .hsync_start = 480 + 17,
3259 .hsync_end = 480 + 17 + 41,
3260 .htotal = 480 + 17 + 41 + 2,
3262 .vsync_start = 272 + 116,
3263 .vsync_end = 272 + 116 + 10,
3264 .vtotal = 272 + 116 + 10 + 2,
3265 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3269 static const struct panel_desc qishenglong_gopher2b_lcd = {
3270 .modes = qishenglong_gopher2b_lcd_modes,
3271 .num_modes = ARRAY_SIZE(qishenglong_gopher2b_lcd_modes),
3277 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3278 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
3279 .connector_type = DRM_MODE_CONNECTOR_DPI,
3282 static const struct display_timing rocktech_rk043fn48h_timing = {
3283 .pixelclock = { 6000000, 9000000, 12000000 },
3284 .hactive = { 480, 480, 480 },
3285 .hback_porch = { 8, 43, 43 },
3286 .hfront_porch = { 2, 8, 8 },
3287 .hsync_len = { 1, 1, 1 },
3288 .vactive = { 272, 272, 272 },
3289 .vback_porch = { 2, 12, 12 },
3290 .vfront_porch = { 1, 4, 4 },
3291 .vsync_len = { 1, 10, 10 },
3292 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW |
3293 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE,
3296 static const struct panel_desc rocktech_rk043fn48h = {
3297 .timings = &rocktech_rk043fn48h_timing,
3304 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3305 .connector_type = DRM_MODE_CONNECTOR_DPI,
3308 static const struct display_timing rocktech_rk070er9427_timing = {
3309 .pixelclock = { 26400000, 33300000, 46800000 },
3310 .hactive = { 800, 800, 800 },
3311 .hfront_porch = { 16, 210, 354 },
3312 .hback_porch = { 46, 46, 46 },
3313 .hsync_len = { 1, 1, 1 },
3314 .vactive = { 480, 480, 480 },
3315 .vfront_porch = { 7, 22, 147 },
3316 .vback_porch = { 23, 23, 23 },
3317 .vsync_len = { 1, 1, 1 },
3318 .flags = DISPLAY_FLAGS_DE_HIGH,
3321 static const struct panel_desc rocktech_rk070er9427 = {
3322 .timings = &rocktech_rk070er9427_timing,
3335 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3338 static const struct drm_display_mode rocktech_rk101ii01d_ct_mode = {
3341 .hsync_start = 1280 + 48,
3342 .hsync_end = 1280 + 48 + 32,
3343 .htotal = 1280 + 48 + 32 + 80,
3345 .vsync_start = 800 + 2,
3346 .vsync_end = 800 + 2 + 5,
3347 .vtotal = 800 + 2 + 5 + 16,
3350 static const struct panel_desc rocktech_rk101ii01d_ct = {
3351 .modes = &rocktech_rk101ii01d_ct_mode,
3362 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
3363 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3364 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3367 static const struct display_timing samsung_ltl101al01_timing = {
3368 .pixelclock = { 66663000, 66663000, 66663000 },
3369 .hactive = { 1280, 1280, 1280 },
3370 .hfront_porch = { 18, 18, 18 },
3371 .hback_porch = { 36, 36, 36 },
3372 .hsync_len = { 16, 16, 16 },
3373 .vactive = { 800, 800, 800 },
3374 .vfront_porch = { 4, 4, 4 },
3375 .vback_porch = { 16, 16, 16 },
3376 .vsync_len = { 3, 3, 3 },
3377 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
3380 static const struct panel_desc samsung_ltl101al01 = {
3381 .timings = &samsung_ltl101al01_timing,
3394 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3395 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3398 static const struct drm_display_mode samsung_ltn101nt05_mode = {
3401 .hsync_start = 1024 + 24,
3402 .hsync_end = 1024 + 24 + 136,
3403 .htotal = 1024 + 24 + 136 + 160,
3405 .vsync_start = 600 + 3,
3406 .vsync_end = 600 + 3 + 6,
3407 .vtotal = 600 + 3 + 6 + 61,
3410 static const struct panel_desc samsung_ltn101nt05 = {
3411 .modes = &samsung_ltn101nt05_mode,
3418 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
3419 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
3420 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3423 static const struct display_timing satoz_sat050at40h12r2_timing = {
3424 .pixelclock = {33300000, 33300000, 50000000},
3425 .hactive = {800, 800, 800},
3426 .hfront_porch = {16, 210, 354},
3427 .hback_porch = {46, 46, 46},
3428 .hsync_len = {1, 1, 40},
3429 .vactive = {480, 480, 480},
3430 .vfront_porch = {7, 22, 147},
3431 .vback_porch = {23, 23, 23},
3432 .vsync_len = {1, 1, 20},
3435 static const struct panel_desc satoz_sat050at40h12r2 = {
3436 .timings = &satoz_sat050at40h12r2_timing,
3443 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3444 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3447 static const struct drm_display_mode sharp_lq070y3dg3b_mode = {
3450 .hsync_start = 800 + 64,
3451 .hsync_end = 800 + 64 + 128,
3452 .htotal = 800 + 64 + 128 + 64,
3454 .vsync_start = 480 + 8,
3455 .vsync_end = 480 + 8 + 2,
3456 .vtotal = 480 + 8 + 2 + 35,
3457 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE,
3460 static const struct panel_desc sharp_lq070y3dg3b = {
3461 .modes = &sharp_lq070y3dg3b_mode,
3465 .width = 152, /* 152.4mm */
3466 .height = 91, /* 91.4mm */
3468 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3469 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
3470 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
3473 static const struct drm_display_mode sharp_lq035q7db03_mode = {
3476 .hsync_start = 240 + 16,
3477 .hsync_end = 240 + 16 + 7,
3478 .htotal = 240 + 16 + 7 + 5,
3480 .vsync_start = 320 + 9,
3481 .vsync_end = 320 + 9 + 1,
3482 .vtotal = 320 + 9 + 1 + 7,
3485 static const struct panel_desc sharp_lq035q7db03 = {
3486 .modes = &sharp_lq035q7db03_mode,
3493 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3496 static const struct display_timing sharp_lq101k1ly04_timing = {
3497 .pixelclock = { 60000000, 65000000, 80000000 },
3498 .hactive = { 1280, 1280, 1280 },
3499 .hfront_porch = { 20, 20, 20 },
3500 .hback_porch = { 20, 20, 20 },
3501 .hsync_len = { 10, 10, 10 },
3502 .vactive = { 800, 800, 800 },
3503 .vfront_porch = { 4, 4, 4 },
3504 .vback_porch = { 4, 4, 4 },
3505 .vsync_len = { 4, 4, 4 },
3506 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE,
3509 static const struct panel_desc sharp_lq101k1ly04 = {
3510 .timings = &sharp_lq101k1ly04_timing,
3517 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
3518 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3521 static const struct drm_display_mode sharp_ls020b1dd01d_modes[] = {
3525 .hsync_start = 240 + 58,
3526 .hsync_end = 240 + 58 + 1,
3527 .htotal = 240 + 58 + 1 + 1,
3529 .vsync_start = 160 + 24,
3530 .vsync_end = 160 + 24 + 10,
3531 .vtotal = 160 + 24 + 10 + 6,
3532 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC,
3537 .hsync_start = 240 + 8,
3538 .hsync_end = 240 + 8 + 1,
3539 .htotal = 240 + 8 + 1 + 1,
3541 .vsync_start = 160 + 24,
3542 .vsync_end = 160 + 24 + 10,
3543 .vtotal = 160 + 24 + 10 + 6,
3544 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC,
3548 static const struct panel_desc sharp_ls020b1dd01d = {
3549 .modes = sharp_ls020b1dd01d_modes,
3550 .num_modes = ARRAY_SIZE(sharp_ls020b1dd01d_modes),
3556 .bus_format = MEDIA_BUS_FMT_RGB565_1X16,
3557 .bus_flags = DRM_BUS_FLAG_DE_HIGH
3558 | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE
3559 | DRM_BUS_FLAG_SHARP_SIGNALS,
3562 static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = {
3565 .hsync_start = 800 + 1,
3566 .hsync_end = 800 + 1 + 64,
3567 .htotal = 800 + 1 + 64 + 64,
3569 .vsync_start = 480 + 1,
3570 .vsync_end = 480 + 1 + 23,
3571 .vtotal = 480 + 1 + 23 + 22,
3574 static const struct panel_desc shelly_sca07010_bfn_lnn = {
3575 .modes = &shelly_sca07010_bfn_lnn_mode,
3581 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3584 static const struct drm_display_mode starry_kr070pe2t_mode = {
3587 .hsync_start = 800 + 209,
3588 .hsync_end = 800 + 209 + 1,
3589 .htotal = 800 + 209 + 1 + 45,
3591 .vsync_start = 480 + 22,
3592 .vsync_end = 480 + 22 + 1,
3593 .vtotal = 480 + 22 + 1 + 22,
3596 static const struct panel_desc starry_kr070pe2t = {
3597 .modes = &starry_kr070pe2t_mode,
3604 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3605 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
3606 .connector_type = DRM_MODE_CONNECTOR_DPI,
3609 static const struct display_timing startek_kd070wvfpa_mode = {
3610 .pixelclock = { 25200000, 27200000, 30500000 },
3611 .hactive = { 800, 800, 800 },
3612 .hfront_porch = { 19, 44, 115 },
3613 .hback_porch = { 5, 16, 101 },
3614 .hsync_len = { 1, 2, 100 },
3615 .vactive = { 480, 480, 480 },
3616 .vfront_porch = { 5, 43, 67 },
3617 .vback_porch = { 5, 5, 67 },
3618 .vsync_len = { 1, 2, 66 },
3619 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
3620 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
3621 DISPLAY_FLAGS_SYNC_POSEDGE,
3624 static const struct panel_desc startek_kd070wvfpa = {
3625 .timings = &startek_kd070wvfpa_mode,
3637 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3638 .connector_type = DRM_MODE_CONNECTOR_DPI,
3639 .bus_flags = DRM_BUS_FLAG_DE_HIGH |
3640 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
3641 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
3644 static const struct display_timing tsd_tst043015cmhx_timing = {
3645 .pixelclock = { 5000000, 9000000, 12000000 },
3646 .hactive = { 480, 480, 480 },
3647 .hfront_porch = { 4, 5, 65 },
3648 .hback_porch = { 36, 40, 255 },
3649 .hsync_len = { 1, 1, 1 },
3650 .vactive = { 272, 272, 272 },
3651 .vfront_porch = { 2, 8, 97 },
3652 .vback_porch = { 3, 8, 31 },
3653 .vsync_len = { 1, 1, 1 },
3655 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
3656 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE,
3659 static const struct panel_desc tsd_tst043015cmhx = {
3660 .timings = &tsd_tst043015cmhx_timing,
3667 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3668 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
3671 static const struct drm_display_mode tfc_s9700rtwv43tr_01b_mode = {
3674 .hsync_start = 800 + 39,
3675 .hsync_end = 800 + 39 + 47,
3676 .htotal = 800 + 39 + 47 + 39,
3678 .vsync_start = 480 + 13,
3679 .vsync_end = 480 + 13 + 2,
3680 .vtotal = 480 + 13 + 2 + 29,
3683 static const struct panel_desc tfc_s9700rtwv43tr_01b = {
3684 .modes = &tfc_s9700rtwv43tr_01b_mode,
3691 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3692 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
3695 static const struct display_timing tianma_tm070jdhg30_timing = {
3696 .pixelclock = { 62600000, 68200000, 78100000 },
3697 .hactive = { 1280, 1280, 1280 },
3698 .hfront_porch = { 15, 64, 159 },
3699 .hback_porch = { 5, 5, 5 },
3700 .hsync_len = { 1, 1, 256 },
3701 .vactive = { 800, 800, 800 },
3702 .vfront_porch = { 3, 40, 99 },
3703 .vback_porch = { 2, 2, 2 },
3704 .vsync_len = { 1, 1, 128 },
3705 .flags = DISPLAY_FLAGS_DE_HIGH,
3708 static const struct panel_desc tianma_tm070jdhg30 = {
3709 .timings = &tianma_tm070jdhg30_timing,
3716 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3717 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3720 static const struct panel_desc tianma_tm070jvhg33 = {
3721 .timings = &tianma_tm070jdhg30_timing,
3728 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3729 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3732 static const struct display_timing tianma_tm070rvhg71_timing = {
3733 .pixelclock = { 27700000, 29200000, 39600000 },
3734 .hactive = { 800, 800, 800 },
3735 .hfront_porch = { 12, 40, 212 },
3736 .hback_porch = { 88, 88, 88 },
3737 .hsync_len = { 1, 1, 40 },
3738 .vactive = { 480, 480, 480 },
3739 .vfront_porch = { 1, 13, 88 },
3740 .vback_porch = { 32, 32, 32 },
3741 .vsync_len = { 1, 1, 3 },
3742 .flags = DISPLAY_FLAGS_DE_HIGH,
3745 static const struct panel_desc tianma_tm070rvhg71 = {
3746 .timings = &tianma_tm070rvhg71_timing,
3753 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3754 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3757 static const struct drm_display_mode ti_nspire_cx_lcd_mode[] = {
3761 .hsync_start = 320 + 50,
3762 .hsync_end = 320 + 50 + 6,
3763 .htotal = 320 + 50 + 6 + 38,
3765 .vsync_start = 240 + 3,
3766 .vsync_end = 240 + 3 + 1,
3767 .vtotal = 240 + 3 + 1 + 17,
3768 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3772 static const struct panel_desc ti_nspire_cx_lcd_panel = {
3773 .modes = ti_nspire_cx_lcd_mode,
3780 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3781 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
3784 static const struct drm_display_mode ti_nspire_classic_lcd_mode[] = {
3788 .hsync_start = 320 + 6,
3789 .hsync_end = 320 + 6 + 6,
3790 .htotal = 320 + 6 + 6 + 6,
3792 .vsync_start = 240 + 0,
3793 .vsync_end = 240 + 0 + 1,
3794 .vtotal = 240 + 0 + 1 + 0,
3795 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
3799 static const struct panel_desc ti_nspire_classic_lcd_panel = {
3800 .modes = ti_nspire_classic_lcd_mode,
3802 /* The grayscale panel has 8 bit for the color .. Y (black) */
3808 /* This is the grayscale bus format */
3809 .bus_format = MEDIA_BUS_FMT_Y8_1X8,
3810 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
3813 static const struct drm_display_mode toshiba_lt089ac29000_mode = {
3816 .hsync_start = 1280 + 192,
3817 .hsync_end = 1280 + 192 + 128,
3818 .htotal = 1280 + 192 + 128 + 64,
3820 .vsync_start = 768 + 20,
3821 .vsync_end = 768 + 20 + 7,
3822 .vtotal = 768 + 20 + 7 + 3,
3825 static const struct panel_desc toshiba_lt089ac29000 = {
3826 .modes = &toshiba_lt089ac29000_mode,
3832 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
3833 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
3834 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3837 static const struct drm_display_mode tpk_f07a_0102_mode = {
3840 .hsync_start = 800 + 40,
3841 .hsync_end = 800 + 40 + 128,
3842 .htotal = 800 + 40 + 128 + 88,
3844 .vsync_start = 480 + 10,
3845 .vsync_end = 480 + 10 + 2,
3846 .vtotal = 480 + 10 + 2 + 33,
3849 static const struct panel_desc tpk_f07a_0102 = {
3850 .modes = &tpk_f07a_0102_mode,
3856 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
3859 static const struct drm_display_mode tpk_f10a_0102_mode = {
3862 .hsync_start = 1024 + 176,
3863 .hsync_end = 1024 + 176 + 5,
3864 .htotal = 1024 + 176 + 5 + 88,
3866 .vsync_start = 600 + 20,
3867 .vsync_end = 600 + 20 + 5,
3868 .vtotal = 600 + 20 + 5 + 25,
3871 static const struct panel_desc tpk_f10a_0102 = {
3872 .modes = &tpk_f10a_0102_mode,
3880 static const struct display_timing urt_umsh_8596md_timing = {
3881 .pixelclock = { 33260000, 33260000, 33260000 },
3882 .hactive = { 800, 800, 800 },
3883 .hfront_porch = { 41, 41, 41 },
3884 .hback_porch = { 216 - 128, 216 - 128, 216 - 128 },
3885 .hsync_len = { 71, 128, 128 },
3886 .vactive = { 480, 480, 480 },
3887 .vfront_porch = { 10, 10, 10 },
3888 .vback_porch = { 35 - 2, 35 - 2, 35 - 2 },
3889 .vsync_len = { 2, 2, 2 },
3890 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE |
3891 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
3894 static const struct panel_desc urt_umsh_8596md_lvds = {
3895 .timings = &urt_umsh_8596md_timing,
3902 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
3903 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3906 static const struct panel_desc urt_umsh_8596md_parallel = {
3907 .timings = &urt_umsh_8596md_timing,
3914 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3917 static const struct drm_display_mode vivax_tpc9150_panel_mode = {
3920 .hsync_start = 1024 + 160,
3921 .hsync_end = 1024 + 160 + 100,
3922 .htotal = 1024 + 160 + 100 + 60,
3924 .vsync_start = 600 + 12,
3925 .vsync_end = 600 + 12 + 10,
3926 .vtotal = 600 + 12 + 10 + 13,
3929 static const struct panel_desc vivax_tpc9150_panel = {
3930 .modes = &vivax_tpc9150_panel_mode,
3937 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
3938 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
3939 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3942 static const struct drm_display_mode vl050_8048nt_c01_mode = {
3945 .hsync_start = 800 + 210,
3946 .hsync_end = 800 + 210 + 20,
3947 .htotal = 800 + 210 + 20 + 46,
3949 .vsync_start = 480 + 22,
3950 .vsync_end = 480 + 22 + 10,
3951 .vtotal = 480 + 22 + 10 + 23,
3952 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
3955 static const struct panel_desc vl050_8048nt_c01 = {
3956 .modes = &vl050_8048nt_c01_mode,
3963 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3964 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
3967 static const struct drm_display_mode winstar_wf35ltiacd_mode = {
3970 .hsync_start = 320 + 20,
3971 .hsync_end = 320 + 20 + 30,
3972 .htotal = 320 + 20 + 30 + 38,
3974 .vsync_start = 240 + 4,
3975 .vsync_end = 240 + 4 + 3,
3976 .vtotal = 240 + 4 + 3 + 15,
3977 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3980 static const struct panel_desc winstar_wf35ltiacd = {
3981 .modes = &winstar_wf35ltiacd_mode,
3988 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3991 static const struct drm_display_mode yes_optoelectronics_ytc700tlag_05_201c_mode = {
3994 .hsync_start = 1024 + 100,
3995 .hsync_end = 1024 + 100 + 100,
3996 .htotal = 1024 + 100 + 100 + 120,
3998 .vsync_start = 600 + 10,
3999 .vsync_end = 600 + 10 + 10,
4000 .vtotal = 600 + 10 + 10 + 15,
4001 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
4004 static const struct panel_desc yes_optoelectronics_ytc700tlag_05_201c = {
4005 .modes = &yes_optoelectronics_ytc700tlag_05_201c_mode,
4012 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
4013 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
4014 .connector_type = DRM_MODE_CONNECTOR_LVDS,
4017 static const struct drm_display_mode arm_rtsm_mode[] = {
4021 .hsync_start = 1024 + 24,
4022 .hsync_end = 1024 + 24 + 136,
4023 .htotal = 1024 + 24 + 136 + 160,
4025 .vsync_start = 768 + 3,
4026 .vsync_end = 768 + 3 + 6,
4027 .vtotal = 768 + 3 + 6 + 29,
4028 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
4032 static const struct panel_desc arm_rtsm = {
4033 .modes = arm_rtsm_mode,
4040 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
4043 static const struct of_device_id platform_of_match[] = {
4045 .compatible = "ampire,am-1280800n3tzqw-t00h",
4046 .data = &ire_am_1280800n3tzqw_t00h,
4048 .compatible = "ampire,am-480272h3tmqw-t01h",
4049 .data = &ire_am_480272h3tmqw_t01h,
4051 .compatible = "ampire,am-800480l1tmqw-t00h",
4052 .data = &ire_am_800480l1tmqw_t00h,
4054 .compatible = "ampire,am800480r3tmqwa1h",
4055 .data = &ire_am800480r3tmqwa1h,
4057 .compatible = "ampire,am800600p5tmqw-tb8h",
4058 .data = &ire_am800600p5tmqwtb8h,
4060 .compatible = "arm,rtsm-display",
4063 .compatible = "armadeus,st0700-adapt",
4064 .data = &armadeus_st0700_adapt,
4066 .compatible = "auo,b101aw03",
4067 .data = &auo_b101aw03,
4069 .compatible = "auo,b101xtn01",
4070 .data = &auo_b101xtn01,
4072 .compatible = "auo,g070vvn01",
4073 .data = &auo_g070vvn01,
4075 .compatible = "auo,g101evn010",
4076 .data = &auo_g101evn010,
4078 .compatible = "auo,g104sn02",
4079 .data = &auo_g104sn02,
4081 .compatible = "auo,g121ean01",
4082 .data = &auo_g121ean01,
4084 .compatible = "auo,g133han01",
4085 .data = &auo_g133han01,
4087 .compatible = "auo,g156xtn01",
4088 .data = &auo_g156xtn01,
4090 .compatible = "auo,g185han01",
4091 .data = &auo_g185han01,
4093 .compatible = "auo,g190ean01",
4094 .data = &auo_g190ean01,
4096 .compatible = "auo,p320hvn03",
4097 .data = &auo_p320hvn03,
4099 .compatible = "auo,t215hvn01",
4100 .data = &auo_t215hvn01,
4102 .compatible = "avic,tm070ddh03",
4103 .data = &avic_tm070ddh03,
4105 .compatible = "bananapi,s070wv20-ct16",
4106 .data = &bananapi_s070wv20_ct16,
4108 .compatible = "boe,ev121wxm-n10-1850",
4109 .data = &boe_ev121wxm_n10_1850,
4111 .compatible = "boe,hv070wsa-100",
4112 .data = &boe_hv070wsa
4114 .compatible = "cdtech,s043wq26h-ct7",
4115 .data = &cdtech_s043wq26h_ct7,
4117 .compatible = "cdtech,s070pws19hp-fc21",
4118 .data = &cdtech_s070pws19hp_fc21,
4120 .compatible = "cdtech,s070swv29hg-dc44",
4121 .data = &cdtech_s070swv29hg_dc44,
4123 .compatible = "cdtech,s070wv95-ct16",
4124 .data = &cdtech_s070wv95_ct16,
4126 .compatible = "chefree,ch101olhlwh-002",
4127 .data = &chefree_ch101olhlwh_002,
4129 .compatible = "chunghwa,claa070wp03xg",
4130 .data = &chunghwa_claa070wp03xg,
4132 .compatible = "chunghwa,claa101wa01a",
4133 .data = &chunghwa_claa101wa01a
4135 .compatible = "chunghwa,claa101wb01",
4136 .data = &chunghwa_claa101wb01
4138 .compatible = "dataimage,fg040346dsswbg04",
4139 .data = &dataimage_fg040346dsswbg04,
4141 .compatible = "dataimage,fg1001l0dsswmg01",
4142 .data = &dataimage_fg1001l0dsswmg01,
4144 .compatible = "dataimage,scf0700c48ggu18",
4145 .data = &dataimage_scf0700c48ggu18,
4147 .compatible = "dlc,dlc0700yzg-1",
4148 .data = &dlc_dlc0700yzg_1,
4150 .compatible = "dlc,dlc1010gig",
4151 .data = &dlc_dlc1010gig,
4153 .compatible = "edt,et035012dm6",
4154 .data = &edt_et035012dm6,
4156 .compatible = "edt,etm0350g0dh6",
4157 .data = &edt_etm0350g0dh6,
4159 .compatible = "edt,etm043080dh6gp",
4160 .data = &edt_etm043080dh6gp,
4162 .compatible = "edt,etm0430g0dh6",
4163 .data = &edt_etm0430g0dh6,
4165 .compatible = "edt,et057090dhu",
4166 .data = &edt_et057090dhu,
4168 .compatible = "edt,et070080dh6",
4169 .data = &edt_etm0700g0dh6,
4171 .compatible = "edt,etm0700g0dh6",
4172 .data = &edt_etm0700g0dh6,
4174 .compatible = "edt,etm0700g0bdh6",
4175 .data = &edt_etm0700g0bdh6,
4177 .compatible = "edt,etm0700g0edh6",
4178 .data = &edt_etm0700g0bdh6,
4180 .compatible = "edt,etml0700y5dha",
4181 .data = &edt_etml0700y5dha,
4183 .compatible = "edt,etmv570g2dhu",
4184 .data = &edt_etmv570g2dhu,
4186 .compatible = "eink,vb3300-kca",
4187 .data = &eink_vb3300_kca,
4189 .compatible = "evervision,vgg804821",
4190 .data = &evervision_vgg804821,
4192 .compatible = "foxlink,fl500wvr00-a0t",
4193 .data = &foxlink_fl500wvr00_a0t,
4195 .compatible = "frida,frd350h54004",
4196 .data = &frida_frd350h54004,
4198 .compatible = "friendlyarm,hd702e",
4199 .data = &friendlyarm_hd702e,
4201 .compatible = "giantplus,gpg482739qs5",
4202 .data = &giantplus_gpg482739qs5
4204 .compatible = "giantplus,gpm940b0",
4205 .data = &giantplus_gpm940b0,
4207 .compatible = "hannstar,hsd070pww1",
4208 .data = &hannstar_hsd070pww1,
4210 .compatible = "hannstar,hsd100pxn1",
4211 .data = &hannstar_hsd100pxn1,
4213 .compatible = "hannstar,hsd101pww2",
4214 .data = &hannstar_hsd101pww2,
4216 .compatible = "hit,tx23d38vm0caa",
4217 .data = &hitachi_tx23d38vm0caa
4219 .compatible = "innolux,at043tn24",
4220 .data = &innolux_at043tn24,
4222 .compatible = "innolux,at070tn92",
4223 .data = &innolux_at070tn92,
4225 .compatible = "innolux,g070ace-l01",
4226 .data = &innolux_g070ace_l01,
4228 .compatible = "innolux,g070y2-l01",
4229 .data = &innolux_g070y2_l01,
4231 .compatible = "innolux,g070y2-t02",
4232 .data = &innolux_g070y2_t02,
4234 .compatible = "innolux,g101ice-l01",
4235 .data = &innolux_g101ice_l01
4237 .compatible = "innolux,g121i1-l01",
4238 .data = &innolux_g121i1_l01
4240 .compatible = "innolux,g121x1-l03",
4241 .data = &innolux_g121x1_l03,
4243 .compatible = "innolux,n156bge-l21",
4244 .data = &innolux_n156bge_l21,
4246 .compatible = "innolux,zj070na-01p",
4247 .data = &innolux_zj070na_01p,
4249 .compatible = "koe,tx14d24vm1bpa",
4250 .data = &koe_tx14d24vm1bpa,
4252 .compatible = "koe,tx26d202vm0bwa",
4253 .data = &koe_tx26d202vm0bwa,
4255 .compatible = "koe,tx31d200vm0baa",
4256 .data = &koe_tx31d200vm0baa,
4258 .compatible = "kyo,tcg121xglp",
4259 .data = &kyo_tcg121xglp,
4261 .compatible = "lemaker,bl035-rgb-002",
4262 .data = &lemaker_bl035_rgb_002,
4264 .compatible = "lg,lb070wv8",
4265 .data = &lg_lb070wv8,
4267 .compatible = "logicpd,type28",
4268 .data = &logicpd_type_28,
4270 .compatible = "logictechno,lt161010-2nhc",
4271 .data = &logictechno_lt161010_2nh,
4273 .compatible = "logictechno,lt161010-2nhr",
4274 .data = &logictechno_lt161010_2nh,
4276 .compatible = "logictechno,lt170410-2whc",
4277 .data = &logictechno_lt170410_2whc,
4279 .compatible = "logictechno,lttd800480070-l2rt",
4280 .data = &logictechno_lttd800480070_l2rt,
4282 .compatible = "logictechno,lttd800480070-l6wh-rt",
4283 .data = &logictechno_lttd800480070_l6wh_rt,
4285 .compatible = "mitsubishi,aa070mc01-ca1",
4286 .data = &mitsubishi_aa070mc01,
4288 .compatible = "multi-inno,mi0700s4t-6",
4289 .data = &multi_inno_mi0700s4t_6,
4291 .compatible = "multi-inno,mi0800ft-9",
4292 .data = &multi_inno_mi0800ft_9,
4294 .compatible = "multi-inno,mi1010ait-1cp",
4295 .data = &multi_inno_mi1010ait_1cp,
4297 .compatible = "nec,nl12880bc20-05",
4298 .data = &nec_nl12880bc20_05,
4300 .compatible = "nec,nl4827hc19-05b",
4301 .data = &nec_nl4827hc19_05b,
4303 .compatible = "netron-dy,e231732",
4304 .data = &netron_dy_e231732,
4306 .compatible = "newhaven,nhd-4.3-480272ef-atxl",
4307 .data = &newhaven_nhd_43_480272ef_atxl,
4309 .compatible = "nlt,nl192108ac18-02d",
4310 .data = &nlt_nl192108ac18_02d,
4312 .compatible = "nvd,9128",
4315 .compatible = "okaya,rs800480t-7x0gp",
4316 .data = &okaya_rs800480t_7x0gp,
4318 .compatible = "olimex,lcd-olinuxino-43-ts",
4319 .data = &olimex_lcd_olinuxino_43ts,
4321 .compatible = "ontat,yx700wv03",
4322 .data = &ontat_yx700wv03,
4324 .compatible = "ortustech,com37h3m05dtc",
4325 .data = &ortustech_com37h3m,
4327 .compatible = "ortustech,com37h3m99dtc",
4328 .data = &ortustech_com37h3m,
4330 .compatible = "ortustech,com43h4m85ulc",
4331 .data = &ortustech_com43h4m85ulc,
4333 .compatible = "osddisplays,osd070t1718-19ts",
4334 .data = &osddisplays_osd070t1718_19ts,
4336 .compatible = "pda,91-00156-a0",
4337 .data = &pda_91_00156_a0,
4339 .compatible = "powertip,ph800480t013-idf02",
4340 .data = &powertip_ph800480t013_idf02,
4342 .compatible = "qiaodian,qd43003c0-40",
4343 .data = &qd43003c0_40,
4345 .compatible = "qishenglong,gopher2b-lcd",
4346 .data = &qishenglong_gopher2b_lcd,
4348 .compatible = "rocktech,rk043fn48h",
4349 .data = &rocktech_rk043fn48h,
4351 .compatible = "rocktech,rk070er9427",
4352 .data = &rocktech_rk070er9427,
4354 .compatible = "rocktech,rk101ii01d-ct",
4355 .data = &rocktech_rk101ii01d_ct,
4357 .compatible = "samsung,ltl101al01",
4358 .data = &samsung_ltl101al01,
4360 .compatible = "samsung,ltn101nt05",
4361 .data = &samsung_ltn101nt05,
4363 .compatible = "satoz,sat050at40h12r2",
4364 .data = &satoz_sat050at40h12r2,
4366 .compatible = "sharp,lq035q7db03",
4367 .data = &sharp_lq035q7db03,
4369 .compatible = "sharp,lq070y3dg3b",
4370 .data = &sharp_lq070y3dg3b,
4372 .compatible = "sharp,lq101k1ly04",
4373 .data = &sharp_lq101k1ly04,
4375 .compatible = "sharp,ls020b1dd01d",
4376 .data = &sharp_ls020b1dd01d,
4378 .compatible = "shelly,sca07010-bfn-lnn",
4379 .data = &shelly_sca07010_bfn_lnn,
4381 .compatible = "starry,kr070pe2t",
4382 .data = &starry_kr070pe2t,
4384 .compatible = "startek,kd070wvfpa",
4385 .data = &startek_kd070wvfpa,
4387 .compatible = "team-source-display,tst043015cmhx",
4388 .data = &tsd_tst043015cmhx,
4390 .compatible = "tfc,s9700rtwv43tr-01b",
4391 .data = &tfc_s9700rtwv43tr_01b,
4393 .compatible = "tianma,tm070jdhg30",
4394 .data = &tianma_tm070jdhg30,
4396 .compatible = "tianma,tm070jvhg33",
4397 .data = &tianma_tm070jvhg33,
4399 .compatible = "tianma,tm070rvhg71",
4400 .data = &tianma_tm070rvhg71,
4402 .compatible = "ti,nspire-cx-lcd-panel",
4403 .data = &ti_nspire_cx_lcd_panel,
4405 .compatible = "ti,nspire-classic-lcd-panel",
4406 .data = &ti_nspire_classic_lcd_panel,
4408 .compatible = "toshiba,lt089ac29000",
4409 .data = &toshiba_lt089ac29000,
4411 .compatible = "tpk,f07a-0102",
4412 .data = &tpk_f07a_0102,
4414 .compatible = "tpk,f10a-0102",
4415 .data = &tpk_f10a_0102,
4417 .compatible = "urt,umsh-8596md-t",
4418 .data = &urt_umsh_8596md_parallel,
4420 .compatible = "urt,umsh-8596md-1t",
4421 .data = &urt_umsh_8596md_parallel,
4423 .compatible = "urt,umsh-8596md-7t",
4424 .data = &urt_umsh_8596md_parallel,
4426 .compatible = "urt,umsh-8596md-11t",
4427 .data = &urt_umsh_8596md_lvds,
4429 .compatible = "urt,umsh-8596md-19t",
4430 .data = &urt_umsh_8596md_lvds,
4432 .compatible = "urt,umsh-8596md-20t",
4433 .data = &urt_umsh_8596md_parallel,
4435 .compatible = "vivax,tpc9150-panel",
4436 .data = &vivax_tpc9150_panel,
4438 .compatible = "vxt,vl050-8048nt-c01",
4439 .data = &vl050_8048nt_c01,
4441 .compatible = "winstar,wf35ltiacd",
4442 .data = &winstar_wf35ltiacd,
4444 .compatible = "yes-optoelectronics,ytc700tlag-05-201c",
4445 .data = &yes_optoelectronics_ytc700tlag_05_201c,
4447 /* Must be the last entry */
4448 .compatible = "panel-dpi",
4454 MODULE_DEVICE_TABLE(of, platform_of_match);
4456 static int panel_simple_platform_probe(struct platform_device *pdev)
4458 const struct of_device_id *id;
4460 id = of_match_node(platform_of_match, pdev->dev.of_node);
4464 return panel_simple_probe(&pdev->dev, id->data);
4467 static void panel_simple_platform_remove(struct platform_device *pdev)
4469 panel_simple_remove(&pdev->dev);
4472 static void panel_simple_platform_shutdown(struct platform_device *pdev)
4474 panel_simple_shutdown(&pdev->dev);
4477 static const struct dev_pm_ops panel_simple_pm_ops = {
4478 SET_RUNTIME_PM_OPS(panel_simple_suspend, panel_simple_resume, NULL)
4479 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
4480 pm_runtime_force_resume)
4483 static struct platform_driver panel_simple_platform_driver = {
4485 .name = "panel-simple",
4486 .of_match_table = platform_of_match,
4487 .pm = &panel_simple_pm_ops,
4489 .probe = panel_simple_platform_probe,
4490 .remove_new = panel_simple_platform_remove,
4491 .shutdown = panel_simple_platform_shutdown,
4494 struct panel_desc_dsi {
4495 struct panel_desc desc;
4497 unsigned long flags;
4498 enum mipi_dsi_pixel_format format;
4502 static const struct drm_display_mode auo_b080uan01_mode = {
4505 .hsync_start = 1200 + 62,
4506 .hsync_end = 1200 + 62 + 4,
4507 .htotal = 1200 + 62 + 4 + 62,
4509 .vsync_start = 1920 + 9,
4510 .vsync_end = 1920 + 9 + 2,
4511 .vtotal = 1920 + 9 + 2 + 8,
4514 static const struct panel_desc_dsi auo_b080uan01 = {
4516 .modes = &auo_b080uan01_mode,
4523 .connector_type = DRM_MODE_CONNECTOR_DSI,
4525 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
4526 .format = MIPI_DSI_FMT_RGB888,
4530 static const struct drm_display_mode boe_tv080wum_nl0_mode = {
4533 .hsync_start = 1200 + 120,
4534 .hsync_end = 1200 + 120 + 20,
4535 .htotal = 1200 + 120 + 20 + 21,
4537 .vsync_start = 1920 + 21,
4538 .vsync_end = 1920 + 21 + 3,
4539 .vtotal = 1920 + 21 + 3 + 18,
4540 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
4543 static const struct panel_desc_dsi boe_tv080wum_nl0 = {
4545 .modes = &boe_tv080wum_nl0_mode,
4551 .connector_type = DRM_MODE_CONNECTOR_DSI,
4553 .flags = MIPI_DSI_MODE_VIDEO |
4554 MIPI_DSI_MODE_VIDEO_BURST |
4555 MIPI_DSI_MODE_VIDEO_SYNC_PULSE,
4556 .format = MIPI_DSI_FMT_RGB888,
4560 static const struct drm_display_mode lg_ld070wx3_sl01_mode = {
4563 .hsync_start = 800 + 32,
4564 .hsync_end = 800 + 32 + 1,
4565 .htotal = 800 + 32 + 1 + 57,
4567 .vsync_start = 1280 + 28,
4568 .vsync_end = 1280 + 28 + 1,
4569 .vtotal = 1280 + 28 + 1 + 14,
4572 static const struct panel_desc_dsi lg_ld070wx3_sl01 = {
4574 .modes = &lg_ld070wx3_sl01_mode,
4581 .connector_type = DRM_MODE_CONNECTOR_DSI,
4583 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
4584 .format = MIPI_DSI_FMT_RGB888,
4588 static const struct drm_display_mode lg_lh500wx1_sd03_mode = {
4591 .hsync_start = 720 + 12,
4592 .hsync_end = 720 + 12 + 4,
4593 .htotal = 720 + 12 + 4 + 112,
4595 .vsync_start = 1280 + 8,
4596 .vsync_end = 1280 + 8 + 4,
4597 .vtotal = 1280 + 8 + 4 + 12,
4600 static const struct panel_desc_dsi lg_lh500wx1_sd03 = {
4602 .modes = &lg_lh500wx1_sd03_mode,
4609 .connector_type = DRM_MODE_CONNECTOR_DSI,
4611 .flags = MIPI_DSI_MODE_VIDEO,
4612 .format = MIPI_DSI_FMT_RGB888,
4616 static const struct drm_display_mode panasonic_vvx10f004b00_mode = {
4619 .hsync_start = 1920 + 154,
4620 .hsync_end = 1920 + 154 + 16,
4621 .htotal = 1920 + 154 + 16 + 32,
4623 .vsync_start = 1200 + 17,
4624 .vsync_end = 1200 + 17 + 2,
4625 .vtotal = 1200 + 17 + 2 + 16,
4628 static const struct panel_desc_dsi panasonic_vvx10f004b00 = {
4630 .modes = &panasonic_vvx10f004b00_mode,
4637 .connector_type = DRM_MODE_CONNECTOR_DSI,
4639 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
4640 MIPI_DSI_CLOCK_NON_CONTINUOUS,
4641 .format = MIPI_DSI_FMT_RGB888,
4645 static const struct drm_display_mode lg_acx467akm_7_mode = {
4648 .hsync_start = 1080 + 2,
4649 .hsync_end = 1080 + 2 + 2,
4650 .htotal = 1080 + 2 + 2 + 2,
4652 .vsync_start = 1920 + 2,
4653 .vsync_end = 1920 + 2 + 2,
4654 .vtotal = 1920 + 2 + 2 + 2,
4657 static const struct panel_desc_dsi lg_acx467akm_7 = {
4659 .modes = &lg_acx467akm_7_mode,
4666 .connector_type = DRM_MODE_CONNECTOR_DSI,
4669 .format = MIPI_DSI_FMT_RGB888,
4673 static const struct drm_display_mode osd101t2045_53ts_mode = {
4676 .hsync_start = 1920 + 112,
4677 .hsync_end = 1920 + 112 + 16,
4678 .htotal = 1920 + 112 + 16 + 32,
4680 .vsync_start = 1200 + 16,
4681 .vsync_end = 1200 + 16 + 2,
4682 .vtotal = 1200 + 16 + 2 + 16,
4683 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
4686 static const struct panel_desc_dsi osd101t2045_53ts = {
4688 .modes = &osd101t2045_53ts_mode,
4695 .connector_type = DRM_MODE_CONNECTOR_DSI,
4697 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
4698 MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
4699 MIPI_DSI_MODE_NO_EOT_PACKET,
4700 .format = MIPI_DSI_FMT_RGB888,
4704 static const struct of_device_id dsi_of_match[] = {
4706 .compatible = "auo,b080uan01",
4707 .data = &auo_b080uan01
4709 .compatible = "boe,tv080wum-nl0",
4710 .data = &boe_tv080wum_nl0
4712 .compatible = "lg,ld070wx3-sl01",
4713 .data = &lg_ld070wx3_sl01
4715 .compatible = "lg,lh500wx1-sd03",
4716 .data = &lg_lh500wx1_sd03
4718 .compatible = "panasonic,vvx10f004b00",
4719 .data = &panasonic_vvx10f004b00
4721 .compatible = "lg,acx467akm-7",
4722 .data = &lg_acx467akm_7
4724 .compatible = "osddisplays,osd101t2045-53ts",
4725 .data = &osd101t2045_53ts
4730 MODULE_DEVICE_TABLE(of, dsi_of_match);
4732 static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi)
4734 const struct panel_desc_dsi *desc;
4735 const struct of_device_id *id;
4738 id = of_match_node(dsi_of_match, dsi->dev.of_node);
4744 err = panel_simple_probe(&dsi->dev, &desc->desc);
4748 dsi->mode_flags = desc->flags;
4749 dsi->format = desc->format;
4750 dsi->lanes = desc->lanes;
4752 err = mipi_dsi_attach(dsi);
4754 struct panel_simple *panel = mipi_dsi_get_drvdata(dsi);
4756 drm_panel_remove(&panel->base);
4762 static void panel_simple_dsi_remove(struct mipi_dsi_device *dsi)
4766 err = mipi_dsi_detach(dsi);
4768 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err);
4770 panel_simple_remove(&dsi->dev);
4773 static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi)
4775 panel_simple_shutdown(&dsi->dev);
4778 static struct mipi_dsi_driver panel_simple_dsi_driver = {
4780 .name = "panel-simple-dsi",
4781 .of_match_table = dsi_of_match,
4782 .pm = &panel_simple_pm_ops,
4784 .probe = panel_simple_dsi_probe,
4785 .remove = panel_simple_dsi_remove,
4786 .shutdown = panel_simple_dsi_shutdown,
4789 static int __init panel_simple_init(void)
4793 err = platform_driver_register(&panel_simple_platform_driver);
4797 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) {
4798 err = mipi_dsi_driver_register(&panel_simple_dsi_driver);
4800 goto err_did_platform_register;
4805 err_did_platform_register:
4806 platform_driver_unregister(&panel_simple_platform_driver);
4810 module_init(panel_simple_init);
4812 static void __exit panel_simple_exit(void)
4814 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI))
4815 mipi_dsi_driver_unregister(&panel_simple_dsi_driver);
4817 platform_driver_unregister(&panel_simple_platform_driver);
4819 module_exit(panel_simple_exit);
4821 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
4822 MODULE_DESCRIPTION("DRM Driver for Simple Panels");
4823 MODULE_LICENSE("GPL and additional rights");