drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2018 MediaTek Inc.
   4  * Author: Jitao Shi <jitao.shi@mediatek.com>
   5  */
   6
   7 #include <linux/delay.h>
   8 #include <linux/gpio/consumer.h>
   9 #include <linux/module.h>
  10 #include <linux/of.h>
  11 #include <linux/of_device.h>
  12 #include <linux/regulator/consumer.h>
  13
  14 #include <drm/drm_crtc.h>
  15 #include <drm/drm_mipi_dsi.h>
  16 #include <drm/drm_panel.h>
  17
  18 #include <video/mipi_display.h>
  19
  20 struct panel_desc {
  21         const struct drm_display_mode *modes;
  22         unsigned int bpc;
  23
  24         /**
  25          * @width_mm: width of the panel's active display area
  26          * @height_mm: height of the panel's active display area
  27          */
  28         struct {
  29                 unsigned int width_mm;
  30                 unsigned int height_mm;
  31         } size;
  32
  33         unsigned long mode_flags;
  34         enum mipi_dsi_pixel_format format;
  35         const struct panel_init_cmd *init_cmds;
  36         unsigned int lanes;
  37         bool discharge_on_disable;
  38 };
  39
  40 struct boe_panel {
  41         struct drm_panel base;
  42         struct mipi_dsi_device *dsi;
  43
  44         const struct panel_desc *desc;
  45
  46         struct regulator *pp1800;
  47         struct regulator *avee;
  48         struct regulator *avdd;
  49         struct gpio_desc *enable_gpio;
  50
  51         bool prepared;
  52 };
  53
  54 enum dsi_cmd_type {
  55         INIT_DCS_CMD,
  56         DELAY_CMD,
  57 };
  58
  59 struct panel_init_cmd {
  60         enum dsi_cmd_type type;
  61         size_t len;
  62         const char *data;
  63 };
  64
  65 #define _INIT_DCS_CMD(...) { \
  66         .type = INIT_DCS_CMD, \
  67         .len = sizeof((char[]){__VA_ARGS__}), \
  68         .data = (char[]){__VA_ARGS__} }
  69
  70 #define _INIT_DELAY_CMD(...) { \
  71         .type = DELAY_CMD,\
  72         .len = sizeof((char[]){__VA_ARGS__}), \
  73         .data = (char[]){__VA_ARGS__} }
  74
  75 static const struct panel_init_cmd boe_init_cmd[] = {
  76         _INIT_DELAY_CMD(24),
  77         _INIT_DCS_CMD(0xB0, 0x05),
  78         _INIT_DCS_CMD(0xB1, 0xE5),
  79         _INIT_DCS_CMD(0xB3, 0x52),
  80         _INIT_DCS_CMD(0xB0, 0x00),
  81         _INIT_DCS_CMD(0xB3, 0x88),
  82         _INIT_DCS_CMD(0xB0, 0x04),
  83         _INIT_DCS_CMD(0xB8, 0x00),
  84         _INIT_DCS_CMD(0xB0, 0x00),
  85         _INIT_DCS_CMD(0xB6, 0x03),
  86         _INIT_DCS_CMD(0xBA, 0x8B),
  87         _INIT_DCS_CMD(0xBF, 0x1A),
  88         _INIT_DCS_CMD(0xC0, 0x0F),
  89         _INIT_DCS_CMD(0xC2, 0x0C),
  90         _INIT_DCS_CMD(0xC3, 0x02),
  91         _INIT_DCS_CMD(0xC4, 0x0C),
  92         _INIT_DCS_CMD(0xC5, 0x02),
  93         _INIT_DCS_CMD(0xB0, 0x01),
  94         _INIT_DCS_CMD(0xE0, 0x26),
  95         _INIT_DCS_CMD(0xE1, 0x26),
  96         _INIT_DCS_CMD(0xDC, 0x00),
  97         _INIT_DCS_CMD(0xDD, 0x00),
  98         _INIT_DCS_CMD(0xCC, 0x26),
  99         _INIT_DCS_CMD(0xCD, 0x26),
 100         _INIT_DCS_CMD(0xC8, 0x00),
 101         _INIT_DCS_CMD(0xC9, 0x00),
 102         _INIT_DCS_CMD(0xD2, 0x03),
 103         _INIT_DCS_CMD(0xD3, 0x03),
 104         _INIT_DCS_CMD(0xE6, 0x04),
 105         _INIT_DCS_CMD(0xE7, 0x04),
 106         _INIT_DCS_CMD(0xC4, 0x09),
 107         _INIT_DCS_CMD(0xC5, 0x09),
 108         _INIT_DCS_CMD(0xD8, 0x0A),
 109         _INIT_DCS_CMD(0xD9, 0x0A),
 110         _INIT_DCS_CMD(0xC2, 0x0B),
 111         _INIT_DCS_CMD(0xC3, 0x0B),
 112         _INIT_DCS_CMD(0xD6, 0x0C),
 113         _INIT_DCS_CMD(0xD7, 0x0C),
 114         _INIT_DCS_CMD(0xC0, 0x05),
 115         _INIT_DCS_CMD(0xC1, 0x05),
 116         _INIT_DCS_CMD(0xD4, 0x06),
 117         _INIT_DCS_CMD(0xD5, 0x06),
 118         _INIT_DCS_CMD(0xCA, 0x07),
 119         _INIT_DCS_CMD(0xCB, 0x07),
 120         _INIT_DCS_CMD(0xDE, 0x08),
 121         _INIT_DCS_CMD(0xDF, 0x08),
 122         _INIT_DCS_CMD(0xB0, 0x02),
 123         _INIT_DCS_CMD(0xC0, 0x00),
 124         _INIT_DCS_CMD(0xC1, 0x0D),
 125         _INIT_DCS_CMD(0xC2, 0x17),
 126         _INIT_DCS_CMD(0xC3, 0x26),
 127         _INIT_DCS_CMD(0xC4, 0x31),
 128         _INIT_DCS_CMD(0xC5, 0x1C),
 129         _INIT_DCS_CMD(0xC6, 0x2C),
 130         _INIT_DCS_CMD(0xC7, 0x33),
 131         _INIT_DCS_CMD(0xC8, 0x31),
 132         _INIT_DCS_CMD(0xC9, 0x37),
 133         _INIT_DCS_CMD(0xCA, 0x37),
 134         _INIT_DCS_CMD(0xCB, 0x37),
 135         _INIT_DCS_CMD(0xCC, 0x39),
 136         _INIT_DCS_CMD(0xCD, 0x2E),
 137         _INIT_DCS_CMD(0xCE, 0x2F),
 138         _INIT_DCS_CMD(0xCF, 0x2F),
 139         _INIT_DCS_CMD(0xD0, 0x07),
 140         _INIT_DCS_CMD(0xD2, 0x00),
 141         _INIT_DCS_CMD(0xD3, 0x0D),
 142         _INIT_DCS_CMD(0xD4, 0x17),
 143         _INIT_DCS_CMD(0xD5, 0x26),
 144         _INIT_DCS_CMD(0xD6, 0x31),
 145         _INIT_DCS_CMD(0xD7, 0x3F),
 146         _INIT_DCS_CMD(0xD8, 0x3F),
 147         _INIT_DCS_CMD(0xD9, 0x3F),
 148         _INIT_DCS_CMD(0xDA, 0x3F),
 149         _INIT_DCS_CMD(0xDB, 0x37),
 150         _INIT_DCS_CMD(0xDC, 0x37),
 151         _INIT_DCS_CMD(0xDD, 0x37),
 152         _INIT_DCS_CMD(0xDE, 0x39),
 153         _INIT_DCS_CMD(0xDF, 0x2E),
 154         _INIT_DCS_CMD(0xE0, 0x2F),
 155         _INIT_DCS_CMD(0xE1, 0x2F),
 156         _INIT_DCS_CMD(0xE2, 0x07),
 157         _INIT_DCS_CMD(0xB0, 0x03),
 158         _INIT_DCS_CMD(0xC8, 0x0B),
 159         _INIT_DCS_CMD(0xC9, 0x07),
 160         _INIT_DCS_CMD(0xC3, 0x00),
 161         _INIT_DCS_CMD(0xE7, 0x00),
 162         _INIT_DCS_CMD(0xC5, 0x2A),
 163         _INIT_DCS_CMD(0xDE, 0x2A),
 164         _INIT_DCS_CMD(0xCA, 0x43),
 165         _INIT_DCS_CMD(0xC9, 0x07),
 166         _INIT_DCS_CMD(0xE4, 0xC0),
 167         _INIT_DCS_CMD(0xE5, 0x0D),
 168         _INIT_DCS_CMD(0xCB, 0x00),
 169         _INIT_DCS_CMD(0xB0, 0x06),
 170         _INIT_DCS_CMD(0xB8, 0xA5),
 171         _INIT_DCS_CMD(0xC0, 0xA5),
 172         _INIT_DCS_CMD(0xC7, 0x0F),
 173         _INIT_DCS_CMD(0xD5, 0x32),
 174         _INIT_DCS_CMD(0xB8, 0x00),
 175         _INIT_DCS_CMD(0xC0, 0x00),
 176         _INIT_DCS_CMD(0xBC, 0x00),
 177         _INIT_DCS_CMD(0xB0, 0x07),
 178         _INIT_DCS_CMD(0xB1, 0x00),
 179         _INIT_DCS_CMD(0xB2, 0x02),
 180         _INIT_DCS_CMD(0xB3, 0x0F),
 181         _INIT_DCS_CMD(0xB4, 0x25),
 182         _INIT_DCS_CMD(0xB5, 0x39),
 183         _INIT_DCS_CMD(0xB6, 0x4E),
 184         _INIT_DCS_CMD(0xB7, 0x72),
 185         _INIT_DCS_CMD(0xB8, 0x97),
 186         _INIT_DCS_CMD(0xB9, 0xDC),
 187         _INIT_DCS_CMD(0xBA, 0x22),
 188         _INIT_DCS_CMD(0xBB, 0xA4),
 189         _INIT_DCS_CMD(0xBC, 0x2B),
 190         _INIT_DCS_CMD(0xBD, 0x2F),
 191         _INIT_DCS_CMD(0xBE, 0xA9),
 192         _INIT_DCS_CMD(0xBF, 0x25),
 193         _INIT_DCS_CMD(0xC0, 0x61),
 194         _INIT_DCS_CMD(0xC1, 0x97),
 195         _INIT_DCS_CMD(0xC2, 0xB2),
 196         _INIT_DCS_CMD(0xC3, 0xCD),
 197         _INIT_DCS_CMD(0xC4, 0xD9),
 198         _INIT_DCS_CMD(0xC5, 0xE7),
 199         _INIT_DCS_CMD(0xC6, 0xF4),
 200         _INIT_DCS_CMD(0xC7, 0xFA),
 201         _INIT_DCS_CMD(0xC8, 0xFC),
 202         _INIT_DCS_CMD(0xC9, 0x00),
 203         _INIT_DCS_CMD(0xCA, 0x00),
 204         _INIT_DCS_CMD(0xCB, 0x16),
 205         _INIT_DCS_CMD(0xCC, 0xAF),
 206         _INIT_DCS_CMD(0xCD, 0xFF),
 207         _INIT_DCS_CMD(0xCE, 0xFF),
 208         _INIT_DCS_CMD(0xB0, 0x08),
 209         _INIT_DCS_CMD(0xB1, 0x04),
 210         _INIT_DCS_CMD(0xB2, 0x05),
 211         _INIT_DCS_CMD(0xB3, 0x11),
 212         _INIT_DCS_CMD(0xB4, 0x24),
 213         _INIT_DCS_CMD(0xB5, 0x39),
 214         _INIT_DCS_CMD(0xB6, 0x4F),
 215         _INIT_DCS_CMD(0xB7, 0x72),
 216         _INIT_DCS_CMD(0xB8, 0x98),
 217         _INIT_DCS_CMD(0xB9, 0xDC),
 218         _INIT_DCS_CMD(0xBA, 0x23),
 219         _INIT_DCS_CMD(0xBB, 0xA6),
 220         _INIT_DCS_CMD(0xBC, 0x2C),
 221         _INIT_DCS_CMD(0xBD, 0x30),
 222         _INIT_DCS_CMD(0xBE, 0xAA),
 223         _INIT_DCS_CMD(0xBF, 0x26),
 224         _INIT_DCS_CMD(0xC0, 0x62),
 225         _INIT_DCS_CMD(0xC1, 0x9B),
 226         _INIT_DCS_CMD(0xC2, 0xB5),
 227         _INIT_DCS_CMD(0xC3, 0xCF),
 228         _INIT_DCS_CMD(0xC4, 0xDB),
 229         _INIT_DCS_CMD(0xC5, 0xE8),
 230         _INIT_DCS_CMD(0xC6, 0xF5),
 231         _INIT_DCS_CMD(0xC7, 0xFA),
 232         _INIT_DCS_CMD(0xC8, 0xFC),
 233         _INIT_DCS_CMD(0xC9, 0x00),
 234         _INIT_DCS_CMD(0xCA, 0x00),
 235         _INIT_DCS_CMD(0xCB, 0x16),
 236         _INIT_DCS_CMD(0xCC, 0xAF),
 237         _INIT_DCS_CMD(0xCD, 0xFF),
 238         _INIT_DCS_CMD(0xCE, 0xFF),
 239         _INIT_DCS_CMD(0xB0, 0x09),
 240         _INIT_DCS_CMD(0xB1, 0x04),
 241         _INIT_DCS_CMD(0xB2, 0x02),
 242         _INIT_DCS_CMD(0xB3, 0x16),
 243         _INIT_DCS_CMD(0xB4, 0x24),
 244         _INIT_DCS_CMD(0xB5, 0x3B),
 245         _INIT_DCS_CMD(0xB6, 0x4F),
 246         _INIT_DCS_CMD(0xB7, 0x73),
 247         _INIT_DCS_CMD(0xB8, 0x99),
 248         _INIT_DCS_CMD(0xB9, 0xE0),
 249         _INIT_DCS_CMD(0xBA, 0x26),
 250         _INIT_DCS_CMD(0xBB, 0xAD),
 251         _INIT_DCS_CMD(0xBC, 0x36),
 252         _INIT_DCS_CMD(0xBD, 0x3A),
 253         _INIT_DCS_CMD(0xBE, 0xAE),
 254         _INIT_DCS_CMD(0xBF, 0x2A),
 255         _INIT_DCS_CMD(0xC0, 0x66),
 256         _INIT_DCS_CMD(0xC1, 0x9E),
 257         _INIT_DCS_CMD(0xC2, 0xB8),
 258         _INIT_DCS_CMD(0xC3, 0xD1),
 259         _INIT_DCS_CMD(0xC4, 0xDD),
 260         _INIT_DCS_CMD(0xC5, 0xE9),
 261         _INIT_DCS_CMD(0xC6, 0xF6),
 262         _INIT_DCS_CMD(0xC7, 0xFA),
 263         _INIT_DCS_CMD(0xC8, 0xFC),
 264         _INIT_DCS_CMD(0xC9, 0x00),
 265         _INIT_DCS_CMD(0xCA, 0x00),
 266         _INIT_DCS_CMD(0xCB, 0x16),
 267         _INIT_DCS_CMD(0xCC, 0xAF),
 268         _INIT_DCS_CMD(0xCD, 0xFF),
 269         _INIT_DCS_CMD(0xCE, 0xFF),
 270         _INIT_DCS_CMD(0xB0, 0x0A),
 271         _INIT_DCS_CMD(0xB1, 0x00),
 272         _INIT_DCS_CMD(0xB2, 0x02),
 273         _INIT_DCS_CMD(0xB3, 0x0F),
 274         _INIT_DCS_CMD(0xB4, 0x25),
 275         _INIT_DCS_CMD(0xB5, 0x39),
 276         _INIT_DCS_CMD(0xB6, 0x4E),
 277         _INIT_DCS_CMD(0xB7, 0x72),
 278         _INIT_DCS_CMD(0xB8, 0x97),
 279         _INIT_DCS_CMD(0xB9, 0xDC),
 280         _INIT_DCS_CMD(0xBA, 0x22),
 281         _INIT_DCS_CMD(0xBB, 0xA4),
 282         _INIT_DCS_CMD(0xBC, 0x2B),
 283         _INIT_DCS_CMD(0xBD, 0x2F),
 284         _INIT_DCS_CMD(0xBE, 0xA9),
 285         _INIT_DCS_CMD(0xBF, 0x25),
 286         _INIT_DCS_CMD(0xC0, 0x61),
 287         _INIT_DCS_CMD(0xC1, 0x97),
 288         _INIT_DCS_CMD(0xC2, 0xB2),
 289         _INIT_DCS_CMD(0xC3, 0xCD),
 290         _INIT_DCS_CMD(0xC4, 0xD9),
 291         _INIT_DCS_CMD(0xC5, 0xE7),
 292         _INIT_DCS_CMD(0xC6, 0xF4),
 293         _INIT_DCS_CMD(0xC7, 0xFA),
 294         _INIT_DCS_CMD(0xC8, 0xFC),
 295         _INIT_DCS_CMD(0xC9, 0x00),
 296         _INIT_DCS_CMD(0xCA, 0x00),
 297         _INIT_DCS_CMD(0xCB, 0x16),
 298         _INIT_DCS_CMD(0xCC, 0xAF),
 299         _INIT_DCS_CMD(0xCD, 0xFF),
 300         _INIT_DCS_CMD(0xCE, 0xFF),
 301         _INIT_DCS_CMD(0xB0, 0x0B),
 302         _INIT_DCS_CMD(0xB1, 0x04),
 303         _INIT_DCS_CMD(0xB2, 0x05),
 304         _INIT_DCS_CMD(0xB3, 0x11),
 305         _INIT_DCS_CMD(0xB4, 0x24),
 306         _INIT_DCS_CMD(0xB5, 0x39),
 307         _INIT_DCS_CMD(0xB6, 0x4F),
 308         _INIT_DCS_CMD(0xB7, 0x72),
 309         _INIT_DCS_CMD(0xB8, 0x98),
 310         _INIT_DCS_CMD(0xB9, 0xDC),
 311         _INIT_DCS_CMD(0xBA, 0x23),
 312         _INIT_DCS_CMD(0xBB, 0xA6),
 313         _INIT_DCS_CMD(0xBC, 0x2C),
 314         _INIT_DCS_CMD(0xBD, 0x30),
 315         _INIT_DCS_CMD(0xBE, 0xAA),
 316         _INIT_DCS_CMD(0xBF, 0x26),
 317         _INIT_DCS_CMD(0xC0, 0x62),
 318         _INIT_DCS_CMD(0xC1, 0x9B),
 319         _INIT_DCS_CMD(0xC2, 0xB5),
 320         _INIT_DCS_CMD(0xC3, 0xCF),
 321         _INIT_DCS_CMD(0xC4, 0xDB),
 322         _INIT_DCS_CMD(0xC5, 0xE8),
 323         _INIT_DCS_CMD(0xC6, 0xF5),
 324         _INIT_DCS_CMD(0xC7, 0xFA),
 325         _INIT_DCS_CMD(0xC8, 0xFC),
 326         _INIT_DCS_CMD(0xC9, 0x00),
 327         _INIT_DCS_CMD(0xCA, 0x00),
 328         _INIT_DCS_CMD(0xCB, 0x16),
 329         _INIT_DCS_CMD(0xCC, 0xAF),
 330         _INIT_DCS_CMD(0xCD, 0xFF),
 331         _INIT_DCS_CMD(0xCE, 0xFF),
 332         _INIT_DCS_CMD(0xB0, 0x0C),
 333         _INIT_DCS_CMD(0xB1, 0x04),
 334         _INIT_DCS_CMD(0xB2, 0x02),
 335         _INIT_DCS_CMD(0xB3, 0x16),
 336         _INIT_DCS_CMD(0xB4, 0x24),
 337         _INIT_DCS_CMD(0xB5, 0x3B),
 338         _INIT_DCS_CMD(0xB6, 0x4F),
 339         _INIT_DCS_CMD(0xB7, 0x73),
 340         _INIT_DCS_CMD(0xB8, 0x99),
 341         _INIT_DCS_CMD(0xB9, 0xE0),
 342         _INIT_DCS_CMD(0xBA, 0x26),
 343         _INIT_DCS_CMD(0xBB, 0xAD),
 344         _INIT_DCS_CMD(0xBC, 0x36),
 345         _INIT_DCS_CMD(0xBD, 0x3A),
 346         _INIT_DCS_CMD(0xBE, 0xAE),
 347         _INIT_DCS_CMD(0xBF, 0x2A),
 348         _INIT_DCS_CMD(0xC0, 0x66),
 349         _INIT_DCS_CMD(0xC1, 0x9E),
 350         _INIT_DCS_CMD(0xC2, 0xB8),
 351         _INIT_DCS_CMD(0xC3, 0xD1),
 352         _INIT_DCS_CMD(0xC4, 0xDD),
 353         _INIT_DCS_CMD(0xC5, 0xE9),
 354         _INIT_DCS_CMD(0xC6, 0xF6),
 355         _INIT_DCS_CMD(0xC7, 0xFA),
 356         _INIT_DCS_CMD(0xC8, 0xFC),
 357         _INIT_DCS_CMD(0xC9, 0x00),
 358         _INIT_DCS_CMD(0xCA, 0x00),
 359         _INIT_DCS_CMD(0xCB, 0x16),
 360         _INIT_DCS_CMD(0xCC, 0xAF),
 361         _INIT_DCS_CMD(0xCD, 0xFF),
 362         _INIT_DCS_CMD(0xCE, 0xFF),
 363         _INIT_DCS_CMD(0xB0, 0x00),
 364         _INIT_DCS_CMD(0xB3, 0x08),
 365         _INIT_DCS_CMD(0xB0, 0x04),
 366         _INIT_DCS_CMD(0xB8, 0x68),
 367         _INIT_DELAY_CMD(150),
 368         {},
 369 };
 370
 371 static const struct panel_init_cmd auo_kd101n80_45na_init_cmd[] = {
 372         _INIT_DELAY_CMD(24),
 373         _INIT_DCS_CMD(0x11),
 374         _INIT_DELAY_CMD(120),
 375         _INIT_DCS_CMD(0x29),
 376         _INIT_DELAY_CMD(120),
 377         {},
 378 };
 379
 380 static inline struct boe_panel *to_boe_panel(struct drm_panel *panel)
 381 {
 382         return container_of(panel, struct boe_panel, base);
 383 }
 384
 385 static int boe_panel_init_dcs_cmd(struct boe_panel *boe)
 386 {
 387         struct mipi_dsi_device *dsi = boe->dsi;
 388         struct drm_panel *panel = &boe->base;
 389         int i, err = 0;
 390
 391         if (boe->desc->init_cmds) {
 392                 const struct panel_init_cmd *init_cmds = boe->desc->init_cmds;
 393
 394                 for (i = 0; init_cmds[i].len != 0; i++) {
 395                         const struct panel_init_cmd *cmd = &init_cmds[i];
 396
 397                         switch (cmd->type) {
 398                         case DELAY_CMD:
 399                                 msleep(cmd->data[0]);
 400                                 err = 0;
 401                                 break;
 402
 403                         case INIT_DCS_CMD:
 404                                 err = mipi_dsi_dcs_write(dsi, cmd->data[0],
 405                                                          cmd->len <= 1 ? NULL :
 406                                                          &cmd->data[1],
 407                                                          cmd->len - 1);
 408                                 break;
 409
 410                         default:
 411                                 err = -EINVAL;
 412                         }
 413
 414                         if (err < 0) {
 415                                 dev_err(panel->dev,
 416                                         "failed to write command %u\n", i);
 417                                 return err;
 418                         }
 419                 }
 420         }
 421         return 0;
 422 }
 423
 424 static int boe_panel_enter_sleep_mode(struct boe_panel *boe)
 425 {
 426         struct mipi_dsi_device *dsi = boe->dsi;
 427         int ret;
 428
 429         dsi->mode_flags &= ~MIPI_DSI_MODE_LPM;
 430
 431         ret = mipi_dsi_dcs_set_display_off(dsi);
 432         if (ret < 0)
 433                 return ret;
 434
 435         ret = mipi_dsi_dcs_enter_sleep_mode(dsi);
 436         if (ret < 0)
 437                 return ret;
 438
 439         return 0;
 440 }
 441
 442 static int boe_panel_unprepare(struct drm_panel *panel)
 443 {
 444         struct boe_panel *boe = to_boe_panel(panel);
 445         int ret;
 446
 447         if (!boe->prepared)
 448                 return 0;
 449
 450         ret = boe_panel_enter_sleep_mode(boe);
 451         if (ret < 0) {
 452                 dev_err(panel->dev, "failed to set panel off: %d\n", ret);
 453                 return ret;
 454         }
 455
 456         msleep(150);
 457
 458         if (boe->desc->discharge_on_disable) {
 459                 regulator_disable(boe->avee);
 460                 regulator_disable(boe->avdd);
 461                 usleep_range(5000, 7000);
 462                 gpiod_set_value(boe->enable_gpio, 0);
 463                 usleep_range(5000, 7000);
 464                 regulator_disable(boe->pp1800);
 465         } else {
 466                 gpiod_set_value(boe->enable_gpio, 0);
 467                 usleep_range(500, 1000);
 468                 regulator_disable(boe->avee);
 469                 regulator_disable(boe->avdd);
 470                 usleep_range(5000, 7000);
 471                 regulator_disable(boe->pp1800);
 472         }
 473
 474         boe->prepared = false;
 475
 476         return 0;
 477 }
 478
 479 static int boe_panel_prepare(struct drm_panel *panel)
 480 {
 481         struct boe_panel *boe = to_boe_panel(panel);
 482         int ret;
 483
 484         if (boe->prepared)
 485                 return 0;
 486
 487         gpiod_set_value(boe->enable_gpio, 0);
 488         usleep_range(1000, 1500);
 489
 490         ret = regulator_enable(boe->pp1800);
 491         if (ret < 0)
 492                 return ret;
 493
 494         usleep_range(3000, 5000);
 495
 496         ret = regulator_enable(boe->avdd);
 497         if (ret < 0)
 498                 goto poweroff1v8;
 499         ret = regulator_enable(boe->avee);
 500         if (ret < 0)
 501                 goto poweroffavdd;
 502
 503         usleep_range(5000, 10000);
 504
 505         gpiod_set_value(boe->enable_gpio, 1);
 506         usleep_range(1000, 2000);
 507         gpiod_set_value(boe->enable_gpio, 0);
 508         usleep_range(1000, 2000);
 509         gpiod_set_value(boe->enable_gpio, 1);
 510         usleep_range(6000, 10000);
 511
 512         ret = boe_panel_init_dcs_cmd(boe);
 513         if (ret < 0) {
 514                 dev_err(panel->dev, "failed to init panel: %d\n", ret);
 515                 goto poweroff;
 516         }
 517
 518         boe->prepared = true;
 519
 520         return 0;
 521
 522 poweroff:
 523         regulator_disable(boe->avee);
 524 poweroffavdd:
 525         regulator_disable(boe->avdd);
 526 poweroff1v8:
 527         usleep_range(5000, 7000);
 528         regulator_disable(boe->pp1800);
 529         gpiod_set_value(boe->enable_gpio, 0);
 530
 531         return ret;
 532 }
 533
 534 static int boe_panel_enable(struct drm_panel *panel)
 535 {
 536         msleep(130);
 537         return 0;
 538 }
 539
 540 static const struct drm_display_mode boe_tv101wum_nl6_default_mode = {
 541         .clock = 159425,
 542         .hdisplay = 1200,
 543         .hsync_start = 1200 + 100,
 544         .hsync_end = 1200 + 100 + 40,
 545         .htotal = 1200 + 100 + 40 + 24,
 546         .vdisplay = 1920,
 547         .vsync_start = 1920 + 10,
 548         .vsync_end = 1920 + 10 + 14,
 549         .vtotal = 1920 + 10 + 14 + 4,
 550         .vrefresh = 60,
 551 };
 552
 553 static const struct panel_desc boe_tv101wum_nl6_desc = {
 554         .modes = &boe_tv101wum_nl6_default_mode,
 555         .bpc = 8,
 556         .size = {
 557                 .width_mm = 135,
 558                 .height_mm = 216,
 559         },
 560         .lanes = 4,
 561         .format = MIPI_DSI_FMT_RGB888,
 562         .mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
 563                       MIPI_DSI_MODE_LPM,
 564         .init_cmds = boe_init_cmd,
 565         .discharge_on_disable = false,
 566 };
 567
 568 static const struct drm_display_mode auo_kd101n80_45na_default_mode = {
 569         .clock = 157000,
 570         .hdisplay = 1200,
 571         .hsync_start = 1200 + 80,
 572         .hsync_end = 1200 + 80 + 24,
 573         .htotal = 1200 + 80 + 24 + 36,
 574         .vdisplay = 1920,
 575         .vsync_start = 1920 + 16,
 576         .vsync_end = 1920 + 16 + 4,
 577         .vtotal = 1920 + 16 + 4 + 16,
 578         .vrefresh = 60,
 579 };
 580
 581 static const struct panel_desc auo_kd101n80_45na_desc = {
 582         .modes = &auo_kd101n80_45na_default_mode,
 583         .bpc = 8,
 584         .size = {
 585                 .width_mm = 135,
 586                 .height_mm = 216,
 587         },
 588         .lanes = 4,
 589         .format = MIPI_DSI_FMT_RGB888,
 590         .mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
 591                       MIPI_DSI_MODE_LPM,
 592         .init_cmds = auo_kd101n80_45na_init_cmd,
 593         .discharge_on_disable = true,
 594 };
 595
 596 static const struct drm_display_mode boe_tv101wum_n53_default_mode = {
 597         .clock = 159916,
 598         .hdisplay = 1200,
 599         .hsync_start = 1200 + 80,
 600         .hsync_end = 1200 + 80 + 24,
 601         .htotal = 1200 + 80 + 24 + 40,
 602         .vdisplay = 1920,
 603         .vsync_start = 1920 + 20,
 604         .vsync_end = 1920 + 20 + 4,
 605         .vtotal = 1920 + 20 + 4 + 10,
 606         .vrefresh = 60,
 607         .type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,
 608 };
 609
 610 static const struct panel_desc boe_tv101wum_n53_desc = {
 611         .modes = &boe_tv101wum_n53_default_mode,
 612         .bpc = 8,
 613         .size = {
 614                 .width_mm = 135,
 615                 .height_mm = 216,
 616         },
 617         .lanes = 4,
 618         .format = MIPI_DSI_FMT_RGB888,
 619         .mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
 620                       MIPI_DSI_MODE_LPM,
 621         .init_cmds = boe_init_cmd,
 622 };
 623
 624 static int boe_panel_get_modes(struct drm_panel *panel,
 625                                struct drm_connector *connector)
 626 {
 627         struct boe_panel *boe = to_boe_panel(panel);
 628         const struct drm_display_mode *m = boe->desc->modes;
 629         struct drm_display_mode *mode;
 630
 631         mode = drm_mode_duplicate(connector->dev, m);
 632         if (!mode) {
 633                 dev_err(panel->dev, "failed to add mode %ux%u@%u\n",
 634                         m->hdisplay, m->vdisplay, m->vrefresh);
 635                 return -ENOMEM;
 636         }
 637
 638         mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
 639         drm_mode_set_name(mode);
 640         drm_mode_probed_add(connector, mode);
 641
 642         connector->display_info.width_mm = boe->desc->size.width_mm;
 643         connector->display_info.height_mm = boe->desc->size.height_mm;
 644         connector->display_info.bpc = boe->desc->bpc;
 645
 646         return 1;
 647 }
 648
 649 static const struct drm_panel_funcs boe_panel_funcs = {
 650         .unprepare = boe_panel_unprepare,
 651         .prepare = boe_panel_prepare,
 652         .enable = boe_panel_enable,
 653         .get_modes = boe_panel_get_modes,
 654 };
 655
 656 static int boe_panel_add(struct boe_panel *boe)
 657 {
 658         struct device *dev = &boe->dsi->dev;
 659         int err;
 660
 661         boe->avdd = devm_regulator_get(dev, "avdd");
 662         if (IS_ERR(boe->avdd))
 663                 return PTR_ERR(boe->avdd);
 664
 665         boe->avee = devm_regulator_get(dev, "avee");
 666         if (IS_ERR(boe->avee))
 667                 return PTR_ERR(boe->avee);
 668
 669         boe->pp1800 = devm_regulator_get(dev, "pp1800");
 670         if (IS_ERR(boe->pp1800))
 671                 return PTR_ERR(boe->pp1800);
 672
 673         boe->enable_gpio = devm_gpiod_get(dev, "enable", GPIOD_OUT_LOW);
 674         if (IS_ERR(boe->enable_gpio)) {
 675                 dev_err(dev, "cannot get reset-gpios %ld\n",
 676                         PTR_ERR(boe->enable_gpio));
 677                 return PTR_ERR(boe->enable_gpio);
 678         }
 679
 680         gpiod_set_value(boe->enable_gpio, 0);
 681
 682         drm_panel_init(&boe->base, dev, &boe_panel_funcs,
 683                        DRM_MODE_CONNECTOR_DSI);
 684
 685         err = drm_panel_of_backlight(&boe->base);
 686         if (err)
 687                 return err;
 688
 689         boe->base.funcs = &boe_panel_funcs;
 690         boe->base.dev = &boe->dsi->dev;
 691
 692         return drm_panel_add(&boe->base);
 693 }
 694
 695 static int boe_panel_probe(struct mipi_dsi_device *dsi)
 696 {
 697         struct boe_panel *boe;
 698         int ret;
 699         const struct panel_desc *desc;
 700
 701         boe = devm_kzalloc(&dsi->dev, sizeof(*boe), GFP_KERNEL);
 702         if (!boe)
 703                 return -ENOMEM;
 704
 705         desc = of_device_get_match_data(&dsi->dev);
 706         dsi->lanes = desc->lanes;
 707         dsi->format = desc->format;
 708         dsi->mode_flags = desc->mode_flags;
 709         boe->desc = desc;
 710         boe->dsi = dsi;
 711         ret = boe_panel_add(boe);
 712         if (ret < 0)
 713                 return ret;
 714
 715         mipi_dsi_set_drvdata(dsi, boe);
 716
 717         ret = mipi_dsi_attach(dsi);
 718         if (ret)
 719                 drm_panel_remove(&boe->base);
 720
 721         return ret;
 722 }
 723
 724 static void boe_panel_shutdown(struct mipi_dsi_device *dsi)
 725 {
 726         struct boe_panel *boe = mipi_dsi_get_drvdata(dsi);
 727
 728         drm_panel_disable(&boe->base);
 729         drm_panel_unprepare(&boe->base);
 730 }
 731
 732 static int boe_panel_remove(struct mipi_dsi_device *dsi)
 733 {
 734         struct boe_panel *boe = mipi_dsi_get_drvdata(dsi);
 735         int ret;
 736
 737         boe_panel_shutdown(dsi);
 738
 739         ret = mipi_dsi_detach(dsi);
 740         if (ret < 0)
 741                 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", ret);
 742
 743         if (boe->base.dev)
 744                 drm_panel_remove(&boe->base);
 745
 746         return 0;
 747 }
 748
 749 static const struct of_device_id boe_of_match[] = {
 750         { .compatible = "boe,tv101wum-nl6",
 751           .data = &boe_tv101wum_nl6_desc
 752         },
 753         { .compatible = "auo,kd101n80-45na",
 754           .data = &auo_kd101n80_45na_desc
 755         },
 756         { .compatible = "boe,tv101wum-n53",
 757           .data = &boe_tv101wum_n53_desc
 758         },
 759         { /* sentinel */ }
 760 };
 761 MODULE_DEVICE_TABLE(of, boe_of_match);
 762
 763 static struct mipi_dsi_driver boe_panel_driver = {
 764         .driver = {
 765                 .name = "panel-boe-tv101wum-nl6",
 766                 .of_match_table = boe_of_match,
 767         },
 768         .probe = boe_panel_probe,
 769         .remove = boe_panel_remove,
 770         .shutdown = boe_panel_shutdown,
 771 };
 772 module_mipi_dsi_driver(boe_panel_driver);
 773
 774 MODULE_AUTHOR("Jitao Shi <jitao.shi@mediatek.com>");
 775 MODULE_DESCRIPTION("BOE tv101wum-nl6 1200x1920 video mode panel driver");
 776 MODULE_LICENSE("GPL v2");