drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2018 MediaTek Inc.
   4  * Author: Jitao Shi <jitao.shi@mediatek.com>
   5  */
   6
   7 #include <linux/delay.h>
   8 #include <linux/gpio/consumer.h>
   9 #include <linux/module.h>
  10 #include <linux/of.h>
  11 #include <linux/of_device.h>
  12 #include <linux/regulator/consumer.h>
  13
  14 #include <drm/drm_connector.h>
  15 #include <drm/drm_crtc.h>
  16 #include <drm/drm_mipi_dsi.h>
  17 #include <drm/drm_panel.h>
  18
  19 #include <video/mipi_display.h>
  20
  21 struct panel_desc {
  22         const struct drm_display_mode *modes;
  23         unsigned int bpc;
  24
  25         /**
  26          * @width_mm: width of the panel's active display area
  27          * @height_mm: height of the panel's active display area
  28          */
  29         struct {
  30                 unsigned int width_mm;
  31                 unsigned int height_mm;
  32         } size;
  33
  34         unsigned long mode_flags;
  35         enum mipi_dsi_pixel_format format;
  36         const struct panel_init_cmd *init_cmds;
  37         unsigned int lanes;
  38         bool discharge_on_disable;
  39 };
  40
  41 struct boe_panel {
  42         struct drm_panel base;
  43         struct mipi_dsi_device *dsi;
  44
  45         const struct panel_desc *desc;
  46
  47         enum drm_panel_orientation orientation;
  48         struct regulator *pp3300;
  49         struct regulator *pp1800;
  50         struct regulator *avee;
  51         struct regulator *avdd;
  52         struct gpio_desc *enable_gpio;
  53
  54         bool prepared;
  55 };
  56
  57 enum dsi_cmd_type {
  58         INIT_DCS_CMD,
  59         DELAY_CMD,
  60 };
  61
  62 struct panel_init_cmd {
  63         enum dsi_cmd_type type;
  64         size_t len;
  65         const char *data;
  66 };
  67
  68 #define _INIT_DCS_CMD(...) { \
  69         .type = INIT_DCS_CMD, \
  70         .len = sizeof((char[]){__VA_ARGS__}), \
  71         .data = (char[]){__VA_ARGS__} }
  72
  73 #define _INIT_DELAY_CMD(...) { \
  74         .type = DELAY_CMD,\
  75         .len = sizeof((char[]){__VA_ARGS__}), \
  76         .data = (char[]){__VA_ARGS__} }
  77
  78 static const struct panel_init_cmd boe_init_cmd[] = {
  79         _INIT_DELAY_CMD(24),
  80         _INIT_DCS_CMD(0xB0, 0x05),
  81         _INIT_DCS_CMD(0xB1, 0xE5),
  82         _INIT_DCS_CMD(0xB3, 0x52),
  83         _INIT_DCS_CMD(0xB0, 0x00),
  84         _INIT_DCS_CMD(0xB3, 0x88),
  85         _INIT_DCS_CMD(0xB0, 0x04),
  86         _INIT_DCS_CMD(0xB8, 0x00),
  87         _INIT_DCS_CMD(0xB0, 0x00),
  88         _INIT_DCS_CMD(0xB6, 0x03),
  89         _INIT_DCS_CMD(0xBA, 0x8B),
  90         _INIT_DCS_CMD(0xBF, 0x1A),
  91         _INIT_DCS_CMD(0xC0, 0x0F),
  92         _INIT_DCS_CMD(0xC2, 0x0C),
  93         _INIT_DCS_CMD(0xC3, 0x02),
  94         _INIT_DCS_CMD(0xC4, 0x0C),
  95         _INIT_DCS_CMD(0xC5, 0x02),
  96         _INIT_DCS_CMD(0xB0, 0x01),
  97         _INIT_DCS_CMD(0xE0, 0x26),
  98         _INIT_DCS_CMD(0xE1, 0x26),
  99         _INIT_DCS_CMD(0xDC, 0x00),
 100         _INIT_DCS_CMD(0xDD, 0x00),
 101         _INIT_DCS_CMD(0xCC, 0x26),
 102         _INIT_DCS_CMD(0xCD, 0x26),
 103         _INIT_DCS_CMD(0xC8, 0x00),
 104         _INIT_DCS_CMD(0xC9, 0x00),
 105         _INIT_DCS_CMD(0xD2, 0x03),
 106         _INIT_DCS_CMD(0xD3, 0x03),
 107         _INIT_DCS_CMD(0xE6, 0x04),
 108         _INIT_DCS_CMD(0xE7, 0x04),
 109         _INIT_DCS_CMD(0xC4, 0x09),
 110         _INIT_DCS_CMD(0xC5, 0x09),
 111         _INIT_DCS_CMD(0xD8, 0x0A),
 112         _INIT_DCS_CMD(0xD9, 0x0A),
 113         _INIT_DCS_CMD(0xC2, 0x0B),
 114         _INIT_DCS_CMD(0xC3, 0x0B),
 115         _INIT_DCS_CMD(0xD6, 0x0C),
 116         _INIT_DCS_CMD(0xD7, 0x0C),
 117         _INIT_DCS_CMD(0xC0, 0x05),
 118         _INIT_DCS_CMD(0xC1, 0x05),
 119         _INIT_DCS_CMD(0xD4, 0x06),
 120         _INIT_DCS_CMD(0xD5, 0x06),
 121         _INIT_DCS_CMD(0xCA, 0x07),
 122         _INIT_DCS_CMD(0xCB, 0x07),
 123         _INIT_DCS_CMD(0xDE, 0x08),
 124         _INIT_DCS_CMD(0xDF, 0x08),
 125         _INIT_DCS_CMD(0xB0, 0x02),
 126         _INIT_DCS_CMD(0xC0, 0x00),
 127         _INIT_DCS_CMD(0xC1, 0x0D),
 128         _INIT_DCS_CMD(0xC2, 0x17),
 129         _INIT_DCS_CMD(0xC3, 0x26),
 130         _INIT_DCS_CMD(0xC4, 0x31),
 131         _INIT_DCS_CMD(0xC5, 0x1C),
 132         _INIT_DCS_CMD(0xC6, 0x2C),
 133         _INIT_DCS_CMD(0xC7, 0x33),
 134         _INIT_DCS_CMD(0xC8, 0x31),
 135         _INIT_DCS_CMD(0xC9, 0x37),
 136         _INIT_DCS_CMD(0xCA, 0x37),
 137         _INIT_DCS_CMD(0xCB, 0x37),
 138         _INIT_DCS_CMD(0xCC, 0x39),
 139         _INIT_DCS_CMD(0xCD, 0x2E),
 140         _INIT_DCS_CMD(0xCE, 0x2F),
 141         _INIT_DCS_CMD(0xCF, 0x2F),
 142         _INIT_DCS_CMD(0xD0, 0x07),
 143         _INIT_DCS_CMD(0xD2, 0x00),
 144         _INIT_DCS_CMD(0xD3, 0x0D),
 145         _INIT_DCS_CMD(0xD4, 0x17),
 146         _INIT_DCS_CMD(0xD5, 0x26),
 147         _INIT_DCS_CMD(0xD6, 0x31),
 148         _INIT_DCS_CMD(0xD7, 0x3F),
 149         _INIT_DCS_CMD(0xD8, 0x3F),
 150         _INIT_DCS_CMD(0xD9, 0x3F),
 151         _INIT_DCS_CMD(0xDA, 0x3F),
 152         _INIT_DCS_CMD(0xDB, 0x37),
 153         _INIT_DCS_CMD(0xDC, 0x37),
 154         _INIT_DCS_CMD(0xDD, 0x37),
 155         _INIT_DCS_CMD(0xDE, 0x39),
 156         _INIT_DCS_CMD(0xDF, 0x2E),
 157         _INIT_DCS_CMD(0xE0, 0x2F),
 158         _INIT_DCS_CMD(0xE1, 0x2F),
 159         _INIT_DCS_CMD(0xE2, 0x07),
 160         _INIT_DCS_CMD(0xB0, 0x03),
 161         _INIT_DCS_CMD(0xC8, 0x0B),
 162         _INIT_DCS_CMD(0xC9, 0x07),
 163         _INIT_DCS_CMD(0xC3, 0x00),
 164         _INIT_DCS_CMD(0xE7, 0x00),
 165         _INIT_DCS_CMD(0xC5, 0x2A),
 166         _INIT_DCS_CMD(0xDE, 0x2A),
 167         _INIT_DCS_CMD(0xCA, 0x43),
 168         _INIT_DCS_CMD(0xC9, 0x07),
 169         _INIT_DCS_CMD(0xE4, 0xC0),
 170         _INIT_DCS_CMD(0xE5, 0x0D),
 171         _INIT_DCS_CMD(0xCB, 0x00),
 172         _INIT_DCS_CMD(0xB0, 0x06),
 173         _INIT_DCS_CMD(0xB8, 0xA5),
 174         _INIT_DCS_CMD(0xC0, 0xA5),
 175         _INIT_DCS_CMD(0xC7, 0x0F),
 176         _INIT_DCS_CMD(0xD5, 0x32),
 177         _INIT_DCS_CMD(0xB8, 0x00),
 178         _INIT_DCS_CMD(0xC0, 0x00),
 179         _INIT_DCS_CMD(0xBC, 0x00),
 180         _INIT_DCS_CMD(0xB0, 0x07),
 181         _INIT_DCS_CMD(0xB1, 0x00),
 182         _INIT_DCS_CMD(0xB2, 0x02),
 183         _INIT_DCS_CMD(0xB3, 0x0F),
 184         _INIT_DCS_CMD(0xB4, 0x25),
 185         _INIT_DCS_CMD(0xB5, 0x39),
 186         _INIT_DCS_CMD(0xB6, 0x4E),
 187         _INIT_DCS_CMD(0xB7, 0x72),
 188         _INIT_DCS_CMD(0xB8, 0x97),
 189         _INIT_DCS_CMD(0xB9, 0xDC),
 190         _INIT_DCS_CMD(0xBA, 0x22),
 191         _INIT_DCS_CMD(0xBB, 0xA4),
 192         _INIT_DCS_CMD(0xBC, 0x2B),
 193         _INIT_DCS_CMD(0xBD, 0x2F),
 194         _INIT_DCS_CMD(0xBE, 0xA9),
 195         _INIT_DCS_CMD(0xBF, 0x25),
 196         _INIT_DCS_CMD(0xC0, 0x61),
 197         _INIT_DCS_CMD(0xC1, 0x97),
 198         _INIT_DCS_CMD(0xC2, 0xB2),
 199         _INIT_DCS_CMD(0xC3, 0xCD),
 200         _INIT_DCS_CMD(0xC4, 0xD9),
 201         _INIT_DCS_CMD(0xC5, 0xE7),
 202         _INIT_DCS_CMD(0xC6, 0xF4),
 203         _INIT_DCS_CMD(0xC7, 0xFA),
 204         _INIT_DCS_CMD(0xC8, 0xFC),
 205         _INIT_DCS_CMD(0xC9, 0x00),
 206         _INIT_DCS_CMD(0xCA, 0x00),
 207         _INIT_DCS_CMD(0xCB, 0x16),
 208         _INIT_DCS_CMD(0xCC, 0xAF),
 209         _INIT_DCS_CMD(0xCD, 0xFF),
 210         _INIT_DCS_CMD(0xCE, 0xFF),
 211         _INIT_DCS_CMD(0xB0, 0x08),
 212         _INIT_DCS_CMD(0xB1, 0x04),
 213         _INIT_DCS_CMD(0xB2, 0x05),
 214         _INIT_DCS_CMD(0xB3, 0x11),
 215         _INIT_DCS_CMD(0xB4, 0x24),
 216         _INIT_DCS_CMD(0xB5, 0x39),
 217         _INIT_DCS_CMD(0xB6, 0x4F),
 218         _INIT_DCS_CMD(0xB7, 0x72),
 219         _INIT_DCS_CMD(0xB8, 0x98),
 220         _INIT_DCS_CMD(0xB9, 0xDC),
 221         _INIT_DCS_CMD(0xBA, 0x23),
 222         _INIT_DCS_CMD(0xBB, 0xA6),
 223         _INIT_DCS_CMD(0xBC, 0x2C),
 224         _INIT_DCS_CMD(0xBD, 0x30),
 225         _INIT_DCS_CMD(0xBE, 0xAA),
 226         _INIT_DCS_CMD(0xBF, 0x26),
 227         _INIT_DCS_CMD(0xC0, 0x62),
 228         _INIT_DCS_CMD(0xC1, 0x9B),
 229         _INIT_DCS_CMD(0xC2, 0xB5),
 230         _INIT_DCS_CMD(0xC3, 0xCF),
 231         _INIT_DCS_CMD(0xC4, 0xDB),
 232         _INIT_DCS_CMD(0xC5, 0xE8),
 233         _INIT_DCS_CMD(0xC6, 0xF5),
 234         _INIT_DCS_CMD(0xC7, 0xFA),
 235         _INIT_DCS_CMD(0xC8, 0xFC),
 236         _INIT_DCS_CMD(0xC9, 0x00),
 237         _INIT_DCS_CMD(0xCA, 0x00),
 238         _INIT_DCS_CMD(0xCB, 0x16),
 239         _INIT_DCS_CMD(0xCC, 0xAF),
 240         _INIT_DCS_CMD(0xCD, 0xFF),
 241         _INIT_DCS_CMD(0xCE, 0xFF),
 242         _INIT_DCS_CMD(0xB0, 0x09),
 243         _INIT_DCS_CMD(0xB1, 0x04),
 244         _INIT_DCS_CMD(0xB2, 0x02),
 245         _INIT_DCS_CMD(0xB3, 0x16),
 246         _INIT_DCS_CMD(0xB4, 0x24),
 247         _INIT_DCS_CMD(0xB5, 0x3B),
 248         _INIT_DCS_CMD(0xB6, 0x4F),
 249         _INIT_DCS_CMD(0xB7, 0x73),
 250         _INIT_DCS_CMD(0xB8, 0x99),
 251         _INIT_DCS_CMD(0xB9, 0xE0),
 252         _INIT_DCS_CMD(0xBA, 0x26),
 253         _INIT_DCS_CMD(0xBB, 0xAD),
 254         _INIT_DCS_CMD(0xBC, 0x36),
 255         _INIT_DCS_CMD(0xBD, 0x3A),
 256         _INIT_DCS_CMD(0xBE, 0xAE),
 257         _INIT_DCS_CMD(0xBF, 0x2A),
 258         _INIT_DCS_CMD(0xC0, 0x66),
 259         _INIT_DCS_CMD(0xC1, 0x9E),
 260         _INIT_DCS_CMD(0xC2, 0xB8),
 261         _INIT_DCS_CMD(0xC3, 0xD1),
 262         _INIT_DCS_CMD(0xC4, 0xDD),
 263         _INIT_DCS_CMD(0xC5, 0xE9),
 264         _INIT_DCS_CMD(0xC6, 0xF6),
 265         _INIT_DCS_CMD(0xC7, 0xFA),
 266         _INIT_DCS_CMD(0xC8, 0xFC),
 267         _INIT_DCS_CMD(0xC9, 0x00),
 268         _INIT_DCS_CMD(0xCA, 0x00),
 269         _INIT_DCS_CMD(0xCB, 0x16),
 270         _INIT_DCS_CMD(0xCC, 0xAF),
 271         _INIT_DCS_CMD(0xCD, 0xFF),
 272         _INIT_DCS_CMD(0xCE, 0xFF),
 273         _INIT_DCS_CMD(0xB0, 0x0A),
 274         _INIT_DCS_CMD(0xB1, 0x00),
 275         _INIT_DCS_CMD(0xB2, 0x02),
 276         _INIT_DCS_CMD(0xB3, 0x0F),
 277         _INIT_DCS_CMD(0xB4, 0x25),
 278         _INIT_DCS_CMD(0xB5, 0x39),
 279         _INIT_DCS_CMD(0xB6, 0x4E),
 280         _INIT_DCS_CMD(0xB7, 0x72),
 281         _INIT_DCS_CMD(0xB8, 0x97),
 282         _INIT_DCS_CMD(0xB9, 0xDC),
 283         _INIT_DCS_CMD(0xBA, 0x22),
 284         _INIT_DCS_CMD(0xBB, 0xA4),
 285         _INIT_DCS_CMD(0xBC, 0x2B),
 286         _INIT_DCS_CMD(0xBD, 0x2F),
 287         _INIT_DCS_CMD(0xBE, 0xA9),
 288         _INIT_DCS_CMD(0xBF, 0x25),
 289         _INIT_DCS_CMD(0xC0, 0x61),
 290         _INIT_DCS_CMD(0xC1, 0x97),
 291         _INIT_DCS_CMD(0xC2, 0xB2),
 292         _INIT_DCS_CMD(0xC3, 0xCD),
 293         _INIT_DCS_CMD(0xC4, 0xD9),
 294         _INIT_DCS_CMD(0xC5, 0xE7),
 295         _INIT_DCS_CMD(0xC6, 0xF4),
 296         _INIT_DCS_CMD(0xC7, 0xFA),
 297         _INIT_DCS_CMD(0xC8, 0xFC),
 298         _INIT_DCS_CMD(0xC9, 0x00),
 299         _INIT_DCS_CMD(0xCA, 0x00),
 300         _INIT_DCS_CMD(0xCB, 0x16),
 301         _INIT_DCS_CMD(0xCC, 0xAF),
 302         _INIT_DCS_CMD(0xCD, 0xFF),
 303         _INIT_DCS_CMD(0xCE, 0xFF),
 304         _INIT_DCS_CMD(0xB0, 0x0B),
 305         _INIT_DCS_CMD(0xB1, 0x04),
 306         _INIT_DCS_CMD(0xB2, 0x05),
 307         _INIT_DCS_CMD(0xB3, 0x11),
 308         _INIT_DCS_CMD(0xB4, 0x24),
 309         _INIT_DCS_CMD(0xB5, 0x39),
 310         _INIT_DCS_CMD(0xB6, 0x4F),
 311         _INIT_DCS_CMD(0xB7, 0x72),
 312         _INIT_DCS_CMD(0xB8, 0x98),
 313         _INIT_DCS_CMD(0xB9, 0xDC),
 314         _INIT_DCS_CMD(0xBA, 0x23),
 315         _INIT_DCS_CMD(0xBB, 0xA6),
 316         _INIT_DCS_CMD(0xBC, 0x2C),
 317         _INIT_DCS_CMD(0xBD, 0x30),
 318         _INIT_DCS_CMD(0xBE, 0xAA),
 319         _INIT_DCS_CMD(0xBF, 0x26),
 320         _INIT_DCS_CMD(0xC0, 0x62),
 321         _INIT_DCS_CMD(0xC1, 0x9B),
 322         _INIT_DCS_CMD(0xC2, 0xB5),
 323         _INIT_DCS_CMD(0xC3, 0xCF),
 324         _INIT_DCS_CMD(0xC4, 0xDB),
 325         _INIT_DCS_CMD(0xC5, 0xE8),
 326         _INIT_DCS_CMD(0xC6, 0xF5),
 327         _INIT_DCS_CMD(0xC7, 0xFA),
 328         _INIT_DCS_CMD(0xC8, 0xFC),
 329         _INIT_DCS_CMD(0xC9, 0x00),
 330         _INIT_DCS_CMD(0xCA, 0x00),
 331         _INIT_DCS_CMD(0xCB, 0x16),
 332         _INIT_DCS_CMD(0xCC, 0xAF),
 333         _INIT_DCS_CMD(0xCD, 0xFF),
 334         _INIT_DCS_CMD(0xCE, 0xFF),
 335         _INIT_DCS_CMD(0xB0, 0x0C),
 336         _INIT_DCS_CMD(0xB1, 0x04),
 337         _INIT_DCS_CMD(0xB2, 0x02),
 338         _INIT_DCS_CMD(0xB3, 0x16),
 339         _INIT_DCS_CMD(0xB4, 0x24),
 340         _INIT_DCS_CMD(0xB5, 0x3B),
 341         _INIT_DCS_CMD(0xB6, 0x4F),
 342         _INIT_DCS_CMD(0xB7, 0x73),
 343         _INIT_DCS_CMD(0xB8, 0x99),
 344         _INIT_DCS_CMD(0xB9, 0xE0),
 345         _INIT_DCS_CMD(0xBA, 0x26),
 346         _INIT_DCS_CMD(0xBB, 0xAD),
 347         _INIT_DCS_CMD(0xBC, 0x36),
 348         _INIT_DCS_CMD(0xBD, 0x3A),
 349         _INIT_DCS_CMD(0xBE, 0xAE),
 350         _INIT_DCS_CMD(0xBF, 0x2A),
 351         _INIT_DCS_CMD(0xC0, 0x66),
 352         _INIT_DCS_CMD(0xC1, 0x9E),
 353         _INIT_DCS_CMD(0xC2, 0xB8),
 354         _INIT_DCS_CMD(0xC3, 0xD1),
 355         _INIT_DCS_CMD(0xC4, 0xDD),
 356         _INIT_DCS_CMD(0xC5, 0xE9),
 357         _INIT_DCS_CMD(0xC6, 0xF6),
 358         _INIT_DCS_CMD(0xC7, 0xFA),
 359         _INIT_DCS_CMD(0xC8, 0xFC),
 360         _INIT_DCS_CMD(0xC9, 0x00),
 361         _INIT_DCS_CMD(0xCA, 0x00),
 362         _INIT_DCS_CMD(0xCB, 0x16),
 363         _INIT_DCS_CMD(0xCC, 0xAF),
 364         _INIT_DCS_CMD(0xCD, 0xFF),
 365         _INIT_DCS_CMD(0xCE, 0xFF),
 366         _INIT_DCS_CMD(0xB0, 0x00),
 367         _INIT_DCS_CMD(0xB3, 0x08),
 368         _INIT_DCS_CMD(0xB0, 0x04),
 369         _INIT_DCS_CMD(0xB8, 0x68),
 370         _INIT_DELAY_CMD(150),
 371         {},
 372 };
 373
 374 static const struct panel_init_cmd auo_kd101n80_45na_init_cmd[] = {
 375         _INIT_DELAY_CMD(24),
 376         _INIT_DCS_CMD(0x11),
 377         _INIT_DELAY_CMD(120),
 378         _INIT_DCS_CMD(0x29),
 379         _INIT_DELAY_CMD(120),
 380         {},
 381 };
 382
 383 static const struct panel_init_cmd auo_b101uan08_3_init_cmd[] = {
 384         _INIT_DELAY_CMD(24),
 385         _INIT_DCS_CMD(0xB0, 0x01),
 386         _INIT_DCS_CMD(0xC0, 0x48),
 387         _INIT_DCS_CMD(0xC1, 0x48),
 388         _INIT_DCS_CMD(0xC2, 0x47),
 389         _INIT_DCS_CMD(0xC3, 0x47),
 390         _INIT_DCS_CMD(0xC4, 0x46),
 391         _INIT_DCS_CMD(0xC5, 0x46),
 392         _INIT_DCS_CMD(0xC6, 0x45),
 393         _INIT_DCS_CMD(0xC7, 0x45),
 394         _INIT_DCS_CMD(0xC8, 0x64),
 395         _INIT_DCS_CMD(0xC9, 0x64),
 396         _INIT_DCS_CMD(0xCA, 0x4F),
 397         _INIT_DCS_CMD(0xCB, 0x4F),
 398         _INIT_DCS_CMD(0xCC, 0x40),
 399         _INIT_DCS_CMD(0xCD, 0x40),
 400         _INIT_DCS_CMD(0xCE, 0x66),
 401         _INIT_DCS_CMD(0xCF, 0x66),
 402         _INIT_DCS_CMD(0xD0, 0x4F),
 403         _INIT_DCS_CMD(0xD1, 0x4F),
 404         _INIT_DCS_CMD(0xD2, 0x41),
 405         _INIT_DCS_CMD(0xD3, 0x41),
 406         _INIT_DCS_CMD(0xD4, 0x48),
 407         _INIT_DCS_CMD(0xD5, 0x48),
 408         _INIT_DCS_CMD(0xD6, 0x47),
 409         _INIT_DCS_CMD(0xD7, 0x47),
 410         _INIT_DCS_CMD(0xD8, 0x46),
 411         _INIT_DCS_CMD(0xD9, 0x46),
 412         _INIT_DCS_CMD(0xDA, 0x45),
 413         _INIT_DCS_CMD(0xDB, 0x45),
 414         _INIT_DCS_CMD(0xDC, 0x64),
 415         _INIT_DCS_CMD(0xDD, 0x64),
 416         _INIT_DCS_CMD(0xDE, 0x4F),
 417         _INIT_DCS_CMD(0xDF, 0x4F),
 418         _INIT_DCS_CMD(0xE0, 0x40),
 419         _INIT_DCS_CMD(0xE1, 0x40),
 420         _INIT_DCS_CMD(0xE2, 0x66),
 421         _INIT_DCS_CMD(0xE3, 0x66),
 422         _INIT_DCS_CMD(0xE4, 0x4F),
 423         _INIT_DCS_CMD(0xE5, 0x4F),
 424         _INIT_DCS_CMD(0xE6, 0x41),
 425         _INIT_DCS_CMD(0xE7, 0x41),
 426         _INIT_DELAY_CMD(150),
 427         {},
 428 };
 429
 430 static inline struct boe_panel *to_boe_panel(struct drm_panel *panel)
 431 {
 432         return container_of(panel, struct boe_panel, base);
 433 }
 434
 435 static int boe_panel_init_dcs_cmd(struct boe_panel *boe)
 436 {
 437         struct mipi_dsi_device *dsi = boe->dsi;
 438         struct drm_panel *panel = &boe->base;
 439         int i, err = 0;
 440
 441         if (boe->desc->init_cmds) {
 442                 const struct panel_init_cmd *init_cmds = boe->desc->init_cmds;
 443
 444                 for (i = 0; init_cmds[i].len != 0; i++) {
 445                         const struct panel_init_cmd *cmd = &init_cmds[i];
 446
 447                         switch (cmd->type) {
 448                         case DELAY_CMD:
 449                                 msleep(cmd->data[0]);
 450                                 err = 0;
 451                                 break;
 452
 453                         case INIT_DCS_CMD:
 454                                 err = mipi_dsi_dcs_write(dsi, cmd->data[0],
 455                                                          cmd->len <= 1 ? NULL :
 456                                                          &cmd->data[1],
 457                                                          cmd->len - 1);
 458                                 break;
 459
 460                         default:
 461                                 err = -EINVAL;
 462                         }
 463
 464                         if (err < 0) {
 465                                 dev_err(panel->dev,
 466                                         "failed to write command %u\n", i);
 467                                 return err;
 468                         }
 469                 }
 470         }
 471         return 0;
 472 }
 473
 474 static int boe_panel_enter_sleep_mode(struct boe_panel *boe)
 475 {
 476         struct mipi_dsi_device *dsi = boe->dsi;
 477         int ret;
 478
 479         dsi->mode_flags &= ~MIPI_DSI_MODE_LPM;
 480
 481         ret = mipi_dsi_dcs_set_display_off(dsi);
 482         if (ret < 0)
 483                 return ret;
 484
 485         ret = mipi_dsi_dcs_enter_sleep_mode(dsi);
 486         if (ret < 0)
 487                 return ret;
 488
 489         return 0;
 490 }
 491
 492 static int boe_panel_unprepare(struct drm_panel *panel)
 493 {
 494         struct boe_panel *boe = to_boe_panel(panel);
 495         int ret;
 496
 497         if (!boe->prepared)
 498                 return 0;
 499
 500         ret = boe_panel_enter_sleep_mode(boe);
 501         if (ret < 0) {
 502                 dev_err(panel->dev, "failed to set panel off: %d\n", ret);
 503                 return ret;
 504         }
 505
 506         msleep(150);
 507
 508         if (boe->desc->discharge_on_disable) {
 509                 regulator_disable(boe->avee);
 510                 regulator_disable(boe->avdd);
 511                 usleep_range(5000, 7000);
 512                 gpiod_set_value(boe->enable_gpio, 0);
 513                 usleep_range(5000, 7000);
 514                 regulator_disable(boe->pp1800);
 515                 regulator_disable(boe->pp3300);
 516         } else {
 517                 gpiod_set_value(boe->enable_gpio, 0);
 518                 usleep_range(500, 1000);
 519                 regulator_disable(boe->avee);
 520                 regulator_disable(boe->avdd);
 521                 usleep_range(5000, 7000);
 522                 regulator_disable(boe->pp1800);
 523                 regulator_disable(boe->pp3300);
 524         }
 525
 526         boe->prepared = false;
 527
 528         return 0;
 529 }
 530
 531 static int boe_panel_prepare(struct drm_panel *panel)
 532 {
 533         struct boe_panel *boe = to_boe_panel(panel);
 534         int ret;
 535
 536         if (boe->prepared)
 537                 return 0;
 538
 539         gpiod_set_value(boe->enable_gpio, 0);
 540         usleep_range(1000, 1500);
 541
 542         ret = regulator_enable(boe->pp3300);
 543         if (ret < 0)
 544                 return ret;
 545
 546         ret = regulator_enable(boe->pp1800);
 547         if (ret < 0)
 548                 return ret;
 549
 550         usleep_range(3000, 5000);
 551
 552         ret = regulator_enable(boe->avdd);
 553         if (ret < 0)
 554                 goto poweroff1v8;
 555         ret = regulator_enable(boe->avee);
 556         if (ret < 0)
 557                 goto poweroffavdd;
 558
 559         usleep_range(5000, 10000);
 560
 561         gpiod_set_value(boe->enable_gpio, 1);
 562         usleep_range(1000, 2000);
 563         gpiod_set_value(boe->enable_gpio, 0);
 564         usleep_range(1000, 2000);
 565         gpiod_set_value(boe->enable_gpio, 1);
 566         usleep_range(6000, 10000);
 567
 568         ret = boe_panel_init_dcs_cmd(boe);
 569         if (ret < 0) {
 570                 dev_err(panel->dev, "failed to init panel: %d\n", ret);
 571                 goto poweroff;
 572         }
 573
 574         boe->prepared = true;
 575
 576         return 0;
 577
 578 poweroff:
 579         regulator_disable(boe->avee);
 580 poweroffavdd:
 581         regulator_disable(boe->avdd);
 582 poweroff1v8:
 583         usleep_range(5000, 7000);
 584         regulator_disable(boe->pp1800);
 585         gpiod_set_value(boe->enable_gpio, 0);
 586
 587         return ret;
 588 }
 589
 590 static int boe_panel_enable(struct drm_panel *panel)
 591 {
 592         msleep(130);
 593         return 0;
 594 }
 595
 596 static const struct drm_display_mode boe_tv101wum_nl6_default_mode = {
 597         .clock = 159425,
 598         .hdisplay = 1200,
 599         .hsync_start = 1200 + 100,
 600         .hsync_end = 1200 + 100 + 40,
 601         .htotal = 1200 + 100 + 40 + 24,
 602         .vdisplay = 1920,
 603         .vsync_start = 1920 + 10,
 604         .vsync_end = 1920 + 10 + 14,
 605         .vtotal = 1920 + 10 + 14 + 4,
 606 };
 607
 608 static const struct panel_desc boe_tv101wum_nl6_desc = {
 609         .modes = &boe_tv101wum_nl6_default_mode,
 610         .bpc = 8,
 611         .size = {
 612                 .width_mm = 135,
 613                 .height_mm = 216,
 614         },
 615         .lanes = 4,
 616         .format = MIPI_DSI_FMT_RGB888,
 617         .mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
 618                       MIPI_DSI_MODE_LPM,
 619         .init_cmds = boe_init_cmd,
 620         .discharge_on_disable = false,
 621 };
 622
 623 static const struct drm_display_mode auo_kd101n80_45na_default_mode = {
 624         .clock = 157000,
 625         .hdisplay = 1200,
 626         .hsync_start = 1200 + 60,
 627         .hsync_end = 1200 + 60 + 24,
 628         .htotal = 1200 + 60 + 24 + 56,
 629         .vdisplay = 1920,
 630         .vsync_start = 1920 + 16,
 631         .vsync_end = 1920 + 16 + 4,
 632         .vtotal = 1920 + 16 + 4 + 16,
 633 };
 634
 635 static const struct panel_desc auo_kd101n80_45na_desc = {
 636         .modes = &auo_kd101n80_45na_default_mode,
 637         .bpc = 8,
 638         .size = {
 639                 .width_mm = 135,
 640                 .height_mm = 216,
 641         },
 642         .lanes = 4,
 643         .format = MIPI_DSI_FMT_RGB888,
 644         .mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
 645                       MIPI_DSI_MODE_LPM,
 646         .init_cmds = auo_kd101n80_45na_init_cmd,
 647         .discharge_on_disable = true,
 648 };
 649
 650 static const struct drm_display_mode boe_tv101wum_n53_default_mode = {
 651         .clock = 159916,
 652         .hdisplay = 1200,
 653         .hsync_start = 1200 + 80,
 654         .hsync_end = 1200 + 80 + 24,
 655         .htotal = 1200 + 80 + 24 + 60,
 656         .vdisplay = 1920,
 657         .vsync_start = 1920 + 20,
 658         .vsync_end = 1920 + 20 + 4,
 659         .vtotal = 1920 + 20 + 4 + 10,
 660         .type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,
 661 };
 662
 663 static const struct panel_desc boe_tv101wum_n53_desc = {
 664         .modes = &boe_tv101wum_n53_default_mode,
 665         .bpc = 8,
 666         .size = {
 667                 .width_mm = 135,
 668                 .height_mm = 216,
 669         },
 670         .lanes = 4,
 671         .format = MIPI_DSI_FMT_RGB888,
 672         .mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
 673                       MIPI_DSI_MODE_LPM,
 674         .init_cmds = boe_init_cmd,
 675 };
 676
 677 static const struct drm_display_mode auo_b101uan08_3_default_mode = {
 678         .clock = 159667,
 679         .hdisplay = 1200,
 680         .hsync_start = 1200 + 60,
 681         .hsync_end = 1200 + 60 + 4,
 682         .htotal = 1200 + 60 + 4 + 80,
 683         .vdisplay = 1920,
 684         .vsync_start = 1920 + 34,
 685         .vsync_end = 1920 + 34 + 2,
 686         .vtotal = 1920 + 34 + 2 + 24,
 687         .type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,
 688 };
 689
 690 static const struct panel_desc auo_b101uan08_3_desc = {
 691         .modes = &auo_b101uan08_3_default_mode,
 692         .bpc = 8,
 693         .size = {
 694                 .width_mm = 135,
 695                 .height_mm = 216,
 696         },
 697         .lanes = 4,
 698         .format = MIPI_DSI_FMT_RGB888,
 699         .mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
 700                       MIPI_DSI_MODE_LPM,
 701         .init_cmds = auo_b101uan08_3_init_cmd,
 702 };
 703
 704 static const struct drm_display_mode boe_tv105wum_nw0_default_mode = {
 705         .clock = 159916,
 706         .hdisplay = 1200,
 707         .hsync_start = 1200 + 80,
 708         .hsync_end = 1200 + 80 + 24,
 709         .htotal = 1200 + 80 + 24 + 60,
 710         .vdisplay = 1920,
 711         .vsync_start = 1920 + 20,
 712         .vsync_end = 1920 + 20 + 4,
 713         .vtotal = 1920 + 20 + 4 + 10,
 714         .type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,
 715 };
 716
 717 static const struct panel_desc boe_tv105wum_nw0_desc = {
 718         .modes = &boe_tv105wum_nw0_default_mode,
 719         .bpc = 8,
 720         .size = {
 721                 .width_mm = 141,
 722                 .height_mm = 226,
 723         },
 724         .lanes = 4,
 725         .format = MIPI_DSI_FMT_RGB888,
 726         .mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
 727                       MIPI_DSI_MODE_LPM,
 728         .init_cmds = boe_init_cmd,
 729 };
 730
 731 static int boe_panel_get_modes(struct drm_panel *panel,
 732                                struct drm_connector *connector)
 733 {
 734         struct boe_panel *boe = to_boe_panel(panel);
 735         const struct drm_display_mode *m = boe->desc->modes;
 736         struct drm_display_mode *mode;
 737
 738         mode = drm_mode_duplicate(connector->dev, m);
 739         if (!mode) {
 740                 dev_err(panel->dev, "failed to add mode %ux%u@%u\n",
 741                         m->hdisplay, m->vdisplay, drm_mode_vrefresh(m));
 742                 return -ENOMEM;
 743         }
 744
 745         mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
 746         drm_mode_set_name(mode);
 747         drm_mode_probed_add(connector, mode);
 748
 749         connector->display_info.width_mm = boe->desc->size.width_mm;
 750         connector->display_info.height_mm = boe->desc->size.height_mm;
 751         connector->display_info.bpc = boe->desc->bpc;
 752         drm_connector_set_panel_orientation(connector, boe->orientation);
 753
 754         return 1;
 755 }
 756
 757 static const struct drm_panel_funcs boe_panel_funcs = {
 758         .unprepare = boe_panel_unprepare,
 759         .prepare = boe_panel_prepare,
 760         .enable = boe_panel_enable,
 761         .get_modes = boe_panel_get_modes,
 762 };
 763
 764 static int boe_panel_add(struct boe_panel *boe)
 765 {
 766         struct device *dev = &boe->dsi->dev;
 767         int err;
 768
 769         boe->avdd = devm_regulator_get(dev, "avdd");
 770         if (IS_ERR(boe->avdd))
 771                 return PTR_ERR(boe->avdd);
 772
 773         boe->avee = devm_regulator_get(dev, "avee");
 774         if (IS_ERR(boe->avee))
 775                 return PTR_ERR(boe->avee);
 776
 777         boe->pp3300 = devm_regulator_get(dev, "pp3300");
 778         if (IS_ERR(boe->pp3300))
 779                 return PTR_ERR(boe->pp3300);
 780
 781         boe->pp1800 = devm_regulator_get(dev, "pp1800");
 782         if (IS_ERR(boe->pp1800))
 783                 return PTR_ERR(boe->pp1800);
 784
 785         boe->enable_gpio = devm_gpiod_get(dev, "enable", GPIOD_OUT_LOW);
 786         if (IS_ERR(boe->enable_gpio)) {
 787                 dev_err(dev, "cannot get reset-gpios %ld\n",
 788                         PTR_ERR(boe->enable_gpio));
 789                 return PTR_ERR(boe->enable_gpio);
 790         }
 791
 792         gpiod_set_value(boe->enable_gpio, 0);
 793
 794         drm_panel_init(&boe->base, dev, &boe_panel_funcs,
 795                        DRM_MODE_CONNECTOR_DSI);
 796         err = of_drm_get_panel_orientation(dev->of_node, &boe->orientation);
 797         if (err < 0) {
 798                 dev_err(dev, "%pOF: failed to get orientation %d\n", dev->of_node, err);
 799                 return err;
 800         }
 801
 802         err = drm_panel_of_backlight(&boe->base);
 803         if (err)
 804                 return err;
 805
 806         boe->base.funcs = &boe_panel_funcs;
 807         boe->base.dev = &boe->dsi->dev;
 808
 809         drm_panel_add(&boe->base);
 810
 811         return 0;
 812 }
 813
 814 static int boe_panel_probe(struct mipi_dsi_device *dsi)
 815 {
 816         struct boe_panel *boe;
 817         int ret;
 818         const struct panel_desc *desc;
 819
 820         boe = devm_kzalloc(&dsi->dev, sizeof(*boe), GFP_KERNEL);
 821         if (!boe)
 822                 return -ENOMEM;
 823
 824         desc = of_device_get_match_data(&dsi->dev);
 825         dsi->lanes = desc->lanes;
 826         dsi->format = desc->format;
 827         dsi->mode_flags = desc->mode_flags;
 828         boe->desc = desc;
 829         boe->dsi = dsi;
 830         ret = boe_panel_add(boe);
 831         if (ret < 0)
 832                 return ret;
 833
 834         mipi_dsi_set_drvdata(dsi, boe);
 835
 836         ret = mipi_dsi_attach(dsi);
 837         if (ret)
 838                 drm_panel_remove(&boe->base);
 839
 840         return ret;
 841 }
 842
 843 static void boe_panel_shutdown(struct mipi_dsi_device *dsi)
 844 {
 845         struct boe_panel *boe = mipi_dsi_get_drvdata(dsi);
 846
 847         drm_panel_disable(&boe->base);
 848         drm_panel_unprepare(&boe->base);
 849 }
 850
 851 static int boe_panel_remove(struct mipi_dsi_device *dsi)
 852 {
 853         struct boe_panel *boe = mipi_dsi_get_drvdata(dsi);
 854         int ret;
 855
 856         boe_panel_shutdown(dsi);
 857
 858         ret = mipi_dsi_detach(dsi);
 859         if (ret < 0)
 860                 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", ret);
 861
 862         if (boe->base.dev)
 863                 drm_panel_remove(&boe->base);
 864
 865         return 0;
 866 }
 867
 868 static const struct of_device_id boe_of_match[] = {
 869         { .compatible = "boe,tv101wum-nl6",
 870           .data = &boe_tv101wum_nl6_desc
 871         },
 872         { .compatible = "auo,kd101n80-45na",
 873           .data = &auo_kd101n80_45na_desc
 874         },
 875         { .compatible = "boe,tv101wum-n53",
 876           .data = &boe_tv101wum_n53_desc
 877         },
 878         { .compatible = "auo,b101uan08.3",
 879           .data = &auo_b101uan08_3_desc
 880         },
 881         { .compatible = "boe,tv105wum-nw0",
 882           .data = &boe_tv105wum_nw0_desc
 883         },
 884         { /* sentinel */ }
 885 };
 886 MODULE_DEVICE_TABLE(of, boe_of_match);
 887
 888 static struct mipi_dsi_driver boe_panel_driver = {
 889         .driver = {
 890                 .name = "panel-boe-tv101wum-nl6",
 891                 .of_match_table = boe_of_match,
 892         },
 893         .probe = boe_panel_probe,
 894         .remove = boe_panel_remove,
 895         .shutdown = boe_panel_shutdown,
 896 };
 897 module_mipi_dsi_driver(boe_panel_driver);
 898
 899 MODULE_AUTHOR("Jitao Shi <jitao.shi@mediatek.com>");
 900 MODULE_DESCRIPTION("BOE tv101wum-nl6 1200x1920 video mode panel driver");
 901 MODULE_LICENSE("GPL v2");